sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget6/translations/zh_CN/gpu/amdgpu/display/display-managermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/zh_TW/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/it_IT/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ja_JP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ko_KR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/sp_SP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDgpu Display Managerh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]refidid1uh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager.rsthKubhtopic)}(hTable of Contents h](h)}(hTable of Contentsh]hTable of Contents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh bullet_list)}(hhh]h list_item)}(hhh](h paragraph)}(hhh]h reference)}(hhh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]hah ]h"]h$]h&]refidamdgpu-display-manageruh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]h Lifecycle}(hhhhhNhNubah}(h]id2ah ]h"]h$]h&]refid lifecycleuh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh]h)}(hhh]h)}(hhh]h Interrupts}(hjhhhNhNubah}(h]id3ah ]h"]h$]h&]refid interruptsuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh]h)}(hhh]h)}(hhh]hAtomic Implementation}(hj@hhhNhNubah}(h]id4ah ]h"]h$]h&]refidatomic-implementationuh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhj:ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]hColor Management Properties}(hjbhhhNhNubah}(h]id5ah ]h"]h$]h&]refidcolor-management-propertiesuh1hhj_ubah}(h]h ]h"]h$]h&]uh1hhj\ubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]hdrm_crtc Properties}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]refiddrm-crtc-propertiesuh1hhj~ubah}(h]h ]h"]h$]h&]uh1hhj{ubah}(h]h ]h"]h$]h&]uh1hhjxubh)}(hhh]h)}(hhh]h)}(hhh]h)AMD Private Color Management on drm_plane}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]refid)amd-private-color-management-on-drm-planeuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjxubh)}(hhh]h)}(hhh]h)}(hhh]hAMD plane color pipeline}(hjhhhNhNubah}(h]id8ah ]h"]h$]h&]refidamd-plane-color-pipelineuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjxubh)}(hhh]h)}(hhh]h)}(hhh]h-DC Color Capabilities between DCN generations}(hjhhhNhNubah}(h]id9ah ]h"]h$]h&]refid-dc-color-capabilities-between-dcn-generationsuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjxubeh}(h]h ]h"]h$]h&]uh1hhj\ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]hBlend Mode Properties}(hjhhhNhNubah}(h]id10ah ]h"]h$]h&]refidblend-mode-propertiesuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]hBlend configuration flow}(hj4hhhNhNubah}(h]id11ah ]h"]h$]h&]refidblend-configuration-flowuh1hhj1ubah}(h]h ]h"]h$]h&]uh1hhj.ubah}(h]h ]h"]h$]h&]uh1hhj+ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]table-of-contentsah ]contentsah"]table of contentsah$]h&]uh1hhhhKhhhhubh)}(hThe AMDgpu display manager, **amdgpu_dm** (or even simpler, **dm**) sits between DRM and DC. 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struct)c.dm_compressor_infohNtauh1jhhhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhNubhdesc)}(hhh](hdesc_signature)}(hdm_compressor_infoh]hdesc_signature_line)}(hstruct dm_compressor_infoh](hdesc_sig_keyword)}(hstructh]hstruct}(hj hhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hdm_compressor_infoh]h desc_sig_name)}(hjh]hdm_compressor_info}(hj2hhhNhNubah}(h]h ]nah"]h$]h&]uh1j0hj,ubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1j*hjhhhjhKubeh}(h]h ]h"]h$]h&]jHjI add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(h,Buffer info used by frame buffer compressionh]h,Buffer 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``bo_ptr``h]j)}(hjh]hbo_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhjubj)}(hhh]h)}(hPointer to the buffer objecth]hPointer to the buffer object}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKhhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hKhhjubj)}(h``gpu_addr`` MMIO gpu addrh](j)}(h ``gpu_addr``h]j)}(hjTh]hgpu_addr}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhjNubj)}(hhh]h)}(h MMIO gpu addrh]h MMIO gpu addr}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKihjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihKhhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdmub_hpd_work (C struct)c.dmub_hpd_workhNtauh1jhhhhhjhNubj)}(hhh](j)}(h dmub_hpd_workh]j)}(hstruct dmub_hpd_workh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKoubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjhKoubj+)}(h dmub_hpd_workh]j1)}(hjh]h dmub_hpd_work}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjhKoubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjhKoubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjhKohjhhubj_)}(hhh]h)}(h5Handle time consuming work in low priority outbox IRQh]h5Handle time consuming work in low priority outbox IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKshjhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjhKoubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhhhjhNubj)}(hXc**Definition**:: struct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; }; **Members** ``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq ``dmub_notify`` notification for callback function ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKwhj ubj)}(hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };h]hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };}hj-sbah}(h]h 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work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };h]hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hjh]hdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj&hKhjubj)}(h@``acrtc`` amdgpu CRTC instance for which the event has occurred h](j)}(h ``acrtc``h]j)}(hjJh]hacrtc}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjDubj)}(hhh]h)}(h5amdgpu CRTC instance for which the event has occurredh]h5amdgpu CRTC instance for which the event has occurred}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhj_hKhjubj)}(h6``stream`` DC stream for which the event has occurred h](j)}(h ``stream``h]j)}(hjh]hstream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj}ubj)}(hhh]h)}(h*DC stream for which the event has occurredh]h*DC stream for which the event has occurred}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h"``enable`` true if enabling vblankh](j)}(h ``enable``h]j)}(hjh]henable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(htrue if enabling vblankh]htrue if enabling vblank}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jidle_workqueue (C struct)c.idle_workqueuehNtauh1jhhhhhjhNubj)}(hhh](j)}(hidle_workqueueh]j)}(hstruct idle_workqueueh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj$hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhj#hKubj+)}(hidle_workqueueh]j1)}(hjh]hidle_workqueue}(hj6hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj2ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhj#hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhj#hKubah}(h]j ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj#hKhj hhubj_)}(hhh]h)}(h%Work data for periodic action in idleh]h%Work data for periodic action in idle}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjUhhubah}(h]h ]h"]h$]h&]uh1j^hj hhhj#hKubeh}(h]h ](jstructeh"]h$]h&]jjjjpjjpjjjuh1jhhhhhjhNubj)}(hX_**Definition**:: struct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``enable`` true if idle worker is enabled ``running`` true if idle worker is runningh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubh:}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjtubj)}(hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };h]hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjtubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjtubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hjh]hdm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(h*``enable`` true if idle worker is enabled h](j)}(h ``enable``h]j)}(hj7 h]henable}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5 ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj1 ubj)}(hhh]h)}(htrue if idle worker is enabledh]htrue if idle worker is enabled}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL hKhjM ubah}(h]h ]h"]h$]h&]uh1jhj1 ubeh}(h]h ]h"]h$]h&]uh1jhjL hKhjubj)}(h*``running`` true if idle worker is runningh](j)}(h ``running``h]j)}(hjp h]hrunning}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjj ubj)}(hhh]h)}(htrue if idle worker is runningh]htrue if idle worker is running}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhjj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubeh}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jvupdate_offload_work (C struct)c.vupdate_offload_workhNtauh1jhhhhhjhNubj)}(hhh](j)}(hvupdate_offload_workh]j)}(hstruct vupdate_offload_workh](j)}(hj h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj hhhj hKubj+)}(hvupdate_offload_workh]j1)}(hj h]hvupdate_offload_work}(hj hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj hhhj hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj hhhj hKubah}(h]j ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj hKhj hhubj_)}(hhh]h)}(h2Work data for offloading task from vupdate handlerh]h2Work data for offloading task from vupdate handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1j^hj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj$ jj$ jjjuh1jhhhhhjhNubj)}(hX**Definition**:: struct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; }; **Members** ``work`` Kernel work data for the work event ``adev`` amdgpu_device back pointer ``stream`` DC stream associated with the crtc ``adjust`` DC CRTC timing adjust to be applied to the crtch](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj, ubh:}(hj, hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj( ubj)}(hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };h]hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };}hjI sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj( ubh)}(h **Members**h]j)}(hjZ h]hMembers}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj( ubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjy h]hwork}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjs ubj)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjs ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjp ubj)}(h$``adev`` amdgpu_device back pointer h](j)}(h``adev``h]j)}(hj h]hadev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(hamdgpu_device back pointerh]hamdgpu_device back pointer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjp ubj)}(h.``stream`` DC stream associated with the crtc h](j)}(h ``stream``h]j)}(hj h]hstream}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h"DC stream associated with the crtch]h"DC stream associated with the crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjp ubj)}(h:``adjust`` DC CRTC timing adjust to be applied to the crtch](j)}(h ``adjust``h]j)}(hj$ h]hadjust}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h/DC CRTC timing adjust to be applied to the crtch]h/DC CRTC timing adjust to be applied to the crtc}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj: ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj9 hKhjp ubeh}(h]h ]h"]h$]h&]uh1jhj( ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_luminance_data (C struct)c.amdgpu_dm_luminance_datahNtauh1jhhhhhjhNubj)}(hhh](j)}(hamdgpu_dm_luminance_datah]j)}(hstruct amdgpu_dm_luminance_datah](j)}(hj h]hstruct}(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjz hhhj hKubj+)}(hamdgpu_dm_luminance_datah]j1)}(hjx h]hamdgpu_dm_luminance_data}(hj hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjz hhhj hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjv hhhj hKubah}(h]jq ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj hKhjs hhubj_)}(hhh]h)}(hCustom luminance datah]hCustom luminance data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1j^hjs hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jhhhhhjhNubj)}(h**Definition**:: struct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; }; **Members** ``luminance`` Luminance in percent ``input_signal`` Input signal in range 0-255h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };h]hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };}hj sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j)}(h#``luminance`` Luminance in percent h](j)}(h ``luminance``h]j)}(hj- h]h luminance}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj' ubj)}(hhh]h)}(hLuminance in percenth]hLuminance in percent}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjB hKhjC ubah}(h]h ]h"]h$]h&]uh1jhj' ubeh}(h]h ]h"]h$]h&]uh1jhjB hKhj$ ubj)}(h,``input_signal`` Input signal in range 0-255h](j)}(h``input_signal``h]j)}(hjf h]h input_signal}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj` ubj)}(hhh]h)}(hInput signal in range 0-255h]hInput signal in range 0-255}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj| ubah}(h]h ]h"]h$]h&]uh1jhj` ubeh}(h]h ]h"]h$]h&]uh1jhj{ hKhj$ ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_backlight_caps (C struct)c.amdgpu_dm_backlight_capshNtauh1jhhhhhjhNubj)}(hhh](j)}(hamdgpu_dm_backlight_capsh]j)}(hstruct amdgpu_dm_backlight_capsh](j)}(hj h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj hhhj hKubj+)}(hamdgpu_dm_backlight_capsh]j1)}(hj h]hamdgpu_dm_backlight_caps}(hj hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj hhhj hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj hhhj hKubah}(h]j ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj hKhj hhubj_)}(hhh]h)}(hInformation about backlighth]hInformation about backlight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1j^hj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jhhhhhjhNubj)}(hX,**Definition**:: struct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; **Members** ``ext_caps`` Keep the data struct with all the information about the display support for HDR. ``aux_min_input_signal`` Min brightness value supported by the display ``aux_max_input_signal`` Max brightness value supported by the display in nits. ``min_input_signal`` minimum possible input in range 0-255. ``max_input_signal`` maximum possible input in range 0-255. ``caps_valid`` true if these values are from the ACPI interface. ``aux_support`` Describes if the display supports AUX backlight. ``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. ``ac_level`` the default brightness if booted on AC ``dc_level`` the default brightness if booted on DC ``data_points`` the number of custom luminance data points ``luminance_data`` custom luminance datah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubh:}(hj" hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };h]hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };}hj? sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hjP h]hMembers}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j)}(h^``ext_caps`` Keep the data struct with all the information about the display support for HDR. h](j)}(h ``ext_caps``h]j)}(hjo h]hext_caps}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhji ubj)}(hhh]h)}(hPKeep the data struct with all the information about the display support for HDR.h]hPKeep the data struct with all the information about the display support for HDR.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhji ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjf ubj)}(hG``aux_min_input_signal`` Min brightness value supported by the display h](j)}(h``aux_min_input_signal``h]j)}(hj h]haux_min_input_signal}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h-Min brightness value supported by the displayh]h-Min brightness value supported by the display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjf ubj)}(hP``aux_max_input_signal`` Max brightness value supported by the display in nits. h](j)}(h``aux_max_input_signal``h]j)}(hj h]haux_max_input_signal}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h6Max brightness value supported by the display in nits.h]h6Max brightness value supported by the display in nits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjf ubj)}(h<``min_input_signal`` minimum possible input in range 0-255. h](j)}(h``min_input_signal``h]j)}(hjh]hmin_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h&minimum possible input in range 0-255.h]h&minimum possible input in range 0-255.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hKhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hKhjf ubj)}(h<``max_input_signal`` maximum possible input in range 0-255. h](j)}(h``max_input_signal``h]j)}(hjUh]hmax_input_signal}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjOubj)}(hhh]h)}(h&maximum possible input in range 0-255.h]h&maximum possible input in range 0-255.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKhjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhKhjf ubj)}(hA``caps_valid`` true if these values are from the ACPI interface. h](j)}(h``caps_valid``h]j)}(hjh]h caps_valid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h1true if these values are from the ACPI interface.h]h1true if these values are from the ACPI interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubj)}(hA``aux_support`` Describes if the display supports AUX backlight. h](j)}(h``aux_support``h]j)}(hjh]h aux_support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h0Describes if the display supports AUX backlight.h]h0Describes if the display supports AUX backlight.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubj)}(h``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. h](j)}(h``brightness_mask``h]j)}(hjh]hbrightness_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.h]hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubj)}(h4``ac_level`` the default brightness if booted on AC h](j)}(h ``ac_level``h]j)}(hj:h]hac_level}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj4ubj)}(hhh]h)}(h&the default brightness if booted on ACh]h&the default brightness if booted on AC}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhKhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhKhjf ubj)}(h4``dc_level`` the default brightness if booted on DC h](j)}(h ``dc_level``h]j)}(hjsh]hdc_level}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjmubj)}(hhh]h)}(h&the default brightness if booted on DCh]h&the default brightness if booted on DC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubj)}(h;``data_points`` the number of custom luminance data points h](j)}(h``data_points``h]j)}(hjh]h data_points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h*the number of custom luminance data pointsh]h*the number of custom luminance data points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubj)}(h(``luminance_data`` custom luminance datah](j)}(h``luminance_data``h]j)}(hjh]hluminance_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hcustom luminance datah]hcustom luminance data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjf ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubh)}(h**Description**h]j)}(hj(h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubh)}(h3Describe the backlight support for ACPI or eDP AUX.h]h3Describe the backlight support for ACPI or eDP AUX.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdal_allocation (C struct)c.dal_allocationhNtauh1jhhhhhjhNubj)}(hhh](j)}(hdal_allocationh]j)}(hstruct dal_allocationh](j)}(hj h]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hjthhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjbhhhjshKubj+)}(hdal_allocationh]j1)}(hj`h]hdal_allocation}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjbhhhjshKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj^hhhjshKubah}(h]jYah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjshKhj[hhubj_)}(hhh]h)}(h-Tracks mapped FB memory for SMU communicationh]h-Tracks mapped FB memory for SMU communication}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j^hj[hhhjshKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhhhjhNubj)}(hXX**Definition**:: struct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; }; **Members** ``list`` list of dal allocations ``bo`` GPU buffer object ``cpu_ptr`` CPU virtual address of the GPU buffer object ``gpu_addr`` GPU virtual address of the GPU buffer objecth](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };h]htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](j)}(h!``list`` list of dal allocations h](j)}(h``list``h]j)}(hjh]hlist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hlist of dal allocationsh]hlist of dal allocations}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hKhj ubj)}(h``bo`` GPU buffer object h](j)}(h``bo``h]j)}(hjNh]hbo}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjHubj)}(hhh]h)}(hGPU buffer objecth]hGPU buffer object}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchKhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjchKhj ubj)}(h9``cpu_ptr`` CPU virtual address of the GPU buffer object h](j)}(h ``cpu_ptr``h]j)}(hjh]hcpu_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h,CPU virtual address of the GPU buffer objecth]h,CPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h9``gpu_addr`` GPU virtual address of the GPU buffer objecth](j)}(h ``gpu_addr``h]j)}(hjh]hgpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h,GPU virtual address of the GPU buffer objecth]h,GPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(hpd_rx_irq_offload_work_queue (C struct)c.hpd_rx_irq_offload_work_queuehNtauh1jhhhhhjhNubj)}(hhh](j)}(hhpd_rx_irq_offload_work_queueh]j)}(h$struct hpd_rx_irq_offload_work_queueh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj(hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhj'hKubj+)}(hhpd_rx_irq_offload_work_queueh]j1)}(hjh]hhpd_rx_irq_offload_work_queue}(hj:hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj6ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhj'hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhj'hKubah}(h]j ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj'hKhjhhubj_)}(hhh]h)}(h,Work queue to handle hpd_rx_irq offload workh]h,Work queue to handle hpd_rx_irq offload work}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjYhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhj'hKubeh}(h]h ](jstructeh"]h$]h&]jjjjtjjtjjjuh1jhhhhhjhNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; }; **Members** ``wq`` workqueue structure to queue offload work. ``offload_lock`` To protect fields of offload work queue. ``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss ``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event ``aconnector`` The aconnector that this work queue is attached toh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh:}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjxubj)}(hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };h]hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h)hMhjxubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjxubj)}(hhh](j)}(h2``wq`` workqueue structure to queue offload work. h](j)}(h``wq``h]j)}(hjh]hwq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h*workqueue structure to queue offload work.h]h*workqueue structure to queue offload work.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``offload_lock`` To protect fields of offload work queue. h](j)}(h``offload_lock``h]j)}(hjh]h offload_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjubj)}(hhh]h)}(h(To protect fields of offload work queue.h]h(To protect fields of offload work queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hb``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss h](j)}(h``is_handling_link_loss``h]j)}(hj;h]his_handling_link_loss}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj5ubj)}(hhh]h)}(hGUsed to prevent inserting link loss event when we're handling link lossh]hIUsed to prevent inserting link loss event when we’re handling link loss}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjubj)}(h``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event h](j)}(h!``is_handling_mst_msg_rdy_event``h]j)}(hjuh]his_handling_mst_msg_rdy_event}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjoubj)}(hhh]h)}(heUsed to prevent inserting mst message ready event when we're already handling mst message ready eventh]hgUsed to prevent inserting mst message ready event when we’re already handling mst message ready event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hA``aconnector`` The aconnector that this work queue is attached toh](j)}(h``aconnector``h]j)}(hjh]h aconnector}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h2The aconnector that this work queue is attached toh]h2The aconnector that this work queue is attached to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"hpd_rx_irq_offload_work (C struct)c.hpd_rx_irq_offload_workhNtauh1jhhhhhjhNubj)}(hhh](j)}(hhpd_rx_irq_offload_workh]j)}(hstruct hpd_rx_irq_offload_workh](j)}(hj h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjhMubj+)}(hhpd_rx_irq_offload_workh]j1)}(hjh]hhpd_rx_irq_offload_work}(hj)hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj%ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjhMubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjhMhjhhubj_)}(hhh]h)}(h!hpd_rx_irq offload work structureh]h!hpd_rx_irq offload work structure}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjHhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjcjjcjjjuh1jhhhhhjhNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; }; **Members** ``work`` offload work ``data`` reference irq data which is used while handling offload work ``offload_wq`` offload work queue that this work is queued to ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubh:}(hjkhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM"hjgubj)}(hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };h]hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM$hjgubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM+hjgubj)}(hhh](j)}(h``work`` offload work h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM#hjubj)}(hhh]h)}(h offload workh]h offload work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM#hjubj)}(hF``data`` reference irq data which is used while handling offload work h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM'hjubj)}(hhh]h)}(h``offload_wq`` offload work queue that this work is queued to h](j)}(h``offload_wq``h]j)}(hj*h]h offload_wq}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM+hj$ubj)}(hhh]h)}(h.offload work queue that this work is queued toh]h.offload work queue that this work is queued to}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hM+hj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hM+hjubj)}(h``adev`` amdgpu_device pointerh](j)}(h``adev``h]j)}(hjch]hadev}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM.hj]ubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM/hjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhM.hjubeh}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!amdgpu_display_manager (C struct)c.amdgpu_display_managerhNtauh1jhhhhhjhNubj)}(hhh](j)}(hamdgpu_display_managerh]j)}(hstruct amdgpu_display_managerh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM5ubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjhM5ubj+)}(hamdgpu_display_managerh]j1)}(hjh]hamdgpu_display_manager}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjhM5ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjhM5ubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjhM5hjhhubj_)}(hhh]h)}(h%Central amdgpu display manager deviceh]h%Central amdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM4hjhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjhM5ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhhhjhNubj)}(hX**Definition**:: struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; }; **Members** ``dc`` Display Core control structure ``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. ``dmub_notify`` Notification from DMUB. ``dmub_callback`` Callback functions to handle notification from DMUB. ``dmub_thread_offload`` Flag to indicate if callback is offload. ``dmub_fb_info`` Framebuffer regions for the DMUB. ``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. ``dmub_bo`` Buffer object for the DMUB. ``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. ``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. ``dmcub_fw_version`` DMCUB firmware version. ``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. ``adev`` AMDGPU base driver structure ``ddev`` DRM base driver structure ``display_indexes_num`` Max number of display streams supported ``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. ``dc_lock`` Guards access to DC functions that can issue register write sequences. ``audio_lock`` Guards access to audio instance changes. ``audio_component`` Used to notify ELD changes to sound driver. ``audio_registered`` True if the audio component has been registered successfully, false otherwise. ``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). ``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. ``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. ``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. ``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. ``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. ``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. ``dmub_outbox_params`` DMUB Outbox parameters ``irq_handler_list_table_lock`` Synchronizes access to IRQ tables ``backlight_dev`` Backlight control device ``backlight_link`` Link on which to control backlight ``num_of_edps`` number of backlight eDPs ``backlight_caps`` Capabilities of the backlight device ``freesync_module`` Module handling freesync calculations ``hdcp_workqueue`` AMDGPU content protection queue ``vblank_control_workqueue`` Deferred work for vblank control events. ``idle_workqueue`` Periodic work for idle events. ``cached_state`` Caches device atomic state for suspend/resume ``cached_dc_state`` Cached state of content streams ``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` ``fw_dmcu`` Reference to DMCU firmware ``dmcu_fw_version`` Version of the DMCU firmware ``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW ``active_vblank_irq_count`` number of currently active vblank irqs ``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. ``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq ``mst_encoders`` fake encoders used for DP MST. ``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. ``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true ``dmcub_trace_event_en`` enable dmcub trace events ``da_list`` DAL fb memory allocation list, for communication with SMU. ``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done ``delayed_hpd_wq`` work queue used to delay DMUB HPD work ``brightness`` cached backlight values. ``actual_brightness`` last successfully applied backlight values. ``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform ``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. ``dpia_aux_lock`` Guards access to DPIA AUX ``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct ``oem_i2c`` OEM i2c bus ``fused_io`` dmub fused io interfaceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM8hjubj)}(hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; };h]hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; };}hj<sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM:hjubh)}(h **Members**h]j)}(hjMh]hMembers}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](j)}(h&``dc`` Display Core control structure h](j)}(h``dc``h]j)}(hjlh]hdc}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM7hjfubj)}(hhh]h)}(hDisplay Core control structureh]hDisplay Core control structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM7hjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjhM7hjcubj)}(h``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. h](j)}(h ``dmub_srv``h]j)}(hjh]hdmub_srv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMYhjubj)}(hhh]h)}(hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.h]hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMYhjcubj)}(h(``dmub_notify`` Notification from DMUB. h](j)}(h``dmub_notify``h]j)}(hjh]h dmub_notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM`hjubj)}(hhh]h)}(hNotification from DMUB.h]hNotification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM`hjcubj)}(hG``dmub_callback`` Callback functions to handle notification from DMUB. h](j)}(h``dmub_callback``h]j)}(hjh]h dmub_callback}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhjubj)}(hhh]h)}(h4Callback functions to handle notification from DMUB.h]h4Callback functions to handle notification from DMUB.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj-hMhhjcubj)}(hA``dmub_thread_offload`` Flag to indicate if callback is offload. h](j)}(h``dmub_thread_offload``h]j)}(hjQh]hdmub_thread_offload}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMphjKubj)}(hhh]h)}(h(Flag to indicate if callback is offload.h]h(Flag to indicate if callback is offload.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMphjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjfhMphjcubj)}(h3``dmub_fb_info`` Framebuffer regions for the DMUB. h](j)}(h``dmub_fb_info``h]j)}(hjh]h dmub_fb_info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMxhjubj)}(hhh]h)}(h!Framebuffer regions for the DMUB.h]h!Framebuffer regions for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMxhjcubj)}(hG``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. h](j)}(h ``dmub_fw``h]j)}(hjh]hdmub_fw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h:DMUB firmware, required on hardware that has DMUB support.h]h:DMUB firmware, required on hardware that has DMUB support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(h(``dmub_bo`` Buffer object for the DMUB. h](j)}(h ``dmub_bo``h]j)}(hjh]hdmub_bo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hBuffer object for the DMUB.h]hBuffer object for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hE``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. h](j)}(h``dmub_bo_gpu_addr``h]j)}(hj5h]hdmub_bo_gpu_addr}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj/ubj)}(hhh]h)}(h/GPU virtual address for the DMUB buffer object.h]h/GPU virtual address for the DMUB buffer object.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhMhjcubj)}(h=``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. h](j)}(h``dmub_bo_cpu_addr``h]j)}(hjnh]hdmub_bo_cpu_addr}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjhubj)}(hhh]h)}(h'CPU address for the DMUB buffer object.h]h'CPU address for the DMUB buffer object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(h-``dmcub_fw_version`` DMCUB firmware version. h](j)}(h``dmcub_fw_version``h]j)}(hjh]hdmcub_fw_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hDMCUB firmware version.h]hDMCUB firmware version.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hf``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. h](j)}(h``cgs_device``h]j)}(hjh]h cgs_device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hVThe Common Graphics Services device. It provides an interface for accessing registers.h]hVThe Common Graphics Services device. It provides an interface for accessing registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(h&``adev`` AMDGPU base driver structure h](j)}(h``adev``h]j)}(hjh]hadev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM8hjubj)}(hhh]h)}(hAMDGPU base driver structureh]hAMDGPU base driver structure}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hM8hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj/hM8hjcubj)}(h#``ddev`` DRM base driver structure h](j)}(h``ddev``h]j)}(hjSh]hddev}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM9hjMubj)}(hhh]h)}(hDRM base driver structureh]hDRM base driver structure}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhM9hjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjhhM9hjcubj)}(h@``display_indexes_num`` Max number of display streams supported h](j)}(h``display_indexes_num``h]j)}(hjh]hdisplay_indexes_num}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM:hjubj)}(hhh]h)}(h'Max number of display streams supportedh]h'Max number of display streams supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM:hjcubj)}(h``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. h](j)}(h``atomic_obj``h]j)}(hjh]h atomic_obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hIn combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`.h](hIn combination with }(hjhhhNhNubh)}(h:c:type:`dm_atomic_state`h]j)}(hjh]hdm_atomic_state}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sbjdm_atomic_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhb it helps manage global atomic state that doesn’t map cleanly into existing drm resources, like }(hjhhhNhNubh)}(h:c:type:`dc_context`h]j)}(hjh]h dc_context}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj dc_contextuh1hhj hMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hS``dc_lock`` Guards access to DC functions that can issue register write sequences. h](j)}(h ``dc_lock``h]j)}(hjMh]hdc_lock}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjGubj)}(hhh]h)}(hFGuards access to DC functions that can issue register write sequences.h]hFGuards access to DC functions that can issue register write sequences.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjbhMhjcubj)}(h8``audio_lock`` Guards access to audio instance changes. h](j)}(h``audio_lock``h]j)}(hjh]h audio_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h(Guards access to audio instance changes.h]h(Guards access to audio instance changes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(h@``audio_component`` Used to notify ELD changes to sound driver. h](j)}(h``audio_component``h]j)}(hjh]haudio_component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h+Used to notify ELD changes to sound driver.h]h+Used to notify ELD changes to sound driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hd``audio_registered`` True if the audio component has been registered successfully, false otherwise. h](j)}(h``audio_registered``h]j)}(hjh]haudio_registered}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hNTrue if the audio component has been registered successfully, false otherwise.h]hNTrue if the audio component has been registered successfully, false otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hX;``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). h](j)}(h``irq_handler_list_low_tab``h]j)}(hj3h]hirq_handler_list_low_tab}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj-ubj)}(hhh](h)}(hLow priority IRQ handler table.h]hLow priority IRQ handler table.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjIubh)}(hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.h]hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjIubh)}(hONote that handlers are called in the same order as they were registered (FIFO).h]hONote that handlers are called in the same order as they were registered (FIFO).}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjIubeh}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjcubj)}(h``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. h](j)}(h``irq_handler_list_high_tab``h]j)}(hjh]hirq_handler_list_high_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](h)}(h High priority IRQ handler table.h]h High priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately.h](hIt is a n*m table, same as }(hjhhhNhNubh)}(h":c:type:`irq_handler_list_low_tab`h]j)}(hjh]hirq_handler_list_low_tab}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjirq_handler_list_low_tabuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhN. However, handlers in this table are not deferred and are called immediately.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(hY``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. h](j)}(h``pflip_params``h]j)}(hjh]h pflip_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hGPage flip IRQ parameters, passed to registered handlers when triggered.h]hGPage flip IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjcubj)}(hb``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vblank_params``h]j)}(hj1h]h vblank_params}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj+ubj)}(hhh]h)}(hOVertical blanking IRQ parameters, passed to registered handlers when triggered.h]hOVertical blanking IRQ parameters, passed to registered handlers when triggered.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhMhjcubj)}(hh``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vline0_params``h]j)}(hjkh]h vline0_params}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjeubj)}(hhh]h)}(hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.h]hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(ha``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vupdate_params``h]j)}(hjh]hvupdate_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjubj)}(hhh]h)}(hMVertical update IRQ parameters, passed to registered handlers when triggered.h]hMVertical update IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjcubj)}(he``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. h](j)}(h``dmub_trace_params``h]j)}(hjh]hdmub_trace_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.h]hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjcubj)}(h.``dmub_outbox_params`` DMUB Outbox parameters h](j)}(h``dmub_outbox_params``h]j)}(hjh]hdmub_outbox_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMJhjubj)}(hhh]h)}(hDMUB Outbox parametersh]hDMUB Outbox parameters}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMJhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj.hMJhjcubj)}(hB``irq_handler_list_table_lock`` Synchronizes access to IRQ tables h](j)}(h``irq_handler_list_table_lock``h]j)}(hjRh]hirq_handler_list_table_lock}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM;hjLubj)}(hhh]h)}(h!Synchronizes access to IRQ tablesh]h!Synchronizes access to IRQ tables}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghM;hjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhjghM;hjcubj)}(h+``backlight_dev`` Backlight control device h](j)}(h``backlight_dev``h]j)}(hjh]h backlight_dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM<hjubj)}(hhh]h)}(hBacklight control deviceh]hBacklight control device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM<hjcubj)}(h6``backlight_link`` Link on which to control backlight h](j)}(h``backlight_link``h]j)}(hjh]hbacklight_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM=hjubj)}(hhh]h)}(h"Link on which to control backlighth]h"Link on which to control backlight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM=hjcubj)}(h)``num_of_edps`` number of backlight eDPs h](j)}(h``num_of_edps``h]j)}(hjh]h num_of_edps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMKhjubj)}(hhh]h)}(hnumber of backlight eDPsh]hnumber of backlight eDPs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMKhjcubj)}(h8``backlight_caps`` Capabilities of the backlight device h](j)}(h``backlight_caps``h]j)}(hj6h]hbacklight_caps}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM>hj0ubj)}(hhh]h)}(h$Capabilities of the backlight deviceh]h$Capabilities of the backlight device}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM>hjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhM>hjcubj)}(h:``freesync_module`` Module handling freesync calculations h](j)}(h``freesync_module``h]j)}(hjoh]hfreesync_module}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM?hjiubj)}(hhh]h)}(h%Module handling freesync calculationsh]h%Module handling freesync calculations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM?hjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjhM?hjcubj)}(h3``hdcp_workqueue`` AMDGPU content protection queue h](j)}(h``hdcp_workqueue``h]j)}(hjh]hhdcp_workqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM@hjubj)}(hhh]h)}(hAMDGPU content protection queueh]hAMDGPU content protection queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM@hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM@hjcubj)}(hF``vblank_control_workqueue`` Deferred work for vblank control events. h](j)}(h``vblank_control_workqueue``h]j)}(hjh]hvblank_control_workqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM*hjubj)}(hhh]h)}(h(Deferred work for vblank control events.h]h(Deferred work for vblank control events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM*hjcubj)}(h2``idle_workqueue`` Periodic work for idle events. h](j)}(h``idle_workqueue``h]j)}(hjh]hidle_workqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM1hjubj)}(hhh]h)}(hPeriodic work for idle events.h]hPeriodic work for idle events.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hM1hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj/hM1hjcubj)}(h?``cached_state`` Caches device atomic state for suspend/resume h](j)}(h``cached_state``h]j)}(hjSh]h cached_state}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMDhjMubj)}(hhh]h)}(h-Caches device atomic state for suspend/resumeh]h-Caches device atomic state for suspend/resume}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMDhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjhhMDhjcubj)}(h4``cached_dc_state`` Cached state of content streams h](j)}(h``cached_dc_state``h]j)}(hjh]hcached_dc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMEhjubj)}(hhh]h)}(hCached state of content streamsh]hCached state of content streams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMEhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMEhjcubj)}(hm``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` h](j)}(h``compressor``h]j)}(hjh]h compressor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjubj)}(hhh]h)}(h]Frame buffer compression buffer. See :c:type:`struct dm_compressor_info `h](h%Frame buffer compression buffer. See }(hjhhhNhNubh)}(h8:c:type:`struct dm_compressor_info `h]j)}(hjh]hstruct dm_compressor_info}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdm_compressor_infouh1hhjhMFhjubeh}(h]h ]h"]h$]h&]uh1hhjhMFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMFhjcubj)}(h'``fw_dmcu`` Reference to DMCU firmware h](j)}(h ``fw_dmcu``h]j)}(hj h]hfw_dmcu}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMAhj ubj)}(hhh]h)}(hReference to DMCU firmwareh]hReference to DMCU firmware}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2 hMAhj3 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj2 hMAhjcubj)}(h1``dmcu_fw_version`` Version of the DMCU firmware h](j)}(h``dmcu_fw_version``h]j)}(hjV h]hdmcu_fw_version}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMBhjP ubj)}(hhh]h)}(hVersion of the DMCU firmwareh]hVersion of the DMCU firmware}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk hMBhjl ubah}(h]h ]h"]h$]h&]uh1jhjP ubeh}(h]h ]h"]h$]h&]uh1jhjk hMBhjcubj)}(h^``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW h](j)}(h``soc_bounding_box``h]j)}(hj h]hsoc_bounding_box}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM@hj ubj)}(hhh]h)}(hHgpu_info FW provided soc bounding box struct or 0 if not available in FWh]hHgpu_info FW provided soc bounding box struct or 0 if not available in FW}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM?hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hM@hjcubj)}(hC``active_vblank_irq_count`` number of currently active vblank irqs h](j)}(h``active_vblank_irq_count``h]j)}(hj h]hactive_vblank_irq_count}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMGhj ubj)}(hhh]h)}(h&number of currently active vblank irqsh]h&number of currently active vblank irqs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMGhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hMGhjcubj)}(h|``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. h](j)}(h``secure_display_ctx``h]j)}(hj!h]hsecure_display_ctx}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMPhj ubj)}(hhh]h)}(hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.h]hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMOhj!ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj!hMPhjcubj)}(h@``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq h](j)}(h``hpd_rx_offload_wq``h]j)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMWhj6!ubj)}(hhh]h)}(h)Work queue to offload works of hpd_rx_irqh]h)Work queue to offload works of hpd_rx_irq}(hjU!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQ!hMWhjR!ubah}(h]h ]h"]h$]h&]uh1jhj6!ubeh}(h]h ]h"]h$]h&]uh1jhjQ!hMWhjcubj)}(h0``mst_encoders`` fake encoders used for DP MST. h](j)}(h``mst_encoders``h]j)}(hju!h]h mst_encoders}(hjw!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM]hjo!ubj)}(hhh]h)}(hfake encoders used for DP MST.h]hfake encoders used for DP MST.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hM]hj!ubah}(h]h ]h"]h$]h&]uh1jhjo!ubeh}(h]h ]h"]h$]h&]uh1jhj!hM]hjcubj)}(hv``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. h](j)}(h``force_timing_sync``h]j)}(hj!h]hforce_timing_sync}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMHhj!ubj)}(hhh]h)}(h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.h]h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMGhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMHhjcubj)}(h[``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true h](j)}(h``disable_hpd_irq``h]j)}(hj!h]hdisable_hpd_irq}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMMhj!ubj)}(hhh]h)}(hFdisables all HPD and HPD RX interrupt handling in the driver when trueh]hFdisables all HPD and HPD RX interrupt handling in the driver when true}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMLhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMMhjcubj)}(h3``dmcub_trace_event_en`` enable dmcub trace events h](j)}(h``dmcub_trace_event_en``h]j)}(hj""h]hdmcub_trace_event_en}(hj$"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj "ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMIhj"ubj)}(hhh]h)}(henable dmcub trace eventsh]henable dmcub trace events}(hj;"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7"hMIhj8"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj7"hMIhjcubj)}(hG``da_list`` DAL fb memory allocation list, for communication with SMU. h](j)}(h ``da_list``h]j)}(hj["h]hda_list}(hj]"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMfhjU"ubj)}(hhh]h)}(h:DAL fb memory allocation list, for communication with SMU.h]h:DAL fb memory allocation list, for communication with SMU.}(hjt"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp"hMfhjq"ubah}(h]h ]h"]h$]h&]uh1jhjU"ubeh}(h]h ]h"]h$]h&]uh1jhjp"hMfhjcubj)}(h[``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done h](j)}(h``dmub_aux_transfer_done``h]j)}(hj"h]hdmub_aux_transfer_done}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMOhj"ubj)}(hhh]h)}(h?struct completion used to indicate when DMUB transfers are doneh]h?struct completion used to indicate when DMUB transfers are done}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMNhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMOhjcubj)}(h:``delayed_hpd_wq`` work queue used to delay DMUB HPD work h](j)}(h``delayed_hpd_wq``h]j)}(hj"h]hdelayed_hpd_wq}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMPhj"ubj)}(hhh]h)}(h&work queue used to delay DMUB HPD workh]h&work queue used to delay DMUB HPD work}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMPhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMPhjcubj)}(h(``brightness`` cached backlight values. h](j)}(h``brightness``h]j)}(hj#h]h brightness}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMohj#ubj)}(hhh]h)}(hcached backlight values.h]hcached backlight values.}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMohj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMohjcubj)}(hB``actual_brightness`` last successfully applied backlight values. h](j)}(h``actual_brightness``h]j)}(hj@#h]hactual_brightness}(hjB#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMuhj:#ubj)}(hhh]h)}(h+last successfully applied backlight values.h]h+last successfully applied backlight values.}(hjY#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU#hMuhjV#ubah}(h]h ]h"]h$]h&]uh1jhj:#ubeh}(h]h ]h"]h$]h&]uh1jhjU#hMuhjcubj)}(hh``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform h](j)}(h``aux_hpd_discon_quirk``h]j)}(hjy#h]haux_hpd_discon_quirk}(hj{#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM}hjs#ubj)}(hhh]h)}(hNquirk for hpd discon while aux is on-going. occurred on certain intel platformh]hNquirk for hpd discon while aux is on-going. occurred on certain intel platform}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM|hj#ubah}(h]h ]h"]h$]h&]uh1jhjs#ubeh}(h]h ]h"]h$]h&]uh1jhj#hM}hjcubj)}(h@``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. h](j)}(h``edp0_on_dp1_quirk``h]j)}(hj#h]hedp0_on_dp1_quirk}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj#ubj)}(hhh]h)}(h)quirk for platforms that put edp0 on DP1.h]h)quirk for platforms that put edp0 on DP1.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhjcubj)}(h,``dpia_aux_lock`` Guards access to DPIA AUX h](j)}(h``dpia_aux_lock``h]j)}(hj#h]h dpia_aux_lock}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj#ubj)}(hhh]h)}(hGuards access to DPIA AUXh]hGuards access to DPIA AUX}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj$ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjcubj)}(h``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct h](j)}(h``bb_from_dmub``h]j)}(hj%$h]h bb_from_dmub}(hj'$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj$ubj)}(hhh]h)}(hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb structh]hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct}(hj>$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj;$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj:$hMhjcubj)}(h``oem_i2c`` OEM i2c bus h](j)}(h ``oem_i2c``h]j)}(hj_$h]hoem_i2c}(hja$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjY$ubj)}(hhh]h)}(h OEM i2c bush]h OEM i2c bus}(hjx$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt$hMhju$ubah}(h]h ]h"]h$]h&]uh1jhjY$ubeh}(h]h ]h"]h$]h&]uh1jhjt$hMhjcubj)}(h$``fused_io`` dmub fused io interfaceh](j)}(h ``fused_io``h]j)}(hj$h]hfused_io}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj$ubj)}(hhh]h)}(hdmub fused io interfaceh]hdmub fused io interface}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjcubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j amdgpu_hdmi_vsdb_info (C struct)c.amdgpu_hdmi_vsdb_infohNtauh1jhhhhhjhNubj)}(hhh](j)}(hamdgpu_hdmi_vsdb_infoh]j)}(hstruct amdgpu_hdmi_vsdb_infoh](j)}(hj h]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMubj)}(h h]h }(hj%hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj$hhhj$hMubj+)}(hamdgpu_hdmi_vsdb_infoh]j1)}(hj$h]hamdgpu_hdmi_vsdb_info}(hj%hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj%ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj$hhhj$hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj$hhhj$hMubah}(h]j$ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj$hMhj$hhubj_)}(hhh]h)}(hKeep track of the VSDB infoh]hKeep track of the VSDB info}(hj4%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj1%hhubah}(h]h ]h"]h$]h&]uh1j^hj$hhhj$hMubeh}(h]h ](jstructeh"]h$]h&]jjjjL%jjL%jjjuh1jhhhhhjhNubj)}(hXK**Definition**:: struct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; bool replay_mode; }; **Members** ``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. ``freesync_supported`` FreeSync Supported. ``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. ``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz ``replay_mode`` Replay supportedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjX%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT%ubh:}(hjT%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjP%ubj)}(hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; bool replay_mode; };h]hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; bool replay_mode; };}hjq%sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjP%ubh)}(h **Members**h]j)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjP%ubj)}(hhh](j)}(h``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. h](j)}(h``amd_vsdb_version``h]j)}(hj%h]hamd_vsdb_version}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubj)}(hhh]h)}(hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.h]hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhj%ubj)}(h+``freesync_supported`` FreeSync Supported. h](j)}(h``freesync_supported``h]j)}(hj%h]hfreesync_supported}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubj)}(hhh]h)}(hFreeSync Supported.h]hFreeSync Supported.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhj%ubj)}(h=``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. h](j)}(h``min_refresh_rate_hz``h]j)}(hj&h]hmin_refresh_rate_hz}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubj)}(hhh]h)}(h$FreeSync Minimum Refresh Rate in Hz.h]h$FreeSync Minimum Refresh Rate in Hz.}(hj-&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)&hMhj*&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj)&hMhj%ubj)}(h<``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz h](j)}(h``max_refresh_rate_hz``h]j)}(hjM&h]hmax_refresh_rate_hz}(hjO&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjG&ubj)}(hhh]h)}(h#FreeSync Maximum Refresh Rate in Hzh]h#FreeSync Maximum Refresh Rate in Hz}(hjf&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb&hMhjc&ubah}(h]h ]h"]h$]h&]uh1jhjG&ubeh}(h]h ]h"]h$]h&]uh1jhjb&hMhj%ubj)}(h ``replay_mode`` Replay supportedh](j)}(h``replay_mode``h]j)}(hj&h]h replay_mode}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubj)}(hhh]h)}(hReplay supportedh]hReplay supported}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhj%ubeh}(h]h ]h"]h$]h&]uh1jhjP%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubh)}(h**Description**h]j)}(hj&h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhhhubh)}(hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.h]hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhhhubh)}(hhh](h)}(h Lifecycleh]h Lifecycle}(hj&hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj&hhhhhKubh)}(hDM (and consequently DC) is registered in the amdgpu base driver as a IP block. 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This involves calling the initializers of each DM component, then populating the struct with them.h](hInitialize the }(hj(hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]j)}(hj(h]hstruct amdgpu_display_manager}(hj(hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj(ubhk device. This involves calling the initializers of each DM component, then populating the struct with them.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj(hM hjC(ubh)}(hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.h]hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC(ubh)}(h.Some notable things that are initialized here:h]h.Some notable things that are initialized here:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC(ubh)}(hhh](h)}(h(Display Core, both software and hardwareh]h)}(hj)h]h(Display Core, both software and hardware}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj )ubah}(h]h ]h"]h$]h&]uh1hhj )ubh)}(h7DC modules that we need (freesync and color management)h]h)}(hj&)h]h7DC modules that we need (freesync and color management)}(hj()hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj$)ubah}(h]h ]h"]h$]h&]uh1hhj )ubh)}(hDRM software statesh]h)}(hj>)h]hDRM software states}(hj@)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj<)ubah}(h]h ]h"]h$]h&]uh1hhj )ubh)}(hInterrupt sources and handlersh]h)}(hjV)h]hInterrupt sources and handlers}(hjX)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjT)ubah}(h]h ]h"]h$]h&]uh1hhj )ubh)}(hVblank supporth]h)}(hjn)h]hVblank support}(hjp)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjl)ubah}(h]h ]h"]h$]h&]uh1hhj )ubh)}(hDebug FS entries, if enabledh]h)}(hj)h]hDebug FS entries, if enabled}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj)ubah}(h]h ]h"]h$]h&]uh1hhj )ubeh}(h]h ]h"]h$]h&]bullet-uh1hhj)hM hjC(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj&hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_hw_fini (C function) c.dm_hw_finihNtauh1jhj&hhhNhNubj)}(hhh](j)}(h1int dm_hw_fini (struct amdgpu_ip_block *ip_block)h]j)}(h0int dm_hw_fini(struct amdgpu_ip_block *ip_block)h](jZ')}(hinth]hint}(hj)hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj)hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM ubj)}(h h]h }(hj)hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj)hhhj)hM ubj+)}(h dm_hw_finih]j1)}(h dm_hw_finih]h dm_hw_fini}(hj)hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj)ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj)hhhj)hM ubj')}(h"(struct amdgpu_ip_block *ip_block)h]j')}(h struct amdgpu_ip_block *ip_blockh](j)}(hj h]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(h h]h }(hj*hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj)ubh)}(hhh]j1)}(hamdgpu_ip_blockh]hamdgpu_ip_block}(hj*hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj*ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj!*modnameN classnameNjj)}j ]j')}j'j)sb c.dm_hw_finiasbuh1hhj)ubj)}(h h]h }(hj?*hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj)ubj')}(hj'h]h*}(hjM*hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj)ubj1)}(hip_blockh]hip_block}(hjZ*hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj)ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj)ubah}(h]h ]h"]h$]h&]jHjIuh1j'hj)hhhj)hM ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj)hhhj)hM ubah}(h]j)ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj)hM hj)hhubj_)}(hhh]h)}(hTeardown DC deviceh]hTeardown DC device}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*hhubah}(h]h ]h"]h$]h&]uh1j^hj)hhhj)hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj*jj*jjjuh1jhhhj&hNhNubj)}(hXk**Parameters** ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. **Description** Teardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. 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Also flush IRQ workqueues and disable them.h](h)}(h**Parameters**h]j)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*ubj)}(hhh]j)}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](j)}(h$``struct amdgpu_ip_block *ip_block``h]j)}(hj*h]h struct amdgpu_ip_block *ip_block}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*ubj)}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubh)}(h**Description**h]j)}(hj+h]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*ubh)}(hTeardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.h](hTeardown components within }(hj+hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]j)}(hj +h]hstruct amdgpu_display_manager}(hj"+hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj+ubh that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=+hM hj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj&hhhNhNubeh}(h]j ah ]h"] lifecycleah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Interruptsh]h Interrupts}(hjY+hhhNhNubah}(h]h ]h"]h$]h&]hj'uh1hhjV+hhhhhKubh)}(hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.h]hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.}(hjg+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK#hjV+hhubh)}(hXOThe base driver provides IRQ source registration with DRM, handler registration into the base driver's IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. 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They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM's IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See dce110_register_irq_handlers() and dcn10_register_irq_handlers().h](hjThey override the base driver’s IRQ table, and the effect can be seen in the hooks that DM provides for }(hj%,hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]j)}(hj/,h]hamdgpu_irq_src_funcs.process}(hj1,hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj-,ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK3hj%,ubhX . They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM’s IRQ tables. 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Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.}(hjW,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj~,hK:hjV+hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_dm_irq_handler_data (C struct)c.amdgpu_dm_irq_handler_datahNtauh1jhjV+hhhNhNubj)}(hhh](j)}(hamdgpu_dm_irq_handler_datah]j)}(h!struct amdgpu_dm_irq_handler_datah](j)}(hj h]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKubj)}(h h]h }(hj,hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj,hhhj,hKubj+)}(hamdgpu_dm_irq_handler_datah]j1)}(hj,h]hamdgpu_dm_irq_handler_data}(hj,hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj,ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj,hhhj,hKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj,hhhj,hKubah}(h]j,ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj,hKhj,hhubj_)}(hhh]h)}(hData for DM interrupt handlers.h]hData for DM interrupt handlers.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKFhj,hhubah}(h]h ]h"]h$]h&]uh1j^hj,hhhj,hKubeh}(h]h ](jstructeh"]h$]h&]jjjj,jj,jjjuh1jhhhjV+hNhNubj)}(hX?**Definition**:: struct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; }; **Members** ``list`` Linked list entry referencing the next/previous handler ``handler`` Handler function ``handler_arg`` Argument passed to the handler when triggered ``dm`` DM which this handler belongs to ``irq_source`` DC interrupt source that this handler is registered for ``work`` work structh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKJhj-ubj)}(hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };h]hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };}hj!-sbah}(h]h ]h"]h$]h&]jHjIuh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhj-ubh)}(h **Members**h]j)}(hj2-h]hMembers}(hj4-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0-ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKUhj-ubj)}(hhh](j)}(hA``list`` Linked list entry referencing the next/previous handler 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h](j)}(h``handler_arg``h]j)}(hj-h]h handler_arg}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKKhj-ubj)}(hhh]h)}(h-Argument passed to the handler when triggeredh]h-Argument passed to the handler when triggered}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKKhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hKKhjH-ubj)}(h(``dm`` DM which this handler belongs to h](j)}(h``dm``h]j)}(hj-h]hdm}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhj-ubj)}(hhh]h)}(h DM which this handler belongs toh]h DM which this handler belongs to}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hKLhj.ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj.hKLhjH-ubj)}(hG``irq_source`` DC interrupt source that this handler is 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``struct work_struct *work`` work structh](h)}(h**Parameters**h]j)}(hj/h]h Parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKshj/ubj)}(hhh]j)}(h(``struct work_struct *work`` work structh](j)}(h``struct work_struct *work``h]j)}(hj/h]hstruct work_struct *work}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKuhj/ubj)}(hhh]h)}(h work structh]h work struct}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKqhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hKuhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h 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The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.h]hXRegister an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM#hj3ubh)}(hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.h]hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM(hj3ubh)}(h **Return**h]j)}(hj5h]hReturn}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM+hj3ubh)}(hHandler data :c:type:`struct amdgpu_dm_irq_handler_data ` containing the IRQ source, handler function, and argsh](h Handler data }(hj)5hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]j)}(hj35h]h!struct amdgpu_dm_irq_handler_data}(hj55hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj15ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM,hj)5ubh6 containing the IRQ source, handler function, and args}(hj)5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjP5hM,hj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/amdgpu_dm_irq_unregister_interrupt (C function)$c.amdgpu_dm_irq_unregister_interrupthNtauh1jhjV+hhhNhNubj)}(hhh](j)}(hmvoid amdgpu_dm_irq_unregister_interrupt (struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h]j)}(hlvoid amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](jZ')}(hvoidh]hvoid}(hj{5hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjw5hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMjubj)}(h h]h }(hj5hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjw5hhhj5hMjubj+)}(h"amdgpu_dm_irq_unregister_interrupth]j1)}(h"amdgpu_dm_irq_unregister_interrupth]h"amdgpu_dm_irq_unregister_interrupt}(hj5hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj5ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjw5hhhj5hMjubj')}(hE(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj5ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hj5hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj5ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj5modnameN classnameNjj)}j ]j')}j'j5sb$c.amdgpu_dm_irq_unregister_interruptasbuh1hhj5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj5ubj')}(hj'h]h*}(hj6hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj5ubj1)}(hadevh]hadev}(hj6hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj5ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj5ubj')}(henum dc_irq_source irq_sourceh](j)}(henumh]henum}(hj*6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&6ubj)}(h h]h }(hj86hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj&6ubh)}(hhh]j1)}(h dc_irq_sourceh]h dc_irq_source}(hjI6hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjF6ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjK6modnameN classnameNjj)}j ]j5$c.amdgpu_dm_irq_unregister_interruptasbuh1hhj&6ubj)}(h h]h }(hjg6hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj&6ubj1)}(h irq_sourceh]h irq_source}(hju6hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj&6ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj5ubj')}(hvoid *ihh](jZ')}(hvoidh]hvoid}(hj6hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj6ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj6ubj')}(hj'h]h*}(hj6hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj6ubj1)}(hihh]hih}(hj6hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj6ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj5ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjw5hhhj5hMjubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjs5hhhj5hMjubah}(h]jn5ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj5hMjhjp5hhubj_)}(hhh]h)}(h&Remove a handler from the DM IRQ tableh]h&Remove a handler from the DM IRQ table}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMjhj6hhubah}(h]h ]h"]h$]h&]uh1j^hjp5hhhj5hMjubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6jj6jjjuh1jhhhjV+hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device ``enum dc_irq_source irq_source`` IRQ source to remove the given handler from ``void *ih`` Function pointer to the interrupt handler to unregister **Description** Go through both low and high context IRQ tables, and find the given handler for the given irq source. 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Otherwise, do nothing.h](h)}(h**Parameters**h]j)}(hj7h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj6ubj)}(hhh](j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj"7h]hstruct amdgpu_device *adev}(hj$7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 7ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMkhj7ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hj;7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj77hMkhj87ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj77hMkhj7ubj)}(hN``enum dc_irq_source irq_source`` IRQ source to remove the given handler from h](j)}(h!``enum dc_irq_source irq_source``h]j)}(hj[7h]henum dc_irq_source irq_source}(hj]7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY7ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMlhjU7ubj)}(hhh]h)}(h+IRQ source to remove the given handler fromh]h+IRQ source to remove the given handler from}(hjt7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp7hMlhjq7ubah}(h]h ]h"]h$]h&]uh1jhjU7ubeh}(h]h ]h"]h$]h&]uh1jhjp7hMlhj7ubj)}(hE``void *ih`` Function pointer to the interrupt handler to unregister h](j)}(h ``void *ih``h]j)}(hj7h]hvoid *ih}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMmhj7ubj)}(hhh]h)}(h7Function pointer to the interrupt handler to unregisterh]h7Function pointer to the interrupt handler to unregister}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMmhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMmhj7ubeh}(h]h ]h"]h$]h&]uh1jhj6ubh)}(h**Description**h]j)}(hj7h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMohj6ubh)}(hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h]hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_init (C function)c.amdgpu_dm_irq_inithNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h3int amdgpu_dm_irq_init (struct amdgpu_device *adev)h]j)}(h2int amdgpu_dm_irq_init(struct amdgpu_device *adev)h](jZ')}(hinth]hint}(hj8hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj8hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj#8hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj8hhhj"8hMubj+)}(hamdgpu_dm_irq_inith]j1)}(hamdgpu_dm_irq_inith]hamdgpu_dm_irq_init}(hj58hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj18ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj8hhhj"8hMubj')}(h(struct amdgpu_device *adev)h]j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hjQ8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjM8ubj)}(h h]h }(hj^8hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjM8ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hjo8hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjl8ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjq8modnameN classnameNjj)}j ]j')}j'j78sbc.amdgpu_dm_irq_initasbuh1hhjM8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjM8ubj')}(hj'h]h*}(hj8hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjM8ubj1)}(hadevh]hadev}(hj8hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjM8ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjI8ubah}(h]h ]h"]h$]h&]jHjIuh1j'hj8hhhj"8hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj 8hhhj"8hMubah}(h]j8ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj"8hMhj 8hhubj_)}(hhh]h)}(hInitialize DM IRQ managementh]hInitialize DM IRQ management}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8hhubah}(h]h ]h"]h$]h&]uh1j^hj 8hhhj"8hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj8jj8jjjuh1jhhhjV+hNhNubj)}(hXt**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Initialize DM's high and low context IRQ tables. The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order. The low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](h)}(h**Parameters**h]j)}(hj8h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubj)}(hhh]j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj9h]hstruct amdgpu_device *adev}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj9ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hj.9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*9hMhj+9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj*9hMhj 9ubah}(h]h ]h"]h$]h&]uh1jhj8ubh)}(h**Description**h]j)}(hjP9h]h Description}(hjR9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN9ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubh)}(h0Initialize DM's high and low context IRQ tables.h]h2Initialize DM’s high and low context IRQ tables.}(hjf9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubh)}(hX.The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.h](h0The N by M table contains N IRQ sources, with M }(hju9hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]j)}(hj9h]h!struct amdgpu_dm_irq_handler_data}(hj9hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj}9ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhju9ubh hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.}(hju9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj9hMhj8ubh)}(hThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](hpThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See }(hj9hhhNhNubh)}(h.:c:type:`struct irq_list_head `h]j)}(hj9h]hstruct irq_list_head}(hj9hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj irq_list_headuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj9ubh.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj9hMhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_fini (C function)c.amdgpu_dm_irq_finihNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_irq_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_irq_fini(struct amdgpu_device *adev)h](jZ')}(hvoidh]hvoid}(hj9hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj9hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj:hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj9hhhj:hMubj+)}(hamdgpu_dm_irq_finih]j1)}(hamdgpu_dm_irq_finih]hamdgpu_dm_irq_fini}(hj:hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj:ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj9hhhj:hMubj')}(h(struct amdgpu_device *adev)h]j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hj6:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2:ubj)}(h h]h }(hjC:hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj2:ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hjT:hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjQ:ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjV:modnameN classnameNjj)}j ]j')}j'j:sbc.amdgpu_dm_irq_finiasbuh1hhj2:ubj)}(h h]h }(hjt:hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj2:ubj')}(hj'h]h*}(hj:hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj2:ubj1)}(hadevh]hadev}(hj:hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj2:ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj.:ubah}(h]h ]h"]h$]h&]jHjIuh1j'hj9hhhj:hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj9hhhj:hMubah}(h]j9ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj:hMhj9hhubj_)}(hhh]h)}(hTear down DM IRQ managementh]hTear down DM IRQ management}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:hhubah}(h]h ]h"]h$]h&]uh1j^hj9hhhj:hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj:jj:jjjuh1jhhhjV+hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Flush all work within the low context IRQ table.h](h)}(h**Parameters**h]j)}(hj:h]h Parameters}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubj)}(hhh]j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj:h]hstruct amdgpu_device *adev}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubh)}(h**Description**h]j)}(hj5;h]h Description}(hj7;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubh)}(h0Flush all work within the low context IRQ table.h]h0Flush all work within the low context IRQ table.}(hjK;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"amdgpu_dm_irq_handler (C function)c.amdgpu_dm_irq_handlerhNtauh1jhjV+hhhNhNubj)}(hhh](j)}(htint amdgpu_dm_irq_handler (struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h]j)}(hsint amdgpu_dm_irq_handler(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](jZ')}(hinth]hint}(hjz;hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjv;hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj;hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjv;hhhj;hMubj+)}(hamdgpu_dm_irq_handlerh]j1)}(hamdgpu_dm_irq_handlerh]hamdgpu_dm_irq_handler}(hj;hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj;ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjv;hhhj;hMubj')}(hZ(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj;ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hj;hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj;ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj;modnameN classnameNjj)}j ]j')}j'j;sbc.amdgpu_dm_irq_handlerasbuh1hhj;ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj;ubj')}(hj'h]h*}(hj<hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj;ubj1)}(hadevh]hadev}(hj<hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj;ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj;ubj')}(hstruct amdgpu_irq_src *sourceh](j)}(hj h]hstruct}(hj)<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%<ubj)}(h h]h }(hj6<hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj%<ubh)}(hhh]j1)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hjG<hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjD<ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjI<modnameN classnameNjj)}j ]j;c.amdgpu_dm_irq_handlerasbuh1hhj%<ubj)}(h h]h }(hje<hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj%<ubj')}(hj'h]h*}(hjs<hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj%<ubj1)}(hsourceh]hsource}(hj<hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj%<ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj;ubj')}(hstruct amdgpu_iv_entry *entryh](j)}(hj h]hstruct}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubj)}(h h]h }(hj<hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj<ubh)}(hhh]j1)}(hamdgpu_iv_entryh]hamdgpu_iv_entry}(hj<hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj<modnameN classnameNjj)}j ]j;c.amdgpu_dm_irq_handlerasbuh1hhj<ubj)}(h h]h }(hj<hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj<ubj')}(hj'h]h*}(hj<hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj<ubj1)}(hentryh]hentry}(hj<hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj<ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj;ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjv;hhhj;hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjr;hhhj;hMubah}(h]jm;ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj;hMhjo;hhubj_)}(hhh]h)}(hGeneric DM IRQ handlerh]hGeneric DM IRQ handler}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=hhubah}(h]h ]h"]h$]h&]uh1j^hjo;hhhj;hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj2=jj2=jjjuh1jhhhjV+hNhNubj)}(hXv**Parameters** ``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device ``struct amdgpu_irq_src *source`` Unused ``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt **Description** Calls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h](h)}(h**Parameters**h]j)}(hj<=h]h Parameters}(hj>=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:=ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6=ubj)}(hhh](j)}(hR``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj[=h]hstruct amdgpu_device *adev}(hj]=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjU=ubj)}(hhh]h)}(h2amdgpu base driver device containing the DM deviceh]h2amdgpu base driver device containing the DM device}(hjt=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp=hMhjq=ubah}(h]h ]h"]h$]h&]uh1jhjU=ubeh}(h]h ]h"]h$]h&]uh1jhjp=hMhjR=ubj)}(h)``struct amdgpu_irq_src *source`` Unused h](j)}(h!``struct amdgpu_irq_src *source``h]j)}(hj=h]hstruct amdgpu_irq_src *source}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubj)}(hhh]h)}(hUnusedh]hUnused}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhjR=ubj)}(hE``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt h](j)}(h!``struct amdgpu_iv_entry *entry``h]j)}(hj=h]hstruct amdgpu_iv_entry *entry}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubj)}(hhh]h)}(h"Data about the triggered interrupth]h"Data about the triggered interrupt}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhjR=ubeh}(h]h ]h"]h$]h&]uh1jhj6=ubh)}(h**Description**h]j)}(hj>h]h Description}(hj >hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6=ubh)}(hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h]hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_init (C function)c.amdgpu_dm_hpd_inithNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_hpd_init (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_init(struct amdgpu_device *adev)h](jZ')}(hvoidh]hvoid}(hjM>hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjI>hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzubj)}(h h]h }(hj\>hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjI>hhhj[>hMzubj+)}(hamdgpu_dm_hpd_inith]j1)}(hamdgpu_dm_hpd_inith]hamdgpu_dm_hpd_init}(hjn>hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjj>ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjI>hhhj[>hMzubj')}(h(struct amdgpu_device *adev)h]j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj)}(h h]h }(hj>hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj>ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hj>hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj>ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj>modnameN classnameNjj)}j ]j')}j'jp>sbc.amdgpu_dm_hpd_initasbuh1hhj>ubj)}(h h]h }(hj>hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj>ubj')}(hj'h]h*}(hj>hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj>ubj1)}(hadevh]hadev}(hj>hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj>ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj>ubah}(h]h ]h"]h$]h&]jHjIuh1j'hjI>hhhj[>hMzubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjE>hhhj[>hMzubah}(h]j@>ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj[>hMzhjB>hhubj_)}(hhh]h)}(hhpd setup callback.h]hhpd setup callback.}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzhj ?hhubah}(h]h ]h"]h$]h&]uh1j^hjB>hhhj[>hMzubeh}(h]h ](jfunctioneh"]h$]h&]jjjj%?jj%?jjjuh1jhhhjV+hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Setup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hj/?h]h Parameters}(hj1?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hj)?ubj)}(hhh]j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hjN?h]hstruct amdgpu_device *adev}(hjP?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM|hjH?ubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjg?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc?hM|hjd?ubah}(h]h ]h"]h$]h&]uh1jhjH?ubeh}(h]h ]h"]h$]h&]uh1jhjc?hM|hjE?ubah}(h]h ]h"]h$]h&]uh1jhj)?ubh)}(h**Description**h]j)}(hj?h]h Description}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hj)?ubh)}(hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h]hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM}hj)?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_fini (C function)c.amdgpu_dm_hpd_finihNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_hpd_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)h](jZ')}(hvoidh]hvoid}(hj?hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj?hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj?hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj?hhhj?hMubj+)}(hamdgpu_dm_hpd_finih]j1)}(hamdgpu_dm_hpd_finih]hamdgpu_dm_hpd_fini}(hj?hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj?ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj?hhhj?hMubj')}(h(struct amdgpu_device *adev)h]j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hj @hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj)}(h h]h }(hj@hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj@ubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hj)@hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj&@ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj+@modnameN classnameNjj)}j ]j')}j'j?sbc.amdgpu_dm_hpd_finiasbuh1hhj@ubj)}(h h]h }(hjI@hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj@ubj')}(hj'h]h*}(hjW@hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj@ubj1)}(hadevh]hadev}(hjd@hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj@ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj@ubah}(h]h ]h"]h$]h&]jHjIuh1j'hj?hhhj?hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj?hhhj?hMubah}(h]j?ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj?hMhj?hhubj_)}(hhh]h)}(hhpd tear down callback.h]hhpd tear down callback.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@hhubah}(h]h ]h"]h$]h&]uh1j^hj?hhhj?hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj@jj@jjjuh1jhhhjV+hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Tear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hj@h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@ubj)}(hhh]j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hj@h]hstruct amdgpu_device *adev}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@ubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubh)}(h**Description**h]j)}(hj Ah]h Description}(hj AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@ubh)}(hQTear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h]hQTear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.}(hj AhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_pflip_high_irq (C function)c.dm_pflip_high_irqhNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h/void dm_pflip_high_irq (void *interrupt_params)h]j)}(h.void dm_pflip_high_irq(void *interrupt_params)h](jZ')}(hvoidh]hvoid}(hjOAhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjKAhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubj)}(h h]h }(hj^AhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjKAhhhj]AhMubj+)}(hdm_pflip_high_irqh]j1)}(hdm_pflip_high_irqh]hdm_pflip_high_irq}(hjpAhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjlAubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjKAhhhj]AhMubj')}(h(void *interrupt_params)h]j')}(hvoid *interrupt_paramsh](jZ')}(hvoidh]hvoid}(hjAhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjAubj)}(h h]h }(hjAhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjAubj')}(hj'h]h*}(hjAhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjAubj1)}(hinterrupt_paramsh]hinterrupt_params}(hjAhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjAubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjAubah}(h]h ]h"]h$]h&]jHjIuh1j'hjKAhhhj]AhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjGAhhhj]AhMubah}(h]jBAah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj]AhMhjDAhhubj_)}(hhh]h)}(hHandle pageflip interrupth]hHandle pageflip interrupt}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjAhhubah}(h]h ]h"]h$]h&]uh1j^hjDAhhhj]AhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjAjjAjjjuh1jhhhjV+hNhNubj)}(h**Parameters** ``void *interrupt_params`` ignored **Description** Handles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h](h)}(h**Parameters**h]j)}(hjBh]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjAubj)}(hhh]j)}(h#``void *interrupt_params`` ignored h](j)}(h``void *interrupt_params``h]j)}(hj Bh]hvoid *interrupt_params}(hj"BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjBubj)}(hhh]h)}(hignoredh]hignored}(hj9BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5BhMhj6Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj5BhMhjBubah}(h]h ]h"]h$]h&]uh1jhjAubh)}(h**Description**h]j)}(hj[Bh]h Description}(hj]BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYBubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjAubh)}(hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h]hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.}(hjqBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjAubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_crtc_high_irq (C function)c.dm_crtc_high_irqhNtauh1jhjV+hhhNhNubj)}(hhh](j)}(h.void dm_crtc_high_irq (void *interrupt_params)h]j)}(h-void dm_crtc_high_irq(void *interrupt_params)h](jZ')}(hvoidh]hvoid}(hjBhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjBhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubj)}(h h]h }(hjBhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjBhhhjBhMubj+)}(hdm_crtc_high_irqh]j1)}(hdm_crtc_high_irqh]hdm_crtc_high_irq}(hjBhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjBubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjBhhhjBhMubj')}(h(void *interrupt_params)h]j')}(hvoid *interrupt_paramsh](jZ')}(hvoidh]hvoid}(hjBhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjBubj)}(h h]h }(hjBhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjBubj')}(hj'h]h*}(hjBhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjBubj1)}(hinterrupt_paramsh]hinterrupt_params}(hjChhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjBubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjBubah}(h]h ]h"]h$]h&]jHjIuh1j'hjBhhhjBhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjBhhhjBhMubah}(h]jBah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjBhMhjBhhubj_)}(hhh]h)}(hHandles CRTC interrupth]hHandles CRTC interrupt}(hj0ChhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj-Chhubah}(h]h ]h"]h$]h&]uh1j^hjBhhhjBhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjHCjjHCjjjuh1jhhhjV+hNhNubj)}(h**Parameters** ``void *interrupt_params`` used for determining the CRTC instance **Description** Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK event handler.h](h)}(h**Parameters**h]j)}(hjRCh]h Parameters}(hjTChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPCubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjLCubj)}(hhh]j)}(hB``void *interrupt_params`` used for determining the CRTC instance h](j)}(h``void *interrupt_params``h]j)}(hjqCh]hvoid *interrupt_params}(hjsChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoCubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjkCubj)}(hhh]h)}(h&used for determining the CRTC instanceh]h&used for determining the CRTC instance}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjkCubeh}(h]h ]h"]h$]h&]uh1jhjChMhjhCubah}(h]h ]h"]h$]h&]uh1jhjLCubh)}(h**Description**h]j)}(hjCh]h Description}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjLCubh)}(hHHandles the CRTC/VSYNC interrupt by notfying DRM's VBLANK event handler.h]hJHandles the CRTC/VSYNC interrupt by notfying DRM’s VBLANK event handler.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjLCubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV+hhhNhNubeh}(h]j-ah ]h"] interruptsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAtomic Implementationh]hAtomic Implementation}(hjChhhNhNubah}(h]h ]h"]h$]h&]hjIuh1hhjChhhhhK$ubh)}(h*WIP*h]hemphasis)}(hjCh]hWIP}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jChjCubah}(h]h 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h]hstruct}(hj`DhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\Dubj)}(h h]h }(hjmDhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj\Dubh)}(hhh]j1)}(hdrm_atomic_stateh]hdrm_atomic_state}(hj~DhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj{Dubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjDmodnameN classnameNjj)}j ]j')}j'jFDsbc.amdgpu_dm_atomic_commit_tailasbuh1hhj\Dubj)}(h h]h }(hjDhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj\Dubj')}(hj'h]h*}(hjDhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj\Dubj1)}(hstateh]hstate}(hjDhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj\Dubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjXDubah}(h]h ]h"]h$]h&]jHjIuh1j'hjDhhhj1DhM2*ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjDhhhj1DhM2*ubah}(h]jDah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj1DhM2*hjDhhubj_)}(hhh]h)}(h'AMDgpu DM's commit tail implementation.h]h)AMDgpu DM’s commit tail implementation.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM2*hjDhhubah}(h]h ]h"]h$]h&]uh1j^hjDhhhj1DhM2*ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjDjjDjjjuh1jhhhjChNhNubj)}(hX.**Parameters** ``struct drm_atomic_state *state`` The atomic state to commit **Description** This will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h](h)}(h**Parameters**h]j)}(hjEh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM6*hjDubj)}(hhh]j)}(h>``struct drm_atomic_state *state`` The atomic state to commit h](j)}(h"``struct drm_atomic_state *state``h]j)}(hj$Eh]hstruct drm_atomic_state *state}(hj&EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Eubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM3*hjEubj)}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hj=EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9EhM3*hj:Eubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhj9EhM3*hjEubah}(h]h ]h"]h$]h&]uh1jhjDubh)}(h**Description**h]j)}(hj_Eh]h Description}(hjaEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]Eubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM5*hjDubh)}(hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h]hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.}(hjuEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM4*hjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjChhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_atomic_check (C function)c.amdgpu_dm_atomic_checkhNtauh1jhjChhhNhNubj)}(hhh](j)}(hSint amdgpu_dm_atomic_check (struct drm_device *dev, struct drm_atomic_state *state)h]j)}(hRint amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)h](jZ')}(hinth]hint}(hjEhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjEhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMa0ubj)}(h h]h }(hjEhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjEhhhjEhMa0ubj+)}(hamdgpu_dm_atomic_checkh]j1)}(hamdgpu_dm_atomic_checkh]hamdgpu_dm_atomic_check}(hjEhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjEubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjEhhhjEhMa0ubj')}(h8(struct drm_device *dev, struct drm_atomic_state *state)h](j')}(hstruct drm_device *devh](j)}(hj h]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubj)}(h h]h }(hjEhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjEubh)}(hhh]j1)}(h drm_deviceh]h drm_device}(hjEhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjEubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjFmodnameN classnameNjj)}j ]j')}j'jEsbc.amdgpu_dm_atomic_checkasbuh1hhjEubj)}(h h]h }(hjFhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjEubj')}(hj'h]h*}(hj-FhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjEubj1)}(hdevh]hdev}(hj:FhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjEubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjEubj')}(hstruct drm_atomic_state *stateh](j)}(hj h]hstruct}(hjSFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOFubj)}(h h]h }(hj`FhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjOFubh)}(hhh]j1)}(hdrm_atomic_stateh]hdrm_atomic_state}(hjqFhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjnFubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjsFmodnameN classnameNjj)}j ]jFc.amdgpu_dm_atomic_checkasbuh1hhjOFubj)}(h h]h }(hjFhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjOFubj')}(hj'h]h*}(hjFhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjOFubj1)}(hstateh]hstate}(hjFhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjOFubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjEubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjEhhhjEhMa0ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjEhhhjEhMa0ubah}(h]jEah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjEhMa0hjEhhubj_)}(hhh]h)}(h*Atomic check implementation for AMDgpu DM..h]h*Atomic check implementation for AMDgpu DM.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMa0hjFhhubah}(h]h ]h"]h$]h&]uh1j^hjEhhhjEhMa0ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjFjjFjjjuh1jhhhjChNhNubj)}(hX**Parameters** ``struct drm_device *dev`` The DRM device ``struct drm_atomic_state *state`` The atomic state to commit **Description** Validate that the given atomic state is programmable by DC into hardware. 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This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.h](hgValidate that the given atomic state is programmable by DC into hardware. This involves constructing a }(hjGhhhNhNubh)}(h$:c:type:`struct dc_state `h]j)}(hjGh]hstruct dc_state}(hjGhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMe0hjGubh reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It’s important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjGhMe0hjFubh)}(hXNWhen validating the DC state, it's important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.h]hXPWhen validating the DC state, it’s important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMk0hjFubh)}(hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.h]hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMq0hjFubh)}(h **Return**h]j)}(hjGh]hReturn}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMv0hjFubh)}(h!-Error code if validation failed.h]h!-Error code if validation failed.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMw0hjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjChhhNhNubeh}(h]jOah ]h"]atomic implementationah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hColor Management Propertiesh]hColor Management Properties}(hj'HhhhNhNubah}(h]h ]h"]h$]h&]hjkuh1hhj$HhhhhhK-ubh)}(hWe have three types of color management in the AMD display driver. 1. the legacy :c:type:`drm_crtc` DEGAMMA, CTM, and GAMMA properties 2. AMD driver private color management on :c:type:`drm_plane` and :c:type:`drm_crtc` 3. AMD plane color pipelineh](hQWe have three types of color management in the AMD display driver. 1. the legacy }(hj5HhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hj?Hh]hdrm_crtc}(hjAHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj=Hubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_crtcuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK"hj5HubhN DEGAMMA, CTM, and GAMMA properties 2. AMD driver private color management on }(hj5HhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjcHh]h drm_plane}(hjeHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjaHubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_planeuh1hhj\HhK"hj5Hubh and }(hj5HhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjHh]hdrm_crtc}(hjHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_crtcuh1hhj\HhK"hj5Hubh 3. AMD plane color pipeline}(hj5HhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj\HhK"hj$Hhhubh)}(hXThe CRTC properties are the original color management. When they were implemented per-plane color management was not a thing yet. Because of that we could get away with plumbing the DEGAMMA and CTM properties to pre-blending HW functions. This is incompatible with per-plane color management, such as via the AMD private properties or the new drm_plane color pipeline. The only compatible CRTC property with per-plane color management is the GAMMA property as it is applied post-blending.h]hXThe CRTC properties are the original color management. When they were implemented per-plane color management was not a thing yet. Because of that we could get away with plumbing the DEGAMMA and CTM properties to pre-blending HW functions. This is incompatible with per-plane color management, such as via the AMD private properties or the new drm_plane color pipeline. The only compatible CRTC property with per-plane color management is the GAMMA property as it is applied post-blending.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK'hj$Hhhubh)}(hX4The AMD driver private color management properties are only exposed when the kernel is built explicitly with -DAMD_PRIVATE_COLOR. They are temporary building blocks on the path to full-fledged :c:type:`drm_plane` and :c:type:`drm_crtc` color pipelines and lay the driver's groundwork for the color pipelines.h](hThe AMD driver private color management properties are only exposed when the kernel is built explicitly with -DAMD_PRIVATE_COLOR. They are temporary building blocks on the path to full-fledged }(hjHhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjHh]h drm_plane}(hjHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK0hjHubh and }(hjHhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjHh]hdrm_crtc}(hjHhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_crtcuh1hhjHhK0hjHubhK color pipelines and lay the driver’s groundwork for the color pipelines.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjHhK0hj$Hhhubh)}(hzThe AMD plane color pipeline describes AMD's :c:type:`drm_colorops` via the :c:type:`drm_plane`'s COLOR_PIPELINE property.h](h/The AMD plane color pipeline describes AMD’s }(hjIhhhNhNubh)}(h:c:type:`drm_colorops`h]j)}(hjIh]h drm_colorops}(hjIhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_coloropsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK6hjIubh via the }(hjIhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hj?Ih]h drm_plane}(hjAIhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj=Iubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_planeuh1hhj8IhK6hjIubh’s COLOR_PIPELINE property.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj8IhK6hj$Hhhubh)}(hhh](h)}(hdrm_crtc Propertiesh]hdrm_crtc Properties}(hjiIhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjfIhNhNubh)}(hYThe DC interface to HW gives us the following color management blocks per pipe (surface):h]hYThe DC interface to HW gives us the following color management blocks per pipe (surface):}(hjwIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK Plane degamma -> Plane CTM -> Plane regamma -> Plane CTMh]hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM}(hj/JhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKJhjfIubh)}(hXThe input gamma LUT block isn't really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.h]hXThe input gamma LUT block isn’t really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.}(hj>JhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKLhjfIubh)}(hX!The pipe blending also happens after these blocks so we don't actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.h]hX#The pipe blending also happens after these blocks so we don’t actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.}(hjMJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKThjfIubh)}(hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.h]hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.}(hj\JhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKZhjfIubh)}(hIThis means that the following configuration is assumed to be the default:h]hIThis means that the following configuration is assumed to be the default:}(hjkJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK^hjfIubh)}(huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypassh]huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass}(hjzJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKahjfIubeh}(h]jah ]h"]drm_crtc propertiesah$]h&]uh1hhj$HhhhNhNubh)}(hhh](h)}(h)AMD Private Color Management on drm_planeh]h)AMD Private Color Management on drm_plane}(hjJhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjJhNhNubh)}(hIThe AMD private color management properties on a :c:type:`drm_plane` are:h](h1The AMD private color management properties on a }(hjJhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjJh]h drm_plane}(hjJhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKghjJubh are:}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjJhKghjJubh)}(hhh](h)}(hAMD_PLANE_DEGAMMA_LUTh]h)}(hjJh]hAMD_PLANE_DEGAMMA_LUT}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKihjJubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_DEGAMMA_LUT_SIZEh]h)}(hjJh]hAMD_PLANE_DEGAMMA_LUT_SIZE}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKjhjJubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_DEGAMMA_TFh]h)}(hjKh]hAMD_PLANE_DEGAMMA_TF}(hj KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKkhjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_HDR_MULTh]h)}(hj Kh]hAMD_PLANE_HDR_MULT}(hj"KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKlhjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(h AMD_PLANE_CTMh]h)}(hj8Kh]h AMD_PLANE_CTM}(hj:KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKmhj6Kubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_SHAPER_LUTh]h)}(hjPKh]hAMD_PLANE_SHAPER_LUT}(hjRKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKnhjNKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_SHAPER_LUT_SIZEh]h)}(hjhKh]hAMD_PLANE_SHAPER_LUT_SIZE}(hjjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKohjfKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_SHAPER_TFh]h)}(hjKh]hAMD_PLANE_SHAPER_TF}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKphj~Kubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_LUT3Dh]h)}(hjKh]hAMD_PLANE_LUT3D}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKqhjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_LUT3D_SIZEh]h)}(hjKh]hAMD_PLANE_LUT3D_SIZE}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKrhjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_BLEND_LUTh]h)}(hjKh]hAMD_PLANE_BLEND_LUT}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKshjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_BLEND_LUT_SIZEh]h)}(hjKh]hAMD_PLANE_BLEND_LUT_SIZE}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKthjKubah}(h]h ]h"]h$]h&]uh1hhjJubh)}(hAMD_PLANE_BLEND_TF h]h)}(hAMD_PLANE_BLEND_TFh]hAMD_PLANE_BLEND_TF}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKuhjKubah}(h]h ]h"]h$]h&]uh1hhjJubeh}(h]h ]h"]h$]h&]j)j)uh1hhjJhKihjJubh)}(hEThe AMD private color management property on a :c:type:`drm_crtc` is:h](h/The AMD private color management property on a }(hjLhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjLh]hdrm_crtc}(hj!LhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_crtcuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKwhjLubh is:}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj``const struct drm_color_lut *lut`` given lut to check values h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjUh]hconst struct drm_color_lut *lut}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj)}(hhh]h)}(hgiven lut to check valuesh]hgiven lut to check values}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjUubj)}(h``uint32_t size`` lut size h](j)}(h``uint32_t size``h]j)}(hjUh]h uint32_t size}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj)}(hhh]h)}(hlut sizeh]hlut size}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjUubeh}(h]h ]h"]h$]h&]uh1jhjfUubh)}(h**Description**h]j)}(hjUh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjfUubh)}(hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)h]hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjfUubh)}(h **Return**h]j)}(hj&Vh]hReturn}(hj(VhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$Vubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjfUubh)}(hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h]hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.}(hjYhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj:Yubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjYhhhj+YhMubj')}(h;(const struct drm_color_lut32 *lut, struct dc_gamma *gamma)h](j')}(h!const struct drm_color_lut32 *luth](j)}(hj(Oh]hconst}(hjZYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVYubj)}(h h]h }(hjgYhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjVYubj)}(hj h]hstruct}(hjuYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVYubj)}(h h]h }(hjYhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjVYubh)}(hhh]j1)}(hdrm_color_lut32h]hdrm_color_lut32}(hjYhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjYubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjYmodnameN classnameNjj)}j ]j')}j'j@Ysbc.__drm_lut32_to_dc_gammaasbuh1hhjVYubj)}(h h]h }(hjYhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjVYubj')}(hj'h]h*}(hjYhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjVYubj1)}(hluth]hlut}(hjYhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjVYubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjRYubj')}(hstruct dc_gamma *gammah](j)}(hj h]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj)}(h h]h }(hjYhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjYubh)}(hhh]j1)}(hdc_gammah]hdc_gamma}(hjZhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjZubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjZmodnameN classnameNjj)}j ]jYc.__drm_lut32_to_dc_gammaasbuh1hhjYubj)}(h h]h }(hj#ZhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjYubj')}(hj'h]h*}(hj1ZhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjYubj1)}(hgammah]hgamma}(hj>ZhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjYubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjRYubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjYhhhj+YhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjYhhhj+YhMubah}(h]jYah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj+YhMhjYhhubj_)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hjhZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeZhhubah}(h]h ]h"]h$]h&]uh1j^hjYhhhj+YhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjZjjZjjjuh1jhhhj$HhNhNubj)}(h**Parameters** ``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion ``struct dc_gamma *gamma`` DC gamma to set entries **Description** The conversion depends on the size of the lut - whether or not it's legacy.h](h)}(h**Parameters**h]j)}(hjZh]h Parameters}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjZubj)}(hhh](j)}(hL``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hjZh]h!const struct drm_color_lut32 *lut}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjZubj)}(hhh]h)}(h%DRM lookup table for color conversionh]h%DRM lookup table for color conversion}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjZubj)}(h3``struct dc_gamma *gamma`` DC gamma to set entries h](j)}(h``struct dc_gamma *gamma``h]j)}(hjZh]hstruct dc_gamma *gamma}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjZubj)}(hhh]h)}(hDC gamma to set entriesh]hDC gamma to set entries}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjZubeh}(h]h ]h"]h$]h&]uh1jhjZubh)}(h**Description**h]j)}(hj[h]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjZubh)}(hKThe conversion depends on the size of the lut - whether or not it's legacy.h]hMThe conversion depends on the size of the lut - whether or not it’s legacy.}(hj3[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#__drm_ctm_to_dc_matrix (C function)c.__drm_ctm_to_dc_matrixhNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hXvoid __drm_ctm_to_dc_matrix (const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h]j)}(hWvoid __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](jZ')}(hvoidh]hvoid}(hjb[hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj^[hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjq[hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj^[hhhjp[hMubj+)}(h__drm_ctm_to_dc_matrixh]j1)}(h__drm_ctm_to_dc_matrixh]h__drm_ctm_to_dc_matrix}(hj[hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj[ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj^[hhhjp[hMubj')}(h<(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](j')}(hconst struct drm_color_ctm *ctmh](j)}(hj(Oh]hconst}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj[ubj)}(hj h]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj[ubh)}(hhh]j1)}(h drm_color_ctmh]h drm_color_ctm}(hj[hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj[modnameN classnameNjj)}j ]j')}j'j[sbc.__drm_ctm_to_dc_matrixasbuh1hhj[ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj[ubj')}(hj'h]h*}(hj\hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj[ubj1)}(hctmh]hctm}(hj\hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj[ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj[ubj')}(hstruct fixed31_32 *matrixh](j)}(hj h]hstruct}(hj,\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(\ubj)}(h h]h }(hj9\hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj(\ubh)}(hhh]j1)}(h fixed31_32h]h fixed31_32}(hjJ\hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjG\ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjL\modnameN classnameNjj)}j ]j[c.__drm_ctm_to_dc_matrixasbuh1hhj(\ubj)}(h h]h }(hjh\hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj(\ubj')}(hj'h]h*}(hjv\hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj(\ubj1)}(hmatrixh]hmatrix}(hj\hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj(\ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj[ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hj^[hhhjp[hMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjZ[hhhjp[hMubah}(h]jU[ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjp[hMhjW[hhubj_)}(hhh]h)}(h+converts a DRM CTM to a DC CSC float matrixh]h+converts a DRM CTM to a DC CSC float matrix}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\hhubah}(h]h ]h"]h$]h&]uh1j^hjW[hhhjp[hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj\jj\jjjuh1jhhhj$HhNhNubj)}(h**Parameters** ``const struct drm_color_ctm *ctm`` DRM color transformation matrix ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hj\h]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\ubj)}(hhh](j)}(hD``const struct drm_color_ctm *ctm`` DRM color transformation matrix h](j)}(h#``const struct drm_color_ctm *ctm``h]j)}(hj\h]hconst struct drm_color_ctm *ctm}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\ubj)}(hhh]h)}(hDRM color transformation matrixh]hDRM color transformation matrix}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hMhj]ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhj]hMhj\ubj)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hj']h]hstruct fixed31_32 *matrix}(hj)]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%]ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj!]ubj)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hj@]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<]hMhj=]ubah}(h]h ]h"]h$]h&]uh1jhj!]ubeh}(h]h ]h"]h$]h&]uh1jhj<]hMhj\ubeh}(h]h ]h"]h$]h&]uh1jhj\ubh)}(h**Description**h]j)}(hjb]h]h Description}(hjd]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`]ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\ubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hjx]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__drm_ctm_3x4_to_dc_matrix (C function)c.__drm_ctm_3x4_to_dc_matrixhNtauh1jhj$HhhhNhNubj)}(hhh](j)}(h`void __drm_ctm_3x4_to_dc_matrix (const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h]j)}(h_void __drm_ctm_3x4_to_dc_matrix(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](jZ')}(hvoidh]hvoid}(hj]hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj]hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj]hhhj]hM7ubj+)}(h__drm_ctm_3x4_to_dc_matrixh]j1)}(h__drm_ctm_3x4_to_dc_matrixh]h__drm_ctm_3x4_to_dc_matrix}(hj]hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj]ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj]hhhj]hM7ubj')}(h@(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](j')}(h#const struct drm_color_ctm_3x4 *ctmh](j)}(hj(Oh]hconst}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj]ubj)}(hj h]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj)}(h h]h }(hj ^hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj]ubh)}(hhh]j1)}(hdrm_color_ctm_3x4h]hdrm_color_ctm_3x4}(hj^hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj^modnameN classnameNjj)}j ]j')}j'j]sbc.__drm_ctm_3x4_to_dc_matrixasbuh1hhj]ubj)}(h h]h }(hj=^hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj]ubj')}(hj'h]h*}(hjK^hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj]ubj1)}(hctmh]hctm}(hjX^hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj]ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj]ubj')}(hstruct fixed31_32 *matrixh](j)}(hj h]hstruct}(hjq^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm^ubj)}(h h]h }(hj~^hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjm^ubh)}(hhh]j1)}(h fixed31_32h]h fixed31_32}(hj^hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj^modnameN classnameNjj)}j ]j9^c.__drm_ctm_3x4_to_dc_matrixasbuh1hhjm^ubj)}(h h]h }(hj^hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjm^ubj')}(hj'h]h*}(hj^hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjm^ubj1)}(hmatrixh]hmatrix}(hj^hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjm^ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj]ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hj]hhhj]hM7ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj]hhhj]hM7ubah}(h]j]ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj]hM7hj]hhubj_)}(hhh]h)}(h/converts a DRM CTM 3x4 to a DC CSC float matrixh]h/converts a DRM CTM 3x4 to a DC CSC float matrix}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7hj^hhubah}(h]h ]h"]h$]h&]uh1j^hj]hhhj]hM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj _jj _jjjuh1jhhhj$HhNhNubj)}(h**Parameters** ``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM;hj_ubj)}(hhh](j)}(h\``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions h](j)}(h'``const struct drm_color_ctm_3x4 *ctm``h]j)}(hj3_h]h#const struct drm_color_ctm_3x4 *ctm}(hj5_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1_ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM8hj-_ubj)}(hhh]h)}(h3DRM color transformation matrix with 3x4 dimensionsh]h3DRM color transformation matrix with 3x4 dimensions}(hjL_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH_hM8hjI_ubah}(h]h ]h"]h$]h&]uh1jhj-_ubeh}(h]h ]h"]h$]h&]uh1jhjH_hM8hj*_ubj)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hjl_h]hstruct fixed31_32 *matrix}(hjn_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj_ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM9hjf_ubj)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hM9hj_ubah}(h]h ]h"]h$]h&]uh1jhjf_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM9hj*_ubeh}(h]h ]h"]h$]h&]uh1jhj_ubh)}(h**Description**h]j)}(hj_h]h Description}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM;hj_ubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM:hj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_legacy_tf (C function)c.__set_legacy_tfhNtauh1jhj$HhhhNhNubj)}(hhh](j)}(huint __set_legacy_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_legacy_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](jZ')}(hinth]hint}(hj_hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj_hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMMubj)}(h h]h }(hj_hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj_hhhj_hMMubj+)}(h__set_legacy_tfh]j1)}(h__set_legacy_tfh]h__set_legacy_tf}(hj `hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj `ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj_hhhj_hMMubj')}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j')}(hstruct dc_transfer_func *funch](j)}(hj h]hstruct}(hj)`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%`ubj)}(h h]h }(hj6`hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj%`ubh)}(hhh]j1)}(hdc_transfer_funch]hdc_transfer_func}(hjG`hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjD`ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjI`modnameN classnameNjj)}j ]j')}j'j`sbc.__set_legacy_tfasbuh1hhj%`ubj)}(h h]h }(hjg`hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj%`ubj')}(hj'h]h*}(hju`hhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj%`ubj1)}(hfunch]hfunc}(hj`hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj%`ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj!`ubj')}(hconst struct drm_color_lut *luth](j)}(hj(Oh]hconst}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj`ubj)}(hj h]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj`ubh)}(hhh]j1)}(h drm_color_luth]h drm_color_lut}(hj`hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj`ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj`modnameN classnameNjj)}j ]jc`c.__set_legacy_tfasbuh1hhj`ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj`ubj')}(hj'h]h*}(hjahhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj`ubj1)}(hluth]hlut}(hj ahhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj`ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj!`ubj')}(huint32_t lut_sizeh](h)}(hhh]j1)}(huint32_th]huint32_t}(hj)ahhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj&aubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj+amodnameN classnameNjj)}j ]jc`c.__set_legacy_tfasbuh1hhj"aubj)}(h h]h }(hjGahhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj"aubj1)}(hlut_sizeh]hlut_size}(hjUahhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj"aubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj!`ubj')}(h bool has_romh](jZ')}(hj)Th]hbool}(hjnahhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjjaubj)}(h h]h }(hj{ahhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjjaubj1)}(hhas_romh]hhas_rom}(hjahhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjjaubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj!`ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hj_hhhj_hMMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj_hhhj_hMMubah}(h]j_ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj_hMMhj_hhubj_)}(hhh]h)}(h'Calculates the legacy transfer functionh]h'Calculates the legacy transfer function}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMMhjahhubah}(h]h ]h"]h$]h&]uh1j^hj_hhhj_hMMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjajjajjjuh1jhhhj$HhNhNubj)}(hXa**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Description** Only for sRGB input space **Return** 0 in case of success, -ENOMEM if failsh](h)}(h**Parameters**h]j)}(hjah]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMQhjaubj)}(hhh](j)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjah]hstruct dc_transfer_func *func}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMNhjaubj)}(hhh]h)}(htransfer functionh]htransfer function}(hj bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj bhMNhj bubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj bhMNhjaubj)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hj-bh]hconst struct drm_color_lut *lut}(hj/bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+bubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMOhj'bubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjFbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBbhMOhjCbubah}(h]h ]h"]h$]h&]uh1jhj'bubeh}(h]h ]h"]h$]h&]uh1jhjBbhMOhjaubj)}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjfbh]huint32_t lut_size}(hjhbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdbubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMPhj`bubj)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{bhMPhj|bubah}(h]h ]h"]h$]h&]uh1jhj`bubeh}(h]h ]h"]h$]h&]uh1jhj{bhMPhjaubj)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hjbh]h bool has_rom}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMQhjbubj)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMQhjbubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhjbhMQhjaubeh}(h]h ]h"]h$]h&]uh1jhjaubh)}(h**Description**h]j)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMShjaubh)}(hOnly for sRGB input spaceh]hOnly for sRGB input space}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMRhjaubh)}(h **Return**h]j)}(hjch]hReturn}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThjaubh)}(h&0 in case of success, -ENOMEM if failsh]h&0 in case of success, -ENOMEM if fails}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMUhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_output_tf (C function)c.__set_output_tfhNtauh1jhj$HhhhNhNubj)}(hhh](j)}(huint __set_output_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_output_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](jZ')}(hinth]hint}(hjFchhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjBchhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMuubj)}(h h]h }(hjUchhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjBchhhjTchMuubj+)}(h__set_output_tfh]j1)}(h__set_output_tfh]h__set_output_tf}(hjgchhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjccubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjBchhhjTchMuubj')}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j')}(hstruct dc_transfer_func *funch](j)}(hj h]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj)}(h h]h }(hjchhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubh)}(hhh]j1)}(hdc_transfer_funch]hdc_transfer_func}(hjchhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjcubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjcmodnameN classnameNjj)}j ]j')}j'jicsbc.__set_output_tfasbuh1hhjcubj)}(h h]h }(hjchhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubj')}(hj'h]h*}(hjchhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjcubj1)}(hfunch]hfunc}(hjchhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjcubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj{cubj')}(hconst struct drm_color_lut *luth](j)}(hj(Oh]hconst}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj)}(h h]h }(hjdhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubj)}(hj h]hstruct}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj)}(h h]h }(hjdhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubh)}(hhh]j1)}(h drm_color_luth]h drm_color_lut}(hj.dhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj+dubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj0dmodnameN classnameNjj)}j ]jcc.__set_output_tfasbuh1hhjcubj)}(h h]h }(hjLdhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubj')}(hj'h]h*}(hjZdhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjcubj1)}(hluth]hlut}(hjgdhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjcubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj{cubj')}(huint32_t lut_sizeh](h)}(hhh]j1)}(huint32_th]huint32_t}(hjdhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjdubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjdmodnameN classnameNjj)}j ]jcc.__set_output_tfasbuh1hhj|dubj)}(h h]h }(hjdhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj|dubj1)}(hlut_sizeh]hlut_size}(hjdhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj|dubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj{cubj')}(h bool has_romh](jZ')}(hj)Th]hbool}(hjdhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjdubj)}(h h]h }(hjdhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjdubj1)}(hhas_romh]hhas_rom}(hjdhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjdubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj{cubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjBchhhjTchMuubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj>chhhjTchMuubah}(h]j9cah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjTchMuhj;chhubj_)}(hhh]h)}(hFcalculates the output transfer function based on expected input space.h]hFcalculates the output transfer function based on expected input space.}(hj ehhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMuhj ehhubah}(h]h ]h"]h$]h&]uh1j^hj;chhhjTchMuubeh}(h]h ](jfunctioneh"]h$]h&]jjjj%ejj%ejjjuh1jhhhj$HhNhNubj)}(hX6**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hj/eh]h Parameters}(hj1ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-eubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMyhj)eubj)}(hhh](j)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjNeh]hstruct dc_transfer_func *func}(hjPehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLeubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMvhjHeubj)}(hhh]h)}(htransfer functionh]htransfer function}(hjgehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcehMvhjdeubah}(h]h ]h"]h$]h&]uh1jhjHeubeh}(h]h ]h"]h$]h&]uh1jhjcehMvhjEeubj)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjeh]hconst struct drm_color_lut *lut}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMwhjeubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMwhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjehMwhjEeubj)}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjeh]huint32_t lut_size}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMxhjeubj)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMxhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjehMxhjEeubj)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hjeh]h bool has_rom}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMyhjeubj)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMyhjfubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjfhMyhjEeubeh}(h]h ]h"]h$]h&]uh1jhj)eubh)}(h **Return**h]j)}(hj4fh]hReturn}(hj6fhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2fubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM{hj)eubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjJfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM{hj)eubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_output_tf_32 (C function)c.__set_output_tf_32hNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hzint __set_output_tf_32 (struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h]j)}(hyint __set_output_tf_32(struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h](jZ')}(hinth]hint}(hjyfhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjufhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjfhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjufhhhjfhMubj+)}(h__set_output_tf_32h]j1)}(h__set_output_tf_32h]h__set_output_tf_32}(hjfhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjfubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjufhhhjfhMubj')}(hc(struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h](j')}(hstruct dc_transfer_func *funch](j)}(hj h]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj)}(h h]h }(hjfhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjfubh)}(hhh]j1)}(hdc_transfer_funch]hdc_transfer_func}(hjfhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjfubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjfmodnameN classnameNjj)}j ]j')}j'jfsbc.__set_output_tf_32asbuh1hhjfubj)}(h h]h }(hjfhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjfubj')}(hj'h]h*}(hjghhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjfubj1)}(hfunch]hfunc}(hjghhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjfubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjfubj')}(h!const struct drm_color_lut32 *luth](j)}(hj(Oh]hconst}(hj(ghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$gubj)}(h h]h }(hj5ghhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj$gubj)}(hj h]hstruct}(hjCghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$gubj)}(h h]h }(hjPghhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj$gubh)}(hhh]j1)}(hdrm_color_lut32h]hdrm_color_lut32}(hjaghhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj^gubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjcgmodnameN classnameNjj)}j ]jfc.__set_output_tf_32asbuh1hhj$gubj)}(h h]h }(hjghhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj$gubj')}(hj'h]h*}(hjghhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj$gubj1)}(hluth]hlut}(hjghhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj$gubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjfubj')}(huint32_t lut_sizeh](h)}(hhh]j1)}(huint32_th]huint32_t}(hjghhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjgubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjgmodnameN classnameNjj)}j ]jfc.__set_output_tf_32asbuh1hhjgubj)}(h h]h }(hjghhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjgubj1)}(hlut_sizeh]hlut_size}(hjghhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjgubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjfubj')}(h bool has_romh](jZ')}(hj)Th]hbool}(hjghhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjgubj)}(h h]h }(hjhhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjgubj1)}(hhas_romh]hhas_rom}(hjhhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjgubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjfubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjufhhhjfhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjqfhhhjfhMubah}(h]jlfah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjfhMhjnfhhubj_)}(hhh]h)}(hFcalculates the output transfer function based on expected input space.h]hFcalculates the output transfer function based on expected input space.}(hj@hhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj=hhhubah}(h]h ]h"]h$]h&]uh1j^hjnfhhhjfhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjXhjjXhjjjuh1jhhhj$HhNhNubj)}(hX8**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut32 *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjbhh]h Parameters}(hjdhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`hubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\hubj)}(hhh](j)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjhh]hstruct dc_transfer_func *func}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{hubj)}(hhh]h)}(htransfer functionh]htransfer function}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjhubah}(h]h ]h"]h$]h&]uh1jhj{hubeh}(h]h ]h"]h$]h&]uh1jhjhhMhjxhubj)}(hP``const struct drm_color_lut32 *lut`` lookup table that defines the color space h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hjhh]h!const struct drm_color_lut32 *lut}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjhubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjhubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjhhMhjxhubj)}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjhh]huint32_t lut_size}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjhubj)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hj ihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMhj iubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjihMhjxhubj)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hj,ih]h bool has_rom}(hj.ihhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*iubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj&iubj)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjEihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAihMhjBiubah}(h]h ]h"]h$]h&]uh1jhj&iubeh}(h]h ]h"]h$]h&]uh1jhjAihMhjxhubeh}(h]h ]h"]h$]h&]uh1jhj\hubh)}(h **Return**h]j)}(hjgih]hReturn}(hjiihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeiubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\hubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hj}ihhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\hubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_input_tf (C function)c.__set_input_tfhNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hint __set_input_tf (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h]j)}(hint __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](jZ')}(hinth]hint}(hjihhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjihhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM ubj)}(h h]h }(hjihhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjihhhjihM ubj+)}(h__set_input_tfh]j1)}(h__set_input_tfh]h__set_input_tf}(hjihhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjiubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjihhhjihM ubj')}(ho(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](j')}(hstruct dc_color_caps *capsh](j)}(hj h]hstruct}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj)}(h h]h }(hjihhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjiubh)}(hhh]j1)}(h dc_color_capsh]h dc_color_caps}(hjjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjjubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj jmodnameN classnameNjj)}j ]j')}j'jisbc.__set_input_tfasbuh1hhjiubj)}(h h]h }(hj'jhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjiubj')}(hj'h]h*}(hj5jhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjiubj1)}(hcapsh]hcaps}(hjBjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjiubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjiubj')}(hstruct dc_transfer_func *funch](j)}(hj h]hstruct}(hj[jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWjubj)}(h h]h }(hjhjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjWjubh)}(hhh]j1)}(hdc_transfer_funch]hdc_transfer_func}(hjyjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjvjubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj{jmodnameN classnameNjj)}j ]j#jc.__set_input_tfasbuh1hhjWjubj)}(h h]h }(hjjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjWjubj')}(hj'h]h*}(hjjhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjWjubj1)}(hfunch]hfunc}(hjjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjWjubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjiubj')}(hconst struct drm_color_lut *luth](j)}(hj(Oh]hconst}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj)}(h h]h }(hjjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjjubj)}(hj h]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj)}(h h]h }(hjjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjjubh)}(hhh]j1)}(h drm_color_luth]h drm_color_lut}(hjkhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjkubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjkmodnameN classnameNjj)}j ]j#jc.__set_input_tfasbuh1hhjjubj)}(h h]h }(hj"khhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjjubj')}(hj'h]h*}(hj0khhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjjubj1)}(hluth]hlut}(hj=khhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjjubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjiubj')}(huint32_t lut_sizeh](h)}(hhh]j1)}(huint32_th]huint32_t}(hjYkhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjVkubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj[kmodnameN classnameNjj)}j ]j#jc.__set_input_tfasbuh1hhjRkubj)}(h h]h }(hjwkhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjRkubj1)}(hlut_sizeh]hlut_size}(hjkhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjRkubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjiubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjihhhjihM ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjihhhjihM ubah}(h]jiah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjihM hjihhubj_)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjkhhubah}(h]h ]h"]h$]h&]uh1j^hjihhhjihM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjkjjkjjjuh1jhhhj$HhNhNubj)}(hX4**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjkh]h Parameters}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjkubj)}(hhh](j)}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hjkh]hstruct dc_color_caps *caps}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjkubj)}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hj lhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjlhMhjkubj)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hj)lh]hstruct dc_transfer_func *func}(hj+lhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'lubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj#lubj)}(hhh]h)}(htransfer functionh]htransfer function}(hjBlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>lhMhj?lubah}(h]h ]h"]h$]h&]uh1jhj#lubeh}(h]h ]h"]h$]h&]uh1jhj>lhMhjkubj)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjblh]hconst struct drm_color_lut *lut}(hjdlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`lubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\lubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hj{lhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwlhMhjxlubah}(h]h ]h"]h$]h&]uh1jhj\lubeh}(h]h ]h"]h$]h&]uh1jhjwlhMhjkubj)}(h.``uint32_t lut_size`` size of respective lut. h](j)}(h``uint32_t lut_size``h]j)}(hjlh]huint32_t lut_size}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjlubj)}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMhjkubeh}(h]h ]h"]h$]h&]uh1jhjkubh)}(h **Return**h]j)}(hjlh]hReturn}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjkubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjkubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_input_tf_32 (C function)c.__set_input_tf_32hNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hint __set_input_tf_32 (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h]j)}(hint __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h](jZ')}(hinth]hint}(hjmhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjmhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM0ubj)}(h h]h }(hj*mhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjmhhhj)mhM0ubj+)}(h__set_input_tf_32h]j1)}(h__set_input_tf_32h]h__set_input_tf_32}(hjmsbc.__set_input_tf_32asbuh1hhjTmubj)}(h h]h }(hjmhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjTmubj')}(hj'h]h*}(hjmhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjTmubj1)}(hcapsh]hcaps}(hjmhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjTmubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjPmubj')}(hstruct dc_transfer_func *funch](j)}(hj h]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(h h]h }(hjmhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjmubh)}(hhh]j1)}(hdc_transfer_funch]hdc_transfer_func}(hjmhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjmubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjmmodnameN classnameNjj)}j ]jmc.__set_input_tf_32asbuh1hhjmubj)}(h h]h }(hjnhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjmubj')}(hj'h]h*}(hjnhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjmubj1)}(hfunch]hfunc}(hj!nhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjmubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjPmubj')}(h!const struct drm_color_lut32 *luth](j)}(hj(Oh]hconst}(hj:nhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6nubj)}(h h]h }(hjGnhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj6nubj)}(hj h]hstruct}(hjUnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6nubj)}(h h]h }(hjbnhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj6nubh)}(hhh]j1)}(hdrm_color_lut32h]hdrm_color_lut32}(hjsnhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjpnubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjunmodnameN classnameNjj)}j ]jmc.__set_input_tf_32asbuh1hhj6nubj)}(h h]h }(hjnhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj6nubj')}(hj'h]h*}(hjnhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj6nubj1)}(hluth]hlut}(hjnhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj6nubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjPmubj')}(huint32_t lut_sizeh](h)}(hhh]j1)}(huint32_th]huint32_t}(hjnhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjnubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjnmodnameN classnameNjj)}j ]jmc.__set_input_tf_32asbuh1hhjnubj)}(h h]h }(hjnhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjnubj1)}(hlut_sizeh]hlut_size}(hjnhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjnubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjPmubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjmhhhj)mhM0ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjmhhhj)mhM0ubah}(h]jmah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj)mhM0hjmhhubj_)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM0hjohhubah}(h]h ]h"]h$]h&]uh1j^hjmhhhj)mhM0ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6ojj6ojjjuh1jhhhj$HhNhNubj)}(hX6**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut32 *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hj@oh]h Parameters}(hjBohhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>oubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM4hj:oubj)}(hhh](j)}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hj_oh]hstruct dc_color_caps *caps}(hjaohhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]oubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM2hjYoubj)}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hjxohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjtohM2hjuoubah}(h]h ]h"]h$]h&]uh1jhjYoubeh}(h]h ]h"]h$]h&]uh1jhjtohM2hjVoubj)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjoh]hstruct dc_transfer_func *func}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM3hjoubj)}(hhh]h)}(htransfer functionh]htransfer function}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohM3hjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjohM3hjVoubj)}(hP``const struct drm_color_lut32 *lut`` lookup table that defines the color space h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hjoh]h!const struct drm_color_lut32 *lut}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM4hjoubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohM4hjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjohM4hjVoubj)}(h.``uint32_t lut_size`` size of respective lut. h](j)}(h``uint32_t lut_size``h]j)}(hj ph]huint32_t lut_size}(hj phhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM5hjpubj)}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hj#phhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphM5hj pubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jhjphM5hjVoubeh}(h]h ]h"]h$]h&]uh1jhj:oubh)}(h **Return**h]j)}(hjEph]hReturn}(hjGphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCpubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7hj:oubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hj[phhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7hj:oubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(amdgpu_dm_verify_lut3d_size (C function)c.amdgpu_dm_verify_lut3d_sizehNtauh1jhj$HhhhNhNubj)}(hhh](j)}(haint amdgpu_dm_verify_lut3d_size (struct amdgpu_device *adev, struct drm_plane_state *plane_state)h]j)}(h`int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](jZ')}(hinth]hint}(hjphhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjphhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMBubj)}(h h]h }(hjphhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjphhhjphMBubj+)}(hamdgpu_dm_verify_lut3d_sizeh]j1)}(hamdgpu_dm_verify_lut3d_sizeh]hamdgpu_dm_verify_lut3d_size}(hjphhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjpubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjphhhjphMBubj')}(hA(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](j')}(hstruct amdgpu_device *adevh](j)}(hj h]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj)}(h h]h }(hjphhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjpubh)}(hhh]j1)}(h amdgpu_deviceh]h amdgpu_device}(hjphhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjpubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjpmodnameN classnameNjj)}j ]j')}j'jpsbc.amdgpu_dm_verify_lut3d_sizeasbuh1hhjpubj)}(h h]h }(hjqhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjpubj')}(hj'h]h*}(hjqhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjpubj1)}(hadevh]hadev}(hj qhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjpubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjpubj')}(h#struct drm_plane_state *plane_stateh](j)}(hj h]hstruct}(hj9qhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5qubj)}(h h]h }(hjFqhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj5qubh)}(hhh]j1)}(hdrm_plane_stateh]hdrm_plane_state}(hjWqhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjTqubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjYqmodnameN classnameNjj)}j ]jqc.amdgpu_dm_verify_lut3d_sizeasbuh1hhj5qubj)}(h h]h }(hjuqhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj5qubj')}(hj'h]h*}(hjqhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj5qubj1)}(h plane_stateh]h plane_state}(hjqhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj5qubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjpubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjphhhjphMBubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjphhhjphMBubah}(h]j}pah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjphMBhjphhubj_)}(hhh]h)}(hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported sizeh]hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported size}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMBhjqhhubah}(h]h ]h"]h$]h&]uh1j^hjphhhjphMBubeh}(h]h ](jfunctioneh"]h$]h&]jjjjqjjqjjjuh1jhhhj$HhNhNubj)}(hXX**Parameters** ``struct amdgpu_device *adev`` amdgpu device ``struct drm_plane_state *plane_state`` the DRM plane state **Description** Verifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size. **Return** 0 on success. -EINVAL if lut size are invalid.h](h)}(h**Parameters**h]j)}(hjqh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMFhjqubj)}(hhh](j)}(h-``struct amdgpu_device *adev`` amdgpu device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjqh]hstruct amdgpu_device *adev}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMDhjqubj)}(hhh]h)}(h amdgpu deviceh]h amdgpu device}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMDhjrubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjrhMDhjqubj)}(h<``struct drm_plane_state *plane_state`` the DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hj4rh]h#struct drm_plane_state *plane_state}(hj6rhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2rubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMEhj.rubj)}(hhh]h)}(hthe DRM plane stateh]hthe DRM plane state}(hjMrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIrhMEhjJrubah}(h]h ]h"]h$]h&]uh1jhj.rubeh}(h]h ]h"]h$]h&]uh1jhjIrhMEhjqubeh}(h]h ]h"]h$]h&]uh1jhjqubh)}(h**Description**h]j)}(hjorh]h Description}(hjqrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmrubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMGhjqubh)}(hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.h]hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMFhjqubh)}(h **Return**h]j)}(hjrh]hReturn}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMIhjqubh)}(h.0 on success. -EINVAL if lut size are invalid.h]h.0 on success. -EINVAL if lut size are invalid.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMJhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_verify_lut_sizes (C function)c.amdgpu_dm_verify_lut_sizeshNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hHint amdgpu_dm_verify_lut_sizes (const struct drm_crtc_state *crtc_state)h]j)}(hGint amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)h](jZ')}(hinth]hint}(hjrhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjrhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMoubj)}(h h]h }(hjrhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjrhhhjrhMoubj+)}(hamdgpu_dm_verify_lut_sizesh]j1)}(hamdgpu_dm_verify_lut_sizesh]hamdgpu_dm_verify_lut_sizes}(hjrhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjrubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjrhhhjrhMoubj')}(h)(const struct drm_crtc_state *crtc_state)h]j')}(h'const struct drm_crtc_state *crtc_stateh](j)}(hj(Oh]hconst}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(h h]h }(hj%shhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjsubj)}(hj h]hstruct}(hj3shhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubj)}(h h]h }(hj@shhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjsubh)}(hhh]j1)}(hdrm_crtc_stateh]hdrm_crtc_state}(hjQshhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjNsubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjSsmodnameN classnameNjj)}j ]j')}j'jrsbc.amdgpu_dm_verify_lut_sizesasbuh1hhjsubj)}(h h]h }(hjqshhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjsubj')}(hj'h]h*}(hjshhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjsubj1)}(h crtc_stateh]h crtc_state}(hjshhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjsubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjsubah}(h]h ]h"]h$]h&]jHjIuh1j'hjrhhhjrhMoubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjrhhhjrhMoubah}(h]jrah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjrhMohjrhhubj_)}(hhh]h)}(h1verifies if DRM luts match the hw supported sizesh]h1verifies if DRM luts match the hw supported sizes}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMohjshhubah}(h]h ]h"]h$]h&]uh1j^hjrhhhjrhMoubeh}(h]h ](jfunctioneh"]h$]h&]jjjjsjjsjjjuh1jhhhj$HhNhNubj)}(hX **Parameters** ``const struct drm_crtc_state *crtc_state`` the DRM CRTC state **Description** Verifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size. **Return** 0 on success. -EINVAL if any lut sizes are invalid.h](h)}(h**Parameters**h]j)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMshjsubj)}(hhh]j)}(h?``const struct drm_crtc_state *crtc_state`` the DRM CRTC state h](j)}(h+``const struct drm_crtc_state *crtc_state``h]j)}(hjsh]h'const struct drm_crtc_state *crtc_state}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMphjsubj)}(hhh]h)}(hthe DRM CRTC stateh]hthe DRM CRTC state}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhj thMphj tubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhj thMphjsubah}(h]h ]h"]h$]h&]uh1jhjsubh)}(h**Description**h]j)}(hj2th]h Description}(hj4thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0tubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMrhjsubh)}(hgVerifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size.h](h9Verifies that the Degamma and Gamma LUTs attached to the }(hjHthhhNhNubh)}(h:c:type:`crtc_state`h]j)}(hjRth]h crtc_state}(hjTthhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjPtubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj crtc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMqhjHtubh are of the expected size.}(hjHthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjothMqhjsubh)}(h **Return**h]j)}(hj|th]hReturn}(hj~thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjztubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMthjsubh)}(h30 on success. -EINVAL if any lut sizes are invalid.h]h30 on success. -EINVAL if any lut sizes are invalid.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMuhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,amdgpu_dm_check_crtc_color_mgmt (C function)!c.amdgpu_dm_check_crtc_color_mgmthNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hQint amdgpu_dm_check_crtc_color_mgmt (struct dm_crtc_state *crtc, bool check_only)h]j)}(hPint amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, bool check_only)h](jZ')}(hinth]hint}(hjthhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjthhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjthhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjthhhjthMubj+)}(hamdgpu_dm_check_crtc_color_mgmth]j1)}(hamdgpu_dm_check_crtc_color_mgmth]hamdgpu_dm_check_crtc_color_mgmt}(hjthhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjtubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjthhhjthMubj')}(h-(struct dm_crtc_state *crtc, bool check_only)h](j')}(hstruct dm_crtc_state *crtch](j)}(hj h]hstruct}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj)}(h h]h }(hj uhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjtubh)}(hhh]j1)}(h dm_crtc_stateh]h dm_crtc_state}(hjuhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjuubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjumodnameN classnameNjj)}j ]j')}j'jtsb!c.amdgpu_dm_check_crtc_color_mgmtasbuh1hhjtubj)}(h h]h }(hjwhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj-wubh)}(hhh]j1)}(h dm_crtc_stateh]h dm_crtc_state}(hjOwhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjLwubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjQwmodnameN classnameNjj)}j ]j')}j'jwsb"c.amdgpu_dm_update_crtc_color_mgmtasbuh1hhj-wubj)}(h h]h }(hjowhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj-wubj')}(hj'h]h*}(hj}whhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj-wubj1)}(hcrtch]hcrtc}(hjwhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj-wubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj)wubah}(h]h ]h"]h$]h&]jHjIuh1j'hjvhhhjwhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjvhhhjwhMubah}(h]jvah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjwhMhjvhhubj_)}(hhh]h)}(h'Maps DRM color management to DC stream.h]h'Maps DRM color management to DC stream.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwhhubah}(h]h ]h"]h$]h&]uh1j^hjvhhhjwhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjwjjwjjjuh1jhhhj$HhNhNubj)}(hXO**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state **Description** With no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM. - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. - The CRTC CTM will be placed in the gamut remap block if it is non-linear. The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM. For supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together. **Return** 0 on success. Error code if setup fails.h](h)}(h**Parameters**h]j)}(hjwh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubj)}(hhh]j)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hjwh]hstruct dm_crtc_state *crtc}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubj)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj xhMhj xubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhj xhMhjwubah}(h]h ]h"]h$]h&]uh1jhjwubh)}(h**Description**h]j)}(hj0xh]h Description}(hj2xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.xubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubh)}(hWith no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.h]hWith no plane level color management properties we’re free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.}(hjFxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubh)}(hhh](h)}(hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.h]h)}(hjZxh]hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.}(hj\xhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjXxubah}(h]h ]h"]h$]h&]uh1hhjUxubh)}(hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.h]h)}(hjrxh]hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.}(hjtxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjpxubah}(h]h ]h"]h$]h&]uh1hhjUxubh)}(hJThe CRTC CTM will be placed in the gamut remap block if it is non-linear. h]h)}(hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.h]hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjxubah}(h]h ]h"]h$]h&]uh1hhjUxubeh}(h]h ]h"]h$]h&]j)j)uh1hhjixhMhjwubh)}(h~The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM.h]hThe RGM block is typically more fully featured and accurate across all ASICs - DCE can’t support a custom non-linear CRTC DGM.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubh)}(hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.h]hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjwubh)}(h **Return**h]j)}(hjxh]hReturn}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubh)}(h(0 on success. Error code if setup fails.h]h(0 on success. Error code if setup fails.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.amdgpu_dm_update_plane_color_mgmt (C function)#c.amdgpu_dm_update_plane_color_mgmthNtauh1jhj$HhhhNhNubj)}(hhh](j)}(hint amdgpu_dm_update_plane_color_mgmt (struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h]j)}(hint amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](jZ')}(hinth]hint}(hj yhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjyhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjyhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjyhhhjyhMubj+)}(h!amdgpu_dm_update_plane_color_mgmth]j1)}(h!amdgpu_dm_update_plane_color_mgmth]h!amdgpu_dm_update_plane_color_mgmt}(hj-yhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj)yubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjyhhhjyhMubj')}(hh(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](j')}(hstruct dm_crtc_state *crtch](j)}(hj h]hstruct}(hjIyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEyubj)}(h h]h }(hjVyhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjEyubh)}(hhh]j1)}(h dm_crtc_stateh]h dm_crtc_state}(hjgyhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjdyubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjiymodnameN classnameNjj)}j ]j')}j'j/ysb#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhjEyubj)}(h h]h }(hjyhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjEyubj')}(hj'h]h*}(hjyhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjEyubj1)}(hcrtch]hcrtc}(hjyhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjEyubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjAyubj')}(h#struct drm_plane_state *plane_stateh](j)}(hj h]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj)}(h h]h }(hjyhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjyubh)}(hhh]j1)}(hdrm_plane_stateh]hdrm_plane_state}(hjyhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjyubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjymodnameN classnameNjj)}j ]jy#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhjyubj)}(h h]h }(hjyhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjyubj')}(hj'h]h*}(hjzhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjyubj1)}(h plane_stateh]h plane_state}(hjzhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjyubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjAyubj')}(h%struct dc_plane_state *dc_plane_stateh](j)}(hj h]hstruct}(hj+zhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'zubj)}(h h]h }(hj8zhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj'zubh)}(hhh]j1)}(hdc_plane_stateh]hdc_plane_state}(hjIzhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjFzubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjKzmodnameN classnameNjj)}j ]jy#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhj'zubj)}(h h]h }(hjgzhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj'zubj')}(hj'h]h*}(hjuzhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj'zubj1)}(hdc_plane_stateh]hdc_plane_state}(hjzhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj'zubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjAyubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjyhhhjyhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjyhhhjyhMubah}(h]jxah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjyhMhjyhhubj_)}(hhh]h)}(h&Maps DRM color management to DC plane.h]h&Maps DRM color management to DC plane.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzhhubah}(h]h ]h"]h$]h&]uh1j^hjyhhhjyhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjzjjzjjjuh1jhhhj$HhNhNubj)}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``struct drm_plane_state *plane_state`` DRM plane state ``struct dc_plane_state *dc_plane_state`` target DC surface **Description** Update the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management. **Return** 0 on success. -ENOMEM if mem allocation fails.h](h)}(h**Parameters**h]j)}(hjzh]h Parameters}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubj)}(hhh](j)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hjzh]hstruct dm_crtc_state *crtc}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubj)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj{ubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjzubj)}(h8``struct drm_plane_state *plane_state`` DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hj&{h]h#struct drm_plane_state *plane_state}(hj({hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj${ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj {ubj)}(hhh]h)}(hDRM plane stateh]hDRM plane state}(hj?{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;{hMhj<{ubah}(h]h ]h"]h$]h&]uh1jhj {ubeh}(h]h ]h"]h$]h&]uh1jhj;{hMhjzubj)}(h<``struct dc_plane_state *dc_plane_state`` target DC surface h](j)}(h)``struct dc_plane_state *dc_plane_state``h]j)}(hj_{h]h%struct dc_plane_state *dc_plane_state}(hja{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]{ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjY{ubj)}(hhh]h)}(htarget DC surfaceh]htarget DC surface}(hjx{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt{hMhju{ubah}(h]h ]h"]h$]h&]uh1jhjY{ubeh}(h]h ]h"]h$]h&]uh1jhjt{hMhjzubeh}(h]h ]h"]h$]h&]uh1jhjzubh)}(h**Description**h]j)}(hj{h]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubh)}(hUpdate the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.h]hUpdate the underlying dc_stream_state’s input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubh)}(h **Return**h]j)}(hj{h]hReturn}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubh)}(h.0 on success. -ENOMEM if mem allocation fails.h]h.0 on success. -ENOMEM if mem allocation fails.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj$HhhhNhNubh)}(hhh](h)}(h-DC Color Capabilities between DCN generationsh]h-DC Color Capabilities between DCN generations}(hj{hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj{hhhhhK7ubh)}(hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.h]hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hj{hhubh)}(hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.h]hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj{hhubh)}(h'**Color management caps (DPP and MPC)**h]j)}(hj|h]h#Color management caps (DPP and MPC)}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj{hhubh)}(hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.h]hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.}(hj2|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj{hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_SURFACES (C macro)c.MAX_SURFACEShNtauh1jhj{hhhNhNubj)}(hhh](j)}(h MAX_SURFACESh]j)}(h MAX_SURFACESh]j+)}(h MAX_SURFACESh]j1)}(hjT|h]h MAX_SURFACES}(hj^|hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjZ|ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjV|hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKEubah}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjR|hhhjq|hKEubah}(h]jM|ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjq|hKEhjO|hhubj_)}(hhh]h}(h]h ]h"]h$]h&]uh1j^hjO|hhhjq|hKEubeh}(h]h ](jmacroeh"]h$]h&]jjjj|jj|jjjuh1jhhhj{hNhNubh)}(h``MAX_SURFACES``h]j)}(hj|h]h MAX_SURFACES}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKGhj{hhubh block_quote)}(hRrepresentative of the upper bound of surfaces that can be piped to a single CRTC h]h)}(hPrepresentative of the upper bound of surfaces that can be piped to a single CRTCh]hPrepresentative of the upper bound of surfaces that can be piped to a single CRTC}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKEhj|ubah}(h]h ]h"]h$]h&]uh1j|hj|hKEhj{hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_PLANES (C macro) c.MAX_PLANEShNtauh1jhj{hhhNhNubj)}(hhh](j)}(h MAX_PLANESh]j)}(h MAX_PLANESh]j+)}(h MAX_PLANESh]j1)}(hj|h]h MAX_PLANES}(hj|hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj|ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj|hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKIubah}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj|hhhj|hKIubah}(h]j|ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj|hKIhj|hhubj_)}(hhh]h}(h]h ]h"]h$]h&]uh1j^hj|hhhj|hKIubeh}(h]h ](jmacroeh"]h$]h&]jjjj }jj }jjjuh1jhhhj{hNhNubh)}(h``MAX_PLANES``h]j)}(hj}h]h MAX_PLANES}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKKhj{hhubj|)}(hLrepresentative of the upper bound of planes that are supported by the HW h]h)}(hHrepresentative of the upper bound of planes that are supported by the HWh]hHrepresentative of the upper bound of planes that are supported by the HW}(hj*}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKIhj&}ubah}(h]h ]h"]h$]h&]uh1j|hj8}hKIhj{hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jrom_curve_caps (C struct)c.rom_curve_capshNtauh1jhj{hhhNhNubj)}(hhh](j)}(hrom_curve_capsh]j)}(hstruct rom_curve_capsh](j)}(hj h]hstruct}(hjX}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjT}hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKNubj)}(h h]h }(hjf}hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjT}hhhje}hKNubj+)}(hrom_curve_capsh]j1)}(hjR}h]hrom_curve_caps}(hjx}hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjt}ubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjT}hhhje}hKNubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjP}hhhje}hKNubah}(h]jK}ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhje}hKNhjM}hhubj_)}(hhh]h)}(h9predefined transfer function caps for degamma and regammah]h9predefined transfer function caps for degamma and regamma}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj}hhubah}(h]h ]h"]h$]h&]uh1j^hjM}hhhje}hKNubeh}(h]h ](jstructeh"]h$]h&]jjjj}jj}jjjuh1jhhhj{hNhNubj)}(hX**Definition**:: struct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; }; **Members** ``srgb`` RGB color space transfer func ``bt2020`` BT.2020 transfer func ``gamma2_2`` standard gamma ``pq`` perceptual quantizer transfer function ``hlg`` hybrid log–gamma transfer functionh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh:}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj}ubj)}(hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };h]hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };}hj}sbah}(h]h ]h"]h$]h&]jHjIuh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj}ubh)}(h **Members**h]j)}(hj}h]hMembers}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj}ubj)}(hhh](j)}(h'``srgb`` RGB color space transfer func h](j)}(h``srgb``h]j)}(hj~h]hsrgb}(hj ~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj~ubj)}(hhh]h)}(hRGB color space transfer funch]hRGB color space transfer func}(hj ~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hKhj}ubj)}(h!``bt2020`` BT.2020 transfer func h](j)}(h ``bt2020``h]j)}(hj@~h]hbt2020}(hjB~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>~ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj:~ubj)}(hhh]h)}(hBT.2020 transfer funch]hBT.2020 transfer func}(hjY~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU~hKhjV~ubah}(h]h ]h"]h$]h&]uh1jhj:~ubeh}(h]h ]h"]h$]h&]uh1jhjU~hKhj}ubj)}(h``gamma2_2`` standard gamma h](j)}(h ``gamma2_2``h]j)}(hjy~h]hgamma2_2}(hj{~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw~ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjs~ubj)}(hhh]h)}(hstandard gammah]hstandard gamma}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhj~ubah}(h]h ]h"]h$]h&]uh1jhjs~ubeh}(h]h ]h"]h$]h&]uh1jhj~hKhj}ubj)}(h.``pq`` perceptual quantizer transfer function h](j)}(h``pq``h]j)}(hj~h]hpq}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj~ubj)}(hhh]h)}(h&perceptual quantizer transfer functionh]h&perceptual quantizer transfer function}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hKhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hKhj}ubj)}(h,``hlg`` hybrid log–gamma transfer functionh](j)}(h``hlg``h]j)}(hj~h]hhlg}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj~ubj)}(hhh]h)}(h$hybrid log–gamma transfer functionh]h$hybrid log–gamma transfer function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj}ubeh}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpp_color_caps (C struct)c.dpp_color_capshNtauh1jhj{hhhNhNubj)}(hhh](j)}(hdpp_color_capsh]j)}(hstruct dpp_color_capsh](j)}(hj h]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKubj)}(h h]h }(hjShhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjAhhhjRhKubj+)}(hdpp_color_capsh]j1)}(hj?h]hdpp_color_caps}(hjehhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjaubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjAhhhjRhKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj=hhhjRhKubah}(h]j8ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjRhKhj:hhubj_)}(hhh]h)}(h=color pipeline capabilities for display pipe and plane blocksh]h=color pipeline capabilities for display pipe and plane blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1j^hj:hhhjRhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhj{hNhNubj)}(hX**Definition**:: struct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; }; **Members** ``dcn_arch`` all DCE generations treated the same ``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup ``icsc`` input color space conversion ``dgam_ram`` programmable degamma LUT ``post_csc`` post color space conversion, before gamut remap ``gamma_corr`` degamma correction ``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag ``ogam_ram`` programmable out/blend gamma LUT ``ocsc`` output color space conversion ``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes ``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };h]hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh](j)}(h2``dcn_arch`` all DCE generations treated the same h](j)}(h ``dcn_arch``h]j)}(hjh]hdcn_arch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h$all DCE generations treated the sameh]h$all DCE generations treated the same}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(hj``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup h](j)}(h``input_lut_shared``h]j)}(hj-h]hinput_lut_shared}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj'ubj)}(hhh]h)}(hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookuph]hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhKhjubj)}(h&``icsc`` input color space conversion h](j)}(h``icsc``h]j)}(hjgh]hicsc}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjaubj)}(hhh]h)}(hinput color space conversionh]hinput color space conversion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hKhj}ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hKhjubj)}(h&``dgam_ram`` programmable degamma LUT h](j)}(h ``dgam_ram``h]j)}(hjh]hdgam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(hprogrammable degamma LUTh]hprogrammable degamma LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h=``post_csc`` post color space conversion, before gamut remap h](j)}(h ``post_csc``h]j)}(hjـh]hpost_csc}(hjۀhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj׀ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjӀubj)}(hhh]h)}(h/post color space conversion, before gamut remaph]h/post color space conversion, before gamut remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjӀubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h"``gamma_corr`` degamma correction h](j)}(h``gamma_corr``h]j)}(hjh]h gamma_corr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj ubj)}(hhh]h)}(hdegamma correctionh]hdegamma correction}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hKhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj'hKhjubj)}(hz``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag h](j)}(h ``hw_3d_lut``h]j)}(hjKh]h hw_3d_lut}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjEubj)}(hhh]h)}(hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flagh]hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhj`hKhjubj)}(h.``ogam_ram`` programmable out/blend gamma LUT h](j)}(h ``ogam_ram``h]j)}(hjh]hogam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h programmable out/blend gamma LUTh]h programmable out/blend gamma LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h'``ocsc`` output color space conversion h](j)}(h``ocsc``h]j)}(hjh]hocsc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(houtput color space conversionh]houtput color space conversion}(hjׁhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjӁhKhjԁubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjӁhKhjubj)}(h<``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes h](j)}(h``dgam_rom_for_yuv``h]j)}(hjh]hdgam_rom_for_yuv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h&pre-defined degamma LUT for YUV planesh]h&pre-defined degamma LUT for YUV planes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(h=``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT h](j)}(h``dgam_rom_caps``h]j)}(hj0h]h dgam_rom_caps}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj*ubj)}(hhh]h)}(h*pre-definied curve caps for degamma 1D LUTh]h*pre-definied curve caps for degamma 1D LUT}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhKhjubj)}(h<``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](j)}(h``ogam_rom_caps``h]j)}(hjih]h ogam_rom_caps}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjcubj)}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhj~hKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj{hhubh)}(hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)h]hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)}(hj‚hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj{hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_color_caps (C struct)c.mpc_color_capshNtauh1jhj{hhhNhNubj)}(hhh](j)}(hmpc_color_capsh]j)}(hstruct mpc_color_capsh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjhKubj+)}(hmpc_color_capsh]j1)}(hjh]hmpc_color_caps}(hj hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjhKubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjhKubah}(h]j݂ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjhKhj߂hhubj_)}(hhh]h)}(hGcolor pipeline capabilities for multiple pipe and plane combined blocksh]hGcolor pipeline capabilities for multiple pipe and plane combined blocks}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj)hhubah}(h]h ]h"]h$]h&]uh1j^hj߂hhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjDjjDjjjuh1jhhhj{hNhNubj)}(hX**Definition**:: struct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; }; **Members** ``gamut_remap`` color transformation matrix ``ogam_ram`` programmable out gamma LUT ``ocsc`` output color space conversion matrix ``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT ``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT ``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT ``mcm_3d_lut_caps`` HW support cap for MCM LUT memory ``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory ``preblend`` whether color manager supports preblend with MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubh:}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjHubj)}(hXRstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; };h]hXRstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; };}hjisbah}(h]h ]h"]h$]h&]jHjIuh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjHubh)}(h **Members**h]j)}(hjzh]hMembers}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjHubj)}(hhh](j)}(h,``gamut_remap`` color transformation matrix h](j)}(h``gamut_remap``h]j)}(hjh]h gamut_remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(hcolor transformation matrixh]hcolor transformation matrix}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h(``ogam_ram`` programmable out gamma LUT h](j)}(h ``ogam_ram``h]j)}(hj҃h]hogam_ram}(hjԃhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЃubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj̃ubj)}(hhh]h)}(hprogrammable out gamma LUTh]hprogrammable out gamma LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj̃ubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h.``ocsc`` output color space conversion matrix h](j)}(h``ocsc``h]j)}(hj h]hocsc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h$output color space conversion matrixh]h$output color space conversion matrix}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(hA``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT h](j)}(h``num_3dluts``h]j)}(hjDh]h num_3dluts}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj>ubj)}(hhh]h)}(h1MPC 3D LUT; always assumes a preceding shaper LUTh]h1MPC 3D LUT; always assumes a preceding shaper LUT}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhKhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhKhjubj)}(hR``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT h](j)}(h``num_rmcm_3dluts``h]j)}(hj}h]hnum_rmcm_3dluts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjwubj)}(hhh]h)}(h=number of RMCM 3D LUTS; always assumes a preceding shaper LUTh]h=number of RMCM 3D LUTS; always assumes a preceding shaper LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hT``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance h](j)}(h``shared_3d_lut``h]j)}(hjh]h shared_3d_lut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(hAshared 3D LUT flag. Can be either DPP or MPC, but single instanceh]hAshared 3D LUT flag. Can be either DPP or MPC, but single instance}(hjτhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj̄ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj˄hKhjubj)}(h=``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT h](j)}(h``ogam_rom_caps``h]j)}(hjh]h ogam_rom_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h6``mcm_3d_lut_caps`` HW support cap for MCM LUT memory h](j)}(h``mcm_3d_lut_caps``h]j)}(hj)h]hmcm_3d_lut_caps}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj#ubj)}(hhh]h)}(h!HW support cap for MCM LUT memoryh]h!HW support cap for MCM LUT memory}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj>hKhjubj)}(h8``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory h](j)}(h``rmcm_3d_lut_caps``h]j)}(hjbh]hrmcm_3d_lut_caps}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj\ubj)}(hhh]h)}(h"HW support cap for RMCM LUT memoryh]h"HW support cap for RMCM LUT memory}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhKhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhjwhKhjubj)}(h=``preblend`` whether color manager supports preblend with MPCh](j)}(h ``preblend``h]j)}(hjh]hpreblend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh]h)}(h0whether color manager supports preblend with MPCh]h0whether color manager supports preblend with MPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdc_color_caps (C struct)c.dc_color_capshNtauh1jhj{hhhNhNubj)}(hhh](j)}(h dc_color_capsh]j)}(hstruct dc_color_capsh](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjhMubj+)}(h dc_color_capsh]j1)}(hjh]h dc_color_caps}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjhMubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjhMhjhhubj_)}(hhh]h)}(h2color pipes capabilities for DPP and MPC hw blocksh]h2color pipes capabilities for DPP and MPC hw blocks}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj4hhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjOjjOjjjuh1jhhhj{hNhNubj)}(h**Definition**:: struct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; }; **Members** ``dpp`` color pipes caps for DPP ``mpc`` color pipes caps for MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh:}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjSubj)}(hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };h]hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };}hjtsbah}(h]h ]h"]h$]h&]jHjIuh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjSubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjSubj)}(hhh](j)}(h!``dpp`` color pipes caps for DPP h](j)}(h``dpp``h]j)}(hjh]hdpp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubj)}(hhh]h)}(hcolor pipes caps for DPPh]hcolor pipes caps for DPP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(h ``mpc`` color pipes caps for MPCh](j)}(h``mpc``h]j)}(hj݆h]hmpc}(hj߆hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjۆubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj׆ubj)}(hhh]h)}(hcolor pipes caps for MPCh]hcolor pipes caps for MPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhj׆ubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jpipe_split_policy (C enum)c.pipe_split_policyhNtauh1jhj{hhhNhNubj)}(hhh](j)}(hpipe_split_policyh]j)}(henum pipe_split_policyh](j)}(hj,6h]henum}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMubj)}(h h]h }(hjEhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj3hhhjDhMubj+)}(hpipe_split_policyh]j1)}(hj1h]hpipe_split_policy}(hjWhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjSubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj3hhhjDhMubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj/hhhjDhMubah}(h]j*ah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjDhMhj,hhubj_)}(hhh]h)}(h$Pipe split strategy supported by DCNh]h$Pipe split strategy supported by DCN}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMghjvhhubah}(h]h ]h"]h$]h&]uh1j^hj,hhhjDhMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1jhhhj{hNhNubj)}(hX**Constants** ``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. ``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. ``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMkhjubj)}(hhh](j)}(h``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. h](j)}(h``MPC_SPLIT_DYNAMIC``h]j)}(hjh]hMPC_SPLIT_DYNAMIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMphjubj)}(hhh]h)}(hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.h]hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.}(hjӇhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMnhjЇubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjχhMphjubj)}(hg``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. h](j)}(h``MPC_SPLIT_AVOID``h]j)}(hjh]hMPC_SPLIT_AVOID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMthjubj)}(hhh]h)}(hRAvoid pipe split, which means that DC will not try any sort of split optimization.h]hRAvoid pipe split, which means that DC will not try any sort of split optimization.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMshj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMthjubj)}(h``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](j)}(h``MPC_SPLIT_AVOID_MULT_DISP``h]j)}(hj.h]hMPC_SPLIT_AVOID_MULT_DISP}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMxhj(ubj)}(hhh]h)}(hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h]hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMwhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMxhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubh)}(h**Description**h]j)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM{hj{hhubh)}(hlThis enum is used to define the pipe split policy supported by DCN. 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]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMkhjhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjhMnubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1jhhhj{hNhNubj)}(hX,**Definition**:: struct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; }; **Members** ``stream`` Stream state properties ``plane_states`` Surface state ``plane_count`` Total of active planesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMohj ubj)}(hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };h]hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };}hj.sbah}(h]h ]h"]h$]h&]jHjIuh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMqhj ubh)}(h **Members**h]j)}(hj?h]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMwhj ubj)}(hhh](j)}(h#``stream`` Stream state properties h](j)}(h ``stream``h]j)}(hj^h]hstream}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMphjXubj)}(hhh]h)}(hStream state propertiesh]hStream state properties}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMphjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhjshMphjUubj)}(h``plane_states`` Surface state h](j)}(h``plane_states``h]j)}(hjh]h plane_states}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMuhjubj)}(hhh]h)}(h Surface stateh]h Surface state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMuhjUubj)}(h&``plane_count`` Total of active planesh](j)}(h``plane_count``h]j)}(hjЉh]h plane_count}(hj҉hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjΉubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMyhjʉubj)}(hhh]h)}(hTotal of active planesh]hTotal of active planes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMzhjubah}(h]h ]h"]h$]h&]uh1jhjʉubeh}(h]h ]h"]h$]h&]uh1jhjhMyhjUubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0dc_get_underflow_debug_data_for_otg (C function)%c.dc_get_underflow_debug_data_for_otghNtauh1jhj{hhhNhNubj)}(hhh](j)}(hxvoid dc_get_underflow_debug_data_for_otg (struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h]j)}(hwvoid dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](jZ')}(hvoidh]hvoid}(hj*hhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hj&hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj&hhhj8hM ubj+)}(h#dc_get_underflow_debug_data_for_otgh]j1)}(h#dc_get_underflow_debug_data_for_otgh]h#dc_get_underflow_debug_data_for_otg}(hjKhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjGubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hj&hhhj8hM ubj')}(hO(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](j')}(h struct dc *dch](j)}(hj h]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj)}(h h]h }(hjthhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubh)}(hhh]j1)}(hdch]hdc}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjmodnameN classnameNjj)}j ]j')}j'jMsb%c.dc_get_underflow_debug_data_for_otgasbuh1hhjcubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjcubj')}(hj'h]h*}(hjhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjcubj1)}(hdch]hdc}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjcubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj_ubj')}(hint primary_otg_insth](jZ')}(hinth]hint}(hjيhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjՊubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjՊubj1)}(hprimary_otg_insth]hprimary_otg_inst}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjՊubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj_ubj')}(h(struct dc_underflow_debug_data *out_datah](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj ubh)}(hhh]j1)}(hdc_underflow_debug_datah]hdc_underflow_debug_data}(hj,hhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetj.modnameN classnameNjj)}j ]j%c.dc_get_underflow_debug_data_for_otgasbuh1hhj ubj)}(h h]h }(hjJhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhj ubj')}(hj'h]h*}(hjXhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hj ubj1)}(hout_datah]hout_data}(hjehhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hj ubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hj_ubeh}(h]h ]h"]h$]h&]jHjIuh1j'hj&hhhj8hM ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhj"hhhj8hM ubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhj8hM hjhhubj_)}(hhh]h)}(hRetrieve underflow debug data.h]hRetrieve underflow debug data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhj8hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj{hNhNubj)}(hX8**Parameters** ``struct dc *dc`` Pointer to the display core context. ``int primary_otg_inst`` Instance index of the primary OTG that underflowed. ``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. **Description** This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubj)}(hhh](j)}(h7``struct dc *dc`` Pointer to the display core context. h](j)}(h``struct dc *dc``h]j)}(hjЋh]h struct dc *dc}(hjҋhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj΋ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjʋubj)}(hhh]h)}(h$Pointer to the display core context.h]h$Pointer to the display core context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjʋubeh}(h]h ]h"]h$]h&]uh1jhjhM hjNjubj)}(hM``int primary_otg_inst`` Instance index of the primary OTG that underflowed. h](j)}(h``int primary_otg_inst``h]j)}(hj h]hint primary_otg_inst}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubj)}(hhh]h)}(h3Instance index of the primary OTG that underflowed.h]h3Instance index of the primary OTG that underflowed.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjNjubj)}(h~``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. h](j)}(h,``struct dc_underflow_debug_data *out_data``h]j)}(hjBh]h(struct dc_underflow_debug_data *out_data}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj<ubj)}(hhh]h)}(hPPointer to a dc_underflow_debug_data struct to be filled with debug information.h]hPPointer to a dc_underflow_debug_data struct to be filled with debug information.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhM hjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhM hjNjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj}h]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubh)}(hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h]hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/dc_capture_register_software_state (C function)$c.dc_capture_register_software_statehNtauh1jhj{hhhNhNubj)}(hhh](j)}(habool dc_capture_register_software_state (struct dc *dc, struct dc_register_software_state *state)h]j)}(h`bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)h](jZ')}(hj)Th]hbool}(hjŒhhhNhNubah}(h]h ]jf'ah"]h$]h&]uh1jY'hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM ubj)}(h h]h }(hjЌhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjhhhjόhM ubj+)}(h"dc_capture_register_software_stateh]j1)}(h"dc_capture_register_software_stateh]h"dc_capture_register_software_state}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjތubah}(h]h ](jCjDeh"]h$]h&]jHjIuh1j*hjhhhjόhM ubj')}(h9(struct dc *dc, struct dc_register_software_state *state)h](j')}(h struct dc *dch](j)}(hj h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjubh)}(hhh]j1)}(hdch]hdc}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjmodnameN classnameNjj)}j ]j')}j'jsb$c.dc_capture_register_software_stateasbuh1hhjubj)}(h h]h }(hj<hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjubj')}(hj'h]h*}(hjJhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjubj1)}(hdch]hdc}(hjWhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjubj')}(h(struct dc_register_software_state *stateh](j)}(hj h]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj)}(h h]h }(hj}hhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjlubh)}(hhh]j1)}(hdc_register_software_stateh]hdc_register_software_state}(hjhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjubah}(h]h ]h"]h$]h&] refdomainjreftypej' reftargetjmodnameN classnameNjj)}j ]j8$c.dc_capture_register_software_stateasbuh1hhjlubj)}(h h]h }(hjhhhNhNubah}(h]h ]j&ah"]h$]h&]uh1jhjlubj')}(hj'h]h*}(hjhhhNhNubah}(h]h ]j'ah"]h$]h&]uh1j'hjlubj1)}(hstateh]hstate}(hjǍhhhNhNubah}(h]h ]j<ah"]h$]h&]uh1j0hjlubeh}(h]h ]h"]h$]h&]noemphjHjIuh1j'hjubeh}(h]h ]h"]h$]h&]jHjIuh1j'hjhhhjόhM ubeh}(h]h ]h"]h$]h&]jHjIjPuh1jjQjRhjhhhjόhM ubah}(h]jah ](jVjWeh"]h$]h&]j[j\)j]huh1jhjόhM hjhhubj_)}(hhh]h)}(h/Capture software state for register programmingh]h/Capture software state for register programming}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjhhubah}(h]h ]h"]h$]h&]uh1j^hjhhhjόhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhj{hNhNubj)}(hXM**Parameters** ``struct dc *dc`` DC context containing current display configuration ``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate **Description** Extracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming. The function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration) This is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues. **Return** true if state was successfully captured, false on errorh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubj)}(hhh](j)}(hF``struct dc *dc`` DC context containing current display configuration h](j)}(h``struct dc *dc``h]j)}(hj2h]h struct dc *dc}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj,ubj)}(hhh]h)}(h3DC context containing current display configurationh]h3DC context containing current display configuration}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhM hjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhM hj)ubj)}(hi``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate h](j)}(h,``struct dc_register_software_state *state``h]j)}(hjkh]h(struct dc_register_software_state *state}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjeubj)}(hhh]h)}(h;Pointer to dc_register_software_state structure to populateh]h;Pointer to dc_register_software_state structure to populate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjhM hj)ubeh}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubh)}(hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.h]hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubh)}(hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)h]hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)}(hjˎhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubh)}(hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.h]hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.}(hjڎhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubh)}(h7true if state was successfully captured, false on errorh]h7true if state was successfully captured, false on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj{hhhNhNubh)}(hThe color pipeline has undergone major changes between DCN hardware generations. What's possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.h]hThe color pipeline has undergone major changes between DCN hardware generations. What’s possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj{hhubh)}(h)**DCN 2.0 family color caps and mapping**h]j)}(hj'h]h%DCN 2.0 family color caps and mapping}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hhhhKOhj{hhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h+.. kernel-figure:: dcn2_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn2_cm_drm_current.svg candidates}j'jTsuh1jGhjDhhhKubah}(h]h ]h"]h$]h&]uh1jBhj?ubah}(h]h ]h"]h$]h&]uh1j=hj{hhhhhKRubh)}(h)**DCN 3.0 family color caps and mapping**h]j)}(hjeh]h%DCN 3.0 family color caps and mapping}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhhhKShj{hhubj>)}(hhh]jC)}(hhh]jH)}(h+.. kernel-figure:: dcn3_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn3_cm_drm_current.svgjU}j'jsuh1jGhj}hhhKubah}(h]h ]h"]h$]h&]uh1jBhjzubah}(h]h ]h"]h$]h&]uh1j=hj{hhhhhKVubeh}(h]jah ]h"]-dc color capabilities between dcn generationsah$]h&]uh1hhj$HhhhhhK7ubeh}(h]jqah ]h"]color management propertiesah$]h&]uh1hhhhhhhhK-ubh)}(hhh](h)}(hBlend Mode Propertiesh]hBlend Mode Properties}(hjhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjhhhhhKXubh)}(hXPixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in :ref:`DRM Plane Composition Properties `.h](h8Pixel blend mode is a DRM plane composition property of }(hjhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjh]h drm_plane}(hjďhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj drm_planeuh1hhhhKZhjubhX' used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in }(hjhhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]hinline)}(hjh]h DRM Plane Composition Properties}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjplane_composition_propertiesuh1hhhhKZhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKZhjhhubh)}(hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:h]hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjhhubh)}(hhh](h)}(hG*fg.rgb*: Each of the RGB component values from the foreground's pixel.h]h)}(hj"h](jC)}(h*fg.rgb*h]hfg.rgb}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jChj$ubhA: Each of the RGB component values from the foreground’s pixel.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKfhj ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h>*fg.alpha*: Alpha component value from the foreground's pixel.h]h)}(hjGh](jC)}(h *fg.alpha*h]hfg.alpha}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjIubh6: Alpha component value from the foreground’s pixel.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjEubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h?*bg.rgb*: Each of the RGB component values from the background.h]h)}(hjlh](jC)}(h*bg.rgb*h]hbg.rgb}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjnubh7: Each of the RGB component values from the background.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhjjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `. h]h)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `.h](jC)}(h *plane_alpha*h]h plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh: Plane alpha value set by the }(hjhhhNhNubj)}(h**plane "alpha" property**h]hplane “alpha” property}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, see more in }(hjhhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]j)}(hjh]h DRM Plane Composition Properties}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjɐreftyperef refexplicitrefwarnjplane_composition_propertiesuh1hhhhKihjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j)j)uh1hhhhKfhjhhubh)}(h&in the basic alpha blending equation::h]h%in the basic alpha blending equation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjhhubj)}(h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgbh]h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb}hjsbah}(h]h ]h"]h$]h&]jHjIuh1jhhhKnhjhhubh)}(h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.h]h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjhhubh)}(hNDRM has three blend mode to define the blend formula in the plane composition:h]hNDRM has three blend mode to define the blend formula in the plane composition:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjhhubh)}(hhh](h)}(h6**None**: Blend formula that ignores the pixel alpha. h]h)}(h5**None**: Blend formula that ignores the pixel alpha.h](j)}(h**None**h]hNone}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh-: Blend formula that ignores the pixel alpha.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKuhj,ubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhNubh)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage. h]h)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.h](j)}(h**Pre-multiplied**h]hPre-multiplied}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjRubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhNubh)}(hw**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values. h]h)}(hv**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.h](j)}(h **Coverage**h]hCoverage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubhj: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhjxubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhNubeh}(h]h ]h"]h$]h&]j)j'uh1hhhhKuhjhhubh)}(hX1and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane's pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.h]hX3and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane’s pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjhhubh)}(hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:h]hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXTherefore, the blending configuration for a single MPCC instance on the MPC tree is defined by :c:type:`mpcc_blnd_cfg`, where :c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. :c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for :c:type:`MPCC_ALPHA_BLND_MODE`, as described below.;h](h_Therefore, the blending configuration for a single MPCC instance on the MPC tree is defined by }(hjhhhNhNubh)}(h:c:type:`mpcc_blnd_cfg`h]j)}(hjʑh]h mpcc_blnd_cfg}(hj̑hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjȑubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj mpcc_blnd_cfguh1hhhhKhjubh, where }(hjhhhNhNubh)}(h:c:type:`pre_multiplied_alpha`h]j)}(hjh]hpre_multiplied_alpha}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjpre_multiplied_alphauh1hhhhKhjubh3 is the alpha pre-multiplied mode flag used to set }(hjhhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hjh]hMPCC_ALPHA_MULTIPLIED_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjMPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjubhk. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. }(hjhhhNhNubh)}(h:c:type:`mpcc_alpha_blend_mode`h]j)}(hj3h]hmpcc_alpha_blend_mode}(hj5hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjmpcc_alpha_blend_modeuh1hhhhKhjubho defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for }(hjhhhNhNubh)}(h:c:type:`MPCC_ALPHA_BLND_MODE`h]j)}(hjVh]hMPCC_ALPHA_BLND_MODE}(hjXhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjMPCC_ALPHA_BLND_MODEuh1hhhhKhjubh, as described below.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhDM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM blend formula, as follows:h](hDM then maps the elements of }(hj}hhhNhNubhtitle_reference)}(h`enum mpcc_alpha_blend_mode`h]henum mpcc_alpha_blend_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh/ to those in the DRM blend formula, as follows:}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh]h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh](jC)}(h*MPC pixel alpha*h]hMPC pixel alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh matches }(hjhhhNhNubjC)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh6 as the alpha component value from the plane’s pixel}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh]h)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh](jC)}(h*MPC global alpha*h]hMPC global alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjޒubh matches }(hjޒhhhNhNubjC)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjޒubh[ when the pixel alpha should be ignored and, therefore, pixel values are not pre-multiplied}(hjޒhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjڒubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equation h]h)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equationh](jC)}(h*MPC global gain*h]hMPC global gain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh assumes }(hjhhhNhNubjC)}(h*MPC global alpha*h]hMPC global alpha}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh value when both }(hjhhhNhNubjC)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh and }(hjhhhNhNubjC)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jChjubh" participate in the blend equation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]j)j'uh1hhhhKhjhhubh)}(hXhIn short, *fg.alpha* is ignored by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the :c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are pre-multiplied by alpha or not.h](h In short, }(hjthhhNhNubjC)}(h *fg.alpha*h]hfg.alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jChjtubh is ignored by selecting }(hjthhhNhNubh)}(h,:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`h]j)}(hjh]h"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHAuh1hhhhKhjtubhW. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting }(hjthhhNhNubh)}(hD:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`h]j)}(hjh]h:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAINuh1hhhhKhjtubh . And the }(hjthhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hj֓h]hMPCC_ALPHA_MULTIPLIED_MODE}(hjؓhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjԓubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjMPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjtubhF defines if the pixel color values are pre-multiplied by alpha or not.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hBlend configuration flowh]hBlend configuration flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]hj=uh1hhjhhhhhKubh)}(hYThe alpha blending equation is configured from DRM to DC interface by the following path:h]hYThe alpha blending equation is configured from DRM to DC interface by the following path:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjL)}(hhh](h)}(hX%When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC). h]h)}(hX$When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC).h](hWhen updating a }(hj#hhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hj-h]hdrm_plane_state}(hj/hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_plane_stateuh1hhhhKhj#ubh , DM calls }(hj#hhhNhNubh)}(h::c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()`h]j)}(hjPh]h0amdgpu_dm_plane_fill_blending_from_plane_state()}(hjRhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj0amdgpu_dm_plane_fill_blending_from_plane_state()uh1hhhhKhj#ubh that maps }(hj#hhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hjsh]hdrm_plane_state}(hjuhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjdrm_plane_stateuh1hhhhKhj#ubh attributes to }(hj#hhhNhNubh)}(h':c:type:`dc_plane_info `h]j)}(hjh]h dc_plane_info}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj dc_plane_infouh1hhhhKhj#ubh8 struct to be handled in the OS-agnostic component (DC).}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h]h)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h](hOn DC interface, }(hjǔhhhNhNubh)}(h.:c:type:`struct mpcc_blnd_cfg `h]j)}(hjєh]hstruct mpcc_blnd_cfg}(hjӔhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjϔubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjj mpcc_blnd_cfguh1hhhhKhjǔubh7 programs the MPCC blend configuration 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