sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget6/translations/zh_CN/gpu/amdgpu/display/display-managermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/zh_TW/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/it_IT/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ja_JP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ko_KR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/pt_BR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/sp_SP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDgpu Display Managerh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]refidid1uh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager.rsthKubhtopic)}(hTable of Contents h](h)}(hTable of Contentsh]hTable of Contents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh bullet_list)}(hhh]h list_item)}(hhh](h paragraph)}(hhh]h reference)}(hhh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]hah ]h"]h$]h&]refidamdgpu-display-manageruh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]h Lifecycle}(hjhhhNhNubah}(h]id2ah ]h"]h$]h&]refid lifecycleuh1hhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h Interrupts}(hj2hhhNhNubah}(h]id3ah ]h"]h$]h&]refid interruptsuh1hhj/ubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hAtomic Implementation}(hjThhhNhNubah}(h]id4ah ]h"]h$]h&]refidatomic-implementationuh1hhjQubah}(h]h ]h"]h$]h&]uh1hhjNubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]hColor Management Properties}(hjvhhhNhNubah}(h]id5ah ]h"]h$]h&]refidcolor-management-propertiesuh1hhjsubah}(h]h ]h"]h$]h&]uh1hhjpubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]hdrm_crtc Properties}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]refiddrm-crtc-propertiesuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h)AMD Private Color Management on drm_plane}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]refid)amd-private-color-management-on-drm-planeuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hAMD plane color pipeline}(hjhhhNhNubah}(h]id8ah ]h"]h$]h&]refidamd-plane-color-pipelineuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h-DC Color Capabilities between DCN generations}(hjhhhNhNubah}(h]id9ah ]h"]h$]h&]refid-dc-color-capabilities-between-dcn-generationsuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjpubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]hBlend Mode Properties}(hj)hhhNhNubah}(h]id10ah ]h"]h$]h&]refidblend-mode-propertiesuh1hhj&ubah}(h]h ]h"]h$]h&]uh1hhj#ubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]hBlend configuration flow}(hjHhhhNhNubah}(h]id11ah ]h"]h$]h&]refidblend-configuration-flowuh1hhjEubah}(h]h ]h"]h$]h&]uh1hhjBubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhj#ubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hDisplay Properties}(hjvhhhNhNubah}(h]id12ah ]h"]h$]h&]refiddisplay-propertiesuh1hhjsubah}(h]h ]h"]h$]h&]uh1hhjpubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]table-of-contentsah ]contentsah"]table of contentsah$]h&]uh1hhhhKhhhhubh)}(hThe AMDgpu display manager, **amdgpu_dm** (or even simpler, **dm**) sits between DRM and DC. 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It acts as a liaison, converting DRM requests into DC requests, and DC responses into DRM responses.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:8: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chKxhhhhubh)}(h_The root control structure is :c:type:`struct amdgpu_display_manager `.h](hThe root control structure is }(hjhhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]hliteral)}(hjh]hstruct amdgpu_display_manager}(hjhhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc"gpu/amdgpu/display/display-manager refdomainjreftypetype refexplicitrefwarn reftargetamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:8: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chK|hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK|hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singledm_compressor_info (C struct)c.dm_compressor_infohNtauh1jhhhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhNubhdesc)}(hhh](hdesc_signature)}(hdm_compressor_infoh]hdesc_signature_line)}(hstruct dm_compressor_infoh](hdesc_sig_keyword)}(hstructh]hstruct}(hj?hhhNhNubah}(h]h ]kah"]h$]h&]uh1j=hj9hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubhdesc_sig_space)}(h h]h }(hjQhhhNhNubah}(h]h ]wah"]h$]h&]uh1jOhj9hhhjNhKubh desc_name)}(hdm_compressor_infoh]h desc_sig_name)}(hj5h]hdm_compressor_info}(hjhhhhNhNubah}(h]h ]nah"]h$]h&]uh1jfhjbubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1j`hj9hhhjNhKubeh}(h]h ]h"]h$]h&]j~j add_permalinkuh1j7sphinx_line_type declaratorhj3hhhjNhKubah}(h]j)ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j1hjNhKhj.hhubh desc_content)}(hhh]h)}(h,Buffer info used by frame buffer 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the buffer object h](j)}(h ``bo_ptr``h]j)}(hjQh]hbo_ptr}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKfhjKubj-)}(hhh]h)}(hPointer to the buffer objecth]hPointer to the buffer object}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhKfhjgubah}(h]h ]h"]h$]h&]uh1j,hjKubeh}(h]h ]h"]h$]h&]uh1j hjfhKfhj ubj )}(h``gpu_addr`` MMIO gpu addrh](j)}(h ``gpu_addr``h]j)}(hjh]hgpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKfhjubj-)}(hhh]h)}(h MMIO gpu addrh]h MMIO gpu addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKghjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKfhj ubeh}(h]h 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]h"]h$]h&]j~jjuh1j7jjhjhhhjhKzubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhKzhjhhubj)}(hhh]h)}(h5Handle time consuming work in low priority outbox IRQh]h5Handle time consuming work in low priority outbox IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKzubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhhhj+hNubj)}(hXc**Definition**:: struct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; }; **Members** ``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq ``dmub_notify`` notification for callback function ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };h]hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hj(h]hMembers}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh](j )}(hS``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq h](j)}(h``handle_hpd_work``h]j)}(hjGh]hhandle_hpd_work}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjAubj-)}(hhh]h)}(h>Work to be executed in a separate thread to handle hpd_low_irqh]h>Work to be executed in a separate thread to handle hpd_low_irq}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hKhj]ubah}(h]h ]h"]h$]h&]uh1j,hjAubeh}(h]h ]h"]h$]h&]uh1j hj\hKhj>ubj )}(h3``dmub_notify`` notification for callback function h](j)}(h``dmub_notify``h]j)}(hjh]h dmub_notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjzubj-)}(hhh]h)}(h"notification for callback functionh]h"notification for callback function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjzubeh}(h]h ]h"]h$]h&]uh1j hjhKhj>ubj )}(h``adev`` amdgpu_device pointerh](j)}(h``adev``h]j)}(hjh]hadev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhj>ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'vblank_control_work (C struct)c.vblank_control_workhNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hvblank_control_workh]j8)}(hstruct vblank_control_workh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubjP)}(h h]h }(hj!hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhj hKubja)}(hvblank_control_workh]jg)}(hj h]hvblank_control_work}(hj3hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj/ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhj hKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj hhhj hKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hj hKhjhhubj)}(hhh]h)}(hWork data for vblank controlh]hWork data for vblank control}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjRhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjjmjjmjjjuh1j,hhhhhj+hNubj)}(hX**Definition**:: struct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``acrtc`` amdgpu CRTC instance for which the event has occurred ``stream`` DC stream for which the event has occurred ``enable`` true if enabling vblankh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjqubj)}(hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };h]hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjqubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjqubj)}(hhh](j )}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hjh]hdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj hKhjubj )}(h@``acrtc`` amdgpu CRTC instance for which the event has occurred h](j)}(h ``acrtc``h]j)}(hj4 h]hacrtc}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2 ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj. ubj-)}(hhh]h)}(h5amdgpu CRTC instance for which the event has occurredh]h5amdgpu CRTC instance for which the event has occurred}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hKhjJ ubah}(h]h ]h"]h$]h&]uh1j,hj. ubeh}(h]h ]h"]h$]h&]uh1j hjI hKhjubj )}(h6``stream`` DC stream for which the event has occurred h](j)}(h ``stream``h]j)}(hjm h]hstream}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjg ubj-)}(hhh]h)}(h*DC stream for which the event has occurredh]h*DC stream for which the event has occurred}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hjg ubeh}(h]h ]h"]h$]h&]uh1j hj hKhjubj )}(h"``enable`` true if enabling vblankh](j)}(h ``enable``h]j)}(hj h]henable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(htrue if enabling vblankh]htrue if enabling vblank}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hKhjubeh}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'idle_workqueue (C struct)c.idle_workqueuehNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hidle_workqueueh]j8)}(hstruct idle_workqueueh](j>)}(hjAh]hstruct}(hj hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj hhhj hKubja)}(hidle_workqueueh]jg)}(hj h]hidle_workqueue}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj hhhj hKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j1hj hKhj hhubj)}(hhh]h)}(h%Work data for periodic action in idleh]h%Work data for periodic action in idle}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj? hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjjZ jjZ jjjuh1j,hhhhhj+hNubj)}(hX_**Definition**:: struct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``enable`` true if idle worker is enabled ``running`` true if idle worker is runningh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb ubh:}(hjb hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj^ ubj)}(hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };h]hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };}hj sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj^ ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj^ ubj)}(hhh](j )}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hj h]hwork}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hKhj ubj )}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hj h]hdm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hKhj ubj )}(h*``enable`` true if idle worker is enabled h](j)}(h ``enable``h]j)}(hj! h]henable}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(htrue if idle worker is enabledh]htrue if idle worker is enabled}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6 hKhj7 ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj6 hKhj ubj )}(h*``running`` true if idle worker is runningh](j)}(h ``running``h]j)}(hjZ h]hrunning}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjT ubj-)}(hhh]h)}(htrue if idle worker is runningh]htrue if idle worker is running}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjp ubah}(h]h ]h"]h$]h&]uh1j,hjT ubeh}(h]h ]h"]h$]h&]uh1j hjo hKhj ubeh}(h]h ]h"]h$]h&]uh1jhj^ ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'vupdate_offload_work (C struct)c.vupdate_offload_workhNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hvupdate_offload_workh]j8)}(hstruct vupdate_offload_workh](j>)}(hjAh]hstruct}(hj hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj hhhj hKubja)}(hvupdate_offload_workh]jg)}(hj h]hvupdate_offload_work}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj hhhj hKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j1hj hKhj hhubj)}(hhh]h)}(h2Work data for offloading task from vupdate handlerh]h2Work data for offloading task from vupdate handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j,hhhhhj+hNubj)}(hX**Definition**:: struct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; }; **Members** ``work`` Kernel work data for the work event ``adev`` amdgpu_device back pointer ``stream`` DC stream associated with the crtc ``adjust`` DC CRTC timing adjust to be applied to the crtch](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };h]hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };}hj3 sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hjD h]hMembers}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j )}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjc h]hwork}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj] ubj-)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx hKhjy ubah}(h]h ]h"]h$]h&]uh1j,hj] ubeh}(h]h ]h"]h$]h&]uh1j hjx hKhjZ ubj )}(h$``adev`` amdgpu_device back pointer h](j)}(h``adev``h]j)}(hj h]hadev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(hamdgpu_device back pointerh]hamdgpu_device back pointer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hKhjZ ubj )}(h.``stream`` DC stream associated with the crtc h](j)}(h ``stream``h]j)}(hj h]hstream}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(h"DC stream associated with the crtch]h"DC stream associated with the crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hKhjZ ubj )}(h:``adjust`` DC CRTC timing adjust to be applied to the crtch](j)}(h ``adjust``h]j)}(hj h]hadjust}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj-)}(hhh]h)}(h/DC CRTC timing adjust to be applied to the crtch]h/DC CRTC timing adjust to be applied to the crtc}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj$ ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj# hKhjZ ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'#amdgpu_dm_luminance_data (C struct)c.amdgpu_dm_luminance_datahNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hamdgpu_dm_luminance_datah]j8)}(hstruct amdgpu_dm_luminance_datah](j>)}(hjAh]hstruct}(hjh hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjd hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubjP)}(h h]h }(hjv hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjd hhhju hKubja)}(hamdgpu_dm_luminance_datah]jg)}(hjb h]hamdgpu_dm_luminance_data}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjd hhhju hKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj` hhhju hKubah}(h]j[ ah ](jjeh"]h$]h&]jj)jhuh1j1hju hKhj] hhubj)}(hhh]h)}(hCustom luminance datah]hCustom luminance data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhj] hhhju hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j,hhhhhj+hNubj)}(h**Definition**:: struct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; }; **Members** ``luminance`` Luminance in percent ``input_signal`` Input signal in range 0-255h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };h]hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };}hj sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j )}(h#``luminance`` Luminance in percent h](j)}(h ``luminance``h]j)}(hjh]h luminance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(hLuminance in percenth]hLuminance in percent}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hKhj-ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj,hKhjubj )}(h,``input_signal`` Input signal in range 0-255h](j)}(h``input_signal``h]j)}(hjPh]h input_signal}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjJubj-)}(hhh]h)}(hInput signal in range 0-255h]hInput signal in range 0-255}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjfubah}(h]h ]h"]h$]h&]uh1j,hjJubeh}(h]h ]h"]h$]h&]uh1j hjehKhjubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'#amdgpu_dm_backlight_caps (C struct)c.amdgpu_dm_backlight_capshNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hamdgpu_dm_backlight_capsh]j8)}(hstruct amdgpu_dm_backlight_capsh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhKubja)}(hamdgpu_dm_backlight_capsh]jg)}(hjh]hamdgpu_dm_backlight_caps}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhKhjhhubj)}(hhh]h)}(hInformation about backlighth]hInformation about backlight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhhhj+hNubj)}(hX,**Definition**:: struct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; **Members** ``ext_caps`` Keep the data struct with all the information about the display support for HDR. ``aux_min_input_signal`` Min brightness value supported by the display ``aux_max_input_signal`` Max brightness value supported by the display in nits. ``min_input_signal`` minimum possible input in range 0-255. ``max_input_signal`` maximum possible input in range 0-255. ``caps_valid`` true if these values are from the ACPI interface. ``aux_support`` Describes if the display supports AUX backlight. ``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. ``ac_level`` the default brightness if booted on AC ``dc_level`` the default brightness if booted on DC ``data_points`` the number of custom luminance data points ``luminance_data`` custom luminance datah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };h]hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };}hj)sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hj:h]hMembers}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh](j )}(h^``ext_caps`` Keep the data struct with all the information about the display support for HDR. h](j)}(h ``ext_caps``h]j)}(hjYh]hext_caps}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjSubj-)}(hhh]h)}(hPKeep the data struct with all the information about the display support for HDR.h]hPKeep the data struct with all the information about the display support for HDR.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjoubah}(h]h ]h"]h$]h&]uh1j,hjSubeh}(h]h ]h"]h$]h&]uh1j hjnhKhjPubj )}(hG``aux_min_input_signal`` Min brightness value supported by the display h](j)}(h``aux_min_input_signal``h]j)}(hjh]haux_min_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h-Min brightness value supported by the displayh]h-Min brightness value supported by the display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(hP``aux_max_input_signal`` Max brightness value supported by the display in nits. h](j)}(h``aux_max_input_signal``h]j)}(hjh]haux_max_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h6Max brightness value supported by the display in nits.h]h6Max brightness value supported by the display in nits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(h<``min_input_signal`` minimum possible input in range 0-255. h](j)}(h``min_input_signal``h]j)}(hjh]hmin_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h&minimum possible input in range 0-255.h]h&minimum possible input in range 0-255.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(h<``max_input_signal`` maximum possible input in range 0-255. h](j)}(h``max_input_signal``h]j)}(hj?h]hmax_input_signal}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj9ubj-)}(hhh]h)}(h&maximum possible input in range 0-255.h]h&maximum possible input in range 0-255.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThKhjUubah}(h]h ]h"]h$]h&]uh1j,hj9ubeh}(h]h ]h"]h$]h&]uh1j hjThKhjPubj )}(hA``caps_valid`` true if these values are from the ACPI interface. h](j)}(h``caps_valid``h]j)}(hjxh]h caps_valid}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjrubj-)}(hhh]h)}(h1true if these values are from the ACPI interface.h]h1true if these values are from the ACPI interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjrubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(hA``aux_support`` Describes if the display supports AUX backlight. h](j)}(h``aux_support``h]j)}(hjh]h aux_support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h0Describes if the display supports AUX backlight.h]h0Describes if the display supports AUX backlight.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(h``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. h](j)}(h``brightness_mask``h]j)}(hjh]hbrightness_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.h]hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(h4``ac_level`` the default brightness if booted on AC h](j)}(h ``ac_level``h]j)}(hj$h]hac_level}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h&the default brightness if booted on ACh]h&the default brightness if booted on AC}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hKhj:ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj9hKhjPubj )}(h4``dc_level`` the default brightness if booted on DC h](j)}(h ``dc_level``h]j)}(hj]h]hdc_level}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjWubj-)}(hhh]h)}(h&the default brightness if booted on DCh]h&the default brightness if booted on DC}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhKhjsubah}(h]h ]h"]h$]h&]uh1j,hjWubeh}(h]h ]h"]h$]h&]uh1j hjrhKhjPubj )}(h;``data_points`` the number of custom luminance data points h](j)}(h``data_points``h]j)}(hjh]h data_points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(h*the number of custom luminance data pointsh]h*the number of custom luminance data points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubj )}(h(``luminance_data`` custom luminance datah](j)}(h``luminance_data``h]j)}(hjh]hluminance_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj-)}(hhh]h)}(hcustom luminance datah]hcustom luminance data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjPubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubh)}(h3Describe the backlight support for ACPI or eDP AUX.h]h3Describe the backlight support for ACPI or eDP AUX.}(hj(hhhNhNubah}(h]h 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]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhj]hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhhhj+hNubj)}(hXX**Definition**:: struct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; }; **Members** ``list`` list of dal allocations ``bo`` GPU buffer object ``cpu_ptr`` CPU virtual address of the GPU buffer object ``gpu_addr`` GPU virtual address of the GPU buffer objecth](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };h]htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h;hM hjubj)}(hhh](j )}(h!``list`` list of dal allocations h](j)}(h``list``h]j)}(hjh]hlist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hlist of dal allocationsh]hlist of dal allocations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h``bo`` GPU buffer object h](j)}(h``bo``h]j)}(hj8h]hbo}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj2ubj-)}(hhh]h)}(hGPU buffer objecth]hGPU buffer object}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhMhjNubah}(h]h ]h"]h$]h&]uh1j,hj2ubeh}(h]h ]h"]h$]h&]uh1j hjMhMhjubj )}(h9``cpu_ptr`` CPU virtual address of the GPU buffer object h](j)}(h ``cpu_ptr``h]j)}(hjqh]hcpu_ptr}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjkubj-)}(hhh]h)}(h,CPU virtual address of the GPU buffer objecth]h,CPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjkubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h9``gpu_addr`` GPU virtual address of the GPU buffer objecth](j)}(h ``gpu_addr``h]j)}(hjh]hgpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h,GPU virtual address of the GPU buffer objecth]h,GPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'(hpd_rx_irq_offload_work_queue (C struct)c.hpd_rx_irq_offload_work_queuehNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hhpd_rx_irq_offload_work_queueh]j8)}(h$struct hpd_rx_irq_offload_work_queueh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhM ubja)}(hhpd_rx_irq_offload_work_queueh]jg)}(hjh]hhpd_rx_irq_offload_work_queue}(hj$hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhM ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhM hjhhubj)}(hhh]h)}(h,Work queue to handle hpd_rx_irq offload workh]h,Work queue to handle hpd_rx_irq offload work}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjChhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj^jj^jjjuh1j,hhhhhj+hNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; }; **Members** ``wq`` workqueue structure to queue offload work. ``offload_lock`` To protect fields of offload work queue. ``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss ``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event ``aconnector`` The aconnector that this work queue is attached toh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh:}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjbubj)}(hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };h]hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjbubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjbubj)}(hhh](j )}(h2``wq`` workqueue structure to queue offload work. h](j)}(h``wq``h]j)}(hjh]hwq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h*workqueue structure to queue offload work.h]h*workqueue structure to queue offload work.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h:``offload_lock`` To protect fields of offload work queue. h](j)}(h``offload_lock``h]j)}(hjh]h offload_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h(To protect fields of offload work queue.h]h(To protect fields of offload work queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hb``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss h](j)}(h``is_handling_link_loss``h]j)}(hj%h]his_handling_link_loss}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hGUsed to prevent inserting link loss event when we're handling link lossh]hIUsed to prevent inserting link loss event when we’re handling link loss}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj;ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj:hMhjubj )}(h``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event h](j)}(h!``is_handling_mst_msg_rdy_event``h]j)}(hj_h]his_handling_mst_msg_rdy_event}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM!hjYubj-)}(hhh]h)}(heUsed to prevent inserting mst message ready event when we're already handling mst message ready eventh]hgUsed to prevent inserting mst message ready event when we’re already handling mst message ready event}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjuubah}(h]h ]h"]h$]h&]uh1j,hjYubeh}(h]h ]h"]h$]h&]uh1j hjthM!hjubj )}(hA``aconnector`` The aconnector that this work queue is attached toh](j)}(h``aconnector``h]j)}(hjh]h aconnector}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM$hjubj-)}(hhh]h)}(h2The aconnector that this work queue is attached toh]h2The aconnector that this work queue is attached to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM%hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM$hjubeh}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'"hpd_rx_irq_offload_work (C struct)c.hpd_rx_irq_offload_workhNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hhpd_rx_irq_offload_workh]j8)}(hstruct hpd_rx_irq_offload_workh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM+ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhM+ubja)}(hhpd_rx_irq_offload_workh]jg)}(hjh]hhpd_rx_irq_offload_work}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhM+ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhM+ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhM+hjhhubj)}(hhh]h)}(h!hpd_rx_irq offload work structureh]h!hpd_rx_irq offload work structure}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM*hj2hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM+ubeh}(h]h ](jstructeh"]h$]h&]jjjjMjjMjjjuh1j,hhhhhj+hNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; }; **Members** ``work`` offload work ``data`` reference irq data which is used while handling offload work ``offload_wq`` offload work queue that this work is queued to ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh:}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM.hjQubj)}(hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };h]hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };}hjrsbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM0hjQubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM7hjQubj)}(hhh](j )}(h``work`` offload work h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM/hjubj-)}(hhh]h)}(h offload workh]h offload work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM/hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM/hjubj )}(hF``data`` reference irq data which is used while handling offload work h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM3hjubj-)}(hhh]h)}(h``offload_wq`` offload work queue that this work is queued to h](j)}(h``offload_wq``h]j)}(hjh]h offload_wq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM7hjubj-)}(hhh]h)}(h.offload work queue that this work is queued toh]h.offload work queue that this work is queued to}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hM7hj*ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj)hM7hjubj )}(h``adev`` amdgpu_device pointerh](j)}(h``adev``h]j)}(hjMh]hadev}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM:hjGubj-)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM;hjcubah}(h]h ]h"]h$]h&]uh1j,hjGubeh}(h]h ]h"]h$]h&]uh1j hjbhM:hjubeh}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'!amdgpu_display_manager (C struct)c.amdgpu_display_managerhNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hamdgpu_display_managerh]j8)}(hstruct amdgpu_display_managerh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMAubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMAubja)}(hamdgpu_display_managerh]jg)}(hjh]hamdgpu_display_manager}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMAubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhMAubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhMAhjhhubj)}(hhh]h)}(h%Central amdgpu display manager deviceh]h%Central amdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM@hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMAubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhhhj+hNubj)}(hX$**Definition**:: struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; spinlock_t dmub_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; spinlock_t irq_reg_lock; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct workqueue_struct *irq_wq; struct workqueue_struct *vmin_vmax_wq; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct mod_power *power_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_commit *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; void *i2c_devres_group; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct workqueue_struct *hdmi_frl_status_polling_wq; struct delayed_work hdmi_frl_status_polling_work; unsigned int hdmi_frl_status_polling_delay_ms; struct dm_boot_time_crc_info boot_time_crc_info; }; **Members** ``dc`` Display Core control structure ``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. ``dmub_notify`` Notification from DMUB. ``dmub_callback`` Callback functions to handle notification from DMUB. ``dmub_thread_offload`` Flag to indicate if callback is offload. ``dmub_fb_info`` Framebuffer regions for the DMUB. ``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. ``dmub_bo`` Buffer object for the DMUB. ``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. ``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. ``dmcub_fw_version`` DMCUB firmware version. ``fw_inst_size`` Size of the firmware instruction buffer. ``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. ``adev`` AMDGPU base driver structure ``ddev`` DRM base driver structure ``display_indexes_num`` Max number of display streams supported ``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. ``dc_lock`` Guards access to DC functions that can issue register write sequences. ``dmub_lock`` Guards access to DMUB command submission. ``audio_lock`` Guards access to audio instance changes. ``audio_component`` Used to notify ELD changes to sound driver. ``audio_registered`` True if the audio component has been registered successfully, false otherwise. ``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). ``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. ``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. ``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. ``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. ``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. ``irq_reg_lock`` Serializes the read-modify-writes of the HW interrupt control registers. Several interrupt sources share one register - e.g. the enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must not race with acking another. Held only across amdgpu_dm_irq_set() and amdgpu_dm_irq_ack(). ``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. ``dmub_outbox_params`` DMUB Outbox parameters ``irq_handler_list_table_lock`` Synchronizes access to IRQ tables ``irq_wq`` Dedicated high-priority unbound workqueue for deferred IRQ work ``vmin_vmax_wq`` Dedicated unbound workqueue for deferred vmin/vmax updates ``backlight_dev`` Backlight control device ``backlight_link`` Link on which to control backlight ``num_of_edps`` number of backlight eDPs ``backlight_caps`` Capabilities of the backlight device ``freesync_module`` Module handling freesync calculations ``hdcp_workqueue`` AMDGPU content protection queue ``vblank_control_workqueue`` Deferred work for vblank control events. ``idle_workqueue`` Periodic work for idle events. ``cached_state`` Caches device atomic state for suspend/resume ``cached_dc_state`` Cached state of content streams ``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` ``fw_dmcu`` Reference to DMCU firmware ``dmcu_fw_version`` Version of the DMCU firmware ``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW ``active_vblank_irq_count`` number of currently active vblank irqs ``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. ``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq ``mst_encoders`` fake encoders used for DP MST. ``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. ``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true ``dmcub_trace_event_en`` enable dmcub trace events ``da_list`` DAL fb memory allocation list, for communication with SMU. ``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done ``delayed_hpd_wq`` work queue used to delay DMUB HPD work ``brightness`` cached backlight values. ``actual_brightness`` last successfully applied backlight values. ``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform ``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. ``dpia_aux_lock`` Guards access to DPIA AUX ``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct ``i2c_devres_group`` Devres group for DM i2c adapter lifetime management. ``oem_i2c`` OEM i2c bus ``fused_io`` dmub fused io interface ``hdmi_frl_status_polling_work`` workqueue for 200ms frl status pollingh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMDhjubj)}(hX< struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; spinlock_t dmub_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; spinlock_t irq_reg_lock; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct workqueue_struct *irq_wq; struct workqueue_struct *vmin_vmax_wq; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct mod_power *power_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_commit *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; void *i2c_devres_group; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct workqueue_struct *hdmi_frl_status_polling_wq; struct delayed_work hdmi_frl_status_polling_work; unsigned int hdmi_frl_status_polling_delay_ms; struct dm_boot_time_crc_info boot_time_crc_info; };h]hX< struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; spinlock_t dmub_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; spinlock_t irq_reg_lock; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct workqueue_struct *irq_wq; struct workqueue_struct *vmin_vmax_wq; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct mod_power *power_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_commit *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; void *i2c_devres_group; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct workqueue_struct *hdmi_frl_status_polling_wq; struct delayed_work hdmi_frl_status_polling_work; unsigned int hdmi_frl_status_polling_delay_ms; struct dm_boot_time_crc_info boot_time_crc_info; };}hj&sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjubh)}(h **Members**h]j)}(hj7h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](j )}(h&``dc`` Display Core control structure h](j)}(h``dc``h]j)}(hjVh]hdc}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMChjPubj-)}(hhh]h)}(hDisplay Core control structureh]hDisplay Core control structure}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhMChjlubah}(h]h ]h"]h$]h&]uh1j,hjPubeh}(h]h ]h"]h$]h&]uh1j hjkhMChjMubj )}(h``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. h](j)}(h ``dmub_srv``h]j)}(hjh]hdmub_srv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMghjubj-)}(hhh]h)}(hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.h]hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMehjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMghjMubj )}(h(``dmub_notify`` Notification from DMUB. h](j)}(h``dmub_notify``h]j)}(hjh]h dmub_notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMnhjubj-)}(hhh]h)}(hNotification from DMUB.h]hNotification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMnhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMnhjMubj )}(hG``dmub_callback`` Callback functions to handle notification from DMUB. h](j)}(h``dmub_callback``h]j)}(hjh]h dmub_callback}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMvhjubj-)}(hhh]h)}(h4Callback functions to handle notification from DMUB.h]h4Callback functions to handle notification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMvhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMvhjMubj )}(hA``dmub_thread_offload`` Flag to indicate if callback is offload. h](j)}(h``dmub_thread_offload``h]j)}(hj;h]hdmub_thread_offload}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM~hj5ubj-)}(hhh]h)}(h(Flag to indicate if callback is offload.h]h(Flag to indicate if callback is offload.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM~hjQubah}(h]h ]h"]h$]h&]uh1j,hj5ubeh}(h]h ]h"]h$]h&]uh1j hjPhM~hjMubj )}(h3``dmub_fb_info`` Framebuffer regions for the DMUB. h](j)}(h``dmub_fb_info``h]j)}(hjth]h dmub_fb_info}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjnubj-)}(hhh]h)}(h!Framebuffer regions for the DMUB.h]h!Framebuffer regions for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjnubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hG``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. h](j)}(h ``dmub_fw``h]j)}(hjh]hdmub_fw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h:DMUB firmware, required on hardware that has DMUB support.h]h:DMUB firmware, required on hardware that has DMUB support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h(``dmub_bo`` Buffer object for the DMUB. h](j)}(h ``dmub_bo``h]j)}(hjh]hdmub_bo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hBuffer object for the DMUB.h]hBuffer object for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hE``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. h](j)}(h``dmub_bo_gpu_addr``h]j)}(hjh]hdmub_bo_gpu_addr}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h/GPU virtual address for the DMUB buffer object.h]h/GPU virtual address for the DMUB buffer object.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj5ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj4hMhjMubj )}(h=``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. h](j)}(h``dmub_bo_cpu_addr``h]j)}(hjXh]hdmub_bo_cpu_addr}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjRubj-)}(hhh]h)}(h'CPU address for the DMUB buffer object.h]h'CPU address for the DMUB buffer object.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjnubah}(h]h ]h"]h$]h&]uh1j,hjRubeh}(h]h ]h"]h$]h&]uh1j hjmhMhjMubj )}(h-``dmcub_fw_version`` DMCUB firmware version. h](j)}(h``dmcub_fw_version``h]j)}(hjh]hdmcub_fw_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hDMCUB firmware version.h]hDMCUB firmware version.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h:``fw_inst_size`` Size of the firmware instruction buffer. h](j)}(h``fw_inst_size``h]j)}(hjh]h fw_inst_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h(Size of the firmware instruction buffer.h]h(Size of the firmware instruction buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hf``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. h](j)}(h``cgs_device``h]j)}(hjh]h cgs_device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hVThe Common Graphics Services device. It provides an interface for accessing registers.h]hVThe Common Graphics Services device. It provides an interface for accessing registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h&``adev`` AMDGPU base driver structure h](j)}(h``adev``h]j)}(hj=h]hadev}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMDhj7ubj-)}(hhh]h)}(hAMDGPU base driver structureh]hAMDGPU base driver structure}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhMDhjSubah}(h]h ]h"]h$]h&]uh1j,hj7ubeh}(h]h ]h"]h$]h&]uh1j hjRhMDhjMubj )}(h#``ddev`` DRM base driver structure h](j)}(h``ddev``h]j)}(hjvh]hddev}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMEhjpubj-)}(hhh]h)}(hDRM base driver structureh]hDRM base driver structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMEhjubah}(h]h ]h"]h$]h&]uh1j,hjpubeh}(h]h ]h"]h$]h&]uh1j hjhMEhjMubj )}(h@``display_indexes_num`` Max number of display streams supported h](j)}(h``display_indexes_num``h]j)}(hjh]hdisplay_indexes_num}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjubj-)}(hhh]h)}(h'Max number of display streams supportedh]h'Max number of display streams supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMFhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMFhjMubj )}(h``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. h](j)}(h``atomic_obj``h]j)}(hjh]h atomic_obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hIn combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`.h](hIn combination with }(hjhhhNhNubh)}(h:c:type:`dm_atomic_state`h]j)}(hj h]hdm_atomic_state}(hj hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sbj dm_atomic_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhb it helps manage global atomic state that doesn’t map cleanly into existing drm resources, like }(hjhhhNhNubh)}(h:c:type:`dc_context`h]j)}(hj7h]h dc_context}(hj9hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  dc_contextuh1hhj0hMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj0hMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hS``dc_lock`` Guards access to DC functions that can issue register write sequences. h](j)}(h ``dc_lock``h]j)}(hjph]hdc_lock}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjjubj-)}(hhh]h)}(hFGuards access to DC functions that can issue register write sequences.h]hFGuards access to DC functions that can issue register write sequences.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h8``dmub_lock`` Guards access to DMUB command submission. h](j)}(h ``dmub_lock``h]j)}(hjh]h dmub_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h)Guards access to DMUB command submission.h]h)Guards access to DMUB command submission.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h8``audio_lock`` Guards access to audio instance changes. h](j)}(h``audio_lock``h]j)}(hjh]h audio_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h(Guards access to audio instance changes.h]h(Guards access to audio instance changes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h@``audio_component`` Used to notify ELD changes to sound driver. h](j)}(h``audio_component``h]j)}(hjh]haudio_component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(h+Used to notify ELD changes to sound driver.h]h+Used to notify ELD changes to sound driver.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj2ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj1hMhjMubj )}(hd``audio_registered`` True if the audio component has been registered successfully, false otherwise. h](j)}(h``audio_registered``h]j)}(hjUh]haudio_registered}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjOubj-)}(hhh]h)}(hNTrue if the audio component has been registered successfully, false otherwise.h]hNTrue if the audio component has been registered successfully, false otherwise.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjkubah}(h]h ]h"]h$]h&]uh1j,hjOubeh}(h]h ]h"]h$]h&]uh1j hjjhMhjMubj )}(hX;``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). h](j)}(h``irq_handler_list_low_tab``h]j)}(hjh]hirq_handler_list_low_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh](h)}(hLow priority IRQ handler table.h]hLow priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.h]hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hONote that handlers are called in the same order as they were registered (FIFO).h]hONote that handlers are called in the same order as they were registered (FIFO).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubeh}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(h``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. h](j)}(h``irq_handler_list_high_tab``h]j)}(hjh]hirq_handler_list_high_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh](h)}(h High priority IRQ handler table.h]h High priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately.h](hIt is a n*m table, same as }(hjhhhNhNubh)}(h":c:type:`irq_handler_list_low_tab`h]j)}(hjh]hirq_handler_list_low_tab}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j irq_handler_list_low_tabuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhN. However, handlers in this table are not deferred and are called immediately.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj6hMhjubeh}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hY``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. h](j)}(h``pflip_params``h]j)}(hjSh]h pflip_params}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjMubj-)}(hhh]h)}(hGPage flip IRQ parameters, passed to registered handlers when triggered.h]hGPage flip IRQ parameters, passed to registered handlers when triggered.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjiubah}(h]h ]h"]h$]h&]uh1j,hjMubeh}(h]h ]h"]h$]h&]uh1j hjhhM hjMubj )}(hb``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vblank_params``h]j)}(hjh]h vblank_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hOVertical blanking IRQ parameters, passed to registered handlers when triggered.h]hOVertical blanking IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(hh``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vline0_params``h]j)}(hjh]h vline0_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj-)}(hhh]h)}(hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.h]hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjMubj )}(ha``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vupdate_params``h]j)}(hjh]hvupdate_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM%hjubj-)}(hhh]h)}(hMVertical update IRQ parameters, passed to registered handlers when triggered.h]hMVertical update IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM$hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM%hjMubj )}(hXv``irq_reg_lock`` Serializes the read-modify-writes of the HW interrupt control registers. Several interrupt sources share one register - e.g. the enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must not race with acking another. Held only across amdgpu_dm_irq_set() and amdgpu_dm_irq_ack(). h](j)}(h``irq_reg_lock``h]j)}(hj;h]h irq_reg_lock}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM2hj5ubj-)}(hhh]h)}(hXdSerializes the read-modify-writes of the HW interrupt control registers. Several interrupt sources share one register - e.g. the enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must not race with acking another. Held only across amdgpu_dm_irq_set() and amdgpu_dm_irq_ack().h]hXdSerializes the read-modify-writes of the HW interrupt control registers. Several interrupt sources share one register - e.g. the enable and clear bits of both VSTARTUP (vblank) and VUPDATE_NO_LOCK live in OTG_GLOBAL_SYNC_STATUS. Therefore, enabling one source must not race with acking another. Held only across amdgpu_dm_irq_set() and amdgpu_dm_irq_ack().}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM-hjQubah}(h]h ]h"]h$]h&]uh1j,hj5ubeh}(h]h ]h"]h$]h&]uh1j hjPhM2hjMubj )}(he``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. h](j)}(h``dmub_trace_params``h]j)}(hjuh]hdmub_trace_params}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM:hjoubj-)}(hhh]h)}(hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.h]hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM9hjubah}(h]h ]h"]h$]h&]uh1j,hjoubeh}(h]h ]h"]h$]h&]uh1j hjhM:hjMubj )}(h.``dmub_outbox_params`` DMUB Outbox parameters h](j)}(h``dmub_outbox_params``h]j)}(hjh]hdmub_outbox_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMXhjubj-)}(hhh]h)}(hDMUB Outbox parametersh]hDMUB Outbox parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMXhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMXhjMubj )}(hB``irq_handler_list_table_lock`` Synchronizes access to IRQ tables h](j)}(h``irq_handler_list_table_lock``h]j)}(hjh]hirq_handler_list_table_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMGhjubj-)}(hhh]h)}(h!Synchronizes access to IRQ tablesh]h!Synchronizes access to IRQ tables}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMGhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMGhjMubj )}(hK``irq_wq`` Dedicated high-priority unbound workqueue for deferred IRQ work h](j)}(h ``irq_wq``h]j)}(hj! h]hirq_wq}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMHhj ubj-)}(hhh]h)}(h?Dedicated high-priority unbound workqueue for deferred IRQ workh]h?Dedicated high-priority unbound workqueue for deferred IRQ work}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6 hMHhj7 ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj6 hMHhjMubj )}(hL``vmin_vmax_wq`` Dedicated unbound workqueue for deferred vmin/vmax updates h](j)}(h``vmin_vmax_wq``h]j)}(hjZ h]h vmin_vmax_wq}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMIhjT ubj-)}(hhh]h)}(h:Dedicated unbound workqueue for deferred vmin/vmax updatesh]h:Dedicated unbound workqueue for deferred vmin/vmax updates}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo hMIhjp ubah}(h]h ]h"]h$]h&]uh1j,hjT ubeh}(h]h ]h"]h$]h&]uh1j hjo hMIhjMubj )}(h+``backlight_dev`` Backlight control device h](j)}(h``backlight_dev``h]j)}(hj h]h backlight_dev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMJhj ubj-)}(hhh]h)}(hBacklight control deviceh]hBacklight control device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMJhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hMJhjMubj )}(h6``backlight_link`` Link on which to control backlight h](j)}(h``backlight_link``h]j)}(hj h]hbacklight_link}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMKhj ubj-)}(hhh]h)}(h"Link on which to control backlighth]h"Link on which to control backlight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMKhj ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj hMKhjMubj )}(h)``num_of_edps`` number of backlight eDPs h](j)}(h``num_of_edps``h]j)}(hj!h]h num_of_edps}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMYhj ubj-)}(hhh]h)}(hnumber of backlight eDPsh]hnumber of backlight eDPs}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMYhj!ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj!hMYhjMubj )}(h8``backlight_caps`` Capabilities of the backlight device h](j)}(h``backlight_caps``h]j)}(hj>!h]hbacklight_caps}(hj@!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj` h](j)}(h``compressor``h]j)}(hj"h]h compressor}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMThj"ubj-)}(hhh]h)}(h]Frame buffer compression buffer. See :c:type:`struct dm_compressor_info `h](h%Frame buffer compression buffer. See }(hj"hhhNhNubh)}(h8:c:type:`struct dm_compressor_info `h]j)}(hj"h]hstruct dm_compressor_info}(hj"hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j dm_compressor_infouh1hhj"hMThj"ubeh}(h]h ]h"]h$]h&]uh1hhj"hMThj"ubah}(h]h ]h"]h$]h&]uh1j,hj"ubeh}(h]h ]h"]h$]h&]uh1j hj"hMThjMubj )}(h'``fw_dmcu`` Reference to DMCU firmware h](j)}(h ``fw_dmcu``h]j)}(hj%#h]hfw_dmcu}(hj'#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj##ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMOhj#ubj-)}(hhh]h)}(hReference to DMCU firmwareh]hReference to DMCU firmware}(hj>#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:#hMOhj;#ubah}(h]h ]h"]h$]h&]uh1j,hj#ubeh}(h]h ]h"]h$]h&]uh1j hj:#hMOhjMubj )}(h1``dmcu_fw_version`` Version of the DMCU firmware h](j)}(h``dmcu_fw_version``h]j)}(hj^#h]hdmcu_fw_version}(hj`#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMPhjX#ubj-)}(hhh]h)}(hVersion of the DMCU firmwareh]hVersion of the DMCU firmware}(hjw#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs#hMPhjt#ubah}(h]h ]h"]h$]h&]uh1j,hjX#ubeh}(h]h ]h"]h$]h&]uh1j hjs#hMPhjMubj )}(h^``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW h](j)}(h``soc_bounding_box``h]j)}(hj#h]hsoc_bounding_box}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMkhj#ubj-)}(hhh]h)}(hHgpu_info FW provided soc bounding box struct or 0 if not available in FWh]hHgpu_info FW provided soc bounding box struct or 0 if not available in FW}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMjhj#ubah}(h]h ]h"]h$]h&]uh1j,hj#ubeh}(h]h ]h"]h$]h&]uh1j hj#hMkhjMubj )}(hC``active_vblank_irq_count`` number of currently active vblank irqs h](j)}(h``active_vblank_irq_count``h]j)}(hj#h]hactive_vblank_irq_count}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMrhj#ubj-)}(hhh]h)}(h&number of currently active vblank irqsh]h&number of currently active vblank irqs}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMrhj#ubah}(h]h ]h"]h$]h&]uh1j,hj#ubeh}(h]h ]h"]h$]h&]uh1j hj#hMrhjMubj )}(h|``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. h](j)}(h``secure_display_ctx``h]j)}(hj $h]hsecure_display_ctx}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM{hj$ubj-)}(hhh]h)}(hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.h]hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.}(hj#$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMzhj $ubah}(h]h ]h"]h$]h&]uh1j,hj$ubeh}(h]h ]h"]h$]h&]uh1j hj$hM{hjMubj )}(h@``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq h](j)}(h``hpd_rx_offload_wq``h]j)}(hjD$h]hhpd_rx_offload_wq}(hjF$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj>$ubj-)}(hhh]h)}(h)Work queue to offload works of hpd_rx_irqh]h)Work queue to offload works of hpd_rx_irq}(hj]$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjY$hMhjZ$ubah}(h]h ]h"]h$]h&]uh1j,hj>$ubeh}(h]h ]h"]h$]h&]uh1j hjY$hMhjMubj )}(h0``mst_encoders`` fake encoders used for DP MST. h](j)}(h``mst_encoders``h]j)}(hj}$h]h mst_encoders}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjw$ubj-)}(hhh]h)}(hfake encoders used for DP MST.h]hfake encoders used for DP MST.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hMhj$ubah}(h]h ]h"]h$]h&]uh1j,hjw$ubeh}(h]h ]h"]h$]h&]uh1j hj$hMhjMubj )}(hv``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. h](j)}(h``force_timing_sync``h]j)}(hj$h]hforce_timing_sync}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMVhj$ubj-)}(hhh]h)}(h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.h]h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMUhj$ubah}(h]h ]h"]h$]h&]uh1j,hj$ubeh}(h]h ]h"]h$]h&]uh1j hj$hMVhjMubj )}(h[``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true h](j)}(h``disable_hpd_irq``h]j)}(hj$h]hdisable_hpd_irq}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM[hj$ubj-)}(hhh]h)}(hFdisables all HPD and HPD RX interrupt handling in the driver when trueh]hFdisables all HPD and HPD RX interrupt handling in the driver when true}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMZhj%ubah}(h]h ]h"]h$]h&]uh1j,hj$ubeh}(h]h ]h"]h$]h&]uh1j hj%hM[hjMubj )}(h3``dmcub_trace_event_en`` enable dmcub trace events h](j)}(h``dmcub_trace_event_en``h]j)}(hj*%h]hdmcub_trace_event_en}(hj,%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMWhj$%ubj-)}(hhh]h)}(henable dmcub trace eventsh]henable dmcub trace events}(hjC%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?%hMWhj@%ubah}(h]h ]h"]h$]h&]uh1j,hj$%ubeh}(h]h ]h"]h$]h&]uh1j hj?%hMWhjMubj )}(hG``da_list`` DAL fb memory allocation list, for communication with SMU. h](j)}(h ``da_list``h]j)}(hjc%h]hda_list}(hje%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj]%ubj-)}(hhh]h)}(h:DAL fb memory allocation list, for communication with SMU.h]h:DAL fb memory allocation list, for communication with SMU.}(hj|%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx%hMhjy%ubah}(h]h ]h"]h$]h&]uh1j,hj]%ubeh}(h]h ]h"]h$]h&]uh1j hjx%hMhjMubj )}(h[``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done h](j)}(h``dmub_aux_transfer_done``h]j)}(hj%h]hdmub_aux_transfer_done}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM]hj%ubj-)}(hhh]h)}(h?struct completion used to indicate when DMUB transfers are doneh]h?struct completion used to indicate when DMUB transfers are done}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM\hj%ubah}(h]h ]h"]h$]h&]uh1j,hj%ubeh}(h]h ]h"]h$]h&]uh1j hj%hM]hjMubj )}(h:``delayed_hpd_wq`` work queue used to delay DMUB HPD work h](j)}(h``delayed_hpd_wq``h]j)}(hj%h]hdelayed_hpd_wq}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM^hj%ubj-)}(hhh]h)}(h&work queue used to delay DMUB HPD workh]h&work queue used to delay DMUB HPD work}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hM^hj%ubah}(h]h ]h"]h$]h&]uh1j,hj%ubeh}(h]h ]h"]h$]h&]uh1j hj%hM^hjMubj )}(h(``brightness`` cached backlight values. h](j)}(h``brightness``h]j)}(hj&h]h brightness}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj &ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj &ubj-)}(hhh]h)}(hcached backlight values.h]hcached backlight values.}(hj(&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$&hMhj%&ubah}(h]h ]h"]h$]h&]uh1j,hj &ubeh}(h]h ]h"]h$]h&]uh1j hj$&hMhjMubj )}(hB``actual_brightness`` last successfully applied backlight values. h](j)}(h``actual_brightness``h]j)}(hjH&h]hactual_brightness}(hjJ&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjB&ubj-)}(hhh]h)}(h+last successfully applied backlight values.h]h+last successfully applied backlight values.}(hja&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]&hMhj^&ubah}(h]h ]h"]h$]h&]uh1j,hjB&ubeh}(h]h ]h"]h$]h&]uh1j hj]&hMhjMubj )}(hh``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform h](j)}(h``aux_hpd_discon_quirk``h]j)}(hj&h]haux_hpd_discon_quirk}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj{&ubj-)}(hhh]h)}(hNquirk for hpd discon while aux is on-going. occurred on certain intel platformh]hNquirk for hpd discon while aux is on-going. occurred on certain intel platform}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1j,hj{&ubeh}(h]h ]h"]h$]h&]uh1j hj&hMhjMubj )}(h@``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. h](j)}(h``edp0_on_dp1_quirk``h]j)}(hj&h]hedp0_on_dp1_quirk}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubj-)}(hhh]h)}(h)quirk for platforms that put edp0 on DP1.h]h)quirk for platforms that put edp0 on DP1.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMhj&ubah}(h]h ]h"]h$]h&]uh1j,hj&ubeh}(h]h ]h"]h$]h&]uh1j hj&hMhjMubj )}(h,``dpia_aux_lock`` Guards access to DPIA AUX h](j)}(h``dpia_aux_lock``h]j)}(hj&h]h dpia_aux_lock}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubj-)}(hhh]h)}(hGuards access to DPIA AUXh]hGuards access to DPIA AUX}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 'hMhj 'ubah}(h]h ]h"]h$]h&]uh1j,hj&ubeh}(h]h ]h"]h$]h&]uh1j hj 'hMhjMubj )}(h``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct h](j)}(h``bb_from_dmub``h]j)}(hj-'h]h bb_from_dmub}(hj/'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj''ubj-)}(hhh]h)}(hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb structh]hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct}(hjF'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjC'ubah}(h]h ]h"]h$]h&]uh1j,hj''ubeh}(h]h ]h"]h$]h&]uh1j hjB'hMhjMubj )}(hJ``i2c_devres_group`` Devres group for DM i2c adapter lifetime management. h](j)}(h``i2c_devres_group``h]j)}(hjg'h]hi2c_devres_group}(hji'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhja'ubj-)}(hhh]h)}(h4Devres group for DM i2c adapter lifetime management.h]h4Devres group for DM i2c adapter lifetime management.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|'hMhj}'ubah}(h]h ]h"]h$]h&]uh1j,hja'ubeh}(h]h ]h"]h$]h&]uh1j hj|'hMhjMubj )}(h``oem_i2c`` OEM i2c bus h](j)}(h ``oem_i2c``h]j)}(hj'h]hoem_i2c}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj'ubj-)}(hhh]h)}(h OEM i2c bush]h OEM i2c bus}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1j,hj'ubeh}(h]h ]h"]h$]h&]uh1j hj'hMhjMubj )}(h%``fused_io`` dmub fused io interface h](j)}(h ``fused_io``h]j)}(hj'h]hfused_io}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj'ubj-)}(hhh]h)}(hdmub fused io interfaceh]hdmub fused io interface}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1j,hj'ubeh}(h]h ]h"]h$]h&]uh1j hj'hMhjMubj )}(hG``hdmi_frl_status_polling_work`` workqueue for 200ms frl status pollingh](j)}(h ``hdmi_frl_status_polling_work``h]j)}(hj(h]hhdmi_frl_status_polling_work}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj (ubj-)}(hhh]h)}(h&workqueue for 200ms frl status pollingh]h&workqueue for 200ms frl status polling}(hj+(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj((ubah}(h]h ]h"]h$]h&]uh1j,hj (ubeh}(h]h ]h"]h$]h&]uh1j hj'(hMhjMubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j' amdgpu_hdmi_vsdb_info (C struct)c.amdgpu_hdmi_vsdb_infohNtauh1jhhhhhj+hNubj-)}(hhh](j2)}(hamdgpu_hdmi_vsdb_infoh]j8)}(hstruct amdgpu_hdmi_vsdb_infoh](j>)}(hjAh]hstruct}(hjl(hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjh(hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMubjP)}(h h]h }(hjz(hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjh(hhhjy(hMubja)}(hamdgpu_hdmi_vsdb_infoh]jg)}(hjf(h]hamdgpu_hdmi_vsdb_info}(hj(hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj(ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjh(hhhjy(hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjd(hhhjy(hMubah}(h]j_(ah ](jjeh"]h$]h&]jj)jhuh1j1hjy(hMhja(hhubj)}(hhh]h)}(hKeep track of the VSDB infoh]hKeep track of the VSDB info}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(hhubah}(h]h ]h"]h$]h&]uh1jhja(hhhjy(hMubeh}(h]h ](jstructeh"]h$]h&]jjjj(jj(jjjuh1j,hhhhhj+hNubj)}(hX**Definition**:: struct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; }; **Members** ``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. ``freesync_supported`` FreeSync Supported. ``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. ``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz ``freesync_mccs_vcp_code`` MCCS VCP code for freesync state ``replay_mode`` Replay supportedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubj)}(hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; };h]hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; };}hj(sbah}(h]h ]h"]h$]h&]j~juh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubh)}(h **Members**h]j)}(hj(h]hMembers}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubj)}(hhh](j )}(h``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. h](j)}(h``amd_vsdb_version``h]j)}(hj)h]hamd_vsdb_version}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hj)ubj-)}(hhh]h)}(hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.h]hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.}(hj4)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hj1)ubah}(h]h ]h"]h$]h&]uh1j,hj)ubeh}(h]h ]h"]h$]h&]uh1j hj0)hM hj)ubj )}(h+``freesync_supported`` FreeSync Supported. h](j)}(h``freesync_supported``h]j)}(hjU)h]hfreesync_supported}(hjW)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjO)ubj-)}(hhh]h)}(hFreeSync Supported.h]hFreeSync Supported.}(hjn)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj)hMhjk)ubah}(h]h ]h"]h$]h&]uh1j,hjO)ubeh}(h]h ]h"]h$]h&]uh1j hjj)hMhj)ubj )}(h=``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. h](j)}(h``min_refresh_rate_hz``h]j)}(hj)h]hmin_refresh_rate_hz}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj)ubj-)}(hhh]h)}(h$FreeSync Minimum Refresh Rate in Hz.h]h$FreeSync Minimum Refresh Rate in Hz.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMhj)ubah}(h]h ]h"]h$]h&]uh1j,hj)ubeh}(h]h ]h"]h$]h&]uh1j hj)hMhj)ubj )}(h<``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz h](j)}(h``max_refresh_rate_hz``h]j)}(hj)h]hmax_refresh_rate_hz}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj)ubj-)}(hhh]h)}(h#FreeSync Maximum Refresh Rate in Hzh]h#FreeSync Maximum Refresh Rate in Hz}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hMhj)ubah}(h]h ]h"]h$]h&]uh1j,hj)ubeh}(h]h ]h"]h$]h&]uh1j hj)hMhj)ubj )}(h<``freesync_mccs_vcp_code`` MCCS VCP code for freesync state h](j)}(h``freesync_mccs_vcp_code``h]j)}(hj*h]hfreesync_mccs_vcp_code}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hj)ubj-)}(hhh]h)}(h MCCS VCP code for freesync stateh]h MCCS VCP code for freesync state}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1j,hj)ubeh}(h]h ]h"]h$]h&]uh1j hj*hM hj)ubj )}(h ``replay_mode`` Replay supportedh](j)}(h``replay_mode``h]j)}(hj9*h]h replay_mode}(hj;*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7*ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM$hj3*ubj-)}(hhh]h)}(hReplay supportedh]hReplay supported}(hjR*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM%hjO*ubah}(h]h ]h"]h$]h&]uh1j,hj3*ubeh}(h]h ]h"]h$]h&]uh1j hjN*hM$hj)ubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj+hNubh)}(h**Description**h]j)}(hj|*h]h Description}(hj~*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM(hhhhubh)}(hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.h]hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhhhubh)}(hhh](h)}(h Lifecycleh]h Lifecycle}(hj*hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj*hhhhhKubh)}(hDM (and consequently DC) is registered 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Also flush IRQ workqueues and disable them.h](h)}(h**Parameters**h]j)}(hjY.h]h Parameters}(hj[.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW.ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMqhjS.ubj)}(hhh]j )}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](j)}(h$``struct amdgpu_ip_block *ip_block``h]j)}(hjx.h]h struct amdgpu_ip_block *ip_block}(hjz.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv.ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMnhjr.ubj-)}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMnhj.ubah}(h]h ]h"]h$]h&]uh1j,hjr.ubeh}(h]h ]h"]h$]h&]uh1j hj.hMnhjo.ubah}(h]h ]h"]h$]h&]uh1jhjS.ubh)}(h**Description**h]j)}(hj.h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMphjS.ubh)}(hTeardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. 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Also flush IRQ workqueues and disable them.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hMohjS.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj*hhhNhNubeh}(h]jah ]h"] lifecycleah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Interruptsh]h Interrupts}(hj /hhhNhNubah}(h]h ]h"]h$]h&]hj;uh1hhj /hhhhhKubh)}(hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.h]hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK2hj /hhubh)}(hXOThe base driver provides IRQ source registration with DRM, handler registration into the base driver's IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. 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This generic handler looks up the IRQ table, and calls the respective }(hj)/hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]j)}(hj3/h]hamdgpu_irq_src_funcs.process}(hj5/hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj1/ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK6hj)/ubh hookups.}(hj)/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjP/hK6hj /hhubh)}(hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:h]hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:}(hj[/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK`h]h)}(hjo/h]h)}(hjo/h]j)}(hjo/h]h0amdgpu_display_manager.irq_handler_list_high_tab}(hjw/hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjt/ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK?hjq/ubah}(h]h ]h"]h$]h&]uh1hhj/hK?hjm/ubah}(h]h ]h"]h$]h&]uh1hhjj/ubh)}(hS:c:type:`amdgpu_display_manager.irq_handler_list_low_tab ` h]h)}(hR:c:type:`amdgpu_display_manager.irq_handler_list_low_tab `h]h)}(hj/h]j)}(hj/h]h/amdgpu_display_manager.irq_handler_list_low_tab}(hj/hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK@hj/ubah}(h]h ]h"]h$]h&]uh1hhj/hK@hj/ubah}(h]h ]h"]h$]h&]uh1hhjj/ubeh}(h]h ]h"]h$]h&]jU-jV-uh1hhj/hK?hj /hhubh)}(hXThey override the base driver's IRQ table, and the effect can be seen in the hooks that DM provides for :c:type:`amdgpu_irq_src_funcs.process `. They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM's IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See amdgpu_dm_dce110_register_irq_handlers() and amdgpu_dm_dcn10_register_irq_handlers().h](hjThey override the base driver’s IRQ table, and the effect can be seen in the hooks that DM provides for }(hj/hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]j)}(hj/h]hamdgpu_irq_src_funcs.process}(hj/hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKBhj/ubhX4. They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM’s IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See amdgpu_dm_dce110_register_irq_handlers() and amdgpu_dm_dcn10_register_irq_handlers().}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj/hKBhj /hhubh)}(hTo expose DC's hardware interrupt toggle to the base driver, DM implements :c:type:`amdgpu_irq_src_funcs.set ` hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.h](hMTo expose DC’s hardware interrupt toggle to the base driver, DM implements }(hj 0hhhNhNubh)}(h9:c:type:`amdgpu_irq_src_funcs.set `h]j)}(hj0h]hamdgpu_irq_src_funcs.set}(hj0hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKJhj 0ubh\ hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.}(hj 0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj10hKJhj /hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'%amdgpu_dm_irq_handler_data (C struct)c.amdgpu_dm_irq_handler_datahNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(hamdgpu_dm_irq_handler_datah]j8)}(h!struct amdgpu_dm_irq_handler_datah](j>)}(hjAh]hstruct}(hjU0hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjQ0hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKubjP)}(h h]h }(hjc0hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjQ0hhhjb0hKubja)}(hamdgpu_dm_irq_handler_datah]jg)}(hjO0h]hamdgpu_dm_irq_handler_data}(hju0hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjq0ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjQ0hhhjb0hKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjM0hhhjb0hKubah}(h]jH0ah ](jjeh"]h$]h&]jj)jhuh1j1hjb0hKhjJ0hhubj)}(hhh]h)}(hData for DM interrupt handlers.h]hData for DM interrupt handlers.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKVhj0hhubah}(h]h ]h"]h$]h&]uh1jhjJ0hhhjb0hKubeh}(h]h ](jstructeh"]h$]h&]jjjj0jj0jjjuh1j,hhhj /hNhNubj)}(hX?**Definition**:: struct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; }; **Members** ``list`` Linked list entry referencing the next/previous handler ``handler`` Handler function ``handler_arg`` Argument passed to the handler when triggered ``dm`` DM which this handler belongs to ``irq_source`` DC interrupt source that this handler is registered for ``work`` work structh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: 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]jrah"]h$]h&]uh1jfhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj4modnameN classnameNj'j*)}j-]jZ4"c.amdgpu_dm_irq_register_interruptasbuh1hhj4ubjP)}(h h]h }(hj4hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj4ubj+)}(hj+h]h*}(hj4hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubjg)}(h int_paramsh]h int_params}(hj4hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj4ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj4ubjK+)}(hvoid (*ih)(void*)h](j +)}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj4ubjP)}(h h]h }(hj5hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj4ubj+)}(h(h]h(}(hj5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubj+)}(hj+h]h*}(hj,5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubjg)}(hihh]hih}(hj95hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj4ubj+)}(h)h]h)}(hjG5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubj+)}(hj 5h]h(}(hjU5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubj +)}(hvoidh]hvoid}(hjb5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj4ubj+)}(hj+h]h*}(hjp5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubj+)}(hjI5h]h)}(hj}5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj4ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj4ubjK+)}(hvoid *handler_argsh](j +)}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj5ubjP)}(h h]h }(hj5hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj5ubj+)}(hj+h]h*}(hj5hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj5ubjg)}(h handler_argsh]h handler_args}(hj5hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj5ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj4ubeh}(h]h ]h"]h$]h&]j~juh1jD+hj3hhhj3hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj3hhhj3hMubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j1hj3hMhj3hhubj)}(hhh]h)}(hRegister a handler within DM.h]hRegister a handler within DM.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj3hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6jj6jjjuh1j,hhhj /hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device. ``struct dc_interrupt_params *int_params`` Interrupt parameters containing the source, and handler context ``void (*ih)(void *)`` Function pointer to the interrupt handler to register ``void *handler_args`` Arguments passed to the handler when the interrupt occurs **Description** Register an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep. 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The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.h]hXRegister an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. 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If found, remove it. Otherwise, do nothing.h](h)}(h**Parameters**h]j)}(hj59h]h Parameters}(hj79hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj39ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMQhj/9ubj)}(hhh](j )}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjT9h]hstruct amdgpu_device *adev}(hjV9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMNhjN9ubj-)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjm9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji9hMNhjj9ubah}(h]h ]h"]h$]h&]uh1j,hjN9ubeh}(h]h ]h"]h$]h&]uh1j hji9hMNhjK9ubj )}(hN``enum dc_irq_source irq_source`` IRQ source to remove the given handler from h](j)}(h!``enum dc_irq_source irq_source``h]j)}(hj9h]henum dc_irq_source irq_source}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMOhj9ubj-)}(hhh]h)}(h+IRQ source to remove the given handler fromh]h+IRQ source to remove the given handler from}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMOhj9ubah}(h]h ]h"]h$]h&]uh1j,hj9ubeh}(h]h ]h"]h$]h&]uh1j hj9hMOhjK9ubj )}(hE``void *ih`` Function pointer to the interrupt handler to unregister h](j)}(h ``void *ih``h]j)}(hj9h]hvoid *ih}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMPhj9ubj-)}(hhh]h)}(h7Function pointer to the interrupt handler to unregisterh]h7Function pointer to the interrupt handler to unregister}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMPhj9ubah}(h]h ]h"]h$]h&]uh1j,hj9ubeh}(h]h ]h"]h$]h&]uh1j hj9hMPhjK9ubeh}(h]h ]h"]h$]h&]uh1jhj/9ubh)}(h**Description**h]j)}(hj:h]h Description}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMRhj/9ubh)}(hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h]hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMQhj/9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_irq_init (C function)c.amdgpu_dm_irq_inithNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h3int amdgpu_dm_irq_init (struct amdgpu_device *adev)h]j8)}(h2int amdgpu_dm_irq_init(struct amdgpu_device *adev)h](j +)}(hinth]hint}(hjF:hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjB:hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzubjP)}(h h]h }(hjU:hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjB:hhhjT:hMzubja)}(hamdgpu_dm_irq_inith]jg)}(hamdgpu_dm_irq_inith]hamdgpu_dm_irq_init}(hjg:hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjc:ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjB:hhhjT:hMzubjE+)}(h(struct amdgpu_device *adev)h]jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hj:hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj:ubjP)}(h h]h }(hj:hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj:ubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj:hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj:ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj:modnameN classnameNj'j*)}j-]j+)}j+ji:sbc.amdgpu_dm_irq_initasbuh1hhj:ubjP)}(h h]h }(hj:hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj:ubj+)}(hj+h]h*}(hj:hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj:ubjg)}(hadevh]hadev}(hj:hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj:ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj{:ubah}(h]h ]h"]h$]h&]j~juh1jD+hjB:hhhjT:hMzubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj>:hhhjT:hMzubah}(h]j9:ah ](jjeh"]h$]h&]jj)jhuh1j1hjT:hMzhj;:hhubj)}(hhh]h)}(hInitialize DM IRQ managementh]hInitialize DM IRQ management}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzhj;hhubah}(h]h ]h"]h$]h&]uh1jhj;:hhhjT:hMzubeh}(h]h ](jfunctioneh"]h$]h&]jjjj;jj;jjjuh1j,hhhj /hNhNubj)}(hXt**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Initialize DM's high and low context IRQ tables. The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order. The low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](h)}(h**Parameters**h]j)}(hj(;h]h Parameters}(hj*;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hj";ubj)}(hhh]j )}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjG;h]hstruct amdgpu_device *adev}(hjI;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE;ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM{hjA;ubj-)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hj`;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\;hM{hj];ubah}(h]h ]h"]h$]h&]uh1j,hjA;ubeh}(h]h ]h"]h$]h&]uh1j hj\;hM{hj>;ubah}(h]h ]h"]h$]h&]uh1jhj";ubh)}(h**Description**h]j)}(hj;h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM}hj";ubh)}(h0Initialize DM's high and low context IRQ tables.h]h2Initialize DM’s high and low context IRQ tables.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM|hj";ubh)}(hX.The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.h](h0The N by M table contains N IRQ sources, with M }(hj;hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]j)}(hj;h]h!struct amdgpu_dm_irq_handler_data}(hj;hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j amdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hj;ubh hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj;hM~hj";ubh)}(hThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](hpThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See }(hj;hhhNhNubh)}(h.:c:type:`struct irq_list_head `h]j)}(hj;h]hstruct irq_list_head}(hj;hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  irq_list_headuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj;ubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj<hMhj";ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_irq_fini (C function)c.amdgpu_dm_irq_finihNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h4void amdgpu_dm_irq_fini (struct amdgpu_device *adev)h]j8)}(h3void amdgpu_dm_irq_fini(struct amdgpu_device *adev)h](j +)}(hvoidh]hvoid}(hj+<hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj'<hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hj:<hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj'<hhhj9<hMubja)}(hamdgpu_dm_irq_finih]jg)}(hamdgpu_dm_irq_finih]hamdgpu_dm_irq_fini}(hjL<hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjH<ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj'<hhhj9<hMubjE+)}(h(struct amdgpu_device *adev)h]jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hjh<hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjd<ubjP)}(h h]h }(hju<hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjd<ubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj<hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj<modnameN classnameNj'j*)}j-]j+)}j+jN<sbc.amdgpu_dm_irq_finiasbuh1hhjd<ubjP)}(h h]h }(hj<hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjd<ubj+)}(hj+h]h*}(hj<hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjd<ubjg)}(hadevh]hadev}(hj<hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjd<ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj`<ubah}(h]h ]h"]h$]h&]j~juh1jD+hj'<hhhj9<hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj#<hhhj9<hMubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1j1hj9<hMhj <hhubj)}(hhh]h)}(hTear down DM IRQ managementh]hTear down DM IRQ management}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj<hhubah}(h]h ]h"]h$]h&]uh1jhj <hhhj9<hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj=jj=jjjuh1j,hhhj /hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Removes all handlers from the IRQ tables under the spinlock, cancels pending work items, and deallocates all handler data.h](h)}(h**Parameters**h]j)}(hj =h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj =ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubj)}(hhh]j )}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj,=h]hstruct amdgpu_device *adev}(hj.=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj&=ubj-)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjE=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA=hMhjB=ubah}(h]h ]h"]h$]h&]uh1j,hj&=ubeh}(h]h ]h"]h$]h&]uh1j hjA=hMhj#=ubah}(h]h ]h"]h$]h&]uh1jhj=ubh)}(h**Description**h]j)}(hjg=h]h Description}(hji=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje=ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubh)}(hzRemoves all handlers from the IRQ tables under the spinlock, cancels pending work items, and deallocates all handler data.h]hzRemoves all handlers from the IRQ tables under the spinlock, cancels pending work items, and deallocates all handler data.}(hj}=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'"amdgpu_dm_irq_handler (C function)c.amdgpu_dm_irq_handlerhNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(htint amdgpu_dm_irq_handler (struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h]j8)}(hsint amdgpu_dm_irq_handler(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](j +)}(hinth]hint}(hj=hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj=hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hj=hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj=hhhj=hMubja)}(hamdgpu_dm_irq_handlerh]jg)}(hamdgpu_dm_irq_handlerh]hamdgpu_dm_irq_handler}(hj=hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj=ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj=hhhj=hMubjE+)}(hZ(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hj=hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj=ubjP)}(h h]h }(hj=hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj=ubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj>hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj>ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj >modnameN classnameNj'j*)}j-]j+)}j+j=sbc.amdgpu_dm_irq_handlerasbuh1hhj=ubjP)}(h h]h }(hj'>hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj=ubj+)}(hj+h]h*}(hj5>hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj=ubjg)}(hadevh]hadev}(hjB>hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj=ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj=ubjK+)}(hstruct amdgpu_irq_src *sourceh](j>)}(hjAh]hstruct}(hj[>hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjW>ubjP)}(h h]h }(hjh>hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjW>ubh)}(hhh]jg)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hjy>hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjv>ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj{>modnameN classnameNj'j*)}j-]j#>c.amdgpu_dm_irq_handlerasbuh1hhjW>ubjP)}(h h]h }(hj>hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjW>ubj+)}(hj+h]h*}(hj>hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjW>ubjg)}(hsourceh]hsource}(hj>hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjW>ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj=ubjK+)}(hstruct amdgpu_iv_entry *entryh](j>)}(hjAh]hstruct}(hj>hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj>ubjP)}(h h]h }(hj>hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj>ubh)}(hhh]jg)}(hamdgpu_iv_entryh]hamdgpu_iv_entry}(hj>hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj>ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj>modnameN classnameNj'j*)}j-]j#>c.amdgpu_dm_irq_handlerasbuh1hhj>ubjP)}(h h]h }(hj?hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj>ubj+)}(hj+h]h*}(hj?hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj>ubjg)}(hentryh]hentry}(hj"?hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj>ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj=ubeh}(h]h ]h"]h$]h&]j~juh1jD+hj=hhhj=hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj=hhhj=hMubah}(h]j=ah ](jjeh"]h$]h&]jj)jhuh1j1hj=hMhj=hhubj)}(hhh]h)}(hGeneric DM IRQ handlerh]hGeneric DM IRQ handler}(hjL?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjI?hhubah}(h]h ]h"]h$]h&]uh1jhj=hhhj=hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjd?jjd?jjjuh1j,hhhj /hNhNubj)}(hXv**Parameters** ``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device ``struct amdgpu_irq_src *source`` Unused ``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt **Description** Calls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h](h)}(h**Parameters**h]j)}(hjn?h]h Parameters}(hjp?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjh?ubj)}(hhh](j )}(hR``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj?h]hstruct amdgpu_device *adev}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj?ubj-)}(hhh]h)}(h2amdgpu base driver device containing the DM deviceh]h2amdgpu base driver device containing the DM device}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1j,hj?ubeh}(h]h ]h"]h$]h&]uh1j hj?hMhj?ubj )}(h)``struct amdgpu_irq_src *source`` Unused h](j)}(h!``struct amdgpu_irq_src *source``h]j)}(hj?h]hstruct amdgpu_irq_src *source}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj?ubj-)}(hhh]h)}(hUnusedh]hUnused}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1j,hj?ubeh}(h]h ]h"]h$]h&]uh1j hj?hMhj?ubj )}(hE``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt h](j)}(h!``struct amdgpu_iv_entry *entry``h]j)}(hj?h]hstruct amdgpu_iv_entry *entry}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj?ubj-)}(hhh]h)}(h"Data about the triggered interrupth]h"Data about the triggered interrupt}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1j,hj?ubeh}(h]h ]h"]h$]h&]uh1j hj@hMhj?ubeh}(h]h ]h"]h$]h&]uh1jhjh?ubh)}(h**Description**h]j)}(hj:@h]h Description}(hj<@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8@ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjh?ubh)}(hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h]hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.}(hjP@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjh?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_hpd_init (C function)c.amdgpu_dm_hpd_inithNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h4void amdgpu_dm_hpd_init (struct amdgpu_device *adev)h]j8)}(h3void amdgpu_dm_hpd_init(struct amdgpu_device *adev)h](j +)}(hvoidh]hvoid}(hj@hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj{@hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hj@hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj{@hhhj@hMubja)}(hamdgpu_dm_hpd_inith]jg)}(hamdgpu_dm_hpd_inith]hamdgpu_dm_hpd_init}(hj@hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj@ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj{@hhhj@hMubjE+)}(h(struct amdgpu_device *adev)h]jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hj@hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj@ubjP)}(h h]h }(hj@hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj@ubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj@hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj@ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj@modnameN classnameNj'j*)}j-]j+)}j+j@sbc.amdgpu_dm_hpd_initasbuh1hhj@ubjP)}(h h]h }(hj@hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj@ubj+)}(hj+h]h*}(hjAhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj@ubjg)}(hadevh]hadev}(hjAhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj@ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj@ubah}(h]h ]h"]h$]h&]j~juh1jD+hj{@hhhj@hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjw@hhhj@hMubah}(h]jr@ah ](jjeh"]h$]h&]jj)jhuh1j1hj@hMhjt@hhubj)}(hhh]h)}(hhpd setup callback.h]hhpd setup callback.}(hj?AhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj)}(hjAh]hstruct}(hj=BhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj9BubjP)}(h h]h }(hjJBhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj9Bubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj[BhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjXBubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj]BmodnameN classnameNj'j*)}j-]j+)}j+j#Bsbc.amdgpu_dm_hpd_finiasbuh1hhj9BubjP)}(h h]h }(hj{BhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj9Bubj+)}(hj+h]h*}(hjBhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj9Bubjg)}(hadevh]hadev}(hjBhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj9Bubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj5Bubah}(h]h ]h"]h$]h&]j~juh1jD+hjAhhhjBhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjAhhhjBhMubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1j1hjBhMhjAhhubj)}(hhh]h)}(hhpd tear down callback.h]hhpd tear down callback.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjBhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjBjjBjjjuh1j,hhhj /hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Tear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hjBh]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubj)}(hhh]j )}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hjCh]hstruct amdgpu_device *adev}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubj-)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjCubah}(h]h ]h"]h$]h&]uh1j,hjBubeh}(h]h ]h"]h$]h&]uh1j hjChMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubh)}(h**Description**h]j)}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:Cubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubh)}(hQTear down the hpd pins used by the card (evergreen+). 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Gets displayindex through the ink index and calls helper to do the processing.h](h)}(h**Parameters**h]j)}(hjDh]h Parameters}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMQhjDubj)}(hhh](j )}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hjDh]hstruct amdgpu_device *adev}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMNhjDubj-)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMNhjEubah}(h]h ]h"]h$]h&]uh1j,hjDubeh}(h]h ]h"]h$]h&]uh1j hjEhMNhjDubj )}(hA``struct dmub_notification *notify`` dmub notification structure h](j)}(h$``struct dmub_notification *notify``h]j)}(hj+Eh]h struct dmub_notification *notify}(hj-EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Eubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMOhj%Eubj-)}(hhh]h)}(hdmub notification structureh]hdmub notification structure}(hjDEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@EhMOhjAEubah}(h]h ]h"]h$]h&]uh1j,hj%Eubeh}(h]h ]h"]h$]h&]uh1j hj@EhMOhjDubeh}(h]h ]h"]h$]h&]uh1jhjDubh)}(h**Description**h]j)}(hjfEh]h Description}(hjhEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMQhjDubh)}(hvDmub Hpd interrupt processing callback. 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Gets displayindex through the ink index and calls helper to do the processing.}(hj|EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMPhjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'$dmub_hpd_sense_callback (C function)c.dmub_hpd_sense_callbackhNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h[void dmub_hpd_sense_callback (struct amdgpu_device *adev, struct dmub_notification *notify)h]j8)}(hZvoid dmub_hpd_sense_callback(struct amdgpu_device *adev, struct dmub_notification *notify)h](j +)}(hvoidh]hvoid}(hjEhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjEhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hjEhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjEhhhjEhMubja)}(hdmub_hpd_sense_callbackh]jg)}(hdmub_hpd_sense_callbackh]hdmub_hpd_sense_callback}(hjEhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjEubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjEhhhjEhMubjE+)}(h>(struct amdgpu_device *adev, struct dmub_notification *notify)h](jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hjEhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjEubjP)}(h h]h }(hjEhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjEubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hjFhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjFubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjFmodnameN classnameNj'j*)}j-]j+)}j+jEsbc.dmub_hpd_sense_callbackasbuh1hhjEubjP)}(h h]h }(hj&FhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjEubj+)}(hj+h]h*}(hj4FhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjEubjg)}(hadevh]hadev}(hjAFhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjEubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjEubjK+)}(h struct dmub_notification *notifyh](j>)}(hjAh]hstruct}(hjZFhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjVFubjP)}(h h]h }(hjgFhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjVFubh)}(hhh]jg)}(hdmub_notificationh]hdmub_notification}(hjxFhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjuFubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjzFmodnameN classnameNj'j*)}j-]j"Fc.dmub_hpd_sense_callbackasbuh1hhjVFubjP)}(h h]h }(hjFhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjVFubj+)}(hj+h]h*}(hjFhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjVFubjg)}(hnotifyh]hnotify}(hjFhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjVFubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjEubeh}(h]h ]h"]h$]h&]j~juh1jD+hjEhhhjEhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjEhhhjEhMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1j1hjEhMhjEhhubj)}(hhh]h)}(h#DMUB HPD sense processing callback.h]h#DMUB HPD sense processing callback.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjFhhubah}(h]h ]h"]h$]h&]uh1jhjEhhhjEhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjFjjFjjjuh1j,hhhj /hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer ``struct dmub_notification *notify`` dmub notification structure **Description** HPD sense changes can occur during low power states and need to be notified from firmware to driver.h](h)}(h**Parameters**h]j)}(hjFh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjFubj)}(hhh](j )}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hjGh]hstruct amdgpu_device *adev}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjGubj-)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj5GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1GhMhj2Gubah}(h]h ]h"]h$]h&]uh1j,hjGubeh}(h]h ]h"]h$]h&]uh1j hj1GhMhjGubj )}(hA``struct dmub_notification *notify`` dmub notification structure h](j)}(h$``struct dmub_notification *notify``h]j)}(hjUGh]h struct dmub_notification *notify}(hjWGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSGubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjOGubj-)}(hhh]h)}(hdmub notification structureh]hdmub notification structure}(hjnGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjGhMhjkGubah}(h]h ]h"]h$]h&]uh1j,hjOGubeh}(h]h ]h"]h$]h&]uh1j hjjGhMhjGubeh}(h]h ]h"]h$]h&]uh1jhjFubh)}(h**Description**h]j)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjFubh)}(hdHPD sense changes can occur during low power states and need to be notified from firmware to driver.h]hdHPD sense changes can occur during low power states and need to be notified from firmware to driver.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dm_pflip_high_irq (C function)c.dm_pflip_high_irqhNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h/void dm_pflip_high_irq (void *interrupt_params)h]j8)}(h.void dm_pflip_high_irq(void *interrupt_params)h](j +)}(hvoidh]hvoid}(hjGhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjGhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hjGhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjGhhhjGhMubja)}(hdm_pflip_high_irqh]jg)}(hdm_pflip_high_irqh]hdm_pflip_high_irq}(hjGhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjGubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjGhhhjGhMubjE+)}(h(void *interrupt_params)h]jK+)}(hvoid *interrupt_paramsh](j +)}(hvoidh]hvoid}(hjHhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjHubjP)}(h h]h }(hj HhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjHubj+)}(hj+h]h*}(hj.HhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjHubjg)}(hinterrupt_paramsh]hinterrupt_params}(hj;HhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjHubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj Hubah}(h]h ]h"]h$]h&]j~juh1jD+hjGhhhjGhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjGhhhjGhMubah}(h]jGah ](jjeh"]h$]h&]jj)jhuh1j1hjGhMhjGhhubj)}(hhh]h)}(hHandle pageflip interrupth]hHandle pageflip interrupt}(hjeHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjbHhhubah}(h]h ]h"]h$]h&]uh1jhjGhhhjGhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj}Hjj}Hjjjuh1j,hhhj /hNhNubj)}(h**Parameters** ``void *interrupt_params`` ignored **Description** Handles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h](h)}(h**Parameters**h]j)}(hjHh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjHubj)}(hhh]j )}(h#``void *interrupt_params`` ignored h](j)}(h``void *interrupt_params``h]j)}(hjHh]hvoid *interrupt_params}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjHubj-)}(hhh]h)}(hignoredh]hignored}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjHubah}(h]h ]h"]h$]h&]uh1j,hjHubeh}(h]h ]h"]h$]h&]uh1j hjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubh)}(h**Description**h]j)}(hjHh]h Description}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjHubh)}(hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h]hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'%dm_crtc_high_irq_handler (C function)c.dm_crtc_high_irq_handlerhNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(hUvoid dm_crtc_high_irq_handler (struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)h]j8)}(hTvoid dm_crtc_high_irq_handler(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)h](j +)}(hvoidh]hvoid}(hj&IhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj"Ihhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubjP)}(h h]h }(hj5IhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj"Ihhhj4IhMubja)}(hdm_crtc_high_irq_handlerh]jg)}(hdm_crtc_high_irq_handlerh]hdm_crtc_high_irq_handler}(hjGIhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjCIubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj"Ihhhj4IhMubjE+)}(h7(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)h](jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hjcIhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj_IubjP)}(h h]h }(hjpIhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj_Iubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hjIhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj~Iubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjImodnameN classnameNj'j*)}j-]j+)}j+jIIsbc.dm_crtc_high_irq_handlerasbuh1hhj_IubjP)}(h h]h }(hjIhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj_Iubj+)}(hj+h]h*}(hjIhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj_Iubjg)}(hadevh]hadev}(hjIhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj_Iubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj[IubjK+)}(hstruct amdgpu_crtc *acrtch](j>)}(hjAh]hstruct}(hjIhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjIubjP)}(h h]h }(hjIhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjIubh)}(hhh]jg)}(h amdgpu_crtch]h amdgpu_crtc}(hjIhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjIubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjImodnameN classnameNj'j*)}j-]jIc.dm_crtc_high_irq_handlerasbuh1hhjIubjP)}(h h]h }(hjJhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjIubj+)}(hj+h]h*}(hjJhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjIubjg)}(hacrtch]hacrtc}(hj,JhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjIubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj[Iubeh}(h]h ]h"]h$]h&]j~juh1jD+hj"Ihhhj4IhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjIhhhj4IhMubah}(h]jIah ](jjeh"]h$]h&]jj)jhuh1j1hj4IhMhjIhhubj)}(hhh]h)}(h%Common OTG vblank/flip event handlingh]h%Common OTG vblank/flip event handling}(hjVJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjSJhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhj4IhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjnJjjnJjjjuh1j,hhhj /hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` amdgpu device ``struct amdgpu_crtc *acrtc`` the CRTC to service Performs writeback completion, vblank event handling, CRC processing, VRR BTR updates and pageflip completion delivery. **Description** On DCN this is driven by VUPDATE_NO_LOCK (the register latch point) from dm_vupdate_high_irq(); on DCE it is driven by VLINE0 at the start of vblank from dm_crtc_high_irq().h](h)}(h**Parameters**h]j)}(hjxJh]h Parameters}(hjzJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvJubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjrJubj)}(hhh](j )}(h-``struct amdgpu_device *adev`` amdgpu device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjJh]hstruct amdgpu_device *adev}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjJubj-)}(hhh]h)}(h amdgpu deviceh]h amdgpu device}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjJubah}(h]h ]h"]h$]h&]uh1j,hjJubeh}(h]h ]h"]h$]h&]uh1j hjJhMhjJubj )}(h``struct amdgpu_crtc *acrtc`` the CRTC to service Performs writeback completion, vblank event handling, CRC processing, VRR BTR updates and pageflip completion delivery. h](j)}(h``struct amdgpu_crtc *acrtc``h]j)}(hjJh]hstruct amdgpu_crtc *acrtc}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjJubj-)}(hhh]h)}(hthe CRTC to service Performs writeback completion, vblank event handling, CRC processing, VRR BTR updates and pageflip completion delivery.h]hthe CRTC to service Performs writeback completion, vblank event handling, CRC processing, VRR BTR updates and pageflip completion delivery.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjJubah}(h]h ]h"]h$]h&]uh1j,hjJubeh}(h]h ]h"]h$]h&]uh1j hjJhMhjJubeh}(h]h ]h"]h$]h&]uh1jhjrJubh)}(h**Description**h]j)}(hj Kh]h Description}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Kubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjrJubh)}(hOn DCN this is driven by VUPDATE_NO_LOCK (the register latch point) from dm_vupdate_high_irq(); on DCE it is driven by VLINE0 at the start of vblank from dm_crtc_high_irq().h]hOn DCN this is driven by VUPDATE_NO_LOCK (the register latch point) from dm_vupdate_high_irq(); on DCE it is driven by VLINE0 at the start of vblank from dm_crtc_high_irq().}(hj"KhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjrJubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dm_crtc_high_irq (C function)c.dm_crtc_high_irqhNtauh1jhj /hhhNhNubj-)}(hhh](j2)}(h.void dm_crtc_high_irq (void *interrupt_params)h]j8)}(h-void dm_crtc_high_irq(void *interrupt_params)h](j +)}(hvoidh]hvoid}(hjQKhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjMKhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMwubjP)}(h h]h }(hj`KhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjMKhhhj_KhMwubja)}(hdm_crtc_high_irqh]jg)}(hdm_crtc_high_irqh]hdm_crtc_high_irq}(hjrKhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjnKubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjMKhhhj_KhMwubjE+)}(h(void *interrupt_params)h]jK+)}(hvoid *interrupt_paramsh](j +)}(hvoidh]hvoid}(hjKhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjKubjP)}(h h]h }(hjKhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjKubj+)}(hj+h]h*}(hjKhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjKubjg)}(hinterrupt_paramsh]hinterrupt_params}(hjKhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjKubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjKubah}(h]h ]h"]h$]h&]j~juh1jD+hjMKhhhj_KhMwubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjIKhhhj_KhMwubah}(h]jDKah ](jjeh"]h$]h&]jj)jhuh1j1hj_KhMwhjFKhhubj)}(hhh]h)}(hHandles CRTC interrupth]hHandles CRTC interrupt}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMwhjKhhubah}(h]h ]h"]h$]h&]uh1jhjFKhhhj_KhMwubeh}(h]h ](jfunctioneh"]h$]h&]jjjjKjjKjjjuh1j,hhhj /hNhNubj)}(hX1**Parameters** ``void *interrupt_params`` used for determining the CRTC instance **Description** Handles the CRTC/VSYNC interrupt by notifying DRM's VBLANK event handler. Used on DCE (VLINE0, set to vblank start). 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The work gets scheduled from the IRQ handler if there was a hotplug interrupt. It walks through the connector table and calls hotplug handler for each connector. After this, it sends a DRM hotplug event to alert userspace. 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The work gets scheduled from the IRQ handler if there was a hotplug interrupt. It walks through the connector table and calls hotplug handler for each connector. After this, it sends a DRM hotplug event to alert userspace.h]hXThis is the hotplug event work handler (all ASICs). The work gets scheduled from the IRQ handler if there was a hotplug interrupt. It walks through the connector table and calls hotplug handler for each connector. After this, it sends a DRM hotplug event to alert userspace.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh~/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:35: ./drivers/gpu/drm/amd/amdgpu/amdgpu_display.chK7hj/Pubh)}(hThis design approach is required in order to defer hotplug event handling from the IRQ handler to a work handler because hotplug handler has to use mutexes which cannot be locked in an IRQ handler (since :c:type:`mutex_lock` may sleep).h](hThis design approach is required in order to defer hotplug event handling from the IRQ handler to a work handler because hotplug handler has to use mutexes which cannot be locked in an IRQ handler (since }(hjPhhhNhNubh)}(h:c:type:`mutex_lock`h]j)}(hjPh]h mutex_lock}(hjPhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  mutex_lockuh1hh~/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:35: ./drivers/gpu/drm/amd/amdgpu/amdgpu_display.chK=hjPubh may sleep).}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjPhK=hj/Pubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj /hhhNhNubeh}(h]jAah ]h"] interruptsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAtomic Implementationh]hAtomic Implementation}(hjPhhhNhNubah}(h]h ]h"]h$]h&]hj]uh1hhjPhhhhhK'ubh)}(h*WIP*h]hemphasis)}(hjQh]hWIP}(hj QhhhNhNubah}(h]h ]h"]h$]h&]uh1j QhjQubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMDhjPhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j')amdgpu_dm_atomic_commit_tail (C function)c.amdgpu_dm_atomic_commit_tailhNtauh1jhjPhhhNhNubj-)}(hhh](j2)}(hCvoid amdgpu_dm_atomic_commit_tail (struct drm_atomic_commit *state)h]j8)}(hBvoid amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state)h](j +)}(hvoidh]hvoid}(hj8QhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj4Qhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubjP)}(h h]h }(hjGQhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj4QhhhjFQhMubja)}(hamdgpu_dm_atomic_commit_tailh]jg)}(hamdgpu_dm_atomic_commit_tailh]hamdgpu_dm_atomic_commit_tail}(hjYQhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjUQubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj4QhhhjFQhMubjE+)}(h!(struct drm_atomic_commit *state)h]jK+)}(hstruct drm_atomic_commit *stateh](j>)}(hjAh]hstruct}(hjuQhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjqQubjP)}(h h]h }(hjQhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqQubh)}(hhh]jg)}(hdrm_atomic_commith]hdrm_atomic_commit}(hjQhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjQubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjQmodnameN classnameNj'j*)}j-]j+)}j+j[Qsbc.amdgpu_dm_atomic_commit_tailasbuh1hhjqQubjP)}(h h]h }(hjQhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqQubj+)}(hj+h]h*}(hjQhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjqQubjg)}(hstateh]hstate}(hjQhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjqQubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjmQubah}(h]h ]h"]h$]h&]j~juh1jD+hj4QhhhjFQhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj0QhhhjFQhMubah}(h]j+Qah ](jjeh"]h$]h&]jj)jhuh1j1hjFQhMhj-Qhhubj)}(hhh]h)}(h'AMDgpu DM's commit tail implementation.h]h)AMDgpu DM’s commit tail implementation.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjQhhubah}(h]h ]h"]h$]h&]uh1jhj-QhhhjFQhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjRjjRjjjuh1j,hhhjPhNhNubj)}(hX/**Parameters** ``struct drm_atomic_commit *state`` The atomic state to commit **Description** This will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h](h)}(h**Parameters**h]j)}(hjRh]h Parameters}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjRubj)}(hhh]j )}(h?``struct drm_atomic_commit *state`` The atomic state to commit h](j)}(h#``struct drm_atomic_commit *state``h]j)}(hj9Rh]hstruct drm_atomic_commit *state}(hj;RhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Rubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj3Rubj-)}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hjRRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNRhMhjORubah}(h]h ]h"]h$]h&]uh1j,hj3Rubeh}(h]h ]h"]h$]h&]uh1j hjNRhMhj0Rubah}(h]h ]h"]h$]h&]uh1jhjRubh)}(h**Description**h]j)}(hjtRh]h Description}(hjvRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrRubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjRubh)}(hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h]hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjPhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'#amdgpu_dm_atomic_check (C function)c.amdgpu_dm_atomic_checkhNtauh1jhjPhhhNhNubj-)}(hhh](j2)}(hTint amdgpu_dm_atomic_check (struct drm_device *dev, struct drm_atomic_commit *state)h]j8)}(hSint amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state)h](j +)}(hinth]hint}(hjRhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjRhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubjP)}(h h]h }(hjRhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjRhhhjRhMubja)}(hamdgpu_dm_atomic_checkh]jg)}(hamdgpu_dm_atomic_checkh]hamdgpu_dm_atomic_check}(hjRhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjRubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjRhhhjRhMubjE+)}(h9(struct drm_device *dev, struct drm_atomic_commit *state)h](jK+)}(hstruct drm_device *devh](j>)}(hjAh]hstruct}(hjRhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjRubjP)}(h h]h }(hjShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjRubh)}(hhh]jg)}(h drm_deviceh]h drm_device}(hjShhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjSubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjSmodnameN classnameNj'j*)}j-]j+)}j+jRsbc.amdgpu_dm_atomic_checkasbuh1hhjRubjP)}(h h]h }(hj4ShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjRubj+)}(hj+h]h*}(hjBShhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjRubjg)}(hdevh]hdev}(hjOShhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjRubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjRubjK+)}(hstruct drm_atomic_commit *stateh](j>)}(hjAh]hstruct}(hjhShhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjdSubjP)}(h h]h }(hjuShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjdSubh)}(hhh]jg)}(hdrm_atomic_commith]hdrm_atomic_commit}(hjShhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjSubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjSmodnameN classnameNj'j*)}j-]j0Sc.amdgpu_dm_atomic_checkasbuh1hhjdSubjP)}(h h]h }(hjShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjdSubj+)}(hj+h]h*}(hjShhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjdSubjg)}(hstateh]hstate}(hjShhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjdSubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjRubeh}(h]h ]h"]h$]h&]j~juh1jD+hjRhhhjRhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjRhhhjRhMubah}(h]jRah ](jjeh"]h$]h&]jj)jhuh1j1hjRhMhjRhhubj)}(hhh]h)}(h*Atomic check implementation for AMDgpu DM.h]h*Atomic check implementation for AMDgpu DM.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjShhubah}(h]h ]h"]h$]h&]uh1jhjRhhhjRhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjTjjTjjjuh1j,hhhjPhNhNubj)}(hX**Parameters** ``struct drm_device *dev`` The DRM device ``struct drm_atomic_commit *state`` The atomic state to commit **Description** Validate that the given atomic state is programmable by DC into hardware. This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes. When validating the DC state, it's important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events. Note that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item. **Return** -Error code if validation failed.h](h)}(h**Parameters**h]j)}(hj Th]h Parameters}(hj ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Tubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubj)}(hhh](j )}(h*``struct drm_device *dev`` The DRM device h](j)}(h``struct drm_device *dev``h]j)}(hj*Th]hstruct drm_device *dev}(hj,ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(Tubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj$Tubj-)}(hhh]h)}(hThe DRM deviceh]hThe DRM device}(hjCThhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?ThMhj@Tubah}(h]h ]h"]h$]h&]uh1j,hj$Tubeh}(h]h ]h"]h$]h&]uh1j hj?ThMhj!Tubj )}(h?``struct drm_atomic_commit *state`` The atomic state to commit h](j)}(h#``struct drm_atomic_commit *state``h]j)}(hjcTh]hstruct drm_atomic_commit *state}(hjeThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaTubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj]Tubj-)}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hj|ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxThMhjyTubah}(h]h ]h"]h$]h&]uh1j,hj]Tubeh}(h]h ]h"]h$]h&]uh1j hjxThMhj!Tubeh}(h]h ]h"]h$]h&]uh1jhjTubh)}(h**Description**h]j)}(hjTh]h Description}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubh)}(hXeValidate that the given atomic state is programmable by DC into hardware. This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.h](hgValidate that the given atomic state is programmable by DC into hardware. This involves constructing a }(hjThhhNhNubh)}(h$:c:type:`struct dc_state `h]j)}(hjTh]hstruct dc_state}(hjThhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j dc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubh reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It’s important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjThMhjTubh)}(hXNWhen validating the DC state, it's important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.h]hXPWhen validating the DC state, it’s important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubh)}(hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.h]hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubh)}(h **Return**h]j)}(hjUh]hReturn}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubh)}(h!-Error code if validation failed.h]h!-Error code if validation failed.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:44: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjPhhhNhNubeh}(h]jcah ]h"]atomic implementationah$]h&]uh1hhhhhhhhK'ubh)}(hhh](h)}(hColor Management Propertiesh]hColor Management Properties}(hj Plane degamma -> Plane CTM -> Plane regamma -> Plane CTMh]hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM}(hjDWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKPhj{Vubh)}(hXThe input gamma LUT block isn't really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.h]hXThe input gamma LUT block isn’t really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.}(hjSWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKRhj{Vubh)}(hX!The pipe blending also happens after these blocks so we don't actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.h]hX#The pipe blending also happens after these blocks so we don’t actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.}(hjbWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKZhj{Vubh)}(hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.h]hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.}(hjqWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK`hj{Vubh)}(hIThis means that the following configuration is assumed to be the default:h]hIThis means that the following configuration is assumed to be the default:}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKdhj{Vubh)}(huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypassh]huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKghj{Vubeh}(h]jah ]h"]drm_crtc propertiesah$]h&]uh1hhj9UhhhNhNubh)}(hhh](h)}(h)AMD Private Color Management on drm_planeh]h)AMD Private Color Management on drm_plane}(hjWhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjWhNhNubh)}(hIThe AMD private color management properties on a :c:type:`drm_plane` are:h](h1The AMD private color management properties on a }(hjWhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjWh]h drm_plane}(hjWhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKmhjWubh are:}(hjWhhhNhNubeh}(h]h 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classnameNj'j*)}j-]j+)}j+__extract_blob_lutsbc.__extract_blob_lutasbuh1hhj7\hhhjI\hMubjP)}(h h]h }(hj\hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj7\hhhjI\hMubj+)}(hj+h]h*}(hj\hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj7\hhhjI\hMubja)}(h__extract_blob_luth]jg)}(hj\h]h__extract_blob_lut}(hj\hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj\ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj7\hhhjI\hMubjE+)}(h6(const struct drm_property_blob *blob, uint32_t *size)h](jK+)}(h$const struct drm_property_blob *blobh](j>)}(hj=\h]hconst}(hj\hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj\ubjP)}(h h]h }(hj\hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj\ubj>)}(hjAh]hstruct}(hj\hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj\ubjP)}(h h]h }(hj\hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj\ubh)}(hhh]jg)}(hdrm_property_blobh]hdrm_property_blob}(hj ]hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj ]modnameN classnameNj'j*)}j-]j\c.__extract_blob_lutasbuh1hhj\ubjP)}(h h]h }(hj(]hhhNhNubah}(h]h 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color mgmt property blob}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hMhj^ubah}(h]h ]h"]h$]h&]uh1j,hj]ubeh}(h]h ]h"]h$]h&]uh1j hj^hMhj]ubj )}(h``uint32_t *size`` lut size h](j)}(h``uint32_t *size``h]j)}(hj<^h]huint32_t *size}(hj>^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:^ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj6^ubj-)}(hhh]h)}(hlut sizeh]hlut size}(hjU^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQ^hMhjR^ubah}(h]h ]h"]h$]h&]uh1j,hj6^ubeh}(h]h ]h"]h$]h&]uh1j hjQ^hMhj]ubeh}(h]h ]h"]h$]h&]uh1jhj]ubh)}(h **Return**h]j)}(hjw^h]hReturn}(hjy^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju^ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj]ubh)}(hDRM LUT or NULLh]hDRM LUT or NULL}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'!__extract_blob_lut32 (C function)c.__extract_blob_lut32hNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hjconst struct drm_color_lut32 * __extract_blob_lut32 (const struct drm_property_blob *blob, uint32_t *size)h]j8)}(hhconst struct drm_color_lut32 *__extract_blob_lut32(const struct drm_property_blob *blob, uint32_t *size)h](j>)}(hj=\h]hconst}(hj^hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj^hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hj^hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj^hhhj^hMubj>)}(hjAh]hstruct}(hj^hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj^hhhj^hMubjP)}(h h]h }(hj^hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj^hhhj^hMubh)}(hhh]jg)}(hdrm_color_lut32h]hdrm_color_lut32}(hj^hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj^modnameN classnameNj'j*)}j-]j+)}j+__extract_blob_lut32sbc.__extract_blob_lut32asbuh1hhj^hhhj^hMubjP)}(h h]h }(hj_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj^hhhj^hMubj+)}(hj+h]h*}(hj%_hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj^hhhj^hMubja)}(h__extract_blob_lut32h]jg)}(hj_h]h__extract_blob_lut32}(hj6_hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj2_ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj^hhhj^hMubjE+)}(h6(const struct drm_property_blob *blob, uint32_t *size)h](jK+)}(h$const struct drm_property_blob *blobh](j>)}(hj=\h]hconst}(hjQ_hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjM_ubjP)}(h h]h }(hj^_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjM_ubj>)}(hjAh]hstruct}(hjl_hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjM_ubjP)}(h h]h }(hjy_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjM_ubh)}(hhh]jg)}(hdrm_property_blobh]hdrm_property_blob}(hj_hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj_modnameN classnameNj'j*)}j-]j_c.__extract_blob_lut32asbuh1hhjM_ubjP)}(h h]h }(hj_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjM_ubj+)}(hj+h]h*}(hj_hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjM_ubjg)}(hblobh]hblob}(hj_hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjM_ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjI_ubjK+)}(huint32_t *sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hj_hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj_modnameN classnameNj'j*)}j-]j_c.__extract_blob_lut32asbuh1hhj_ubjP)}(h h]h }(hj_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj_ubj+)}(hj+h]h*}(hj `hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj_ubjg)}(hsizeh]hsize}(hj`hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj_ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjI_ubeh}(h]h ]h"]h$]h&]j~juh1jD+hj^hhhj^hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj^hhhj^hMubah}(h]j^ah ](jjeh"]h$]h&]jj)jhuh1j1hj^hMhj^hhubj)}(hhh]h)}(h.Extracts the DRM lut and lut size from a blob.h]h.Extracts the DRM lut and lut size from a blob.}(hjB`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj?`hhubah}(h]h ]h"]h$]h&]uh1jhj^hhhj^hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjZ`jjZ`jjjuh1j,hhhj9UhNhNubj)}(h**Parameters** ``const struct drm_property_blob *blob`` DRM color mgmt property blob ``uint32_t *size`` lut size **Return** DRM LUT or NULLh](h)}(h**Parameters**h]j)}(hjd`h]h Parameters}(hjf`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb`ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj^`ubj)}(hhh](j )}(hF``const struct drm_property_blob *blob`` DRM color mgmt property blob h](j)}(h(``const struct drm_property_blob *blob``h]j)}(hj`h]h$const struct drm_property_blob *blob}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}`ubj-)}(hhh]h)}(hDRM color mgmt property blobh]hDRM color mgmt property blob}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hMhj`ubah}(h]h ]h"]h$]h&]uh1j,hj}`ubeh}(h]h ]h"]h$]h&]uh1j hj`hMhjz`ubj )}(h``uint32_t *size`` lut size h](j)}(h``uint32_t *size``h]j)}(hj`h]huint32_t *size}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj`ubj-)}(hhh]h)}(hlut sizeh]hlut size}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hMhj`ubah}(h]h ]h"]h$]h&]uh1j,hj`ubeh}(h]h ]h"]h$]h&]uh1j hj`hMhjz`ubeh}(h]h ]h"]h$]h&]uh1jhj^`ubh)}(h **Return**h]j)}(hj`h]hReturn}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj^`ubh)}(hDRM LUT or NULLh]hDRM LUT or NULL}(hj ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj^`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__is_lut_linear (C function)c.__is_lut_linearhNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hEbool __is_lut_linear (const struct drm_color_lut *lut, uint32_t size)h]j8)}(hDbool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)h](j +)}(hboolh]hbool}(hj)}(hj=\h]hconst}(hjyahhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjuaubjP)}(h h]h }(hjahhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjuaubj>)}(hjAh]hstruct}(hjahhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjuaubjP)}(h h]h }(hjahhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjuaubh)}(hhh]jg)}(h drm_color_luth]h drm_color_lut}(hjahhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjaubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjamodnameN classnameNj'j*)}j-]j+)}j+j_asbc.__is_lut_linearasbuh1hhjuaubjP)}(h h]h }(hjahhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjuaubj+)}(hj+h]h*}(hjahhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjuaubjg)}(hluth]hlut}(hjahhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjuaubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjqaubjK+)}(h uint32_t sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hj bhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjbubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj bmodnameN classnameNj'j*)}j-]jac.__is_lut_linearasbuh1hhjbubjP)}(h h]h }(hj'bhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjbubjg)}(hsizeh]hsize}(hj5bhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjbubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjqaubeh}(h]h ]h"]h$]h&]j~juh1jD+hj8ahhhjJahMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj4ahhhjJahMubah}(h]j/aah ](jjeh"]h$]h&]jj)jhuh1j1hjJahMhj1ahhubj)}(hhh]h)}(h4check if the given lut is a linear mapping of valuesh]h4check if the given lut is a linear mapping of values}(hj_bhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\bhhubah}(h]h ]h"]h$]h&]uh1jhj1ahhhjJahMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjwbjjwbjjjuh1j,hhhj9UhNhNubj)}(hXx**Parameters** ``const struct drm_color_lut *lut`` given lut to check values ``uint32_t size`` lut size **Description** It is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES) **Return** True if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h](h)}(h**Parameters**h]j)}(hjbh]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{bubj)}(hhh](j )}(h>``const struct drm_color_lut *lut`` given lut to check values h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjbh]hconst struct drm_color_lut *lut}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubj-)}(hhh]h)}(hgiven lut to check valuesh]hgiven lut to check values}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1j,hjbubeh}(h]h ]h"]h$]h&]uh1j hjbhMhjbubj )}(h``uint32_t size`` lut size h](j)}(h``uint32_t size``h]j)}(hjbh]h uint32_t size}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubj-)}(hhh]h)}(hlut sizeh]hlut size}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMhjbubah}(h]h ]h"]h$]h&]uh1j,hjbubeh}(h]h ]h"]h$]h&]uh1j hjbhMhjbubeh}(h]h ]h"]h$]h&]uh1jhj{bubh)}(h**Description**h]j)}(hjch]h Description}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{bubh)}(hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)h]hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)}(hj*chhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{bubh)}(h **Return**h]j)}(hj;ch]hReturn}(hj=chhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9cubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{bubh)}(hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h]hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.}(hjQchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{bubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'"__drm_lut_to_dc_gamma (C function)c.__drm_lut_to_dc_gammahNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hdvoid __drm_lut_to_dc_gamma (const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h]j8)}(hcvoid __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h](j +)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj|chhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hjchhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj|chhhjchMubja)}(h__drm_lut_to_dc_gammah]jg)}(h__drm_lut_to_dc_gammah]h__drm_lut_to_dc_gamma}(hjchhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjcubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj|chhhjchMubjE+)}(hI(const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h](jK+)}(hconst struct drm_color_lut *luth](j>)}(hj=\h]hconst}(hjchhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjcubjP)}(h h]h }(hjchhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjcubj>)}(hjAh]hstruct}(hjchhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjcubjP)}(h h]h }(hjchhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjcubh)}(hhh]jg)}(h drm_color_luth]h drm_color_lut}(hjchhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjcubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjcmodnameN classnameNj'j*)}j-]j+)}j+jcsbc.__drm_lut_to_dc_gammaasbuh1hhjcubjP)}(h h]h }(hjdhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjcubj+)}(hj+h]h*}(hj$dhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjcubjg)}(hluth]hlut}(hj1dhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjcubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjcubjK+)}(hstruct dc_gamma *gammah](j>)}(hjAh]hstruct}(hjJdhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjFdubjP)}(h h]h }(hjWdhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjFdubh)}(hhh]jg)}(hdc_gammah]hdc_gamma}(hjhdhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjedubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjjdmodnameN classnameNj'j*)}j-]jdc.__drm_lut_to_dc_gammaasbuh1hhjFdubjP)}(h h]h }(hjdhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjFdubj+)}(hj+h]h*}(hjdhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjFdubjg)}(hgammah]hgamma}(hjdhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjFdubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjcubjK+)}(hbool is_legacyh](j +)}(hj>ah]hbool}(hjdhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjdubjP)}(h h]h }(hjdhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjdubjg)}(h is_legacyh]h is_legacy}(hjdhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjdubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjcubeh}(h]h ]h"]h$]h&]j~juh1jD+hj|chhhjchMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjxchhhjchMubah}(h]jscah ](jjeh"]h$]h&]jj)jhuh1j1hjchMhjuchhubj)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjdhhubah}(h]h ]h"]h$]h&]uh1jhjuchhhjchMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjejjejjjuh1j,hhhj9UhNhNubj)}(hX**Parameters** ``const struct drm_color_lut *lut`` DRM lookup table for color conversion ``struct dc_gamma *gamma`` DC gamma to set entries ``bool is_legacy`` legacy or atomic gamma **Description** The conversion depends on the size of the lut - whether or not it's legacy.h](h)}(h**Parameters**h]j)}(hj!eh]h Parameters}(hj#ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubj)}(hhh](j )}(hJ``const struct drm_color_lut *lut`` DRM lookup table for color conversion h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hj@eh]hconst struct drm_color_lut *lut}(hjBehhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>eubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj:eubj-)}(hhh]h)}(h%DRM lookup table for color conversionh]h%DRM lookup table for color conversion}(hjYehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUehMhjVeubah}(h]h ]h"]h$]h&]uh1j,hj:eubeh}(h]h ]h"]h$]h&]uh1j hjUehMhj7eubj )}(h3``struct dc_gamma *gamma`` DC gamma to set entries h](j)}(h``struct dc_gamma *gamma``h]j)}(hjyeh]hstruct dc_gamma *gamma}(hj{ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjweubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjseubj-)}(hhh]h)}(hDC gamma to set entriesh]hDC gamma to set entries}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1j,hjseubeh}(h]h ]h"]h$]h&]uh1j hjehMhj7eubj )}(h*``bool is_legacy`` legacy or atomic gamma h](j)}(h``bool is_legacy``h]j)}(hjeh]hbool is_legacy}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubj-)}(hhh]h)}(hlegacy or atomic gammah]hlegacy or atomic gamma}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1j,hjeubeh}(h]h ]h"]h$]h&]uh1j hjehMhj7eubeh}(h]h ]h"]h$]h&]uh1jhjeubh)}(h**Description**h]j)}(hjeh]h Description}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubh)}(hKThe conversion depends on the size of the lut - whether or not it's legacy.h]hMThe conversion depends on the size of the lut - whether or not it’s legacy.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'$__drm_lut32_to_dc_gamma (C function)c.__drm_lut32_to_dc_gammahNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hXvoid __drm_lut32_to_dc_gamma (const struct drm_color_lut32 *lut, struct dc_gamma *gamma)h]j8)}(hWvoid __drm_lut32_to_dc_gamma(const struct drm_color_lut32 *lut, struct dc_gamma *gamma)h](j +)}(hvoidh]hvoid}(hj2fhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj.fhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hjAfhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj.fhhhj@fhMubja)}(h__drm_lut32_to_dc_gammah]jg)}(h__drm_lut32_to_dc_gammah]h__drm_lut32_to_dc_gamma}(hjSfhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjOfubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj.fhhhj@fhMubjE+)}(h;(const struct drm_color_lut32 *lut, struct dc_gamma *gamma)h](jK+)}(h!const struct drm_color_lut32 *luth](j>)}(hj=\h]hconst}(hjofhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjkfubjP)}(h h]h }(hj|fhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjkfubj>)}(hjAh]hstruct}(hjfhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjkfubjP)}(h h]h }(hjfhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjkfubh)}(hhh]jg)}(hdrm_color_lut32h]hdrm_color_lut32}(hjfhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjfubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjfmodnameN classnameNj'j*)}j-]j+)}j+jUfsbc.__drm_lut32_to_dc_gammaasbuh1hhjkfubjP)}(h h]h }(hjfhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjkfubj+)}(hj+h]h*}(hjfhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjkfubjg)}(hluth]hlut}(hjfhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjkfubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjgfubjK+)}(hstruct dc_gamma *gammah](j>)}(hjAh]hstruct}(hjfhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjfubjP)}(h h]h }(hj ghhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjfubh)}(hhh]jg)}(hdc_gammah]hdc_gamma}(hjghhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjgubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjgmodnameN classnameNj'j*)}j-]jfc.__drm_lut32_to_dc_gammaasbuh1hhjfubjP)}(h h]h }(hj8ghhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjfubj+)}(hj+h]h*}(hjFghhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjfubjg)}(hgammah]hgamma}(hjSghhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjfubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjgfubeh}(h]h ]h"]h$]h&]j~juh1jD+hj.fhhhj@fhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj*fhhhj@fhMubah}(h]j%fah ](jjeh"]h$]h&]jj)jhuh1j1hj@fhMhj'fhhubj)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hj}ghhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjzghhubah}(h]h ]h"]h$]h&]uh1jhj'fhhhj@fhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjgjjgjjjuh1j,hhhj9UhNhNubj)}(h**Parameters** ``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion ``struct dc_gamma *gamma`` DC gamma to set entries **Description** The conversion depends on the size of the lut - whether or not it's legacy.h](h)}(h**Parameters**h]j)}(hjgh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjgubj)}(hhh](j )}(hL``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hjgh]h!const struct drm_color_lut32 *lut}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjgubj-)}(hhh]h)}(h%DRM lookup table for color conversionh]h%DRM lookup table for color conversion}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMhjgubah}(h]h ]h"]h$]h&]uh1j,hjgubeh}(h]h ]h"]h$]h&]uh1j hjghMhjgubj )}(h3``struct dc_gamma *gamma`` DC gamma to set entries h](j)}(h``struct dc_gamma *gamma``h]j)}(hjgh]hstruct dc_gamma *gamma}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjgubj-)}(hhh]h)}(hDC gamma to set entriesh]hDC gamma to set entries}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhMhj hubah}(h]h ]h"]h$]h&]uh1j,hjgubeh}(h]h ]h"]h$]h&]uh1j hj hhMhjgubeh}(h]h ]h"]h$]h&]uh1jhjgubh)}(h**Description**h]j)}(hj2hh]h Description}(hj4hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0hubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjgubh)}(hKThe conversion depends on the size of the lut - whether or not it's legacy.h]hMThe conversion depends on the size of the lut - whether or not it’s legacy.}(hjHhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'#__drm_ctm_to_dc_matrix (C function)c.__drm_ctm_to_dc_matrixhNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hXvoid __drm_ctm_to_dc_matrix (const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h]j8)}(hWvoid __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](j +)}(hvoidh]hvoid}(hjwhhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjshhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM.ubjP)}(h h]h }(hjhhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjshhhhjhhM.ubja)}(h__drm_ctm_to_dc_matrixh]jg)}(h__drm_ctm_to_dc_matrixh]h__drm_ctm_to_dc_matrix}(hjhhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjhubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjshhhhjhhM.ubjE+)}(h<(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](jK+)}(hconst struct drm_color_ctm *ctmh](j>)}(hj=\h]hconst}(hjhhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhubjP)}(h h]h }(hjhhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhubj>)}(hjAh]hstruct}(hjhhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhubjP)}(h h]h }(hjhhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhubh)}(hhh]jg)}(h drm_color_ctmh]h drm_color_ctm}(hjhhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjhubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjhmodnameN classnameNj'j*)}j-]j+)}j+jhsbc.__drm_ctm_to_dc_matrixasbuh1hhjhubjP)}(h h]h }(hj ihhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhubj+)}(hj+h]h*}(hjihhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjhubjg)}(hctmh]hctm}(hj(ihhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjhubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjhubjK+)}(hstruct fixed31_32 *matrixh](j>)}(hjAh]hstruct}(hjAihhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj=iubjP)}(h h]h }(hjNihhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj=iubh)}(hhh]jg)}(h fixed31_32h]h fixed31_32}(hj_ihhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj\iubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjaimodnameN classnameNj'j*)}j-]j ic.__drm_ctm_to_dc_matrixasbuh1hhj=iubjP)}(h h]h }(hj}ihhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj=iubj+)}(hj+h]h*}(hjihhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj=iubjg)}(hmatrixh]hmatrix}(hjihhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj=iubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjhubeh}(h]h ]h"]h$]h&]j~juh1jD+hjshhhhjhhM.ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjohhhhjhhM.ubah}(h]jjhah ](jjeh"]h$]h&]jj)jhuh1j1hjhhM.hjlhhhubj)}(hhh]h)}(h+converts a DRM CTM to a DC CSC float matrixh]h+converts a DRM CTM to a DC CSC float matrix}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM.hjihhubah}(h]h ]h"]h$]h&]uh1jhjlhhhhjhhM.ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjijjijjjuh1j,hhhj9UhNhNubj)}(h**Parameters** ``const struct drm_color_ctm *ctm`` DRM color transformation matrix ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hjih]h Parameters}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM2hjiubj)}(hhh](j )}(hD``const struct drm_color_ctm *ctm`` DRM color transformation matrix h](j)}(h#``const struct drm_color_ctm *ctm``h]j)}(hjjh]hconst struct drm_color_ctm *ctm}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM/hjiubj-)}(hhh]h)}(hDRM color transformation matrixh]hDRM color transformation matrix}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhM/hjjubah}(h]h ]h"]h$]h&]uh1j,hjiubeh}(h]h ]h"]h$]h&]uh1j hjjhM/hjiubj )}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:jubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM0hj6jubj-)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjUjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQjhM0hjRjubah}(h]h ]h"]h$]h&]uh1j,hj6jubeh}(h]h ]h"]h$]h&]uh1j hjQjhM0hjiubeh}(h]h ]h"]h$]h&]uh1jhjiubh)}(h**Description**h]j)}(hjwjh]h Description}(hjyjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjujubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM2hjiubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM1hjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j''__drm_ctm_3x4_to_dc_matrix (C function)c.__drm_ctm_3x4_to_dc_matrixhNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(h`void __drm_ctm_3x4_to_dc_matrix (const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h]j8)}(h_void __drm_ctm_3x4_to_dc_matrix(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](j +)}(hvoidh]hvoid}(hjjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMPubjP)}(h h]h }(hjjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjjhhhjjhMPubja)}(h__drm_ctm_3x4_to_dc_matrixh]jg)}(h__drm_ctm_3x4_to_dc_matrixh]h__drm_ctm_3x4_to_dc_matrix}(hjjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjjhhhjjhMPubjE+)}(h@(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](jK+)}(h#const struct drm_color_ctm_3x4 *ctmh](j>)}(hj=\h]hconst}(hjjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjjubjP)}(h h]h }(hjkhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjjubj>)}(hjAh]hstruct}(hjkhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjjubjP)}(h h]h }(hj!khhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjjubh)}(hhh]jg)}(hdrm_color_ctm_3x4h]hdrm_color_ctm_3x4}(hj2khhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj/kubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj4kmodnameN classnameNj'j*)}j-]j+)}j+jjsbc.__drm_ctm_3x4_to_dc_matrixasbuh1hhjjubjP)}(h h]h }(hjRkhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjjubj+)}(hj+h]h*}(hj`khhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjjubjg)}(hctmh]hctm}(hjmkhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjjubjK+)}(hstruct fixed31_32 *matrixh](j>)}(hjAh]hstruct}(hjkhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjkubjP)}(h h]h }(hjkhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjkubh)}(hhh]jg)}(h fixed31_32h]h fixed31_32}(hjkhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjkubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjkmodnameN classnameNj'j*)}j-]jNkc.__drm_ctm_3x4_to_dc_matrixasbuh1hhjkubjP)}(h h]h }(hjkhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjkubj+)}(hj+h]h*}(hjkhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjkubjg)}(hmatrixh]hmatrix}(hjkhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjkubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjjubeh}(h]h ]h"]h$]h&]j~juh1jD+hjjhhhjjhMPubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjjhhhjjhMPubah}(h]jjah ](jjeh"]h$]h&]jj)jhuh1j1hjjhMPhjjhhubj)}(hhh]h)}(h/converts a DRM CTM 3x4 to a DC CSC float matrixh]h/converts a DRM CTM 3x4 to a DC CSC float matrix}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMPhjlhhubah}(h]h ]h"]h$]h&]uh1jhjjhhhjjhMPubeh}(h]h ](jfunctioneh"]h$]h&]jjjjljjljjjuh1j,hhhj9UhNhNubj)}(h**Parameters** ``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hj)lh]h Parameters}(hj+lhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'lubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThj#lubj)}(hhh](j )}(h\``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions h](j)}(h'``const struct drm_color_ctm_3x4 *ctm``h]j)}(hjHlh]h#const struct drm_color_ctm_3x4 *ctm}(hjJlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFlubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMQhjBlubj-)}(hhh]h)}(h3DRM color transformation matrix with 3x4 dimensionsh]h3DRM color transformation matrix with 3x4 dimensions}(hjalhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]lhMQhj^lubah}(h]h ]h"]h$]h&]uh1j,hjBlubeh}(h]h ]h"]h$]h&]uh1j hj]lhMQhj?lubj )}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hjlh]hstruct fixed31_32 *matrix}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMRhj{lubj-)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMRhjlubah}(h]h ]h"]h$]h&]uh1j,hj{lubeh}(h]h ]h"]h$]h&]uh1j hjlhMRhj?lubeh}(h]h ]h"]h$]h&]uh1jhj#lubh)}(h**Description**h]j)}(hjlh]h Description}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThj#lubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMShj#lubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__set_legacy_tf (C function)c.__set_legacy_tfhNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(huint __set_legacy_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j8)}(htint __set_legacy_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j +)}(hinth]hint}(hjmhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjlhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhubjP)}(h h]h }(hjmhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjlhhhjmhMhubja)}(h__set_legacy_tfh]jg)}(h__set_legacy_tfh]h__set_legacy_tf}(hj"mhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjmubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjlhhhjmhMhubjE+)}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](jK+)}(hstruct dc_transfer_func *funch](j>)}(hjAh]hstruct}(hj>mhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj:mubjP)}(h h]h }(hjKmhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj:mubh)}(hhh]jg)}(hdc_transfer_funch]hdc_transfer_func}(hj\mhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjYmubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj^mmodnameN classnameNj'j*)}j-]j+)}j+j$msbc.__set_legacy_tfasbuh1hhj:mubjP)}(h h]h }(hj|mhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj:mubj+)}(hj+h]h*}(hjmhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj:mubjg)}(hfunch]hfunc}(hjmhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj:mubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj6mubjK+)}(hconst struct drm_color_lut *luth](j>)}(hj=\h]hconst}(hjmhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjmubjP)}(h h]h }(hjmhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjmubj>)}(hjAh]hstruct}(hjmhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjmubjP)}(h h]h }(hjmhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjmubh)}(hhh]jg)}(h drm_color_luth]h drm_color_lut}(hjmhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjmubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmmodnameN classnameNj'j*)}j-]jxmc.__set_legacy_tfasbuh1hhjmubjP)}(h h]h }(hjnhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjmubj+)}(hj+h]h*}(hjnhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjmubjg)}(hluth]hlut}(hj"nhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjmubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj6mubjK+)}(huint32_t lut_sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hj>nhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj;nubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj@nmodnameN classnameNj'j*)}j-]jxmc.__set_legacy_tfasbuh1hhj7nubjP)}(h h]h }(hj\nhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj7nubjg)}(hlut_sizeh]hlut_size}(hjjnhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj7nubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj6mubjK+)}(h bool has_romh](j +)}(hj>ah]hbool}(hjnhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjnubjP)}(h h]h }(hjnhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjnubjg)}(hhas_romh]hhas_rom}(hjnhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjnubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj6mubeh}(h]h ]h"]h$]h&]j~juh1jD+hjlhhhjmhMhubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjlhhhjmhMhubah}(h]jlah ](jjeh"]h$]h&]jj)jhuh1j1hjmhMhhjlhhubj)}(hhh]h)}(h'Calculates the legacy transfer functionh]h'Calculates the legacy transfer function}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhhjnhhubah}(h]h ]h"]h$]h&]uh1jhjlhhhjmhMhubeh}(h]h ](jfunctioneh"]h$]h&]jjjjnjjnjjjuh1j,hhhj9UhNhNubj)}(hXa**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Description** Only for sRGB input space **Return** 0 in case of success, -ENOMEM if failsh](h)}(h**Parameters**h]j)}(hjnh]h Parameters}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMlhjnubj)}(hhh](j )}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hj oh]hstruct dc_transfer_func *func}(hj ohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMihjoubj-)}(hhh]h)}(htransfer functionh]htransfer function}(hj"ohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMihjoubah}(h]h ]h"]h$]h&]uh1j,hjoubeh}(h]h ]h"]h$]h&]uh1j hjohMihjoubj )}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjBoh]hconst struct drm_color_lut *lut}(hjDohhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@oubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMjhj)}(hjAh]hstruct}(hjphhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjpubjP)}(h h]h }(hjphhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjpubh)}(hhh]jg)}(hdc_transfer_funch]hdc_transfer_func}(hjphhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjpmodnameN classnameNj'j*)}j-]j+)}j+j~psbc.__set_output_tfasbuh1hhjpubjP)}(h h]h }(hjphhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjpubj+)}(hj+h]h*}(hjphhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjpubjg)}(hfunch]hfunc}(hjphhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjpubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjpubjK+)}(hconst struct drm_color_lut *luth](j>)}(hj=\h]hconst}(hj qhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjqubjP)}(h h]h }(hjqhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqubj>)}(hjAh]hstruct}(hj%qhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjqubjP)}(h h]h }(hj2qhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqubh)}(hhh]jg)}(h drm_color_luth]h drm_color_lut}(hjCqhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj@qubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjEqmodnameN classnameNj'j*)}j-]jpc.__set_output_tfasbuh1hhjqubjP)}(h h]h }(hjaqhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqubj+)}(hj+h]h*}(hjoqhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjqubjg)}(hluth]hlut}(hj|qhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjqubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjpubjK+)}(huint32_t lut_sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hjqhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjqubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjqmodnameN classnameNj'j*)}j-]jpc.__set_output_tfasbuh1hhjqubjP)}(h h]h }(hjqhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqubjg)}(hlut_sizeh]hlut_size}(hjqhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjqubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjpubjK+)}(h bool has_romh](j +)}(hj>ah]hbool}(hjqhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjqubjP)}(h h]h }(hjqhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjqubjg)}(hhas_romh]hhas_rom}(hjqhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjqubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjpubeh}(h]h ]h"]h$]h&]j~juh1jD+hjWphhhjiphMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjSphhhjiphMubah}(h]jNpah ](jjeh"]h$]h&]jj)jhuh1j1hjiphMhjPphhubj)}(hhh]h)}(hFcalculates the output transfer function based on expected input space.h]hFcalculates the output transfer function based on expected input space.}(hj"rhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjrhhubah}(h]h ]h"]h$]h&]uh1jhjPphhhjiphMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj:rjj:rjjjuh1j,hhhj9UhNhNubj)}(hX6**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjDrh]h Parameters}(hjFrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBrubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj>rubj)}(hhh](j )}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjcrh]hstruct dc_transfer_func *func}(hjerhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjarubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj]rubj-)}(hhh]h)}(htransfer functionh]htransfer function}(hj|rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxrhMhjyrubah}(h]h ]h"]h$]h&]uh1j,hj]rubeh}(h]h ]h"]h$]h&]uh1j hjxrhMhjZrubj )}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjrh]hconst struct drm_color_lut *lut}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjrubj-)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j,hjrubeh}(h]h ]h"]h$]h&]uh1j hjrhMhjZrubj )}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjrh]huint32_t lut_size}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjrubj-)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j,hjrubeh}(h]h ]h"]h$]h&]uh1j hjrhMhjZrubj )}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hjsh]h bool has_rom}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhj subah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjsubj-)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hj'shhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#shMhj$subah}(h]h ]h"]h$]h&]uh1j,hjsubeh}(h]h ]h"]h$]h&]uh1j hj#shMhjZrubeh}(h]h ]h"]h$]h&]uh1jhj>rubh)}(h **Return**h]j)}(hjIsh]hReturn}(hjKshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGsubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj>rubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hj_shhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj>rubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__set_output_tf_32 (C function)c.__set_output_tf_32hNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hzint __set_output_tf_32 (struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h]j8)}(hyint __set_output_tf_32(struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h](j +)}(hinth]hint}(hjshhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjshhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hjshhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjshhhjshMubja)}(h__set_output_tf_32h]jg)}(h__set_output_tf_32h]h__set_output_tf_32}(hjshhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjsubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjshhhjshMubjE+)}(hc(struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h](jK+)}(hstruct dc_transfer_func *funch](j>)}(hjAh]hstruct}(hjshhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjsubjP)}(h h]h }(hjshhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjsubh)}(hhh]jg)}(hdc_transfer_funch]hdc_transfer_func}(hjshhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjsmodnameN classnameNj'j*)}j-]j+)}j+jssbc.__set_output_tf_32asbuh1hhjsubjP)}(h h]h }(hj thhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjsubj+)}(hj+h]h*}(hjthhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjsubjg)}(hfunch]hfunc}(hj$thhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjsubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjsubjK+)}(h!const struct drm_color_lut32 *luth](j>)}(hj=\h]hconst}(hj=thhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj9tubjP)}(h h]h }(hjJthhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj9tubj>)}(hjAh]hstruct}(hjXthhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj9tubjP)}(h h]h }(hjethhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj9tubh)}(hhh]jg)}(hdrm_color_lut32h]hdrm_color_lut32}(hjvthhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjstubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjxtmodnameN classnameNj'j*)}j-]jtc.__set_output_tf_32asbuh1hhj9tubjP)}(h h]h }(hjthhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj9tubj+)}(hj+h]h*}(hjthhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj9tubjg)}(hluth]hlut}(hjthhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj9tubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjsubjK+)}(huint32_t lut_sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hjthhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjtubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjtmodnameN classnameNj'j*)}j-]jtc.__set_output_tf_32asbuh1hhjtubjP)}(h h]h }(hjthhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjtubjg)}(hlut_sizeh]hlut_size}(hjthhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjtubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjsubjK+)}(h bool has_romh](j +)}(hj>ah]hbool}(hjuhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj uubjP)}(h h]h }(hjuhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj uubjg)}(hhas_romh]hhas_rom}(hj+uhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj uubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjsubeh}(h]h ]h"]h$]h&]j~juh1jD+hjshhhjshMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjshhhjshMubah}(h]jsah ](jjeh"]h$]h&]jj)jhuh1j1hjshMhjshhubj)}(hhh]h)}(hFcalculates the output transfer function based on expected input space.h]hFcalculates the output transfer function based on expected input space.}(hjUuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRuhhubah}(h]h ]h"]h$]h&]uh1jhjshhhjshMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjmujjmujjjuh1j,hhhj9UhNhNubj)}(hX8**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut32 *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjwuh]h Parameters}(hjyuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuuubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjquubj)}(hhh](j )}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjuh]hstruct dc_transfer_func *func}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjuubj-)}(hhh]h)}(htransfer functionh]htransfer function}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjuubah}(h]h ]h"]h$]h&]uh1j,hjuubeh}(h]h ]h"]h$]h&]uh1j hjuhMhjuubj )}(hP``const struct drm_color_lut32 *lut`` lookup table that defines the color space h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hjuh]h!const struct drm_color_lut32 *lut}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjuubj-)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjuubah}(h]h ]h"]h$]h&]uh1j,hjuubeh}(h]h ]h"]h$]h&]uh1j hjuhMhjuubj )}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjvh]huint32_t lut_size}(hj vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjvubj-)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hj!vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjvubah}(h]h ]h"]h$]h&]uh1j,hjvubeh}(h]h ]h"]h$]h&]uh1j hjvhMhjuubj )}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hjAvh]h bool has_rom}(hjCvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?vubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj;vubj-)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjZvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVvhMhjWvubah}(h]h ]h"]h$]h&]uh1j,hj;vubeh}(h]h ]h"]h$]h&]uh1j hjVvhMhjuubeh}(h]h ]h"]h$]h&]uh1jhjquubh)}(h **Return**h]j)}(hj|vh]hReturn}(hj~vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzvubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjquubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjquubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__set_input_tf (C function)c.__set_input_tfhNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hint __set_input_tf (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h]j8)}(hint __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](j +)}(hinth]hint}(hjvhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjvhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM9ubjP)}(h h]h }(hjvhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjvhhhjvhM9ubja)}(h__set_input_tfh]jg)}(h__set_input_tfh]h__set_input_tf}(hjvhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjvubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjvhhhjvhM9ubjE+)}(ho(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](jK+)}(hstruct dc_color_caps *capsh](j>)}(hjAh]hstruct}(hjvhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjvubjP)}(h h]h }(hj whhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjvubh)}(hhh]jg)}(h dc_color_capsh]h dc_color_caps}(hjwhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjwmodnameN classnameNj'j*)}j-]j+)}j+jvsbc.__set_input_tfasbuh1hhjvubjP)}(h h]h }(hj)}(hjAh]hstruct}(hjpwhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjlwubjP)}(h h]h }(hj}whhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjlwubh)}(hhh]jg)}(hdc_transfer_funch]hdc_transfer_func}(hjwhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjwubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjwmodnameN classnameNj'j*)}j-]j8wc.__set_input_tfasbuh1hhjlwubjP)}(h h]h }(hjwhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjlwubj+)}(hj+h]h*}(hjwhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjlwubjg)}(hfunch]hfunc}(hjwhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjlwubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjvubjK+)}(hconst struct drm_color_lut *luth](j>)}(hj=\h]hconst}(hjwhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjwubjP)}(h h]h }(hjwhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjwubj>)}(hjAh]hstruct}(hjwhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjwubjP)}(h h]h }(hjxhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjwubh)}(hhh]jg)}(h drm_color_luth]h drm_color_lut}(hjxhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjxubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjxmodnameN classnameNj'j*)}j-]j8wc.__set_input_tfasbuh1hhjwubjP)}(h h]h }(hj7xhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjwubj+)}(hj+h]h*}(hjExhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjwubjg)}(hluth]hlut}(hjRxhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjwubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjvubjK+)}(huint32_t lut_sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hjnxhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjkxubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjpxmodnameN classnameNj'j*)}j-]j8wc.__set_input_tfasbuh1hhjgxubjP)}(h h]h }(hjxhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjgxubjg)}(hlut_sizeh]hlut_size}(hjxhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjgxubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjvubeh}(h]h ]h"]h$]h&]j~juh1jD+hjvhhhjvhM9ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjvhhhjvhM9ubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j1hjvhM9hjvhhubj)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM9hjxhhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhM9ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjxjjxjjjuh1j,hhhj9UhNhNubj)}(hX4**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjxh]h Parameters}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM=hjxubj)}(hhh](j )}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hjyh]hstruct dc_color_caps *caps}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM;hjxubj-)}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhM;hjyubah}(h]h ]h"]h$]h&]uh1j,hjxubeh}(h]h ]h"]h$]h&]uh1j hjyhM;hjxubj )}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hj>yh]hstruct dc_transfer_func *func}(hj@yhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhjyubj-)}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhM>hjyubah}(h]h ]h"]h$]h&]uh1j,hjyubeh}(h]h ]h"]h$]h&]uh1j hjyhM>hjxubeh}(h]h ]h"]h$]h&]uh1jhjxubh)}(h **Return**h]j)}(hjyh]hReturn}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM@hjxubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM@hjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__set_input_tf_32 (C function)c.__set_input_tf_32hNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hint __set_input_tf_32 (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h]j8)}(hint __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h](j +)}(hinth]hint}(hj0zhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj,zhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM_ubjP)}(h h]h }(hj?zhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj,zhhhj>zhM_ubja)}(h__set_input_tf_32h]jg)}(h__set_input_tf_32h]h__set_input_tf_32}(hjQzhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjMzubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj,zhhhj>zhM_ubjE+)}(hq(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h](jK+)}(hstruct dc_color_caps *capsh](j>)}(hjAh]hstruct}(hjmzhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjizubjP)}(h h]h }(hjzzhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjizubh)}(hhh]jg)}(h dc_color_capsh]h dc_color_caps}(hjzhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjzmodnameN classnameNj'j*)}j-]j+)}j+jSzsbc.__set_input_tf_32asbuh1hhjizubjP)}(h h]h }(hjzhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjizubj+)}(hj+h]h*}(hjzhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjizubjg)}(hcapsh]hcaps}(hjzhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjizubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjezubjK+)}(hstruct dc_transfer_func *funch](j>)}(hjAh]hstruct}(hjzhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjzubjP)}(h h]h }(hjzhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjzubh)}(hhh]jg)}(hdc_transfer_funch]hdc_transfer_func}(hjzhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjzubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjzmodnameN classnameNj'j*)}j-]jzc.__set_input_tf_32asbuh1hhjzubjP)}(h h]h }(hj{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjzubj+)}(hj+h]h*}(hj){hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjzubjg)}(hfunch]hfunc}(hj6{hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjzubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjezubjK+)}(h!const struct drm_color_lut32 *luth](j>)}(hj=\h]hconst}(hjO{hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjK{ubjP)}(h h]h }(hj\{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjK{ubj>)}(hjAh]hstruct}(hjj{hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjK{ubjP)}(h h]h }(hjw{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjK{ubh)}(hhh]jg)}(hdrm_color_lut32h]hdrm_color_lut32}(hj{hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj{modnameN classnameNj'j*)}j-]jzc.__set_input_tf_32asbuh1hhjK{ubjP)}(h h]h }(hj{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjK{ubj+)}(hj+h]h*}(hj{hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjK{ubjg)}(hluth]hlut}(hj{hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjK{ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjezubjK+)}(huint32_t lut_sizeh](h)}(hhh]jg)}(huint32_th]huint32_t}(hj{hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj{modnameN classnameNj'j*)}j-]jzc.__set_input_tf_32asbuh1hhj{ubjP)}(h h]h }(hj{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj{ubjg)}(hlut_sizeh]hlut_size}(hj |hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj{ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjezubeh}(h]h ]h"]h$]h&]j~juh1jD+hj,zhhhj>zhM_ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj(zhhhj>zhM_ubah}(h]j#zah ](jjeh"]h$]h&]jj)jhuh1j1hj>zhM_hj%zhhubj)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hj3|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM_hj0|hhubah}(h]h ]h"]h$]h&]uh1jhj%zhhhj>zhM_ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjK|jjK|jjjuh1j,hhhj9UhNhNubj)}(hX6**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut32 *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjU|h]h Parameters}(hjW|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS|ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMchjO|ubj)}(hhh](j )}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hjt|h]hstruct dc_color_caps *caps}(hjv|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr|ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMahjn|ubj-)}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMahj|ubah}(h]h ]h"]h$]h&]uh1j,hjn|ubeh}(h]h ]h"]h$]h&]uh1j hj|hMahjk|ubj )}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hj|h]hstruct dc_transfer_func *func}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMbhj|ubj-)}(hhh]h)}(htransfer functionh]htransfer function}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMbhj|ubah}(h]h ]h"]h$]h&]uh1j,hj|ubeh}(h]h ]h"]h$]h&]uh1j hj|hMbhjk|ubj )}(hP``const struct drm_color_lut32 *lut`` lookup table that defines the color space h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hj|h]h!const struct drm_color_lut32 *lut}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMchj|ubj-)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMchj|ubah}(h]h ]h"]h$]h&]uh1j,hj|ubeh}(h]h ]h"]h$]h&]uh1j hj|hMchjk|ubj )}(h.``uint32_t lut_size`` size of respective lut. h](j)}(h``uint32_t lut_size``h]j)}(hj}h]huint32_t lut_size}(hj!}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMdhj}ubj-)}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hj8}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4}hMdhj5}ubah}(h]h ]h"]h$]h&]uh1j,hj}ubeh}(h]h ]h"]h$]h&]uh1j hj4}hMdhjk|ubeh}(h]h ]h"]h$]h&]uh1jhjO|ubh)}(h **Return**h]j)}(hjZ}h]hReturn}(hj\}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX}ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMfhjO|ubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjp}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMfhjO|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'(amdgpu_dm_verify_lut3d_size (C function)c.amdgpu_dm_verify_lut3d_sizehNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(haint amdgpu_dm_verify_lut3d_size (struct amdgpu_device *adev, struct drm_plane_state *plane_state)h]j8)}(h`int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](j +)}(hinth]hint}(hj}hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj}hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hj}hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj}hhhj}hMubja)}(hamdgpu_dm_verify_lut3d_sizeh]jg)}(hamdgpu_dm_verify_lut3d_sizeh]hamdgpu_dm_verify_lut3d_size}(hj}hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj}ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj}hhhj}hMubjE+)}(hA(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](jK+)}(hstruct amdgpu_device *adevh](j>)}(hjAh]hstruct}(hj}hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj}ubjP)}(h h]h }(hj}hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj}ubh)}(hhh]jg)}(h amdgpu_deviceh]h amdgpu_device}(hj}hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj}ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj}modnameN classnameNj'j*)}j-]j+)}j+j}sbc.amdgpu_dm_verify_lut3d_sizeasbuh1hhj}ubjP)}(h h]h }(hj~hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj}ubj+)}(hj+h]h*}(hj(~hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj}ubjg)}(hadevh]hadev}(hj5~hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj}ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj}ubjK+)}(h#struct drm_plane_state *plane_stateh](j>)}(hjAh]hstruct}(hjN~hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjJ~ubjP)}(h h]h }(hj[~hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjJ~ubh)}(hhh]jg)}(hdrm_plane_stateh]hdrm_plane_state}(hjl~hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhji~ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjn~modnameN classnameNj'j*)}j-]j~c.amdgpu_dm_verify_lut3d_sizeasbuh1hhjJ~ubjP)}(h h]h }(hj~hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjJ~ubj+)}(hj+h]h*}(hj~hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjJ~ubjg)}(h plane_stateh]h plane_state}(hj~hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjJ~ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj}ubeh}(h]h ]h"]h$]h&]j~juh1jD+hj}hhhj}hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj}hhhj}hMubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1j1hj}hMhj}hhubj)}(hhh]h)}(hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported sizeh]hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported size}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~hhubah}(h]h ]h"]h$]h&]uh1jhj}hhhj}hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj~jj~jjjuh1j,hhhj9UhNhNubj)}(hXX**Parameters** ``struct amdgpu_device *adev`` amdgpu device ``struct drm_plane_state *plane_state`` the DRM plane state **Description** Verifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size. **Return** 0 on success. -EINVAL if lut size are invalid.h](h)}(h**Parameters**h]j)}(hj~h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~ubj)}(hhh](j )}(h-``struct amdgpu_device *adev`` amdgpu device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjh]hstruct amdgpu_device *adev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj ubj-)}(hhh]h)}(h amdgpu deviceh]h amdgpu device}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj&ubah}(h]h ]h"]h$]h&]uh1j,hj ubeh}(h]h ]h"]h$]h&]uh1j hj%hMhjubj )}(h<``struct drm_plane_state *plane_state`` the DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hjIh]h#struct drm_plane_state *plane_state}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjCubj-)}(hhh]h)}(hthe DRM plane stateh]hthe DRM plane state}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hMhj_ubah}(h]h ]h"]h$]h&]uh1j,hjCubeh}(h]h ]h"]h$]h&]uh1j hj^hMhjubeh}(h]h ]h"]h$]h&]uh1jhj~ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~ubh)}(hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.h]hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~ubh)}(h.0 on success. -EINVAL if lut size are invalid.h]h.0 on success. -EINVAL if lut size are invalid.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j''amdgpu_dm_verify_lut_sizes (C function)c.amdgpu_dm_verify_lut_sizeshNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hHint amdgpu_dm_verify_lut_sizes (const struct drm_crtc_state *crtc_state)h]j8)}(hGint amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)h](j +)}(hinth]hint}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMubja)}(hamdgpu_dm_verify_lut_sizesh]jg)}(hamdgpu_dm_verify_lut_sizesh]hamdgpu_dm_verify_lut_sizes}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMubjE+)}(h)(const struct drm_crtc_state *crtc_state)h]jK+)}(h'const struct drm_crtc_state *crtc_stateh](j>)}(hj=\h]hconst}(hj-hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj)ubjP)}(h h]h }(hj:hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj)ubj>)}(hjAh]hstruct}(hjHhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj)ubjP)}(h h]h }(hjUhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj)ubh)}(hhh]jg)}(hdrm_crtc_stateh]hdrm_crtc_state}(hjfhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjcubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjhmodnameN classnameNj'j*)}j-]j+)}j+jsbc.amdgpu_dm_verify_lut_sizesasbuh1hhj)ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj)ubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj)ubjg)}(h crtc_stateh]h crtc_state}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj)ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj%ubah}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhMhjhhubj)}(hhh]h)}(h1verifies if DRM luts match the hw supported sizesh]h1verifies if DRM luts match the hw supported sizes}(hjˀhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjȀhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhj9UhNhNubj)}(hX **Parameters** ``const struct drm_crtc_state *crtc_state`` the DRM CRTC state **Description** Verifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size. **Return** 0 on success. -EINVAL if any lut sizes are invalid.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubj)}(hhh]j )}(h?``const struct drm_crtc_state *crtc_state`` the DRM CRTC state h](j)}(h+``const struct drm_crtc_state *crtc_state``h]j)}(hj h]h'const struct drm_crtc_state *crtc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubj-)}(hhh]h)}(hthe DRM CRTC stateh]hthe DRM CRTC state}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMhj"ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj!hMhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjGh]h Description}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(hgVerifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size.h](h9Verifies that the Degamma and Gamma LUTs attached to the }(hj]hhhNhNubh)}(h:c:type:`crtc_state`h]j)}(hjgh]h crtc_state}(hjihhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  crtc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj]ubh are of the expected size.}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(h30 on success. -EINVAL if any lut sizes are invalid.h]h30 on success. -EINVAL if any lut sizes are invalid.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j',amdgpu_dm_check_crtc_color_mgmt (C function)!c.amdgpu_dm_check_crtc_color_mgmthNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hQint amdgpu_dm_check_crtc_color_mgmt (struct dm_crtc_state *crtc, bool check_only)h]j8)}(hPint amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, bool check_only)h](j +)}(hinth]hint}(hjցhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjҁhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjҁhhhjhMubja)}(hamdgpu_dm_check_crtc_color_mgmth]jg)}(hamdgpu_dm_check_crtc_color_mgmth]hamdgpu_dm_check_crtc_color_mgmt}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjҁhhhjhMubjE+)}(h-(struct dm_crtc_state *crtc, bool check_only)h](jK+)}(hstruct dm_crtc_state *crtch](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(h dm_crtc_stateh]h dm_crtc_state}(hj1hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj.ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj3modnameN classnameNj'j*)}j-]j+)}j+jsb!c.amdgpu_dm_check_crtc_color_mgmtasbuh1hhjubjP)}(h h]h }(hjQhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hj_hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hcrtch]hcrtc}(hjlhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj ubjK+)}(hbool check_onlyh](j +)}(hj>ah]hbool}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubjg)}(h check_onlyh]h check_only}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj ubeh}(h]h ]h"]h$]h&]j~juh1jD+hjҁhhhjhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj΁hhhjhMubah}(h]jɁah ](jjeh"]h$]h&]jj)jhuh1j1hjhMhjˁhhubj)}(hhh]h)}(h0Check if DRM color props are programmable by DC.h]h0Check if DRM color props are programmable by DC.}(hjʂhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjǂhhubah}(h]h ]h"]h$]h&]uh1jhjˁhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhj9UhNhNubj)}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``bool check_only`` only check color state without update dc stream **Description** This function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block. The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM. For supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together. **Return** 0 on success. Error code if validation fails.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubj)}(hhh](j )}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hj h]hstruct dm_crtc_state *crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubj-)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj!ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj hMhjubj )}(hD``bool check_only`` only check color state without update dc stream h](j)}(h``bool check_only``h]j)}(hjDh]hbool check_only}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj>ubj-)}(hhh]h)}(h/only check color state without update dc streamh]h/only check color state without update dc stream}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhjZubah}(h]h ]h"]h$]h&]uh1j,hj>ubeh}(h]h ]h"]h$]h&]uh1j hjYhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(hXThis function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block.h]hXThis function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(h~The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM.h]hThe RGM block is typically more fully featured and accurate across all ASICs - DCE can’t support a custom non-linear CRTC DGM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together.h]hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(h **Return**h]j)}(hjăh]hReturn}(hjƃhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƒubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubh)}(h-0 on success. Error code if validation fails.h]h-0 on success. Error code if validation fails.}(hjڃhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'-amdgpu_dm_update_crtc_color_mgmt (C function)"c.amdgpu_dm_update_crtc_color_mgmthNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hAint amdgpu_dm_update_crtc_color_mgmt (struct dm_crtc_state *crtc)h]j8)}(h@int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)h](j +)}(hinth]hint}(hj hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMAubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMAubja)}(h amdgpu_dm_update_crtc_color_mgmth]jg)}(h amdgpu_dm_update_crtc_color_mgmth]h amdgpu_dm_update_crtc_color_mgmt}(hj*hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj&ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMAubjE+)}(h(struct dm_crtc_state *crtc)h]jK+)}(hstruct dm_crtc_state *crtch](j>)}(hjAh]hstruct}(hjFhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjBubjP)}(h h]h }(hjShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjBubh)}(hhh]jg)}(h dm_crtc_stateh]h dm_crtc_state}(hjdhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjaubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjfmodnameN classnameNj'j*)}j-]j+)}j+j,sb"c.amdgpu_dm_update_crtc_color_mgmtasbuh1hhjBubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjBubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjBubjg)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjBubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hj>ubah}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjhMAubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhMAubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhMAhjhhubj)}(hhh]h)}(h'Maps DRM color management to DC stream.h]h'Maps DRM color management to DC stream.}(hjɄhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMAhjƄhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMAubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhj9UhNhNubj)}(hXO**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state **Description** With no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM. - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. - The CRTC CTM will be placed in the gamut remap block if it is non-linear. The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM. For supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together. **Return** 0 on success. Error code if setup fails.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMEhjubj)}(hhh]j )}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hj h]hstruct dm_crtc_state *crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMBhjubj-)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMBhj ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMBhjubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjEh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMDhjubh)}(hWith no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.h]hWith no plane level color management properties we’re free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMChjubh)}(hhh](h)}(hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.h]h)}(hjoh]hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMGhjmubah}(h]h ]h"]h$]h&]uh1hhjjubh)}(hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.h]h)}(hjh]hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMHhjubah}(h]h ]h"]h$]h&]uh1hhjjubh)}(hJThe CRTC CTM will be placed in the gamut remap block if it is non-linear. h]h)}(hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.h]hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMIhjubah}(h]h ]h"]h$]h&]uh1hhjjubeh}(h]h ]h"]h$]h&]jU-jV-uh1hhj~hMGhjubh)}(h~The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM.h]hThe RGM block is typically more fully featured and accurate across all ASICs - DCE can’t support a custom non-linear CRTC DGM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMKhjubh)}(hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.h]hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.}(hj˅hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMNhjubh)}(h **Return**h]j)}(hj܅h]hReturn}(hjޅhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjڅubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMRhjubh)}(h(0 on success. Error code if setup fails.h]h(0 on success. Error code if setup fails.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMShjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'.amdgpu_dm_update_plane_color_mgmt (C function)#c.amdgpu_dm_update_plane_color_mgmthNtauh1jhj9UhhhNhNubj-)}(hhh](j2)}(hint amdgpu_dm_update_plane_color_mgmt (struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h]j8)}(hint amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](j +)}(hinth]hint}(hj!hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM ubjP)}(h h]h }(hj0hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhj/hM ubja)}(h!amdgpu_dm_update_plane_color_mgmth]jg)}(h!amdgpu_dm_update_plane_color_mgmth]h!amdgpu_dm_update_plane_color_mgmt}(hjBhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj>ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhj/hM ubjE+)}(hh(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](jK+)}(hstruct dm_crtc_state *crtch](j>)}(hjAh]hstruct}(hj^hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjZubjP)}(h h]h }(hjkhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjZubh)}(hhh]jg)}(h dm_crtc_stateh]h dm_crtc_state}(hj|hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjyubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj~modnameN classnameNj'j*)}j-]j+)}j+jDsb#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhjZubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjZubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjZubjg)}(hcrtch]hcrtc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjZubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjVubjK+)}(h#struct drm_plane_state *plane_stateh](j>)}(hjAh]hstruct}(hjІhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj̆ubjP)}(h h]h }(hj݆hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj̆ubh)}(hhh]jg)}(hdrm_plane_stateh]hdrm_plane_state}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhj̆ubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj̆ubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj̆ubjg)}(h plane_stateh]h plane_state}(hj'hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj̆ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjVubjK+)}(h%struct dc_plane_state *dc_plane_stateh](j>)}(hjAh]hstruct}(hj@hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj<ubjP)}(h h]h }(hjMhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj<ubh)}(hhh]jg)}(hdc_plane_stateh]hdc_plane_state}(hj^hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj`modnameN classnameNj'j*)}j-]j#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhj<ubjP)}(h h]h }(hj|hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj<ubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj<ubjg)}(hdc_plane_stateh]hdc_plane_state}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj<ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjVubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhj/hM ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhj/hM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hj/hM hjhhubj)}(hhh]h)}(h&Maps DRM color management to DC plane.h]h&Maps DRM color management to DC plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj/hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjهjjهjjjuh1j,hhhj9UhNhNubj)}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``struct drm_plane_state *plane_state`` DRM plane state ``struct dc_plane_state *dc_plane_state`` target DC surface **Description** Update the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management. **Return** 0 on success. -ENOMEM if mem allocation fails.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj݇ubj)}(hhh](j )}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hjh]hstruct dm_crtc_state *crtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjubj-)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM hjubj )}(h8``struct drm_plane_state *plane_state`` DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hj;h]h#struct drm_plane_state *plane_state}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj5ubj-)}(hhh]h)}(hDRM plane stateh]hDRM plane state}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM hjQubah}(h]h ]h"]h$]h&]uh1j,hj5ubeh}(h]h ]h"]h$]h&]uh1j hjPhM hjubj )}(h<``struct dc_plane_state *dc_plane_state`` target DC surface h](j)}(h)``struct dc_plane_state *dc_plane_state``h]j)}(hjth]h%struct dc_plane_state *dc_plane_state}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hjnubj-)}(hhh]h)}(htarget DC surfaceh]htarget DC surface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjnubeh}(h]h ]h"]h$]h&]uh1j hjhM hjubeh}(h]h ]h"]h$]h&]uh1jhj݇ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj݇ubh)}(hUpdate the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.h]hUpdate the underlying dc_stream_state’s input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.}(hjňhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj݇ubh)}(h **Return**h]j)}(hjֈh]hReturn}(hj؈hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԈubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj݇ubh)}(h.0 on success. -ENOMEM if mem allocation fails.h]h.0 on success. -ENOMEM if mem allocation fails.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:53: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj݇ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9UhhhNhNubh)}(hhh](h)}(h-DC Color Capabilities between DCN generationsh]h-DC Color Capabilities between DCN generations}(hjhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjhhhhhK:ubh)}(hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.h]hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)}(hjAh]hstruct}(hjmhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjihhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKQubjP)}(h h]h }(hj{hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjihhhjzhKQubja)}(hrom_curve_capsh]jg)}(hjgh]hrom_curve_caps}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjihhhjzhKQubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjehhhjzhKQubah}(h]j`ah ](jjeh"]h$]h&]jj)jhuh1j1hjzhKQhjbhhubj)}(hhh]h)}(h9predefined transfer function caps for degamma and regammah]h9predefined transfer function caps for degamma and regamma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjzhKQubeh}(h]h ](jstructeh"]h$]h&]jjjjNJjjNJjjjuh1j,hhhjhNhNubj)}(hX**Definition**:: struct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; }; **Members** ``srgb`` RGB color space transfer func ``bt2020`` BT.2020 transfer func ``gamma2_2`` standard gamma ``pq`` perceptual quantizer transfer function ``hlg`` hybrid log–gamma transfer functionh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjӊhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϊubh:}(hjϊhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjˊubj)}(hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };h]hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjˊubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjˊubj)}(hhh](j )}(h'``srgb`` RGB color space transfer func h](j)}(h``srgb``h]j)}(hjh]hsrgb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(hRGB color space transfer funch]hRGB color space transfer func}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hKhj2ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj1hKhjubj )}(h!``bt2020`` BT.2020 transfer func h](j)}(h ``bt2020``h]j)}(hjUh]hbt2020}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjOubj-)}(hhh]h)}(hBT.2020 transfer funch]hBT.2020 transfer func}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKhjkubah}(h]h ]h"]h$]h&]uh1j,hjOubeh}(h]h ]h"]h$]h&]uh1j hjjhKhjubj )}(h``gamma2_2`` standard gamma h](j)}(h ``gamma2_2``h]j)}(hjh]hgamma2_2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(hstandard gammah]hstandard gamma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h.``pq`` perceptual quantizer transfer function h](j)}(h``pq``h]j)}(hjNjh]hpq}(hjɋhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjŋubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h&perceptual quantizer transfer functionh]h&perceptual quantizer transfer function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj܋hKhj݋ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj܋hKhjubj )}(h,``hlg`` hybrid log–gamma transfer functionh](j)}(h``hlg``h]j)}(hjh]hhlg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h$hybrid log–gamma transfer functionh]h$hybrid log–gamma transfer function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjˊubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpp_color_caps (C struct)c.dpp_color_capshNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdpp_color_capsh]j8)}(hstruct dpp_color_capsh](j>)}(hjAh]hstruct}(hjZhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjVhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKubjP)}(h h]h }(hjhhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjVhhhjghKubja)}(hdpp_color_capsh]jg)}(hjTh]hdpp_color_caps}(hjzhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjvubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjVhhhjghKubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjRhhhjghKubah}(h]jMah ](jjeh"]h$]h&]jj)jhuh1j1hjghKhjOhhubj)}(hhh]h)}(h=color pipeline capabilities for display pipe and plane blocksh]h=color pipeline capabilities for display pipe and plane blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjOhhhjghKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX**Definition**:: struct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; uint16_t upsp_pre_scaler : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; }; **Members** ``dcn_arch`` all DCE generations treated the same ``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup ``icsc`` input color space conversion ``dgam_ram`` programmable degamma LUT ``post_csc`` post color space conversion, before gamut remap ``gamma_corr`` degamma correction ``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag ``ogam_ram`` programmable out/blend gamma LUT ``ocsc`` output color space conversion ``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes ``upsp_pre_scaler`` Ability to upsample 420/422 before scaling ``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; uint16_t upsp_pre_scaler : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };h]hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; uint16_t upsp_pre_scaler : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };}hjٌsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(h2``dcn_arch`` all DCE generations treated the same h](j)}(h ``dcn_arch``h]j)}(hj h]hdcn_arch}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h$all DCE generations treated the sameh]h$all DCE generations treated the same}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(hj``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup h](j)}(h``input_lut_shared``h]j)}(hjBh]hinput_lut_shared}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj<ubj-)}(hhh]h)}(hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookuph]hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjXubah}(h]h ]h"]h$]h&]uh1j,hj<ubeh}(h]h ]h"]h$]h&]uh1j hjWhKhjubj )}(h&``icsc`` input color space conversion h](j)}(h``icsc``h]j)}(hj|h]hicsc}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjvubj-)}(hhh]h)}(hinput color space conversionh]hinput color space conversion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjvubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h&``dgam_ram`` programmable degamma LUT h](j)}(h ``dgam_ram``h]j)}(hjh]hdgam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(hprogrammable degamma LUTh]hprogrammable degamma LUT}(hj΍hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʍhKhjˍubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjʍhKhjubj )}(h=``post_csc`` post color space conversion, before gamut remap h](j)}(h ``post_csc``h]j)}(hjh]hpost_csc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h/post color space conversion, before gamut remaph]h/post color space conversion, before gamut remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h"``gamma_corr`` degamma correction h](j)}(h``gamma_corr``h]j)}(hj'h]h gamma_corr}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj!ubj-)}(hhh]h)}(hdegamma correctionh]hdegamma correction}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hKhj=ubah}(h]h ]h"]h$]h&]uh1j,hj!ubeh}(h]h ]h"]h$]h&]uh1j hj<hKhjubj )}(hz``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag h](j)}(h ``hw_3d_lut``h]j)}(hj`h]h hw_3d_lut}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjZubj-)}(hhh]h)}(hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flagh]hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjvubah}(h]h ]h"]h$]h&]uh1j,hjZubeh}(h]h ]h"]h$]h&]uh1j hjuhKhjubj )}(h.``ogam_ram`` programmable out/blend gamma LUT h](j)}(h ``ogam_ram``h]j)}(hjh]hogam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h programmable out/blend gamma LUTh]h programmable out/blend gamma LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h'``ocsc`` output color space conversion h](j)}(h``ocsc``h]j)}(hjӎh]hocsc}(hjՎhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjюubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: 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./drivers/gpu/drm/amd/display/dc/dc.hhKhj?ubj-)}(hhh]h)}(h*Ability to upsample 420/422 before scalingh]h*Ability to upsample 420/422 before scaling}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhj[ubah}(h]h ]h"]h$]h&]uh1j,hj?ubeh}(h]h ]h"]h$]h&]uh1j hjZhKhjubj )}(h=``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT h](j)}(h``dgam_rom_caps``h]j)}(hj~h]h dgam_rom_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjxubj-)}(hhh]h)}(h*pre-definied curve caps for degamma 1D LUTh]h*pre-definied curve caps for degamma 1D LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j,hjxubeh}(h]h ]h"]h$]h&]uh1j hjhKhjubj )}(h<``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](j)}(h``ogam_rom_caps``h]j)}(hjh]h ogam_rom_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj-)}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hjЏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj͏ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj̏hKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubh)}(hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)h]hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'mpc_color_caps (C struct)c.mpc_color_capshNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hmpc_color_capsh]j8)}(hstruct mpc_color_capsh](j>)}(hjAh]hstruct}(hj8hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj4hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjFhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj4hhhjEhMubja)}(hmpc_color_capsh]jg)}(hj2h]hmpc_color_caps}(hjXhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjTubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj4hhhjEhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj0hhhjEhMubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1j1hjEhMhj-hhubj)}(hhh]h)}(hGcolor pipeline capabilities for multiple pipe and plane combined blocksh]hGcolor pipeline capabilities for multiple pipe and plane combined blocks}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM-hjwhhubah}(h]h ]h"]h$]h&]uh1jhj-hhhjEhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX***Definition**:: struct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; struct fixed31_32 max_gamut_remap_coeff; }; **Members** ``gamut_remap`` color transformation matrix ``ogam_ram`` programmable out gamma LUT ``ocsc`` output color space conversion matrix ``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT ``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT ``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT ``mcm_3d_lut_caps`` HW support cap for MCM LUT memory ``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory ``preblend`` whether color manager supports preblend with MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM1hjubj)}(hXstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; struct fixed31_32 max_gamut_remap_coeff; };h]hXstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; struct fixed31_32 max_gamut_remap_coeff; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM3hjubh)}(h **Members**h]j)}(hjȐh]hMembers}(hjʐhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƐubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMAhjubj)}(hhh](j )}(h,``gamut_remap`` color transformation matrix h](j)}(h``gamut_remap``h]j)}(hjh]h gamut_remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM1hjubj-)}(hhh]h)}(hcolor transformation matrixh]hcolor transformation matrix}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM1hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM1hjސubj )}(h(``ogam_ram`` programmable out gamma LUT h](j)}(h ``ogam_ram``h]j)}(hj h]hogam_ram}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM2hjubj-)}(hhh]h)}(hprogrammable out gamma LUTh]hprogrammable out gamma LUT}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hM2hj6ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj5hM2hjސubj )}(h.``ocsc`` output color space conversion matrix h](j)}(h``ocsc``h]j)}(hjYh]hocsc}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM3hjSubj-)}(hhh]h)}(h$output color space conversion matrixh]h$output color space conversion matrix}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhM3hjoubah}(h]h ]h"]h$]h&]uh1j,hjSubeh}(h]h ]h"]h$]h&]uh1j hjnhM3hjސubj )}(hA``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT h](j)}(h``num_3dluts``h]j)}(hjh]h num_3dluts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM4hjubj-)}(hhh]h)}(h1MPC 3D LUT; always assumes a preceding shaper LUTh]h1MPC 3D LUT; always assumes a preceding shaper LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM4hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM4hjސubj )}(hR``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT h](j)}(h``num_rmcm_3dluts``h]j)}(hjˑh]hnum_rmcm_3dluts}(hj͑hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɑubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM5hjőubj-)}(hhh]h)}(h=number of RMCM 3D LUTS; always assumes a preceding shaper LUTh]h=number of RMCM 3D LUTS; always assumes a preceding shaper LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM5hjubah}(h]h ]h"]h$]h&]uh1j,hjőubeh}(h]h ]h"]h$]h&]uh1j hjhM5hjސubj )}(hT``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance h](j)}(h``shared_3d_lut``h]j)}(hjh]h shared_3d_lut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM7hjubj-)}(hhh]h)}(hAshared 3D LUT flag. Can be either DPP or MPC, but single instanceh]hAshared 3D LUT flag. Can be either DPP or MPC, but single instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM6hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM7hjސubj )}(h=``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT h](j)}(h``ogam_rom_caps``h]j)}(hj>h]h ogam_rom_caps}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM83hj8ubj-)}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShM8hjTubah}(h]h ]h"]h$]h&]uh1j,hj8ubeh}(h]h ]h"]h$]h&]uh1j hjShM8hjސubj )}(h6``mcm_3d_lut_caps`` HW support cap for MCM LUT memory h](j)}(h``mcm_3d_lut_caps``h]j)}(hjwh]hmcm_3d_lut_caps}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM9hjqubj-)}(hhh]h)}(h!HW support cap for MCM LUT memoryh]h!HW support cap for MCM LUT memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM9hjubah}(h]h ]h"]h$]h&]uh1j,hjqubeh}(h]h ]h"]h$]h&]uh1j hjhM9hjސubj )}(h8``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory h](j)}(h``rmcm_3d_lut_caps``h]j)}(hjh]hrmcm_3d_lut_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM:hjubj-)}(hhh]h)}(h"HW support cap for RMCM LUT memoryh]h"HW support cap for RMCM LUT memory}(hjɒhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjŒhM:hjƒubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjŒhM:hjސubj )}(h=``preblend`` whether color manager supports preblend with MPCh](j)}(h ``preblend``h]j)}(hjh]hpreblend}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM:hjubj-)}(hhh]h)}(h0whether color manager supports preblend with MPCh]h0whether color manager supports preblend with MPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM;hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM:hjސubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_color_caps (C struct)c.dc_color_capshNtauh1jhjhhhNhNubj-)}(hhh](j2)}(h dc_color_capsh]j8)}(hstruct dc_color_capsh](j>)}(hjAh]hstruct}(hjChhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj?hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMAubjP)}(h h]h }(hjQhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj?hhhjPhMAubja)}(h dc_color_capsh]jg)}(hj=h]h dc_color_caps}(hjchhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj_ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj?hhhjPhMAubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj;hhhjPhMAubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1j1hjPhMAhj8hhubj)}(hhh]h)}(h2color pipes capabilities for DPP and MPC hw blocksh]h2color pipes capabilities for DPP and MPC hw blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMKhjhhubah}(h]h ]h"]h$]h&]uh1jhj8hhhjPhMAubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(h**Definition**:: struct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; }; **Members** ``dpp`` color pipes caps for DPP ``mpc`` color pipes caps for MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMOhjubj)}(hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };h]hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };}hj“sbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMQhjubh)}(h **Members**h]j)}(hjӓh]hMembers}(hjՓhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjѓubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMVhjubj)}(hhh](j )}(h!``dpp`` color pipes caps for DPP h](j)}(h``dpp``h]j)}(hjh]hdpp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMMhjubj-)}(hhh]h)}(hcolor pipes caps for DPPh]hcolor pipes caps for DPP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMMhjubj )}(h ``mpc`` color pipes caps for MPCh](j)}(h``mpc``h]j)}(hj+h]hmpc}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMMhj%ubj-)}(hhh]h)}(hcolor pipes caps for MPCh]hcolor pipes caps for MPC}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMNhjAubah}(h]h ]h"]h$]h&]uh1j,hj%ubeh}(h]h ]h"]h$]h&]uh1j hj@hMMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'pipe_split_policy (C enum)c.pipe_split_policyhNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hpipe_split_policyh]j8)}(henum pipe_split_policyh](j>)}(hj^8h]henum}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMTubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMTubja)}(hpipe_split_policyh]jg)}(hjh]hpipe_split_policy}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMTubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj}hhhjhMTubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1j1hjhMThjzhhubj)}(hhh]h)}(h$Pipe split strategy supported by DCNh]h$Pipe split strategy supported by DCN}(hjǔhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjĔhhubah}(h]h ]h"]h$]h&]uh1jhjzhhhjhMTubeh}(h]h ](jenumeh"]h$]h&]jjjjߔjjߔjjjuh1j,hhhjhNhNubj)}(hX**Constants** ``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. ``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. ``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](h)}(h **Constants**h]j)}(hjh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(h``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. h](j)}(h``MPC_SPLIT_DYNAMIC``h]j)}(hjh]hMPC_SPLIT_DYNAMIC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.h]hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hg``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. h](j)}(h``MPC_SPLIT_AVOID``h]j)}(hjBh]hMPC_SPLIT_AVOID}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj<ubj-)}(hhh]h)}(hRAvoid pipe split, which means that DC will not try any sort of split optimization.h]hRAvoid pipe split, which means that DC will not try any sort of split optimization.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjXubah}(h]h ]h"]h$]h&]uh1j,hj<ubeh}(h]h ]h"]h$]h&]uh1j hjWhMhjubj )}(h``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](j)}(h``MPC_SPLIT_AVOID_MULT_DISP``h]j)}(hj|h]hMPC_SPLIT_AVOID_MULT_DISP}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjvubj-)}(hhh]h)}(hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h]hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjvubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubh)}(hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.h]hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.}(hjՕhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'"dc_check_state_update (C function)c.dc_check_state_updatehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hstruct dc_update_descriptor dc_check_state_update (const struct dc_check_config *check_config, const struct dc_state_update *updates)h]j8)}(hstruct dc_update_descriptor dc_check_state_update(const struct dc_check_config *check_config, const struct dc_state_update *updates)h](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMfubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhj hMfubh)}(hhh]jg)}(hdc_update_descriptorh]hdc_update_descriptor}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+dc_check_state_updatesbc.dc_check_state_updateasbuh1hhjhhhj hMfubjP)}(h h]h }(hj=hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhj hMfubja)}(hdc_check_state_updateh]jg)}(hj:h]hdc_check_state_update}(hjOhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjKubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhj hMfubjE+)}(hS(const struct dc_check_config *check_config, const struct dc_state_update *updates)h](jK+)}(h*const struct dc_check_config *check_configh](j>)}(hj=\h]hconst}(hjjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjfubjP)}(h h]h }(hjwhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjfubj>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjfubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjfubh)}(hhh]jg)}(hdc_check_configh]hdc_check_config}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j8c.dc_check_state_updateasbuh1hhjfubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjfubj+)}(hj+h]h*}(hjϖhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjfubjg)}(h check_configh]h check_config}(hjܖhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjfubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjbubjK+)}(h%const struct dc_state_update *updatesh](j>)}(hj=\h]hconst}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_state_updateh]hdc_state_update}(hj.hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj0modnameN classnameNj'j*)}j-]j8c.dc_check_state_updateasbuh1hhjubjP)}(h h]h }(hjLhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjZhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hupdatesh]hupdates}(hjghhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjbubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhj hMfubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhj hMfubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hj hMfhjhhubj)}(hhh]h)}(h)Classify an update without committing it.h]h)Classify an update without committing it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMfhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMfubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(h**Parameters** ``const struct dc_check_config *check_config`` DC check configuration ``const struct dc_state_update *updates`` root update object to classify **Return** descriptor indicating update type and required lock scope.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMjhjubj)}(hhh](j )}(hF``const struct dc_check_config *check_config`` DC check configuration h](j)}(h.``const struct dc_check_config *check_config``h]j)}(hjҗh]h*const struct dc_check_config *check_config}(hjԗhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЗubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMghj̗ubj-)}(hhh]h)}(hDC check configurationh]hDC check configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMghjubah}(h]h ]h"]h$]h&]uh1j,hj̗ubeh}(h]h ]h"]h$]h&]uh1j hjhMghjɗubj )}(hI``const struct dc_state_update *updates`` root update object to classify h](j)}(h)``const struct dc_state_update *updates``h]j)}(hj h]h%const struct dc_state_update *updates}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhhjubj-)}(hhh]h)}(hroot update object to classifyh]hroot update object to classify}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhhj!ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj hMhhjɗubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h **Return**h]j)}(hjFh]hReturn}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMjhjubh)}(h:descriptor indicating update type and required lock scope.h]h:descriptor indicating update type and required lock scope.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMjhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_update_state (C function)c.dc_update_statehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hKbool dc_update_state (struct dc *dc, const struct dc_state_update *updates)h]j8)}(hJbool dc_update_state(struct dc *dc, const struct dc_state_update *updates)h](j +)}(hj>ah]hbool}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMqubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMqubja)}(hdc_update_stateh]jg)}(hdc_update_stateh]hdc_update_state}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMqubjE+)}(h6(struct dc *dc, const struct dc_state_update *updates)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjǘhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjØubjP)}(h h]h }(hjԘhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjØubh)}(hhh]jg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jsbc.dc_update_stateasbuh1hhjØubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjØubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjØubjg)}(hdch]hdc}(hj hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjØubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubjK+)}(h%const struct dc_state_update *updatesh](j>)}(hj=\h]hconst}(hj9hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj5ubjP)}(h h]h }(hjFhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj5ubj>)}(hjAh]hstruct}(hjThhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj5ubjP)}(h h]h }(hjahhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj5ubh)}(hhh]jg)}(hdc_state_updateh]hdc_state_update}(hjrhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjoubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjtmodnameN classnameNj'j*)}j-]jc.dc_update_stateasbuh1hhj5ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj5ubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj5ubjg)}(hupdatesh]hupdates}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj5ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjhMqubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhMqubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1j1hjhMqhjhhubj)}(hhh]h)}(h#Commit an absolute dc_state_update.h]h#Commit an absolute dc_state_update.}(hjՙhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMqhjҙhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMqubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(h**Parameters** ``struct dc *dc`` DC structure ``const struct dc_state_update *updates`` root update object carrying stream, plane, and probe updates **Return** true on success, false on failure.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMuhjubj)}(hhh](j )}(h``struct dc *dc`` DC structure h](j)}(h``struct dc *dc``h]j)}(hjh]h struct dc *dc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMrhjubj-)}(hhh]h)}(h DC structureh]h DC structure}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMrhj,ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj+hMrhj ubj )}(hg``const struct dc_state_update *updates`` root update object carrying stream, plane, and probe updates h](j)}(h)``const struct dc_state_update *updates``h]j)}(hjOh]h%const struct dc_state_update *updates}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMshjIubj-)}(hhh]h)}(h)}(hjAh]hstruct}(hjϚhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj˚hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM|ubjP)}(h h]h }(hjݚhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj˚hhhjܚhM|ubh)}(hhh]jg)}(hdc_update_scratch_spaceh]hdc_update_scratch_space}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+dc_update_state_initsbc.dc_update_state_initasbuh1hhj˚hhhjܚhM|ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj˚hhhjܚhM|ubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj˚hhhjܚhM|ubja)}(hdc_update_state_inith]jg)}(hj h]hdc_update_state_init}(hj.hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj*ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj˚hhhjܚhM|ubjE+)}(h6(struct dc *dc, const struct dc_state_update *updates)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjIhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjEubjP)}(h h]h }(hjVhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjEubh)}(hhh]jg)}(hdch]hdc}(hjghhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjdubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjimodnameN classnameNj'j*)}j-]j c.dc_update_state_initasbuh1hhjEubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjEubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjEubjg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjEubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjAubjK+)}(h%const struct dc_state_update *updatesh](j>)}(hj=\h]hconst}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjƛhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj>)}(hjAh]hstruct}(hjԛhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_state_updateh]hdc_state_update}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j c.dc_update_state_initasbuh1hhjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hupdatesh]hupdates}(hj+hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjAubeh}(h]h ]h"]h$]h&]j~juh1jD+hj˚hhhjܚhM|ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjǚhhhjܚhM|ubah}(h]jšah ](jjeh"]h$]h&]jj)jhuh1j1hjܚhM|hjĚhhubj)}(hhh]h)}(h/Acquire and initialise a commit scratch buffer.h]h/Acquire and initialise a commit scratch buffer.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM|hjRhhubah}(h]h ]h"]h$]h&]uh1jhjĚhhhjܚhM|ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjmjjmjjjuh1j,hhhjhNhNubj)}(hXo**Parameters** ``struct dc *dc`` DC structure ``const struct dc_state_update *updates`` update descriptor; validated before the slot is acquired **Return** a scratch slot on success, NULL if validation fails or the pool is exhausted. The slot must be released via dc_update_state_cleanup() on success, or automatically by dc_update_state_prepare() on failure.h](h)}(h**Parameters**h]j)}(hjwh]h Parameters}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubj)}(hhh](j )}(h``struct dc *dc`` DC structure h](j)}(h``struct dc *dc``h]j)}(hjh]h struct dc *dc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM}hjubj-)}(hhh]h)}(h DC structureh]h DC structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM}hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM}hjubj )}(hc``const struct dc_state_update *updates`` update descriptor; validated before the slot is acquired h](j)}(h)``const struct dc_state_update *updates``h]j)}(hjϜh]h%const struct dc_state_update *updates}(hjќhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͜ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM~hjɜubj-)}(hhh]h)}(h8update descriptor; validated before the slot is acquiredh]h8update descriptor; validated before the slot is acquired}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM~hjubah}(h]h ]h"]h$]h&]uh1j,hjɜubeh}(h]h ]h"]h$]h&]uh1j hjhM~hjubeh}(h]h ]h"]h$]h&]uh1jhjqubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubh)}(ha scratch slot on success, NULL if validation fails or the pool is exhausted. The slot must be released via dc_update_state_cleanup() on success, or automatically by dc_update_state_prepare() on failure.h]ha scratch slot on success, NULL if validation fails or the pool is exhausted. The slot must be released via dc_update_state_cleanup() on success, or automatically by dc_update_state_prepare() on failure.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'$dc_update_state_prepare (C function)c.dc_update_state_preparehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hFbool dc_update_state_prepare (struct dc_update_scratch_space *scratch)h]j8)}(hEbool dc_update_state_prepare(struct dc_update_scratch_space *scratch)h](j +)}(hj>ah]hbool}(hjOhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjKhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hj]hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjKhhhj\hMubja)}(hdc_update_state_prepareh]jg)}(hdc_update_state_prepareh]hdc_update_state_prepare}(hjohhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjkubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjKhhhj\hMubjE+)}(h)(struct dc_update_scratch_space *scratch)h]jK+)}(h'struct dc_update_scratch_space *scratchh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_update_scratch_spaceh]hdc_update_scratch_space}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jqsbc.dc_update_state_prepareasbuh1hhjubjP)}(h h]h }(hjɝhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjםhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hscratchh]hscratch}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubah}(h]h ]h"]h$]h&]j~juh1jD+hjKhhhj\hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjGhhhj\hMubah}(h]jBah ](jjeh"]h$]h&]jj)jhuh1j1hj\hMhjDhhubj)}(hhh]h)}(h)Prepare the commit under the global lock.h]h)Prepare the commit under the global lock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjDhhhj\hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj&jj&jjjuh1j,hhhjhNhNubj)}(h**Parameters** ``struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init() **Description** On failure the scratch slot is released and false is returned; the caller must not call execute or cleanup.h](h)}(h**Parameters**h]j)}(hj0h]h Parameters}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj*ubj)}(hhh]j )}(hW``struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init() h](j)}(h+``struct dc_update_scratch_space *scratch``h]j)}(hjOh]h'struct dc_update_scratch_space *scratch}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjIubj-)}(hhh]h)}(h*commit scratch from dc_update_state_init()h]h*commit scratch from dc_update_state_init()}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1j,hjIubeh}(h]h ]h"]h$]h&]uh1j hjdhMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj*ubh)}(hkOn failure the scratch slot is released and false is returned; the caller must not call execute or cleanup.h]hkOn failure the scratch slot is released and false is returned; the caller must not call execute or cleanup.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'$dc_update_state_execute (C function)c.dc_update_state_executehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hLvoid dc_update_state_execute (const struct dc_update_scratch_space *scratch)h]j8)}(hKvoid dc_update_state_execute(const struct dc_update_scratch_space *scratch)h](j +)}(hvoidh]hvoid}(hjϞhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj˞hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjޞhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj˞hhhjݞhMubja)}(hdc_update_state_executeh]jg)}(hdc_update_state_executeh]hdc_update_state_execute}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj˞hhhjݞhMubjE+)}(h/(const struct dc_update_scratch_space *scratch)h]jK+)}(h-const struct dc_update_scratch_space *scratchh](j>)}(hj=\h]hconst}(hj hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj>)}(hjAh]hstruct}(hj'hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hj4hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_update_scratch_spaceh]hdc_update_scratch_space}(hjEhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjBubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjGmodnameN classnameNj'j*)}j-]j+)}j+jsbc.dc_update_state_executeasbuh1hhjubjP)}(h h]h }(hjehhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjshhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hscratchh]hscratch}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubah}(h]h ]h"]h$]h&]j~juh1jD+hj˞hhhjݞhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjǞhhhjݞhMubah}(h]jžah ](jjeh"]h$]h&]jj)jhuh1j1hjݞhMhjĞhhubj)}(hhh]h)}(h1Program hardware; called without the global lock.h]h1Program hardware; called without the global lock.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjĞhhhjݞhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjŸjjŸjjjuh1j,hhhjhNhNubj)}(hn**Parameters** ``const struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init()h](h)}(h**Parameters**h]j)}(hj̟h]h Parameters}(hjΟhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʟubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjƟubj)}(hhh]j )}(h\``const struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init()h](j)}(h1``const struct dc_update_scratch_space *scratch``h]j)}(hjh]h-const struct dc_update_scratch_space *scratch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h*commit scratch from dc_update_state_init()h]h*commit scratch from dc_update_state_init()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjƟubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'$dc_update_state_cleanup (C function)c.dc_update_state_cleanuphNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hFbool dc_update_state_cleanup (struct dc_update_scratch_space *scratch)h]j8)}(hEbool dc_update_state_cleanup(struct dc_update_scratch_space *scratch)h](j +)}(hj>ah]hbool}(hjEhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjAhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjShhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjAhhhjRhMubja)}(hdc_update_state_cleanuph]jg)}(hdc_update_state_cleanuph]hdc_update_state_cleanup}(hjehhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjaubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjAhhhjRhMubjE+)}(h)(struct dc_update_scratch_space *scratch)h]jK+)}(h'struct dc_update_scratch_space *scratchh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj}ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj}ubh)}(hhh]jg)}(hdc_update_scratch_spaceh]hdc_update_scratch_space}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jgsbc.dc_update_state_cleanupasbuh1hhj}ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj}ubj+)}(hj+h]h*}(hj͠hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hj}ubjg)}(hscratchh]hscratch}(hjڠhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj}ubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjyubah}(h]h ]h"]h$]h&]j~juh1jD+hjAhhhjRhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj=hhhjRhMubah}(h]j8ah ](jjeh"]h$]h&]jj)jhuh1j1hjRhMhj:hhubj)}(hhh]h)}(h1Finalise the commit and release the scratch slot.h]h1Finalise the commit and release the scratch slot.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj:hhhjRhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(h**Parameters** ``struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init() **Description** Must be called with the global lock held. Returns true if the caller must loop back to prepare (SEAMLESS continuation).h](h)}(h**Parameters**h]j)}(hj&h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj ubj)}(hhh]j )}(hW``struct dc_update_scratch_space *scratch`` commit scratch from dc_update_state_init() h](j)}(h+``struct dc_update_scratch_space *scratch``h]j)}(hjEh]h'struct dc_update_scratch_space *scratch}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj?ubj-)}(hhh]h)}(h*commit scratch from dc_update_state_init()h]h*commit scratch from dc_update_state_init()}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhj[ubah}(h]h ]h"]h$]h&]uh1j,hj?ubeh}(h]h ]h"]h$]h&]uh1j hjZhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj ubh)}(hwMust be called with the global lock held. Returns true if the caller must loop back to prepare (SEAMLESS continuation).h]hwMust be called with the global lock held. Returns true if the caller must loop back to prepare (SEAMLESS continuation).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_probe_latencies (C struct)c.dc_probe_latencieshNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_probe_latenciesh]j8)}(hstruct dc_probe_latenciesh](j>)}(hjAh]hstruct}(hjšhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjӡhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjҡhMubja)}(hdc_probe_latenciesh]jg)}(hjh]hdc_probe_latencies}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjҡhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjҡhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjҡhMhjhhubj)}(hhh]h)}(h!min/max/avg memory latency in ns.h]h!min/max/avg memory latency in ns.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjҡhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX=**Definition**:: struct dc_probe_latencies { uint32_t max_latency_ns; uint32_t avg_latency_ns; uint32_t min_latency_ns; }; **Members** ``max_latency_ns`` maximum latency in nanoseconds ``avg_latency_ns`` average latency in nanoseconds ``min_latency_ns`` minimum latency in nanosecondsh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubh:}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj#ubj)}(hustruct dc_probe_latencies { uint32_t max_latency_ns; uint32_t avg_latency_ns; uint32_t min_latency_ns; };h]hustruct dc_probe_latencies { uint32_t max_latency_ns; uint32_t avg_latency_ns; uint32_t min_latency_ns; };}hjDsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj#ubh)}(h **Members**h]j)}(hjUh]hMembers}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj#ubj)}(hhh](j )}(h2``max_latency_ns`` maximum latency in nanoseconds h](j)}(h``max_latency_ns``h]j)}(hjth]hmax_latency_ns}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjnubj-)}(hhh]h)}(hmaximum latency in nanosecondsh]hmaximum latency in nanoseconds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjnubeh}(h]h ]h"]h$]h&]uh1j hjhMhjkubj )}(h2``avg_latency_ns`` average latency in nanoseconds h](j)}(h``avg_latency_ns``h]j)}(hjh]havg_latency_ns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(haverage latency in nanosecondsh]haverage latency in nanoseconds}(hjƢhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj¢hMhjâubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj¢hMhjkubj )}(h1``min_latency_ns`` minimum latency in nanosecondsh](j)}(h``min_latency_ns``h]j)}(hjh]hmin_latency_ns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(hminimum latency in nanosecondsh]hminimum latency in nanoseconds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjkubeh}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_probe_status (C struct)c.dc_probe_statushNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_probe_statush]j8)}(hstruct dc_probe_statush](j>)}(hjAh]hstruct}(hj@hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj<hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjNhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj<hhhjMhMubja)}(hdc_probe_statush]jg)}(hj:h]hdc_probe_status}(hj`hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj\ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj<hhhjMhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj8hhhjMhMubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j1hjMhMhj5hhubj)}(hhh]h)}(hresults for a probe.h]hresults for a probe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj5hhhjMhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX **Definition**:: struct dc_probe_status { bool valid; enum dc_probe_type type; union { uint32_t bandwidth_mbps; struct dc_probe_latencies latency; uint32_t urgent_assertion_count; uint32_t prefetch_data_size; } u; }; **Members** ``valid`` true if a measurement was latched. ``type`` type of the probe that produced this result. ``u.bandwidth_mbps`` peak BW in Mbps (DC_PROBE_PEAK_MEM_BW). ``u.latency`` min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), stored as struct dc_probe_latencies. ``u.urgent_assertion_count`` number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT). ``u.prefetch_data_size`` total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE).h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hstruct dc_probe_status { bool valid; enum dc_probe_type type; union { uint32_t bandwidth_mbps; struct dc_probe_latencies latency; uint32_t urgent_assertion_count; uint32_t prefetch_data_size; } u; };h]hstruct dc_probe_status { bool valid; enum dc_probe_type type; union { uint32_t bandwidth_mbps; struct dc_probe_latencies latency; uint32_t urgent_assertion_count; uint32_t prefetch_data_size; } u; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(h **Members**h]j)}(hjУh]hMembers}(hjңhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjΣubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(h-``valid`` true if a measurement was latched. h](j)}(h ``valid``h]j)}(hjh]hvalid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h"true if a measurement was latched.h]h"true if a measurement was latched.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(h6``type`` type of the probe that produced this result. h](j)}(h``type``h]j)}(hj(h]htype}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj"ubj-)}(hhh]h)}(h,type of the probe that produced this result.h]h,type of the probe that produced this result.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hMhj>ubah}(h]h ]h"]h$]h&]uh1j,hj"ubeh}(h]h ]h"]h$]h&]uh1j hj=hMhjubj )}(h=``u.bandwidth_mbps`` peak BW in Mbps (DC_PROBE_PEAK_MEM_BW). h](j)}(h``u.bandwidth_mbps``h]j)}(hjah]hu.bandwidth_mbps}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj[ubj-)}(hhh]h)}(h'peak BW in Mbps (DC_PROBE_PEAK_MEM_BW).h]h'peak BW in Mbps (DC_PROBE_PEAK_MEM_BW).}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubah}(h]h ]h"]h$]h&]uh1j,hj[ubeh}(h]h ]h"]h$]h&]uh1j hjvhMhjubj )}(hl``u.latency`` min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), stored as struct dc_probe_latencies. h](j)}(h ``u.latency``h]j)}(hjh]h u.latency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h]min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), stored as struct dc_probe_latencies.h]h]min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), stored as struct dc_probe_latencies.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hb``u.urgent_assertion_count`` number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT). h](j)}(h``u.urgent_assertion_count``h]j)}(hjԤh]hu.urgent_assertion_count}(hj֤hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjҤubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjΤubj-)}(hhh]h)}(hDnumber of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT).h]hDnumber of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjΤubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hT``u.prefetch_data_size`` total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE).h](j)}(h``u.prefetch_data_size``h]j)}(hj h]hu.prefetch_data_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h;total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE).h]h;total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE).}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj#ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj"hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_get_status_type (C enum)c.dc_get_status_typehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_get_status_typeh]j8)}(henum dc_get_status_typeh](j>)}(hj^8h]henum}(hjghhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjchhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjuhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjchhhjthMubja)}(hdc_get_status_typeh]jg)}(hjah]hdc_get_status_type}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjchhhjthMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj_hhhjthMubah}(h]jZah ](jjeh"]h$]h&]jj)jhuh1j1hjthMhj\hhubj)}(hhh]h)}(h3Bitmask selecting which status classes to populate.h]h3Bitmask selecting which status classes to populate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhj\hhhjthMubeh}(h]h ](jenumeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(h**Constants** ``DC_GET_STATUS_STREAM`` populate stream_status fields in dc_state_status ``DC_GET_STATUS_PROBE`` populate probe_status fields in dc_state_statush](h)}(h **Constants**h]j)}(hj˥h]h Constants}(hjͥhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjɥubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.h hMhjťubj)}(hhh](j )}(hJ``DC_GET_STATUS_STREAM`` populate stream_status fields in dc_state_status h](j)}(h``DC_GET_STATUS_STREAM``h]j)}(hjh]hDC_GET_STATUS_STREAM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h0populate stream_status fields in dc_state_statush]h0populate stream_status fields in dc_state_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hG``DC_GET_STATUS_PROBE`` populate probe_status fields in dc_state_statush](j)}(h``DC_GET_STATUS_PROBE``h]j)}(hj#h]hDC_GET_STATUS_PROBE}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h/populate probe_status fields in dc_state_statush]h/populate probe_status fields in dc_state_status}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj9ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj8hMhjubeh}(h]h ]h"]h$]h&]uh1jhjťubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j' dc_get_status_options (C struct)c.dc_get_status_optionshNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_get_status_optionsh]j8)}(hstruct dc_get_status_optionsh](j>)}(hjAh]hstruct}(hj}hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjyhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjyhhhjhMubja)}(hdc_get_status_optionsh]jg)}(hjwh]hdc_get_status_options}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjyhhhjhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjuhhhjhMubah}(h]jpah ](jjeh"]h$]h&]jj)jhuh1j1hjhMhjrhhubj)}(hhh]h)}(h'Input selector for dc_state_get_status.h]h'Input selector for dc_state_get_status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjצjjצjjjuh1j,hhhjhNhNubj)}(hXC**Definition**:: struct dc_get_status_options { struct dc_state *state; uint32_t types; const struct dc_stream_state *stream; const struct dc_probe_state *probe; }; **Members** ``state`` source state to read status from ``types`` OR of dc_get_status_type values selecting classes to populate ``stream`` optional stream filter for DC_GET_STATUS_STREAM. NULL means populate status for all streams in the state ``probe`` optional probe filter for DC_GET_STATUS_PROBE. NULL means populate status for all probes in the stateh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjߦubh:}(hjߦhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjۦubj)}(hstruct dc_get_status_options { struct dc_state *state; uint32_t types; const struct dc_stream_state *stream; const struct dc_probe_state *probe; };h]hstruct dc_get_status_options { struct dc_state *state; uint32_t types; const struct dc_stream_state *stream; const struct dc_probe_state *probe; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjۦubh)}(h **Members**h]j)}(hj h]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjۦubj)}(hhh](j )}(h+``state`` source state to read status from h](j)}(h ``state``h]j)}(hj,h]hstate}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj&ubj-)}(hhh]h)}(h source state to read status fromh]h source state to read status from}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhMhjBubah}(h]h ]h"]h$]h&]uh1j,hj&ubeh}(h]h ]h"]h$]h&]uh1j hjAhMhj#ubj )}(hH``types`` OR of dc_get_status_type values selecting classes to populate h](j)}(h ``types``h]j)}(hjeh]htypes}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj_ubj-)}(hhh]h)}(h=OR of dc_get_status_type values selecting classes to populateh]h=OR of dc_get_status_type values selecting classes to populate}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhj{ubah}(h]h ]h"]h$]h&]uh1j,hj_ubeh}(h]h ]h"]h$]h&]uh1j hjzhMhj#ubj )}(ht``stream`` optional stream filter for DC_GET_STATUS_STREAM. NULL means populate status for all streams in the state h](j)}(h ``stream``h]j)}(hjh]hstream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(hhoptional stream filter for DC_GET_STATUS_STREAM. NULL means populate status for all streams in the stateh]hhoptional stream filter for DC_GET_STATUS_STREAM. NULL means populate status for all streams in the state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhj#ubj )}(ho``probe`` optional probe filter for DC_GET_STATUS_PROBE. NULL means populate status for all probes in the stateh](j)}(h ``probe``h]j)}(hjاh]hprobe}(hjڧhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֧ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjҧubj-)}(hhh]h)}(heoptional probe filter for DC_GET_STATUS_PROBE. NULL means populate status for all probes in the stateh]heoptional probe filter for DC_GET_STATUS_PROBE. NULL means populate status for all probes in the state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjҧubeh}(h]h ]h"]h$]h&]uh1j hjhMhj#ubeh}(h]h ]h"]h$]h&]uh1jhjۦubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_state_status (C struct)c.dc_state_statushNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_state_statush]j8)}(hstruct dc_state_statush](j>)}(hjAh]hstruct}(hj1hhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hj-hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hj?hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj-hhhj>hMubja)}(hdc_state_statush]jg)}(hj+h]hdc_state_status}(hjQhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjMubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj-hhhj>hMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj)hhhj>hMubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1j1hj>hMhj&hhubj)}(hhh]h)}(h3Output-only status object from dc_state_get_status.h]h3Output-only status object from dc_state_get_status.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjphhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj>hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX**Definition**:: struct dc_state_status { int stream_count; struct dc_stream_status *stream_status[MAX_STREAMS]; int probe_count; struct dc_probe_status *probe_status[MAX_PROBES]; }; **Members** ``stream_count`` number of valid entries in stream_status (DC_GET_STATUS_STREAM) ``stream_status`` pointers to live per-stream status entries ``probe_count`` number of valid entries in probe_status (DC_GET_STATUS_PROBE) ``probe_status`` pointers to live per-probe status entriesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hstruct dc_state_status { int stream_count; struct dc_stream_status *stream_status[MAX_STREAMS]; int probe_count; struct dc_probe_status *probe_status[MAX_PROBES]; };h]hstruct dc_state_status { int stream_count; struct dc_stream_status *stream_status[MAX_STREAMS]; int probe_count; struct dc_probe_status *probe_status[MAX_PROBES]; };}hjsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjèhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(hQ``stream_count`` number of valid entries in stream_status (DC_GET_STATUS_STREAM) h](j)}(h``stream_count``h]j)}(hjh]h stream_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjިubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjڨubj-)}(hhh]h)}(h?number of valid entries in stream_status (DC_GET_STATUS_STREAM)h]h?number of valid entries in stream_status (DC_GET_STATUS_STREAM)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjڨubeh}(h]h ]h"]h$]h&]uh1j hjhMhjרubj )}(h=``stream_status`` pointers to live per-stream status entries h](j)}(h``stream_status``h]j)}(hjh]h stream_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h*pointers to live per-stream status entriesh]h*pointers to live per-stream status entries}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj/ubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hj.hMhjרubj )}(hN``probe_count`` number of valid entries in probe_status (DC_GET_STATUS_PROBE) h](j)}(h``probe_count``h]j)}(hjRh]h probe_count}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjLubj-)}(hhh]h)}(h=number of valid entries in probe_status (DC_GET_STATUS_PROBE)h]h=number of valid entries in probe_status (DC_GET_STATUS_PROBE)}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMhjhubah}(h]h ]h"]h$]h&]uh1j,hjLubeh}(h]h ]h"]h$]h&]uh1j hjghMhjרubj )}(h:``probe_status`` pointers to live per-probe status entriesh](j)}(h``probe_status``h]j)}(hjh]h probe_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h)pointers to live per-probe status entriesh]h)pointers to live per-probe status entries}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjרubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j' dc_state_get_status (C function)c.dc_state_get_statushNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hpenum dc_status dc_state_get_status (struct dc_state_status *status, const struct dc_get_status_options *options)h]j8)}(hoenum dc_status dc_state_get_status(struct dc_state_status *status, const struct dc_get_status_options *options)h](j>)}(hj^8h]henum}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMubh)}(hhh]jg)}(h dc_statush]h dc_status}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+dc_state_get_statussbc.dc_state_get_statusasbuh1hhjhhhjhMubjP)}(h h]h }(hj%hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhMubja)}(hdc_state_get_statush]jg)}(hj"h]hdc_state_get_status}(hj7hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj3ubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhMubjE+)}(hM(struct dc_state_status *status, const struct dc_get_status_options *options)h](jK+)}(hstruct dc_state_status *statush](j>)}(hjAh]hstruct}(hjRhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjNubjP)}(h h]h }(hj_hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjNubh)}(hhh]jg)}(hdc_state_statush]hdc_state_status}(hjphhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjmubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjrmodnameN classnameNj'j*)}j-]j c.dc_state_get_statusasbuh1hhjNubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjNubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjNubjg)}(hstatush]hstatus}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjNubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjJubjK+)}(h+const struct dc_get_status_options *optionsh](j>)}(hj=\h]hconst}(hjªhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjϪhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj>)}(hjAh]hstruct}(hjݪhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_get_status_optionsh]hdc_get_status_options}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j c.dc_state_get_statusasbuh1hhjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hj'hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hoptionsh]hoptions}(hj4hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjJubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjݩhhhjhMubah}(h]jةah ](jjeh"]h$]h&]jj)jhuh1j1hjhMhjکhhubj)}(hhh]h)}(h%Unified status readback for dc_state.h]h%Unified status readback for dc_state.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj[hhubah}(h]h ]h"]h$]h&]uh1jhjکhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjvjjvjjjuh1j,hhhjhNhNubj)}(hX**Parameters** ``struct dc_state_status *status`` output object populated according to options->types ``const struct dc_get_status_options *options`` selects the source state, status classes to fill, and filters **Return** DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjzubj)}(hhh](j )}(hW``struct dc_state_status *status`` output object populated according to options->types h](j)}(h"``struct dc_state_status *status``h]j)}(hjh]hstruct dc_state_status *status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h3output object populated according to options->typesh]h3output object populated according to options->types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubj )}(hn``const struct dc_get_status_options *options`` selects the source state, status classes to fill, and filters h](j)}(h/``const struct dc_get_status_options *options``h]j)}(hjثh]h+const struct dc_get_status_options *options}(hjګhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֫ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjҫubj-)}(hhh]h)}(h=selects the source state, status classes to fill, and filtersh]h=selects the source state, status classes to fill, and filters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjҫubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjzubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjzubh)}(h7DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL.h]h7DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_validation_stream (C struct)c.dc_validation_streamhNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_validation_streamh]j8)}(hstruct dc_validation_streamh](j>)}(hjAh]hstruct}(hjXhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjThhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjfhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjThhhjehMubja)}(hdc_validation_streamh]jg)}(hjRh]hdc_validation_stream}(hjxhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjtubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjThhhjehMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjPhhhjehMubah}(h]jKah ](jjeh"]h$]h&]jj)jhuh1j1hjehMhjMhhubj)}(hhh]h)}(h4Per-stream surface/stream association for validationh]h4Per-stream surface/stream association for validation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM+ hjhhubah}(h]h ]h"]h$]h&]uh1jhjMhhhjehMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hX/**Definition**:: struct dc_validation_stream { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; }; **Members** ``stream`` Stream state properties ``plane_states`` Surface state ``plane_count`` Total of active planesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM/ hjubj)}(hstruct dc_validation_stream { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };h]hstruct dc_validation_stream { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };}hj׬sbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM1 hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM7 hjubj)}(hhh](j )}(h#``stream`` Stream state properties h](j)}(h ``stream``h]j)}(hjh]hstream}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM0 hjubj-)}(hhh]h)}(hStream state propertiesh]hStream state properties}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM0 hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM0 hjubj )}(h``plane_states`` Surface state h](j)}(h``plane_states``h]j)}(hj@h]h plane_states}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM5 hj:ubj-)}(hhh]h)}(h Surface stateh]h Surface state}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhM5 hjVubah}(h]h ]h"]h$]h&]uh1j,hj:ubeh}(h]h ]h"]h$]h&]uh1j hjUhM5 hjubj )}(h&``plane_count`` Total of active planesh](j)}(h``plane_count``h]j)}(hjyh]h plane_count}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM9 hjsubj-)}(hhh]h)}(hTotal of active planesh]hTotal of active planes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM: hjubah}(h]h ]h"]h$]h&]uh1j,hjsubeh}(h]h ]h"]h$]h&]uh1j hjhM9 hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_validation_set (C struct)c.dc_validation_sethNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hdc_validation_seth]j8)}(hstruct dc_validation_seth](j>)}(hjAh]hstruct}(hjӭhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjϭhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM@ ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjϭhhhjhM@ ubja)}(hdc_validation_seth]jg)}(hjͭh]hdc_validation_set}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjϭhhhjhM@ ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj˭hhhjhM@ ubah}(h]jƭah ](jjeh"]h$]h&]jj)jhuh1j1hjhM@ hjȭhhubj)}(hhh]h)}(h7Root validation input grouping all streams for a commith]h7Root validation input grouping all streams for a commit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM? hjhhubah}(h]h ]h"]h$]h&]uh1jhjȭhhhjhM@ ubeh}(h]h ](jstructeh"]h$]h&]jjjj-jj-jjjuh1j,hhhjhNhNubj)}(hX**Definition**:: struct dc_validation_set { struct dc_validation_stream streams[MAX_STREAMS]; uint8_t stream_count; struct dc_probe_state probes[MAX_PROBES]; uint8_t probe_count; }; **Members** ``streams`` Per-stream entries (stream + its planes) ``stream_count`` Number of active entries in **streams** ``probes`` Global probe descriptors to validate alongside the streams ``probe_count`` Number of active entries in **probes**h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMC hj1ubj)}(hstruct dc_validation_set { struct dc_validation_stream streams[MAX_STREAMS]; uint8_t stream_count; struct dc_probe_state probes[MAX_PROBES]; uint8_t probe_count; };h]hstruct dc_validation_set { struct dc_validation_stream streams[MAX_STREAMS]; uint8_t stream_count; struct dc_probe_state probes[MAX_PROBES]; uint8_t probe_count; };}hjRsbah}(h]h ]h"]h$]h&]j~juh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhME hj1ubh)}(h **Members**h]j)}(hjch]hMembers}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhML hj1ubj)}(hhh](j )}(h5``streams`` Per-stream entries (stream + its planes) h](j)}(h ``streams``h]j)}(hjh]hstreams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMD hj|ubj-)}(hhh]h)}(h(Per-stream entries (stream + its planes)h]h(Per-stream entries (stream + its planes)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMD hjubah}(h]h ]h"]h$]h&]uh1j,hj|ubeh}(h]h ]h"]h$]h&]uh1j hjhMD hjyubj )}(h9``stream_count`` Number of active entries in **streams** h](j)}(h``stream_count``h]j)}(hjh]h stream_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMI hjubj-)}(hhh]h)}(h'Number of active entries in **streams**h](hNumber of active entries in }(hjԮhhhNhNubj)}(h **streams**h]hstreams}(hjܮhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԮubeh}(h]h ]h"]h$]h&]uh1hhjЮhMI hjѮubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjЮhMI hjyubj )}(hF``probes`` Global probe descriptors to validate alongside the streams h](j)}(h ``probes``h]j)}(hjh]hprobes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMN hjubj-)}(hhh]h)}(h:Global probe descriptors to validate alongside the streamsh]h:Global probe descriptors to validate alongside the streams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMN hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMN hjyubj )}(h6``probe_count`` Number of active entries in **probes**h](j)}(h``probe_count``h]j)}(hj;h]h probe_count}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMR hj5ubj-)}(hhh]h)}(h&Number of active entries in **probes**h](hNumber of active entries in }(hjThhhNhNubj)}(h **probes**h]hprobes}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMS hjQubah}(h]h ]h"]h$]h&]uh1j,hj5ubeh}(h]h ]h"]h$]h&]uh1j hjPhMR hjyubeh}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'0dc_get_underflow_debug_data_for_otg (C function)%c.dc_get_underflow_debug_data_for_otghNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hvoid dc_get_underflow_debug_data_for_otg (struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data)h]j8)}(hvoid dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](j +)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM ubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjhM ubja)}(h#dc_get_underflow_debug_data_for_otgh]jg)}(h#dc_get_underflow_debug_data_for_otgh]h#dc_get_underflow_debug_data_for_otg}(hjįhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjhM ubjE+)}(hX(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjܯubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjܯubh)}(hhh]jg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jƯsb%c.dc_get_underflow_debug_data_for_otgasbuh1hhjܯubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjܯubj+)}(hj+h]h*}(hj,hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjܯubjg)}(hdch]hdc}(hj9hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjܯubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjدubjK+)}(hunsigned int primary_otg_insth](j +)}(hunsignedh]hunsigned}(hjRhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjNubjP)}(h h]h }(hj`hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjNubj +)}(hinth]hint}(hjnhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjNubjP)}(h h]h }(hj|hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjNubjg)}(hprimary_otg_insth]hprimary_otg_inst}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjNubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjدubjK+)}(h(struct dc_underflow_debug_data *out_datah](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_underflow_debug_datah]hdc_underflow_debug_data}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjðmodnameN classnameNj'j*)}j-]j%c.dc_get_underflow_debug_data_for_otgasbuh1hhjubjP)}(h h]h }(hj߰hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hout_datah]hout_data}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjدubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjhM ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjhM hjhhubj)}(hhh]h)}(hRetrieve underflow debug data.h]hRetrieve underflow debug data.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj!hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj<jj<jjjuh1j,hhhjhNhNubj)}(hXA**Parameters** ``struct dc *dc`` Pointer to the display core context. ``unsigned int primary_otg_inst`` Instance index of the primary OTG that underflowed. ``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. **Description** This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h](h)}(h**Parameters**h]j)}(hjFh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj@ubj)}(hhh](j )}(h7``struct dc *dc`` Pointer to the display core context. h](j)}(h``struct dc *dc``h]j)}(hjeh]h struct dc *dc}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj_ubj-)}(hhh]h)}(h$Pointer to the display core context.h]h$Pointer to the display core context.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhM hj{ubah}(h]h ]h"]h$]h&]uh1j,hj_ubeh}(h]h ]h"]h$]h&]uh1j hjzhM hj\ubj )}(hV``unsigned int primary_otg_inst`` Instance index of the primary OTG that underflowed. h](j)}(h!``unsigned int primary_otg_inst``h]j)}(hjh]hunsigned int primary_otg_inst}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubj-)}(hhh]h)}(h3Instance index of the primary OTG that underflowed.h]h3Instance index of the primary OTG that underflowed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM hj\ubj )}(h~``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. h](j)}(h,``struct dc_underflow_debug_data *out_data``h]j)}(hjױh]h(struct dc_underflow_debug_data *out_data}(hjٱhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjձubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjѱubj-)}(hhh]h)}(hPPointer to a dc_underflow_debug_data struct to be filled with debug information.h]hPPointer to a dc_underflow_debug_data struct to be filled with debug information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1j,hjѱubeh}(h]h ]h"]h$]h&]uh1j hjhM hj\ubeh}(h]h ]h"]h$]h&]uh1jhj@ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj@ubh)}(hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h]hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'/dc_capture_register_software_state (C function)$c.dc_capture_register_software_statehNtauh1jhjhhhNhNubj-)}(hhh](j2)}(habool dc_capture_register_software_state (struct dc *dc, struct dc_register_software_state *state)h]j8)}(h`bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)h](j +)}(hj>ah]hbool}(hjWhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjShhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjehhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjShhhjdhMubja)}(h"dc_capture_register_software_stateh]jg)}(h"dc_capture_register_software_stateh]h"dc_capture_register_software_state}(hjwhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjsubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjShhhjdhMubjE+)}(h9(struct dc *dc, struct dc_register_software_state *state)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jysb$c.dc_capture_register_software_stateasbuh1hhjubjP)}(h h]h }(hjѲhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hj߲hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubjK+)}(h(struct dc_register_software_state *stateh](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdc_register_software_stateh]hdc_register_software_state}(hj#hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj%modnameN classnameNj'j*)}j-]jͲ$c.dc_capture_register_software_stateasbuh1hhjubjP)}(h h]h }(hjAhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjOhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hstateh]hstate}(hj\hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubeh}(h]h ]h"]h$]h&]j~juh1jD+hjShhhjdhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjOhhhjdhMubah}(h]jJah ](jjeh"]h$]h&]jj)jhuh1j1hjdhMhjLhhubj)}(hhh]h)}(h/Capture software state for register programmingh]h/Capture software state for register programming}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjLhhhjdhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j,hhhjhNhNubj)}(hXM**Parameters** ``struct dc *dc`` DC context containing current display configuration ``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate **Description** Extracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming. The function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration) This is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues. **Return** true if state was successfully captured, false on errorh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(hF``struct dc *dc`` DC context containing current display configuration h](j)}(h``struct dc *dc``h]j)}(hjdzh]h struct dc *dc}(hjɳhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjųubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h3DC context containing current display configurationh]h3DC context containing current display configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjܳhMhjݳubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjܳhMhjubj )}(hi``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate h](j)}(h,``struct dc_register_software_state *state``h]j)}(hjh]h(struct dc_register_software_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj-)}(hhh]h)}(h;Pointer to dc_register_software_state structure to populateh]h;Pointer to dc_register_software_state structure to populate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hj;h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.h]hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)h]hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.h]hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(h7true if state was successfully captured, false on errorh]h7true if state was successfully captured, false on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'dc_get_qos_info (C function)c.dc_get_qos_infohNtauh1jhjhhhNhNubj-)}(hhh](j2)}(h>bool dc_get_qos_info (struct dc *dc, struct dc_qos_info *info)h]j8)}(h=bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)h](j +)}(hj>ah]hbool}(hjŴhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMubjP)}(h h]h }(hjӴhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjhhhjҴhMubja)}(hdc_get_qos_infoh]jg)}(hdc_get_qos_infoh]hdc_get_qos_info}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hjhhhjҴhMubjE+)}(h)(struct dc *dc, struct dc_qos_info *info)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetj!modnameN classnameNj'j*)}j-]j+)}j+jsbc.dc_get_qos_infoasbuh1hhjubjP)}(h h]h }(hj?hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjMhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hdch]hdc}(hjZhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubjK+)}(hstruct dc_qos_info *infoh](j>)}(hjAh]hstruct}(hjshhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjoubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjoubh)}(hhh]jg)}(h dc_qos_infoh]h dc_qos_info}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j;c.dc_get_qos_infoasbuh1hhjoubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjoubj+)}(hj+h]h*}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjoubjg)}(hinfoh]hinfo}(hjʵhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjoubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubeh}(h]h ]h"]h$]h&]j~juh1jD+hjhhhjҴhMubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhjhhhjҴhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j1hjҴhMhjhhubj)}(hhh]h)}(h?Retrieve Quality of Service (QoS) information from display coreh]h?Retrieve Quality of Service (QoS) information from display core}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjҴhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j,hhhjhNhNubj)}(hX%**Parameters** ``struct dc *dc`` DC context containing current display configuration ``struct dc_qos_info *info`` Pointer to dc_qos_info structure to populate with QoS metrics **Description** This function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements. QoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds) The function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero'd info structure. **Return** true if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performedh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j )}(hF``struct dc *dc`` DC context containing current display configuration h](j)}(h``struct dc *dc``h]j)}(hj5h]h struct dc *dc}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj/ubj-)}(hhh]h)}(h3DC context containing current display configurationh]h3DC context containing current display configuration}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhMhjKubah}(h]h ]h"]h$]h&]uh1j,hj/ubeh}(h]h ]h"]h$]h&]uh1j hjJhMhj,ubj )}(h[``struct dc_qos_info *info`` Pointer to dc_qos_info structure to populate with QoS metrics h](j)}(h``struct dc_qos_info *info``h]j)}(hjnh]hstruct dc_qos_info *info}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjhubj-)}(hhh]h)}(h=Pointer to dc_qos_info structure to populate with QoS metricsh]h=Pointer to dc_qos_info structure to populate with QoS metrics}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j,hjhubeh}(h]h ]h"]h$]h&]uh1j hjhMhj,ubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hThis function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements.h]hThis function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hQoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds)h]hQoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds)}(hjζhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(hThe function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero'd info structure.h]hThe function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero’d info structure.}(hjݶhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM$hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM(hjubh)}(htrue if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performedh]htrue if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM)hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'1dc_override_memory_bandwidth_request (C function)&c.dc_override_memory_bandwidth_requesthNtauh1jhjhhhNhNubj-)}(hhh](j2)}(hWunsigned int dc_override_memory_bandwidth_request (struct dc *dc, unsigned int bw_mbps)h]j8)}(hVunsigned int dc_override_memory_bandwidth_request(struct dc *dc, unsigned int bw_mbps)h](j +)}(hunsignedh]hunsigned}(hj3hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj/hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM/ubjP)}(h h]h }(hjBhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj/hhhjAhM/ubj +)}(hinth]hint}(hjPhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hj/hhhjAhM/ubjP)}(h h]h }(hj^hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhj/hhhjAhM/ubja)}(h$dc_override_memory_bandwidth_requesth]jg)}(h$dc_override_memory_bandwidth_requesth]h$dc_override_memory_bandwidth_request}(hjphhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjlubah}(h]h ](jyjzeh"]h$]h&]j~juh1j`hj/hhhjAhM/ubjE+)}(h%(struct dc *dc, unsigned int bw_mbps)h](jK+)}(h struct dc *dch](j>)}(hjAh]hstruct}(hjhhhNhNubah}(h]h ]jJah"]h$]h&]uh1j=hjubjP)}(h h]h }(hjhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubh)}(hhh]jg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubah}(h]h ]h"]h$]h&] refdomainjreftypej+ reftargetjmodnameN classnameNj'j*)}j-]j+)}j+jrsb&c.dc_override_memory_bandwidth_requestasbuh1hhjubjP)}(h h]h }(hjʷhhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj+)}(hj+h]h*}(hjطhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j+hjubjg)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubjK+)}(hunsigned int bw_mbpsh](j +)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjubjP)}(h h]h }(hj hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubj +)}(hinth]hint}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1j +hjubjP)}(h h]h }(hj(hhhNhNubah}(h]h ]j\ah"]h$]h&]uh1jOhjubjg)}(hbw_mbpsh]hbw_mbps}(hj6hhhNhNubah}(h]h ]jrah"]h$]h&]uh1jfhjubeh}(h]h ]h"]h$]h&]noemphj~juh1jJ+hjubeh}(h]h ]h"]h$]h&]j~juh1jD+hj/hhhjAhM/ubeh}(h]h ]h"]h$]h&]j~jjuh1j7jjhj+hhhjAhM/ubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1j1hjAhM/hj(hhubj)}(hhh]h)}(h|Override the DCN nominal memory bandwidth request sent to PMFW, independent of the current display mode. For debug use only.h]h|Override the DCN nominal memory bandwidth request sent to PMFW, independent of the current display mode. For debug use only.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM/hj]hhubah}(h]h ]h"]h$]h&]uh1jhj(hhhjAhM/ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjxjjxjjjuh1j,hhhjhNhNubj)}(h**Parameters** ``struct dc *dc`` DC instance ``unsigned int bw_mbps`` requested bandwidth in MB/s; 0 clears the override **Return** capped bandwidth value actually applied (MB/s)h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM3hj|ubj)}(hhh](j )}(h``struct dc *dc`` DC instance h](j)}(h``struct dc *dc``h]j)}(hjh]h struct dc *dc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM2hjubj-)}(hhh]h)}(h DC instanceh]h DC instance}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM2hjubah}(h]h ]h"]h$]h&]uh1j,hjubeh}(h]h ]h"]h$]h&]uh1j hjhM2hjubj )}(hL``unsigned int bw_mbps`` requested bandwidth in MB/s; 0 clears the override h](j)}(h``unsigned int bw_mbps``h]j)}(hjڸh]hunsigned int bw_mbps}(hjܸhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjظubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM3hjԸubj-)}(hhh]h)}(h2requested bandwidth in MB/s; 0 clears the overrideh]h2requested bandwidth in MB/s; 0 clears the override}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM3hjubah}(h]h ]h"]h$]h&]uh1j,hjԸubeh}(h]h ]h"]h$]h&]uh1j hjhM3hjubeh}(h]h ]h"]h$]h&]uh1jhj|ubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM5hj|ubh)}(h.capped bandwidth value actually applied (MB/s)h]h.capped bandwidth value actually applied (MB/s)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:74: ./drivers/gpu/drm/amd/display/dc/dc.hhM5hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubh)}(hThe color pipeline has undergone major changes between DCN hardware generations. What's possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.h]hThe color pipeline has undergone major changes between DCN hardware generations. What’s possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjhhubh)}(h)**DCN 2.0 family color caps and mapping**h]j)}(hjQh]h%DCN 2.0 family color caps and mapping}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1hhhhKRhjhhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h+.. kernel-figure:: dcn2_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn2_cm_drm_current.svg candidates}j+j~suh1jqhjnhhhKubah}(h]h ]h"]h$]h&]uh1jlhjiubah}(h]h ]h"]h$]h&]uh1jghjhhhhhKUubh)}(h)**DCN 3.0 family color caps and mapping**h]j)}(hjh]h%DCN 3.0 family color caps and mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKVhjhhubjh)}(hhh]jm)}(hhh]jr)}(h+.. kernel-figure:: dcn3_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn3_cm_drm_current.svgj}j+jsuh1jqhjhhhKubah}(h]h ]h"]h$]h&]uh1jlhjubah}(h]h ]h"]h$]h&]uh1jghjhhhhhKYubeh}(h]j ah ]h"]-dc color capabilities between dcn generationsah$]h&]uh1hhj9UhhhhhK:ubeh}(h]jah ]h"]color management propertiesah$]h&]uh1hhhhhhhhK0ubh)}(hhh](h)}(hBlend Mode Propertiesh]hBlend Mode Properties}(hjԹhhhNhNubah}(h]h ]h"]h$]h&]hj2uh1hhjѹhhhhhK[ubh)}(hXPixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in :ref:`DRM Plane Composition Properties `.h](h8Pixel blend mode is a DRM plane composition property of }(hjhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjh]h drm_plane}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  drm_planeuh1hhhhK]hjubhX' used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in }(hjhhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]hinline)}(hjh]h DRM Plane Composition Properties}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj plane_composition_propertiesuh1hhhhK]hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK]hjѹhhubh)}(hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:h]hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjѹhhubh)}(hhh](h)}(hG*fg.rgb*: Each of the RGB component values from the foreground's pixel.h]h)}(hjLh](j Q)}(h*fg.rgb*h]hfg.rgb}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j QhjNubhA: Each of the RGB component values from the foreground’s pixel.}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihjJubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h>*fg.alpha*: Alpha component value from the foreground's pixel.h]h)}(hjqh](j Q)}(h *fg.alpha*h]hfg.alpha}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjsubh6: Alpha component value from the foreground’s pixel.}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKjhjoubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h?*bg.rgb*: Each of the RGB component values from the background.h]h)}(hjh](j Q)}(h*bg.rgb*h]hbg.rgb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjubh7: Each of the RGB component values from the background.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `. h]h)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `.h](j Q)}(h *plane_alpha*h]h plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjubh: Plane alpha value set by the }(hjhhhNhNubj)}(h**plane "alpha" property**h]hplane “alpha” property}(hjӺhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, see more in }(hjhhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]j)}(hjh]h DRM Plane Composition Properties}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj plane_composition_propertiesuh1hhhhKlhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubeh}(h]h ]h"]h$]h&]jU-jV-uh1hhhhKihjѹhhubh)}(h&in the basic alpha blending equation::h]h%in the basic alpha blending equation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjѹhhubj)}(h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgbh]h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb}hj)sbah}(h]h ]h"]h$]h&]j~juh1jhhhKqhjѹhhubh)}(h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.h]h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjѹhhubh)}(hNDRM has three blend mode to define the blend formula in the plane composition:h]hNDRM has three blend mode to define the blend formula in the plane composition:}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjѹhhubh)}(hhh](h)}(h6**None**: Blend formula that ignores the pixel alpha. h]h)}(h5**None**: Blend formula that ignores the pixel alpha.h](j)}(h**None**h]hNone}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh-: Blend formula that ignores the pixel alpha.}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKxhjVubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage. h]h)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.h](j)}(h**Pre-multiplied**h]hPre-multiplied}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhj|ubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubh)}(hw**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values. h]h)}(hv**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.h](j)}(h **Coverage**h]hCoverage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhj: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK}hjubah}(h]h ]h"]h$]h&]uh1hhjShhhhhNubeh}(h]h ]h"]h$]h&]jU-j+uh1hhhhKxhjѹhhubh)}(hX1and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane's pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.h]hX3and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane’s pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.}(hjλhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjѹhhubh)}(hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:h]hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:}(hjܻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjѹhhubh)}(hXTherefore, the blending configuration for a single MPCC instance on the MPC tree is defined by :c:type:`mpcc_blnd_cfg`, where :c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. :c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for :c:type:`MPCC_ALPHA_BLND_MODE`, as described below.h](h_Therefore, the blending configuration for a single MPCC instance on the MPC tree is defined by }(hjhhhNhNubh)}(h:c:type:`mpcc_blnd_cfg`h]j)}(hjh]h mpcc_blnd_cfg}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  mpcc_blnd_cfguh1hhhhKhjubh, where }(hjhhhNhNubh)}(h:c:type:`pre_multiplied_alpha`h]j)}(hjh]hpre_multiplied_alpha}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j pre_multiplied_alphauh1hhhhKhjubh3 is the alpha pre-multiplied mode flag used to set }(hjhhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hj:h]hMPCC_ALPHA_MULTIPLIED_MODE}(hj<hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j MPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjubhk. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. }(hjhhhNhNubh)}(h:c:type:`mpcc_alpha_blend_mode`h]j)}(hj]h]hmpcc_alpha_blend_mode}(hj_hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j mpcc_alpha_blend_modeuh1hhhhKhjubho defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for }(hjhhhNhNubh)}(h:c:type:`MPCC_ALPHA_BLND_MODE`h]j)}(hjh]hMPCC_ALPHA_BLND_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j MPCC_ALPHA_BLND_MODEuh1hhhhKhjubh, as described below.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjѹhhubh)}(hhDM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM blend formula, as follows:h](hDM then maps the elements of }(hjhhhNhNubhtitle_reference)}(h`enum mpcc_alpha_blend_mode`h]henum mpcc_alpha_blend_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/ to those in the DRM blend formula, as follows:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjѹhhubh)}(hhh](h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh]h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh](j Q)}(h*MPC pixel alpha*h]hMPC pixel alpha}(hjԼhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjмubh matches }(hjмhhhNhNubj Q)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjмubh6 as the alpha component value from the plane’s pixel}(hjмhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj̼ubah}(h]h ]h"]h$]h&]uh1hhjɼhhhhhNubh)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh]h)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh](j Q)}(h*MPC global alpha*h]hMPC global alpha}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjubh matches }(hjhhhNhNubj Q)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjubh[ when the pixel alpha should be ignored and, therefore, pixel values are not pre-multiplied}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjɼhhhhhNubh)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equation h]h)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equationh](j Q)}(h*MPC global gain*h]hMPC global gain}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhj@ubh assumes }(hj@hhhNhNubj Q)}(h*MPC global alpha*h]hMPC global alpha}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhj@ubh value when both }(hj@hhhNhNubj Q)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhj@ubh and }(hj@hhhNhNubj Q)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhj@ubh" participate in the blend equation}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj<ubah}(h]h ]h"]h$]h&]uh1hhjɼhhhhhNubeh}(h]h ]h"]h$]h&]jU-j+uh1hhhhKhjѹhhubh)}(hXhIn short, *fg.alpha* is ignored by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the :c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are pre-multiplied by alpha or not.h](h In short, }(hjhhhNhNubj Q)}(h *fg.alpha*h]hfg.alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j Qhjubh is ignored by selecting }(hjhhhNhNubh)}(h,:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`h]j)}(hjh]h"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j "MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHAuh1hhhhKhjubhW. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting }(hjhhhNhNubh)}(hD:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`h]j)}(hjݽh]h:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN}(hj߽hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj۽ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j :MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAINuh1hhhhKhjubh . And the }(hjhhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hjh]hMPCC_ALPHA_MULTIPLIED_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j MPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjubhF defines if the pixel color values are pre-multiplied by alpha or not.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjѹhhubh)}(hhh](h)}(hBlend configuration flowh]hBlend configuration flow}(hj*hhhNhNubah}(h]h ]h"]h$]h&]hjQuh1hhj'hhhhhKubh)}(hYThe alpha blending equation is configured from DRM to DC interface by the following path:h]hYThe alpha blending equation is configured from DRM to DC interface by the following path:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'hhubjY)}(hhh](h)}(hX%When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC). h]h)}(hX$When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC).h](hWhen updating a }(hjMhhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hjWh]hdrm_plane_state}(hjYhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j drm_plane_stateuh1hhhhKhjMubh , DM calls }(hjMhhhNhNubh)}(h::c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()`h]j)}(hjzh]h0amdgpu_dm_plane_fill_blending_from_plane_state()}(hj|hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j 0amdgpu_dm_plane_fill_blending_from_plane_state()uh1hhhhKhjMubh that maps }(hjMhhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hjh]hdrm_plane_state}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j drm_plane_stateuh1hhhhKhjMubh attributes to }(hjMhhhNhNubh)}(h':c:type:`dc_plane_info `h]j)}(hjh]h dc_plane_info}(hj¾hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  dc_plane_infouh1hhhhKhjMubh8 struct to be handled in the OS-agnostic component (DC).}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjIubah}(h]h ]h"]h$]h&]uh1hhjFhhhhhNubh)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP. h]h)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h](hOn DC interface, }(hjhhhNhNubh)}(h.:c:type:`struct mpcc_blnd_cfg `h]j)}(hjh]hstruct mpcc_blnd_cfg}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  mpcc_blnd_cfguh1hhhhKhjubh7 programs the MPCC blend configuration considering the }(hjhhhNhNubh)}(h':c:type:`dc_plane_info `h]j)}(hjh]h dc_plane_info}(hj hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnj'j+j  dc_plane_infouh1hhhhKhjubh input from DPP.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjFhhhhhNubeh}(h]h ]h"]h$]h&]jZjZjZhjZjZuh1jYhj'hhhhhKubeh}(h]jWah ]h"]blend configuration flowah$]h&]uh1hhjѹhhhhhKubeh}(h]j8ah ]h"]blend mode propertiesah$]h&]uh1hhhhhhhhK[ubh)}(hhh](h)}(hDisplay Propertiesh]hDisplay Properties}(hjbhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj_hhhhhKubh)}(hThe 'adaptive backlight modulation' property is used for the compositor to directly control the adaptive backlight modulation power savings feature that is part of DCN hardware.h]hThe ‘adaptive backlight modulation’ property is used for the compositor to directly control the adaptive backlight modulation power savings feature that is part of DCN hardware.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:188: ./drivers/gpu/drm/amd/amdgpu/amdgpu_display.chMhj_hhubh)}(hIThe property will be attached specifically to eDP panels that support it.h]hIThe property will be attached specifically to eDP panels that support it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:188: ./drivers/gpu/drm/amd/amdgpu/amdgpu_display.chMhj_hhubh)}(hXThe property is by default set to 'sysfs' to allow the sysfs file 'panel_power_savings' to be able to control it. If set to 'off' the compositor will ensure it stays off. The other values 'min', 'bias min', 'bias max', and 'max' will control the intensity of the power savings.h]hX1The property is by default set to ‘sysfs’ to allow the sysfs file ‘panel_power_savings’ to be able to control it. If set to ‘off’ the compositor will ensure it stays off. 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