sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget6/translations/zh_CN/gpu/amdgpu/display/display-managermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/zh_TW/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/it_IT/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ja_JP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ko_KR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/sp_SP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDgpu Display Managerh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]refidid1uh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager.rsthKubhtopic)}(hTable of Contents h](h)}(hTable of Contentsh]hTable of Contents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh bullet_list)}(hhh]h list_item)}(hhh](h paragraph)}(hhh]h reference)}(hhh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]hah ]h"]h$]h&]refidamdgpu-display-manageruh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]h Lifecycle}(hhhhhNhNubah}(h]id2ah ]h"]h$]h&]refid lifecycleuh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh]h)}(hhh]h)}(hhh]h Interrupts}(hjhhhNhNubah}(h]id3ah ]h"]h$]h&]refid interruptsuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh]h)}(hhh]h)}(hhh]hAtomic Implementation}(hj@hhhNhNubah}(h]id4ah ]h"]h$]h&]refidatomic-implementationuh1hhj=ubah}(h]h ]h"]h$]h&]uh1hhj:ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]hColor Management Properties}(hjbhhhNhNubah}(h]id5ah ]h"]h$]h&]refidcolor-management-propertiesuh1hhj_ubah}(h]h ]h"]h$]h&]uh1hhj\ubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]h-DC Color Capabilities between DCN generations}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]refid-dc-color-capabilities-between-dcn-generationsuh1hhj~ubah}(h]h ]h"]h$]h&]uh1hhj{ubah}(h]h ]h"]h$]h&]uh1hhjxubah}(h]h ]h"]h$]h&]uh1hhj\ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]hBlend Mode Properties}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]refidblend-mode-propertiesuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]hBlend configuration flow}(hjhhhNhNubah}(h]id8ah ]h"]h$]h&]refidblend-configuration-flowuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]table-of-contentsah ]contentsah"]table of contentsah$]h&]uh1hhhhKhhhhubh)}(hThe AMDgpu display manager, **amdgpu_dm** (or even simpler, **dm**) sits between DRM and DC. It acts as a liaison, converting DRM requests into DC requests, and DC responses into DRM responses.h](hThe AMDgpu display manager, }(hjhhhNhNubhstrong)}(h **amdgpu_dm**h]h amdgpu_dm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (or even simpler, }(hjhhhNhNubj)}(h**dm**h]hdm}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh) sits between DRM and DC. It acts as a liaison, converting DRM requests into DC requests, and DC responses into DRM responses.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:8: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chKhhhhubh)}(h_The root control structure is :c:type:`struct amdgpu_display_manager `.h](hThe root control structure is }(hjFhhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]hliteral)}(hjPh]hstruct amdgpu_display_manager}(hjThhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jRhjNubah}(h]h ]h"]h$]h&]refdoc"gpu/amdgpu/display/display-manager refdomainj_reftypetype refexplicitrefwarn reftargetamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:8: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chKhjFubh.}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjshKhhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singledm_compressor_info (C struct)c.dm_compressor_infohNtauh1j~hhhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhNubhdesc)}(hhh](hdesc_signature)}(hdm_compressor_infoh]hdesc_signature_line)}(hstruct dm_compressor_infoh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hdm_compressor_infoh]h desc_sig_name)}(hjh]hdm_compressor_info}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(h,Buffer info used by frame buffer compressionh]h,Buffer info used by frame buffer compression}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKbhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j_structeh"]h$]h&]domainj_objtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhhhjhNubh container)}(h**Definition**:: struct dm_compressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; uint64_t gpu_addr; }; **Members** ``cpu_addr`` MMIO cpu addr ``bo_ptr`` Pointer to the buffer object ``gpu_addr`` MMIO gpu addrh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh:}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKfhj!ubh literal_block)}(hgstruct dm_compressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; uint64_t gpu_addr; };h]hgstruct dm_compressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; uint64_t gpu_addr; };}hjDsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhj!ubh)}(h **Members**h]j)}(hjUh]hMembers}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKnhj!ubhdefinition_list)}(hhh](hdefinition_list_item)}(h``cpu_addr`` MMIO cpu addr h](hterm)}(h ``cpu_addr``h]jS)}(hjzh]hcpu_addr}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjxubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKdhjrubh definition)}(hhh]h)}(h MMIO cpu addrh]h MMIO cpu addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKdhjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jphjhKdhjmubjq)}(h(``bo_ptr`` Pointer to the buffer object h](jw)}(h ``bo_ptr``h]jS)}(hjh]hbo_ptr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKehjubj)}(hhh]h)}(hPointer to the buffer objecth]hPointer to the buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKehjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKehjmubjq)}(h``gpu_addr`` MMIO gpu addrh](jw)}(h ``gpu_addr``h]jS)}(hjh]hgpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKehjubj)}(hhh]h)}(h MMIO gpu addrh]h MMIO gpu addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKehjmubeh}(h]h ]h"]h$]h&]uh1jkhj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdmub_hpd_work (C struct)c.dmub_hpd_workhNtauh1j~hhhhhjhNubj)}(hhh](j)}(h dmub_hpd_workh]j)}(hstruct dmub_hpd_workh](j)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKlubj)}(h h]h }(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDhhhjUhKlubj)}(h dmub_hpd_workh]j)}(hjBh]h dmub_hpd_work}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ](jjeh"]h$]h&]jjuh1jhjDhhhjUhKlubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj@hhhjUhKlubah}(h]j;ah ](jjeh"]h$]h&]jj)jhuh1jhjUhKlhj=hhubj)}(hhh]h)}(h5Handle time consuming work in low priority outbox IRQh]h5Handle time consuming work in low priority outbox IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKphjhhubah}(h]h ]h"]h$]h&]uh1jhj=hhhjUhKlubeh}(h]h ](j_structeh"]h$]h&]jj_jjjjjjjuh1jhhhhhjhNubj )}(hXc**Definition**:: struct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; }; **Members** ``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq ``dmub_notify`` notification for callback function ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKthjubjC)}(hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };h]hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKvhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhK|hjubjl)}(hhh](jq)}(hS``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq h](jw)}(h``handle_hpd_work``h]jS)}(hjh]hhandle_hpd_work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKshjubj)}(hhh]h)}(h>Work to be executed in a separate thread to handle hpd_low_irqh]h>Work to be executed in a separate thread to handle hpd_low_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKshj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj hKshjubjq)}(h3``dmub_notify`` notification for callback function h](jw)}(h``dmub_notify``h]jS)}(hj0h]h dmub_notify}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj.ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKthj*ubj)}(hhh]h)}(h"notification for callback functionh]h"notification for callback function}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhKthjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jphjEhKthjubjq)}(h``adev`` amdgpu_device pointerh](jw)}(h``adev``h]jS)}(hjih]hadev}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjgubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKthjcubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKuhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jphj~hKthjubeh}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jvblank_control_work (C struct)c.vblank_control_workhNtauh1j~hhhhhjhNubj)}(hhh](j)}(hvblank_control_workh]j)}(hstruct vblank_control_workh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhK{ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhK{ubj)}(hvblank_control_workh]j)}(hjh]hvblank_control_work}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhK{ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhK{ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhK{hjhhubj)}(hhh]h)}(hWork data for vblank controlh]hWork data for vblank control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhK}hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK{ubeh}(h]h ](j_structeh"]h$]h&]jj_jjjjjjjuh1jhhhhhjhNubj )}(hX**Definition**:: struct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``acrtc`` amdgpu CRTC instance for which the event has occurred ``stream`` DC stream for which the event has occurred ``enable`` true if enabling vblankh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh:}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj!ubjC)}(hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };h]hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };}hjBsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj!ubh)}(h **Members**h]j)}(hjSh]hMembers}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj!ubjl)}(hhh](jq)}(h-``work`` Kernel work data for the work event h](jw)}(h``work``h]jS)}(hjrh]hwork}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjpubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjlubj)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jphjhKhjiubjq)}(h%``dm`` amdgpu display manager device h](jw)}(h``dm``h]jS)}(hjh]hdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjiubjq)}(h@``acrtc`` amdgpu CRTC instance for which the event has occurred h](jw)}(h ``acrtc``h]jS)}(hjh]hacrtc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h5amdgpu CRTC instance for which the event has occurredh]h5amdgpu CRTC instance for which the event has occurred}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjiubjq)}(h6``stream`` DC stream for which the event has occurred h](jw)}(h ``stream``h]jS)}(hjh]hstream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h*DC stream for which the event has occurredh]h*DC stream for which the event has occurred}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hKhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj2hKhjiubjq)}(h"``enable`` true if enabling vblankh](jw)}(h ``enable``h]jS)}(hjVh]henable}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjTubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjPubj)}(hhh]h)}(htrue if enabling vblankh]htrue if enabling vblank}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jphjkhKhjiubeh}(h]h ]h"]h$]h&]uh1jkhj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jidle_workqueue (C struct)c.idle_workqueuehNtauh1j~hhhhhjhNubj)}(hhh](j)}(hidle_workqueueh]j)}(hstruct idle_workqueueh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hidle_workqueueh]j)}(hjh]hidle_workqueue}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h%Work data for periodic action in idleh]h%Work data for periodic action in idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j_structeh"]h$]h&]jj_jj jj jjjuh1jhhhhhjhNubj )}(hX_**Definition**:: struct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``enable`` true if idle worker is enabled ``running`` true if idle worker is runningh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubjC)}(hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };h]hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };}hj/sbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hj@h]hMembers}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubjl)}(hhh](jq)}(h-``work`` Kernel work data for the work event h](jw)}(h``work``h]jS)}(hj_h]hwork}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj]ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjYubj)}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthKhjuubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jphjthKhjVubjq)}(h%``dm`` amdgpu display manager device h](jw)}(h``dm``h]jS)}(hjh]hdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjVubjq)}(h*``enable`` true if idle worker is enabled h](jw)}(h ``enable``h]jS)}(hjh]henable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(htrue if idle worker is enabledh]htrue if idle worker is enabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjVubjq)}(h*``running`` true if idle worker is runningh](jw)}(h ``running``h]jS)}(hj h]hrunning}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(htrue if idle worker is runningh]htrue if idle worker is running}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjVubeh}(h]h ]h"]h$]h&]uh1jkhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_luminance_data (C struct)c.amdgpu_dm_luminance_datahNtauh1j~hhhhhjhNubj)}(hhh](j)}(hamdgpu_dm_luminance_datah]j)}(hstruct amdgpu_dm_luminance_datah](j)}(hjh]hstruct}(hjd hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj` hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hjr hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj` hhhjq hKubj)}(hamdgpu_dm_luminance_datah]j)}(hj^ h]hamdgpu_dm_luminance_data}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj` hhhjq hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj\ hhhjq hKubah}(h]jW ah ](jjeh"]h$]h&]jj)jhuh1jhjq hKhjY hhubj)}(hhh]h)}(hCustom luminance datah]hCustom luminance data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhjY hhhjq hKubeh}(h]h ](j_structeh"]h$]h&]jj_jj jj jjjuh1jhhhhhjhNubj )}(h**Definition**:: struct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; }; **Members** ``luminance`` Luminance in percent ``input_signal`` Input signal in range 0-255h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubjC)}(hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };h]hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubjl)}(hhh](jq)}(h#``luminance`` Luminance in percent h](jw)}(h ``luminance``h]jS)}(hj h]h luminance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(hLuminance in percenth]hLuminance in percent}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj( hKhj) ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj( hKhj ubjq)}(h,``input_signal`` Input signal in range 0-255h](jw)}(h``input_signal``h]jS)}(hjL h]h input_signal}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjJ ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjF ubj)}(hhh]h)}(hInput signal in range 0-255h]hInput signal in range 0-255}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjb ubah}(h]h ]h"]h$]h&]uh1jhjF ubeh}(h]h ]h"]h$]h&]uh1jphja hKhj ubeh}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_backlight_caps (C struct)c.amdgpu_dm_backlight_capshNtauh1j~hhhhhjhNubj)}(hhh](j)}(hamdgpu_dm_backlight_capsh]j)}(hstruct amdgpu_dm_backlight_capsh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hKubj)}(hamdgpu_dm_backlight_capsh]j)}(hj h]hamdgpu_dm_backlight_caps}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhj hhubj)}(hhh]h)}(hInformation about backlighth]hInformation about backlight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](j_structeh"]h$]h&]jj_jj jj jjjuh1jhhhhhjhNubj )}(hX**Definition**:: struct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; **Members** ``ext_caps`` Keep the data struct with all the information about the display support for HDR. ``aux_min_input_signal`` Min brightness value supported by the display ``aux_max_input_signal`` Max brightness value supported by the display in nits. ``min_input_signal`` minimum possible input in range 0-255. ``max_input_signal`` maximum possible input in range 0-255. ``caps_valid`` true if these values are from the ACPI interface. ``aux_support`` Describes if the display supports AUX backlight. ``ac_level`` the default brightness if booted on AC ``dc_level`` the default brightness if booted on DC ``data_points`` the number of custom luminance data points ``luminance_data`` custom luminance datah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubjC)}(hXlstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };h]hXlstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };}hj% sbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj6 h]hMembers}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4 ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubjl)}(hhh](jq)}(h^``ext_caps`` Keep the data struct with all the information about the display support for HDR. h](jw)}(h ``ext_caps``h]jS)}(hjU h]hext_caps}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjS ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjO ubj)}(hhh]h)}(hPKeep the data struct with all the information about the display support for HDR.h]hPKeep the data struct with all the information about the display support for HDR.}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjk ubah}(h]h ]h"]h$]h&]uh1jhjO ubeh}(h]h ]h"]h$]h&]uh1jphjj hKhjL ubjq)}(hG``aux_min_input_signal`` Min brightness value supported by the display h](jw)}(h``aux_min_input_signal``h]jS)}(hj h]haux_min_input_signal}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h-Min brightness value supported by the displayh]h-Min brightness value supported by the display}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(hP``aux_max_input_signal`` Max brightness value supported by the display in nits. h](jw)}(h``aux_max_input_signal``h]jS)}(hj h]haux_max_input_signal}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h6Max brightness value supported by the display in nits.h]h6Max brightness value supported by the display in nits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(h<``min_input_signal`` minimum possible input in range 0-255. h](jw)}(h``min_input_signal``h]jS)}(hj h]hmin_input_signal}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h&minimum possible input in range 0-255.h]h&minimum possible input in range 0-255.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(h<``max_input_signal`` maximum possible input in range 0-255. h](jw)}(h``max_input_signal``h]jS)}(hj; h]hmax_input_signal}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj9 ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj5 ubj)}(hhh]h)}(h&maximum possible input in range 0-255.h]h&maximum possible input in range 0-255.}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP hKhjQ ubah}(h]h ]h"]h$]h&]uh1jhj5 ubeh}(h]h ]h"]h$]h&]uh1jphjP hKhjL ubjq)}(hA``caps_valid`` true if these values are from the ACPI interface. h](jw)}(h``caps_valid``h]jS)}(hjt h]h caps_valid}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjr ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjn ubj)}(hhh]h)}(h1true if these values are from the ACPI interface.h]h1true if these values are from the ACPI interface.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjn ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(hA``aux_support`` Describes if the display supports AUX backlight. h](jw)}(h``aux_support``h]jS)}(hj h]h aux_support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h0Describes if the display supports AUX backlight.h]h0Describes if the display supports AUX backlight.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(h4``ac_level`` the default brightness if booted on AC h](jw)}(h ``ac_level``h]jS)}(hj h]hac_level}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h&the default brightness if booted on ACh]h&the default brightness if booted on AC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubjq)}(h4``dc_level`` the default brightness if booted on DC h](jw)}(h ``dc_level``h]jS)}(hj h]hdc_level}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(h&the default brightness if booted on DCh]h&the default brightness if booted on DC}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4 hKhj5 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj4 hKhjL ubjq)}(h;``data_points`` the number of custom luminance data points h](jw)}(h``data_points``h]jS)}(hjX h]h data_points}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjV ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjR ubj)}(hhh]h)}(h*the number of custom luminance data pointsh]h*the number of custom luminance data points}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm hKhjn ubah}(h]h ]h"]h$]h&]uh1jhjR ubeh}(h]h ]h"]h$]h&]uh1jphjm hKhjL ubjq)}(h(``luminance_data`` custom luminance datah](jw)}(h``luminance_data``h]jS)}(hj h]hluminance_data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh]h)}(hcustom luminance datah]hcustom luminance data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hKhjL ubeh}(h]h ]h"]h$]h&]uh1jkhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubh)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubh)}(h3Describe the backlight support for ACPI or eDP AUX.h]h3Describe the backlight support for ACPI or eDP AUX.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdal_allocation (C struct)c.dal_allocationhNtauh1j~hhhhhjhNubj)}(hhh](j)}(hdal_allocationh]j)}(hstruct dal_allocationh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hdal_allocationh]j)}(hj h]hdal_allocation}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h-Tracks mapped FB memory for SMU communicationh]h-Tracks mapped FB memory for SMU communication}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjQhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j_structeh"]h$]h&]jj_jjljjljjjuh1jhhhhhjhNubj )}(hXX**Definition**:: struct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; }; **Members** ``list`` list of dal allocations ``bo`` GPU buffer object ``cpu_ptr`` CPU virtual address of the GPU buffer object ``gpu_addr`` GPU virtual address of the GPU buffer objecth](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh:}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjpubjC)}(htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };h]htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjpubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjpubjl)}(hhh](jq)}(h!``list`` list of dal allocations h](jw)}(h``list``h]jS)}(hjh]hlist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hlist of dal allocationsh]hlist of dal allocations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjubjq)}(h``bo`` GPU buffer object h](jw)}(h``bo``h]jS)}(hjh]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hGPU buffer objecth]hGPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjubjq)}(h9``cpu_ptr`` CPU virtual address of the GPU buffer object h](jw)}(h ``cpu_ptr``h]jS)}(hj3h]hcpu_ptr}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj1ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj-ubj)}(hhh]h)}(h,CPU virtual address of the GPU buffer objecth]h,CPU virtual address of the GPU buffer object}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhKhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jphjHhKhjubjq)}(h9``gpu_addr`` GPU virtual address of the GPU buffer objecth](jw)}(h ``gpu_addr``h]jS)}(hjlh]hgpu_addr}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjfubj)}(hhh]h)}(h,GPU virtual address of the GPU buffer objecth]h,GPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jphjhKhjubeh}(h]h ]h"]h$]h&]uh1jkhjpubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(hpd_rx_irq_offload_work_queue (C struct)c.hpd_rx_irq_offload_work_queuehNtauh1j~hhhhhjhNubj)}(hhh](j)}(hhpd_rx_irq_offload_work_queueh]j)}(h$struct hpd_rx_irq_offload_work_queueh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hhpd_rx_irq_offload_work_queueh]j)}(hjh]hhpd_rx_irq_offload_work_queue}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h,Work queue to handle hpd_rx_irq offload workh]h,Work queue to handle hpd_rx_irq offload work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j_structeh"]h$]h&]jj_jj jj jjjuh1jhhhhhjhNubj )}(hX**Definition**:: struct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; }; **Members** ``wq`` workqueue structure to queue offload work. ``offload_lock`` To protect fields of offload work queue. ``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss ``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event ``aconnector`` The aconnector that this work queue is attached toh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubh:}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj$ubjC)}(hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };h]hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };}hjEsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj$ubh)}(h **Members**h]j)}(hjVh]hMembers}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj$ubjl)}(hhh](jq)}(h2``wq`` workqueue structure to queue offload work. h](jw)}(h``wq``h]jS)}(hjuh]hwq}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjsubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjoubj)}(hhh]h)}(h*workqueue structure to queue offload work.h]h*workqueue structure to queue offload work.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jphjhKhjlubjq)}(h:``offload_lock`` To protect fields of offload work queue. h](jw)}(h``offload_lock``h]jS)}(hjh]h offload_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(h(To protect fields of offload work queue.h]h(To protect fields of offload work queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjlubjq)}(hb``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss h](jw)}(h``is_handling_link_loss``h]jS)}(hjh]his_handling_link_loss}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(hGUsed to prevent inserting link loss event when we're handling link lossh]hIUsed to prevent inserting link loss event when we’re handling link loss}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhKhjlubjq)}(h``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event h](jw)}(h!``is_handling_mst_msg_rdy_event``h]jS)}(hj!h]his_handling_mst_msg_rdy_event}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh]h)}(heUsed to prevent inserting mst message ready event when we're already handling mst message ready eventh]hgUsed to prevent inserting mst message ready event when we’re already handling mst message ready event}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj6hKhjlubjq)}(hA``aconnector`` The aconnector that this work queue is attached toh](jw)}(h``aconnector``h]jS)}(hj[h]h aconnector}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjUubj)}(hhh]h)}(h2The aconnector that this work queue is attached toh]h2The aconnector that this work queue is attached to}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jphjphMhjlubeh}(h]h ]h"]h$]h&]uh1jkhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhjhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"hpd_rx_irq_offload_work (C struct)c.hpd_rx_irq_offload_workhNtauh1j~hhhhhjhNubj)}(hhh](j)}(hhpd_rx_irq_offload_workh]j)}(hstruct hpd_rx_irq_offload_workh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(hhpd_rx_irq_offload_workh]j)}(hjh]hhpd_rx_irq_offload_work}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjhhubj)}(hhh]h)}(h!hpd_rx_irq offload work structureh]h!hpd_rx_irq offload work structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](j_structeh"]h$]h&]jj_jjjjjjjuh1jhhhhhjhNubj )}(hX_**Definition**:: struct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; }; **Members** ``work`` offload work ``data`` reference irq data which is used while handling offload work ``offload_wq`` offload work queue that this work is queued toh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjubjC)}(hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; };h]hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(h **Members**h]j)}(hjEh]hMembers}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubjl)}(hhh](jq)}(h``work`` offload work h](jw)}(h``work``h]jS)}(hjdh]hwork}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjbubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hj^ubj)}(hhh]h)}(h offload workh]h offload work}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhM hjzubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jphjyhM hj[ubjq)}(hF``data`` reference irq data which is used while handling offload work h](jw)}(h``data``h]jS)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,hhhj=hMubj)}(hamdgpu_display_managerh]j)}(hj*h]hamdgpu_display_manager}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ](jjeh"]h$]h&]jjuh1jhj,hhhj=hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj(hhhj=hMubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1jhj=hMhj%hhubj)}(hhh]h)}(h%Central amdgpu display manager deviceh]h%Central amdgpu display manager device}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjohhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj=hMubeh}(h]h ](j_structeh"]h$]h&]jj_jjjjjjjuh1jhhhhhjhNubj )}(hX;**Definition**:: struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; struct mutex dpia_aux_lock; struct dml2_soc_bb *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; }; **Members** ``dc`` Display Core control structure ``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. ``dmub_notify`` Notification from DMUB. ``dmub_callback`` Callback functions to handle notification from DMUB. ``dmub_thread_offload`` Flag to indicate if callback is offload. ``dmub_fb_info`` Framebuffer regions for the DMUB. ``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. ``dmub_bo`` Buffer object for the DMUB. ``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. ``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. ``dmcub_fw_version`` DMCUB firmware version. ``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. ``adev`` AMDGPU base driver structure ``ddev`` DRM base driver structure ``display_indexes_num`` Max number of display streams supported ``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. ``dc_lock`` Guards access to DC functions that can issue register write sequences. ``audio_lock`` Guards access to audio instance changes. ``audio_component`` Used to notify ELD changes to sound driver. ``audio_registered`` True if the audio component has been registered successfully, false otherwise. ``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). ``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. ``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. ``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. ``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. ``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. ``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. ``dmub_outbox_params`` DMUB Outbox parameters ``irq_handler_list_table_lock`` Synchronizes access to IRQ tables ``backlight_dev`` Backlight control device ``backlight_link`` Link on which to control backlight ``num_of_edps`` number of backlight eDPs ``backlight_caps`` Capabilities of the backlight device ``freesync_module`` Module handling freesync calculations ``hdcp_workqueue`` AMDGPU content protection queue ``vblank_control_workqueue`` Deferred work for vblank control events. ``idle_workqueue`` Periodic work for idle events. ``cached_state`` Caches device atomic state for suspend/resume ``cached_dc_state`` Cached state of content streams ``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` ``fw_dmcu`` Reference to DMCU firmware ``dmcu_fw_version`` Version of the DMCU firmware ``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW ``active_vblank_irq_count`` number of currently active vblank irqs ``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. ``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq ``mst_encoders`` fake encoders used for DP MST. ``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. ``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true ``dmcub_trace_event_en`` enable dmcub trace events ``da_list`` DAL fb memory allocation list, for communication with SMU. ``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done ``delayed_hpd_wq`` work queue used to delay DMUB HPD work ``brightness`` cached backlight values. ``actual_brightness`` last successfully applied backlight values. ``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform ``dpia_aux_lock`` Guards access to DPIA AUX ``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ ``oem_i2c`` OEM i2c bush](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubjC)}(hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; struct mutex dpia_aux_lock; struct dml2_soc_bb *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; };h]hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; struct mutex dpia_aux_lock; struct dml2_soc_bb *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM`hjubjl)}(hhh](jq)}(h&``dc`` Display Core control structure h](jw)}(h``dc``h]jS)}(hjh]hdc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hDisplay Core control structureh]hDisplay Core control structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. h](jw)}(h ``dmub_srv``h]jS)}(hjh]hdmub_srv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM?hjubj)}(hhh]h)}(hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.h]hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM=hj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj-hM?hjubjq)}(h(``dmub_notify`` Notification from DMUB. h](jw)}(h``dmub_notify``h]jS)}(hjRh]h dmub_notify}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjPubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjLubj)}(hhh]h)}(hNotification from DMUB.h]hNotification from DMUB.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMFhjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jphjghMFhjubjq)}(hG``dmub_callback`` Callback functions to handle notification from DMUB. h](jw)}(h``dmub_callback``h]jS)}(hjh]h dmub_callback}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMNhjubj)}(hhh]h)}(h4Callback functions to handle notification from DMUB.h]h4Callback functions to handle notification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMNhjubjq)}(hA``dmub_thread_offload`` Flag to indicate if callback is offload. h](jw)}(h``dmub_thread_offload``h]jS)}(hjh]hdmub_thread_offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMVhjubj)}(hhh]h)}(h(Flag to indicate if callback is offload.h]h(Flag to indicate if callback is offload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMVhjubjq)}(h3``dmub_fb_info`` Framebuffer regions for the DMUB. h](jw)}(h``dmub_fb_info``h]jS)}(hjh]h dmub_fb_info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM^hjubj)}(hhh]h)}(h!Framebuffer regions for the DMUB.h]h!Framebuffer regions for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM^hjubjq)}(hG``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. h](jw)}(h ``dmub_fw``h]jS)}(hj6h]hdmub_fw}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj4ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMehj0ubj)}(hhh]h)}(h:DMUB firmware, required on hardware that has DMUB support.h]h:DMUB firmware, required on hardware that has DMUB support.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMehjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jphjKhMehjubjq)}(h(``dmub_bo`` Buffer object for the DMUB. h](jw)}(h ``dmub_bo``h]jS)}(hjoh]hdmub_bo}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjmubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMlhjiubj)}(hhh]h)}(hBuffer object for the DMUB.h]hBuffer object for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMlhjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jphjhMlhjubjq)}(hE``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. h](jw)}(h``dmub_bo_gpu_addr``h]jS)}(hjh]hdmub_bo_gpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMshjubj)}(hhh]h)}(h/GPU virtual address for the DMUB buffer object.h]h/GPU virtual address for the DMUB buffer object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMshjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMshjubjq)}(h=``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. h](jw)}(h``dmub_bo_cpu_addr``h]jS)}(hjh]hdmub_bo_cpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMzhjubj)}(hhh]h)}(h'CPU address for the DMUB buffer object.h]h'CPU address for the DMUB buffer object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMzhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMzhjubjq)}(h-``dmcub_fw_version`` DMCUB firmware version. h](jw)}(h``dmcub_fw_version``h]jS)}(hjh]hdmcub_fw_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hDMCUB firmware version.h]hDMCUB firmware version.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj/hMhjubjq)}(hf``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. h](jw)}(h``cgs_device``h]jS)}(hjSh]h cgs_device}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjQubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjMubj)}(hhh]h)}(hVThe Common Graphics Services device. It provides an interface for accessing registers.h]hVThe Common Graphics Services device. It provides an interface for accessing registers.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jphjhhMhjubjq)}(h&``adev`` AMDGPU base driver structure h](jw)}(h``adev``h]jS)}(hjh]hadev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hAMDGPU base driver structureh]hAMDGPU base driver structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h#``ddev`` DRM base driver structure h](jw)}(h``ddev``h]jS)}(hjh]hddev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hDRM base driver structureh]hDRM base driver structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h@``display_indexes_num`` Max number of display streams supported h](jw)}(h``display_indexes_num``h]jS)}(hjh]hdisplay_indexes_num}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjubj)}(hhh]h)}(h'Max number of display streams supportedh]h'Max number of display streams supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM hjubjq)}(h``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. h](jw)}(h``atomic_obj``h]jS)}(hj8h]h atomic_obj}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj6ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj2ubj)}(hhh]h)}(hIn combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`.h](hIn combination with }(hjQhhhNhNubh)}(h:c:type:`dm_atomic_state`h]jS)}(hj[h]hdm_atomic_state}(hj]hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sbjqdm_atomic_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjQubhb it helps manage global atomic state that doesn’t map cleanly into existing drm resources, like }(hjQhhhNhNubh)}(h:c:type:`dc_context`h]jS)}(hjh]h dc_context}(hjhhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq dc_contextuh1hhjhMhjQubh.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jphjMhMhjubjq)}(hS``dc_lock`` Guards access to DC functions that can issue register write sequences. h](jw)}(h ``dc_lock``h]jS)}(hjh]hdc_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hFGuards access to DC functions that can issue register write sequences.h]hFGuards access to DC functions that can issue register write sequences.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h8``audio_lock`` Guards access to audio instance changes. h](jw)}(h``audio_lock``h]jS)}(hjh]h audio_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(h(Guards access to audio instance changes.h]h(Guards access to audio instance changes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h@``audio_component`` Used to notify ELD changes to sound driver. h](jw)}(h``audio_component``h]jS)}(hj3h]haudio_component}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj1ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj-ubj)}(hhh]h)}(h+Used to notify ELD changes to sound driver.h]h+Used to notify ELD changes to sound driver.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhMhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jphjHhMhjubjq)}(hd``audio_registered`` True if the audio component has been registered successfully, false otherwise. h](jw)}(h``audio_registered``h]jS)}(hjlh]haudio_registered}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjfubj)}(hhh]h)}(hNTrue if the audio component has been registered successfully, false otherwise.h]hNTrue if the audio component has been registered successfully, false otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(hX;``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). h](jw)}(h``irq_handler_list_low_tab``h]jS)}(hjh]hirq_handler_list_low_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](h)}(hLow priority IRQ handler table.h]hLow priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.h]hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hONote that handlers are called in the same order as they were registered (FIFO).h]hONote that handlers are called in the same order as they were registered (FIFO).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. h](jw)}(h``irq_handler_list_high_tab``h]jS)}(hjh]hirq_handler_list_high_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](h)}(h High priority IRQ handler table.h]h High priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately.h](hIt is a n*m table, same as }(hj&hhhNhNubh)}(h":c:type:`irq_handler_list_low_tab`h]jS)}(hj0h]hirq_handler_list_low_tab}(hj2hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj.ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqirq_handler_list_low_tabuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubhN. However, handlers in this table are not deferred and are called immediately.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(hY``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. h](jw)}(h``pflip_params``h]jS)}(hjjh]h pflip_params}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjhubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjdubj)}(hhh]h)}(hGPage flip IRQ parameters, passed to registered handlers when triggered.h]hGPage flip IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(hb``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. h](jw)}(h``vblank_params``h]jS)}(hjh]h vblank_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hOVertical blanking IRQ parameters, passed to registered handlers when triggered.h]hOVertical blanking IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(hh``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. h](jw)}(h``vline0_params``h]jS)}(hjh]h vline0_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.h]hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(ha``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. h](jw)}(h``vupdate_params``h]jS)}(hjh]hvupdate_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hMVertical update IRQ parameters, passed to registered handlers when triggered.h]hMVertical update IRQ parameters, passed to registered handlers when triggered.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj-hMhjubjq)}(he``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. h](jw)}(h``dmub_trace_params``h]jS)}(hjRh]hdmub_trace_params}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjPubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjLubj)}(hhh]h)}(hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.h]hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jphjghMhjubjq)}(h.``dmub_outbox_params`` DMUB Outbox parameters h](jw)}(h``dmub_outbox_params``h]jS)}(hjh]hdmub_outbox_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM0hjubj)}(hhh]h)}(hDMUB Outbox parametersh]hDMUB Outbox parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM0hjubjq)}(hB``irq_handler_list_table_lock`` Synchronizes access to IRQ tables h](jw)}(h``irq_handler_list_table_lock``h]jS)}(hjh]hirq_handler_list_table_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM!hjubj)}(hhh]h)}(h!Synchronizes access to IRQ tablesh]h!Synchronizes access to IRQ tables}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM!hjubjq)}(h+``backlight_dev`` Backlight control device h](jw)}(h``backlight_dev``h]jS)}(hjh]h backlight_dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM"hjubj)}(hhh]h)}(hBacklight control deviceh]hBacklight control device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM"hjubjq)}(h6``backlight_link`` Link on which to control backlight h](jw)}(h``backlight_link``h]jS)}(hj7h]hbacklight_link}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj5ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM#hj1ubj)}(hhh]h)}(h"Link on which to control backlighth]h"Link on which to control backlight}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhM#hjMubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jphjLhM#hjubjq)}(h)``num_of_edps`` number of backlight eDPs h](jw)}(h``num_of_edps``h]jS)}(hjph]h num_of_edps}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjnubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM1hjjubj)}(hhh]h)}(hnumber of backlight eDPsh]hnumber of backlight eDPs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM1hjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jphjhM1hjubjq)}(h8``backlight_caps`` Capabilities of the backlight device h](jw)}(h``backlight_caps``h]jS)}(hjh]hbacklight_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM$hjubj)}(hhh]h)}(h$Capabilities of the backlight deviceh]h$Capabilities of the backlight device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM$hjubjq)}(h:``freesync_module`` Module handling freesync calculations h](jw)}(h``freesync_module``h]jS)}(hjh]hfreesync_module}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM%hjubj)}(hhh]h)}(h%Module handling freesync calculationsh]h%Module handling freesync calculations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM%hjubjq)}(h3``hdcp_workqueue`` AMDGPU content protection queue h](jw)}(h``hdcp_workqueue``h]jS)}(hjh]hhdcp_workqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM&hjubj)}(hhh]h)}(hAMDGPU content protection queueh]hAMDGPU content protection queue}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hM&hj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj0hM&hjubjq)}(hF``vblank_control_workqueue`` Deferred work for vblank control events. h](jw)}(h``vblank_control_workqueue``h]jS)}(hjTh]hvblank_control_workqueue}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjRubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjNubj)}(hhh]h)}(h(Deferred work for vblank control events.h]h(Deferred work for vblank control events.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jphjihMhjubjq)}(h2``idle_workqueue`` Periodic work for idle events. h](jw)}(h``idle_workqueue``h]jS)}(hjh]hidle_workqueue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh]h)}(hPeriodic work for idle events.h]hPeriodic work for idle events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubjq)}(h?``cached_state`` Caches device atomic state for suspend/resume h](jw)}(h``cached_state``h]jS)}(hjh]h cached_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM*hjubj)}(hhh]h)}(h-Caches device atomic state for suspend/resumeh]h-Caches device atomic state for suspend/resume}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM*hjubjq)}(h4``cached_dc_state`` Cached state of content streams h](jw)}(h``cached_dc_state``h]jS)}(hjh]hcached_dc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM+hjubj)}(hhh]h)}(hCached state of content streamsh]hCached state of content streams}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM+hjubjq)}(hm``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` h](jw)}(h``compressor``h]jS)}(hj8h]h compressor}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj6ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM,hj2ubj)}(hhh]h)}(h]Frame buffer compression buffer. See :c:type:`struct dm_compressor_info `h](h%Frame buffer compression buffer. See }(hjQhhhNhNubh)}(h8:c:type:`struct dm_compressor_info `h]jS)}(hj[h]hstruct dm_compressor_info}(hj]hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqdm_compressor_infouh1hhjMhM,hjQubeh}(h]h ]h"]h$]h&]uh1hhjMhM,hjNubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jphjMhM,hjubjq)}(h'``fw_dmcu`` Reference to DMCU firmware h](jw)}(h ``fw_dmcu``h]jS)}(hjh]hfw_dmcu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM'hjubj)}(hhh]h)}(hReference to DMCU firmwareh]hReference to DMCU firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM'hjubjq)}(h1``dmcu_fw_version`` Version of the DMCU firmware h](jw)}(h``dmcu_fw_version``h]jS)}(hjh]hdmcu_fw_version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM(hjubj)}(hhh]h)}(hVersion of the DMCU firmwareh]hVersion of the DMCU firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM(hjubjq)}(h^``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW h](jw)}(h``soc_bounding_box``h]jS)}(hjh]hsoc_bounding_box}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM&hjubj)}(hhh]h)}(hHgpu_info FW provided soc bounding box struct or 0 if not available in FWh]hHgpu_info FW provided soc bounding box struct or 0 if not available in FW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM&hjubjq)}(hC``active_vblank_irq_count`` number of currently active vblank irqs h](jw)}(h``active_vblank_irq_count``h]jS)}(hj<h]hactive_vblank_irq_count}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj:ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM-hj6ubj)}(hhh]h)}(h&number of currently active vblank irqsh]h&number of currently active vblank irqs}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhM-hjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jphjQhM-hjubjq)}(h|``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. h](jw)}(h``secure_display_ctx``h]jS)}(hjuh]hsecure_display_ctx}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjsubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM6hjoubj)}(hhh]h)}(hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.h]hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM5hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jphjhM6hjubjq)}(h@``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq h](jw)}(h``hpd_rx_offload_wq``h]jS)}(hjh]hhpd_rx_offload_wq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM=hjubj)}(hhh]h)}(h)Work queue to offload works of hpd_rx_irqh]h)Work queue to offload works of hpd_rx_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM=hjubjq)}(h0``mst_encoders`` fake encoders used for DP MST. h](jw)}(h``mst_encoders``h]jS)}(hjh]h mst_encoders}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMChjubj)}(hhh]h)}(hfake encoders used for DP MST.h]hfake encoders used for DP MST.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMChjubjq)}(hv``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. h](jw)}(h``force_timing_sync``h]jS)}(hj!h]hforce_timing_sync}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM.hjubj)}(hhh]h)}(h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.h]h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM-hj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphj6hM.hjubjq)}(h[``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true h](jw)}(h``disable_hpd_irq``h]jS)}(hj[h]hdisable_hpd_irq}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM3hjUubj)}(hhh]h)}(hFdisables all HPD and HPD RX interrupt handling in the driver when trueh]hFdisables all HPD and HPD RX interrupt handling in the driver when true}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM2hjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jphjphM3hjubjq)}(h3``dmcub_trace_event_en`` enable dmcub trace events h](jw)}(h``dmcub_trace_event_en``h]jS)}(hjh]hdmcub_trace_event_en}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM/hjubj)}(hhh]h)}(henable dmcub trace eventsh]henable dmcub trace events}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM/hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhM/hjubjq)}(hG``da_list`` DAL fb memory allocation list, for communication with SMU. h](jw)}(h ``da_list``h]jS)}(hjh]hda_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMLhjubj)}(hhh]h)}(h:DAL fb memory allocation list, for communication with SMU.h]h:DAL fb memory allocation list, for communication with SMU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMLhjubjq)}(h[``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done h](jw)}(h``dmub_aux_transfer_done``h]jS)}(hj h]hdmub_aux_transfer_done}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM5hj ubj)}(hhh]h)}(h?struct completion used to indicate when DMUB transfers are doneh]h?struct completion used to indicate when DMUB transfers are done}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM4hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hM5hjubjq)}(h:``delayed_hpd_wq`` work queue used to delay DMUB HPD work h](jw)}(h``delayed_hpd_wq``h]jS)}(hjA h]hdelayed_hpd_wq}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj? ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM6hj; ubj)}(hhh]h)}(h&work queue used to delay DMUB HPD workh]h&work queue used to delay DMUB HPD work}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hM6hjW ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jphjV hM6hjubjq)}(h(``brightness`` cached backlight values. h](jw)}(h``brightness``h]jS)}(hjz h]h brightness}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjx ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMUhjt ubj)}(hhh]h)}(hcached backlight values.h]hcached backlight values.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMUhj ubah}(h]h ]h"]h$]h&]uh1jhjt ubeh}(h]h ]h"]h$]h&]uh1jphj hMUhjubjq)}(hB``actual_brightness`` last successfully applied backlight values. h](jw)}(h``actual_brightness``h]jS)}(hj h]hactual_brightness}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM[hj ubj)}(hhh]h)}(h+last successfully applied backlight values.h]h+last successfully applied backlight values.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM[hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj hM[hjubjq)}(hh``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform h](jw)}(h``aux_hpd_discon_quirk``h]jS)}(hj h]haux_hpd_discon_quirk}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMchj ubj)}(hhh]h)}(hNquirk for hpd discon while aux is on-going. occurred on certain intel platformh]hNquirk for hpd discon while aux is on-going. occurred on certain intel platform}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMbhj!ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jphj!hMchjubjq)}(h,``dpia_aux_lock`` Guards access to DPIA AUX h](jw)}(h``dpia_aux_lock``h]jS)}(hj&!h]h dpia_aux_lock}(hj(!hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj$!ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMjhj !ubj)}(hhh]h)}(hGuards access to DPIA AUXh]hGuards access to DPIA AUX}(hj?!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;!hMjhj`.h](h0The functions to do so are provided as hooks in }(hj$hhhNhNubh)}(h,:c:type:`struct amd_ip_funcs `h]jS)}(hj$h]hstruct amd_ip_funcs}(hj$hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj$ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq amd_ip_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:17: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj5$hMhj#hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_hw_init (C function) c.dm_hw_inithNtauh1j~hj#hhhNhNubj)}(hhh](j)}(h1int dm_hw_init (struct amdgpu_ip_block *ip_block)h]j)}(h0int dm_hw_init(struct amdgpu_ip_block *ip_block)h](hdesc_sig_keyword_type)}(hinth]hint}(hj[$hhhNhNubah}(h]h ]ktah"]h$]h&]uh1jY$hjU$hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM ubj)}(h h]h }(hjk$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU$hhhjj$hM ubj)}(h dm_hw_inith]j)}(h dm_hw_inith]h dm_hw_init}(hj}$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy$ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjU$hhhjj$hM ubhdesc_parameterlist)}(h"(struct amdgpu_ip_block *ip_block)h]hdesc_parameter)}(h struct amdgpu_ip_block *ip_blockh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubh)}(hhh]j)}(hamdgpu_ip_blockh]hamdgpu_ip_block}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainj_reftype identifier reftargetj$modnameN classnameNjwjz)}j}]jx ASTIdentifier)}j$j$sb c.dm_hw_initasbuh1hhj$ubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubhdesc_sig_punctuation)}(h*h]h*}(hj$hhhNhNubah}(h]h ]pah"]h$]h&]uh1j$hj$ubj)}(hip_blockh]hip_block}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj$ubah}(h]h ]h"]h$]h&]jjuh1j$hjU$hhhjj$hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjQ$hhhjj$hM ubah}(h]jL$ah ](jjeh"]h$]h&]jj)jhuh1jhjj$hM hjN$hhubj)}(hhh]h)}(hInitialize DC deviceh]hInitialize DC device}(hj'%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj$%hhubah}(h]h ]h"]h$]h&]uh1jhjN$hhhjj$hM ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj?%jj?%jjjuh1jhhhj#hNhNubj )}(hX**Parameters** ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. **Description** Initialize the :c:type:`struct amdgpu_display_manager ` device. This involves calling the initializers of each DM component, then populating the struct with them. Although the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item. Some notable things that are initialized here: - Display Core, both software and hardware - DC modules that we need (freesync and color management) - DRM software states - Interrupt sources and handlers - Vblank support - Debug FS entries, if enabledh](h)}(h**Parameters**h]j)}(hjI%h]h Parameters}(hjK%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG%ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC%ubjl)}(hhh]jq)}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](jw)}(h$``struct amdgpu_ip_block *ip_block``h]jS)}(hjh%h]h struct amdgpu_ip_block *ip_block}(hjj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjf%ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjb%ubj)}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}%hM hj~%ubah}(h]h ]h"]h$]h&]uh1jhjb%ubeh}(h]h ]h"]h$]h&]uh1jphj}%hM hj_%ubah}(h]h ]h"]h$]h&]uh1jkhjC%ubh)}(h**Description**h]j)}(hj%h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC%ubh)}(hInitialize the :c:type:`struct amdgpu_display_manager ` device. This involves calling the initializers of each DM component, then populating the struct with them.h](hInitialize the }(hj%hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]jS)}(hj%h]hstruct amdgpu_display_manager}(hj%hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj%ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj%ubhk device. This involves calling the initializers of each DM component, then populating the struct with them.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj%hM hjC%ubh)}(hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.h]hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC%ubh)}(h.Some notable things that are initialized here:h]h.Some notable things that are initialized here:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjC%ubh)}(hhh](h)}(h(Display Core, both software and hardwareh]h)}(hj&h]h(Display Core, both software and hardware}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj &ubah}(h]h ]h"]h$]h&]uh1hhj &ubh)}(h7DC modules that we need (freesync and color management)h]h)}(hj&&h]h7DC modules that we need (freesync and color management)}(hj(&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj$&ubah}(h]h ]h"]h$]h&]uh1hhj &ubh)}(hDRM software statesh]h)}(hj>&h]hDRM software states}(hj@&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj<&ubah}(h]h ]h"]h$]h&]uh1hhj &ubh)}(hInterrupt sources and handlersh]h)}(hjV&h]hInterrupt sources and handlers}(hjX&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjT&ubah}(h]h ]h"]h$]h&]uh1hhj &ubh)}(hVblank supporth]h)}(hjn&h]hVblank support}(hjp&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjl&ubah}(h]h ]h"]h$]h&]uh1hhj &ubh)}(hDebug FS entries, if enabledh]h)}(hj&h]hDebug FS entries, if enabled}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj&ubah}(h]h ]h"]h$]h&]uh1hhj &ubeh}(h]h ]h"]h$]h&]bullet-uh1hhj&hM hjC%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj#hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_hw_fini (C function) c.dm_hw_finihNtauh1j~hj#hhhNhNubj)}(hhh](j)}(h1int dm_hw_fini (struct amdgpu_ip_block *ip_block)h]j)}(h0int dm_hw_fini(struct amdgpu_ip_block *ip_block)h](jZ$)}(hinth]hint}(hj&hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj&hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM ubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&hhhj&hM ubj)}(h dm_hw_finih]j)}(h dm_hw_finih]h dm_hw_fini}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&hhhj&hM ubj$)}(h"(struct amdgpu_ip_block *ip_block)h]j$)}(h struct amdgpu_ip_block *ip_blockh](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubh)}(hhh]j)}(hamdgpu_ip_blockh]hamdgpu_ip_block}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj!'modnameN classnameNjwjz)}j}]j$)}j$j&sb c.dm_hw_finiasbuh1hhj&ubj)}(h h]h }(hj?'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj$)}(hj$h]h*}(hjM'hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj&ubj)}(hip_blockh]hip_block}(hjZ'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj&ubah}(h]h ]h"]h$]h&]jjuh1j$hj&hhhj&hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj&hhhj&hM ubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1jhj&hM hj&hhubj)}(hhh]h)}(hTeardown DC deviceh]hTeardown DC device}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj'hhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj&hM ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj'jj'jjjuh1jhhhj#hNhNubj )}(hXk**Parameters** ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. **Description** Teardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.h](h)}(h**Parameters**h]j)}(hj'h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj'ubjl)}(hhh]jq)}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](jw)}(h$``struct amdgpu_ip_block *ip_block``h]jS)}(hj'h]h struct amdgpu_ip_block *ip_block}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj'ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj'ubj)}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jphj'hM hj'ubah}(h]h ]h"]h$]h&]uh1jkhj'ubh)}(h**Description**h]j)}(hj(h]h Description}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj'ubh)}(hTeardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.h](hTeardown components within }(hj(hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]jS)}(hj (h]hstruct amdgpu_display_manager}(hj"(hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj(ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj(ubh that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.}(hj(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj=(hM hj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj#hhhNhNubeh}(h]j ah ]h"] lifecycleah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Interruptsh]h Interrupts}(hjY(hhhNhNubah}(h]h ]h"]h$]h&]hj'uh1hhjV(hhhhhKubh)}(hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.h]hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.}(hjg(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK"hjV(hhubh)}(hXOThe base driver provides IRQ source registration with DRM, handler registration into the base driver's IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. This generic handler looks up the IRQ table, and calls the respective :c:type:`amdgpu_irq_src_funcs.process ` hookups.h](hX The base driver provides IRQ source registration with DRM, handler registration into the base driver’s IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. This generic handler looks up the IRQ table, and calls the respective }(hjv(hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]jS)}(hj(h]hamdgpu_irq_src_funcs.process}(hj(hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj~(ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK&hjv(ubh hookups.}(hjv(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj(hK&hjV(hhubh)}(hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:h]hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK,hjV(hhubh)}(hhh](h)}(hS:c:type:`amdgpu_display_manager.irq_handler_list_high_tab `h]h)}(hj(h]h)}(hj(h]jS)}(hj(h]h0amdgpu_display_manager.irq_handler_list_high_tab}(hj(hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj(ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK/hj(ubah}(h]h ]h"]h$]h&]uh1hhj(hK/hj(ubah}(h]h ]h"]h$]h&]uh1hhj(ubh)}(hS:c:type:`amdgpu_display_manager.irq_handler_list_low_tab ` h]h)}(hR:c:type:`amdgpu_display_manager.irq_handler_list_low_tab `h]h)}(hj(h]jS)}(hj(h]h/amdgpu_display_manager.irq_handler_list_low_tab}(hj(hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj(ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK0hj(ubah}(h]h ]h"]h$]h&]uh1hhj)hK0hj(ubah}(h]h ]h"]h$]h&]uh1hhj(ubeh}(h]h ]h"]h$]h&]j&j&uh1hhj(hK/hjV(hhubh)}(hXThey override the base driver's IRQ table, and the effect can be seen in the hooks that DM provides for :c:type:`amdgpu_irq_src_funcs.process `. They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM's IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See dce110_register_irq_handlers() and dcn10_register_irq_handlers().h](hjThey override the base driver’s IRQ table, and the effect can be seen in the hooks that DM provides for }(hj%)hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]jS)}(hj/)h]hamdgpu_irq_src_funcs.process}(hj1)hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj-)ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK2hj%)ubhX . They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM’s IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See dce110_register_irq_handlers() and dcn10_register_irq_handlers().}(hj%)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjL)hK2hjV(hhubh)}(hTo expose DC's hardware interrupt toggle to the base driver, DM implements :c:type:`amdgpu_irq_src_funcs.set ` hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.h](hMTo expose DC’s hardware interrupt toggle to the base driver, DM implements }(hjW)hhhNhNubh)}(h9:c:type:`amdgpu_irq_src_funcs.set `h]jS)}(hja)h]hamdgpu_irq_src_funcs.set}(hjc)hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj_)ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK9hjW)ubh\ hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.}(hjW)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj~)hK9hjV(hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_dm_irq_handler_data (C struct)c.amdgpu_dm_irq_handler_datahNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(hamdgpu_dm_irq_handler_datah]j)}(h!struct amdgpu_dm_irq_handler_datah](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhj)hKubj)}(hamdgpu_dm_irq_handler_datah]j)}(hj)h]hamdgpu_dm_irq_handler_data}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj)hhhj)hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj)hhhj)hKubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1jhj)hKhj)hhubj)}(hhh]h)}(hData for DM interrupt handlers.h]hData for DM interrupt handlers.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKEhj)hhubah}(h]h ]h"]h$]h&]uh1jhj)hhhj)hKubeh}(h]h ](j_structeh"]h$]h&]jj_jj)jj)jjjuh1jhhhjV(hNhNubj )}(hX?**Definition**:: struct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; }; **Members** ``list`` Linked list entry referencing the next/previous handler ``handler`` Handler function ``handler_arg`` Argument passed to the handler when triggered ``dm`` DM which this handler belongs to ``irq_source`` DC interrupt source that this handler is registered for ``work`` work structh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh:}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKIhj*ubjC)}(hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };h]hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };}hj!*sbah}(h]h ]h"]h$]h&]jjuh1jBh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKKhj*ubh)}(h **Members**h]j)}(hj2*h]hMembers}(hj4*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKThj*ubjl)}(hhh](jq)}(hA``list`` Linked list entry referencing the next/previous handler h](jw)}(h``list``h]jS)}(hjQ*h]hlist}(hjS*hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjO*ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKHhjK*ubj)}(hhh]h)}(h7Linked list entry referencing the next/previous handlerh]h7Linked list entry referencing the next/previous handler}(hjj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf*hKHhjg*ubah}(h]h ]h"]h$]h&]uh1jhjK*ubeh}(h]h ]h"]h$]h&]uh1jphjf*hKHhjH*ubjq)}(h``handler`` Handler function h](jw)}(h ``handler``h]jS)}(hj*h]hhandler}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj*ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKIhj*ubj)}(hhh]h)}(hHandler functionh]hHandler function}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKIhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jphj*hKIhjH*ubjq)}(h>``handler_arg`` Argument passed to the handler when triggered h](jw)}(h``handler_arg``h]jS)}(hj*h]h handler_arg}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj*ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKJhj*ubj)}(hhh]h)}(h-Argument passed to the handler when triggeredh]h-Argument passed to the handler when triggered}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKJhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jphj*hKJhjH*ubjq)}(h(``dm`` DM which this handler belongs to h](jw)}(h``dm``h]jS)}(hj*h]hdm}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj*ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKKhj*ubj)}(hhh]h)}(h DM which this handler belongs toh]h DM which this handler belongs to}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hKKhj+ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jphj+hKKhjH*ubjq)}(hG``irq_source`` DC interrupt source that this handler is registered for h](jw)}(h``irq_source``h]jS)}(hj5+h]h irq_source}(hj7+hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj3+ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhj/+ubj)}(hhh]h)}(h7DC interrupt source that this handler is registered forh]h7DC interrupt source that this handler is registered for}(hjN+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ+hKLhjK+ubah}(h]h ]h"]h$]h&]uh1jhj/+ubeh}(h]h ]h"]h$]h&]uh1jphjJ+hKLhjH*ubjq)}(h``work`` work structh](jw)}(h``work``h]jS)}(hjn+h]hwork}(hjp+hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjl+ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhjh+ubj)}(hhh]h)}(h work structh]h work struct}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKMhj+ubah}(h]h ]h"]h$]h&]uh1jhjh+ubeh}(h]h ]h"]h$]h&]uh1jphj+hKLhjH*ubeh}(h]h ]h"]h$]h&]uh1jkhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_irq_work_func (C function)c.dm_irq_work_funchNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h0void dm_irq_work_func (struct work_struct *work)h]j)}(h/void dm_irq_work_func(struct work_struct *work)h](jZ$)}(hvoidh]hvoid}(hj+hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj+hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKrubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhj+hKrubj)}(hdm_irq_work_funch]j)}(hdm_irq_work_funch]hdm_irq_work_func}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj+hhhj+hKrubj$)}(h(struct work_struct *work)h]j$)}(hstruct work_struct *workh](j)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubh)}(hhh]j)}(h work_structh]h work_struct}(hj#,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ,ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj%,modnameN classnameNjwjz)}j}]j$)}j$j+sbc.dm_irq_work_funcasbuh1hhj,ubj)}(h h]h }(hjC,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj$)}(hj$h]h*}(hjQ,hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj,ubj)}(hworkh]hwork}(hj^,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj+ubah}(h]h ]h"]h$]h&]jjuh1j$hj+hhhj+hKrubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj+hhhj+hKrubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1jhj+hKrhj+hhubj)}(hhh]h)}(h6Handle an IRQ outside of the interrupt handler proper.h]h6Handle an IRQ outside of the interrupt handler proper.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKnhj,hhubah}(h]h ]h"]h$]h&]uh1jhj+hhhj+hKrubeh}(h]h ](j_functioneh"]h$]h&]jj_jj,jj,jjjuh1jhhhjV(hNhNubj )}(h:**Parameters** ``struct work_struct *work`` work structh](h)}(h**Parameters**h]j)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKrhj,ubjl)}(hhh]jq)}(h(``struct work_struct *work`` work structh](jw)}(h``struct work_struct *work``h]jS)}(hj,h]hstruct work_struct *work}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj,ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKthj,ubj)}(hhh]h)}(h work structh]h work struct}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKphj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jphj,hKthj,ubah}(h]h ]h"]h$]h&]uh1jkhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(unregister_all_irq_handlers (C function)c.unregister_all_irq_handlershNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h=void unregister_all_irq_handlers (struct amdgpu_device *adev)h]j)}(h0hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj/ubj$)}(hj0h]h)}(hjK0hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj/ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj.ubj$)}(hvoid *handler_argsh](jZ$)}(hvoidh]hvoid}(hjc0hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj_0ubj)}(h h]h }(hjq0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_0ubj$)}(hj$h]h*}(hj0hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj_0ubj)}(h handler_argsh]h handler_args}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_0ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj.ubeh}(h]h ]h"]h$]h&]jjuh1j$hj.hhhj.hM.ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj.hhhj.hM.ubah}(h]j.ah ](jjeh"]h$]h&]jj)jhuh1jhj.hM.hj.hhubj)}(hhh]h)}(hRegister a handler within DM.h]hRegister a handler within DM.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj0hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj.hM.ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj0jj0jjjuh1jhhhjV(hNhNubj )}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device. ``struct dc_interrupt_params *int_params`` Interrupt parameters containing the source, and handler context ``void (*ih)(void *)`` Function pointer to the interrupt handler to register ``void *handler_args`` Arguments passed to the handler when the interrupt occurs **Description** Register an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep. Registered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first. **Return** Handler data :c:type:`struct amdgpu_dm_irq_handler_data ` containing the IRQ source, handler function, and argsh](h)}(h**Parameters**h]j)}(hj0h]h Parameters}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM!hj0ubjl)}(hhh](jq)}(hP``struct amdgpu_device *adev`` The base driver device containing the DM device. h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj0h]hstruct amdgpu_device *adev}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj0ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj0ubj)}(hhh]h)}(h0The base driver device containing the DM device.h]h0The base driver device containing the DM device.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 1hMhj 1ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jphj 1hMhj0ubjq)}(hk``struct dc_interrupt_params *int_params`` Interrupt parameters containing the source, and handler context h](jw)}(h*``struct dc_interrupt_params *int_params``h]jS)}(hj01h]h&struct dc_interrupt_params *int_params}(hj21hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj.1ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj*1ubj)}(hhh]h)}(h?Interrupt parameters containing the source, and handler contexth]h?Interrupt parameters containing the source, and handler context}(hjI1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE1hMhjF1ubah}(h]h ]h"]h$]h&]uh1jhj*1ubeh}(h]h ]h"]h$]h&]uh1jphjE1hMhj0ubjq)}(hM``void (*ih)(void *)`` Function pointer to the interrupt handler to register h](jw)}(h``void (*ih)(void *)``h]jS)}(hji1h]hvoid (*ih)(void *)}(hjk1hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjg1ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM hjc1ubj)}(hhh]h)}(h5Function pointer to the interrupt handler to registerh]h5Function pointer to the interrupt handler to register}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~1hM hj1ubah}(h]h ]h"]h$]h&]uh1jhjc1ubeh}(h]h ]h"]h$]h&]uh1jphj~1hM hj0ubjq)}(hQ``void *handler_args`` Arguments passed to the handler when the interrupt occurs h](jw)}(h``void *handler_args``h]jS)}(hj1h]hvoid *handler_args}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj1ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM!hj1ubj)}(hhh]h)}(h9Arguments passed to the handler when the interrupt occursh]h9Arguments passed to the handler when the interrupt occurs}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hM!hj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jphj1hM!hj0ubeh}(h]h ]h"]h$]h&]uh1jkhj0ubh)}(h**Description**h]j)}(hj1h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM#hj0ubh)}(hXRegister an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.h]hXRegister an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM#hj0ubh)}(hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.h]hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM(hj0ubh)}(h **Return**h]j)}(hj2h]hReturn}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM+hj0ubjl)}(hhh]jq)}(hHandler data :c:type:`struct amdgpu_dm_irq_handler_data ` containing the IRQ source, handler function, and argsh](jw)}(hhHandler data :c:type:`struct amdgpu_dm_irq_handler_data ` containing the IRQh](h Handler data }(hj02hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]jS)}(hj:2h]h!struct amdgpu_dm_irq_handler_data}(hj<2hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj82ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM+hj02ubh containing the IRQ}(hj02hhhNhNubeh}(h]h ]h"]h$]h&]uh1jvhjW2hM+hj,2ubj)}(hhh]h)}(h"source, handler function, and argsh]h"source, handler function, and args}(hje2hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM,hjb2ubah}(h]h ]h"]h$]h&]uh1jhj,2ubeh}(h]h ]h"]h$]h&]uh1jphjW2hM+hj)2ubah}(h]h ]h"]h$]h&]uh1jkhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/amdgpu_dm_irq_unregister_interrupt (C function)$c.amdgpu_dm_irq_unregister_interrupthNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(hmvoid amdgpu_dm_irq_unregister_interrupt (struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h]j)}(hlvoid amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](jZ$)}(hvoidh]hvoid}(hj2hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj2hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMqubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhj2hMqubj)}(h"amdgpu_dm_irq_unregister_interrupth]j)}(h"amdgpu_dm_irq_unregister_interrupth]h"amdgpu_dm_irq_unregister_interrupt}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj2hhhj2hMqubj$)}(hE(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftarget,j3modnameN classnameNjwjz)}j}]j$)}j$j2sb$c.amdgpu_dm_irq_unregister_interruptasbuh1hhj2ubj)}(h h]h }(hj!3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj$)}(hj$h]h*}(hj/3hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj2ubj)}(hadevh]hadev}(hj<3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj2ubj$)}(henum dc_irq_source irq_sourceh](j)}(henumh]henum}(hjU3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ3ubj)}(h h]h }(hjc3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ3ubh)}(hhh]j)}(h dc_irq_sourceh]h dc_irq_source}(hjt3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq3ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjv3modnameN classnameNjwjz)}j}]j3$c.amdgpu_dm_irq_unregister_interruptasbuh1hhjQ3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ3ubj)}(h irq_sourceh]h irq_source}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ3ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj2ubj$)}(hvoid *ihh](jZ$)}(hvoidh]hvoid}(hj3hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj3ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj$)}(hj$h]h*}(hj3hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj3ubj)}(hihh]hih}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj2ubeh}(h]h ]h"]h$]h&]jjuh1j$hj2hhhj2hMqubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj2hhhj2hMqubah}(h]j2ah ](jjeh"]h$]h&]jj)jhuh1jhj2hMqhj2hhubj)}(hhh]h)}(h&Remove a handler from the DM IRQ tableh]h&Remove a handler from the DM IRQ table}(hj 4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMihj 4hhubah}(h]h ]h"]h$]h&]uh1jhj2hhhj2hMqubeh}(h]h ](j_functioneh"]h$]h&]jj_jj$4jj$4jjjuh1jhhhjV(hNhNubj )}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device ``enum dc_irq_source irq_source`` IRQ source to remove the given handler from ``void *ih`` Function pointer to the interrupt handler to unregister **Description** Go through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h](h)}(h**Parameters**h]j)}(hj.4h]h Parameters}(hj04hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,4ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMmhj(4ubjl)}(hhh](jq)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hjM4h]hstruct amdgpu_device *adev}(hjO4hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjK4ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMjhjG4ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjf4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb4hMjhjc4ubah}(h]h ]h"]h$]h&]uh1jhjG4ubeh}(h]h ]h"]h$]h&]uh1jphjb4hMjhjD4ubjq)}(hN``enum dc_irq_source irq_source`` IRQ source to remove the given handler from h](jw)}(h!``enum dc_irq_source irq_source``h]jS)}(hj4h]henum dc_irq_source irq_source}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj4ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMkhj4ubj)}(hhh]h)}(h+IRQ source to remove the given handler fromh]h+IRQ source to remove the given handler from}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMkhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jphj4hMkhjD4ubjq)}(hE``void *ih`` Function pointer to the interrupt handler to unregister h](jw)}(h ``void *ih``h]jS)}(hj4h]hvoid *ih}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj4ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMlhj4ubj)}(hhh]h)}(h7Function pointer to the interrupt handler to unregisterh]h7Function pointer to the interrupt handler to unregister}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMlhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jphj4hMlhjD4ubeh}(h]h ]h"]h$]h&]uh1jkhj(4ubh)}(h**Description**h]j)}(hj4h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj(4ubh)}(hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h]hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj(4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_init (C function)c.amdgpu_dm_irq_inithNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h3int amdgpu_dm_irq_init (struct amdgpu_device *adev)h]j)}(h2int amdgpu_dm_irq_init(struct amdgpu_device *adev)h](jZ$)}(hinth]hint}(hj?5hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj;5hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hjN5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;5hhhjM5hMubj)}(hamdgpu_dm_irq_inith]j)}(hamdgpu_dm_irq_inith]hamdgpu_dm_irq_init}(hj`5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\5ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj;5hhhjM5hMubj$)}(h(struct amdgpu_device *adev)h]j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj|5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx5ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj5modnameN classnameNjwjz)}j}]j$)}j$jb5sbc.amdgpu_dm_irq_initasbuh1hhjx5ubj)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx5ubj$)}(hj$h]h*}(hj5hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjx5ubj)}(hadevh]hadev}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjx5ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjt5ubah}(h]h ]h"]h$]h&]jjuh1j$hj;5hhhjM5hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj75hhhjM5hMubah}(h]j25ah ](jjeh"]h$]h&]jj)jhuh1jhjM5hMhj45hhubj)}(hhh]h)}(hInitialize DM IRQ managementh]hInitialize DM IRQ management}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jhj45hhhjM5hMubeh}(h]h ](j_functioneh"]h$]h&]jj_jj6jj6jjjuh1jhhhjV(hNhNubj )}(hXt**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Initialize DM's high and low context IRQ tables. The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order. The low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](h)}(h**Parameters**h]j)}(hj!6h]h Parameters}(hj#6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6ubjl)}(hhh]jq)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj@6h]hstruct amdgpu_device *adev}(hjB6hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj>6ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:6ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjY6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU6hMhjV6ubah}(h]h ]h"]h$]h&]uh1jhj:6ubeh}(h]h ]h"]h$]h&]uh1jphjU6hMhj76ubah}(h]h ]h"]h$]h&]uh1jkhj6ubh)}(h**Description**h]j)}(hj{6h]h Description}(hj}6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy6ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6ubh)}(h0Initialize DM's high and low context IRQ tables.h]h2Initialize DM’s high and low context IRQ tables.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6ubh)}(hX.The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.h](h0The N by M table contains N IRQ sources, with M }(hj6hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]jS)}(hj6h]h!struct amdgpu_dm_irq_handler_data}(hj6hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj6ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6ubh hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubh)}(hThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](hpThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See }(hj6hhhNhNubh)}(h.:c:type:`struct irq_list_head `h]jS)}(hj6h]hstruct irq_list_head}(hj6hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj6ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq irq_list_headuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj6ubh.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_fini (C function)c.amdgpu_dm_irq_finihNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_irq_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_irq_fini(struct amdgpu_device *adev)h](jZ$)}(hvoidh]hvoid}(hj$7hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj 7hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj37hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj 7hhhj27hMubj)}(hamdgpu_dm_irq_finih]j)}(hamdgpu_dm_irq_finih]hamdgpu_dm_irq_fini}(hjE7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjA7ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj 7hhhj27hMubj$)}(h(struct amdgpu_device *adev)h]j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hja7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]7ubj)}(h h]h }(hjn7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]7ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|7ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj7modnameN classnameNjwjz)}j}]j$)}j$jG7sbc.amdgpu_dm_irq_finiasbuh1hhj]7ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]7ubj$)}(hj$h]h*}(hj7hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj]7ubj)}(hadevh]hadev}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]7ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjY7ubah}(h]h ]h"]h$]h&]jjuh1j$hj 7hhhj27hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj7hhhj27hMubah}(h]j7ah ](jjeh"]h$]h&]jj)jhuh1jhj27hMhj7hhubj)}(hhh]h)}(hTear down DM IRQ managementh]hTear down DM IRQ management}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj7hhubah}(h]h ]h"]h$]h&]uh1jhj7hhhj27hMubeh}(h]h ](j_functioneh"]h$]h&]jj_jj7jj7jjjuh1jhhhjV(hNhNubj )}(h**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Flush all work within the low context IRQ table.h](h)}(h**Parameters**h]j)}(hj8h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubjl)}(hhh]jq)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj%8h]hstruct amdgpu_device *adev}(hj'8hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj#8ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubj)}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hj>8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:8hMhj;8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jphj:8hMhj8ubah}(h]h ]h"]h$]h&]uh1jkhj8ubh)}(h**Description**h]j)}(hj`8h]h Description}(hjb8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^8ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubh)}(h0Flush all work within the low context IRQ table.h]h0Flush all work within the low context IRQ table.}(hjv8hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"amdgpu_dm_irq_handler (C function)c.amdgpu_dm_irq_handlerhNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(htint amdgpu_dm_irq_handler (struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h]j)}(hsint amdgpu_dm_irq_handler(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](jZ$)}(hinth]hint}(hj8hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj8hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhj8hMubj)}(hamdgpu_dm_irq_handlerh]j)}(hamdgpu_dm_irq_handlerh]hamdgpu_dm_irq_handler}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj8hhhj8hMubj$)}(hZ(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj9modnameN classnameNjwjz)}j}]j$)}j$j8sbc.amdgpu_dm_irq_handlerasbuh1hhj8ubj)}(h h]h }(hj 9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj$)}(hj$h]h*}(hj.9hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj8ubj)}(hadevh]hadev}(hj;9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj8ubj$)}(hstruct amdgpu_irq_src *sourceh](j)}(hjh]hstruct}(hjT9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP9ubj)}(h h]h }(hja9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP9ubh)}(hhh]j)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hjr9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjo9ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjt9modnameN classnameNjwjz)}j}]j9c.amdgpu_dm_irq_handlerasbuh1hhjP9ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP9ubj$)}(hj$h]h*}(hj9hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjP9ubj)}(hsourceh]hsource}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjP9ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj8ubj$)}(hstruct amdgpu_iv_entry *entryh](j)}(hjh]hstruct}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj)}(h h]h }(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubh)}(hhh]j)}(hamdgpu_iv_entryh]hamdgpu_iv_entry}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj9modnameN classnameNjwjz)}j}]j9c.amdgpu_dm_irq_handlerasbuh1hhj9ubj)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj$)}(hj$h]h*}(hj:hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj9ubj)}(hentryh]hentry}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj8ubeh}(h]h ]h"]h$]h&]jjuh1j$hj8hhhj8hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj8hhhj8hMubah}(h]j8ah ](jjeh"]h$]h&]jj)jhuh1jhj8hMhj8hhubj)}(hhh]h)}(hGeneric DM IRQ handlerh]hGeneric DM IRQ handler}(hjE:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjB:hhubah}(h]h ]h"]h$]h&]uh1jhj8hhhj8hMubeh}(h]h ](j_functioneh"]h$]h&]jj_jj]:jj]:jjjuh1jhhhjV(hNhNubj )}(hXv**Parameters** ``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device ``struct amdgpu_irq_src *source`` Unused ``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt **Description** Calls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h](h)}(h**Parameters**h]j)}(hjg:h]h Parameters}(hji:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje:ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhja:ubjl)}(hhh](jq)}(hR``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj:h]hstruct amdgpu_device *adev}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj:ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubj)}(hhh]h)}(h2amdgpu base driver device containing the DM deviceh]h2amdgpu base driver device containing the DM device}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jphj:hMhj}:ubjq)}(h)``struct amdgpu_irq_src *source`` Unused h](jw)}(h!``struct amdgpu_irq_src *source``h]jS)}(hj:h]hstruct amdgpu_irq_src *source}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj:ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubj)}(hhh]h)}(hUnusedh]hUnused}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jphj:hMhj}:ubjq)}(hE``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt h](jw)}(h!``struct amdgpu_iv_entry *entry``h]jS)}(hj:h]hstruct amdgpu_iv_entry *entry}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj:ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj:ubj)}(hhh]h)}(h"Data about the triggered interrupth]h"Data about the triggered interrupt}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jphj ;hMhj}:ubeh}(h]h ]h"]h$]h&]uh1jkhja:ubh)}(h**Description**h]j)}(hj3;h]h Description}(hj5;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhja:ubh)}(hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h]hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.}(hjI;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhja:ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_init (C function)c.amdgpu_dm_hpd_inithNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_hpd_init (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_init(struct amdgpu_device *adev)h](jZ$)}(hvoidh]hvoid}(hjx;hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjt;hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMxubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt;hhhj;hMxubj)}(hamdgpu_dm_hpd_inith]j)}(hamdgpu_dm_hpd_inith]hamdgpu_dm_hpd_init}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjt;hhhj;hMxubj$)}(h(struct amdgpu_device *adev)h]j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj;modnameN classnameNjwjz)}j}]j$)}j$j;sbc.amdgpu_dm_hpd_initasbuh1hhj;ubj)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj$)}(hj$h]h*}(hj<hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj;ubj)}(hadevh]hadev}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj;ubah}(h]h ]h"]h$]h&]jjuh1j$hjt;hhhj;hMxubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjp;hhhj;hMxubah}(h]jk;ah ](jjeh"]h$]h&]jj)jhuh1jhj;hMxhjm;hhubj)}(hhh]h)}(hhpd setup callback.h]hhpd setup callback.}(hj8<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMqhj5<hhubah}(h]h ]h"]h$]h&]uh1jhjm;hhhj;hMxubeh}(h]h ](j_functioneh"]h$]h&]jj_jjP<jjP<jjjuh1jhhhjV(hNhNubj )}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Setup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hjZ<h]h Parameters}(hj\<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX<ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMuhjT<ubjl)}(hhh]jq)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hjy<h]hstruct amdgpu_device *adev}(hj{<hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjw<ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMshjs<ubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMshj<ubah}(h]h ]h"]h$]h&]uh1jhjs<ubeh}(h]h ]h"]h$]h&]uh1jphj<hMshjp<ubah}(h]h ]h"]h$]h&]uh1jkhjT<ubh)}(h**Description**h]j)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMuhjT<ubh)}(hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h]hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMuhjT<ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_fini (C function)c.amdgpu_dm_hpd_finihNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h4void amdgpu_dm_hpd_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)h](jZ$)}(hvoidh]hvoid}(hj<hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj<hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhj=hMubj)}(hamdgpu_dm_hpd_finih]j)}(hamdgpu_dm_hpd_finih]hamdgpu_dm_hpd_fini}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj<hhhj=hMubj$)}(h(struct amdgpu_device *adev)h]j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj6=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2=ubj)}(h h]h }(hjC=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2=ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hjT=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQ=ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjV=modnameN classnameNjwjz)}j}]j$)}j$j=sbc.amdgpu_dm_hpd_finiasbuh1hhj2=ubj)}(h h]h }(hjt=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2=ubj$)}(hj$h]h*}(hj=hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj2=ubj)}(hadevh]hadev}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2=ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj.=ubah}(h]h ]h"]h$]h&]jjuh1j$hj<hhhj=hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj<hhhj=hMubah}(h]j<ah ](jjeh"]h$]h&]jj)jhuh1jhj=hMhj<hhubj)}(hhh]h)}(hhpd tear down callback.h]hhpd tear down callback.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=hhubah}(h]h ]h"]h$]h&]uh1jhj<hhhj=hMubeh}(h]h ](j_functioneh"]h$]h&]jj_jj=jj=jjjuh1jhhhjV(hNhNubj )}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Tear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hj=h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubjl)}(hhh]jq)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj=h]hstruct amdgpu_device *adev}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj=ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubj)}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jphj>hMhj=ubah}(h]h ]h"]h$]h&]uh1jkhj=ubh)}(h**Description**h]j)}(hj5>h]h Description}(hj7>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3>ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubh)}(hQTear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h]hQTear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.}(hjK>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_pflip_high_irq (C function)c.dm_pflip_high_irqhNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h/void dm_pflip_high_irq (void *interrupt_params)h]j)}(h.void dm_pflip_high_irq(void *interrupt_params)h](jZ$)}(hvoidh]hvoid}(hjz>hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjv>hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubj)}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjv>hhhj>hMubj)}(hdm_pflip_high_irqh]j)}(hdm_pflip_high_irqh]hdm_pflip_high_irq}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjv>hhhj>hMubj$)}(h(void *interrupt_params)h]j$)}(hvoid *interrupt_paramsh](jZ$)}(hvoidh]hvoid}(hj>hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj>ubj)}(h h]h }(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubj$)}(hj$h]h*}(hj>hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj>ubj)}(hinterrupt_paramsh]hinterrupt_params}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj>ubah}(h]h ]h"]h$]h&]jjuh1j$hjv>hhhj>hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjr>hhhj>hMubah}(h]jm>ah ](jjeh"]h$]h&]jj)jhuh1jhj>hMhjo>hhubj)}(hhh]h)}(hHandle pageflip interrupth]hHandle pageflip interrupt}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj?hhubah}(h]h ]h"]h$]h&]uh1jhjo>hhhj>hMubeh}(h]h ](j_functioneh"]h$]h&]jj_jj"?jj"?jjjuh1jhhhjV(hNhNubj )}(h**Parameters** ``void *interrupt_params`` ignored **Description** Handles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h](h)}(h**Parameters**h]j)}(hj,?h]h Parameters}(hj.?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj&?ubjl)}(hhh]jq)}(h#``void *interrupt_params`` ignored h](jw)}(h``void *interrupt_params``h]jS)}(hjK?h]hvoid *interrupt_params}(hjM?hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjI?ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjE?ubj)}(hhh]h)}(hignoredh]hignored}(hjd?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`?hMhja?ubah}(h]h ]h"]h$]h&]uh1jhjE?ubeh}(h]h ]h"]h$]h&]uh1jphj`?hMhjB?ubah}(h]h ]h"]h$]h&]uh1jkhj&?ubh)}(h**Description**h]j)}(hj?h]h Description}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj&?ubh)}(hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.h]hhHandles the pageflip interrupt by notifying all interested parties that the pageflip has been completed.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj&?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_crtc_high_irq (C function)c.dm_crtc_high_irqhNtauh1j~hjV(hhhNhNubj)}(hhh](j)}(h.void dm_crtc_high_irq (void *interrupt_params)h]j)}(h-void dm_crtc_high_irq(void *interrupt_params)h](jZ$)}(hvoidh]hvoid}(hj?hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj?hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM_ubj)}(h h]h }(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?hhhj?hM_ubj)}(hdm_crtc_high_irqh]j)}(hdm_crtc_high_irqh]hdm_crtc_high_irq}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj?hhhj?hM_ubj$)}(h(void *interrupt_params)h]j$)}(hvoid *interrupt_paramsh](jZ$)}(hvoidh]hvoid}(hj@hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj@ubj)}(h h]h }(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj$)}(hj$h]h*}(hj$@hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj@ubj)}(hinterrupt_paramsh]hinterrupt_params}(hj1@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj@ubah}(h]h ]h"]h$]h&]jjuh1j$hj?hhhj?hM_ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj?hhhj?hM_ubah}(h]j?ah ](jjeh"]h$]h&]jj)jhuh1jhj?hM_hj?hhubj)}(hhh]h)}(hHandles CRTC interrupth]hHandles CRTC interrupt}(hj[@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMYhjX@hhubah}(h]h ]h"]h$]h&]uh1jhj?hhhj?hM_ubeh}(h]h ](j_functioneh"]h$]h&]jj_jjs@jjs@jjjuh1jhhhjV(hNhNubj )}(h**Parameters** ``void *interrupt_params`` used for determining the CRTC instance **Description** Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK event handler.h](h)}(h**Parameters**h]j)}(hj}@h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{@ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM]hjw@ubjl)}(hhh]jq)}(hB``void *interrupt_params`` used for determining the CRTC instance h](jw)}(h``void *interrupt_params``h]jS)}(hj@h]hvoid *interrupt_params}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj@ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMZhj@ubj)}(hhh]h)}(h&used for determining the CRTC instanceh]h&used for determining the CRTC instance}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMZhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jphj@hMZhj@ubah}(h]h ]h"]h$]h&]uh1jkhjw@ubh)}(h**Description**h]j)}(hj@h]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM\hjw@ubh)}(hHHandles the CRTC/VSYNC interrupt by notfying DRM's VBLANK event handler.h]hJHandles the CRTC/VSYNC interrupt by notfying DRM’s VBLANK event handler.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM\hjw@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjV(hhhNhNubeh}(h]j-ah ]h"] interruptsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAtomic Implementationh]hAtomic Implementation}(hj AhhhNhNubah}(h]h ]h"]h$]h&]hjIuh1hhj AhhhhhK$ubh)}(h*WIP*h]hemphasis)}(hjAh]hWIP}(hj!AhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjAubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:38: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM?hj Ahhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)amdgpu_dm_atomic_commit_tail (C function)c.amdgpu_dm_atomic_commit_tailhNtauh1j~hj AhhhNhNubj)}(hhh](j)}(hBvoid amdgpu_dm_atomic_commit_tail (struct drm_atomic_state *state)h]j)}(hAvoid amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)h](jZ$)}(hvoidh]hvoid}(hjNAhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjJAhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMZ'ubj)}(h h]h }(hj]AhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJAhhhj\AhMZ'ubj)}(hamdgpu_dm_atomic_commit_tailh]j)}(hamdgpu_dm_atomic_commit_tailh]hamdgpu_dm_atomic_commit_tail}(hjoAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkAubah}(h]h ](jjeh"]h$]h&]jjuh1jhjJAhhhj\AhMZ'ubj$)}(h (struct drm_atomic_state *state)h]j$)}(hstruct drm_atomic_state *stateh](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubh)}(hhh]j)}(hdrm_atomic_stateh]hdrm_atomic_state}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjAmodnameN classnameNjwjz)}j}]j$)}j$jqAsbc.amdgpu_dm_atomic_commit_tailasbuh1hhjAubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubj$)}(hj$h]h*}(hjAhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjAubj)}(hstateh]hstate}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjAubah}(h]h ]h"]h$]h&]jjuh1j$hjJAhhhj\AhMZ'ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjFAhhhj\AhMZ'ubah}(h]jAAah ](jjeh"]h$]h&]jj)jhuh1jhj\AhMZ'hjCAhhubj)}(hhh]h)}(h'AMDgpu DM's commit tail implementation.h]h)AMDgpu DM’s commit tail implementation.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMS'hj Bhhubah}(h]h ]h"]h$]h&]uh1jhjCAhhhj\AhMZ'ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj&Bjj&Bjjjuh1jhhhj AhNhNubj )}(hX.**Parameters** ``struct drm_atomic_state *state`` The atomic state to commit **Description** This will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h](h)}(h**Parameters**h]j)}(hj0Bh]h Parameters}(hj2BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.Bubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMW'hj*Bubjl)}(hhh]jq)}(h>``struct drm_atomic_state *state`` The atomic state to commit h](jw)}(h"``struct drm_atomic_state *state``h]jS)}(hjOBh]hstruct drm_atomic_state *state}(hjQBhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjMBubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMT'hjIBubj)}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hjhBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdBhMT'hjeBubah}(h]h ]h"]h$]h&]uh1jhjIBubeh}(h]h ]h"]h$]h&]uh1jphjdBhMT'hjFBubah}(h]h ]h"]h$]h&]uh1jkhj*Bubh)}(h**Description**h]j)}(hjBh]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMV'hj*Bubh)}(hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h]hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMV'hj*Bubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj AhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_atomic_check (C function)c.amdgpu_dm_atomic_checkhNtauh1j~hj AhhhNhNubj)}(hhh](j)}(hSint amdgpu_dm_atomic_check (struct drm_device *dev, struct drm_atomic_state *state)h]j)}(hRint amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)h](jZ$)}(hinth]hint}(hjBhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjBhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM.ubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBhhhjBhM.ubj)}(hamdgpu_dm_atomic_checkh]j)}(hamdgpu_dm_atomic_checkh]hamdgpu_dm_atomic_check}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]jjuh1jhjBhhhjBhM.ubj$)}(h8(struct drm_device *dev, struct drm_atomic_state *state)h](j$)}(hstruct drm_device *devh](j)}(hjh]hstruct}(hj ChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubh)}(hhh]j)}(h drm_deviceh]h drm_device}(hj*ChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'Cubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj,CmodnameN classnameNjwjz)}j}]j$)}j$jBsbc.amdgpu_dm_atomic_checkasbuh1hhjCubj)}(h h]h }(hjJChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubj$)}(hj$h]h*}(hjXChhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjCubj)}(hdevh]hdev}(hjeChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCubj$)}(hstruct drm_atomic_state *stateh](j)}(hjh]hstruct}(hj~ChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzCubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzCubh)}(hhh]j)}(hdrm_atomic_stateh]hdrm_atomic_state}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjCmodnameN classnameNjwjz)}j}]jFCc.amdgpu_dm_atomic_checkasbuh1hhjzCubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzCubj$)}(hj$h]h*}(hjChhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjzCubj)}(hstateh]hstate}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzCubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCubeh}(h]h ]h"]h$]h&]jjuh1j$hjBhhhjBhM.ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjBhhhjBhM.ubah}(h]jBah ](jjeh"]h$]h&]jj)jhuh1jhjBhM.hjBhhubj)}(hhh]h)}(h*Atomic check implementation for AMDgpu DM.h]h*Atomic check implementation for AMDgpu DM.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjChhubah}(h]h ]h"]h$]h&]uh1jhjBhhhjBhM.ubeh}(h]h ](j_functioneh"]h$]h&]jj_jjDjjDjjjuh1jhhhj AhNhNubj )}(hX**Parameters** ``struct drm_device *dev`` The DRM device ``struct drm_atomic_state *state`` The atomic state to commit **Description** Validate that the given atomic state is programmable by DC into hardware. This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes. When validating the DC state, it's important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events. Note that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item. **Return** -Error code if validation failed.h](h)}(h**Parameters**h]j)}(hj!Dh]h Parameters}(hj#DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjDubjl)}(hhh](jq)}(h*``struct drm_device *dev`` The DRM device h](jw)}(h``struct drm_device *dev``h]jS)}(hj@Dh]hstruct drm_device *dev}(hjBDhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj>Dubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hj:Dubj)}(hhh]h)}(hThe DRM deviceh]hThe DRM device}(hjYDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUDhM-hjVDubah}(h]h ]h"]h$]h&]uh1jhj:Dubeh}(h]h ]h"]h$]h&]uh1jphjUDhM-hj7Dubjq)}(h>``struct drm_atomic_state *state`` The atomic state to commit h](jw)}(h"``struct drm_atomic_state *state``h]jS)}(hjyDh]hstruct drm_atomic_state *state}(hj{DhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjwDubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjsDubj)}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhM-hjDubah}(h]h ]h"]h$]h&]uh1jhjsDubeh}(h]h ]h"]h$]h&]uh1jphjDhM-hj7Dubeh}(h]h ]h"]h$]h&]uh1jkhjDubh)}(h**Description**h]j)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjDubh)}(hXeValidate that the given atomic state is programmable by DC into hardware. This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.h](hgValidate that the given atomic state is programmable by DC into hardware. This involves constructing a }(hjDhhhNhNubh)}(h$:c:type:`struct dc_state `h]jS)}(hjDh]hstruct dc_state}(hjDhhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjDubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqdc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjDubh reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It’s important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjDhM-hjDubh)}(hXNWhen validating the DC state, it's important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.h]hXPWhen validating the DC state, it’s important that the right locks are acquired. For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM-hjDubh)}(hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.h]hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.}(hj EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM.hjDubh)}(h **Return**h]j)}(hjEh]hReturn}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM.hjDubh)}(h!-Error code if validation failed.h]h!-Error code if validation failed.}(hj2EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM.hjDubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj AhhhNhNubeh}(h]jOah ]h"]atomic implementationah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hColor Management Propertiesh]hColor Management Properties}(hjREhhhNhNubah}(h]h ]h"]h$]h&]hjkuh1hhjOEhhhhhK-ubh)}(hYThe DC interface to HW gives us the following color management blocks per pipe (surface):h]hYThe DC interface to HW gives us the following color management blocks per pipe (surface):}(hj`EhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK!hjOEhhubh)}(hhh](h)}(hInput gamma LUT (de-normalized)h]h)}(hjtEh]hInput gamma LUT (de-normalized)}(hjvEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK$hjrEubah}(h]h ]h"]h$]h&]uh1hhjoEubh)}(hInput CSC (normalized)h]h)}(hjEh]hInput CSC (normalized)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK%hjEubah}(h]h ]h"]h$]h&]uh1hhjoEubh)}(h Surface degamma LUT (normalized)h]h)}(hjEh]h Surface degamma LUT (normalized)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK&hjEubah}(h]h ]h"]h$]h&]uh1hhjoEubh)}(hSurface CSC (normalized)h]h)}(hjEh]hSurface CSC (normalized)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK'hjEubah}(h]h ]h"]h$]h&]uh1hhjoEubh)}(h Surface regamma LUT (normalized)h]h)}(hjEh]h Surface regamma LUT (normalized)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK(hjEubah}(h]h ]h"]h$]h&]uh1hhjoEubh)}(hOutput CSC (normalized) h]h)}(hOutput CSC (normalized)h]hOutput CSC (normalized)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK)hjEubah}(h]h ]h"]h$]h&]uh1hhjoEubeh}(h]h ]h"]h$]h&]j&j&uh1hhjEhK$hjOEhhubh)}(hBut these aren't a direct mapping to DRM color properties. The current DRM interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware is essentially giving:h]hBut these aren’t a direct mapping to DRM color properties. The current DRM interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware is essentially giving:}(hj FhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK+hjOEhhubh)}(hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTMh]hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK/hjOEhhubh)}(hXThe input gamma LUT block isn't really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.h]hXThe input gamma LUT block isn’t really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.}(hj'FhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK1hjOEhhubh)}(hX!The pipe blending also happens after these blocks so we don't actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.h]hX#The pipe blending also happens after these blocks so we don’t actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.}(hj6FhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK8hjOEhhubh)}(hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.h]hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.}(hjEFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK=hjOEhhubh)}(hIThis means that the following configuration is assumed to be the default:h]hIThis means that the following configuration is assumed to be the default:}(hjTFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKAhjOEhhubh)}(huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypassh]huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass}(hjcFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKDhjOEhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_dm_init_color_mod (C function)c.amdgpu_dm_init_color_modhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(h$void amdgpu_dm_init_color_mod (void)h]j)}(h#void amdgpu_dm_init_color_mod(void)h](jZ$)}(hvoidh]hvoid}(hjFhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjFhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKSubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFhhhjFhKSubj)}(hamdgpu_dm_init_color_modh]j)}(hamdgpu_dm_init_color_modh]hamdgpu_dm_init_color_mod}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](jjeh"]h$]h&]jjuh1jhjFhhhjFhKSubj$)}(h(void)h]j$)}(hvoidh]jZ$)}(hvoidh]hvoid}(hjFhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjFubah}(h]h ]h"]h$]h&]noemphjjuh1j$hjFubah}(h]h ]h"]h$]h&]jjuh1j$hjFhhhjFhKSubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjFhhhjFhKSubah}(h]j~Fah ](jjeh"]h$]h&]jj)jhuh1jhjFhKShjFhhubj)}(hhh]h)}(hInitialize the color module.h]hInitialize the color module.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKNhjFhhubah}(h]h ]h"]h$]h&]uh1jhjFhhhjFhKSubeh}(h]h ](j_functioneh"]h$]h&]jj_jj Gjj Gjjjuh1jhhhjOEhNhNubj )}(h**Parameters** ``void`` no arguments **Description** We're not using the full color module, only certain components. Only call setup functions for components that we need.h](h)}(h**Parameters**h]j)}(hjGh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKRhjGubjl)}(hhh]jq)}(h``void`` no arguments h](jw)}(h``void``h]jS)}(hj3Gh]hvoid}(hj5GhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj1Gubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKUhj-Gubj)}(hhh]h)}(h no argumentsh]h no arguments}(hjLGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHGhKUhjIGubah}(h]h ]h"]h$]h&]uh1jhj-Gubeh}(h]h ]h"]h$]h&]uh1jphjHGhKUhj*Gubah}(h]h ]h"]h$]h&]uh1jkhjGubh)}(h**Description**h]j)}(hjnGh]h Description}(hjpGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlGubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKWhjGubh)}(hvWe're not using the full color module, only certain components. Only call setup functions for components that we need.h]hxWe’re not using the full color module, only certain components. Only call setup functions for components that we need.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKOhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__extract_blob_lut (C function)c.__extract_blob_luthNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hfconst struct drm_color_lut * __extract_blob_lut (const struct drm_property_blob *blob, uint32_t *size)h]j)}(hdconst struct drm_color_lut *__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)h](j)}(hconsth]hconst}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMQubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhjGhMQubj)}(hjh]hstruct}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhjGhMQubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhjGhMQubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjGmodnameN classnameNjwjz)}j}]j$)}j$__extract_blob_lutsbc.__extract_blob_lutasbuh1hhjGhhhjGhMQubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhjGhMQubj$)}(hj$h]h*}(hjHhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjGhhhjGhMQubj)}(h__extract_blob_luth]j)}(hj Hh]h__extract_blob_lut}(hj.HhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*Hubah}(h]h ](jjeh"]h$]h&]jjuh1jhjGhhhjGhMQubj$)}(h6(const struct drm_property_blob *blob, uint32_t *size)h](j$)}(h$const struct drm_property_blob *blobh](j)}(hjGh]hconst}(hjIHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubj)}(h h]h }(hjVHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubj)}(hjh]hstruct}(hjdHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubj)}(h h]h }(hjqHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubh)}(hhh]j)}(hdrm_property_blobh]hdrm_property_blob}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjHmodnameN classnameNjwjz)}j}]j Hc.__extract_blob_lutasbuh1hhjEHubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubj$)}(hj$h]h*}(hjHhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjEHubj)}(hblobh]hblob}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEHubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjAHubj$)}(huint32_t *sizeh](h)}(hhh]j)}(huint32_th]huint32_t}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjHmodnameN classnameNjwjz)}j}]j Hc.__extract_blob_lutasbuh1hhjHubj)}(h h]h }(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubj$)}(hj$h]h*}(hjIhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjHubj)}(hsizeh]hsize}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjAHubeh}(h]h ]h"]h$]h&]jjuh1j$hjGhhhjGhMQubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjGhhhjGhMQubah}(h]jGah ](jjeh"]h$]h&]jj)jhuh1jhjGhMQhjGhhubj)}(hhh]h)}(h.Extracts the DRM lut and lut size from a blob.h]h.Extracts the DRM lut and lut size from a blob.}(hj:IhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMJhj7Ihhubah}(h]h ]h"]h$]h&]uh1jhjGhhhjGhMQubeh}(h]h ](j_functioneh"]h$]h&]jj_jjRIjjRIjjjuh1jhhhjOEhNhNubj )}(h**Parameters** ``const struct drm_property_blob *blob`` DRM color mgmt property blob ``uint32_t *size`` lut size **Return** DRM LUT or NULLh](h)}(h**Parameters**h]j)}(hj\Ih]h Parameters}(hj^IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZIubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMNhjVIubjl)}(hhh](jq)}(hF``const struct drm_property_blob *blob`` DRM color mgmt property blob h](jw)}(h(``const struct drm_property_blob *blob``h]jS)}(hj{Ih]h$const struct drm_property_blob *blob}(hj}IhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjyIubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMKhjuIubj)}(hhh]h)}(hDRM color mgmt property blobh]hDRM color mgmt property blob}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMKhjIubah}(h]h ]h"]h$]h&]uh1jhjuIubeh}(h]h ]h"]h$]h&]uh1jphjIhMKhjrIubjq)}(h``uint32_t *size`` lut size h](jw)}(h``uint32_t *size``h]jS)}(hjIh]huint32_t *size}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjIubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMLhjIubj)}(hhh]h)}(hlut sizeh]hlut size}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMLhjIubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jphjIhMLhjrIubeh}(h]h ]h"]h$]h&]uh1jkhjVIubh)}(h **Return**h]j)}(hjIh]hReturn}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMNhjVIubh)}(hDRM LUT or NULLh]hDRM LUT or NULL}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMNhjVIubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__is_lut_linear (C function)c.__is_lut_linearhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hEbool __is_lut_linear (const struct drm_color_lut *lut, uint32_t size)h]j)}(hDbool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)h](jZ$)}(hboolh]hbool}(hj4JhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj0Jhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMeubj)}(h h]h }(hjCJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0JhhhjBJhMeubj)}(h__is_lut_linearh]j)}(h__is_lut_linearh]h__is_lut_linear}(hjUJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQJubah}(h]h ](jjeh"]h$]h&]jjuh1jhj0JhhhjBJhMeubj$)}(h0(const struct drm_color_lut *lut, uint32_t size)h](j$)}(hconst struct drm_color_lut *luth](j)}(hjGh]hconst}(hjqJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubj)}(h h]h }(hj~JhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubj)}(hjh]hstruct}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjJmodnameN classnameNjwjz)}j}]j$)}j$jWJsbc.__is_lut_linearasbuh1hhjmJubj)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubj$)}(hj$h]h*}(hjJhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjmJubj)}(hluth]hlut}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmJubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjiJubj$)}(h uint32_t sizeh](h)}(hhh]j)}(huint32_th]huint32_t}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjKmodnameN classnameNjwjz)}j}]jJc.__is_lut_linearasbuh1hhjJubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubj)}(hsizeh]hsize}(hj-KhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjiJubeh}(h]h ]h"]h$]h&]jjuh1j$hj0JhhhjBJhMeubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj,JhhhjBJhMeubah}(h]j'Jah ](jjeh"]h$]h&]jj)jhuh1jhjBJhMehj)Jhhubj)}(hhh]h)}(h4check if the given lut is a linear mapping of valuesh]h4check if the given lut is a linear mapping of values}(hjWKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMYhjTKhhubah}(h]h ]h"]h$]h&]uh1jhj)JhhhjBJhMeubeh}(h]h ](j_functioneh"]h$]h&]jj_jjoKjjoKjjjuh1jhhhjOEhNhNubj )}(hXx**Parameters** ``const struct drm_color_lut *lut`` given lut to check values ``uint32_t size`` lut size **Description** It is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES) **Return** True if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h](h)}(h**Parameters**h]j)}(hjyKh]h Parameters}(hj{KhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwKubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM]hjsKubjl)}(hhh](jq)}(h>``const struct drm_color_lut *lut`` given lut to check values h](jw)}(h#``const struct drm_color_lut *lut``h]jS)}(hjKh]hconst struct drm_color_lut *lut}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjKubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMZhjKubj)}(hhh]h)}(hgiven lut to check valuesh]hgiven lut to check values}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMZhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jphjKhMZhjKubjq)}(h``uint32_t size`` lut size h](jw)}(h``uint32_t size``h]jS)}(hjKh]h uint32_t size}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjKubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM[hjKubj)}(hhh]h)}(hlut sizeh]hlut size}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhM[hjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jphjKhM[hjKubeh}(h]h ]h"]h$]h&]uh1jkhjsKubh)}(h**Description**h]j)}(hj Lh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Lubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM]hjsKubh)}(hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)h]hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)}(hj"LhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM]hjsKubh)}(h **Return**h]j)}(hj3Lh]hReturn}(hj5LhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1Lubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMahjsKubh)}(hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h]hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.}(hjILhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMahjsKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"__drm_lut_to_dc_gamma (C function)c.__drm_lut_to_dc_gammahNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hdvoid __drm_lut_to_dc_gamma (const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h]j)}(hcvoid __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h](jZ$)}(hvoidh]hvoid}(hjxLhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjtLhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtLhhhjLhMubj)}(h__drm_lut_to_dc_gammah]j)}(h__drm_lut_to_dc_gammah]h__drm_lut_to_dc_gamma}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ](jjeh"]h$]h&]jjuh1jhjtLhhhjLhMubj$)}(hI(const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h](j$)}(hconst struct drm_color_lut *luth](j)}(hjGh]hconst}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hjh]hstruct}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjLmodnameN classnameNjwjz)}j}]j$)}j$jLsbc.__drm_lut_to_dc_gammaasbuh1hhjLubj)}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj$)}(hj$h]h*}(hjMhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjLubj)}(hluth]hlut}(hj)MhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjLubj$)}(hstruct dc_gamma *gammah](j)}(hjh]hstruct}(hjBMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>Mubj)}(h h]h }(hjOMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>Mubh)}(hhh]j)}(hdc_gammah]hdc_gamma}(hj`MhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]Mubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjbMmodnameN classnameNjwjz)}j}]j Mc.__drm_lut_to_dc_gammaasbuh1hhj>Mubj)}(h h]h }(hj~MhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>Mubj$)}(hj$h]h*}(hjMhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj>Mubj)}(hgammah]hgamma}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>Mubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjLubj$)}(hbool is_legacyh](jZ$)}(hj6Jh]hbool}(hjMhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjMubj)}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj)}(h is_legacyh]h is_legacy}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjLubeh}(h]h ]h"]h$]h&]jjuh1j$hjtLhhhjLhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjpLhhhjLhMubah}(h]jkLah ](jjeh"]h$]h&]jj)jhuh1jhjLhMhjmLhhubj)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM{hjMhhubah}(h]h ]h"]h$]h&]uh1jhjmLhhhjLhMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjNjjNjjjuh1jhhhjOEhNhNubj )}(hX**Parameters** ``const struct drm_color_lut *lut`` DRM lookup table for color conversion ``struct dc_gamma *gamma`` DC gamma to set entries ``bool is_legacy`` legacy or atomic gamma **Description** The conversion depends on the size of the lut - whether or not it's legacy.h](h)}(h**Parameters**h]j)}(hjNh]h Parameters}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjNubjl)}(hhh](jq)}(hJ``const struct drm_color_lut *lut`` DRM lookup table for color conversion h](jw)}(h#``const struct drm_color_lut *lut``h]jS)}(hj8Nh]hconst struct drm_color_lut *lut}(hj:NhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj6Nubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM|hj2Nubj)}(hhh]h)}(h%DRM lookup table for color conversionh]h%DRM lookup table for color conversion}(hjQNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMNhM|hjNNubah}(h]h ]h"]h$]h&]uh1jhj2Nubeh}(h]h ]h"]h$]h&]uh1jphjMNhM|hj/Nubjq)}(h3``struct dc_gamma *gamma`` DC gamma to set entries h](jw)}(h``struct dc_gamma *gamma``h]jS)}(hjqNh]hstruct dc_gamma *gamma}(hjsNhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjoNubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM}hjkNubj)}(hhh]h)}(hDC gamma to set entriesh]hDC gamma to set entries}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhM}hjNubah}(h]h ]h"]h$]h&]uh1jhjkNubeh}(h]h ]h"]h$]h&]uh1jphjNhM}hj/Nubjq)}(h*``bool is_legacy`` legacy or atomic gamma h](jw)}(h``bool is_legacy``h]jS)}(hjNh]hbool is_legacy}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjNubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM~hjNubj)}(hhh]h)}(hlegacy or atomic gammah]hlegacy or atomic gamma}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhM~hjNubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jphjNhM~hj/Nubeh}(h]h ]h"]h$]h&]uh1jkhjNubh)}(h**Description**h]j)}(hjNh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjNubh)}(hKThe conversion depends on the size of the lut - whether or not it's legacy.h]hMThe conversion depends on the size of the lut - whether or not it’s legacy.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjNubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#__drm_ctm_to_dc_matrix (C function)c.__drm_ctm_to_dc_matrixhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hXvoid __drm_ctm_to_dc_matrix (const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h]j)}(hWvoid __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](jZ$)}(hvoidh]hvoid}(hj*OhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj&Ohhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hj9OhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&Ohhhj8OhMubj)}(h__drm_ctm_to_dc_matrixh]j)}(h__drm_ctm_to_dc_matrixh]h__drm_ctm_to_dc_matrix}(hjKOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGOubah}(h]h ](jjeh"]h$]h&]jjuh1jhj&Ohhhj8OhMubj$)}(h<(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](j$)}(hconst struct drm_color_ctm *ctmh](j)}(hjGh]hconst}(hjgOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubj)}(h h]h }(hjtOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubj)}(hjh]hstruct}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubh)}(hhh]j)}(h drm_color_ctmh]h drm_color_ctm}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjOmodnameN classnameNjwjz)}j}]j$)}j$jMOsbc.__drm_ctm_to_dc_matrixasbuh1hhjcOubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubj$)}(hj$h]h*}(hjOhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjcOubj)}(hctmh]hctm}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcOubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj_Oubj$)}(hstruct fixed31_32 *matrixh](j)}(hjh]hstruct}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubj)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubh)}(hhh]j)}(h fixed31_32h]h fixed31_32}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjPmodnameN classnameNjwjz)}j}]jOc.__drm_ctm_to_dc_matrixasbuh1hhjOubj)}(h h]h }(hj0PhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubj$)}(hj$h]h*}(hj>PhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjOubj)}(hmatrixh]hmatrix}(hjKPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj_Oubeh}(h]h ]h"]h$]h&]jjuh1j$hj&Ohhhj8OhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj"Ohhhj8OhMubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1jhj8OhMhjOhhubj)}(hhh]h)}(h+converts a DRM CTM to a DC CSC float matrixh]h+converts a DRM CTM to a DC CSC float matrix}(hjuPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjrPhhubah}(h]h ]h"]h$]h&]uh1jhjOhhhj8OhMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjPjjPjjjuh1jhhhjOEhNhNubj )}(h**Parameters** ``const struct drm_color_ctm *ctm`` DRM color transformation matrix ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hjPh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjPubjl)}(hhh](jq)}(hD``const struct drm_color_ctm *ctm`` DRM color transformation matrix h](jw)}(h#``const struct drm_color_ctm *ctm``h]jS)}(hjPh]hconst struct drm_color_ctm *ctm}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjPubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjPubj)}(hhh]h)}(hDRM color transformation matrixh]hDRM color transformation matrix}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jphjPhMhjPubjq)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](jw)}(h``struct fixed31_32 *matrix``h]jS)}(hjPh]hstruct fixed31_32 *matrix}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjPubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjPubj)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhMhjQubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jphjQhMhjPubeh}(h]h ]h"]h$]h&]uh1jkhjPubh)}(h**Description**h]j)}(hj*Qh]h Description}(hj,QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(Qubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjPubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hj@QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__drm_ctm_3x4_to_dc_matrix (C function)c.__drm_ctm_3x4_to_dc_matrixhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(h`void __drm_ctm_3x4_to_dc_matrix (const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h]j)}(h_void __drm_ctm_3x4_to_dc_matrix(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](jZ$)}(hvoidh]hvoid}(hjoQhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjkQhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hj~QhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkQhhhj}QhMubj)}(h__drm_ctm_3x4_to_dc_matrixh]j)}(h__drm_ctm_3x4_to_dc_matrixh]h__drm_ctm_3x4_to_dc_matrix}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](jjeh"]h$]h&]jjuh1jhjkQhhhj}QhMubj$)}(h@(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](j$)}(h#const struct drm_color_ctm_3x4 *ctmh](j)}(hjGh]hconst}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubh)}(hhh]j)}(hdrm_color_ctm_3x4h]hdrm_color_ctm_3x4}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjQmodnameN classnameNjwjz)}j}]j$)}j$jQsbc.__drm_ctm_3x4_to_dc_matrixasbuh1hhjQubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubj$)}(hj$h]h*}(hjRhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjQubj)}(hctmh]hctm}(hj RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjQubj$)}(hstruct fixed31_32 *matrixh](j)}(hjh]hstruct}(hj9RhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Rubj)}(h h]h }(hjFRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Rubh)}(hhh]j)}(h fixed31_32h]h fixed31_32}(hjWRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTRubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjYRmodnameN classnameNjwjz)}j}]jRc.__drm_ctm_3x4_to_dc_matrixasbuh1hhj5Rubj)}(h h]h }(hjuRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Rubj$)}(hj$h]h*}(hjRhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj5Rubj)}(hmatrixh]hmatrix}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5Rubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjQubeh}(h]h ]h"]h$]h&]jjuh1j$hjkQhhhj}QhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjgQhhhj}QhMubah}(h]jbQah ](jjeh"]h$]h&]jj)jhuh1jhj}QhMhjdQhhubj)}(hhh]h)}(h/converts a DRM CTM 3x4 to a DC CSC float matrixh]h/converts a DRM CTM 3x4 to a DC CSC float matrix}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRhhubah}(h]h ]h"]h$]h&]uh1jhjdQhhhj}QhMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjRjjRjjjuh1jhhhjOEhNhNubj )}(h**Parameters** ``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hjRh]h Parameters}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRubjl)}(hhh](jq)}(h\``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions h](jw)}(h'``const struct drm_color_ctm_3x4 *ctm``h]jS)}(hjRh]h#const struct drm_color_ctm_3x4 *ctm}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjRubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRubj)}(hhh]h)}(h3DRM color transformation matrix with 3x4 dimensionsh]h3DRM color transformation matrix with 3x4 dimensions}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMhjSubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jphjShMhjRubjq)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](jw)}(h``struct fixed31_32 *matrix``h]jS)}(hj4Sh]hstruct fixed31_32 *matrix}(hj6ShhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj2Subah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj.Subj)}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjMShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIShMhjJSubah}(h]h ]h"]h$]h&]uh1jhj.Subeh}(h]h ]h"]h$]h&]uh1jphjIShMhjRubeh}(h]h ]h"]h$]h&]uh1jkhjRubh)}(h**Description**h]j)}(hjoSh]h Description}(hjqShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmSubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_legacy_tf (C function)c.__set_legacy_tfhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(huint __set_legacy_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_legacy_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](jZ$)}(hinth]hint}(hjShhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjShhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhhjShMubj)}(h__set_legacy_tfh]j)}(h__set_legacy_tfh]h__set_legacy_tf}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](jjeh"]h$]h&]jjuh1jhjShhhjShMubj$)}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j$)}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubj)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubh)}(hhh]j)}(hdc_transfer_funch]hdc_transfer_func}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj Tubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjTmodnameN classnameNjwjz)}j}]j$)}j$jSsbc.__set_legacy_tfasbuh1hhjSubj)}(h h]h }(hj/ThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubj$)}(hj$h]h*}(hj=ThhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjSubj)}(hfunch]hfunc}(hjJThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjSubj$)}(hconst struct drm_color_lut *luth](j)}(hjGh]hconst}(hjcThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubj)}(h h]h }(hjpThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubj)}(hjh]hstruct}(hj~ThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjTmodnameN classnameNjwjz)}j}]j+Tc.__set_legacy_tfasbuh1hhj_Tubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubj$)}(hj$h]h*}(hjThhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj_Tubj)}(hluth]hlut}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_Tubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjSubj$)}(huint32_t lut_sizeh](h)}(hhh]j)}(huint32_th]huint32_t}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjTmodnameN classnameNjwjz)}j}]j+Tc.__set_legacy_tfasbuh1hhjTubj)}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj)}(hlut_sizeh]hlut_size}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjSubj$)}(h bool has_romh](jZ$)}(hj6Jh]hbool}(hj6UhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj2Uubj)}(h h]h }(hjCUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Uubj)}(hhas_romh]hhas_rom}(hjQUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Uubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjSubeh}(h]h ]h"]h$]h&]jjuh1j$hjShhhjShMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjShhhjShMubah}(h]jSah ](jjeh"]h$]h&]jj)jhuh1jhjShMhjShhubj)}(hhh]h)}(h'Calculates the legacy transfer functionh]h'Calculates the legacy transfer function}(hj{UhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjxUhhubah}(h]h ]h"]h$]h&]uh1jhjShhhjShMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjUjjUjjjuh1jhhhjOEhNhNubj )}(hXa**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Description** Only for sRGB input space **Return** 0 in case of success, -ENOMEM if failsh](h)}(h**Parameters**h]j)}(hjUh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubjl)}(hhh](jq)}(h4``struct dc_transfer_func *func`` transfer function h](jw)}(h!``struct dc_transfer_func *func``h]jS)}(hjUh]hstruct dc_transfer_func *func}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjUubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj)}(hhh]h)}(htransfer functionh]htransfer function}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jphjUhMhjUubjq)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](jw)}(h#``const struct drm_color_lut *lut``h]jS)}(hjUh]hconst struct drm_color_lut *lut}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjUubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj VhMhj Vubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jphj VhMhjUubjq)}(h-``uint32_t lut_size`` size of respective lut h](jw)}(h``uint32_t lut_size``h]jS)}(hj.Vh]huint32_t lut_size}(hj0VhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj,Vubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj(Vubj)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjGVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCVhMhjDVubah}(h]h ]h"]h$]h&]uh1jhj(Vubeh}(h]h ]h"]h$]h&]uh1jphjCVhMhjUubjq)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](jw)}(h``bool has_rom``h]jS)}(hjgVh]h bool has_rom}(hjiVhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjeVubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjaVubj)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|VhMhj}Vubah}(h]h ]h"]h$]h&]uh1jhjaVubeh}(h]h ]h"]h$]h&]uh1jphj|VhMhjUubeh}(h]h ]h"]h$]h&]uh1jkhjUubh)}(h**Description**h]j)}(hjVh]h Description}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubh)}(hOnly for sRGB input spaceh]hOnly for sRGB input space}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubh)}(h **Return**h]j)}(hjVh]hReturn}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubh)}(h&0 in case of success, -ENOMEM if failsh]h&0 in case of success, -ENOMEM if fails}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_output_tf (C function)c.__set_output_tfhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(huint __set_output_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_output_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](jZ$)}(hinth]hint}(hjWhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj Whhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM ubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj WhhhjWhM ubj)}(h__set_output_tfh]j)}(h__set_output_tfh]h__set_output_tf}(hj/WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+Wubah}(h]h ](jjeh"]h$]h&]jjuh1jhj WhhhjWhM ubj$)}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j$)}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjKWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGWubj)}(h h]h }(hjXWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGWubh)}(hhh]j)}(hdc_transfer_funch]hdc_transfer_func}(hjiWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfWubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjkWmodnameN classnameNjwjz)}j}]j$)}j$j1Wsbc.__set_output_tfasbuh1hhjGWubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGWubj$)}(hj$h]h*}(hjWhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjGWubj)}(hfunch]hfunc}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGWubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCWubj$)}(hconst struct drm_color_lut *luth](j)}(hjGh]hconst}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(hjh]hstruct}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjWmodnameN classnameNjwjz)}j}]jWc.__set_output_tfasbuh1hhjWubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj$)}(hj$h]h*}(hj"XhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjWubj)}(hluth]hlut}(hj/XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCWubj$)}(huint32_t lut_sizeh](h)}(hhh]j)}(huint32_th]huint32_t}(hjKXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHXubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjMXmodnameN classnameNjwjz)}j}]jWc.__set_output_tfasbuh1hhjDXubj)}(h h]h }(hjiXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDXubj)}(hlut_sizeh]hlut_size}(hjwXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDXubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCWubj$)}(h bool has_romh](jZ$)}(hj6Jh]hbool}(hjXhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjXubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj)}(hhas_romh]hhas_rom}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjCWubeh}(h]h ]h"]h$]h&]jjuh1j$hj WhhhjWhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjWhhhjWhM ubah}(h]jWah ](jjeh"]h$]h&]jj)jhuh1jhjWhM hjWhhubj)}(hhh]h)}(hFcalculates the output transfer function based on expected input space.h]hFcalculates the output transfer function based on expected input space.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjXhhubah}(h]h ]h"]h$]h&]uh1jhjWhhhjWhM ubeh}(h]h ](j_functioneh"]h$]h&]jj_jjXjjXjjjuh1jhhhjOEhNhNubj )}(hX6**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjXh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjXubjl)}(hhh](jq)}(h4``struct dc_transfer_func *func`` transfer function h](jw)}(h!``struct dc_transfer_func *func``h]jS)}(hjYh]hstruct dc_transfer_func *func}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjYubj)}(hhh]h)}(htransfer functionh]htransfer function}(hj/YhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+YhMhj,Yubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jphj+YhMhj Yubjq)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](jw)}(h#``const struct drm_color_lut *lut``h]jS)}(hjOYh]hconst struct drm_color_lut *lut}(hjQYhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjMYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjIYubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjhYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdYhMhjeYubah}(h]h ]h"]h$]h&]uh1jhjIYubeh}(h]h ]h"]h$]h&]uh1jphjdYhMhj Yubjq)}(h-``uint32_t lut_size`` size of respective lut h](jw)}(h``uint32_t lut_size``h]jS)}(hjYh]huint32_t lut_size}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjYubj)}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jphjYhMhj Yubjq)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](jw)}(h``bool has_rom``h]jS)}(hjYh]h bool has_rom}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjYubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjYubj)}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhMhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jphjYhMhj Yubeh}(h]h ]h"]h$]h&]uh1jkhjXubh)}(h **Return**h]j)}(hjYh]hReturn}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjXubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjXubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_input_tf (C function)c.__set_input_tfhNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hint __set_input_tf (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h]j)}(hint __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](jZ$)}(hinth]hint}(hjAZhhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj=Zhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMiubj)}(h h]h }(hjPZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ZhhhjOZhMiubj)}(h__set_input_tfh]j)}(h__set_input_tfh]h__set_input_tf}(hjbZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^Zubah}(h]h ](jjeh"]h$]h&]jjuh1jhj=ZhhhjOZhMiubj$)}(ho(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](j$)}(hstruct dc_color_caps *capsh](j)}(hjh]hstruct}(hj~ZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzZubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzZubh)}(hhh]j)}(h dc_color_capsh]h dc_color_caps}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjZmodnameN classnameNjwjz)}j}]j$)}j$jdZsbc.__set_input_tfasbuh1hhjzZubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzZubj$)}(hj$h]h*}(hjZhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjzZub!j)}(hcapsh]hcaps}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzZubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjvZubj$)}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubh)}(hhh]j)}(hdc_transfer_funch]hdc_transfer_func}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj [ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj[modnameN classnameNjwjz)}j}]jZc.__set_input_tfasbuh1hhjZubj)}(h h]h }(hj,[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj$)}(hj$h]h*}(hj:[hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjZubj)}(hfunch]hfunc}(hjG[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjvZubj$)}(hconst struct drm_color_lut *luth](j)}(hjGh]hconst}(hj`[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubj)}(h h]h }(hjm[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubj)}(hjh]hstruct}(hj{[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubh)}(hhh]j)}(h drm_color_luth]h drm_color_lut}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj[modnameN classnameNjwjz)}j}]jZc.__set_input_tfasbuh1hhj\[ubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubj$)}(hj$h]h*}(hj[hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj\[ubj)}(hluth]hlut}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\[ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjvZubj$)}(huint32_t lut_sizeh](h)}(hhh]j)}(huint32_th]huint32_t}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj[modnameN classnameNjwjz)}j}]jZc.__set_input_tfasbuh1hhj[ubj)}(h h]h }(hj \hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj)}(hlut_sizeh]hlut_size}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjvZubeh}(h]h ]h"]h$]h&]jjuh1j$hj=ZhhhjOZhMiubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9ZhhhjOZhMiubah}(h]j4Zah ](jjeh"]h$]h&]jj)jhuh1jhjOZhMihj6Zhhubj)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjD\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM_hjA\hhubah}(h]h ]h"]h$]h&]uh1jhj6ZhhhjOZhMiubeh}(h]h ](j_functioneh"]h$]h&]jj_jj\\jj\\jjjuh1jhhhjOEhNhNubj )}(hX4**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjf\h]h Parameters}(hjh\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd\ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMchj`\ubjl)}(hhh](jq)}(h5``struct dc_color_caps *caps`` dc color capabilities h](jw)}(h``struct dc_color_caps *caps``h]jS)}(hj\h]hstruct dc_color_caps *caps}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj\ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMahj\ubj)}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMahj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jphj\hMahj|\ubjq)}(h4``struct dc_transfer_func *func`` transfer function h](jw)}(h!``struct dc_transfer_func *func``h]jS)}(hj\h]hstruct dc_transfer_func *func}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj\ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMbhj\ubj)}(hhh]h)}(htransfer functionh]htransfer function}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hMbhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jphj\hMbhj|\ubjq)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](jw)}(h#``const struct drm_color_lut *lut``h]jS)}(hj\h]hconst struct drm_color_lut *lut}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj\ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMchj\ubj)}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ]hMchj ]ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jphj ]hMchj|\ubjq)}(h.``uint32_t lut_size`` size of respective lut. h](jw)}(h``uint32_t lut_size``h]jS)}(hj0]h]huint32_t lut_size}(hj2]hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj.]ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMdhj*]ubj)}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hjI]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE]hMdhjF]ubah}(h]h ]h"]h$]h&]uh1jhj*]ubeh}(h]h ]h"]h$]h&]uh1jphjE]hMdhj|\ubeh}(h]h ]h"]h$]h&]uh1jkhj`\ubh)}(h **Return**h]j)}(hjk]h]hReturn}(hjm]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji]ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMfhj`\ubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMfhj`\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(amdgpu_dm_verify_lut3d_size (C function)c.amdgpu_dm_verify_lut3d_sizehNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(haint amdgpu_dm_verify_lut3d_size (struct amdgpu_device *adev, struct drm_plane_state *plane_state)h]j)}(h`int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](jZ$)}(hinth]hint}(hj]hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj]hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM2ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhj]hM2ubj)}(hamdgpu_dm_verify_lut3d_sizeh]j)}(hamdgpu_dm_verify_lut3d_sizeh]hamdgpu_dm_verify_lut3d_size}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj]hhhj]hM2ubj$)}(hA(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](j$)}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubh)}(hhh]j)}(h amdgpu_deviceh]h amdgpu_device}(hj ^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj ^modnameN classnameNjwjz)}j}]j$)}j$j]sbc.amdgpu_dm_verify_lut3d_sizeasbuh1hhj]ubj)}(h h]h }(hj+^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj$)}(hj$h]h*}(hj9^hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj]ubj)}(hadevh]hadev}(hjF^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj]ubj$)}(h#struct drm_plane_state *plane_stateh](j)}(hjh]hstruct}(hj_^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[^ubj)}(h h]h }(hjl^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[^ubh)}(hhh]j)}(hdrm_plane_stateh]hdrm_plane_state}(hj}^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjz^ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetj^modnameN classnameNjwjz)}j}]j'^c.amdgpu_dm_verify_lut3d_sizeasbuh1hhj[^ubj)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[^ubj$)}(hj$h]h*}(hj^hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj[^ubj)}(h plane_stateh]h plane_state}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[^ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj]ubeh}(h]h ]h"]h$]h&]jjuh1j$hj]hhhj]hM2ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj]hhhj]hM2ubah}(h]j]ah ](jjeh"]h$]h&]jj)jhuh1jhj]hM2hj]hhubj)}(hhh]h)}(hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported sizeh]hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported size}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM'hj^hhubah}(h]h ]h"]h$]h&]uh1jhj]hhhj]hM2ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj^jj^jjjuh1jhhhjOEhNhNubj )}(hXX**Parameters** ``struct amdgpu_device *adev`` amdgpu device ``struct drm_plane_state *plane_state`` the DRM plane state **Description** Verifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size. **Return** 0 on success. -EINVAL if lut size are invalid.h](h)}(h**Parameters**h]j)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM+hj^ubjl)}(hhh](jq)}(h-``struct amdgpu_device *adev`` amdgpu device h](jw)}(h``struct amdgpu_device *adev``h]jS)}(hj!_h]hstruct amdgpu_device *adev}(hj#_hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj_ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM)hj_ubj)}(hhh]h)}(h amdgpu deviceh]h amdgpu device}(hj:_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6_hM)hj7_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jphj6_hM)hj_ubjq)}(h<``struct drm_plane_state *plane_state`` the DRM plane state h](jw)}(h'``struct drm_plane_state *plane_state``h]jS)}(hjZ_h]h#struct drm_plane_state *plane_state}(hj\_hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjX_ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM*hjT_ubj)}(hhh]h)}(hthe DRM plane stateh]hthe DRM plane state}(hjs_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo_hM*hjp_ubah}(h]h ]h"]h$]h&]uh1jhjT_ubeh}(h]h ]h"]h$]h&]uh1jphjo_hM*hj_ubeh}(h]h ]h"]h$]h&]uh1jkhj^ubh)}(h**Description**h]j)}(hj_h]h Description}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM,hj^ubh)}(hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.h]hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM,hj^ubh)}(h **Return**h]j)}(hj_h]hReturn}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM/hj^ubh)}(h.0 on success. -EINVAL if lut size are invalid.h]h.0 on success. -EINVAL if lut size are invalid.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM/hj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_verify_lut_sizes (C function)c.amdgpu_dm_verify_lut_sizeshNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hHint amdgpu_dm_verify_lut_sizes (const struct drm_crtc_state *crtc_state)h]j)}(hGint amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)h](jZ$)}(hinth]hint}(hj`hhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hj_hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM]ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhj`hM]ubj)}(hamdgpu_dm_verify_lut_sizesh]j)}(hamdgpu_dm_verify_lut_sizesh]hamdgpu_dm_verify_lut_sizes}(hj"`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj_hhhj`hM]ubj$)}(h)(const struct drm_crtc_state *crtc_state)h]j$)}(h'const struct drm_crtc_state *crtc_stateh](j)}(hjGh]hconst}(hj>`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubj)}(h h]h }(hjK`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubj)}(hjh]hstruct}(hjY`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubj)}(h h]h }(hjf`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubh)}(hhh]j)}(hdrm_crtc_stateh]hdrm_crtc_state}(hjw`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt`ubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjy`modnameN classnameNjwjz)}j}]j$)}j$j$`sbc.amdgpu_dm_verify_lut_sizesasbuh1hhj:`ubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubj$)}(hj$h]h*}(hj`hhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj:`ubj)}(h crtc_stateh]h crtc_state}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:`ubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj6`ubah}(h]h ]h"]h$]h&]jjuh1j$hj_hhhj`hM]ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj_hhhj`hM]ubah}(h]j_ah ](jjeh"]h$]h&]jj)jhuh1jhj`hM]hj_hhubj)}(hhh]h)}(h1verifies if DRM luts match the hw supported sizesh]h1verifies if DRM luts match the hw supported sizes}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThj`hhubah}(h]h ]h"]h$]h&]uh1jhj_hhhj`hM]ubeh}(h]h ](j_functioneh"]h$]h&]jj_jj`jj`jjjuh1jhhhjOEhNhNubj )}(hX **Parameters** ``const struct drm_crtc_state *crtc_state`` the DRM CRTC state **Description** Verifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size. **Return** 0 on success. -EINVAL if any lut sizes are invalid.h](h)}(h**Parameters**h]j)}(hj`h]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMXhj`ubjl)}(hhh]jq)}(h?``const struct drm_crtc_state *crtc_state`` the DRM CRTC state h](jw)}(h+``const struct drm_crtc_state *crtc_state``h]jS)}(hjah]h'const struct drm_crtc_state *crtc_state}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjaubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMUhjaubj)}(hhh]h)}(hthe DRM CRTC stateh]hthe DRM CRTC state}(hj6ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2ahMUhj3aubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jphj2ahMUhjaubah}(h]h ]h"]h$]h&]uh1jkhj`ubh)}(h**Description**h]j)}(hjXah]h Description}(hjZahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVaubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMWhj`ubh)}(hgVerifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size.h](h9Verifies that the Degamma and Gamma LUTs attached to the }(hjnahhhNhNubh)}(h:c:type:`crtc_state`h]jS)}(hjxah]h crtc_state}(hjzahhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjvaubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq crtc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMWhjnaubh are of the expected size.}(hjnahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjahMWhj`ubh)}(h **Return**h]j)}(hjah]hReturn}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMZhj`ubh)}(h30 on success. -EINVAL if any lut sizes are invalid.h]h30 on success. -EINVAL if any lut sizes are invalid.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMZhj`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-amdgpu_dm_update_crtc_color_mgmt (C function)"c.amdgpu_dm_update_crtc_color_mgmthNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hAint amdgpu_dm_update_crtc_color_mgmt (struct dm_crtc_state *crtc)h]j)}(h@int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)h](jZ$)}(hinth]hint}(hjahhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjahhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjahhhjahMubj)}(h amdgpu_dm_update_crtc_color_mgmth]j)}(h amdgpu_dm_update_crtc_color_mgmth]h amdgpu_dm_update_crtc_color_mgmt}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ](jjeh"]h$]h&]jjuh1jhjahhhjahMubj$)}(h(struct dm_crtc_state *crtc)h]j$)}(hstruct dm_crtc_state *crtch](j)}(hjh]hstruct}(hj$bhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj bubj)}(h h]h }(hj1bhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj bubh)}(hhh]j)}(h dm_crtc_stateh]h dm_crtc_state}(hjBbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?bubah}(h]h ]h"]h$]h&] refdomainj_reftypej$ reftargetjDbmodnameN classnameNjwjz)}j}]j$)}j$j bsb"c.amdgpu_dm_update_crtc_color_mgmtasbuh1hhj bubj)}(h h]h }(hjbbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj bubj$)}(hj$h]h*}(hjpbhhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hj bubj)}(hcrtch]hcrtc}(hj}bhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hjbubah}(h]h ]h"]h$]h&]jjuh1j$hjahhhjahMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjahhhjahMubah}(h]jaah ](jjeh"]h$]h&]jj)jhuh1jhjahMhjahhubj)}(hhh]h)}(h'Maps DRM color management to DC stream.h]h'Maps DRM color management to DC stream.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMxhjbhhubah}(h]h ]h"]h$]h&]uh1jhjahhhjahMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjbjjbjjjuh1jhhhjOEhNhNubj )}(hXO**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state **Description** With no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM. - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. - The CRTC CTM will be placed in the gamut remap block if it is non-linear. The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM. For supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together. **Return** 0 on success. Error code if setup fails.h](h)}(h**Parameters**h]j)}(hjbh]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM|hjbubjl)}(hhh]jq)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](jw)}(h``struct dm_crtc_state *crtc``h]jS)}(hjbh]hstruct dm_crtc_state *crtc}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjbubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMyhjbubj)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhMyhjbubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jphjbhMyhjbubah}(h]h ]h"]h$]h&]uh1jkhjbubh)}(h**Description**h]j)}(hj#ch]h Description}(hj%chhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!cubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM{hjbubh)}(hWith no plane level color management properties we're free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.h]hWith no plane level color management properties we’re free to use any of the HW blocks as long as the CRTC CTM always comes before the CRTC RGM and after the CRTC DGM.}(hj9chhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM{hjbubh)}(hhh](h)}(hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.h]h)}(hjMch]hKThe CRTC RGM block will be placed in the RGM LUT block if it is non-linear.}(hjOchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjKcubah}(h]h ]h"]h$]h&]uh1hhjHcubh)}(hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.h]h)}(hjech]hKThe CRTC DGM block will be placed in the DGM LUT block if it is non-linear.}(hjgchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjccubah}(h]h ]h"]h$]h&]uh1hhjHcubh)}(hJThe CRTC CTM will be placed in the gamut remap block if it is non-linear. h]h)}(hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.h]hIThe CRTC CTM will be placed in the gamut remap block if it is non-linear.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj{cubah}(h]h ]h"]h$]h&]uh1hhjHcubeh}(h]h ]h"]h$]h&]j&j&uh1hhj\chMhjbubh)}(h~The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM.h]hThe RGM block is typically more fully featured and accurate across all ASICs - DCE can’t support a custom non-linear CRTC DGM.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubh)}(hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.h]hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of CRTC properties or blend adjustments together.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubh)}(h **Return**h]j)}(hjch]hReturn}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubh)}(h(0 on success. Error code if setup fails.h]h(0 on success. Error code if setup fails.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjbubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.amdgpu_dm_update_plane_color_mgmt (C function)#c.amdgpu_dm_update_plane_color_mgmthNtauh1j~hjOEhhhNhNubj)}(hhh](j)}(hint amdgpu_dm_update_plane_color_mgmt (struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h]j)}(hint amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](jZ$)}(hinth]hint}(hjchhhNhNubah}(h]h ]jf$ah"]h$]h&]uh1jY$hjchhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj)}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhj dhMubj)}(h!amdgpu_dm_update_plane_color_mgmth]j)}(h!amdgpu_dm_update_plane_color_mgmth]h!amdgpu_dm_update_plane_color_mgmt}(hj dhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ](jjeh"]h$]h&]jjuh1jhjchhhj dhMubj$)}(hh(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](j$)}(hstruct dm_crtc_state *crtch](j)}(hjh]hstruct}(hjemodnameN classnameNjwjz)}j}]jvd#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhjeubj)}(h h]h }(hjZehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj$)}(hj$h]h*}(hjhehhhNhNubah}(h]h ]j$ah"]h$]h&]uh1j$hjeubj)}(hdc_plane_stateh]hdc_plane_state}(hjuehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphjjuh1j$hj4dubeh}(h]h ]h"]h$]h&]jjuh1j$hjchhhj dhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjchhhj dhMubah}(h]jcah ](jjeh"]h$]h&]jj)jhuh1jhj dhMhjchhubj)}(hhh]h)}(h&Maps DRM color management to DC plane.h]h&Maps DRM color management to DC plane.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjehhubah}(h]h ]h"]h$]h&]uh1jhjchhhj dhMubeh}(h]h ](j_functioneh"]h$]h&]jj_jjejjejjjuh1jhhhjOEhNhNubj )}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``struct drm_plane_state *plane_state`` DRM plane state ``struct dc_plane_state *dc_plane_state`` target DC surface **Description** Update the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management. **Return** 0 on success. -ENOMEM if mem allocation fails.h](h)}(h**Parameters**h]j)}(hjeh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubjl)}(hhh](jq)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](jw)}(h``struct dm_crtc_state *crtc``h]jS)}(hjeh]hstruct dm_crtc_state *crtc}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjeubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubj)}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehMhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jphjehMhjeubjq)}(h8``struct drm_plane_state *plane_state`` DRM plane state h](jw)}(h'``struct drm_plane_state *plane_state``h]jS)}(hjfh]h#struct drm_plane_state *plane_state}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjfubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjfubj)}(hhh]h)}(hDRM plane stateh]hDRM plane state}(hj2fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.fhMhj/fubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jphj.fhMhjeubjq)}(h<``struct dc_plane_state *dc_plane_state`` target DC surface h](jw)}(h)``struct dc_plane_state *dc_plane_state``h]jS)}(hjRfh]h%struct dc_plane_state *dc_plane_state}(hjTfhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjPfubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjLfubj)}(hhh]h)}(htarget DC surfaceh]htarget DC surface}(hjkfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjgfhMhjhfubah}(h]h ]h"]h$]h&]uh1jhjLfubeh}(h]h ]h"]h$]h&]uh1jphjgfhMhjeubeh}(h]h ]h"]h$]h&]uh1jkhjeubh)}(h**Description**h]j)}(hjfh]h Description}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubh)}(hUpdate the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.h]hUpdate the underlying dc_stream_state’s input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubh)}(h **Return**h]j)}(hjfh]hReturn}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubh)}(h.0 on success. -ENOMEM if mem allocation fails.h]h.0 on success. -ENOMEM if mem allocation fails.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjOEhhhNhNubh)}(hhh](h)}(h-DC Color Capabilities between DCN generationsh]h-DC Color Capabilities between DCN generations}(hjfhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjfhhhhhK7ubh)}(hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.h]hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjfhhubh)}(hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.h]hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjfhhubh)}(h'**Color management caps (DPP and MPC)**h]j)}(hjgh]h#Color management caps (DPP and MPC)}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj gubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjfhhubh)}(hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.h]hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.}(hj%ghhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_SURFACES (C macro)c.MAX_SURFACEShNtauh1j~hjfhhhNhNubj)}(hhh](j)}(h MAX_SURFACESh]j)}(h MAX_SURFACESh]j)}(h MAX_SURFACESh]j)}(hjGgh]h MAX_SURFACES}(hjQghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMgubah}(h]h ](jjeh"]h$]h&]jjuh1jhjIghhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhK=ubah}(h]h ]h"]h$]h&]jjjuh1jjjhjEghhhjdghK=ubah}(h]j@gah ](jjeh"]h$]h&]jj)jhuh1jhjdghK=hjBghhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjBghhhjdghK=ubeh}(h]h ](j_macroeh"]h$]h&]jj_jj}gjj}gjjjuh1jhhhjfhNhNubh)}(h``MAX_SURFACES``h]jS)}(hjgh]h MAX_SURFACES}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjgubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhK?hjfhhubh block_quote)}(hRrepresentative of the upper bound of surfaces that can be piped to a single CRTC h]h)}(hPrepresentative of the upper bound of surfaces that can be piped to a single CRTCh]hPrepresentative of the upper bound of surfaces that can be piped to a single CRTC}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhK;hjgubah}(h]h ]h"]h$]h&]uh1jghjghK;hjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_PLANES (C macro) c.MAX_PLANEShNtauh1j~hjfhhhNhNubj)}(hhh](j)}(h MAX_PLANESh]j)}(h MAX_PLANESh]j)}(h MAX_PLANESh]j)}(hjgh]h MAX_PLANES}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ](jjeh"]h$]h&]jjuh1jhjghhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKAubah}(h]h ]h"]h$]h&]jjjuh1jjjhjghhhjghKAubah}(h]jgah ](jjeh"]h$]h&]jj)jhuh1jhjghKAhjghhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjghhhjghKAubeh}(h]h ](j_macroeh"]h$]h&]jj_jjgjjgjjjuh1jhhhjfhNhNubh)}(h``MAX_PLANES``h]jS)}(hjhh]h MAX_PLANES}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjhubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKChjfhhubjg)}(hLrepresentative of the upper bound of planes that are supported by the HW h]h)}(hHrepresentative of the upper bound of planes that are supported by the HWh]hHrepresentative of the upper bound of planes that are supported by the HW}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhK?hjhubah}(h]h ]h"]h$]h&]uh1jghj+hhK?hjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jrom_curve_caps (C struct)c.rom_curve_capshNtauh1j~hjfhhhNhNubj)}(hhh](j)}(hrom_curve_capsh]j)}(hstruct rom_curve_capsh](j)}(hjh]hstruct}(hjKhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKDubj)}(h h]h }(hjYhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhhhjXhhKDubj)}(hrom_curve_capsh]j)}(hjEhh]hrom_curve_caps}(hjkhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjghubah}(h]h ](jjeh"]h$]h&]jjuh1jhjGhhhhjXhhKDubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjChhhhjXhhKDubah}(h]j>hah ](jjeh"]h$]h&]jj)jhuh1jhjXhhKDhj@hhhubj)}(hhh]h)}(h9predefined transfer function caps for degamma and regammah]h9predefined transfer function caps for degamma and regamma}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhhubah}(h]h ]h"]h$]h&]uh1jhj@hhhhjXhhKDubeh}(h]h ](j_structeh"]h$]h&]jj_jjhjjhjjjuh1jhhhjfhNhNubj )}(hX**Definition**:: struct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; }; **Members** ``srgb`` RGB color space transfer func ``bt2020`` BT.2020 transfer func ``gamma2_2`` standard gamma ``pq`` perceptual quantizer transfer function ``hlg`` hybrid log–gamma transfer functionh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubh:}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhubjC)}(hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };h]hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };}hjhsbah}(h]h ]h"]h$]h&]jjuh1jBhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhubh)}(h **Members**h]j)}(hjhh]hMembers}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhubjl)}(hhh](jq)}(h'``srgb`` RGB color space transfer func h](jw)}(h``srgb``h]jS)}(hjhh]hsrgb}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjhubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhubj)}(hhh]h)}(hRGB color space transfer funch]hRGB color space transfer func}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKhjiubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jphjihKhjhubjq)}(h!``bt2020`` BT.2020 transfer func h](jw)}(h ``bt2020``h]jS)}(hj3ih]hbt2020}(hj5ihhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj1iubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj-iubj)}(hhh]h)}(hBT.2020 transfer funch]hBT.2020 transfer func}(hjLihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHihKhjIiubah}(h]h ]h"]h$]h&]uh1jhj-iubeh}(h]h ]h"]h$]h&]uh1jphjHihKhjhubjq)}(h``gamma2_2`` standard gamma h](jw)}(h ``gamma2_2``h]jS)}(hjlih]hgamma2_2}(hjnihhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjjiubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjfiubj)}(hhh]h)}(hstandard gammah]hstandard gamma}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKhjiubah}(h]h ]h"]h$]h&]uh1jhjfiubeh}(h]h ]h"]h$]h&]uh1jphjihKhjhubjq)}(h.``pq`` perceptual quantizer transfer function h](jw)}(h``pq``h]jS)}(hjih]hpq}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjiubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjiubj)}(hhh]h)}(h&perceptual quantizer transfer functionh]h&perceptual quantizer transfer function}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihKhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jphjihKhjhubjq)}(h,``hlg`` hybrid log–gamma transfer functionh](jw)}(h``hlg``h]jS)}(hjih]hhlg}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjiubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjiubj)}(hhh]h)}(h$hybrid log–gamma transfer functionh]h$hybrid log–gamma transfer function}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jphjihKhjhubeh}(h]h ]h"]h$]h&]uh1jkhjhubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpp_color_caps (C struct)c.dpp_color_capshNtauh1j~hjfhhhNhNubj)}(hhh](j)}(hdpp_color_capsh]j)}(hstruct dpp_color_capsh](j)}(hjh]hstruct}(hj8jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4jhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKubj)}(h h]h }(hjFjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4jhhhjEjhKubj)}(hdpp_color_capsh]j)}(hj2jh]hdpp_color_caps}(hjXjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj4jhhhjEjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj0jhhhjEjhKubah}(h]j+jah ](jjeh"]h$]h&]jj)jhuh1jhjEjhKhj-jhhubj)}(hhh]h)}(h=color pipeline capabilities for display pipe and plane blocksh]h=color pipeline capabilities for display pipe and plane blocks}(hjzjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjwjhhubah}(h]h ]h"]h$]h&]uh1jhj-jhhhjEjhKubeh}(h]h ](j_structeh"]h$]h&]jj_jjjjjjjjjuh1jhhhjfhNhNubj )}(hX**Definition**:: struct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; }; **Members** ``dcn_arch`` all DCE generations treated the same ``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup ``icsc`` input color space conversion ``dgam_ram`` programmable degamma LUT ``post_csc`` post color space conversion, before gamut remap ``gamma_corr`` degamma correction ``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag ``ogam_ram`` programmable out/blend gamma LUT ``ocsc`` output color space conversion ``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes ``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubh:}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjjubjC)}(hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };h]hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };}hjjsbah}(h]h ]h"]h$]h&]jjuh1jBhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjjubh)}(h **Members**h]j)}(hjjh]hMembers}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjjubjl)}(hhh](jq)}(h2``dcn_arch`` all DCE generations treated the same h](jw)}(h ``dcn_arch``h]jS)}(hjjh]hdcn_arch}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjjubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjjubj)}(hhh]h)}(h$all DCE generations treated the sameh]h$all DCE generations treated the same}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKhjjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jphjjhKhjjubjq)}(hj``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup h](jw)}(h``input_lut_shared``h]jS)}(hj kh]hinput_lut_shared}(hj"khhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjkubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjkubj)}(hhh]h)}(hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookuph]hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup}(hj9khhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj6kubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jphj5khKhjjubjq)}(h&``icsc`` input color space conversion h](jw)}(h``icsc``h]jS)}(hjZkh]hicsc}(hj\khhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjXkubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjTkubj)}(hhh]h)}(hinput color space conversionh]hinput color space conversion}(hjskhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjokhKhjpkubah}(h]h ]h"]h$]h&]uh1jhjTkubeh}(h]h ]h"]h$]h&]uh1jphjokhKhjjubjq)}(h&``dgam_ram`` programmable degamma LUT h](jw)}(h ``dgam_ram``h]jS)}(hjkh]hdgam_ram}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjkubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjkubj)}(hhh]h)}(hprogrammable degamma LUTh]hprogrammable degamma LUT}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjkubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jphjkhKhjjubjq)}(h=``post_csc`` post color space conversion, before gamut remap h](jw)}(h ``post_csc``h]jS)}(hjkh]hpost_csc}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjkubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjkubj)}(hhh]h)}(h/post color space conversion, before gamut remaph]h/post color space conversion, before gamut remap}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjkubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jphjkhKhjjubjq)}(h"``gamma_corr`` degamma correction h](jw)}(h``gamma_corr``h]jS)}(hjlh]h gamma_corr}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjlubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjkubj)}(hhh]h)}(hdegamma correctionh]hdegamma correction}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhKhjlubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jphjlhKhjjubjq)}(hz``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag h](jw)}(h ``hw_3d_lut``h]jS)}(hj>lh]h hw_3d_lut}(hj@lhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjqhhhjSqhKubah}(h]j9qah ](jjeh"]h$]h&]jj)jhuh1jhjSqhKhj;qhhubj)}(hhh]h)}(h$Pipe split strategy supported by DCNh]h$Pipe split strategy supported by DCN}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqhhubah}(h]h ]h"]h$]h&]uh1jhj;qhhhjSqhKubeh}(h]h ](j_enumeh"]h$]h&]jj_jjqjjqjjjuh1jhhhjfhNhNubj )}(hX**Constants** ``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. ``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. ``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](h)}(h **Constants**h]j)}(hjqh]h Constants}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubjl)}(hhh](jq)}(h``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. h](jw)}(h``MPC_SPLIT_DYNAMIC``h]jS)}(hjqh]hMPC_SPLIT_DYNAMIC}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjqubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubj)}(hhh]h)}(hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.h]hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jphjqhMhjqubjq)}(hg``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. h](jw)}(h``MPC_SPLIT_AVOID``h]jS)}(hjrh]hMPC_SPLIT_AVOID}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjrubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM#hjqubj)}(hhh]h)}(hRAvoid pipe split, which means that DC will not try any sort of split optimization.h]hRAvoid pipe split, which means that DC will not try any sort of split optimization.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM"hjrubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jphjrhM#hjqubjq)}(h``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](jw)}(h``MPC_SPLIT_AVOID_MULT_DISP``h]jS)}(hj=rh]hMPC_SPLIT_AVOID_MULT_DISP}(hj?rhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj;rubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM'hj7rubj)}(hhh]h)}(hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h]hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.}(hjVrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM&hjSrubah}(h]h ]h"]h$]h&]uh1jhj7rubeh}(h]h ]h"]h$]h&]uh1jphjRrhM'hjqubeh}(h]h ]h"]h$]h&]uh1jkhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubh)}(h**Description**h]j)}(hjrh]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~rubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM+hjfhhubh)}(hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.h]hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjfhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdc_validation_set (C struct)c.dc_validation_sethNtauh1j~hjfhhhNhNubj)}(hhh](j)}(hdc_validation_seth]j)}(hstruct dc_validation_seth](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhjrhMubj)}(hdc_validation_seth]j)}(hjrh]hdc_validation_set}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubah}(h]h ](jjeh"]h$]h&]jjuh1jhjrhhhjrhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjrhhhjrhMubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1jhjrhMhjrhhubj)}(hhh]h)}(h:Struct to store surface/stream associations for validationh]h:Struct to store surface/stream associations for validation}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjrhhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjrhMubeh}(h]h ](j_structeh"]h$]h&]jj_jjsjjsjjjuh1jhhhjfhNhNubj )}(hX,**Definition**:: struct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; }; **Members** ``stream`` Stream state properties ``plane_states`` Surface state ``plane_count`` Total of active planesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj$shhhNhNubah}(h]h ]h"]h$]h&]uh1jhj subh:}(hj shhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM$hjsubjC)}(hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };h]hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };}hj=ssbah}(h]h ]h"]h$]h&]jjuh1jBhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM&hjsubh)}(h **Members**h]j)}(hjNsh]hMembers}(hjPshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLsubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM,hjsubjl)}(hhh](jq)}(h#``stream`` Stream state properties h](jw)}(h ``stream``h]jS)}(hjmsh]hstream}(hjoshhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjksubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM%hjgsubj)}(hhh]h)}(hStream state propertiesh]hStream state properties}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshM%hjsubah}(h]h ]h"]h$]h&]uh1jhjgsubeh}(h]h ]h"]h$]h&]uh1jphjshM%hjdsubjq)}(h``plane_states`` Surface state h](jw)}(h``plane_states``h]jS)}(hjsh]h plane_states}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjsubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM*hjsubj)}(hhh]h)}(h Surface stateh]h Surface state}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshM*hjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jphjshM*hjdsubjq)}(h&``plane_count`` Total of active planesh](jw)}(h``plane_count``h]jS)}(hjsh]h plane_count}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjsubah}(h]h ]h"]h$]h&]uh1jvhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM.hjsubj)}(hhh]h)}(hTotal of active planesh]hTotal of active planes}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM/hjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jphjshM.hjdsubeh}(h]h ]h"]h$]h&]uh1jkhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjfhhhNhNubh)}(hThe color pipeline has undergone major changes between DCN hardware generations. What's possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.h]hThe color pipeline has undergone major changes between DCN hardware generations. What’s possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.}(hj thhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjfhhubh)}(h)**DCN 2.0 family color caps and mapping**h]j)}(hj0th]h%DCN 2.0 family color caps and mapping}(hj2thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.tubah}(h]h ]h"]h$]h&]uh1hhhhKOhjfhhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h+.. kernel-figure:: dcn2_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn2_cm_drm_current.svg candidates}j$j]tsuh1jPthjMthhhKubah}(h]h ]h"]h$]h&]uh1jKthjHtubah}(h]h ]h"]h$]h&]uh1jFthjfhhhhhKRubh)}(h)**DCN 3.0 family color caps and mapping**h]j)}(hjnth]h%DCN 3.0 family color caps and mapping}(hjpthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjltubah}(h]h ]h"]h$]h&]uh1hhhhKShjfhhubjGt)}(hhh]jLt)}(hhh]jQt)}(h+.. kernel-figure:: dcn3_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn3_cm_drm_current.svgj^t}j$jtsuh1jPthjthhhKubah}(h]h ]h"]h$]h&]uh1jKthjtubah}(h]h ]h"]h$]h&]uh1jFthjfhhhhhKVubeh}(h]jah ]h"]-dc color capabilities between dcn generationsah$]h&]uh1hhjOEhhhhhK7ubeh}(h]jqah ]h"]color management propertiesah$]h&]uh1hhhhhhhhK-ubh)}(hhh](h)}(hBlend Mode Propertiesh]hBlend Mode Properties}(hjthhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjthhhhhKXubh)}(hXPixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in :ref:`DRM Plane Composition Properties `.h](h8Pixel blend mode is a DRM plane composition property of }(hjthhhNhNubh)}(h:c:type:`drm_plane`h]jS)}(hjth]h drm_plane}(hjthhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjtubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq drm_planeuh1hhhhKZhjtubhX' used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in }(hjthhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]hinline)}(hjth]h DRM Plane Composition Properties}(hjthhhNhNubah}(h]h ](j^stdstd-refeh"]h$]h&]uh1jthjtubah}(h]h ]h"]h$]h&]refdocjk refdomainjtreftyperef refexplicitrefwarnjqplane_composition_propertiesuh1hhhhKZhjtubh.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKZhjthhubh)}(hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:h]hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjthhubh)}(hhh](h)}(hG*fg.rgb*: Each of the RGB component values from the foreground's pixel.h]h)}(hj+uh](j A)}(h*fg.rgb*h]hfg.rgb}(hj0uhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj-uubhA: Each of the RGB component values from the foreground’s pixel.}(hj-uhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKfhj)uubah}(h]h ]h"]h$]h&]uh1hhj&uhhhhhNubh)}(h>*fg.alpha*: Alpha component value from the foreground's pixel.h]h)}(hjPuh](j A)}(h *fg.alpha*h]hfg.alpha}(hjUuhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjRuubh6: Alpha component value from the foreground’s pixel.}(hjRuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjNuubah}(h]h ]h"]h$]h&]uh1hhj&uhhhhhNubh)}(h?*bg.rgb*: Each of the RGB component values from the background.h]h)}(hjuuh](j A)}(h*bg.rgb*h]hbg.rgb}(hjzuhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjwuubh7: Each of the RGB component values from the background.}(hjwuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhjsuubah}(h]h ]h"]h$]h&]uh1hhj&uhhhhhNubh)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `. h]h)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `.h](j A)}(h *plane_alpha*h]h plane_alpha}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjuubh: Plane alpha value set by the }(hjuhhhNhNubj)}(h**plane "alpha" property**h]hplane “alpha” property}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh, see more in }(hjuhhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]jt)}(hjuh]h DRM Plane Composition Properties}(hjuhhhNhNubah}(h]h ](j^stdstd-refeh"]h$]h&]uh1jthjuubah}(h]h ]h"]h$]h&]refdocjk refdomainjureftyperef refexplicitrefwarnjqplane_composition_propertiesuh1hhhhKihjuubh.}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihjuubah}(h]h ]h"]h$]h&]uh1hhj&uhhhhhNubeh}(h]h ]h"]h$]h&]j&j&uh1hhhhKfhjthhubh)}(h&in the basic alpha blending equation::h]h%in the basic alpha blending equation:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjthhubjC)}(h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgbh]h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb}hjvsbah}(h]h ]h"]h$]h&]jjuh1jBhhhKnhjthhubh)}(h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.h]h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjthhubh)}(hNDRM has three blend mode to define the blend formula in the plane composition:h]hNDRM has three blend mode to define the blend formula in the plane composition:}(hj$vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjthhubh)}(hhh](h)}(h6**None**: Blend formula that ignores the pixel alpha. h]h)}(h5**None**: Blend formula that ignores the pixel alpha.h](j)}(h**None**h]hNone}(hj=vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9vubh-: Blend formula that ignores the pixel alpha.}(hj9vhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKuhj5vubah}(h]h ]h"]h$]h&]uh1hhj2vhhhhhNubh)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage. h]h)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.h](j)}(h**Pre-multiplied**h]hPre-multiplied}(hjcvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_vubh: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.}(hj_vhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhj[vubah}(h]h ]h"]h$]h&]uh1hhj2vhhhhhNubh)}(hw**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values. h]h)}(hv**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.h](j)}(h **Coverage**h]hCoverage}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubhj: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhjvubah}(h]h ]h"]h$]h&]uh1hhj2vhhhhhNubeh}(h]h ]h"]h$]h&]j&j$uh1hhhhKuhjthhubh)}(hX1and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane's pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.h]hX3and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane’s pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjthhubh)}(hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:h]hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjthhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpcc_blnd_cfg (C struct)c.mpcc_blnd_cfghNtauh1j~hjthhhNhNubj)}(hhh](j)}(h mpcc_blnd_cfgh]j)}(hstruct mpcc_blnd_cfgh](j)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:134: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKubj)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhjvhKubj)}(h mpcc_blnd_cfgh]j)}(hjvh]h mpcc_blnd_cfg}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ](jjeh"]h$]h&]jjuh1jhjvhhhjvhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjvhhhjvhKubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1jhjvhKhjvhhubj)}(hhh]h)}(hMPCC blending configurationh]hMPCC blending configuration}(hj$whhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:134: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK|hj!whhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhKubeh}(h]h ](j_structeh"]h$]h&]jj_jj``MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN``h]jS)}(hj{h]h:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj{ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:146: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK[hj{ubj)}(hhh]h)}(hOper pixel alpha using DPP alpha value multiplied by a global gain (plane alpha)h]hOper pixel alpha using DPP alpha value multiplied by a global gain (plane alpha)}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:146: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKYhj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jphj{hK[hj]{ubjq)}(hl``MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`` global alpha value, ignores pixel alpha and consider only plane alphah](jw)}(h&``MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA``h]jS)}(hj{h]h"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj{ubah}(h]h ]h"]h$]h&]uh1jvh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:146: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK^hj{ubj)}(hhh]h)}(hEglobal alpha value, ignores pixel alpha and consider only plane alphah]hEglobal alpha value, ignores pixel alpha and consider only plane alpha}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hK^hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jphj{hK^hj]{ubeh}(h]h ]h"]h$]h&]uh1jkhjA{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjthhhNhNubh)}(hhDM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM blend formula, as follows:h](hDM then maps the elements of }(hj|hhhNhNubhtitle_reference)}(h`enum mpcc_alpha_blend_mode`h]henum mpcc_alpha_blend_mode}(hj$|hhhNhNubah}(h]h ]h"]h$]h&]uh1j"|hj|ubh/ to those in the DRM blend formula, as follows:}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjthhubh)}(hhh](h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh]h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh](j A)}(h*MPC pixel alpha*h]hMPC pixel alpha}(hjG|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjC|ubh matches }(hjC|hhhNhNubj A)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjY|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhjC|ubh6 as the alpha component value from the plane’s pixel}(hjC|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj?|ubah}(h]h ]h"]h$]h&]uh1hhj<|hhhhhNubh)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh]h)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh](j A)}(h*MPC global alpha*h]hMPC global alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj{|ubh matches }(hj{|hhhNhNubj A)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj{|ubh[ when the pixel alpha should be ignored and, therefore, pixel values are not pre-multiplied}(hj{|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjw|ubah}(h]h ]h"]h$]h&]uh1hhj<|hhhhhNubh)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equation h]h)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equationh](j A)}(h*MPC global gain*h]hMPC global gain}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|ubh assumes }(hj|hhhNhNubj A)}(h*MPC global alpha*h]hMPC global alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|ubh value when both }(hj|hhhNhNubj A)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|ubh and }(hj|hhhNhNubj A)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj|ubh" participate in the blend equation}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj|ubah}(h]h ]h"]h$]h&]uh1hhj<|hhhhhNubeh}(h]h ]h"]h$]h&]j&j$uh1hhhhKhjthhubh)}(hXhIn short, *fg.alpha* is ignored by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the :c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are pre-multiplied by alpha or not.h](h In short, }(hj}hhhNhNubj A)}(h *fg.alpha*h]hfg.alpha}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jAhj}ubh is ignored by selecting }(hj}hhhNhNubh)}(h,:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`h]jS)}(hj-}h]h"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA}(hj/}hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj+}ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHAuh1hhhhKhj}ubhW. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting }(hj}hhhNhNubh)}(hD:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`h]jS)}(hjP}h]h:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN}(hjR}hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjN}ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAINuh1hhhhKhj}ubh . And the }(hj}hhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]jS)}(hjs}h]hMPCC_ALPHA_MULTIPLIED_MODE}(hju}hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjq}ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqMPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhj}ubhF defines if the pixel color values are pre-multiplied by alpha or not.}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjthhubh)}(hhh](h)}(hBlend configuration flowh]hBlend configuration flow}(hj}hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj}hhhhhKubh)}(hYThe alpha blending equation is configured from DRM to DC interface by the following path:h]hYThe alpha blending equation is configured from DRM to DC interface by the following path:}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubhenumerated_list)}(hhh](h)}(hX%When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC). h]h)}(hX$When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC).h](hWhen updating a }(hj}hhhNhNubh)}(h+:c:type:`drm_plane_state `h]jS)}(hj}h]hdrm_plane_state}(hj}hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj}ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqdrm_plane_stateuh1hhhhKhj}ubh , DM calls }(hj}hhhNhNubh)}(h::c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()`h]jS)}(hj}h]h0amdgpu_dm_plane_fill_blending_from_plane_state()}(hj}hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj}ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq0amdgpu_dm_plane_fill_blending_from_plane_state()uh1hhhhKhj}ubh that maps }(hj}hhhNhNubh)}(h+:c:type:`drm_plane_state `h]jS)}(hj~h]hdrm_plane_state}(hj~hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj~ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jqdrm_plane_stateuh1hhhhKhj}ubh attributes to }(hj}hhhNhNubh)}(h':c:type:`dc_plane_info `h]jS)}(hj5~h]h dc_plane_info}(hj7~hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj3~ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq dc_plane_infouh1hhhhKhj}ubh8 struct to be handled in the OS-agnostic component (DC).}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1hhj}hhhhhNubh)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h]h)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h](hOn DC interface, }(hjf~hhhNhNubh)}(h.:c:type:`struct mpcc_blnd_cfg `h]jS)}(hjp~h]hstruct mpcc_blnd_cfg}(hjr~hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhjn~ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq mpcc_blnd_cfguh1hhhhKhjf~ubh7 programs the MPCC blend configuration considering the }(hjf~hhhNhNubh)}(h':c:type:`dc_plane_info `h]jS)}(hj~h]h dc_plane_info}(hj~hhhNhNubah}(h]h ](j^j_c-typeeh"]h$]h&]uh1jRhj~ubah}(h]h ]h"]h$]h&]refdocjk refdomainj_reftypetype refexplicitrefwarnjwj{jq dc_plane_infouh1hhhhKhjf~ubh input from DPP.}(hjf~hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjb~ubah}(h]h ]h"]h$]h&]uh1hhj}hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j}hj}hhhhhKubeh}(h]jah ]h"]blend configuration flowah$]h&]uh1hhjthhhhhKubeh}(h]jah ]h"]blend mode propertiesah$]h&]uh1hhhhhhhhKXubeh}(h]hah ]h"]amdgpu display managerah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j~hjj jS(j jAj-jLEjOjtjqjtjj~jj~ju nametypes}(j~jjS(jAjLEjtjtj~j~uh}(hhj hjjj;j@jjjjjW j\ j j jj jjjjj#j(j!j!j j#jL$jQ$j&j&j-jV(j)j)j+j+j-j-j.j.j2j2j25j75j7j7j8j8jk;jp;j<j<jm>jr>j?j?jOj AjAAjFAjBjBjqjOEj~FjFjGjGj'Jj,JjkLjpLjOj"OjbQjgQjSjSjWjWj4Zj9Zj]j]j_j_jajajcjcjjfj@gjEgjgjgj>hjChj+jj0jjmjmjojoj9qj>qjrjrjjtjvjvjzjzjj}hhjhj'jjIj@jkjbjjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}jKsRparse_messages]transform_messages] transformerN include_log] decorationNhhub.