sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget6/translations/zh_CN/gpu/amdgpu/display/display-managermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/zh_TW/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/it_IT/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ja_JP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ko_KR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/pt_BR/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/sp_SP/gpu/amdgpu/display/display-managermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDgpu Display Managerh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]refidid1uh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager.rsthKubhtopic)}(hTable of Contents h](h)}(hTable of Contentsh]hTable of Contents}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh bullet_list)}(hhh]h list_item)}(hhh](h paragraph)}(hhh]h reference)}(hhh]hAMDgpu Display Manager}(hhhhhNhNubah}(h]hah ]h"]h$]h&]refidamdgpu-display-manageruh1hhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]h Lifecycle}(hjhhhNhNubah}(h]id2ah ]h"]h$]h&]refid lifecycleuh1hhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h Interrupts}(hj2hhhNhNubah}(h]id3ah ]h"]h$]h&]refid interruptsuh1hhj/ubah}(h]h ]h"]h$]h&]uh1hhj,ubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hAtomic Implementation}(hjThhhNhNubah}(h]id4ah ]h"]h$]h&]refidatomic-implementationuh1hhjQubah}(h]h ]h"]h$]h&]uh1hhjNubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]hColor Management Properties}(hjvhhhNhNubah}(h]id5ah ]h"]h$]h&]refidcolor-management-propertiesuh1hhjsubah}(h]h ]h"]h$]h&]uh1hhjpubh)}(hhh](h)}(hhh]h)}(hhh]h)}(hhh]hdrm_crtc Properties}(hjhhhNhNubah}(h]id6ah ]h"]h$]h&]refiddrm-crtc-propertiesuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h)AMD Private Color Management on drm_plane}(hjhhhNhNubah}(h]id7ah ]h"]h$]h&]refid)amd-private-color-management-on-drm-planeuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]hAMD plane color pipeline}(hjhhhNhNubah}(h]id8ah ]h"]h$]h&]refidamd-plane-color-pipelineuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh]h)}(hhh]h)}(hhh]h-DC Color Capabilities between DCN generations}(hjhhhNhNubah}(h]id9ah ]h"]h$]h&]refid-dc-color-capabilities-between-dcn-generationsuh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhjpubeh}(h]h ]h"]h$]h&]uh1hhjubh)}(hhh](h)}(hhh]h)}(hhh]hBlend Mode Properties}(hj)hhhNhNubah}(h]id10ah ]h"]h$]h&]refidblend-mode-propertiesuh1hhj&ubah}(h]h ]h"]h$]h&]uh1hhj#ubh)}(hhh]h)}(hhh]h)}(hhh]h)}(hhh]hBlend configuration flow}(hjHhhhNhNubah}(h]id11ah ]h"]h$]h&]refidblend-configuration-flowuh1hhjEubah}(h]h ]h"]h$]h&]uh1hhjBubah}(h]h ]h"]h$]h&]uh1hhj?ubah}(h]h ]h"]h$]h&]uh1hhj#ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubeh}(h]table-of-contentsah ]contentsah"]table of contentsah$]h&]uh1hhhhKhhhhubh)}(hThe AMDgpu display manager, **amdgpu_dm** (or even simpler, **dm**) sits between DRM and DC. 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struct)c.dm_compressor_infohNtauh1jhhhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhNubhdesc)}(hhh](hdesc_signature)}(hdm_compressor_infoh]hdesc_signature_line)}(hstruct dm_compressor_infoh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubhdesc_sig_space)}(h h]h }(hj/hhhNhNubah}(h]h ]wah"]h$]h&]uh1j-hjhhhj,hKubh desc_name)}(hdm_compressor_infoh]h desc_sig_name)}(hjh]hdm_compressor_info}(hjFhhhNhNubah}(h]h ]nah"]h$]h&]uh1jDhj@ubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1j>hjhhhj,hKubeh}(h]h ]h"]h$]h&]j\j] add_permalinkuh1jsphinx_line_type declaratorhjhhhj,hKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhj,hKhj hhubh desc_content)}(hhh]h)}(h,Buffer info used by frame buffer compressionh]h,Buffer info used by frame buffer compression}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKehjthhubah}(h]h ]h"]h$]h&]uh1jrhj hhhj,hKubeh}(h]h ](jstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j hhhhhj hNubh container)}(h**Definition**:: struct dm_compressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; uint64_t gpu_addr; }; **Members** ``cpu_addr`` MMIO cpu addr ``bo_ptr`` Pointer to the buffer object ``gpu_addr`` MMIO gpu addrh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKihjubh literal_block)}(hgstruct dm_compressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; uint64_t gpu_addr; };h]hgstruct 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]h"]h$]h&]j\j]jduh1jjejfhjnhhhjhK|ubah}(h]jiah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhK|hjkhhubjs)}(hhh]h)}(h5Handle time consuming work in low priority outbox IRQh]h5Handle time consuming work in low priority outbox IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jrhjkhhhjhK|ubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhhhj hNubj)}(hXc**Definition**:: struct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; }; **Members** ``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq ``dmub_notify`` notification for callback function ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };h]hstruct dmub_hpd_work { struct work_struct handle_hpd_work; struct dmub_notification *dmub_notify; struct amdgpu_device *adev; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh](j)}(hS``handle_hpd_work`` Work to be executed in a separate thread to handle hpd_low_irq h](j)}(h``handle_hpd_work``h]j)}(hj%h]hhandle_hpd_work}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h>Work to be executed in a separate thread to handle hpd_low_irqh]h>Work to be executed in a separate thread to handle hpd_low_irq}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hKhj;ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj:hKhjubj)}(h3``dmub_notify`` notification for callback function h](j)}(h``dmub_notify``h]j)}(hj^h]h dmub_notify}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjXubj )}(hhh]h)}(h"notification for callback functionh]h"notification for callback function}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshKhjtubah}(h]h ]h"]h$]h&]uh1j hjXubeh}(h]h ]h"]h$]h&]uh1jhjshKhjubj)}(h``adev`` amdgpu_device pointerh](j)}(h``adev``h]j)}(hjh]hadev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jvblank_control_work (C struct)c.vblank_control_workhNtauh1jhhhhhj hNubj )}(hhh](j)}(hvblank_control_workh]j)}(hstruct vblank_control_workh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhKubj?)}(hvblank_control_workh]jE)}(hjh]hvblank_control_work}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhKubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhKhjhhubjs)}(hhh]h)}(hWork data for vblank controlh]hWork data for vblank control}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj0hhubah}(h]h ]h"]h$]h&]uh1jrhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjKjjKjjjuh1j hhhhhj hNubj)}(hX**Definition**:: struct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``acrtc`` amdgpu CRTC instance for which the event has occurred ``stream`` DC stream for which the event has occurred ``enable`` true if enabling vblankh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh:}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjOubj)}(hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };h]hstruct vblank_control_work { struct work_struct work; struct amdgpu_display_manager *dm; struct amdgpu_crtc *acrtc; struct dc_stream_state *stream; bool enable; };}hjpsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjOubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjOubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hjh]hdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h@``acrtc`` amdgpu CRTC instance for which the event has occurred h](j)}(h ``acrtc``h]j)}(hj h]hacrtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(h5amdgpu CRTC instance for which the event has occurredh]h5amdgpu CRTC instance for which the event has occurred}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj' hKhj( ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj' hKhjubj)}(h6``stream`` DC stream for which the event has occurred h](j)}(h ``stream``h]j)}(hjK h]hstream}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjE ubj )}(hhh]h)}(h*DC stream for which the event has occurredh]h*DC stream for which the event has occurred}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj` hKhja ubah}(h]h ]h"]h$]h&]uh1j hjE ubeh}(h]h ]h"]h$]h&]uh1jhj` hKhjubj)}(h"``enable`` true if enabling vblankh](j)}(h ``enable``h]j)}(hj h]henable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj~ ubj )}(hhh]h)}(htrue if enabling vblankh]htrue if enabling vblank}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1j hj~ ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jidle_workqueue (C struct)c.idle_workqueuehNtauh1jhhhhhj hNubj )}(hhh](j)}(hidle_workqueueh]j)}(hstruct idle_workqueueh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj hhhj hKubj?)}(hidle_workqueueh]jE)}(hj h]hidle_workqueue}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj hhhj hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj hhhj hKubah}(h]j ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj hKhj hhubjs)}(hhh]h)}(h%Work data for periodic action in idleh]h%Work data for periodic action in idle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jrhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj8 jj8 jjjuh1j hhhhhj hNubj)}(hX_**Definition**:: struct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; }; **Members** ``work`` Kernel work data for the work event ``dm`` amdgpu display manager device ``enable`` true if idle worker is enabled ``running`` true if idle worker is runningh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ ubh:}(hj@ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj< ubj)}(hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };h]hstruct idle_workqueue { struct work_struct work; struct amdgpu_display_manager *dm; bool enable; bool running; };}hj] sbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj< ubh)}(h **Members**h]j)}(hjn h]hMembers}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj< ubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hj h]hwork}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h%``dm`` amdgpu display manager device h](j)}(h``dm``h]j)}(hj h]hdm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(hamdgpu display manager deviceh]hamdgpu display manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h*``enable`` true if idle worker is enabled h](j)}(h ``enable``h]j)}(hj h]henable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(htrue if idle worker is enabledh]htrue if idle worker is enabled}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h*``running`` true if idle worker is runningh](j)}(h ``running``h]j)}(hj8 h]hrunning}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6 ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj2 ubj )}(hhh]h)}(htrue if idle worker is runningh]htrue if idle worker is running}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjN ubah}(h]h ]h"]h$]h&]uh1j hj2 ubeh}(h]h ]h"]h$]h&]uh1jhjM hKhj ubeh}(h]h ]h"]h$]h&]uh1jhj< ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jvupdate_offload_work (C struct)c.vupdate_offload_workhNtauh1jhhhhhj hNubj )}(hhh](j)}(hvupdate_offload_workh]j)}(hstruct vupdate_offload_workh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj hhhj hKubj?)}(hvupdate_offload_workh]jE)}(hj h]hvupdate_offload_work}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj hhhj hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj hhhj hKubah}(h]j ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj hKhj hhubjs)}(hhh]h)}(h2Work data for offloading task from vupdate handlerh]h2Work data for offloading task from vupdate handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jrhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j hhhhhj hNubj)}(hX**Definition**:: struct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; }; **Members** ``work`` Kernel work data for the work event ``adev`` amdgpu_device back pointer ``stream`` DC stream associated with the crtc ``adjust`` DC CRTC timing adjust to be applied to the crtch](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };h]hstruct vupdate_offload_work { struct work_struct work; struct amdgpu_device *adev; struct dc_stream_state *stream; struct dc_crtc_timing_adjust *adjust; };}hj sbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj" h]hMembers}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j)}(h-``work`` Kernel work data for the work event h](j)}(h``work``h]j)}(hjA h]hwork}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj? ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj; ubj )}(hhh]h)}(h#Kernel work data for the work eventh]h#Kernel work data for the work event}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hKhjW ubah}(h]h ]h"]h$]h&]uh1j hj; ubeh}(h]h ]h"]h$]h&]uh1jhjV hKhj8 ubj)}(h$``adev`` amdgpu_device back pointer h](j)}(h``adev``h]j)}(hjz h]hadev}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjt ubj )}(hhh]h)}(hamdgpu_device back pointerh]hamdgpu_device back pointer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hjt ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj8 ubj)}(h.``stream`` DC stream associated with the crtc h](j)}(h ``stream``h]j)}(hj h]hstream}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(h"DC stream associated with the crtch]h"DC stream associated with the crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj8 ubj)}(h:``adjust`` DC CRTC timing adjust to be applied to the crtch](j)}(h ``adjust``h]j)}(hj h]hadjust}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(h/DC CRTC timing adjust to be applied to the crtch]h/DC CRTC timing adjust to be applied to the crtc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj8 ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_luminance_data (C struct)c.amdgpu_dm_luminance_datahNtauh1jhhhhhj hNubj )}(hhh](j)}(hamdgpu_dm_luminance_datah]j)}(hstruct amdgpu_dm_luminance_datah](j)}(hjh]hstruct}(hjF hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjB hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hjT hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjB hhhjS hKubj?)}(hamdgpu_dm_luminance_datah]jE)}(hj@ h]hamdgpu_dm_luminance_data}(hjf hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjb ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjB hhhjS hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj> hhhjS hKubah}(h]j9 ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjS hKhj; hhubjs)}(hhh]h)}(hCustom luminance datah]hCustom luminance data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jrhj; hhhjS hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j hhhhhj hNubj)}(h**Definition**:: struct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; }; **Members** ``luminance`` Luminance in percent ``input_signal`` Input signal in range 0-255h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };h]hKstruct amdgpu_dm_luminance_data { u8 luminance; u8 input_signal; };}hj sbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj)}(hhh](j)}(h#``luminance`` Luminance in percent h](j)}(h ``luminance``h]j)}(hj h]h luminance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj ubj )}(hhh]h)}(hLuminance in percenth]hLuminance in percent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h,``input_signal`` Input signal in range 0-255h](j)}(h``input_signal``h]j)}(hj.h]h input_signal}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj(ubj )}(hhh]h)}(hInput signal in range 0-255h]hInput signal in range 0-255}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjDubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_backlight_caps (C struct)c.amdgpu_dm_backlight_capshNtauh1jhhhhhj hNubj )}(hhh](j)}(hamdgpu_dm_backlight_capsh]j)}(hstruct amdgpu_dm_backlight_capsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhKubj?)}(hamdgpu_dm_backlight_capsh]jE)}(hjh]hamdgpu_dm_backlight_caps}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhKubah}(h]j{ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhKhj}hhubjs)}(hhh]h)}(hInformation about backlighth]hInformation about backlight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jrhj}hhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhhhj hNubj)}(hX,**Definition**:: struct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; **Members** ``ext_caps`` Keep the data struct with all the information about the display support for HDR. ``aux_min_input_signal`` Min brightness value supported by the display ``aux_max_input_signal`` Max brightness value supported by the display in nits. ``min_input_signal`` minimum possible input in range 0-255. ``max_input_signal`` maximum possible input in range 0-255. ``caps_valid`` true if these values are from the ACPI interface. ``aux_support`` Describes if the display supports AUX backlight. ``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. ``ac_level`` the default brightness if booted on AC ``dc_level`` the default brightness if booted on DC ``data_points`` the number of custom luminance data points ``luminance_data`` custom luminance datah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };h]hXstruct amdgpu_dm_backlight_caps { union dpcd_sink_ext_caps *ext_caps; u32 aux_min_input_signal; u32 aux_max_input_signal; int min_input_signal; int max_input_signal; bool caps_valid; bool aux_support; u32 brightness_mask; u8 ac_level; u8 dc_level; u8 data_points; struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj)}(hhh](j)}(h^``ext_caps`` Keep the data struct with all the information about the display support for HDR. h](j)}(h ``ext_caps``h]j)}(hj7h]hext_caps}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj1ubj )}(hhh]h)}(hPKeep the data struct with all the information about the display support for HDR.h]hPKeep the data struct with all the information about the display support for HDR.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjMubah}(h]h ]h"]h$]h&]uh1j hj1ubeh}(h]h ]h"]h$]h&]uh1jhjLhKhj.ubj)}(hG``aux_min_input_signal`` Min brightness value supported by the display h](j)}(h``aux_min_input_signal``h]j)}(hjqh]haux_min_input_signal}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjkubj )}(hhh]h)}(h-Min brightness value supported by the displayh]h-Min brightness value supported by the display}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjkubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(hP``aux_max_input_signal`` Max brightness value supported by the display in nits. h](j)}(h``aux_max_input_signal``h]j)}(hjh]haux_max_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h6Max brightness value supported by the display in nits.h]h6Max brightness value supported by the display in nits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h<``min_input_signal`` minimum possible input in range 0-255. h](j)}(h``min_input_signal``h]j)}(hjh]hmin_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h&minimum possible input in range 0-255.h]h&minimum possible input in range 0-255.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h<``max_input_signal`` maximum possible input in range 0-255. h](j)}(h``max_input_signal``h]j)}(hjh]hmax_input_signal}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h&maximum possible input in range 0-255.h]h&maximum possible input in range 0-255.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hKhj3ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj2hKhj.ubj)}(hA``caps_valid`` true if these values are from the ACPI interface. h](j)}(h``caps_valid``h]j)}(hjVh]h caps_valid}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjPubj )}(hhh]h)}(h1true if these values are from the ACPI interface.h]h1true if these values are from the ACPI interface.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjlubah}(h]h ]h"]h$]h&]uh1j hjPubeh}(h]h ]h"]h$]h&]uh1jhjkhKhj.ubj)}(hA``aux_support`` Describes if the display supports AUX backlight. h](j)}(h``aux_support``h]j)}(hjh]h aux_support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h0Describes if the display supports AUX backlight.h]h0Describes if the display supports AUX backlight.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h``brightness_mask`` After deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values. h](j)}(h``brightness_mask``h]j)}(hjh]hbrightness_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.h]hrAfter deriving brightness, OR it with this mask. Workaround for panels with issues with certain brightness values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h4``ac_level`` the default brightness if booted on AC h](j)}(h ``ac_level``h]j)}(hjh]hac_level}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(h&the default brightness if booted on ACh]h&the default brightness if booted on AC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h4``dc_level`` the default brightness if booted on DC h](j)}(h ``dc_level``h]j)}(hj;h]hdc_level}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhj5ubj )}(hhh]h)}(h&the default brightness if booted on DCh]h&the default brightness if booted on DC}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhKhjQubah}(h]h ]h"]h$]h&]uh1j hj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhKhj.ubj)}(h;``data_points`` the number of custom luminance data points h](j)}(h``data_points``h]j)}(hjth]h data_points}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjnubj )}(hhh]h)}(h*the number of custom luminance data pointsh]h*the number of custom luminance data points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjnubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubj)}(h(``luminance_data`` custom luminance datah](j)}(h``luminance_data``h]j)}(hjh]hluminance_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubj )}(hhh]h)}(hcustom luminance datah]hcustom luminance data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubh)}(h3Describe the backlight support for ACPI or eDP AUX.h]h3Describe the backlight support for ACPI or eDP AUX.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKhhhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdal_allocation (C struct)c.dal_allocationhNtauh1jhhhhhj hNubj )}(hhh](j)}(hdal_allocationh]j)}(hstruct dal_allocationh](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj*hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhKubj.)}(h h]h }(hj<hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj*hhhj;hKubj?)}(hdal_allocationh]jE)}(hj(h]hdal_allocation}(hjNhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjJubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj*hhhj;hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj&hhhj;hKubah}(h]j!ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj;hKhj#hhubjs)}(hhh]h)}(h-Tracks mapped FB memory for SMU communicationh]h-Tracks mapped FB memory for SMU communication}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjmhhubah}(h]h ]h"]h$]h&]uh1jrhj#hhhj;hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhhhj hNubj)}(hXX**Definition**:: struct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; }; **Members** ``list`` list of dal allocations ``bo`` GPU buffer object ``cpu_ptr`` CPU virtual address of the GPU buffer object ``gpu_addr`` GPU virtual address of the GPU buffer objecth](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };h]htstruct dal_allocation { struct list_head list; struct amdgpu_bo *bo; void *cpu_ptr; u64 gpu_addr; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](j)}(h!``list`` list of dal allocations h](j)}(h``list``h]j)}(hjh]hlist}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$],h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hlist of dal allocationsh]hlist of dal allocations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``bo`` GPU buffer object h](j)}(h``bo``h]j)}(hjh]hbo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hGPU buffer objecth]hGPU buffer object}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hMhj,ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj+hMhjubj)}(h9``cpu_ptr`` CPU virtual address of the GPU buffer object h](j)}(h ``cpu_ptr``h]j)}(hjOh]hcpu_ptr}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjIubj )}(hhh]h)}(h,CPU virtual address of the GPU buffer objecth]h,CPU virtual address of the GPU buffer object}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubah}(h]h ]h"]h$]h&]uh1j hjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjubj)}(h9``gpu_addr`` GPU virtual address of the GPU buffer objecth](j)}(h ``gpu_addr``h]j)}(hjh]hgpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h,GPU virtual address of the GPU buffer objecth]h,GPU virtual address of the GPU buffer object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(hpd_rx_irq_offload_work_queue (C struct)c.hpd_rx_irq_offload_work_queuehNtauh1jhhhhhj hNubj )}(hhh](j)}(hhpd_rx_irq_offload_work_queueh]j)}(h$struct hpd_rx_irq_offload_work_queueh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM ubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhM ubj?)}(hhpd_rx_irq_offload_work_queueh]jE)}(hjh]hhpd_rx_irq_offload_work_queue}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhM ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhM ubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhM hjhhubjs)}(hhh]h)}(h,Work queue to handle hpd_rx_irq offload workh]h,Work queue to handle hpd_rx_irq offload work}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj!hhubah}(h]h ]h"]h$]h&]uh1jrhjhhhjhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj<jj<jjjuh1j hhhhhj hNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; }; **Members** ``wq`` workqueue structure to queue offload work. ``offload_lock`` To protect fields of offload work queue. ``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss ``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event ``aconnector`` The aconnector that this work queue is attached toh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubh:}(hjDhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj@ubj)}(hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };h]hstruct hpd_rx_irq_offload_work_queue { struct workqueue_struct *wq; spinlock_t offload_lock; bool is_handling_link_loss; bool is_handling_mst_msg_rdy_event; struct amdgpu_dm_connector *aconnector; };}hjasbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj@ubh)}(h **Members**h]j)}(hjrh]hMembers}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj@ubj)}(hhh](j)}(h2``wq`` workqueue structure to queue offload work. h](j)}(h``wq``h]j)}(hjh]hwq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h*workqueue structure to queue offload work.h]h*workqueue structure to queue offload work.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``offload_lock`` To protect fields of offload work queue. h](j)}(h``offload_lock``h]j)}(hjh]h offload_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h(To protect fields of offload work queue.h]h(To protect fields of offload work queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hb``is_handling_link_loss`` Used to prevent inserting link loss event when we're handling link loss h](j)}(h``is_handling_link_loss``h]j)}(hjh]his_handling_link_loss}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hGUsed to prevent inserting link loss event when we're handling link lossh]hIUsed to prevent inserting link loss event when we’re handling link loss}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``is_handling_mst_msg_rdy_event`` Used to prevent inserting mst message ready event when we're already handling mst message ready event h](j)}(h!``is_handling_mst_msg_rdy_event``h]j)}(hj=h]his_handling_mst_msg_rdy_event}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM#hj7ubj )}(hhh]h)}(heUsed to prevent inserting mst message ready event when we're already handling mst message ready eventh]hgUsed to prevent inserting mst message ready event when we’re already handling mst message ready event}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM"hjSubah}(h]h ]h"]h$]h&]uh1j hj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhM#hjubj)}(hA``aconnector`` The aconnector that this work queue is attached toh](j)}(h``aconnector``h]j)}(hjwh]h aconnector}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM&hjqubj )}(hhh]h)}(h2The aconnector that this work queue is attached toh]h2The aconnector that this work queue is attached to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM'hjubah}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ]h"]h$]h&]uh1jhjhM&hjubeh}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"hpd_rx_irq_offload_work (C struct)c.hpd_rx_irq_offload_workhNtauh1jhhhhhj hNubj )}(hhh](j)}(hhpd_rx_irq_offload_workh]j)}(hstruct hpd_rx_irq_offload_workh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM-ubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhM-ubj?)}(hhpd_rx_irq_offload_workh]jE)}(hjh]hhpd_rx_irq_offload_work}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhM-ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhM-ubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhM-hjhhubjs)}(hhh]h)}(h!hpd_rx_irq offload work structureh]h!hpd_rx_irq offload work structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM,hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhjhM-ubeh}(h]h ](jstructeh"]h$]h&]jjjj+jj+jjjuh1j hhhhhj hNubj)}(hX**Definition**:: struct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; }; **Members** ``work`` offload work ``data`` reference irq data which is used while handling offload work ``offload_wq`` offload work queue that this work is queued to ``adev`` amdgpu_device pointerh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh:}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM0hj/ubj)}(hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };h]hstruct hpd_rx_irq_offload_work { struct work_struct work; union hpd_irq_data data; struct hpd_rx_irq_offload_work_queue *offload_wq; struct amdgpu_device *adev; };}hjPsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM2hj/ubh)}(h **Members**h]j)}(hjah]hMembers}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM9hj/ubj)}(hhh](j)}(h``work`` offload work h](j)}(h``work``h]j)}(hjh]hwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM1hjzubj )}(hhh]h)}(h offload workh]h offload work}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM1hjubah}(h]h ]h"]h$]h&]uh1j hjzubeh}(h]h ]h"]h$]h&]uh1jhjhM1hjwubj)}(hF``data`` reference irq data which is used while handling offload work h](j)}(h``data``h]j)}(hjh]hdata}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM5hjubj )}(hhh]h)}(h``offload_wq`` offload work queue that this work is queued to h](j)}(h``offload_wq``h]j)}(hjh]h offload_wq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM9hjubj )}(hhh]h)}(h.offload work queue that this work is queued toh]h.offload work queue that this work is queued to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM9hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjwubj)}(h``adev`` amdgpu_device pointerh](j)}(h``adev``h]j)}(hj+h]hadev}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM<hj%ubj )}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM=hjAubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1jhj@hM<hjwubeh}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!amdgpu_display_manager (C struct)c.amdgpu_display_managerhNtauh1jhhhhhj hNubj )}(hhh](j)}(hamdgpu_display_managerh]j)}(hstruct amdgpu_display_managerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMCubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhMCubj?)}(hamdgpu_display_managerh]jE)}(hjh]hamdgpu_display_manager}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhMCubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj}hhhjhMCubah}(h]jxah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhMChjzhhubjs)}(hhh]h)}(h%Central amdgpu display manager deviceh]h%Central amdgpu display manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMBhjhhubah}(h]h ]h"]h$]h&]uh1jrhjzhhhjhMCubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhhhj hNubj)}(hX **Definition**:: struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct dm_boot_time_crc_info boot_time_crc_info; }; **Members** ``dc`` Display Core control structure ``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. ``dmub_notify`` Notification from DMUB. ``dmub_callback`` Callback functions to handle notification from DMUB. ``dmub_thread_offload`` Flag to indicate if callback is offload. ``dmub_fb_info`` Framebuffer regions for the DMUB. ``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. ``dmub_bo`` Buffer object for the DMUB. ``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. ``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. ``dmcub_fw_version`` DMCUB firmware version. ``fw_inst_size`` Size of the firmware instruction buffer. ``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. ``adev`` AMDGPU base driver structure ``ddev`` DRM base driver structure ``display_indexes_num`` Max number of display streams supported ``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. ``dc_lock`` Guards access to DC functions that can issue register write sequences. ``audio_lock`` Guards access to audio instance changes. ``audio_component`` Used to notify ELD changes to sound driver. ``audio_registered`` True if the audio component has been registered successfully, false otherwise. ``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). ``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. ``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. ``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. ``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. ``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. ``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. ``dmub_outbox_params`` DMUB Outbox parameters ``irq_handler_list_table_lock`` Synchronizes access to IRQ tables ``backlight_dev`` Backlight control device ``backlight_link`` Link on which to control backlight ``num_of_edps`` number of backlight eDPs ``backlight_caps`` Capabilities of the backlight device ``freesync_module`` Module handling freesync calculations ``hdcp_workqueue`` AMDGPU content protection queue ``vblank_control_workqueue`` Deferred work for vblank control events. ``idle_workqueue`` Periodic work for idle events. ``cached_state`` Caches device atomic state for suspend/resume ``cached_dc_state`` Cached state of content streams ``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` ``fw_dmcu`` Reference to DMCU firmware ``dmcu_fw_version`` Version of the DMCU firmware ``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW ``active_vblank_irq_count`` number of currently active vblank irqs ``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. ``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq ``mst_encoders`` fake encoders used for DP MST. ``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. ``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true ``dmcub_trace_event_en`` enable dmcub trace events ``da_list`` DAL fb memory allocation list, for communication with SMU. ``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done ``delayed_hpd_wq`` work queue used to delay DMUB HPD work ``brightness`` cached backlight values. ``actual_brightness`` last successfully applied backlight values. ``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform ``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. ``dpia_aux_lock`` Guards access to DPIA AUX ``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct ``oem_i2c`` OEM i2c bus ``fused_io`` dmub fused io interfaceh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjubj)}(hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct dm_boot_time_crc_info boot_time_crc_info; };h]hX struct amdgpu_display_manager { struct dc *dc; struct dmub_srv *dmub_srv; struct dmub_notification *dmub_notify; dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; struct dmub_srv_fb_info *dmub_fb_info; const struct firmware *dmub_fw; struct amdgpu_bo *dmub_bo; u64 dmub_bo_gpu_addr; void *dmub_bo_cpu_addr; uint32_t dmcub_fw_version; uint32_t fw_inst_size; struct cgs_device *cgs_device; struct amdgpu_device *adev; struct drm_device *ddev; u16 display_indexes_num; struct drm_private_obj atomic_obj; struct mutex dc_lock; struct mutex audio_lock; struct drm_audio_component *audio_component; bool audio_registered; struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; struct common_irq_params pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; struct common_irq_params vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; struct common_irq_params dmub_trace_params[1]; struct common_irq_params dmub_outbox_params[1]; spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; uint8_t num_of_edps; struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; struct mod_freesync *freesync_module; struct hdcp_workqueue *hdcp_workqueue; struct workqueue_struct *vblank_control_workqueue; struct idle_workqueue *idle_workqueue; struct drm_atomic_state *cached_state; struct dc_state *cached_dc_state; struct dm_compressor_info compressor; const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; uint32_t active_vblank_irq_count; #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY); struct secure_display_context secure_display_ctx; #endif; struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; bool force_timing_sync; bool disable_hpd_irq; bool dmcub_trace_event_en; struct list_head da_list; struct completion dmub_aux_transfer_done; struct workqueue_struct *delayed_hpd_wq; u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; bool aux_hpd_discon_quirk; bool edp0_on_dp1_quirk; struct mutex dpia_aux_lock; void *bb_from_dmub; struct amdgpu_i2c_adapter *oem_i2c; struct fused_io_sync { struct completion replied; char reply_data[0x40]; } fused_io[8]; struct dm_boot_time_crc_info boot_time_crc_info; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMHhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj)}(hhh](j)}(h&``dc`` Display Core control structure h](j)}(h``dc``h]j)}(hj4h]hdc}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMEhj.ubj )}(hhh]h)}(hDisplay Core control structureh]hDisplay Core control structure}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhMEhjJubah}(h]h ]h"]h$]h&]uh1j hj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMEhj+ubj)}(h``dmub_srv`` DMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it. h](j)}(h ``dmub_srv``h]j)}(hjmh]hdmub_srv}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMghjgubj )}(hhh]h)}(hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.h]hDMUB service, used for controlling the DMUB on hardware that supports it. The pointer to the dmub_srv will be NULL on hardware that does not support it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMehjubah}(h]h ]h"]h$]h&]uh1j hjgubeh}(h]h ]h"]h$]h&]uh1jhjhMghj+ubj)}(h(``dmub_notify`` Notification from DMUB. h](j)}(h``dmub_notify``h]j)}(hjh]h dmub_notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMnhjubj )}(hhh]h)}(hNotification from DMUB.h]hNotification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMnhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMnhj+ubj)}(hG``dmub_callback`` Callback functions to handle notification from DMUB. h](j)}(h``dmub_callback``h]j)}(hjh]h dmub_callback}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMvhjubj )}(hhh]h)}(h4Callback functions to handle notification from DMUB.h]h4Callback functions to handle notification from DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMvhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMvhj+ubj)}(hA``dmub_thread_offload`` Flag to indicate if callback is offload. h](j)}(h``dmub_thread_offload``h]j)}(hjh]hdmub_thread_offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM~hjubj )}(hhh]h)}(h(Flag to indicate if callback is offload.h]h(Flag to indicate if callback is offload.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hM~hj/ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj.hM~hj+ubj)}(h3``dmub_fb_info`` Framebuffer regions for the DMUB. h](j)}(h``dmub_fb_info``h]j)}(hjRh]h dmub_fb_info}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjLubj )}(hhh]h)}(h!Framebuffer regions for the DMUB.h]h!Framebuffer regions for the DMUB.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghMhjhubah}(h]h ]h"]h$]h&]uh1j hjLubeh}(h]h ]h"]h$]h&]uh1jhjghMhj+ubj)}(hG``dmub_fw`` DMUB firmware, required on hardware that has DMUB support. h](j)}(h ``dmub_fw``h]j)}(hjh]hdmub_fw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h:DMUB firmware, required on hardware that has DMUB support.h]h:DMUB firmware, required on hardware that has DMUB support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h(``dmub_bo`` Buffer object for the DMUB. h](j)}(h ``dmub_bo``h]j)}(hjh]hdmub_bo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hBuffer object for the DMUB.h]hBuffer object for the DMUB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hE``dmub_bo_gpu_addr`` GPU virtual address for the DMUB buffer object. h](j)}(h``dmub_bo_gpu_addr``h]j)}(hjh]hdmub_bo_gpu_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h/GPU virtual address for the DMUB buffer object.h]h/GPU virtual address for the DMUB buffer object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h=``dmub_bo_cpu_addr`` CPU address for the DMUB buffer object. h](j)}(h``dmub_bo_cpu_addr``h]j)}(hj6h]hdmub_bo_cpu_addr}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj0ubj )}(hhh]h)}(h'CPU address for the DMUB buffer object.h]h'CPU address for the DMUB buffer object.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjLubah}(h]h ]h"]h$]h&]uh1j hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhj+ubj)}(h-``dmcub_fw_version`` DMCUB firmware version. h](j)}(h``dmcub_fw_version``h]j)}(hjoh]hdmcub_fw_version}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjiubj )}(hhh]h)}(hDMCUB firmware version.h]hDMCUB firmware version.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjiubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h:``fw_inst_size`` Size of the firmware instruction buffer. h](j)}(h``fw_inst_size``h]j)}(hjh]h fw_inst_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h(Size of the firmware instruction buffer.h]h(Size of the firmware instruction buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hf``cgs_device`` The Common Graphics Services device. It provides an interface for accessing registers. h](j)}(h``cgs_device``h]j)}(hjh]h cgs_device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hVThe Common Graphics Services device. It provides an interface for accessing registers.h]hVThe Common Graphics Services device. It provides an interface for accessing registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h&``adev`` AMDGPU base driver structure h](j)}(h``adev``h]j)}(hjh]hadev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhjubj )}(hhh]h)}(hAMDGPU base driver structureh]hAMDGPU base driver structure}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMFhj1ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj0hMFhj+ubj)}(h#``ddev`` DRM base driver structure h](j)}(h``ddev``h]j)}(hjTh]hddev}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMGhjNubj )}(hhh]h)}(hDRM base driver structureh]hDRM base driver structure}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihMGhjjubah}(h]h ]h"]h$]h&]uh1j hjNubeh}(h]h ]h"]h$]h&]uh1jhjihMGhj+ubj)}(h@``display_indexes_num`` Max number of display streams supported h](j)}(h``display_indexes_num``h]j)}(hjh]hdisplay_indexes_num}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMHhjubj )}(hhh]h)}(h'Max number of display streams supportedh]h'Max number of display streams supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMHhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMHhj+ubj)}(h``atomic_obj`` In combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`. h](j)}(h``atomic_obj``h]j)}(hjh]h atomic_obj}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hIn combination with :c:type:`dm_atomic_state` it helps manage global atomic state that doesn't map cleanly into existing drm resources, like :c:type:`dc_context`.h](hIn combination with }(hjhhhNhNubh)}(h:c:type:`dm_atomic_state`h]j)}(hjh]hdm_atomic_state}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarn c:parent_keysphinx.domains.c LookupKey)}data]sbjdm_atomic_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhb it helps manage global atomic state that doesn’t map cleanly into existing drm resources, like }(hjhhhNhNubh)}(h:c:type:`dc_context`h]j)}(hjh]h dc_context}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j dc_contextuh1hhjhMhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hS``dc_lock`` Guards access to DC functions that can issue register write sequences. h](j)}(h ``dc_lock``h]j)}(hjNh]hdc_lock}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjHubj )}(hhh]h)}(hFGuards access to DC functions that can issue register write sequences.h]hFGuards access to DC functions that can issue register write sequences.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjdubah}(h]h ]h"]h$]h&]uh1j hjHubeh}(h]h ]h"]h$]h&]uh1jhjchMhj+ubj)}(h8``audio_lock`` Guards access to audio instance changes. h](j)}(h``audio_lock``h]j)}(hjh]h audio_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h(Guards access to audio instance changes.h]h(Guards access to audio instance changes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(h@``audio_component`` Used to notify ELD changes to sound driver. h](j)}(h``audio_component``h]j)}(hjh]haudio_component}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(h+Used to notify ELD changes to sound driver.h]h+Used to notify ELD changes to sound driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hd``audio_registered`` True if the audio component has been registered successfully, false otherwise. h](j)}(h``audio_registered``h]j)}(hjh]haudio_registered}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hNTrue if the audio component has been registered successfully, false otherwise.h]hNTrue if the audio component has been registered successfully, false otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hX;``irq_handler_list_low_tab`` Low priority IRQ handler table. It is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep. Note that handlers are called in the same order as they were registered (FIFO). h](j)}(h``irq_handler_list_low_tab``h]j)}(hj4h]hirq_handler_list_low_tab}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj.ubj )}(hhh](h)}(hLow priority IRQ handler table.h]hLow priority IRQ handler table.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjJubh)}(hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.h]hIt is a n*m table consisting of n IRQ sources, and m handlers per IRQ source. Low priority IRQ handlers are deferred to a workqueue to be processed. Hence, they can sleep.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjJubh)}(hONote that handlers are called in the same order as they were registered (FIFO).h]hONote that handlers are called in the same order as they were registered (FIFO).}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjJubeh}(h]h ]h"]h$]h&]uh1j hj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhj+ubj)}(h``irq_handler_list_high_tab`` High priority IRQ handler table. It is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately. h](j)}(h``irq_handler_list_high_tab``h]j)}(hjh]hirq_handler_list_high_tab}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh](h)}(h High priority IRQ handler table.h]h High priority IRQ handler table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubh)}(hIt is a n*m table, same as :c:type:`irq_handler_list_low_tab`. However, handlers in this table are not deferred and are called immediately.h](hIt is a n*m table, same as }(hjhhhNhNubh)}(h":c:type:`irq_handler_list_low_tab`h]j)}(hjh]hirq_handler_list_low_tab}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jirq_handler_list_low_tabuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubhN. However, handlers in this table are not deferred and are called immediately.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(hY``pflip_params`` Page flip IRQ parameters, passed to registered handlers when triggered. h](j)}(h``pflip_params``h]j)}(hjh]h pflip_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hGPage flip IRQ parameters, passed to registered handlers when triggered.h]hGPage flip IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj hMhj+ubj)}(hb``vblank_params`` Vertical blanking IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vblank_params``h]j)}(hj2h]h vblank_params}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hj,ubj )}(hhh]h)}(hOVertical blanking IRQ parameters, passed to registered handlers when triggered.h]hOVertical blanking IRQ parameters, passed to registered handlers when triggered.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM hjHubah}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhM hj+ubj)}(hh``vline0_params`` OTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vline0_params``h]j)}(hjlh]h vline0_params}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjfubj )}(hhh]h)}(hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.h]hUOTG vertical interrupt0 IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjfubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(ha``vupdate_params`` Vertical update IRQ parameters, passed to registered handlers when triggered. h](j)}(h``vupdate_params``h]j)}(hjh]hvupdate_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubj )}(hhh]h)}(hMVertical update IRQ parameters, passed to registered handlers when triggered.h]hMVertical update IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj+ubj)}(he``dmub_trace_params`` DMUB trace event IRQ parameters, passed to registered handlers when triggered. h](j)}(h``dmub_trace_params``h]j)}(hjh]hdmub_trace_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM'hjubj )}(hhh]h)}(hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.h]hNDMUB trace event IRQ parameters, passed to registered handlers when triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM&hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhM'hj+ubj)}(h.``dmub_outbox_params`` DMUB Outbox parameters h](j)}(h``dmub_outbox_params``h]j)}(hjh]hdmub_outbox_params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMXhjubj )}(hhh]h)}(hDMUB Outbox parametersh]hDMUB Outbox parameters}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMXhj0ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj/hMXhj+ubj)}(hB``irq_handler_list_table_lock`` Synchronizes access to IRQ tables h](j)}(h``irq_handler_list_table_lock``h]j)}(hjSh]hirq_handler_list_table_lock}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMIhjMubj )}(hhh]h)}(h!Synchronizes access to IRQ tablesh]h!Synchronizes access to IRQ tables}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMIhjiubah}(h]h ]h"]h$]h&]uh1j hjMubeh}(h]h ]h"]h$]h&]uh1jhjhhMIhj+ubj)}(h+``backlight_dev`` Backlight control device h](j)}(h``backlight_dev``h]j)}(hjh]h backlight_dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMJhjubj )}(hhh]h)}(hBacklight control deviceh]hBacklight control device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMJhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMJhj+ubj)}(h6``backlight_link`` Link on which to control backlight h](j)}(h``backlight_link``h]j)}(hjh]hbacklight_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMKhjubj )}(hhh]h)}(h"Link on which to control backlighth]h"Link on which to control backlight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMKhj+ubj)}(h)``num_of_edps`` number of backlight eDPs h](j)}(h``num_of_edps``h]j)}(hjh]h num_of_edps}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMYhjubj )}(hhh]h)}(hnumber of backlight eDPsh]hnumber of backlight eDPs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMYhj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj hMYhj+ubj)}(h8``backlight_caps`` Capabilities of the backlight device h](j)}(h``backlight_caps``h]j)}(hj7 h]hbacklight_caps}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5 ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMLhj1 ubj )}(hhh]h)}(h$Capabilities of the backlight deviceh]h$Capabilities of the backlight device}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL hMLhjM ubah}(h]h ]h"]h$]h&]uh1j hj1 ubeh}(h]h ]h"]h$]h&]uh1jhjL hMLhj+ubj)}(h:``freesync_module`` Module handling freesync calculations h](j)}(h``freesync_module``h]j)}(hjp h]hfreesync_module}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMMhjj ubj )}(hhh]h)}(h%Module handling freesync calculationsh]h%Module handling freesync calculations}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMMhj ubah}(h]h ]h"]h$]h&]uh1j hjj ubeh}(h]h ]h"]h$]h&]uh1jhj hMMhj+ubj)}(h3``hdcp_workqueue`` AMDGPU content protection queue h](j)}(h``hdcp_workqueue``h]j)}(hj h]hhdcp_workqueue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMNhj ubj )}(hhh]h)}(hAMDGPU content protection queueh]hAMDGPU content protection queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMNhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hMNhj+ubj)}(hF``vblank_control_workqueue`` Deferred work for vblank control events. h](j)}(h``vblank_control_workqueue``h]j)}(hj h]hvblank_control_workqueue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM?hj ubj )}(hhh]h)}(h(Deferred work for vblank control events.h]h(Deferred work for vblank control events. }(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM?hj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj hM?hj+ubj)}(h2``idle_workqueue`` Periodic work for idle events. h](j)}(h``idle_workqueue``h]j)}(hj!h]hidle_workqueue}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMFhj!ubj )}(hhh]h)}(hPeriodic work for idle events.h]hPeriodic work for idle events.}(hj4!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0!hMFhj1!ubah}(h]h ]h"]h$]h&]uh1j hj!ubeh}(h]h ]h"]h$]h&]uh1jhj0!hMFhj+ubj)}(h?``cached_state`` Caches device atomic state for suspend/resume h](j)}(h``cached_state``h]j)}(hjT!h]h cached_state}(hjV!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMRhjN!ubj )}(hhh]h)}(h-Caches device atomic state for suspend/resumeh]h-Caches device atomic state for suspend/resume}(hjm!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji!hMRhjj!ubah}(h]h ]h"]h$]h&]uh1j hjN!ubeh}(h]h ]h"]h$]h&]uh1jhji!hMRhj+ubj)}(h4``cached_dc_state`` Cached state of content streams h](j)}(h``cached_dc_state``h]j)}(hj!h]hcached_dc_state}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMShj!ubj )}(hhh]h)}(hCached state of content streamsh]hCached state of content streams}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMShj!ubah}(h]h ]h"]h$]h&]uh1j hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMShj+ubj)}(hm``compressor`` Frame buffer compression buffer. See :c:type:`struct dm_compressor_info ` h](j)}(h``compressor``h]j)}(hj!h]h compressor}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMThj!ubj )}(hhh]h)}(h]Frame buffer compression buffer. See :c:type:`struct dm_compressor_info `h](h%Frame buffer compression buffer. See }(hj!hhhNhNubh)}(h8:c:type:`struct dm_compressor_info `h]j)}(hj!h]hstruct dm_compressor_info}(hj!hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdm_compressor_infouh1hhj!hMThj!ubeh}(h]h ]h"]h$]h&]uh1hhj!hMThj!ubah}(h]h ]h"]h$]h&]uh1j hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMThj+ubj)}(h'``fw_dmcu`` Reference to DMCU firmware h](j)}(h ``fw_dmcu``h]j)}(hj"h]hfw_dmcu}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMOhj"ubj )}(hhh]h)}(hReference to DMCU firmwareh]hReference to DMCU firmware}(hj7"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3"hMOhj4"ubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1jhj3"hMOhj+ubj)}(h1``dmcu_fw_version`` Version of the DMCU firmware h](j)}(h``dmcu_fw_version``h]j)}(hjW"h]hdmcu_fw_version}(hjY"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMPhjQ"ubj )}(hhh]h)}(hVersion of the DMCU firmwareh]hVersion of the DMCU firmware}(hjp"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl"hMPhjm"ubah}(h]h ]h"]h$]h&]uh1j hjQ"ubeh}(h]h ]h"]h$]h&]uh1jhjl"hMPhj+ubj)}(h^``soc_bounding_box`` gpu_info FW provided soc bounding box struct or 0 if not available in FW h](j)}(h``soc_bounding_box``h]j)}(hj"h]hsoc_bounding_box}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMUhj"ubj )}(hhh]h)}(hHgpu_info FW provided soc bounding box struct or 0 if not available in FWh]hHgpu_info FW provided soc bounding box struct or 0 if not available in FW}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMThj"ubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMUhj+ubj)}(hC``active_vblank_irq_count`` number of currently active vblank irqs h](j)}(h``active_vblank_irq_count``h]j)}(hj"h]hactive_vblank_irq_count}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM\hj"ubj )}(hhh]h)}(h&number of currently active vblank irqsh]h&number of currently active vblank irqs}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hM\hj"ubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM\hj+ubj)}(h|``secure_display_ctx`` Store secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc. h](j)}(h``secure_display_ctx``h]j)}(hj#h]hsecure_display_ctx}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMehj"ubj )}(hhh]h)}(hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.h]hdStore secure display relevant info. e.g. the ROI information , the work_struct to command dmub, etc.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMdhj#ubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1jhj#hMehj+ubj)}(h@``hpd_rx_offload_wq`` Work queue to offload works of hpd_rx_irq h](j)}(h``hpd_rx_offload_wq``h]j)}(hj=#h]hhpd_rx_offload_wq}(hj?#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMlhj7#ubj )}(hhh]h)}(h)Work queue to offload works of hpd_rx_irqh]h)Work queue to offload works of hpd_rx_irq}(hjV#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR#hMlhjS#ubah}(h]h ]h"]h$]h&]uh1j hj7#ubeh}(h]h ]h"]h$]h&]uh1jhjR#hMlhj+ubj)}(h0``mst_encoders`` fake encoders used for DP MST. h](j)}(h``mst_encoders``h]j)}(hjv#h]h mst_encoders}(hjx#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMrhjp#ubj )}(hhh]h)}(hfake encoders used for DP MST.h]hfake encoders used for DP MST.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hMrhj#ubah}(h]h ]h"]h$]h&]uh1j hjp#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMrhj+ubj)}(hv``force_timing_sync`` set via debugfs. When set, indicates that all connected displays will be forced to synchronize. h](j)}(h``force_timing_sync``h]j)}(hj#h]hforce_timing_sync}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMVhj#ubj )}(hhh]h)}(h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.h]h_set via debugfs. When set, indicates that all connected displays will be forced to synchronize.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMUhj#ubah}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMVhj+ubj)}(h[``disable_hpd_irq`` disables all HPD and HPD RX interrupt handling in the driver when true h](j)}(h``disable_hpd_irq``h]j)}(hj#h]hdisable_hpd_irq}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM[hj#ubj )}(hhh]h)}(hFdisables all HPD and HPD RX interrupt handling in the driver when trueh]hFdisables all HPD and HPD RX interrupt handling in the driver when true}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMZhj#ubah}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hM[hj+ubj)}(h3``dmcub_trace_event_en`` enable dmcub trace events h](j)}(h``dmcub_trace_event_en``h]j)}(hj#$h]hdmcub_trace_event_en}(hj%$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMWhj$ubj )}(hhh]h)}(henable dmcub trace eventsh]henable dmcub trace events}(hj<$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8$hMWhj9$ubah}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ]h"]h$]h&]uh1jhj8$hMWhj+ubj)}(hG``da_list`` DAL fb memory allocation list, for communication with SMU. h](j)}(h ``da_list``h]j)}(hj\$h]hda_list}(hj^$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM{hjV$ubj )}(hhh]h)}(h:DAL fb memory allocation list, for communication with SMU.h]h:DAL fb memory allocation list, for communication with SMU.}(hju$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq$hM{hjr$ubah}(h]h ]h"]h$]h&]uh1j hjV$ubeh}(h]h ]h"]h$]h&]uh1jhjq$hM{hj+ubj)}(h[``dmub_aux_transfer_done`` struct completion used to indicate when DMUB transfers are done h](j)}(h``dmub_aux_transfer_done``h]j)}(hj$h]hdmub_aux_transfer_done}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM]hj$ubj )}(hhh]h)}(h?struct completion used to indicate when DMUB transfers are doneh]h?struct completion used to indicate when DMUB transfers are done}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM\hj$ubah}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM]hj+ubj)}(h:``delayed_hpd_wq`` work queue used to delay DMUB HPD work h](j)}(h``delayed_hpd_wq``h]j)}(hj$h]hdelayed_hpd_wq}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhM^hj$ubj )}(hhh]h)}(h&work queue used to delay DMUB HPD workh]h&work queue used to delay DMUB HPD work}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hM^hj$ubah}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM^hj+ubj)}(h(``brightness`` cached backlight values. h](j)}(h``brightness``h]j)}(hj%h]h brightness}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubj )}(hhh]h)}(hcached backlight values.h]hcached backlight values.}(hj!%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj%ubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhj+ubj)}(hB``actual_brightness`` last successfully applied backlight values. h](j)}(h``actual_brightness``h]j)}(hjA%h]hactual_brightness}(hjC%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj;%ubj )}(hhh]h)}(h+last successfully applied backlight values.h]h+last successfully applied backlight values.}(hjZ%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV%hMhjW%ubah}(h]h ]h"]h$]h&]uh1j hj;%ubeh}(h]h ]h"]h$]h&]uh1jhjV%hMhj+ubj)}(hh``aux_hpd_discon_quirk`` quirk for hpd discon while aux is on-going. occurred on certain intel platform h](j)}(h``aux_hpd_discon_quirk``h]j)}(hjz%h]haux_hpd_discon_quirk}(hj|%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjt%ubj )}(hhh]h)}(hNquirk for hpd discon while aux is on-going. occurred on certain intel platformh]hNquirk for hpd discon while aux is on-going. occurred on certain intel platform}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubah}(h]h ]h"]h$]h&]uh1j hjt%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhj+ubj)}(h@``edp0_on_dp1_quirk`` quirk for platforms that put edp0 on DP1. h](j)}(h``edp0_on_dp1_quirk``h]j)}(hj%h]hedp0_on_dp1_quirk}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubj )}(hhh]h)}(h)quirk for platforms that put edp0 on DP1.h]h)quirk for platforms that put edp0 on DP1.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hMhj%ubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hMhj+ubj)}(h,``dpia_aux_lock`` Guards access to DPIA AUX h](j)}(h``dpia_aux_lock``h]j)}(hj%h]h dpia_aux_lock}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj%ubj )}(hhh]h)}(hGuards access to DPIA AUXh]hGuards access to DPIA AUX}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hMhj&ubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhj+ubj)}(h``bb_from_dmub`` Bounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct h](j)}(h``bb_from_dmub``h]j)}(hj&&h]h bb_from_dmub}(hj(&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj &ubj )}(hhh]h)}(hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb structh]hBounding box data read from dmub during early initialization for DCN4+ Data is stored as a byte array that should be casted to the appropriate bb struct}(hj?&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj<&ubah}(h]h ]h"]h$]h&]uh1j hj &ubeh}(h]h ]h"]h$]h&]uh1jhj;&hMhj+ubj)}(h``oem_i2c`` OEM i2c bus h](j)}(h ``oem_i2c``h]j)}(hj`&h]hoem_i2c}(hjb&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjZ&ubj )}(hhh]h)}(h OEM i2c bush]h OEM i2c bus}(hjy&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju&hMhjv&ubah}(h]h ]h"]h$]h&]uh1j hjZ&ubeh}(h]h ]h"]h$]h&]uh1jhju&hMhj+ubj)}(h$``fused_io`` dmub fused io interfaceh](j)}(h ``fused_io``h]j)}(hj&h]hfused_io}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubj )}(hhh]h)}(hdmub fused io interfaceh]hdmub fused io interface}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj&ubah}(h]h ]h"]h$]h&]uh1j hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhj+ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j amdgpu_hdmi_vsdb_info (C struct)c.amdgpu_hdmi_vsdb_infohNtauh1jhhhhhj hNubj )}(hhh](j)}(hamdgpu_hdmi_vsdb_infoh]j)}(hstruct amdgpu_hdmi_vsdb_infoh](j)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj&hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMubj.)}(h h]h }(hj'hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj&hhhj'hMubj?)}(hamdgpu_hdmi_vsdb_infoh]jE)}(hj&h]hamdgpu_hdmi_vsdb_info}(hj'hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj'ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj&hhhj'hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj&hhhj'hMubah}(h]j&ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj'hMhj&hhubjs)}(hhh]h)}(hKeep track of the VSDB infoh]hKeep track of the VSDB info}(hj5'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj2'hhubah}(h]h ]h"]h$]h&]uh1jrhj&hhhj'hMubeh}(h]h ](jstructeh"]h$]h&]jjjjM'jjM'jjjuh1j hhhhhj hNubj)}(hX**Definition**:: struct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; }; **Members** ``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. ``freesync_supported`` FreeSync Supported. ``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. ``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz ``freesync_mccs_vcp_code`` MCCS VCP code for freesync state ``replay_mode`` Replay supportedh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjY'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU'ubh:}(hjU'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjQ'ubj)}(hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; };h]hstruct amdgpu_hdmi_vsdb_info { unsigned int amd_vsdb_version; bool freesync_supported; unsigned int min_refresh_rate_hz; unsigned int max_refresh_rate_hz; unsigned int freesync_mccs_vcp_code; bool replay_mode; };}hjr'sbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjQ'ubh)}(h **Members**h]j)}(hj'h]hMembers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjQ'ubj)}(hhh](j)}(h``amd_vsdb_version`` Vendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send. h](j)}(h``amd_vsdb_version``h]j)}(hj'h]hamd_vsdb_version}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj'ubj )}(hhh]h)}(hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.h]hoVendor Specific Data Block Version, should be used to determine which Vendor Specific InfoFrame (VSIF) to send.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj'ubah}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj'ubj)}(h+``freesync_supported`` FreeSync Supported. h](j)}(h``freesync_supported``h]j)}(hj'h]hfreesync_supported}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj'ubj )}(hhh]h)}(hFreeSync Supported.h]hFreeSync Supported.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj'ubj)}(h=``min_refresh_rate_hz`` FreeSync Minimum Refresh Rate in Hz. h](j)}(h``min_refresh_rate_hz``h]j)}(hj(h]hmin_refresh_rate_hz}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubj )}(hhh]h)}(h$FreeSync Minimum Refresh Rate in Hz.h]h$FreeSync Minimum Refresh Rate in Hz.}(hj.(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*(hMhj+(ubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhj*(hMhj'ubj)}(h<``max_refresh_rate_hz`` FreeSync Maximum Refresh Rate in Hz h](j)}(h``max_refresh_rate_hz``h]j)}(hjN(h]hmax_refresh_rate_hz}(hjP(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhjH(ubj )}(hhh]h)}(h#FreeSync Maximum Refresh Rate in Hzh]h#FreeSync Maximum Refresh Rate in Hz}(hjg(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc(hMhjd(ubah}(h]h ]h"]h$]h&]uh1j hjH(ubeh}(h]h ]h"]h$]h&]uh1jhjc(hMhj'ubj)}(h<``freesync_mccs_vcp_code`` MCCS VCP code for freesync state h](j)}(h``freesync_mccs_vcp_code``h]j)}(hj(h]hfreesync_mccs_vcp_code}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubj )}(hhh]h)}(h MCCS VCP code for freesync stateh]h MCCS VCP code for freesync state}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMhj(ubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhj'ubj)}(h ``replay_mode`` Replay supportedh](j)}(h``replay_mode``h]j)}(hj(h]h replay_mode}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubj )}(hhh]h)}(hReplay supportedh]hReplay supported}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhj(ubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhj'ubeh}(h]h ]h"]h$]h&]uh1jhjQ'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhj hNubh)}(h**Description**h]j)}(hj)h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhhhubh)}(hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.h]hAMDGPU supports FreeSync over HDMI by using the VSDB section, and this struct is useful to keep track of the display-specific information about FreeSync.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:11: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.hhMhhhhubh)}(hhh](h)}(h Lifecycleh]h Lifecycle}(hj+)hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj()hhhhhKubh)}(hDM (and consequently DC) is registered in the amdgpu base driver as a IP block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to the base driver's device list to be initialized and torn down accordingly.h]hDM (and consequently DC) is registered in the amdgpu base driver as a IP block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to the base driver’s device list to be initialized and torn down accordingly.}(hj9)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:17: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj()hhubh)}(h]The functions to do so are provided as hooks in :c:type:`struct amd_ip_funcs `.h](h0The functions to do so are provided as hooks in }(hjH)hhhNhNubh)}(h,:c:type:`struct amd_ip_funcs `h]j)}(hjR)h]hstruct amd_ip_funcs}(hjT)hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjP)ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j amd_ip_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:17: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjH)ubh.}(hjH)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjo)hMhj()hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_hw_init (C function) c.dm_hw_inithNtauh1jhj()hhhNhNubj )}(hhh](j)}(h1int dm_hw_init (struct amdgpu_ip_block *ip_block)h]j)}(h0int dm_hw_init(struct amdgpu_ip_block *ip_block)h](hdesc_sig_keyword_type)}(hinth]hint}(hj)hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j)hj)hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM ubj.)}(h h]h }(hj)hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj)hhhj)hM ubj?)}(h dm_hw_inith]jE)}(h dm_hw_inith]h dm_hw_init}(hj)hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj)ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj)hhhj)hM ubhdesc_parameterlist)}(h"(struct amdgpu_ip_block *ip_block)h]hdesc_parameter)}(h struct amdgpu_ip_block *ip_blockh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj)ubj.)}(h h]h }(hj)hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj)ubh)}(hhh]jE)}(hamdgpu_ip_blockh]hamdgpu_ip_block}(hj)hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj)ubah}(h]h ]h"]h$]h&] refdomainjreftype identifier reftargetj)modnameN classnameNjj)}j ]j ASTIdentifier)}j *j)sb c.dm_hw_initasbuh1hhj)ubj.)}(h h]h }(hj*hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj)ubhdesc_sig_punctuation)}(h*h]h*}(hj(*hhhNhNubah}(h]h ]pah"]h$]h&]uh1j&*hj)ubjE)}(hip_blockh]hip_block}(hj7*hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj)ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj)ubah}(h]h ]h"]h$]h&]j\j]uh1j)hj)hhhj)hM ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj)hhhj)hM ubah}(h]j)ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj)hM hj)hhubjs)}(hhh]h)}(hInitialize DC deviceh]hInitialize DC device}(hja*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj^*hhubah}(h]h ]h"]h$]h&]uh1jrhj)hhhj)hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjy*jjy*jjjuh1j hhhj()hNhNubj)}(hX**Parameters** ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. **Description** Initialize the :c:type:`struct amdgpu_display_manager ` device. This involves calling the initializers of each DM component, then populating the struct with them. Although the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item. Some notable things that are initialized here: - Display Core, both software and hardware - DC modules that we need (freesync and color management) - DRM software states - Interrupt sources and handlers - Vblank support - Debug FS entries, if enabledh](h)}(h**Parameters**h]j)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj}*ubj)}(hhh]j)}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](j)}(h$``struct amdgpu_ip_block *ip_block``h]j)}(hj*h]h struct amdgpu_ip_block *ip_block}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*ubj )}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hM hj*ubah}(h]h ]h"]h$]h&]uh1jhj}*ubh)}(h**Description**h]j)}(hj*h]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj}*ubh)}(hInitialize the :c:type:`struct amdgpu_display_manager ` device. This involves calling the initializers of each DM component, then populating the struct with them.h](hInitialize the }(hj*hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]j)}(hj*h]hstruct amdgpu_display_manager}(hj*hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj*ubhk device. This involves calling the initializers of each DM component, then populating the struct with them.}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj+hM hj}*ubh)}(hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.h]hAlthough the function implies hardware initialization, both hardware and software are initialized here. Splitting them out to their relevant init hooks is a future TODO item.}(hj%+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj}*ubh)}(h.Some notable things that are initialized here:h]h.Some notable things that are initialized here:}(hj4+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj}*ubh)}(hhh](h)}(h(Display Core, both software and hardwareh]h)}(hjH+h]h(Display Core, both software and hardware}(hjJ+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjF+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubh)}(h7DC modules that we need (freesync and color management)h]h)}(hj`+h]h7DC modules that we need (freesync and color management)}(hjb+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj^+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubh)}(hDRM software statesh]h)}(hjx+h]hDRM software states}(hjz+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hjv+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubh)}(hInterrupt sources and handlersh]h)}(hj+h]hInterrupt sources and handlers}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubh)}(hVblank supporth]h)}(hj+h]hVblank support}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubh)}(hDebug FS entries, if enabledh]h)}(hj+h]hDebug FS entries, if enabled}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM hj+ubah}(h]h ]h"]h$]h&]uh1hhjC+ubeh}(h]h ]h"]h$]h&]bullet-uh1hhjW+hM hj}*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj()hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_hw_fini (C function) c.dm_hw_finihNtauh1jhj()hhhNhNubj )}(hhh](j)}(h1int dm_hw_fini (struct amdgpu_ip_block *ip_block)h]j)}(h0int dm_hw_fini(struct amdgpu_ip_block *ip_block)h](j))}(hinth]hint}(hj+hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj+hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM" ubj.)}(h h]h }(hj ,hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj+hhhj ,hM" ubj?)}(h dm_hw_finih]jE)}(h dm_hw_finih]h dm_hw_fini}(hj,hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj,ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj+hhhj ,hM" ubj))}(h"(struct amdgpu_ip_block *ip_block)h]j))}(h struct amdgpu_ip_block *ip_blockh](j)}(hjh]hstruct}(hj;,hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj7,ubj.)}(h h]h }(hjH,hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7,ubh)}(hhh]jE)}(hamdgpu_ip_blockh]hamdgpu_ip_block}(hjY,hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjV,ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj[,modnameN classnameNjj)}j ]j*)}j *j!,sb c.dm_hw_finiasbuh1hhj7,ubj.)}(h h]h }(hjy,hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7,ubj'*)}(hj**h]h*}(hj,hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj7,ubjE)}(hip_blockh]hip_block}(hj,hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj7,ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj3,ubah}(h]h ]h"]h$]h&]j\j]uh1j)hj+hhhj ,hM" ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj+hhhj ,hM" ubah}(h]j+ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj ,hM" hj+hhubjs)}(hhh]h)}(hTeardown DC deviceh]hTeardown DC device}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM" hj,hhubah}(h]h ]h"]h$]h&]uh1jrhj+hhhj ,hM" ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj,jj,jjjuh1j hhhj()hNhNubj)}(hXk**Parameters** ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. **Description** Teardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.h](h)}(h**Parameters**h]j)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM& hj,ubj)}(hhh]j)}(hZ``struct amdgpu_ip_block *ip_block`` Pointer to the amdgpu_ip_block for this hw instance. h](j)}(h$``struct amdgpu_ip_block *ip_block``h]j)}(hj,h]h struct amdgpu_ip_block *ip_block}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM# hj,ubj )}(hhh]h)}(h4Pointer to the amdgpu_ip_block for this hw instance.h]h4Pointer to the amdgpu_ip_block for this hw instance.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hM# hj-ubah}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ]h"]h$]h&]uh1jhj-hM# hj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubh)}(h**Description**h]j)}(hj:-h]h Description}(hj<-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8-ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM% hj,ubh)}(hTeardown components within :c:type:`struct amdgpu_display_manager ` that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.h](hTeardown components within }(hjP-hhhNhNubh)}(h@:c:type:`struct amdgpu_display_manager `h]j)}(hjZ-h]hstruct amdgpu_display_manager}(hj\-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjX-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:20: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM$ hjP-ubh that require cleanup. This involves cleaning up the DRM device, DC, and any modules that were loaded. Also flush IRQ workqueues and disable them.}(hjP-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjw-hM$ hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj()hhhNhNubeh}(h]jah ]h"] lifecycleah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Interruptsh]h Interrupts}(hj-hhhNhNubah}(h]h ]h"]h$]h&]hj;uh1hhj-hhhhhKubh)}(hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.h]hDM provides another layer of IRQ management on top of what the base driver already provides. This is something that could be cleaned up, and is a future TODO item.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK#hj-hhubh)}(hXOThe base driver provides IRQ source registration with DRM, handler registration into the base driver's IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. This generic handler looks up the IRQ table, and calls the respective :c:type:`amdgpu_irq_src_funcs.process ` hookups.h](hX The base driver provides IRQ source registration with DRM, handler registration into the base driver’s IRQ table, and a handler callback amdgpu_irq_handler(), with which DRM calls on interrupts. This generic handler looks up the IRQ table, and calls the respective }(hj-hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]j)}(hj-h]hamdgpu_irq_src_funcs.process}(hj-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK'hj-ubh hookups.}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj-hK'hj-hhubh)}(hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:h]hWhat DM provides on top are two IRQ tables specifically for top-half and bottom-half IRQ handling, with the bottom-half implementing workqueues:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK-hj-hhubh)}(hhh](h)}(hS:c:type:`amdgpu_display_manager.irq_handler_list_high_tab `h]h)}(hj-h]h)}(hj-h]j)}(hj-h]h0amdgpu_display_manager.irq_handler_list_high_tab}(hj-hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK0hj-ubah}(h]h ]h"]h$]h&]uh1hhj.hK0hj-ubah}(h]h ]h"]h$]h&]uh1hhj-ubh)}(hS:c:type:`amdgpu_display_manager.irq_handler_list_low_tab ` h]h)}(hR:c:type:`amdgpu_display_manager.irq_handler_list_low_tab `h]h)}(hj,.h]j)}(hj,.h]h/amdgpu_display_manager.irq_handler_list_low_tab}(hj1.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj..ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_display_manageruh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK1hj*.ubah}(h]h ]h"]h$]h&]uh1hhjL.hK1hj&.ubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]j+j+uh1hhj.hK0hj-hhubh)}(hXThey override the base driver's IRQ table, and the effect can be seen in the hooks that DM provides for :c:type:`amdgpu_irq_src_funcs.process `. They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM's IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See dce110_register_irq_handlers() and dcn10_register_irq_handlers().h](hjThey override the base driver’s IRQ table, and the effect can be seen in the hooks that DM provides for }(hj_.hhhNhNubh)}(h=:c:type:`amdgpu_irq_src_funcs.process `h]j)}(hji.h]hamdgpu_irq_src_funcs.process}(hjk.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjg.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK3hj_.ubhX . They are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up DM’s IRQ tables. However, in order for base driver to recognize this hook, DM still needs to register the IRQ with the base driver. See dce110_register_irq_handlers() and dcn10_register_irq_handlers().}(hj_.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hK3hj-hhubh)}(hTo expose DC's hardware interrupt toggle to the base driver, DM implements :c:type:`amdgpu_irq_src_funcs.set ` hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.h](hMTo expose DC’s hardware interrupt toggle to the base driver, DM implements }(hj.hhhNhNubh)}(h9:c:type:`amdgpu_irq_src_funcs.set `h]j)}(hj.h]hamdgpu_irq_src_funcs.set}(hj.hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_irq_src_funcsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:26: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chK:hj.ubh\ hooks. Base driver calls it through amdgpu_irq_update() to enable or disable the interrupt.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj.hK:hj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_dm_irq_handler_data (C struct)c.amdgpu_dm_irq_handler_datahNtauh1jhj-hhhNhNubj )}(hhh](j)}(hamdgpu_dm_irq_handler_datah]j)}(h!struct amdgpu_dm_irq_handler_datah](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj.hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKubj.)}(h h]h }(hj.hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj.hhhj.hKubj?)}(hamdgpu_dm_irq_handler_datah]jE)}(hj.h]hamdgpu_dm_irq_handler_data}(hj.hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj.ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj.hhhj.hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj.hhhj.hKubah}(h]j.ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj.hKhj.hhubjs)}(hhh]h)}(hData for DM interrupt handlers.h]hData for DM interrupt handlers.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKFhj/hhubah}(h]h ]h"]h$]h&]uh1jrhj.hhhj.hKubeh}(h]h ](jstructeh"]h$]h&]jjjj6/jj6/jjjuh1j hhhj-hNhNubj)}(hX?**Definition**:: struct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; }; **Members** ``list`` Linked list entry referencing the next/previous handler ``handler`` Handler function ``handler_arg`` Argument passed to the handler when triggered ``dm`` DM which this handler belongs to ``irq_source`` DC interrupt source that this handler is registered for ``work`` work structh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjB/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>/ubh:}(hj>/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKJhj:/ubj)}(hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };h]hstruct amdgpu_dm_irq_handler_data { struct list_head list; interrupt_handler handler; void *handler_arg; struct amdgpu_display_manager *dm; enum dc_irq_source irq_source; struct work_struct work; };}hj[/sbah}(h]h ]h"]h$]h&]j\j]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhj:/ubh)}(h **Members**h]j)}(hjl/h]hMembers}(hjn/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj/ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKUhj:/ubj)}(hhh](j)}(hA``list`` Linked list entry referencing the next/previous handler h](j)}(h``list``h]j)}(hj/h]hlist}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKIhj/ubj )}(hhh]h)}(h7Linked list entry referencing the next/previous handlerh]h7Linked list entry referencing the next/previous handler}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hKIhj/ubah}(h]h ]h"]h$]h&]uh1j hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hKIhj/ubj)}(h``handler`` Handler function h](j)}(h ``handler``h]j)}(hj/h]hhandler}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKJhj/ubj )}(hhh]h)}(hHandler functionh]hHandler function}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hKJhj/ubah}(h]h ]h"]h$]h&]uh1j hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hKJhj/ubj)}(h>``handler_arg`` Argument passed to the handler when triggered h](j)}(h``handler_arg``h]j)}(hj/h]h handler_arg}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKKhj/ubj )}(hhh]h)}(h-Argument passed to the handler when triggeredh]h-Argument passed to the handler when triggered}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKKhj0ubah}(h]h ]h"]h$]h&]uh1j hj/ubeh}(h]h ]h"]h$]h&]uh1jhj0hKKhj/ubj)}(h(``dm`` DM which this handler belongs to h](j)}(h``dm``h]j)}(hj60h]hdm}(hj80hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj40ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKLhj00ubj )}(hhh]h)}(h DM which this handler belongs toh]h DM which this handler belongs to}(hjO0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjK0hKLhjL0ubah}(h]h ]h"]h$]h&]uh1j hj00ubeh}(h]h ]h"]h$]h&]uh1jhjK0hKLhj/ubj)}(hG``irq_source`` DC interrupt source that this handler is registered for h](j)}(h``irq_source``h]j)}(hjo0h]h irq_source}(hjq0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm0ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKMhji0ubj )}(hhh]h)}(h7DC interrupt source that this handler is registered forh]h7DC interrupt source that this handler is registered for}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKMhj0ubah}(h]h ]h"]h$]h&]uh1j hji0ubeh}(h]h ]h"]h$]h&]uh1jhj0hKMhj/ubj)}(h``work`` work structh](j)}(h``work``h]j)}(hj0h]hwork}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKMhj0ubj )}(hhh]h)}(h work structh]h work struct}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: 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}(hjL1hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj;1ubh)}(hhh]jE)}(h work_structh]h work_struct}(hj]1hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjZ1ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj_1modnameN classnameNjj)}j ]j*)}j *j%1sbc.dm_irq_work_funcasbuh1hhj;1ubj.)}(h h]h }(hj}1hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj;1ubj'*)}(hj**h]h*}(hj1hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj;1ubjE)}(hworkh]hwork}(hj1hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj;1ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj71ubah}(h]h ]h"]h$]h&]j\j]uh1j)hj0hhhj1hKoubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj0hhhj1hKoubah}(h]j0ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj1hKohj0hhubjs)}(hhh]h)}(h6Handle an IRQ outside of the interrupt handler proper.h]h6Handle an IRQ outside of the interrupt handler proper.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chKohj1hhubah}(h]h ]h"]h$]h&]uh1jrhj0hhhj1hKoubeh}(h]h ](jfunctioneh"]h$]h&]jjjj1jj1jjjuh1j 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]j(ah"]h$]h&]uh1jhj4ubj.)}(h h]h }(hj4hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4ubh)}(hhh]jE)}(hdc_interrupt_paramsh]hdc_interrupt_params}(hj4hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj4modnameN classnameNjj)}j ]jb4"c.amdgpu_dm_irq_register_interruptasbuh1hhj4ubj.)}(h h]h }(hj4hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4ubj'*)}(hj**h]h*}(hj4hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj4ubjE)}(h int_paramsh]h int_params}(hj4hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj4ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj 4ubj))}(hvoid (*ih)(void*)h](j))}(hvoidh]hvoid}(hj 5hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj5ubj.)}(h h]h }(hj5hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj5ubj'*)}(h(h]h(}(hj&5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubj'*)}(hj**h]h*}(hj45hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubjE)}(hihh]hih}(hjA5hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj5ubj'*)}(h)h]h)}(hjO5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubj'*)}(hj(5h]h(}(hj]5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubj))}(hvoidh]hvoid}(hjj5hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj5ubj'*)}(hj**h]h*}(hjx5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubj'*)}(hjQ5h]h)}(hj5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj 4ubj))}(hvoid *handler_argsh](j))}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj5ubj.)}(h h]h }(hj5hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj5ubj'*)}(hj**h]h*}(hj5hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj5ubjE)}(h handler_argsh]h handler_args}(hj5hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj5ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj 4ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj3hhhj3hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj3hhhj3hMubah}(h]j3ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj3hMhj3hhubjs)}(hhh]h)}(hRegister a handler within DM.h]hRegister a handler within DM.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj5hhubah}(h]h ]h"]h$]h&]uh1jrhj3hhhj3hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj6jj6jjjuh1j hhhj-hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device. ``struct dc_interrupt_params *int_params`` Interrupt parameters containing the source, and handler context ``void (*ih)(void *)`` Function pointer to the interrupt handler to register ``void *handler_args`` Arguments passed to the handler when the interrupt occurs **Description** Register an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep. 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The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.h]hXRegister an interrupt handler for the given IRQ source, under the given context. The context can either be high or low. High context handlers are executed directly within ISR context, while low context is executed within a workqueue, thereby allowing operations that sleep.}(hj-7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM#hj 6ubh)}(hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.h]hpRegistered handlers are called in a FIFO manner, i.e. the most recently registered handler will be called first.}(hj<7hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM(hj 6ubh)}(h **Return**h]j)}(hjM7h]hReturn}(hjO7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK7ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM+hj 6ubh)}(hHandler data :c:type:`struct amdgpu_dm_irq_handler_data ` containing the IRQ source, handler function, and argsh](h Handler data }(hjc7hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]j)}(hjm7h]h!struct amdgpu_dm_irq_handler_data}(hjo7hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjk7ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM,hjc7ubh6 containing the IRQ source, handler function, and args}(hjc7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj7hM,hj 6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/amdgpu_dm_irq_unregister_interrupt (C function)$c.amdgpu_dm_irq_unregister_interrupthNtauh1jhj-hhhNhNubj )}(hhh](j)}(hmvoid amdgpu_dm_irq_unregister_interrupt (struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h]j)}(hlvoid amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](j))}(hvoidh]hvoid}(hj7hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj7hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMjubj.)}(h h]h }(hj7hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7hhhj7hMjubj?)}(h"amdgpu_dm_irq_unregister_interrupth]jE)}(h"amdgpu_dm_irq_unregister_interrupth]h"amdgpu_dm_irq_unregister_interrupt}(hj7hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj7ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj7hhhj7hMjubj))}(hE(struct amdgpu_device *adev, enum dc_irq_source irq_source, void *ih)h](j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj7ubj.)}(h h]h }(hj7hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7ubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hj8hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj 8ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj8modnameN classnameNjj)}j ]j*)}j *j7sb$c.amdgpu_dm_irq_unregister_interruptasbuh1hhj7ubj.)}(h h]h }(hj08hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj7ubj'*)}(hj**h]h*}(hj>8hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj7ubjE)}(hadevh]hadev}(hjK8hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj7ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj7ubj))}(henum dc_irq_source irq_sourceh](j)}(henumh]henum}(hjd8hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj`8ubj.)}(h h]h }(hjr8hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`8ubh)}(hhh]jE)}(h dc_irq_sourceh]h dc_irq_source}(hj8hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj8ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj8modnameN classnameNjj)}j ]j,8$c.amdgpu_dm_irq_unregister_interruptasbuh1hhj`8ubj.)}(h h]h }(hj8hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`8ubjE)}(h irq_sourceh]h irq_source}(hj8hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`8ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj7ubj))}(hvoid *ihh](j))}(hvoidh]hvoid}(hj8hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj8ubj.)}(h h]h }(hj8hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj8ubj'*)}(hj**h]h*}(hj8hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj8ubjE)}(hihh]hih}(hj8hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj8ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj7ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj7hhhj7hMjubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj7hhhj7hMjubah}(h]j7ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj7hMjhj7hhubjs)}(hhh]h)}(h&Remove a handler from the DM IRQ tableh]h&Remove a handler from the DM IRQ table}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMjhj9hhubah}(h]h ]h"]h$]h&]uh1jrhj7hhhj7hMjubeh}(h]h ](jfunctioneh"]h$]h&]jjjj39jj39jjjuh1j hhhj-hNhNubj)}(hX**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device ``enum dc_irq_source irq_source`` IRQ source to remove the given handler from ``void *ih`` Function pointer to the interrupt handler to unregister **Description** Go through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h](h)}(h**Parameters**h]j)}(hj=9h]h Parameters}(hj?9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;9ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj79ubj)}(hhh](j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj\9h]hstruct amdgpu_device *adev}(hj^9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMkhjV9ubj )}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hju9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq9hMkhjr9ubah}(h]h ]h"]h$]h&]uh1j hjV9ubeh}(h]h ]h"]h$]h&]uh1jhjq9hMkhjS9ubj)}(hN``enum dc_irq_source irq_source`` IRQ source to remove the given handler from h](j)}(h!``enum dc_irq_source irq_source``h]j)}(hj9h]henum dc_irq_source irq_source}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMlhj9ubj )}(hhh]h)}(h+IRQ source to remove the given handler fromh]h+IRQ source to remove the given handler from}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMlhj9ubah}(h]h ]h"]h$]h&]uh1j hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMlhjS9ubj)}(hE``void *ih`` Function pointer to the interrupt handler to unregister h](j)}(h ``void *ih``h]j)}(hj9h]hvoid *ih}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMmhj9ubj )}(hhh]h)}(h7Function pointer to the interrupt handler to unregisterh]h7Function pointer to the interrupt handler to unregister}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMmhj9ubah}(h]h ]h"]h$]h&]uh1j hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMmhjS9ubeh}(h]h ]h"]h$]h&]uh1jhj79ubh)}(h**Description**h]j)}(hj :h]h Description}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMohj79ubh)}(hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.h]hGo through both low and high context IRQ tables, and find the given handler for the given irq source. If found, remove it. Otherwise, do nothing.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMnhj79ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_init (C function)c.amdgpu_dm_irq_inithNtauh1jhj-hhhNhNubj )}(hhh](j)}(h3int amdgpu_dm_irq_init (struct amdgpu_device *adev)h]j)}(h2int amdgpu_dm_irq_init(struct amdgpu_device *adev)h](j))}(hinth]hint}(hjN:hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjJ:hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj.)}(h h]h }(hj]:hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjJ:hhhj\:hMubj?)}(hamdgpu_dm_irq_inith]jE)}(hamdgpu_dm_irq_inith]hamdgpu_dm_irq_init}(hjo:hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjk:ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjJ:hhhj\:hMubj))}(h(struct amdgpu_device *adev)h]j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj:ubj.)}(h h]h }(hj:hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj:ubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hj:hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj:ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj:modnameN classnameNjj)}j ]j*)}j *jq:sbc.amdgpu_dm_irq_initasbuh1hhj:ubj.)}(h h]h }(hj:hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj:ubj'*)}(hj**h]h*}(hj:hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj:ubjE)}(hadevh]hadev}(hj:hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj:ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj:ubah}(h]h ]h"]h$]h&]j\j]uh1j)hjJ:hhhj\:hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjF:hhhj\:hMubah}(h]jA:ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj\:hMhjC:hhubjs)}(hhh]h)}(hInitialize DM IRQ managementh]hInitialize DM IRQ management}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj ;hhubah}(h]h ]h"]h$]h&]uh1jrhjC:hhhj\:hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj&;jj&;jjjuh1j hhhj-hNhNubj)}(hXt**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Initialize DM's high and low context IRQ tables. The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order. The low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](h)}(h**Parameters**h]j)}(hj0;h]h Parameters}(hj2;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj*;ubj)}(hhh]j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hjO;h]hstruct amdgpu_device *adev}(hjQ;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM;ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjI;ubj )}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjh;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd;hMhje;ubah}(h]h ]h"]h$]h&]uh1j hjI;ubeh}(h]h ]h"]h$]h&]uh1jhjd;hMhjF;ubah}(h]h ]h"]h$]h&]uh1jhj*;ubh)}(h**Description**h]j)}(hj;h]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj*;ubh)}(h0Initialize DM's high and low context IRQ tables.h]h2Initialize DM’s high and low context IRQ tables.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj*;ubh)}(hX.The N by M table contains N IRQ sources, with M :c:type:`struct amdgpu_dm_irq_handler_data ` hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.h](h0The N by M table contains N IRQ sources, with M }(hj;hhhNhNubh)}(hH:c:type:`struct amdgpu_dm_irq_handler_data `h]j)}(hj;h]h!struct amdgpu_dm_irq_handler_data}(hj;hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jamdgpu_dm_irq_handler_datauh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj;ubh hooked together in a linked list. The list_heads are initialized here. When an interrupt n is triggered, all m handlers are called in sequence, FIFO according to registration order.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj;hMhj*;ubh)}(hThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See :c:type:`struct irq_list_head `.h](hpThe low context table requires special steps to initialize, since handlers will be deferred to a workqueue. See }(hj;hhhNhNubh)}(h.:c:type:`struct irq_list_head `h]j)}(hj;h]hstruct irq_list_head}(hj;hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j irq_list_headuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj;ubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj<hMhj*;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_irq_fini (C function)c.amdgpu_dm_irq_finihNtauh1jhj-hhhNhNubj )}(hhh](j)}(h4void amdgpu_dm_irq_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_irq_fini(struct amdgpu_device *adev)h](j))}(hvoidh]hvoid}(hj3<hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj/<hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj.)}(h h]h }(hjB<hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj/<hhhjA<hMubj?)}(hamdgpu_dm_irq_finih]jE)}(hamdgpu_dm_irq_finih]hamdgpu_dm_irq_fini}(hjT<hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjP<ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj/<hhhjA<hMubj))}(h(struct amdgpu_device *adev)h]j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hjp<hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjl<ubj.)}(h h]h }(hj}<hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjl<ubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hj<hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj<modnameN classnameNjj)}j ]j*)}j *jV<sbc.amdgpu_dm_irq_finiasbuh1hhjl<ubj.)}(h h]h }(hj<hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjl<ubj'*)}(hj**h]h*}(hj<hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjl<ubjE)}(hadevh]hadev}(hj<hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjl<ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjh<ubah}(h]h ]h"]h$]h&]j\j]uh1j)hj/<hhhjA<hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj+<hhhjA<hMubah}(h]j&<ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjA<hMhj(<hhubjs)}(hhh]h)}(hTear down DM IRQ managementh]hTear down DM IRQ management}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj<hhubah}(h]h ]h"]h$]h&]uh1jrhj(<hhhjA<hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj =jj =jjjuh1j hhhj-hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` The base driver device containing the DM device **Description** Flush all work within the low context IRQ table.h](h)}(h**Parameters**h]j)}(hj=h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubj)}(hhh]j)}(hO``struct amdgpu_device *adev`` The base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj4=h]hstruct amdgpu_device *adev}(hj6=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2=ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj.=ubj )}(hhh]h)}(h/The base driver device containing the DM deviceh]h/The base driver device containing the DM device}(hjM=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI=hMhjJ=ubah}(h]h ]h"]h$]h&]uh1j hj.=ubeh}(h]h ]h"]h$]h&]uh1jhjI=hMhj+=ubah}(h]h ]h"]h$]h&]uh1jhj=ubh)}(h**Description**h]j)}(hjo=h]h Description}(hjq=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm=ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubh)}(h0Flush all work within the low context IRQ table.h]h0Flush all work within the low context IRQ table.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"amdgpu_dm_irq_handler (C function)c.amdgpu_dm_irq_handlerhNtauh1jhj-hhhNhNubj )}(hhh](j)}(htint amdgpu_dm_irq_handler (struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h]j)}(hsint amdgpu_dm_irq_handler(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](j))}(hinth]hint}(hj=hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj=hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj.)}(h h]h }(hj=hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj=hhhj=hMubj?)}(hamdgpu_dm_irq_handlerh]jE)}(hamdgpu_dm_irq_handlerh]hamdgpu_dm_irq_handler}(hj=hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj=ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj=hhhj=hMubj))}(hZ(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry)h](j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj=ubj.)}(h h]h }(hj=hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj=ubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hj>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj >ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj>modnameN classnameNjj)}j ]j*)}j *j=sbc.amdgpu_dm_irq_handlerasbuh1hhj=ubj.)}(h h]h }(hj/>hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj=ubj'*)}(hj**h]h*}(hj=>hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj=ubjE)}(hadevh]hadev}(hjJ>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj=ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj=ubj))}(hstruct amdgpu_irq_src *sourceh](j)}(hjh]hstruct}(hjc>hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj_>ubj.)}(h h]h }(hjp>hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj_>ubh)}(hhh]jE)}(hamdgpu_irq_srch]hamdgpu_irq_src}(hj>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj~>ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj>modnameN classnameNjj)}j ]j+>c.amdgpu_dm_irq_handlerasbuh1hhj_>ubj.)}(h h]h }(hj>hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj_>ubj'*)}(hj**h]h*}(hj>hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj_>ubjE)}(hsourceh]hsource}(hj>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj_>ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj=ubj))}(hstruct amdgpu_iv_entry *entryh](j)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj>ubj.)}(h h]h }(hj>hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj>ubh)}(hhh]jE)}(hamdgpu_iv_entryh]hamdgpu_iv_entry}(hj>hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj>ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj>modnameN classnameNjj)}j ]j+>c.amdgpu_dm_irq_handlerasbuh1hhj>ubj.)}(h h]h }(hj?hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj>ubj'*)}(hj**h]h*}(hj?hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj>ubjE)}(hentryh]hentry}(hj*?hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj>ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj=ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj=hhhj=hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj=hhhj=hMubah}(h]j=ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj=hMhj=hhubjs)}(hhh]h)}(hGeneric DM IRQ handlerh]hGeneric DM IRQ handler}(hjT?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjQ?hhubah}(h]h ]h"]h$]h&]uh1jrhj=hhhj=hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjl?jjl?jjjuh1j hhhj-hNhNubj)}(hXv**Parameters** ``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device ``struct amdgpu_irq_src *source`` Unused ``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt **Description** Calls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h](h)}(h**Parameters**h]j)}(hjv?h]h Parameters}(hjx?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt?ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjp?ubj)}(hhh](j)}(hR``struct amdgpu_device *adev`` amdgpu base driver device containing the DM device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj?h]hstruct amdgpu_device *adev}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj?ubj )}(hhh]h)}(h2amdgpu base driver device containing the DM deviceh]h2amdgpu base driver device containing the DM device}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1j hj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubj)}(h)``struct amdgpu_irq_src *source`` Unused h](j)}(h!``struct amdgpu_irq_src *source``h]j)}(hj?h]hstruct amdgpu_irq_src *source}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj?ubj )}(hhh]h)}(hUnusedh]hUnused}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1j hj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubj)}(hE``struct amdgpu_iv_entry *entry`` Data about the triggered interrupt h](j)}(h!``struct amdgpu_iv_entry *entry``h]j)}(hj@h]hstruct amdgpu_iv_entry *entry}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhj@ubj )}(hhh]h)}(h"Data about the triggered interrupth]h"Data about the triggered interrupt}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1j hj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj?ubeh}(h]h ]h"]h$]h&]uh1jhjp?ubh)}(h**Description**h]j)}(hjB@h]h Description}(hjD@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@@ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjp?ubh)}(hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.h]hCalls all registered high irq work immediately, and schedules work for low irq. The DM IRQ table is used to find the corresponding handlers.}(hjX@hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjp?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_init (C function)c.amdgpu_dm_hpd_inithNtauh1jhj-hhhNhNubj )}(hhh](j)}(h4void amdgpu_dm_hpd_init (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_init(struct amdgpu_device *adev)h](j))}(hvoidh]hvoid}(hj@hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj@hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzubj.)}(h h]h }(hj@hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj@hhhj@hMzubj?)}(hamdgpu_dm_hpd_inith]jE)}(hamdgpu_dm_hpd_inith]hamdgpu_dm_hpd_init}(hj@hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj@ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj@hhhj@hMzubj))}(h(struct amdgpu_device *adev)h]j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hj@hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj@ubj.)}(h h]h }(hj@hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj@ubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hj@hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj@ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj@modnameN classnameNjj)}j ]j*)}j *j@sbc.amdgpu_dm_hpd_initasbuh1hhj@ubj.)}(h h]h }(hjAhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj@ubj'*)}(hj**h]h*}(hjAhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj@ubjE)}(hadevh]hadev}(hjAhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj@ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj@ubah}(h]h ]h"]h$]h&]j\j]uh1j)hj@hhhj@hMzubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj@hhhj@hMzubah}(h]jz@ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj@hMzhj|@hhubjs)}(hhh]h)}(hhpd setup callback.h]hhpd setup callback.}(hjGAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMzhjDAhhubah}(h]h ]h"]h$]h&]uh1jrhj|@hhhj@hMzubeh}(h]h ](jfunctioneh"]h$]h&]jjjj_Ajj_Ajjjuh1j hhhj-hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Setup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hjiAh]h Parameters}(hjkAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgAubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hjcAubj)}(hhh]j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hjAh]hstruct amdgpu_device *adev}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM|hjAubj )}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhM|hjAubah}(h]h ]h"]h$]h&]uh1j hjAubeh}(h]h ]h"]h$]h&]uh1jhjAhM|hjAubah}(h]h ]h"]h$]h&]uh1jhjcAubh)}(h**Description**h]j)}(hjAh]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM~hjcAubh)}(hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.h]hrSetup the hpd pins used by the card (evergreen+). Enable the pin, set the polarity, and enable the hpd interrupts.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chM}hjcAubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jamdgpu_dm_hpd_fini (C function)c.amdgpu_dm_hpd_finihNtauh1jhj-hhhNhNubj )}(hhh](j)}(h4void amdgpu_dm_hpd_fini (struct amdgpu_device *adev)h]j)}(h3void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)h](j))}(hvoidh]hvoid}(hjBhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjBhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMubj.)}(h h]h }(hjBhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjBhhhjBhMubj?)}(hamdgpu_dm_hpd_finih]jE)}(hamdgpu_dm_hpd_finih]hamdgpu_dm_hpd_fini}(hj)BhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj%Bubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjBhhhjBhMubj))}(h(struct amdgpu_device *adev)h]j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hjEBhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjABubj.)}(h h]h }(hjRBhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjABubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hjcBhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`Bubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjeBmodnameN classnameNjj)}j ]j*)}j *j+Bsbc.amdgpu_dm_hpd_finiasbuh1hhjABubj.)}(h h]h }(hjBhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjABubj'*)}(hj**h]h*}(hjBhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjABubjE)}(hadevh]hadev}(hjBhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjABubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj=Bubah}(h]h ]h"]h$]h&]j\j]uh1j)hjBhhhjBhMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjBhhhjBhMubah}(h]jAah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjBhMhjAhhubjs)}(hhh]h)}(hhpd tear down callback.h]hhpd tear down callback.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBhhubah}(h]h ]h"]h$]h&]uh1jrhjAhhhjBhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjBjjBjjjuh1j hhhj-hNhNubj)}(h**Parameters** ``struct amdgpu_device *adev`` amdgpu_device pointer **Description** Tear down the hpd pins used by the card (evergreen+). Disable the hpd interrupts.h](h)}(h**Parameters**h]j)}(hjBh]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubj)}(hhh]j)}(h5``struct amdgpu_device *adev`` amdgpu_device pointer h](j)}(h``struct amdgpu_device *adev``h]j)}(hj Ch]hstruct amdgpu_device *adev}(hj ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjCubj )}(hhh]h)}(hamdgpu_device pointerh]hamdgpu_device pointer}(hj"ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChMhjCubah}(h]h ]h"]h$]h&]uh1j hjCubeh}(h]h ]h"]h$]h&]uh1jhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjBubh)}(h**Description**h]j)}(hjDCh]h Description}(hjFChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBCubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubh)}(hQTear down the hpd pins used by the card (evergreen+). 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Disable the hpd interrupts.}(hjZChhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:29: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.chMhjBubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdm_pflip_high_irq (C function)c.dm_pflip_high_irqhNtauh1jhj-hhhNhNubj )}(hhh](j)}(h/void dm_pflip_high_irq (void *interrupt_params)h]j)}(h.void dm_pflip_high_irq(void *interrupt_params)h](j))}(hvoidh]hvoid}(hjChhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjChhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMubj.)}(h h]h }(hjChhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjChhhjChMubj?)}(hdm_pflip_high_irqh]jE)}(hdm_pflip_high_irqh]hdm_pflip_high_irq}(hjChhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjCubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjChhhjChMubj))}(h(void *interrupt_params)h]j))}(hvoid *interrupt_paramsh](j))}(hvoidh]hvoid}(hjChhhNhNubah}(h]h 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]h"]h$]h&]uh1jhj9Dubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj5Dubj)}(hhh]j)}(h#``void *interrupt_params`` ignored h](j)}(h``void *interrupt_params``h]j)}(hjZDh]hvoid *interrupt_params}(hj\DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXDubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjTDubj )}(hhh]h)}(hignoredh]hignored}(hjsDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjoDhMhjpDubah}(h]h ]h"]h$]h&]uh1j hjTDubeh}(h]h ]h"]h$]h&]uh1jhjoDhMhjQDubah}(h]h ]h"]h$]h&]uh1jhj5Dubh)}(h**Description**h]j)}(hjDh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhj5Dubh)}(hhHandles the pageflip interrupt by notifying all interested parties that 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interrupt by notfying DRM's VBLANK event handler.h](h)}(h**Parameters**h]j)}(hjEh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjEubj)}(hhh]j)}(hB``void *interrupt_params`` used for determining the CRTC instance h](j)}(h``void *interrupt_params``h]j)}(hjEh]hvoid *interrupt_params}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjEubj )}(hhh]h)}(h&used for determining the CRTC instanceh]h&used for determining the CRTC instance}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhMhjEubah}(h]h ]h"]h$]h&]uh1j hjEubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjEubah}(h]h ]h"]h$]h&]uh1jhjEubh)}(h**Description**h]j)}(hjEh]h Description}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjEubh)}(hHHandles the CRTC/VSYNC interrupt by notfying DRM's VBLANK event handler.h]hJHandles the CRTC/VSYNC interrupt by notfying DRM’s VBLANK event handler.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:32: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjEubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubeh}(h]jAah ]h"] interruptsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAtomic Implementationh]hAtomic Implementation}(hjFhhhNhNubah}(h]h ]h"]h$]h&]hj]uh1hhjFhhhhhK$ubh)}(h*WIP*h]hemphasis)}(hj,Fh]hWIP}(hj0FhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhj*Fubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:38: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chMhjFhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)amdgpu_dm_atomic_commit_tail (C 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refdomainjreftypej * reftargetjFmodnameN classnameNjj)}j ]j*)}j *jFsbc.amdgpu_dm_atomic_commit_tailasbuh1hhjFubj.)}(h h]h }(hjFhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjFubj'*)}(hj**h]h*}(hjFhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjFubjE)}(hstateh]hstate}(hjFhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjFubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjFubah}(h]h ]h"]h$]h&]j\j]uh1j)hjYFhhhjkFhM*ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjUFhhhjkFhM*ubah}(h]jPFah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjkFhM*hjRFhhubjs)}(hhh]h)}(h'AMDgpu DM's commit tail implementation.h]h)AMDgpu DM’s commit tail implementation.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM*hjGhhubah}(h]h ]h"]h$]h&]uh1jrhjRFhhhjkFhM*ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj5Gjj5Gjjjuh1j hhhjFhNhNubj)}(hX.**Parameters** ``struct drm_atomic_state *state`` The atomic state to commit **Description** This will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h](h)}(h**Parameters**h]j)}(hj?Gh]h Parameters}(hjAGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=Gubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM*hj9Gubj)}(hhh]j)}(h>``struct drm_atomic_state *state`` The atomic state to commit h](j)}(h"``struct drm_atomic_state *state``h]j)}(hj^Gh]hstruct drm_atomic_state *state}(hj`GhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\Gubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM*hjXGubj )}(hhh]h)}(hThe atomic state to commith]hThe atomic state to commit}(hjwGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsGhM*hjtGubah}(h]h ]h"]h$]h&]uh1j hjXGubeh}(h]h ]h"]h$]h&]uh1jhjsGhM*hjUGubah}(h]h ]h"]h$]h&]uh1jhj9Gubh)}(h**Description**h]j)}(hjGh]h Description}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM*hj9Gubh)}(hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.h]hThis will tell DC to commit the constructed DC state from atomic_check, programming the hardware. Any failures here implies a hardware failure, since atomic check should have filtered anything non-kosher.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM*hj9Gubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjFhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#amdgpu_dm_atomic_check (C function)c.amdgpu_dm_atomic_checkhNtauh1jhjFhhhNhNubj )}(hhh](j)}(hSint amdgpu_dm_atomic_check (struct drm_device *dev, struct drm_atomic_state *state)h]j)}(hRint amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)h](j))}(hinth]hint}(hjGhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjGhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM1ubj.)}(h h]h }(hjGhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjGhhhjGhM1ubj?)}(hamdgpu_dm_atomic_checkh]jE)}(hamdgpu_dm_atomic_checkh]hamdgpu_dm_atomic_check}(hjGhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjGubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjGhhhjGhM1ubj))}(h8(struct drm_device *dev, struct drm_atomic_state *state)h](j))}(hstruct drm_device *devh](j)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjHubj.)}(h h]h }(hj(HhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjHubh)}(hhh]jE)}(h drm_deviceh]h drm_device}(hj9HhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj6Hubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj;HmodnameN classnameNjj)}j ]j*)}j *jHsbc.amdgpu_dm_atomic_checkasbuh1hhjHubj.)}(h h]h }(hjYHhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjHubj'*)}(hj**h]h*}(hjgHhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjHubjE)}(hdevh]hdev}(hjtHhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjHubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjHubj))}(hstruct drm_atomic_state *stateh](j)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjHubj.)}(h h]h }(hjHhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjHubh)}(hhh]jE)}(hdrm_atomic_stateh]hdrm_atomic_state}(hjHhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjHubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjHmodnameN classnameNjj)}j ]jUHc.amdgpu_dm_atomic_checkasbuh1hhjHubj.)}(h h]h }(hjHhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjHubj'*)}(hj**h]h*}(hjHhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjHubjE)}(hstateh]hstate}(hjHhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjHubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjHubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjGhhhjGhM1ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjGhhhjGhM1ubah}(h]jGah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjGhM1hjGhhubjs)}(hhh]h)}(h*Atomic check implementation for AMDgpu DM.h]h*Atomic check implementation for AMDgpu DM.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM1hj Ihhubah}(h]h ]h"]h$]h&]uh1jrhjGhhhjGhM1ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj&Ijj&Ijjjuh1j hhhjFhNhNubj)}(hX**Parameters** ``struct drm_device *dev`` The DRM device ``struct drm_atomic_state *state`` The atomic state to commit **Description** Validate that the given atomic state is programmable by DC into hardware. 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This involves constructing a :c:type:`struct dc_state ` reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It's important not to modify the existing DC state. Otherwise, atomic_check may unexpectedly commit hardware changes.h](hgValidate that the given atomic state is programmable by DC into hardware. This involves constructing a }(hjIhhhNhNubh)}(h$:c:type:`struct dc_state `h]j)}(hjIh]hstruct dc_state}(hjIhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM1hjIubh reflecting the new hardware state we wish to commit, then querying DC to see if it is programmable. It’s important not to modify the existing DC state. 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For full updates case which removes/adds/updates streams on one CRTC while flipping on another CRTC, acquiring global lock will guarantee that any such full update commit will wait for completion of any outstanding flip using DRMs synchronization events.}(hj JhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM#1hj*Iubh)}(hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.h]hXNote that DM adds the affected connectors for all CRTCs in state, when that might not seem necessary. This is because DC stream creation requires the DC sink, which is tied to the DRM connector state. Cleaning this up should be possible but non-trivial - a possible TODO item.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM)1hj*Iubh)}(h **Return**h]j)}(hj+Jh]hReturn}(hj-JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Jubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM.1hj*Iubh)}(h!-Error code if validation failed.h]h!-Error code if validation failed.}(hjAJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:41: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.chM/1hj*Iubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjFhhhNhNubeh}(h]jcah ]h"]atomic implementationah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hColor Management Propertiesh]hColor Management Properties}(hjaJhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj^JhhhhhK-ubh)}(hWe have three types of color management in the AMD display driver. 1. the legacy :c:type:`drm_crtc` DEGAMMA, CTM, and GAMMA properties 2. AMD driver private color management on :c:type:`drm_plane` and :c:type:`drm_crtc` 3. AMD plane color pipelineh](hQWe have three types of color management in the AMD display driver. 1. the legacy }(hjoJhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjyJh]hdrm_crtc}(hj{JhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjwJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_crtcuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK%hjoJubhN DEGAMMA, CTM, and GAMMA properties 2. AMD driver private color management on }(hjoJhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjJh]h drm_plane}(hjJhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hhjJhK%hjoJubh and }(hjoJhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjJh]hdrm_crtc}(hjJhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_crtcuh1hhjJhK%hjoJubh 3. AMD plane color pipeline}(hjoJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjJhK%hj^Jhhubh)}(hXThe CRTC properties are the original color management. When they were implemented per-plane color management was not a thing yet. Because of that we could get away with plumbing the DEGAMMA and CTM properties to pre-blending HW functions. This is incompatible with per-plane color management, such as via the AMD private properties or the new drm_plane color pipeline. The only compatible CRTC property with per-plane color management is the GAMMA property as it is applied post-blending.h]hXThe CRTC properties are the original color management. When they were implemented per-plane color management was not a thing yet. Because of that we could get away with plumbing the DEGAMMA and CTM properties to pre-blending HW functions. This is incompatible with per-plane color management, such as via the AMD private properties or the new drm_plane color pipeline. The only compatible CRTC property with per-plane color management is the GAMMA property as it is applied post-blending.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK*hj^Jhhubh)}(hX4The AMD driver private color management properties are only exposed when the kernel is built explicitly with -DAMD_PRIVATE_COLOR. They are temporary building blocks on the path to full-fledged :c:type:`drm_plane` and :c:type:`drm_crtc` color pipelines and lay the driver's groundwork for the color pipelines.h](hThe AMD driver private color management properties are only exposed when the kernel is built explicitly with -DAMD_PRIVATE_COLOR. They are temporary building blocks on the path to full-fledged }(hjJhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjKh]h drm_plane}(hjKhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK3hjJubh and }(hjJhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hj$Kh]hdrm_crtc}(hj&KhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj"Kubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_crtcuh1hhjKhK3hjJubhK color pipelines and lay the driver’s groundwork for the color pipelines.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjKhK3hj^Jhhubh)}(hzThe AMD plane color pipeline describes AMD's :c:type:`drm_colorops` via the :c:type:`drm_plane`'s COLOR_PIPELINE property.h](h/The AMD plane color pipeline describes AMD’s }(hjKKhhhNhNubh)}(h:c:type:`drm_colorops`h]j)}(hjUKh]h drm_colorops}(hjWKhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjSKubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_coloropsuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK9hjKKubh via the }(hjKKhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjyKh]h drm_plane}(hj{KhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjwKubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hhjrKhK9hjKKubh’s COLOR_PIPELINE property.}(hjKKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjrKhK9hj^Jhhubh)}(hhh](h)}(hdrm_crtc Propertiesh]hdrm_crtc Properties}(hjKhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjKhNhNubh)}(hYThe DC interface to HW gives us the following color management blocks per pipe (surface):h]hYThe DC interface to HW gives us the following color management blocks per pipe (surface):}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK?hjKubh)}(hhh](h)}(hInput gamma LUT (de-normalized)h]h)}(hjKh]hInput gamma LUT (de-normalized)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKBhjKubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(hInput CSC (normalized)h]h)}(hjKh]hInput CSC (normalized)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKChjKubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(h Surface degamma LUT (normalized)h]h)}(hjKh]h Surface degamma LUT (normalized)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKDhjKubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(hSurface CSC (normalized)h]h)}(hj Lh]hSurface CSC (normalized)}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKEhj Lubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(h Surface regamma LUT (normalized)h]h)}(hj%Lh]h Surface regamma LUT (normalized)}(hj'LhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKFhj#Lubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(hOutput CSC (normalized) h]h)}(hOutput CSC (normalized)h]hOutput CSC (normalized)}(hj?LhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKGhj;Lubah}(h]h ]h"]h$]h&]uh1hhjKubeh}(h]h ]h"]h$]h&]j+j+uh1hhjKhKBhjKubh)}(hBut these aren't a direct mapping to DRM color properties. The current DRM interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware is essentially giving:h]hBut these aren’t a direct mapping to DRM color properties. The current DRM interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware is essentially giving:}(hjZLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKIhjKubh)}(hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTMh]hEPlane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM}(hjiLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKMhjKubh)}(hXThe input gamma LUT block isn't really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.h]hXThe input gamma LUT block isn’t really applicable here since it operates on the actual input data itself rather than the HW fp representation. The input and output CSC blocks are technically available to use as part of the DC interface but are typically used internally by DC for conversions between color spaces. These could be blended together with user adjustments in the future but for now these should remain untouched.}(hjxLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKOhjKubh)}(hX!The pipe blending also happens after these blocks so we don't actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.h]hX#The pipe blending also happens after these blocks so we don’t actually support any CRTC props with correct blending with multiple planes - but we can still support CRTC color management properties in DM in most single plane cases correctly with clever management of the DC interface in DM.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKWhjKubh)}(hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.h]hAs per DRM documentation, blocks should be in hardware bypass when their respective property is set to NULL. A linear DGM/RGM LUT should also considered as putting the respective block into bypass mode.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK]hjKubh)}(hIThis means that the following configuration is assumed to be the default:h]hIThis means that the following configuration is assumed to be the default:}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKahjKubh)}(huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypassh]huPlane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKdhjKubeh}(h]jah ]h"]drm_crtc propertiesah$]h&]uh1hhj^JhhhNhNubh)}(hhh](h)}(h)AMD Private Color Management on drm_planeh]h)AMD Private Color Management on drm_plane}(hjLhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjLhNhNubh)}(hIThe AMD private color management properties on a :c:type:`drm_plane` are:h](h1The AMD private color management properties on a }(hjLhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjLh]h drm_plane}(hjLhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKjhjLubh are:}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjMhKjhjLubh)}(hhh](h)}(hAMD_PLANE_DEGAMMA_LUTh]h)}(hjMh]hAMD_PLANE_DEGAMMA_LUT}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKlhjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_DEGAMMA_LUT_SIZEh]h)}(hj*Mh]hAMD_PLANE_DEGAMMA_LUT_SIZE}(hj,MhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKmhj(Mubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_DEGAMMA_TFh]h)}(hjBMh]hAMD_PLANE_DEGAMMA_TF}(hjDMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKnhj@Mubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_HDR_MULTh]h)}(hjZMh]hAMD_PLANE_HDR_MULT}(hj\MhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKohjXMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(h AMD_PLANE_CTMh]h)}(hjrMh]h AMD_PLANE_CTM}(hjtMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKphjpMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_SHAPER_LUTh]h)}(hjMh]hAMD_PLANE_SHAPER_LUT}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKqhjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_SHAPER_LUT_SIZEh]h)}(hjMh]hAMD_PLANE_SHAPER_LUT_SIZE}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKrhjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_SHAPER_TFh]h)}(hjMh]hAMD_PLANE_SHAPER_TF}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKshjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_LUT3Dh]h)}(hjMh]hAMD_PLANE_LUT3D}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKthjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_LUT3D_SIZEh]h)}(hjMh]hAMD_PLANE_LUT3D_SIZE}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKuhjMubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_BLEND_LUTh]h)}(hjNh]hAMD_PLANE_BLEND_LUT}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKvhjNubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_BLEND_LUT_SIZEh]h)}(hjNh]hAMD_PLANE_BLEND_LUT_SIZE}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKwhjNubah}(h]h ]h"]h$]h&]uh1hhj Mubh)}(hAMD_PLANE_BLEND_TF h]h)}(hAMD_PLANE_BLEND_TFh]hAMD_PLANE_BLEND_TF}(hj4NhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKxhj0Nubah}(h]h ]h"]h$]h&]uh1hhj Mubeh}(h]h ]h"]h$]h&]j+j+uh1hhj!MhKlhjLubh)}(hEThe AMD private color management property on a :c:type:`drm_crtc` is:h](h/The AMD private color management property on a }(hjONhhhNhNubh)}(h:c:type:`drm_crtc`h]j)}(hjYNh]hdrm_crtc}(hj[NhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjWNubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_crtcuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKzhjONubh is:}(hjONhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjvNhKzhjLubh)}(hhh]h)}(hAMD_CRTC_REGAMMA_TF h]h)}(hAMD_CRTC_REGAMMA_TFh]hAMD_CRTC_REGAMMA_TF}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK|hjNubah}(h]h ]h"]h$]h&]uh1hhjNubah}(h]h ]h"]h$]h&]j+j+uh1hhjNhK|hjLubh)}(h'Use of these properties is discouraged.h]h'Use of these properties is discouraged.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chK~hjLubeh}(h]jah ]h"])amd private color management on drm_planeah$]h&]uh1hhj^JhhhNhNubh)}(hhh](h)}(hAMD plane color pipelineh]hAMD plane color pipeline}(hjNhhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhjNhNhNubh)}(hThe AMD :c:type:`drm_plane` color pipeline is advertised for DCN generations 3.0 and newer. It exposes these elements in this order:h](hThe AMD }(hjNhhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjNh]h drm_plane}(hjNhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubhi color pipeline is advertised for DCN generations 3.0 and newer. It exposes these elements in this order:}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjNhKhjNubhenumerated_list)}(hhh](h)}(h1D curve coloroph]h)}(hjOh]h1D curve colorop}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h Multiplierh]h)}(hjOh]h Multiplier}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h3x4 CTMh]h)}(hj3Oh]h3x4 CTM}(hj5OhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhj1Oubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h1D curve coloroph]h)}(hjKOh]h1D curve colorop}(hjMOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjIOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h1D LUTh]h)}(hjcOh]h1D LUT}(hjeOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjaOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h3D LUTh]h)}(hj{Oh]h3D LUT}(hj}OhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjyOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h1D curve coloroph]h)}(hjOh]h1D curve colorop}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjOubah}(h]h ]h"]h$]h&]uh1hhjNubh)}(h1D LUT h]h)}(h1D LUTh]h1D LUT}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjOubah}(h]h ]h"]h$]h&]uh1hhjNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jNhjNubh)}(hKThe multiplier (#2) is a simple multiplier that is applied to all channels.h]hKThe multiplier (#2) is a simple multiplier that is applied to all channels.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubh)}(h(The 3x4 CTM (#3) is a simple 3x4 matrix.h]h(The 3x4 CTM (#3) is a simple 3x4 matrix.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubh)}(h#1, and #7 are non-linear to linear curves. #4 is a linear to non-linear curve. They support sRGB, PQ, and BT.709/BT.2020 EOTFs or their inverse.h]h#1, and #7 are non-linear to linear curves. #4 is a linear to non-linear curve. They support sRGB, PQ, and BT.709/BT.2020 EOTFs or their inverse.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubh)}(h2The 1D LUTs (#5 and #8) are plain 4096 entry LUTs.h]h2The 1D LUTs (#5 and #8) are plain 4096 entry LUTs.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubh)}(h;The 3DLUT (#6) is a tetrahedrally interpolated 17 cube LUT.h]h;The 3DLUT (#6) is a tetrahedrally interpolated 17 cube LUT.}(hj PhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:47: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjNubeh}(h]jah ]h"]amd plane color pipelineah$]h&]uh1hhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%amdgpu_dm_init_color_mod (C function)c.amdgpu_dm_init_color_modhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(h$void amdgpu_dm_init_color_mod (void)h]j)}(h#void amdgpu_dm_init_color_mod(void)h](j))}(hvoidh]hvoid}(hj8PhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj4Phhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKubj.)}(h h]h }(hjGPhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4PhhhjFPhKubj?)}(hamdgpu_dm_init_color_modh]jE)}(hamdgpu_dm_init_color_modh]hamdgpu_dm_init_color_mod}(hjYPhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjUPubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj4PhhhjFPhKubj))}(h(void)h]j))}(hvoidh]j))}(hvoidh]hvoid}(hjuPhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjqPubah}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjmPubah}(h]h ]h"]h$]h&]j\j]uh1j)hj4PhhhjFPhKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj0PhhhjFPhKubah}(h]j+Pah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjFPhKhj-Phhubjs)}(hhh]h)}(hInitialize the color module.h]hInitialize the color module.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjPhhubah}(h]h ]h"]h$]h&]uh1jrhj-PhhhjFPhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjPjjPjjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``void`` no arguments **Description** We're not using the full color module, only certain components. Only call setup functions for components that we need.h](h)}(h**Parameters**h]j)}(hjPh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjPubj)}(hhh]j)}(h``void`` no arguments h](j)}(h``void``h]j)}(hjPh]hvoid}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjPubj )}(hhh]h)}(h no argumentsh]h no arguments}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhKhjPubah}(h]h ]h"]h$]h&]uh1j hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhKhjPubah}(h]h ]h"]h$]h&]uh1jhjPubh)}(h**Description**h]j)}(hjQh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjPubh)}(hvWe're not using the full color module, only certain components. Only call setup functions for components that we need.h]hxWe’re not using the full color module, only certain components. Only call setup functions for components that we need.}(hj1QhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chKhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__extract_blob_lut (C function)c.__extract_blob_luthNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hfconst struct drm_color_lut * __extract_blob_lut (const struct drm_property_blob *blob, uint32_t *size)h]j)}(hdconst struct drm_color_lut *__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)h](j)}(hconsth]hconst}(hj`QhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj\Qhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hjoQhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\QhhhjnQhMubj)}(hjh]hstruct}(hj}QhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj\QhhhjnQhMubj.)}(h h]h }(hjQhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\QhhhjnQhMubh)}(hhh]jE)}(h drm_color_luth]h drm_color_lut}(hjQhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjQubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjQmodnameN classnameNjj)}j ]j*)}j *__extract_blob_lutsbc.__extract_blob_lutasbuh1hhj\QhhhjnQhMubj.)}(h h]h }(hjQhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\QhhhjnQhMubj'*)}(hj**h]h*}(hjQhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj\QhhhjnQhMubj?)}(h__extract_blob_luth]jE)}(hjQh]h__extract_blob_lut}(hjQhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjQubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj\QhhhjnQhMubj))}(h6(const struct drm_property_blob *blob, uint32_t *size)h](j))}(h$const struct drm_property_blob *blobh](j)}(hjbQh]hconst}(hjQhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjQubj.)}(h h]h }(hjRhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjQubj)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjQubj.)}(h h]h }(hjRhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjQubh)}(hhh]jE)}(hdrm_property_blobh]hdrm_property_blob}(hj/RhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj,Rubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj1RmodnameN classnameNjj)}j ]jQc.__extract_blob_lutasbuh1hhjQubj.)}(h h]h }(hjMRhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjQubj'*)}(hj**h]h*}(hj[RhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjQubjE)}(hblobh]hblob}(hjhRhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjQubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjQubj))}(huint32_t *sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hjRhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjRubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjRmodnameN classnameNjj)}j ]jQc.__extract_blob_lutasbuh1hhj}Rubj.)}(h h]h }(hjRhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj}Rubj'*)}(hj**h]h*}(hjRhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj}RubjE)}(hsizeh]hsize}(hjRhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj}Rubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjQubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj\QhhhjnQhMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjXQhhhjnQhMubah}(h]jSQah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjnQhMhjUQhhubjs)}(hhh]h)}(h.Extracts the DRM lut and lut size from a blob.h]h.Extracts the DRM lut and lut size from a blob.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjRhhubah}(h]h ]h"]h$]h&]uh1jrhjUQhhhjnQhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjRjjRjjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``const struct drm_property_blob *blob`` DRM color mgmt property blob ``uint32_t *size`` lut size **Return** DRM LUT or NULLh](h)}(h**Parameters**h]j)}(hj Sh]h Parameters}(hj ShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjSubj)}(hhh](j)}(hF``const struct drm_property_blob *blob`` DRM color mgmt property blob h](j)}(h(``const struct drm_property_blob *blob``h]j)}(hj(Sh]h$const struct drm_property_blob *blob}(hj*ShhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&Subah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj"Subj )}(hhh]h)}(hDRM color mgmt property blobh]hDRM color mgmt property blob}(hjAShhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ShMhj>Subah}(h]h ]h"]h$]h&]uh1j hj"Subeh}(h]h ]h"]h$]h&]uh1jhj=ShMhjSubj)}(h``uint32_t *size`` lut size h](j)}(h``uint32_t *size``h]j)}(hjaSh]huint32_t *size}(hjcShhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_Subah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj[Subj )}(hhh]h)}(hlut sizeh]hlut size}(hjzShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvShMhjwSubah}(h]h ]h"]h$]h&]uh1j hj[Subeh}(h]h ]h"]h$]h&]uh1jhjvShMhjSubeh}(h]h ]h"]h$]h&]uh1jhjSubh)}(h **Return**h]j)}(hjSh]hReturn}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjSubh)}(hDRM LUT or NULLh]hDRM LUT or NULL}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!__extract_blob_lut32 (C function)c.__extract_blob_lut32hNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hjconst struct drm_color_lut32 * __extract_blob_lut32 (const struct drm_property_blob *blob, uint32_t *size)h]j)}(hhconst struct drm_color_lut32 *__extract_blob_lut32(const struct drm_property_blob *blob, uint32_t *size)h](j)}(hjbQh]hconst}(hjShhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjShhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hjShhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjShhhjShMubj)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjShhhjShMubj.)}(h h]h }(hj ThhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjShhhjShMubh)}(hhh]jE)}(hdrm_color_lut32h]hdrm_color_lut32}(hjThhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjTubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjTmodnameN classnameNjj)}j ]j*)}j *__extract_blob_lut32sbc.__extract_blob_lut32asbuh1hhjShhhjShMubj.)}(h h]h }(hjhjShhhjShMubj))}(h6(const struct drm_property_blob *blob, uint32_t *size)h](j))}(h$const struct drm_property_blob *blobh](j)}(hjbQh]hconst}(hjvThhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjrTubj.)}(h h]h }(hjThhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrTubj)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjrTubj.)}(h h]h }(hjThhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrTubh)}(hhh]jE)}(hdrm_property_blobh]hdrm_property_blob}(hjThhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjTubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjTmodnameN classnameNjj)}j ]j7Tc.__extract_blob_lut32asbuh1hhjrTubj.)}(h h]h }(hjThhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrTubj'*)}(hj**h]h*}(hjThhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjrTubjE)}(hblobh]hblob}(hjThhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjrTubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjnTubj))}(huint32_t *sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hjUhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjUubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjUmodnameN classnameNjj)}j ]j7Tc.__extract_blob_lut32asbuh1hhjTubj.)}(h h]h }(hj"UhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjTubj'*)}(hj**h]h*}(hj0UhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjTubjE)}(hsizeh]hsize}(hj=UhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjTubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjnTubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjShhhjShMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjShhhjShMubah}(h]jSah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjShMhjShhubjs)}(hhh]h)}(h.Extracts the DRM lut and lut size from a blob.h]h.Extracts the DRM lut and lut size from a blob.}(hjgUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjdUhhubah}(h]h ]h"]h$]h&]uh1jrhjShhhjShMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjUjjUjjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``const struct drm_property_blob *blob`` DRM color mgmt property blob ``uint32_t *size`` lut size **Return** DRM LUT or NULLh](h)}(h**Parameters**h]j)}(hjUh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj)}(hhh](j)}(hF``const struct drm_property_blob *blob`` DRM color mgmt property blob h](j)}(h(``const struct drm_property_blob *blob``h]j)}(hjUh]h$const struct drm_property_blob *blob}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj )}(hhh]h)}(hDRM color mgmt property blobh]hDRM color mgmt property blob}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1j hjUubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjUubj)}(h``uint32_t *size`` lut size h](j)}(h``uint32_t *size``h]j)}(hjUh]huint32_t *size}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubj )}(hhh]h)}(hlut sizeh]hlut size}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjUubah}(h]h ]h"]h$]h&]uh1j hjUubeh}(h]h ]h"]h$]h&]uh1jhjUhMhjUubeh}(h]h ]h"]h$]h&]uh1jhjUubh)}(h **Return**h]j)}(hjVh]hReturn}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubh)}(hDRM LUT or NULLh]hDRM LUT or NULL}(hj2VhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__is_lut_linear (C function)c.__is_lut_linearhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hEbool __is_lut_linear (const struct drm_color_lut *lut, uint32_t size)h]j)}(hDbool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)h](j))}(hboolh]hbool}(hjaVhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj]Vhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hjpVhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj]VhhhjoVhMubj?)}(h__is_lut_linearh]jE)}(h__is_lut_linearh]h__is_lut_linear}(hjVhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj~Vubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj]VhhhjoVhMubj))}(h0(const struct drm_color_lut *lut, uint32_t size)h](j))}(hconst struct drm_color_lut *luth](j)}(hjbQh]hconst}(hjVhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjVubj.)}(h h]h }(hjVhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjVubj)}(hjh]hstruct}(hjVhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjVubj.)}(h h]h }(hjVhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjVubh)}(hhh]jE)}(h drm_color_luth]h drm_color_lut}(hjVhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjVubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjVmodnameN classnameNjj)}j ]j*)}j *jVsbc.__is_lut_linearasbuh1hhjVubj.)}(h h]h }(hjVhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjVubj'*)}(hj**h]h*}(hjWhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjVubjE)}(hluth]hlut}(hjWhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjVubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjVubj))}(h uint32_t sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hj.WhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj+Wubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj0WmodnameN classnameNjj)}j ]jVc.__is_lut_linearasbuh1hhj'Wubj.)}(h h]h }(hjLWhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj'WubjE)}(hsizeh]hsize}(hjZWhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj'Wubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjVubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj]VhhhjoVhMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjYVhhhjoVhMubah}(h]jTVah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjoVhMhjVVhhubjs)}(hhh]h)}(h4check if the given lut is a linear mapping of valuesh]h4check if the given lut is a linear mapping of values}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWhhubah}(h]h ]h"]h$]h&]uh1jrhjVVhhhjoVhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjWjjWjjjuh1j hhhj^JhNhNubj)}(hXx**Parameters** ``const struct drm_color_lut *lut`` given lut to check values ``uint32_t size`` lut size **Description** It is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES) **Return** True if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h](h)}(h**Parameters**h]j)}(hjWh]h Parameters}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubj)}(hhh](j)}(h>``const struct drm_color_lut *lut`` given lut to check values h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjWh]hconst struct drm_color_lut *lut}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubj )}(hhh]h)}(hgiven lut to check valuesh]hgiven lut to check values}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhMhjWubah}(h]h ]h"]h$]h&]uh1j hjWubeh}(h]h ]h"]h$]h&]uh1jhjWhMhjWubj)}(h``uint32_t size`` lut size h](j)}(h``uint32_t size``h]j)}(hjWh]h uint32_t size}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubj )}(hhh]h)}(hlut sizeh]hlut size}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhMhjXubah}(h]h ]h"]h$]h&]uh1j hjWubeh}(h]h ]h"]h$]h&]uh1jhjXhMhjWubeh}(h]h ]h"]h$]h&]uh1jhjWubh)}(h**Description**h]j)}(hj9Xh]h Description}(hj;XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7Xubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubh)}(hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)h]hIt is considered linear if the lut represents: f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0, MAX_COLOR_LUT_ENTRIES)}(hjOXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubh)}(h **Return**h]j)}(hj`Xh]hReturn}(hjbXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Xubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubh)}(hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.h]hfTrue if the given lut is a linear mapping of values, i.e. it acts like a bypass LUT. Otherwise, false.}(hjvXhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjWubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"__drm_lut_to_dc_gamma (C function)c.__drm_lut_to_dc_gammahNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hdvoid __drm_lut_to_dc_gamma (const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h]j)}(hcvoid __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, struct dc_gamma *gamma, bool is_legacy)h](j))}(hvoidh]hvoid}(hjXhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjXhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hjXhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjXhhhjXhMubj?)}(h__drm_lut_to_dc_gammah]jE)}(h__drm_lut_to_dc_gammah]h__drm_lut_to_dc_gamma}(hjXhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjXubah}(h]h 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]j:ah"]h$]h&]uh1j-hjkYubh)}(hhh]jE)}(hdc_gammah]hdc_gamma}(hjYhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjYubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjYmodnameN classnameNjj)}j ]j7Yc.__drm_lut_to_dc_gammaasbuh1hhjkYubj.)}(h h]h }(hjYhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjkYubj'*)}(hj**h]h*}(hjYhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjkYubjE)}(hgammah]hgamma}(hjYhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjkYubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjXubj))}(hbool is_legacyh](j))}(hjcVh]hbool}(hjYhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjYubj.)}(h h]h }(hjYhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjYubjE)}(h is_legacyh]h is_legacy}(hjYhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjYubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjXubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjXhhhjXhMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjXhhhjXhMubah}(h]jXah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjXhMhjXhhubjs)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hj$ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj!Zhhubah}(h]h ]h"]h$]h&]uh1jrhjXhhhjXhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjhjS[hhhje[hMubj))}(h;(const struct drm_color_lut32 *lut, struct dc_gamma *gamma)h](j))}(h!const struct drm_color_lut32 *luth](j)}(hjbQh]hconst}(hj[hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj[ubj.)}(h h]h }(hj[hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj[ubj)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj[ubj.)}(h h]h }(hj[hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj[ubh)}(hhh]jE)}(hdrm_color_lut32h]hdrm_color_lut32}(hj[hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj[modnameN classnameNjj)}j ]j*)}j *jz[sbc.__drm_lut32_to_dc_gammaasbuh1hhj[ubj.)}(h h]h }(hj[hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj[ubj'*)}(hj**h]h*}(hj[hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj[ubjE)}(hluth]hlut}(hj\hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj[ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[ubj))}(hstruct dc_gamma *gammah](j)}(hjh]hstruct}(hj!\hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj\ubj.)}(h h]h }(hj.\hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\ubh)}(hhh]jE)}(hdc_gammah]hdc_gamma}(hj?\hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj<\ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjA\modnameN classnameNjj)}j ]j[c.__drm_lut32_to_dc_gammaasbuh1hhj\ubj.)}(h h]h }(hj]\hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\ubj'*)}(hj**h]h*}(hjk\hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj\ubjE)}(hgammah]hgamma}(hjx\hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj\ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjS[hhhje[hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjO[hhhje[hMubah}(h]jJ[ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhje[hMhjL[hhubjs)}(hhh]h)}(h&convert the drm_color_lut to dc_gamma.h]h&convert the drm_color_lut to dc_gamma.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj\hhubah}(h]h ]h"]h$]h&]uh1jrhjL[hhhje[hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj\jj\jjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion ``struct dc_gamma *gamma`` DC gamma to set entries **Description** The conversion depends on the size of the lut - whether or not it's legacy.h](h)}(h**Parameters**h]j)}(hj\h]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj\ubj)}(hhh](j)}(hL``const struct drm_color_lut32 *lut`` DRM lookup table for color conversion h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hj\h]h!const struct drm_color_lut32 *lut}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj\ubj )}(hhh]h)}(h%DRM lookup table for color conversionh]h%DRM lookup table for color conversion}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hM hj\ubah}(h]h ]h"]h$]h&]uh1j hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hM hj\ubj)}(h3``struct dc_gamma *gamma`` DC gamma to set entries h](j)}(h``struct dc_gamma *gamma``h]j)}(hj]h]hstruct dc_gamma *gamma}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj]ubj )}(hhh]h)}(hDC gamma to set entriesh]hDC gamma to set entries}(hj5]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1]hM hj2]ubah}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ]h"]h$]h&]uh1jhj1]hM hj\ubeh}(h]h ]h"]h$]h&]uh1jhj\ubh)}(h**Description**h]j)}(hjW]h]h Description}(hjY]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU]ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj\ubh)}(hKThe conversion depends on the size of the lut - whether or not it's legacy.h]hMThe conversion depends on the size of the lut - whether or not it’s legacy.}(hjm]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM hj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#__drm_ctm_to_dc_matrix (C function)c.__drm_ctm_to_dc_matrixhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hXvoid __drm_ctm_to_dc_matrix (const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h]j)}(hWvoid __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](j))}(hvoidh]hvoid}(hj]hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj]hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hj]hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj]hhhj]hMubj?)}(h__drm_ctm_to_dc_matrixh]jE)}(h__drm_ctm_to_dc_matrixh]h__drm_ctm_to_dc_matrix}(hj]hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj]ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj]hhhj]hMubj))}(h<(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix)h](j))}(hconst struct drm_color_ctm *ctmh](j)}(hjbQh]hconst}(hj]hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj]ubj.)}(h h]h }(hj]hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj]ubj)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj]ubj.)}(h h]h }(hj^hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj]ubh)}(hhh]jE)}(h drm_color_ctmh]h drm_color_ctm}(hj^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj^modnameN classnameNjj)}j ]j*)}j *j]sbc.__drm_ctm_to_dc_matrixasbuh1hhj]ubj.)}(h h]h }(hj2^hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj]ubj'*)}(hj**h]h*}(hj@^hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj]ubjE)}(hctmh]hctm}(hjM^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj]ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj]ubj))}(hstruct fixed31_32 *matrixh](j)}(hjh]hstruct}(hjf^hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjb^ubj.)}(h h]h }(hjs^hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjb^ubh)}(hhh]jE)}(h fixed31_32h]h fixed31_32}(hj^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj^modnameN classnameNjj)}j ]j.^c.__drm_ctm_to_dc_matrixasbuh1hhjb^ubj.)}(h h]h }(hj^hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjb^ubj'*)}(hj**h]h*}(hj^hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjb^ubjE)}(hmatrixh]hmatrix}(hj^hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjb^ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj]ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj]hhhj]hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj]hhhj]hMubah}(h]j]ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj]hMhj]hhubjs)}(hhh]h)}(h+converts a DRM CTM to a DC CSC float matrixh]h+converts a DRM CTM to a DC CSC float matrix}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj^hhubah}(h]h ]h"]h$]h&]uh1jrhj]hhhj]hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj^jj^jjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``const struct drm_color_ctm *ctm`` DRM color transformation matrix ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hj _h]h Parameters}(hj _hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj_ubj)}(hhh](j)}(hD``const struct drm_color_ctm *ctm`` DRM color transformation matrix h](j)}(h#``const struct drm_color_ctm *ctm``h]j)}(hj(_h]hconst struct drm_color_ctm *ctm}(hj*_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&_ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj"_ubj )}(hhh]h)}(hDRM color transformation matrixh]hDRM color transformation matrix}(hjA_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=_hMhj>_ubah}(h]h ]h"]h$]h&]uh1j hj"_ubeh}(h]h ]h"]h$]h&]uh1jhj=_hMhj_ubj)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hja_h]hstruct fixed31_32 *matrix}(hjc_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj__ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj[_ubj )}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjz_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv_hMhjw_ubah}(h]h ]h"]h$]h&]uh1j hj[_ubeh}(h]h ]h"]h$]h&]uh1jhjv_hMhj_ubeh}(h]h ]h"]h$]h&]uh1jhj_ubh)}(h**Description**h]j)}(hj_h]h Description}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj_ubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'__drm_ctm_3x4_to_dc_matrix (C function)c.__drm_ctm_3x4_to_dc_matrixhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(h`void __drm_ctm_3x4_to_dc_matrix (const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h]j)}(h_void __drm_ctm_3x4_to_dc_matrix(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](j))}(hvoidh]hvoid}(hj_hhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj_hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM:ubj.)}(h h]h }(hj_hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj_hhhj_hM:ubj?)}(h__drm_ctm_3x4_to_dc_matrixh]jE)}(h__drm_ctm_3x4_to_dc_matrixh]h__drm_ctm_3x4_to_dc_matrix}(hj`hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj_ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj_hhhj_hM:ubj))}(h@(const struct drm_color_ctm_3x4 *ctm, struct fixed31_32 *matrix)h](j))}(h#const struct drm_color_ctm_3x4 *ctmh](j)}(hjbQh]hconst}(hj`hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj`ubj.)}(h h]h }(hj+`hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`ubj)}(hjh]hstruct}(hj9`hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj`ubj.)}(h h]h }(hjF`hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`ubh)}(hhh]jE)}(hdrm_color_ctm_3x4h]hdrm_color_ctm_3x4}(hjW`hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjT`ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjY`modnameN classnameNjj)}j ]j*)}j *j`sbc.__drm_ctm_3x4_to_dc_matrixasbuh1hhj`ubj.)}(h h]h }(hjw`hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`ubj'*)}(hj**h]h*}(hj`hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj`ubjE)}(hctmh]hctm}(hj`hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj`ubj))}(hstruct fixed31_32 *matrixh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj`ubj.)}(h h]h }(hj`hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`ubh)}(hhh]jE)}(h fixed31_32h]h fixed31_32}(hj`hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj`modnameN classnameNjj)}j ]js`c.__drm_ctm_3x4_to_dc_matrixasbuh1hhj`ubj.)}(h h]h }(hj`hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`ubj'*)}(hj**h]h*}(hj`hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj`ubjE)}(hmatrixh]hmatrix}(hjahhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj`ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj_hhhj_hM:ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj_hhhj_hM:ubah}(h]j_ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj_hM:hj_hhubjs)}(hhh]h)}(h/converts a DRM CTM 3x4 to a DC CSC float matrixh]h/converts a DRM CTM 3x4 to a DC CSC float matrix}(hj,ahhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM:hj)ahhubah}(h]h ]h"]h$]h&]uh1jrhj_hhhj_hM:ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjDajjDajjjuh1j hhhj^JhNhNubj)}(h**Parameters** ``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions ``struct fixed31_32 *matrix`` DC CSC float matrix **Description** The matrix needs to be a 3x4 (12 entry) matrix.h](h)}(h**Parameters**h]j)}(hjNah]h Parameters}(hjPahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLaubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM>hjHaubj)}(hhh](j)}(h\``const struct drm_color_ctm_3x4 *ctm`` DRM color transformation matrix with 3x4 dimensions h](j)}(h'``const struct drm_color_ctm_3x4 *ctm``h]j)}(hjmah]h#const struct drm_color_ctm_3x4 *ctm}(hjoahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkaubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM;hjgaubj )}(hhh]h)}(h3DRM color transformation matrix with 3x4 dimensionsh]h3DRM color transformation matrix with 3x4 dimensions}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahM;hjaubah}(h]h ]h"]h$]h&]uh1j hjgaubeh}(h]h ]h"]h$]h&]uh1jhjahM;hjdaubj)}(h2``struct fixed31_32 *matrix`` DC CSC float matrix h](j)}(h``struct fixed31_32 *matrix``h]j)}(hjah]hstruct fixed31_32 *matrix}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM<hjaubj )}(hhh]h)}(hDC CSC float matrixh]hDC CSC float matrix}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahM<hjaubah}(h]h ]h"]h$]h&]uh1j hjaubeh}(h]h ]h"]h$]h&]uh1jhjahM<hjdaubeh}(h]h ]h"]h$]h&]uh1jhjHaubh)}(h**Description**h]j)}(hjah]h Description}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM>hjHaubh)}(h/The matrix needs to be a 3x4 (12 entry) matrix.h]h/The matrix needs to be a 3x4 (12 entry) matrix.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM=hjHaubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_legacy_tf (C function)c.__set_legacy_tfhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(huint __set_legacy_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_legacy_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j))}(hinth]hint}(hj&bhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj"bhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMPubj.)}(h h]h }(hj5bhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj"bhhhj4bhMPubj?)}(h__set_legacy_tfh]jE)}(h__set_legacy_tfh]h__set_legacy_tf}(hjGbhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjCbubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj"bhhhj4bhMPubj))}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j))}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjcbhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj_bubj.)}(h h]h }(hjpbhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj_bubh)}(hhh]jE)}(hdc_transfer_funch]hdc_transfer_func}(hjbhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj~bubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjbmodnameN classnameNjj)}j ]j*)}j *jIbsbc.__set_legacy_tfasbuh1hhj_bubj.)}(h h]h }(hjbhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj_bubj'*)}(hj**h]h*}(hjbhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj_bubjE)}(hfunch]hfunc}(hjbhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj_bubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[bubj))}(hconst struct drm_color_lut *luth](j)}(hjbQh]hconst}(hjbhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjbubj.)}(h h]h }(hjbhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjbubj)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjbubj.)}(h h]h }(hjbhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjbubh)}(hhh]jE)}(h drm_color_luth]h drm_color_lut}(hjchhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj cubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjcmodnameN classnameNjj)}j ]jbc.__set_legacy_tfasbuh1hhjbubj.)}(h h]h }(hj,chhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjbubj'*)}(hj**h]h*}(hj:chhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjbubjE)}(hluth]hlut}(hjGchhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjbubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[bubj))}(huint32_t lut_sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hjcchhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj`cubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjecmodnameN classnameNjj)}j ]jbc.__set_legacy_tfasbuh1hhj\cubj.)}(h h]h }(hjchhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj\cubjE)}(hlut_sizeh]hlut_size}(hjchhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj\cubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[bubj))}(h bool has_romh](j))}(hjcVh]hbool}(hjchhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjcubj.)}(h h]h }(hjchhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjcubjE)}(hhas_romh]hhas_rom}(hjchhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjcubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj[bubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj"bhhhj4bhMPubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjbhhhj4bhMPubah}(h]jbah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj4bhMPhjbhhubjs)}(hhh]h)}(h'Calculates the legacy transfer functionh]h'Calculates the legacy transfer function}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMPhjchhubah}(h]h ]h"]h$]h&]uh1jrhjbhhhj4bhMPubeh}(h]h ](jfunctioneh"]h$]h&]jjjjdjjdjjjuh1j hhhj^JhNhNubj)}(hXa**Parameters** ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut ``bool has_rom`` if ROM can be used for hardcoded curve **Description** Only for sRGB input space **Return** 0 in case of success, -ENOMEM if failsh](h)}(h**Parameters**h]j)}(hjdh]h Parameters}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj dubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThj dubj)}(hhh](j)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hj.dh]hstruct dc_transfer_func *func}(hj0dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,dubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMQhj(dubj )}(hhh]h)}(htransfer functionh]htransfer function}(hjGdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCdhMQhjDdubah}(h]h ]h"]h$]h&]uh1j hj(dubeh}(h]h ]h"]h$]h&]uh1jhjCdhMQhj%dubj)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjgdh]hconst struct drm_color_lut *lut}(hjidhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjedubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMRhjadubj )}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|dhMRhj}dubah}(h]h ]h"]h$]h&]uh1j hjadubeh}(h]h ]h"]h$]h&]uh1jhj|dhMRhj%dubj)}(h-``uint32_t lut_size`` size of respective lut h](j)}(h``uint32_t lut_size``h]j)}(hjdh]huint32_t lut_size}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMShjdubj )}(hhh]h)}(hsize of respective luth]hsize of respective lut}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMShjdubah}(h]h ]h"]h$]h&]uh1j hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMShj%dubj)}(h8``bool has_rom`` if ROM can be used for hardcoded curve h](j)}(h``bool has_rom``h]j)}(hjdh]h bool has_rom}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMThjdubj )}(hhh]h)}(h&if ROM can be used for hardcoded curveh]h&if ROM can be used for hardcoded curve}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMThjdubah}(h]h ]h"]h$]h&]uh1j hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMThj%dubeh}(h]h ]h"]h$]h&]uh1jhj dubh)}(h**Description**h]j)}(hjeh]h Description}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMVhj dubh)}(hOnly for sRGB input spaceh]hOnly for sRGB input space}(hj*ehhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMUhj dubh)}(h **Return**h]j)}(hj;eh]hReturn}(hj=ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9eubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMWhj dubh)}(h&0 in case of success, -ENOMEM if failsh]h&0 in case of success, -ENOMEM if fails}(hjQehhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMXhj dubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_output_tf (C function)c.__set_output_tfhNtauh1jhj^JhhhNhNubj )}(hhh](j)}(huint __set_output_tf (struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h]j)}(htint __set_output_tf(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j))}(hinth]hint}(hjehhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj|ehhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMxubj.)}(h h]h }(hjehhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj|ehhhjehMxubj?)}(h__set_output_tfh]jE)}(h__set_output_tfh]h__set_output_tf}(hjehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjeubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj|ehhhjehMxubj))}(ha(struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size, bool has_rom)h](j))}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjehhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjeubj.)}(h h]h }(hjehhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjeubh)}(hhh]jE)}(hdc_transfer_funch]hdc_transfer_func}(hjehhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjeubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjemodnameN classnameNjj)}j ]j*)}j *jesbc.__set_output_tfasbuh1hhjeubj.)}(h h]h }(hjehhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjeubj'*)}(hj**h]h*}(hj fhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjeubjE)}(hfunch]hfunc}(hjfhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjeubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjeubj))}(hconst struct drm_color_lut *luth](j)}(hjbQh]hconst}(hj/fhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj+fubj.)}(h h]h }(hjhjhhhhjhhMubj))}(hc(struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size, bool has_rom)h](j))}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhubj.)}(h h]h }(hjhhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhubh)}(hhh]jE)}(hdc_transfer_funch]hdc_transfer_func}(hjihhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj iubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjimodnameN classnameNjj)}j ]j*)}j *jhsbc.__set_output_tf_32asbuh1hhjhubj.)}(h h]h }(hj.ihhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhubj'*)}(hj**h]h*}(hjhjkhhhjkhMubj))}(ho(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut *lut, uint32_t lut_size)h](j))}(hstruct dc_color_caps *capsh](j)}(hjh]hstruct}(hj#lhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjlubj.)}(h h]h }(hj0lhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjlubh)}(hhh]jE)}(h dc_color_capsh]h dc_color_caps}(hjAlhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj>lubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjClmodnameN classnameNjj)}j ]j*)}j *j lsbc.__set_input_tfasbuh1hhjlubj.)}(h h]h }(hjalhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjlubj'*)}(hj**h]h*}(hjolhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjlubjE)}(hcapsh]hcaps}(hj|lhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjlubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjlubj))}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjlubj.)}(h h]h }(hjlhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjlubh)}(hhh]jE)}(hdc_transfer_funch]hdc_transfer_func}(hjlhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjlubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjlmodnameN classnameNjj)}j ]j]lc.__set_input_tfasbuh1hhjlubj.)}(h h]h }(hjlhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjlubj'*)}(hj**h]h*}(hjlhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjlubjE)}(hfunch]hfunc}(hjlhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjlubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjlubj))}(hconst struct drm_color_lut *luth](j)}(hjbQh]hconst}(hjmhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjmubj.)}(h h]h }(hjmhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjmubj)}(hjh]hstruct}(hj mhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjmubj.)}(h h]h }(hj-mhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjmubh)}(hhh]jE)}(h drm_color_luth]h drm_color_lut}(hj>mhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj;mubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj@mmodnameN classnameNjj)}j ]j]lc.__set_input_tfasbuh1hhjmubj.)}(h h]h }(hj\mhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjmubj'*)}(hj**h]h*}(hjjmhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjmubjE)}(hluth]hlut}(hjwmhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjmubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjlubj))}(huint32_t lut_sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hjmhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjmubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjmmodnameN classnameNjj)}j ]j]lc.__set_input_tfasbuh1hhjmubj.)}(h h]h }(hjmhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjmubjE)}(hlut_sizeh]hlut_size}(hjmhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjmubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjlubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjkhhhjkhMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjkhhhjkhMubah}(h]jkah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjkhMhjkhhubjs)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjmhhubah}(h]h ]h"]h$]h&]uh1jrhjkhhhjkhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjnjjnjjjuh1j hhhj^JhNhNubj)}(hX4**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hj nh]h Parameters}(hj nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj nubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjnubj)}(hhh](j)}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hj*nh]hstruct dc_color_caps *caps}(hj,nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(nubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj$nubj )}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hjCnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?nhMhj@nubah}(h]h ]h"]h$]h&]uh1j hj$nubeh}(h]h ]h"]h$]h&]uh1jhj?nhMhj!nubj)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjcnh]hstruct dc_transfer_func *func}(hjenhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjanubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj]nubj )}(hhh]h)}(htransfer functionh]htransfer function}(hj|nhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxnhMhjynubah}(h]h ]h"]h$]h&]uh1j hj]nubeh}(h]h ]h"]h$]h&]uh1jhjxnhMhj!nubj)}(hN``const struct drm_color_lut *lut`` lookup table that defines the color space h](j)}(h#``const struct drm_color_lut *lut``h]j)}(hjnh]hconst struct drm_color_lut *lut}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjnubj )}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1j hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhj!nubj)}(h.``uint32_t lut_size`` size of respective lut. h](j)}(h``uint32_t lut_size``h]j)}(hjnh]huint32_t lut_size}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjnubj )}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1j hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhj!nubeh}(h]h ]h"]h$]h&]uh1jhjnubh)}(h **Return**h]j)}(hjoh]hReturn}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjnubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hj&ohhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjnubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j__set_input_tf_32 (C function)c.__set_input_tf_32hNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hint __set_input_tf_32 (struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h]j)}(hint __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h](j))}(hinth]hint}(hjUohhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjQohhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM3ubj.)}(h h]h }(hjdohhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjQohhhjcohM3ubj?)}(h__set_input_tf_32h]jE)}(h__set_input_tf_32h]h__set_input_tf_32}(hjvohhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjroubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjQohhhjcohM3ubj))}(hq(struct dc_color_caps *caps, struct dc_transfer_func *func, const struct drm_color_lut32 *lut, uint32_t lut_size)h](j))}(hstruct dc_color_caps *capsh](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjoubj.)}(h h]h }(hjohhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjoubh)}(hhh]jE)}(h dc_color_capsh]h dc_color_caps}(hjohhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjoubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjomodnameN classnameNjj)}j ]j*)}j *jxosbc.__set_input_tf_32asbuh1hhjoubj.)}(h h]h }(hjohhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjoubj'*)}(hj**h]h*}(hjohhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjoubjE)}(hcapsh]hcaps}(hjohhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjoubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjoubj))}(hstruct dc_transfer_func *funch](j)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjpubj.)}(h h]h }(hjphhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjpubh)}(hhh]jE)}(hdc_transfer_funch]hdc_transfer_func}(hj"phhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj$pmodnameN classnameNjj)}j ]joc.__set_input_tf_32asbuh1hhjpubj.)}(h h]h }(hj@phhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjpubj'*)}(hj**h]h*}(hjNphhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjpubjE)}(hfunch]hfunc}(hj[phhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjpubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjoubj))}(h!const struct drm_color_lut32 *luth](j)}(hjbQh]hconst}(hjtphhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjppubj.)}(h h]h }(hjphhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjppubj)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjppubj.)}(h h]h }(hjphhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjppubh)}(hhh]jE)}(hdrm_color_lut32h]hdrm_color_lut32}(hjphhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjpmodnameN classnameNjj)}j ]joc.__set_input_tf_32asbuh1hhjppubj.)}(h h]h }(hjphhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjppubj'*)}(hj**h]h*}(hjphhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjppubjE)}(hluth]hlut}(hjphhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjppubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjoubj))}(huint32_t lut_sizeh](h)}(hhh]jE)}(huint32_th]huint32_t}(hjqhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjqmodnameN classnameNjj)}j ]joc.__set_input_tf_32asbuh1hhjpubj.)}(h h]h }(hj qhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjpubjE)}(hlut_sizeh]hlut_size}(hj.qhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjpubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjoubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjQohhhjcohM3ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjMohhhjcohM3ubah}(h]jHoah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjcohM3hjJohhubjs)}(hhh]h)}(hEcalculates the input transfer function based on expected input space.h]hEcalculates the input transfer function based on expected input space.}(hjXqhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM3hjUqhhubah}(h]h ]h"]h$]h&]uh1jrhjJohhhjcohM3ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjpqjjpqjjjuh1j hhhj^JhNhNubj)}(hX6**Parameters** ``struct dc_color_caps *caps`` dc color capabilities ``struct dc_transfer_func *func`` transfer function ``const struct drm_color_lut32 *lut`` lookup table that defines the color space ``uint32_t lut_size`` size of respective lut. **Return** 0 in case of success. -ENOMEM if fails.h](h)}(h**Parameters**h]j)}(hjzqh]h Parameters}(hj|qhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxqubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7hjtqubj)}(hhh](j)}(h5``struct dc_color_caps *caps`` dc color capabilities h](j)}(h``struct dc_color_caps *caps``h]j)}(hjqh]hstruct dc_color_caps *caps}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM5hjqubj )}(hhh]h)}(hdc color capabilitiesh]hdc color capabilities}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhM5hjqubah}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ]h"]h$]h&]uh1jhjqhM5hjqubj)}(h4``struct dc_transfer_func *func`` transfer function h](j)}(h!``struct dc_transfer_func *func``h]j)}(hjqh]hstruct dc_transfer_func *func}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM6hjqubj )}(hhh]h)}(htransfer functionh]htransfer function}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhM6hjqubah}(h]h ]h"]h$]h&]uh1j hjqubeh}(h]h ]h"]h$]h&]uh1jhjqhM6hjqubj)}(hP``const struct drm_color_lut32 *lut`` lookup table that defines the color space h](j)}(h%``const struct drm_color_lut32 *lut``h]j)}(hj rh]h!const struct drm_color_lut32 *lut}(hj rhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj rubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM7hjrubj )}(hhh]h)}(h)lookup table that defines the color spaceh]h)lookup table that defines the color space}(hj$rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj rhM7hj!rubah}(h]h ]h"]h$]h&]uh1j hjrubeh}(h]h ]h"]h$]h&]uh1jhj rhM7hjqubj)}(h.``uint32_t lut_size`` size of respective lut. h](j)}(h``uint32_t lut_size``h]j)}(hjDrh]huint32_t lut_size}(hjFrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBrubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM8hj>rubj )}(hhh]h)}(hsize of respective lut.h]hsize of respective lut.}(hj]rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYrhM8hjZrubah}(h]h ]h"]h$]h&]uh1j hj>rubeh}(h]h ]h"]h$]h&]uh1jhjYrhM8hjqubeh}(h]h ]h"]h$]h&]uh1jhjtqubh)}(h **Return**h]j)}(hjrh]hReturn}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}rubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM:hjtqubh)}(h'0 in case of success. -ENOMEM if fails.h]h'0 in case of success. -ENOMEM if fails.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chM:hjtqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(amdgpu_dm_verify_lut3d_size (C function)c.amdgpu_dm_verify_lut3d_sizehNtauh1jhj^JhhhNhNubj )}(hhh](j)}(haint amdgpu_dm_verify_lut3d_size (struct amdgpu_device *adev, struct drm_plane_state *plane_state)h]j)}(h`int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](j))}(hinth]hint}(hjrhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjrhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMEubj.)}(h h]h }(hjrhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrhhhjrhMEubj?)}(hamdgpu_dm_verify_lut3d_sizeh]jE)}(hamdgpu_dm_verify_lut3d_sizeh]hamdgpu_dm_verify_lut3d_size}(hjrhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjrubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjrhhhjrhMEubj))}(hA(struct amdgpu_device *adev, struct drm_plane_state *plane_state)h](j))}(hstruct amdgpu_device *adevh](j)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjrubj.)}(h h]h }(hjshhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrubh)}(hhh]jE)}(h amdgpu_deviceh]h amdgpu_device}(hjshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj!smodnameN classnameNjj)}j ]j*)}j *jrsbc.amdgpu_dm_verify_lut3d_sizeasbuh1hhjrubj.)}(h h]h }(hj?shhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjrubj'*)}(hj**h]h*}(hjMshhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjrubjE)}(hadevh]hadev}(hjZshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjrubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjrubj))}(h#struct drm_plane_state *plane_stateh](j)}(hjh]hstruct}(hjsshhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjosubj.)}(h h]h }(hjshhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjosubh)}(hhh]jE)}(hdrm_plane_stateh]hdrm_plane_state}(hjshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjsubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjsmodnameN classnameNjj)}j ]j;sc.amdgpu_dm_verify_lut3d_sizeasbuh1hhjosubj.)}(h h]h }(hjshhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjosubj'*)}(hj**h]h*}(hjshhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjosubjE)}(h plane_stateh]h plane_state}(hjshhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjosubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjrubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjrhhhjrhMEubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjrhhhjrhMEubah}(h]jrah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjrhMEhjrhhubjs)}(hhh]h)}(hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported sizeh]hZverifies if 3D LUT is supported and if user shaper and 3D LUTs match the hw supported size}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMEhjshhubah}(h]h ]h"]h$]h&]uh1jrhjrhhhjrhMEubeh}(h]h ](jfunctioneh"]h$]h&]jjjj tjj tjjjuh1j hhhj^JhNhNubj)}(hXX**Parameters** ``struct amdgpu_device *adev`` amdgpu device ``struct drm_plane_state *plane_state`` the DRM plane state **Description** Verifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size. **Return** 0 on success. -EINVAL if lut size are invalid.h](h)}(h**Parameters**h]j)}(hjth]h Parameters}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMIhjtubj)}(hhh](j)}(h-``struct amdgpu_device *adev`` amdgpu device h](j)}(h``struct amdgpu_device *adev``h]j)}(hj5th]hstruct amdgpu_device *adev}(hj7thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3tubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMGhj/tubj )}(hhh]h)}(h amdgpu deviceh]h amdgpu device}(hjNthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJthMGhjKtubah}(h]h ]h"]h$]h&]uh1j hj/tubeh}(h]h ]h"]h$]h&]uh1jhjJthMGhj,tubj)}(h<``struct drm_plane_state *plane_state`` the DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hjnth]h#struct drm_plane_state *plane_state}(hjpthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjltubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMHhjhtubj )}(hhh]h)}(hthe DRM plane stateh]hthe DRM plane state}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMHhjtubah}(h]h ]h"]h$]h&]uh1j hjhtubeh}(h]h ]h"]h$]h&]uh1jhjthMHhj,tubeh}(h]h ]h"]h$]h&]uh1jhjtubh)}(h**Description**h]j)}(hjth]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMJhjtubh)}(hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.h]hVerifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or newer) and if the user shaper and 3D LUTs match the supported size.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMIhjtubh)}(h **Return**h]j)}(hjth]hReturn}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMLhjtubh)}(h.0 on success. -EINVAL if lut size are invalid.h]h.0 on success. -EINVAL if lut size are invalid.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMMhjtubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'amdgpu_dm_verify_lut_sizes (C function)c.amdgpu_dm_verify_lut_sizeshNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hHint amdgpu_dm_verify_lut_sizes (const struct drm_crtc_state *crtc_state)h]j)}(hGint amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)h](j))}(hinth]hint}(hjuhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjuhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMrubj.)}(h h]h }(hj$uhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjuhhhj#uhMrubj?)}(hamdgpu_dm_verify_lut_sizesh]jE)}(hamdgpu_dm_verify_lut_sizesh]hamdgpu_dm_verify_lut_sizes}(hj6uhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj2uubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjuhhhj#uhMrubj))}(h)(const struct drm_crtc_state *crtc_state)h]j))}(h'const struct drm_crtc_state *crtc_stateh](j)}(hjbQh]hconst}(hjRuhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjNuubj.)}(h h]h }(hj_uhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjNuubj)}(hjh]hstruct}(hjmuhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjNuubj.)}(h h]h }(hjzuhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjNuubh)}(hhh]jE)}(hdrm_crtc_stateh]hdrm_crtc_state}(hjuhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjuubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjumodnameN classnameNjj)}j ]j*)}j *j8usbc.amdgpu_dm_verify_lut_sizesasbuh1hhjNuubj.)}(h h]h }(hjuhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjNuubj'*)}(hj**h]h*}(hjuhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjNuubjE)}(h crtc_stateh]h crtc_state}(hjuhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjNuubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjJuubah}(h]h ]h"]h$]h&]j\j]uh1j)hjuhhhj#uhMrubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj uhhhj#uhMrubah}(h]juah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj#uhMrhj uhhubjs)}(hhh]h)}(h1verifies if DRM luts match the hw supported sizesh]h1verifies if DRM luts match the hw supported sizes}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMrhjuhhubah}(h]h ]h"]h$]h&]uh1jrhj uhhhj#uhMrubeh}(h]h ](jfunctioneh"]h$]h&]jjjjvjjvjjjuh1j hhhj^JhNhNubj)}(hX **Parameters** ``const struct drm_crtc_state *crtc_state`` the DRM CRTC state **Description** Verifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size. **Return** 0 on success. -EINVAL if any lut sizes are invalid.h](h)}(h**Parameters**h]j)}(hjvh]h Parameters}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMvhj vubj)}(hhh]j)}(h?``const struct drm_crtc_state *crtc_state`` the DRM CRTC state h](j)}(h+``const struct drm_crtc_state *crtc_state``h]j)}(hj1vh]h'const struct drm_crtc_state *crtc_state}(hj3vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/vubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMshj+vubj )}(hhh]h)}(hthe DRM CRTC stateh]hthe DRM CRTC state}(hjJvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFvhMshjGvubah}(h]h ]h"]h$]h&]uh1j hj+vubeh}(h]h ]h"]h$]h&]uh1jhjFvhMshj(vubah}(h]h ]h"]h$]h&]uh1jhj vubh)}(h**Description**h]j)}(hjlvh]h Description}(hjnvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjvubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMuhj vubh)}(hgVerifies that the Degamma and Gamma LUTs attached to the :c:type:`crtc_state` are of the expected size.h](h9Verifies that the Degamma and Gamma LUTs attached to the }(hjvhhhNhNubh)}(h:c:type:`crtc_state`h]j)}(hjvh]h crtc_state}(hjvhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j crtc_stateuh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMthjvubh are of the expected size.}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjvhMthj vubh)}(h **Return**h]j)}(hjvh]hReturn}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMwhj vubh)}(h30 on success. -EINVAL if any lut sizes are invalid.h]h30 on success. -EINVAL if any lut sizes are invalid.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMxhj vubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j,amdgpu_dm_check_crtc_color_mgmt (C function)!c.amdgpu_dm_check_crtc_color_mgmthNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hQint amdgpu_dm_check_crtc_color_mgmt (struct dm_crtc_state *crtc, bool check_only)h]j)}(hPint amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, bool check_only)h](j))}(hinth]hint}(hjvhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjvhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hj whhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjvhhhj whMubj?)}(hamdgpu_dm_check_crtc_color_mgmth]jE)}(hamdgpu_dm_check_crtc_color_mgmth]hamdgpu_dm_check_crtc_color_mgmt}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjwubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjvhhhj whMubj))}(h-(struct dm_crtc_state *crtc, bool check_only)h](j))}(hstruct dm_crtc_state *crtch](j)}(hjh]hstruct}(hj8whhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj4wubj.)}(h h]h }(hjEwhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4wubh)}(hhh]jE)}(h dm_crtc_stateh]h dm_crtc_state}(hjVwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjSwubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjXwmodnameN classnameNjj)}j ]j*)}j *jwsb!c.amdgpu_dm_check_crtc_color_mgmtasbuh1hhj4wubj.)}(h h]h }(hjvwhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4wubj'*)}(hj**h]h*}(hjwhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj4wubjE)}(hcrtch]hcrtc}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj4wubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj0wubj))}(hbool check_onlyh](j))}(hjcVh]hbool}(hjwhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjwubj.)}(h h]h }(hjwhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjwubjE)}(h check_onlyh]h check_only}(hjwhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjwubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj0wubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjvhhhj whMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjvhhhj whMubah}(h]jvah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj whMhjvhhubjs)}(hhh]h)}(h0Check if DRM color props are programmable by DC.h]h0Check if DRM color props are programmable by DC.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jrhjvhhhj whMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjxjjxjjjuh1j hhhj^JhNhNubj)}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``bool check_only`` only check color state without update dc stream **Description** This function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block. The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM. For supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together. **Return** 0 on success. Error code if validation fails.h](h)}(h**Parameters**h]j)}(hjxh]h Parameters}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubj)}(hhh](j)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hj0xh]hstruct dm_crtc_state *crtc}(hj2xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.xubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj*xubj )}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hjIxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjExhMhjFxubah}(h]h ]h"]h$]h&]uh1j hj*xubeh}(h]h ]h"]h$]h&]uh1jhjExhMhj'xubj)}(hD``bool check_only`` only check color state without update dc stream h](j)}(h``bool check_only``h]j)}(hjixh]hbool check_only}(hjkxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgxubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjcxubj )}(hhh]h)}(h/only check color state without update dc streamh]h/only check color state without update dc stream}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~xhMhjxubah}(h]h ]h"]h$]h&]uh1j hjcxubeh}(h]h ]h"]h$]h&]uh1jhj~xhMhj'xubeh}(h]h ]h"]h$]h&]uh1jhj xubh)}(h**Description**h]j)}(hjxh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubh)}(hXThis function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block.h]hXThis function just verifies CRTC LUT sizes, if there is enough space for output transfer function and if its parameters can be calculated by AMD color module. It also adjusts some settings for programming CRTC degamma at plane stage, using plane DGM block.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubh)}(h~The RGM block is typically more fully featured and accurate across all ASICs - DCE can't support a custom non-linear CRTC DGM.h]hThe RGM block is typically more fully featured and accurate across all ASICs - DCE can’t support a custom non-linear CRTC DGM.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubh)}(hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together.h]hFor supporting both plane level color management and CRTC level color management at once we have to either restrict the usage of some CRTC properties or blend adjustments together.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubh)}(h **Return**h]j)}(hjxh]hReturn}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubh)}(h-0 on success. Error code if validation fails.h]h-0 on success. Error code if validation fails.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj xubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j-amdgpu_dm_update_crtc_color_mgmt (C function)"c.amdgpu_dm_update_crtc_color_mgmthNtauh1jhj^JhhhNhNubj )}(hhh](j)}(hAint amdgpu_dm_update_crtc_color_mgmt (struct dm_crtc_state *crtc)h]j)}(h@int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)h](j))}(hinth]hint}(hj.yhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj*yhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMubj.)}(h h]h }(hj=yhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj*yhhhjhj*yhhhjhjB{hhhjT{hMubj))}(hh(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state)h](j))}(hstruct dm_crtc_state *crtch](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj{ubj.)}(h h]h }(hj{hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj{ubh)}(hhh]jE)}(h dm_crtc_stateh]h dm_crtc_state}(hj{hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj{modnameN classnameNjj)}j ]j*)}j *ji{sb#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhj{ubj.)}(h h]h }(hj{hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj{ubj'*)}(hj**h]h*}(hj{hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj{ubjE)}(hcrtch]hcrtc}(hj{hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj{ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj{{ubj))}(h#struct drm_plane_state *plane_stateh](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj{ubj.)}(h h]h }(hj|hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj{ubh)}(hhh]jE)}(hdrm_plane_stateh]hdrm_plane_state}(hj|hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj|ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj|modnameN classnameNjj)}j ]j{#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhj{ubj.)}(h h]h }(hj1|hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj{ubj'*)}(hj**h]h*}(hj?|hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj{ubjE)}(h plane_stateh]h plane_state}(hjL|hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj{ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj{{ubj))}(h%struct dc_plane_state *dc_plane_stateh](j)}(hjh]hstruct}(hje|hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhja|ubj.)}(h h]h }(hjr|hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hja|ubh)}(hhh]jE)}(hdc_plane_stateh]hdc_plane_state}(hj|hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj|ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj|modnameN classnameNjj)}j ]j{#c.amdgpu_dm_update_plane_color_mgmtasbuh1hhja|ubj.)}(h h]h }(hj|hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hja|ubj'*)}(hj**h]h*}(hj|hhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hja|ubjE)}(hdc_plane_stateh]hdc_plane_state}(hj|hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhja|ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj{{ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjB{hhhjT{hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj>{hhhjT{hMubah}(h]j9{ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjT{hMhj;{hhubjs)}(hhh]h)}(h&Maps DRM color management to DC plane.h]h&Maps DRM color management to DC plane.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj|hhubah}(h]h ]h"]h$]h&]uh1jrhj;{hhhjT{hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj|jj|jjjuh1j hhhj^JhNhNubj)}(hX**Parameters** ``struct dm_crtc_state *crtc`` amdgpu_dm crtc state ``struct drm_plane_state *plane_state`` DRM plane state ``struct dc_plane_state *dc_plane_state`` target DC surface **Description** Update the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management. **Return** 0 on success. -ENOMEM if mem allocation fails.h](h)}(h**Parameters**h]j)}(hj}h]h Parameters}(hj }hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubj)}(hhh](j)}(h4``struct dm_crtc_state *crtc`` amdgpu_dm crtc state h](j)}(h``struct dm_crtc_state *crtc``h]j)}(hj'}h]hstruct dm_crtc_state *crtc}(hj)}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%}ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj!}ubj )}(hhh]h)}(hamdgpu_dm crtc stateh]hamdgpu_dm crtc state}(hj@}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<}hMhj=}ubah}(h]h ]h"]h$]h&]uh1j hj!}ubeh}(h]h ]h"]h$]h&]uh1jhj<}hMhj}ubj)}(h8``struct drm_plane_state *plane_state`` DRM plane state h](j)}(h'``struct drm_plane_state *plane_state``h]j)}(hj`}h]h#struct drm_plane_state *plane_state}(hjb}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^}ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhjZ}ubj )}(hhh]h)}(hDRM plane stateh]hDRM plane state}(hjy}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju}hMhjv}ubah}(h]h ]h"]h$]h&]uh1j hjZ}ubeh}(h]h ]h"]h$]h&]uh1jhju}hMhj}ubj)}(h<``struct dc_plane_state *dc_plane_state`` target DC surface h](j)}(h)``struct dc_plane_state *dc_plane_state``h]j)}(hj}h]h%struct dc_plane_state *dc_plane_state}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubj )}(hhh]h)}(htarget DC surfaceh]htarget DC surface}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1j hj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj}ubeh}(h]h ]h"]h$]h&]uh1jhj}ubh)}(h**Description**h]j)}(hj}h]h Description}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubh)}(hUpdate the underlying dc_stream_state's input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.h]hUpdate the underlying dc_stream_state’s input transfer function (ITF) in preparation for hardware commit. The transfer function used depends on the preparation done on the stream for color management.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubh)}(h **Return**h]j)}(hj}h]hReturn}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubh)}(h.0 on success. -ENOMEM if mem allocation fails.h]h.0 on success. -ENOMEM if mem allocation fails.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:50: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.chMhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^JhhhNhNubh)}(hhh](h)}(h-DC Color Capabilities between DCN generationsh]h-DC Color Capabilities between DCN generations}(hj*~hhhNhNubah}(h]h ]h"]h$]h&]hjuh1hhj'~hhhhhK7ubh)}(hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.h]hX)DRM/KMS framework defines three CRTC color correction properties: degamma, color transformation matrix (CTM) and gamma, and two properties for degamma and gamma LUT sizes. AMD DC programs some of the color correction features pre-blending but DRM/KMS has not per-plane color correction properties.}(hj8~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hj'~hhubh)}(hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.h]hX?In general, the DRM CRTC color properties are programmed to DC, as follows: CRTC gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps available in the hw is not currently exposed by DRM interface and are bypassed.}(hjF~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj'~hhubh)}(h'**Color management caps (DPP and MPC)**h]j)}(hjV~h]h#Color management caps (DPP and MPC)}(hjX~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT~ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj'~hhubh)}(hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.h]hXaModules/color calculates various color operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. Therefore, we abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities.}(hjl~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:68: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj'~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_SURFACES (C macro)c.MAX_SURFACEShNtauh1jhj'~hhhNhNubj )}(hhh](j)}(h MAX_SURFACESh]j)}(h MAX_SURFACESh]j?)}(h MAX_SURFACESh]jE)}(hj~h]h MAX_SURFACES}(hj~hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj~ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj~hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKEubah}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj~hhhj~hKEubah}(h]j~ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj~hKEhj~hhubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhj~hhhj~hKEubeh}(h]h ](jmacroeh"]h$]h&]jjjj~jj~jjjuh1j hhhj'~hNhNubh)}(h``MAX_SURFACES``h]j)}(hj~h]h MAX_SURFACES}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKGhj'~hhubh block_quote)}(hRrepresentative of the upper bound of surfaces that can be piped to a single CRTC h]h)}(hPrepresentative of the upper bound of surfaces that can be piped to a single CRTCh]hPrepresentative of the upper bound of surfaces that can be piped to a single CRTC}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKEhj~ubah}(h]h ]h"]h$]h&]uh1j~hj~hKEhj'~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jMAX_PLANES (C macro) c.MAX_PLANEShNtauh1jhj'~hhhNhNubj )}(hhh](j)}(h MAX_PLANESh]j)}(h MAX_PLANESh]j?)}(h MAX_PLANESh]jE)}(hjh]h MAX_PLANES}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKIubah}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj hhhj+hKIubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj+hKIhj hhubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhj hhhj+hKIubeh}(h]h ](jmacroeh"]h$]h&]jjjjDjjDjjjuh1j hhhj'~hNhNubh)}(h``MAX_PLANES``h]j)}(hjJh]h MAX_PLANES}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKKhj'~hhubj~)}(hLrepresentative of the upper bound of planes that are supported by the HW h]h)}(hHrepresentative of the upper bound of planes that are supported by the HWh]hHrepresentative of the upper bound of planes that are supported by the HW}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKIhj`ubah}(h]h ]h"]h$]h&]uh1j~hjrhKIhj'~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jrom_curve_caps (C struct)c.rom_curve_capshNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hrom_curve_capsh]j)}(hstruct rom_curve_capsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKNubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhKNubj?)}(hrom_curve_capsh]jE)}(hjh]hrom_curve_caps}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhKNubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhKNubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhKNhjhhubjs)}(hhh]h)}(h9predefined transfer function caps for degamma and regammah]h9predefined transfer function caps for degamma and regamma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhjhKNubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhj'~hNhNubj)}(hX**Definition**:: struct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; }; **Members** ``srgb`` RGB color space transfer func ``bt2020`` BT.2020 transfer func ``gamma2_2`` standard gamma ``pq`` perceptual quantizer transfer function ``hlg`` hybrid log–gamma transfer functionh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };h]hstruct rom_curve_caps { uint16_t srgb : 1; uint16_t bt2020 : 1; uint16_t gamma2_2 : 1; uint16_t pq : 1; uint16_t hlg : 1; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubh)}(h **Members**h]j)}(hj"h]hMembers}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hhh](j)}(h'``srgb`` RGB color space transfer func h](j)}(h``srgb``h]j)}(hjAh]hsrgb}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj;ubj )}(hhh]h)}(hRGB color space transfer funch]hRGB color space transfer func}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhKhjWubah}(h]h ]h"]h$]h&]uh1j hj;ubeh}(h]h ]h"]h$]h&]uh1jhjVhKhj8ubj)}(h!``bt2020`` BT.2020 transfer func h](j)}(h ``bt2020``h]j)}(hjzh]hbt2020}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjtubj )}(hhh]h)}(hBT.2020 transfer funch]hBT.2020 transfer func}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjtubeh}(h]h ]h"]h$]h&]uh1jhjhKhj8ubj)}(h``gamma2_2`` standard gamma h](j)}(h ``gamma2_2``h]j)}(hjh]hgamma2_2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(hstandard gammah]hstandard gamma}(hj̀hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjȀhKhjɀubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjȀhKhj8ubj)}(h.``pq`` perceptual quantizer transfer function h](j)}(h``pq``h]j)}(hjh]hpq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h&perceptual quantizer transfer functionh]h&perceptual quantizer transfer function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj8ubj)}(h,``hlg`` hybrid log–gamma transfer functionh](j)}(h``hlg``h]j)}(hj%h]hhlg}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h$hybrid log–gamma transfer functionh]h$hybrid log–gamma transfer function}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj;ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj:hKhj8ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpp_color_caps (C struct)c.dpp_color_capshNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hdpp_color_capsh]j)}(hstruct dpp_color_capsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj{hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj{hhhjhKubj?)}(hdpp_color_capsh]jE)}(hjyh]hdpp_color_caps}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj{hhhjhKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjwhhhjhKubah}(h]jrah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhKhjthhubjs)}(hhh]h)}(h=color pipeline capabilities for display pipe and plane blocksh]h=color pipeline capabilities for display pipe and plane blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jrhjthhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjفjjفjjjuh1j hhhj'~hNhNubj)}(hX**Definition**:: struct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; }; **Members** ``dcn_arch`` all DCE generations treated the same ``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup ``icsc`` input color space conversion ``dgam_ram`` programmable degamma LUT ``post_csc`` post color space conversion, before gamut remap ``gamma_corr`` degamma correction ``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag ``ogam_ram`` programmable out/blend gamma LUT ``ocsc`` output color space conversion ``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes ``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj݁ubj)}(hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };h]hXstruct dpp_color_caps { uint16_t dcn_arch : 1; uint16_t input_lut_shared : 1; uint16_t icsc : 1; uint16_t dgam_ram : 1; uint16_t post_csc : 1; uint16_t gamma_corr : 1; uint16_t hw_3d_lut : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj݁ubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj݁ubj)}(hhh](j)}(h2``dcn_arch`` all DCE generations treated the same h](j)}(h ``dcn_arch``h]j)}(hj.h]hdcn_arch}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj(ubj )}(hhh]h)}(h$all DCE generations treated the sameh]h$all DCE generations treated the same}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChKhjDubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChKhj%ubj)}(hj``input_lut_shared`` shared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup h](j)}(h``input_lut_shared``h]j)}(hjgh]hinput_lut_shared}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjaubj )}(hhh]h)}(hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookuph]hTshared with DGAM. Input LUT is different than most LUTs, just plain 256-entry lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj}ubah}(h]h ]h"]h$]h&]uh1j hjaubeh}(h]h ]h"]h$]h&]uh1jhj|hKhj%ubj)}(h&``icsc`` input color space conversion h](j)}(h``icsc``h]j)}(hjh]hicsc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(hinput color space conversionh]hinput color space conversion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj%ubj)}(h&``dgam_ram`` programmable degamma LUT h](j)}(h ``dgam_ram``h]j)}(hjڂh]hdgam_ram}(hj܂hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj؂ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjԂubj )}(hhh]h)}(hprogrammable degamma LUTh]hprogrammable degamma LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjԂubeh}(h]h ]h"]h$]h&]uh1jhjhKhj%ubj)}(h=``post_csc`` post color space conversion, before gamut remap h](j)}(h ``post_csc``h]j)}(hjh]hpost_csc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj ubj )}(hhh]h)}(h/post color space conversion, before gamut remaph]h/post color space conversion, before gamut remap}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hKhj)ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj(hKhj%ubj)}(h"``gamma_corr`` degamma correction h](j)}(h``gamma_corr``h]j)}(hjLh]h gamma_corr}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjFubj )}(hhh]h)}(hdegamma correctionh]hdegamma correction}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahKhjbubah}(h]h ]h"]h$]h&]uh1j hjFubeh}(h]h ]h"]h$]h&]uh1jhjahKhj%ubj)}(hz``hw_3d_lut`` 3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag h](j)}(h ``hw_3d_lut``h]j)}(hjh]h hw_3d_lut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flagh]hk3D LUT support. It implies a shaper LUT before. It may be shared with MPC by setting mpc:shared_3d_lut flag}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj%ubj)}(h.``ogam_ram`` programmable out/blend gamma LUT h](j)}(h ``ogam_ram``h]j)}(hjh]hogam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h programmable out/blend gamma LUTh]h programmable out/blend gamma LUT}(hj؃hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjԃhKhjՃubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjԃhKhj%ubj)}(h'``ocsc`` output color space conversion h](j)}(h``ocsc``h]j)}(hjh]hocsc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(houtput color space conversionh]houtput color space conversion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj hKhj%ubj)}(h<``dgam_rom_for_yuv`` pre-defined degamma LUT for YUV planes h](j)}(h``dgam_rom_for_yuv``h]j)}(hj1h]hdgam_rom_for_yuv}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj+ubj )}(hhh]h)}(h&pre-defined degamma LUT for YUV planesh]h&pre-defined degamma LUT for YUV planes}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjGubah}(h]h ]h"]h$]h&]uh1j hj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhKhj%ubj)}(h=``dgam_rom_caps`` pre-definied curve caps for degamma 1D LUT h](j)}(h``dgam_rom_caps``h]j)}(hjjh]h dgam_rom_caps}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjdubj )}(hhh]h)}(h*pre-definied curve caps for degamma 1D LUTh]h*pre-definied curve caps for degamma 1D LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjdubeh}(h]h ]h"]h$]h&]uh1jhjhKhj%ubj)}(h<``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUTh](j)}(h``ogam_rom_caps``h]j)}(hjh]h ogam_rom_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj%ubeh}(h]h ]h"]h$]h&]uh1jhj݁ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubh)}(h**Note**h]j)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj'~hhubh)}(hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)h]hJhdr_mult and gamut remap (CTM) are always available in DPP (in that order)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj'~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_color_caps (C struct)c.mpc_color_capshNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hmpc_color_capsh]j)}(hstruct mpc_color_capsh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKubj.)}(h h]h }(hj2hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj hhhj1hKubj?)}(hmpc_color_capsh]jE)}(hjh]hmpc_color_caps}(hjDhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj@ubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj hhhj1hKubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhj1hKubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj1hKhjhhubjs)}(hhh]h)}(hGcolor pipeline capabilities for multiple pipe and plane combined blocksh]hGcolor pipeline capabilities for multiple pipe and plane combined blocks}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjchhubah}(h]h ]h"]h$]h&]uh1jrhjhhhj1hKubeh}(h]h ](jstructeh"]h$]h&]jjjj~jj~jjjuh1j hhhj'~hNhNubj)}(hX**Definition**:: struct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; }; **Members** ``gamut_remap`` color transformation matrix ``ogam_ram`` programmable out gamma LUT ``ocsc`` output color space conversion matrix ``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT ``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT ``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance ``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT ``mcm_3d_lut_caps`` HW support cap for MCM LUT memory ``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory ``preblend`` whether color manager supports preblend with MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj)}(hXRstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; };h]hXRstruct mpc_color_caps { uint16_t gamut_remap : 1; uint16_t ogam_ram : 1; uint16_t ocsc : 1; uint16_t num_3dluts : 3; uint16_t num_rmcm_3dluts : 3; uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j)}(h,``gamut_remap`` color transformation matrix h](j)}(h``gamut_remap``h]j)}(hjӅh]h gamut_remap}(hjՅhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjхubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjͅubj )}(hhh]h)}(hcolor transformation matrixh]hcolor transformation matrix}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjͅubeh}(h]h ]h"]h$]h&]uh1jhjhKhjʅubj)}(h(``ogam_ram`` programmable out gamma LUT h](j)}(h ``ogam_ram``h]j)}(hj h]hogam_ram}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(hprogrammable out gamma LUTh]hprogrammable out gamma LUT}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hKhj"ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj!hKhjʅubj)}(h.``ocsc`` output color space conversion matrix h](j)}(h``ocsc``h]j)}(hjEh]hocsc}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj?ubj )}(hhh]h)}(h$output color space conversion matrixh]h$output color space conversion matrix}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhKhj[ubah}(h]h ]h"]h$]h&]uh1j hj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhKhjʅubj)}(hA``num_3dluts`` MPC 3D LUT; always assumes a preceding shaper LUT h](j)}(h``num_3dluts``h]j)}(hj~h]h num_3dluts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjxubj )}(hhh]h)}(h1MPC 3D LUT; always assumes a preceding shaper LUTh]h1MPC 3D LUT; always assumes a preceding shaper LUT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjxubeh}(h]h ]h"]h$]h&]uh1jhjhKhjʅubj)}(hR``num_rmcm_3dluts`` number of RMCM 3D LUTS; always assumes a preceding shaper LUT h](j)}(h``num_rmcm_3dluts``h]j)}(hjh]hnum_rmcm_3dluts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h=number of RMCM 3D LUTS; always assumes a preceding shaper LUTh]h=number of RMCM 3D LUTS; always assumes a preceding shaper LUT}(hjІhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj̆hKhj͆ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj̆hKhjʅubj)}(hT``shared_3d_lut`` shared 3D LUT flag. Can be either DPP or MPC, but single instance h](j)}(h``shared_3d_lut``h]j)}(hjh]h shared_3d_lut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(hAshared 3D LUT flag. Can be either DPP or MPC, but single instanceh]hAshared 3D LUT flag. Can be either DPP or MPC, but single instance}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjʅubj)}(h=``ogam_rom_caps`` pre-definied curve caps for regamma 1D LUT h](j)}(h``ogam_rom_caps``h]j)}(hj*h]h ogam_rom_caps}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj$ubj )}(hhh]h)}(h*pre-definied curve caps for regamma 1D LUTh]h*pre-definied curve caps for regamma 1D LUT}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hKhj@ubah}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hKhjʅubj)}(h6``mcm_3d_lut_caps`` HW support cap for MCM LUT memory h](j)}(h``mcm_3d_lut_caps``h]j)}(hjch]hmcm_3d_lut_caps}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhj]ubj )}(hhh]h)}(h!HW support cap for MCM LUT memoryh]h!HW support cap for MCM LUT memory}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhKhjyubah}(h]h ]h"]h$]h&]uh1j hj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhKhjʅubj)}(h8``rmcm_3d_lut_caps`` HW support cap for RMCM LUT memory h](j)}(h``rmcm_3d_lut_caps``h]j)}(hjh]hrmcm_3d_lut_caps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubj )}(hhh]h)}(h"HW support cap for RMCM LUT memoryh]h"HW support cap for RMCM LUT memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjʅubj)}(h=``preblend`` whether color manager supports preblend with MPCh](j)}(h ``preblend``h]j)}(hjՇh]hpreblend}(hjׇhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӇubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjχubj )}(hhh]h)}(h0whether color manager supports preblend with MPCh]h0whether color manager supports preblend with MPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhKhjubah}(h]h ]h"]h$]h&]uh1j hjχubeh}(h]h ]h"]h$]h&]uh1jhjhKhjʅubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdc_color_caps (C struct)c.dc_color_capshNtauh1jhj'~hhhNhNubj )}(hhh](j)}(h dc_color_capsh]j)}(hstruct dc_color_capsh](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj+hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMubj.)}(h h]h }(hj=hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj+hhhj<hMubj?)}(h dc_color_capsh]jE)}(hj)h]h dc_color_caps}(hjOhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjKubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj+hhhj<hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj'hhhj<hMubah}(h]j"ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj<hMhj$hhubjs)}(hhh]h)}(h2color pipes capabilities for DPP and MPC hw blocksh]h2color pipes capabilities for DPP and MPC hw blocks}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM hjnhhubah}(h]h ]h"]h$]h&]uh1jrhj$hhhj<hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j hhhj'~hNhNubj)}(h**Definition**:: struct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; }; **Members** ``dpp`` color pipes caps for DPP ``mpc`` color pipes caps for MPCh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };h]hWstruct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc; };}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj)}(hhh](j)}(h!``dpp`` color pipes caps for DPP h](j)}(h``dpp``h]j)}(hjވh]hdpp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܈ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj؈ubj )}(hhh]h)}(hcolor pipes caps for DPPh]hcolor pipes caps for DPP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hj؈ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjՈubj)}(h ``mpc`` color pipes caps for MPCh](j)}(h``mpc``h]j)}(hjh]hmpc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj )}(hhh]h)}(hcolor pipes caps for MPCh]hcolor pipes caps for MPC}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj-ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjՈubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jpipe_split_policy (C enum)c.pipe_split_policyhNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hpipe_split_policyh]j)}(henum pipe_split_policyh](j)}(hjf8h]henum}(hjqhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjmhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjmhhhj~hMubj?)}(hpipe_split_policyh]jE)}(hjkh]hpipe_split_policy}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjmhhhj~hMubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjihhhj~hMubah}(h]jdah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj~hMhjfhhubjs)}(hhh]h)}(h$Pipe split strategy supported by DCNh]h$Pipe split strategy supported by DCN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMnhjhhubah}(h]h ]h"]h$]h&]uh1jrhjfhhhj~hMubeh}(h]h ](jenumeh"]h$]h&]jjjjˉjjˉjjjuh1j hhhj'~hNhNubj)}(hX**Constants** ``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. ``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. ``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](h)}(h **Constants**h]j)}(hjՉh]h Constants}(hj׉hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӉubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMrhjωubj)}(hhh](j)}(h``MPC_SPLIT_DYNAMIC`` DC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option. h](j)}(h``MPC_SPLIT_DYNAMIC``h]j)}(hjh]hMPC_SPLIT_DYNAMIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMwhjubj )}(hhh]h)}(hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.h]hDC will automatically decide how to split the pipe in order to bring the best trade-off between performance and power consumption. This is the recommended option.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMuhj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhj hMwhjubj)}(hg``MPC_SPLIT_AVOID`` Avoid pipe split, which means that DC will not try any sort of split optimization. h](j)}(h``MPC_SPLIT_AVOID``h]j)}(hj.h]hMPC_SPLIT_AVOID}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM{hj(ubj )}(hhh]h)}(hRAvoid pipe split, which means that DC will not try any sort of split optimization.h]hRAvoid pipe split, which means that DC will not try any sort of split optimization.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMzhjDubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1jhjChM{hjubj)}(h``MPC_SPLIT_AVOID_MULT_DISP`` With this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h](j)}(h``MPC_SPLIT_AVOID_MULT_DISP``h]j)}(hjhh]hMPC_SPLIT_AVOID_MULT_DISP}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjbubj )}(hhh]h)}(hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.h]hWith this option, DC will only try to optimize the pipe utilization when using a single display; if the user connects to a second display, DC will avoid pipe split.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM~hj~ubah}(h]h ]h"]h$]h&]uh1j hjbubeh}(h]h ]h"]h$]h&]uh1jhj}hMhjubeh}(h]h ]h"]h$]h&]uh1jhjωubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj'~hhubh)}(hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.h]hlThis enum is used to define the pipe split policy supported by DCN. By default, DC favors MPC_SPLIT_DYNAMIC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMohj'~hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdc_validation_set (C struct)c.dc_validation_sethNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hdc_validation_seth]j)}(hstruct dc_validation_seth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMuubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhjhMuubj?)}(hdc_validation_seth]jE)}(hjh]hdc_validation_set}(hj hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhjhMuubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhjhMuubah}(h]j܊ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjhMuhjފhhubjs)}(hhh]h)}(h:Struct to store surface/stream associations for validationh]h:Struct to store surface/stream associations for validation}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj(hhubah}(h]h ]h"]h$]h&]uh1jrhjފhhhjhMuubeh}(h]h ](jstructeh"]h$]h&]jjjjCjjCjjjuh1j hhhj'~hNhNubj)}(hX,**Definition**:: struct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; }; **Members** ``stream`` Stream state properties ``plane_states`` Surface state ``plane_count`` Total of active planesh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubh:}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjGubj)}(hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };h]hstruct dc_validation_set { struct dc_stream_state *stream; struct dc_plane_state *plane_states[MAX_SURFACES]; uint8_t plane_count; };}hjhsbah}(h]h ]h"]h$]h&]j\j]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjGubh)}(h **Members**h]j)}(hjyh]hMembers}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjGubj)}(hhh](j)}(h#``stream`` Stream state properties h](j)}(h ``stream``h]j)}(hjh]hstream}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj )}(hhh]h)}(hStream state propertiesh]hStream state properties}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``plane_states`` Surface state h](j)}(h``plane_states``h]j)}(hjыh]h plane_states}(hjӋhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϋubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjˋubj )}(hhh]h)}(h Surface stateh]h Surface state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1j hjˋubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h&``plane_count`` Total of active planesh](j)}(h``plane_count``h]j)}(hj h]h plane_count}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhjubj )}(hhh]h)}(hTotal of active planesh]hTotal of active planes}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMhj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j0dc_get_underflow_debug_data_for_otg (C function)%c.dc_get_underflow_debug_data_for_otghNtauh1jhj'~hhhNhNubj )}(hhh](j)}(hxvoid dc_get_underflow_debug_data_for_otg (struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h]j)}(hwvoid dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](j))}(hvoidh]hvoid}(hjdhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hj`hhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMb ubj.)}(h h]h }(hjshhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj`hhhjrhMb ubj?)}(h#dc_get_underflow_debug_data_for_otgh]jE)}(h#dc_get_underflow_debug_data_for_otgh]h#dc_get_underflow_debug_data_for_otg}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hj`hhhjrhMb ubj))}(hO(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data)h](j))}(h struct dc *dch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubh)}(hhh]jE)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjmodnameN classnameNjj)}j ]j*)}j *jsb%c.dc_get_underflow_debug_data_for_otgasbuh1hhjubj.)}(h h]h }(hjߌhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj'*)}(hj**h]h*}(hjhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjubjE)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjubj))}(hint primary_otg_insth](j))}(hinth]hint}(hjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjubj.)}(h h]h }(hj!hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubjE)}(hprimary_otg_insth]hprimary_otg_inst}(hj/hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjubj))}(h(struct dc_underflow_debug_data *out_datah](j)}(hjh]hstruct}(hjHhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjDubj.)}(h h]h }(hjUhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjDubh)}(hhh]jE)}(hdc_underflow_debug_datah]hdc_underflow_debug_data}(hjfhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjcubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjhmodnameN classnameNjj)}j ]jی%c.dc_get_underflow_debug_data_for_otgasbuh1hhjDubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjDubj'*)}(hj**h]h*}(hjhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjDubjE)}(hout_datah]hout_data}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjDubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjubeh}(h]h ]h"]h$]h&]j\j]uh1j)hj`hhhjrhMb ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhj\hhhjrhMb ubah}(h]jWah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjrhMb hjYhhubjs)}(hhh]h)}(hRetrieve underflow debug data.h]hRetrieve underflow debug data.}(hjɍhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMb hjƍhhubah}(h]h ]h"]h$]h&]uh1jrhjYhhhjrhMb ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j hhhj'~hNhNubj)}(hX8**Parameters** ``struct dc *dc`` Pointer to the display core context. ``int primary_otg_inst`` Instance index of the primary OTG that underflowed. ``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. **Description** This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMf hjubj)}(hhh](j)}(h7``struct dc *dc`` Pointer to the display core context. h](j)}(h``struct dc *dc``h]j)}(hj h]h struct dc *dc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMd hjubj )}(hhh]h)}(h$Pointer to the display core context.h]h$Pointer to the display core context.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMd hj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMd hjubj)}(hM``int primary_otg_inst`` Instance index of the primary OTG that underflowed. h](j)}(h``int primary_otg_inst``h]j)}(hjCh]hint primary_otg_inst}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMe hj=ubj )}(hhh]h)}(h3Instance index of the primary OTG that underflowed.h]h3Instance index of the primary OTG that underflowed.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhMe hjYubah}(h]h ]h"]h$]h&]uh1j hj=ubeh}(h]h ]h"]h$]h&]uh1jhjXhMe hjubj)}(h~``struct dc_underflow_debug_data *out_data`` Pointer to a dc_underflow_debug_data struct to be filled with debug information. h](j)}(h,``struct dc_underflow_debug_data *out_data``h]j)}(hj|h]h(struct dc_underflow_debug_data *out_data}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMf hjvubj )}(hhh]h)}(hPPointer to a dc_underflow_debug_data struct to be filled with debug information.h]hPPointer to a dc_underflow_debug_data struct to be filled with debug information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMf hjubah}(h]h ]h"]h$]h&]uh1j hjvubeh}(h]h ]h"]h$]h&]uh1jhjhMf hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMh hjubh)}(hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.h]hX This function collects and logs underflow-related HW states when underflow happens, including OTG underflow status, current read positions, frame count, and per-HUBP debug data. The results are stored in the provided out_data structure for further analysis or logging.}(hj͎hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMg hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j/dc_capture_register_software_state (C function)$c.dc_capture_register_software_statehNtauh1jhj'~hhhNhNubj )}(hhh](j)}(habool dc_capture_register_software_state (struct dc *dc, struct dc_register_software_state *state)h]j)}(h`bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)h](j))}(hjcVh]hbool}(hjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM@ ubj.)}(h h]h }(hj hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjhhhj hM@ ubj?)}(h"dc_capture_register_software_stateh]jE)}(h"dc_capture_register_software_stateh]h"dc_capture_register_software_state}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjhhhj hM@ ubj))}(h9(struct dc *dc, struct dc_register_software_state *state)h](j))}(h struct dc *dch](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhj4ubj.)}(h h]h }(hjEhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4ubh)}(hhh]jE)}(hdch]hdc}(hjVhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjSubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjXmodnameN classnameNjj)}j ]j*)}j *jsb$c.dc_capture_register_software_stateasbuh1hhj4ubj.)}(h h]h }(hjvhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hj4ubj'*)}(hj**h]h*}(hjhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hj4ubjE)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj4ubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj0ubj))}(h(struct dc_register_software_state *stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubh)}(hhh]jE)}(hdc_register_software_stateh]hdc_register_software_state}(hjȏhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjŏubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjʏmodnameN classnameNjj)}j ]jr$c.dc_capture_register_software_stateasbuh1hhjubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj'*)}(hj**h]h*}(hjhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjubjE)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hj0ubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjhhhj hM@ ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjhhhj hM@ ubah}(h]jah ](jjjkeh"]h$]h&]jojp)jqhuh1jhj hM@ hjhhubjs)}(hhh]h)}(h/Capture software state for register programmingh]h/Capture software state for register programming}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM@ hj(hhubah}(h]h ]h"]h$]h&]uh1jrhjhhhj hM@ ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjCjjCjjjuh1j hhhj'~hNhNubj)}(hXM**Parameters** ``struct dc *dc`` DC context containing current display configuration ``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate **Description** Extracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming. The function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration) This is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues. **Return** true if state was successfully captured, false on errorh](h)}(h**Parameters**h]j)}(hjMh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMD hjGubj)}(hhh](j)}(hF``struct dc *dc`` DC context containing current display configuration h](j)}(h``struct dc *dc``h]j)}(hjlh]h struct dc *dc}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMA hjfubj )}(hhh]h)}(h3DC context containing current display configurationh]h3DC context containing current display configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMA hjubah}(h]h ]h"]h$]h&]uh1j hjfubeh}(h]h ]h"]h$]h&]uh1jhjhMA hjcubj)}(hi``struct dc_register_software_state *state`` Pointer to dc_register_software_state structure to populate h](j)}(h,``struct dc_register_software_state *state``h]j)}(hjh]h(struct dc_register_software_state *state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMB hjubj )}(hhh]h)}(h;Pointer to dc_register_software_state structure to populateh]h;Pointer to dc_register_software_state structure to populate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMB hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1jhjhMB hjcubeh}(h]h ]h"]h$]h&]uh1jhjGubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjސubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMD hjGubh)}(hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.h]hExtracts all software state variables that are used to program hardware register fields across the display driver pipeline. This provides a complete snapshot of the software configuration that drives hardware register programming.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMC hjGubh)}(hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)h]hXdThe function traverses the DC context and extracts values from: - Stream configurations (timing, format, DSC settings) - Plane states (surface format, rotation, scaling, cursor) - Pipe contexts (resource allocation, blending, viewport) - Clock manager (display clocks, DPP clocks, pixel clocks) - Resource context (DET buffer allocation, ODM configuration)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMG hjGubh)}(hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.h]hThis is essential for underflow debugging as it captures the exact software state that determines how registers are programmed, allowing analysis of whether underflow is caused by incorrect register programming or timing issues.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMN hjGubh)}(h **Return**h]j)}(hj%h]hReturn}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMR hjGubh)}(h7true if state was successfully captured, false on errorh]h7true if state was successfully captured, false on error}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMS hjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdc_get_qos_info (C function)c.dc_get_qos_infohNtauh1jhj'~hhhNhNubj )}(hhh](j)}(h>bool dc_get_qos_info (struct dc *dc, struct dc_qos_info *info)h]j)}(h=bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)h](j))}(hjcVh]hbool}(hjjhhhNhNubah}(h]h ]j)ah"]h$]h&]uh1j)hjfhhhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMX ubj.)}(h h]h }(hjxhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjfhhhjwhMX ubj?)}(hdc_get_qos_infoh]jE)}(hdc_get_qos_infoh]hdc_get_qos_info}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ](jWjXeh"]h$]h&]j\j]uh1j>hjfhhhjwhMX ubj))}(h)(struct dc *dc, struct dc_qos_info *info)h](j))}(h struct dc *dch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubh)}(hhh]jE)}(hdch]hdc}(hjđhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetjƑmodnameN classnameNjj)}j ]j*)}j *jsbc.dc_get_qos_infoasbuh1hhjubj.)}(h h]h }(hjhhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj'*)}(hj**h]h*}(hjhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjubjE)}(hdch]hdc}(hjhhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjubj))}(hstruct dc_qos_info *infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]j(ah"]h$]h&]uh1jhjubj.)}(h h]h }(hj%hhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubh)}(hhh]jE)}(h dc_qos_infoh]h dc_qos_info}(hj6hhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhj3ubah}(h]h ]h"]h$]h&] refdomainjreftypej * reftargetj8modnameN classnameNjj)}j ]jc.dc_get_qos_infoasbuh1hhjubj.)}(h h]h }(hjThhhNhNubah}(h]h ]j:ah"]h$]h&]uh1j-hjubj'*)}(hj**h]h*}(hjbhhhNhNubah}(h]h ]j3*ah"]h$]h&]uh1j&*hjubjE)}(hinfoh]hinfo}(hjohhhNhNubah}(h]h ]jPah"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]noemphj\j]uh1j)hjubeh}(h]h ]h"]h$]h&]j\j]uh1j)hjfhhhjwhMX ubeh}(h]h ]h"]h$]h&]j\j]jduh1jjejfhjbhhhjwhMX ubah}(h]j]ah ](jjjkeh"]h$]h&]jojp)jqhuh1jhjwhMX hj_hhubjs)}(hhh]h)}(h?Retrieve Quality of Service (QoS) information from display coreh]h?Retrieve Quality of Service (QoS) information from display core}(сhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMX hjhhubah}(h]h ]h"]h$]h&]uh1jrhj_hhhjwhMX ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j hhhj'~hNhNubj)}(hX%**Parameters** ``struct dc *dc`` DC context containing current display configuration ``struct dc_qos_info *info`` Pointer to dc_qos_info structure to populate with QoS metrics **Description** This function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements. QoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds) The function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero'd info structure. **Return** true if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performedh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM\ hjubj)}(hhh](j)}(hF``struct dc *dc`` DC context containing current display configuration h](j)}(h``struct dc *dc``h]j)}(hjڒh]h struct dc *dc}(hjܒhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjؒubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMY hjԒubj )}(hhh]h)}(h3DC context containing current display configurationh]h3DC context containing current display configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMY hjubah}(h]h ]h"]h$]h&]uh1j hjԒubeh}(h]h ]h"]h$]h&]uh1jhjhMY hjђubj)}(h[``struct dc_qos_info *info`` Pointer to dc_qos_info structure to populate with QoS metrics h](j)}(h``struct dc_qos_info *info``h]j)}(hjh]hstruct dc_qos_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMZ hj ubj )}(hhh]h)}(h=Pointer to dc_qos_info structure to populate with QoS metricsh]h=Pointer to dc_qos_info structure to populate with QoS metrics}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hMZ hj)ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1jhj(hMZ hjђubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjNh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM\ hjubh)}(hThis function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements.h]hThis function retrieves QoS metrics from the display core that can be used by benchmark tools to analyze display system performance. The function may take several milliseconds to execute due to hardware measurement requirements.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM[ hjubh)}(hQoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds)h]hQoS information includes: - Bandwidth bounds (lower limits in Mbps) - Latency bounds (upper limits in nanoseconds) - Hardware-measured bandwidth metrics (peak/average in Mbps) - Hardware-measured latency metrics (maximum/average in nanoseconds)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhM_ hjubh)}(hThe function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero'd info structure.h]hThe function will populate the provided dc_qos_info structure with current QoS measurements. If hardware measurement functions are not available for the current DCN version, the function returns false with zero’d info structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMe hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMi hjubh)}(htrue if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performedh]htrue if QoS information was successfully retrieved, false if measurement functions are unavailable or hardware measurements cannot be performed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhv/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/display-manager:71: ./drivers/gpu/drm/amd/display/dc/dc.hhMj hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj'~hhhNhNubh)}(hThe color pipeline has undergone major changes between DCN hardware generations. What's possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.h]hThe color pipeline has undergone major changes between DCN hardware generations. What’s possible to do before and after blending depends on hardware capabilities, as illustrated below by the DCN 2.0 and DCN 3.0 families schemas.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj'~hhubh)}(h)**DCN 2.0 family color caps and mapping**h]j)}(hjϓh]h%DCN 2.0 family color caps and mapping}(hjѓhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͓ubah}(h]h ]h"]h$]h&]uh1hhhhKOhj'~hhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h+.. kernel-figure:: dcn2_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn2_cm_drm_current.svg candidates}j**jsuh1jhjhhhKubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj'~hhhhhKRubh)}(h)**DCN 3.0 family color caps and mapping**h]j)}(hj h]h%DCN 3.0 family color caps and mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKShj'~hhubj)}(hhh]j)}(hhh]j)}(h+.. kernel-figure:: dcn3_cm_drm_current.svg h]h}(h]h ]h"]h$]h&]uri*gpu/amdgpu/display/dcn3_cm_drm_current.svgj}j**j3suh1jhj%hhhKubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhj'~hhhhhKVubeh}(h]j ah ]h"]-dc color capabilities between dcn generationsah$]h&]uh1hhj^JhhhhhK7ubeh}(h]jah ]h"]color management propertiesah$]h&]uh1hhhhhhhhK-ubh)}(hhh](h)}(hBlend Mode Propertiesh]hBlend Mode Properties}(hjRhhhNhNubah}(h]h ]h"]h$]h&]hj2uh1hhjOhhhhhKXubh)}(hXPixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in :ref:`DRM Plane Composition Properties `.h](h8Pixel blend mode is a DRM plane composition property of }(hj`hhhNhNubh)}(h:c:type:`drm_plane`h]j)}(hjjh]h drm_plane}(hjlhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j drm_planeuh1hhhhKZhj`ubhX' used to describes how pixels from a foreground plane (fg) are composited with the background plane (bg). Here, we present main concepts of DRM blend mode to help to understand how this property is mapped to AMD DC interface. See more about this DRM property and the alpha blending equations in }(hj`hhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]hinline)}(hjh]h DRM Plane Composition Properties}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjplane_composition_propertiesuh1hhhhKZhj`ubh.}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKZhjOhhubh)}(hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:h]hXBasically, a blend mode sets the alpha blending equation for plane composition that fits the mode in which the alpha channel affects the state of pixel color values and, therefore, the resulted pixel color. For example, consider the following elements of the alpha blending equation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjOhhubh)}(hhh](h)}(hG*fg.rgb*: Each of the RGB component values from the foreground's pixel.h]h)}(hjʔh](j/F)}(h*fg.rgb*h]hfg.rgb}(hjϔhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhj̔ubhA: Each of the RGB component values from the foreground’s pixel.}(hj̔hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKfhjȔubah}(h]h ]h"]h$]h&]uh1hhjŔhhhhhNubh)}(h>*fg.alpha*: Alpha component value from the foreground's pixel.h]h)}(hjh](j/F)}(h *fg.alpha*h]hfg.alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh6: Alpha component value from the foreground’s pixel.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKghjubah}(h]h ]h"]h$]h&]uh1hhjŔhhhhhNubh)}(h?*bg.rgb*: Each of the RGB component values from the background.h]h)}(hjh](j/F)}(h*bg.rgb*h]hbg.rgb}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh7: Each of the RGB component values from the background.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1hhjŔhhhhhNubh)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `. h]h)}(h*plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see more in :ref:`DRM Plane Composition Properties `.h](j/F)}(h *plane_alpha*h]h plane_alpha}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhj;ubh: Plane alpha value set by the }(hj;hhhNhNubj)}(h**plane "alpha" property**h]hplane “alpha” property}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh, see more in }(hj;hhhNhNubh)}(hF:ref:`DRM Plane Composition Properties `h]j)}(hjeh]h DRM Plane Composition Properties}(hjghhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]refdocj refdomainjqreftyperef refexplicitrefwarnjplane_composition_propertiesuh1hhhhKihj;ubh.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihj7ubah}(h]h ]h"]h$]h&]uh1hhjŔhhhhhNubeh}(h]h ]h"]h$]h&]j+j+uh1hhhhKfhjOhhubh)}(h&in the basic alpha blending equation::h]h%in the basic alpha blending equation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjOhhubj)}(h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgbh]h/out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb}hjsbah}(h]h ]h"]h$]h&]j\j]uh1jhhhKnhjOhhubh)}(h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.h]h}the alpha channel value of each pixel in a plane is ignored and only the plane alpha affects the resulted pixel color values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjOhhubh)}(hNDRM has three blend mode to define the blend formula in the plane composition:h]hNDRM has three blend mode to define the blend formula in the plane composition:}(hjÕhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjOhhubh)}(hhh](h)}(h6**None**: Blend formula that ignores the pixel alpha. h]h)}(h5**None**: Blend formula that ignores the pixel alpha.h](j)}(h**None**h]hNone}(hjܕhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjؕubh-: Blend formula that ignores the pixel alpha.}(hjؕhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKuhjԕubah}(h]h ]h"]h$]h&]uh1hhjѕhhhhhNubh)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage. h]h)}(h**Pre-multiplied**: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.h](j)}(h**Pre-multiplied**h]hPre-multiplied}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: Blend formula that assumes the pixel color values in a plane was already pre-multiplied by its own alpha channel before storage.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1hhjѕhhhhhNubh)}(hw**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values. h]h)}(hv**Coverage**: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.h](j)}(h **Coverage**h]hCoverage}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubhj: Blend formula that assumes the pixel color values were not pre-multiplied with the alpha channel values.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhj ubah}(h]h ]h"]h$]h&]uh1hhjѕhhhhhNubeh}(h]h ]h"]h$]h&]j+j**uh1hhhhKuhjOhhubh)}(hX1and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane's pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.h]hX3and pre-multiplied is the default pixel blend mode, that means, when no blend mode property is created or defined, DRM considers the plane’s pixels has pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test provides a set of subtests to verify plane alpha and blend mode properties.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjOhhubh)}(hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:h]hThe DRM blend mode and its elements are then mapped by AMDGPU display manager (DM) to program the blending configuration of the Multiple Pipe/Plane Combined (MPC), as follows:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjOhhubh)}(hXTherefore, the blending configuration for a single MPCC instance on the MPC tree is defined by :c:type:`mpcc_blnd_cfg`, where :c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. :c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for :c:type:`MPCC_ALPHA_BLND_MODE`, as described below.h](h_Therefore, the blending configuration for a single MPCC instance on the MPC tree is defined by }(hjhhhhNhNubh)}(h:c:type:`mpcc_blnd_cfg`h]j)}(hjrh]h mpcc_blnd_cfg}(hjthhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j mpcc_blnd_cfguh1hhhhKhjhubh, where }(hjhhhhNhNubh)}(h:c:type:`pre_multiplied_alpha`h]j)}(hjh]hpre_multiplied_alpha}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jpre_multiplied_alphauh1hhhhKhjhubh3 is the alpha pre-multiplied mode flag used to set }(hjhhhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hjh]hMPCC_ALPHA_MULTIPLIED_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jMPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjhubhk. It controls whether alpha is multiplied (true/false), being only true for DRM pre-multiplied blend mode. }(hjhhhhNhNubh)}(h:c:type:`mpcc_alpha_blend_mode`h]j)}(hjۖh]hmpcc_alpha_blend_mode}(hjݖhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjٖubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jmpcc_alpha_blend_modeuh1hhhhKhjhubho defines the alpha blend mode regarding pixel alpha and plane alpha values. It sets one of the three modes for }(hjhhhhNhNubh)}(h:c:type:`MPCC_ALPHA_BLND_MODE`h]j)}(hjh]hMPCC_ALPHA_BLND_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jMPCC_ALPHA_BLND_MODEuh1hhhhKhjhubh, as described below.}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjOhhubh)}(hhDM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM blend formula, as follows:h](hDM then maps the elements of }(hj%hhhNhNubhtitle_reference)}(h`enum mpcc_alpha_blend_mode`h]henum mpcc_alpha_blend_mode}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j-hj%ubh/ to those in the DRM blend formula, as follows:}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjOhhubh)}(hhh](h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh]h)}(h\*MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value from the plane's pixelh](j/F)}(h*MPC pixel alpha*h]hMPC pixel alpha}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j.FhjNubh matches }(hjNhhhNhNubj/F)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j.FhjNubh6 as the alpha component value from the plane’s pixel}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh]h)}(h*MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should be ignored and, therefore, pixel values are not pre-multipliedh](j/F)}(h*MPC global alpha*h]hMPC global alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh matches }(hjhhhNhNubj/F)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh[ when the pixel alpha should be ignored and, therefore, pixel values are not pre-multiplied}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubh)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equation h]h)}(h*MPC global gain* assumes *MPC global alpha* value when both *DRM fg.alpha* and *DRM plane_alpha* participate in the blend equationh](j/F)}(h*MPC global gain*h]hMPC global gain}(hj—hhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh assumes }(hjhhhNhNubj/F)}(h*MPC global alpha*h]hMPC global alpha}(hjԗhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh value when both }(hjhhhNhNubj/F)}(h*DRM fg.alpha*h]h DRM fg.alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh and }(hjhhhNhNubj/F)}(h*DRM plane_alpha*h]hDRM plane_alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh" participate in the blend equation}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhNubeh}(h]h ]h"]h$]h&]j+j**uh1hhhhKhjOhhubh)}(hXhIn short, *fg.alpha* is ignored by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting :c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the :c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are pre-multiplied by alpha or not.h](h In short, }(hjhhhNhNubj/F)}(h *fg.alpha*h]hfg.alpha}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j.Fhjubh is ignored by selecting }(hjhhhNhNubh)}(h,:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`h]j)}(hj8h]h"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA}(hj:hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j"MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHAuh1hhhhKhjubhW. On the other hand, (plane_alpha * fg.alpha) component becomes available by selecting }(hjhhhNhNubh)}(hD:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`h]j)}(hj[h]h:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN}(hj]hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j:MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAINuh1hhhhKhjubh . And the }(hjhhhNhNubh)}(h$:c:type:`MPCC_ALPHA_MULTIPLIED_MODE`h]j)}(hj~h]hMPCC_ALPHA_MULTIPLIED_MODE}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jMPCC_ALPHA_MULTIPLIED_MODEuh1hhhhKhjubhF defines if the pixel color values are pre-multiplied by alpha or not.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjOhhubh)}(hhh](h)}(hBlend configuration flowh]hBlend configuration flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]hjQuh1hhjhhhhhKubh)}(hYThe alpha blending equation is configured from DRM to DC interface by the following path:h]hYThe alpha blending equation is configured from DRM to DC interface by the following path:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjN)}(hhh](h)}(hX%When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC). h]h)}(hX$When updating a :c:type:`drm_plane_state `, DM calls :c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()` that maps :c:type:`drm_plane_state ` attributes to :c:type:`dc_plane_info ` struct to be handled in the OS-agnostic component (DC).h](hWhen updating a }(hj˘hhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hj՘h]hdrm_plane_state}(hjטhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjӘubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_plane_stateuh1hhhhKhj˘ubh , DM calls }(hj˘hhhNhNubh)}(h::c:type:`amdgpu_dm_plane_fill_blending_from_plane_state()`h]j)}(hjh]h0amdgpu_dm_plane_fill_blending_from_plane_state()}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j0amdgpu_dm_plane_fill_blending_from_plane_state()uh1hhhhKhj˘ubh that maps }(hj˘hhhNhNubh)}(h+:c:type:`drm_plane_state `h]j)}(hjh]hdrm_plane_state}(hjhhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj jdrm_plane_stateuh1hhhhKhj˘ubh attributes to }(hj˘hhhNhNubh)}(h':c:type:`dc_plane_info `h]j)}(hj>h]h dc_plane_info}(hj@hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j dc_plane_infouh1hhhhKhj˘ubh8 struct to be handled in the OS-agnostic component (DC).}(hj˘hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjǘubah}(h]h ]h"]h$]h&]uh1hhjĘhhhhhNubh)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h]h)}(hOn DC interface, :c:type:`struct mpcc_blnd_cfg ` programs the MPCC blend configuration considering the :c:type:`dc_plane_info ` input from DPP.h](hOn DC interface, }(hjohhhNhNubh)}(h.:c:type:`struct mpcc_blnd_cfg `h]j)}(hjyh]hstruct mpcc_blnd_cfg}(hj{hhhNhNubah}(h]h ](jjc-typeeh"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjj j mpcc_blnd_cfguh1hhhhKhjoubh7 programs the MPCC blend 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