msphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget3/translations/zh_CN/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/zh_TW/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/it_IT/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ja_JP/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ko_KR/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/sp_SP/gpu/amdgpu/display/dcn-overviewmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhtarget)}(h.. _dcn_overview:h]h}(h]h ]h"]h$]h&]refid dcn-overviewuh1hhKhhhhhM/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-overview.rstubhsection)}(hhh](htitle)}(hDisplay Core Next (DCN)h]hDisplay Core Next (DCN)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXTo equip our readers with the basic knowledge of how AMD Display Core Next (DCN) works, we need to start with an overview of the hardware pipeline. Below you can see a picture that provides a DCN overview, keep in mind that this is a generic diagram, and we have variations per ASIC.h]hXTo equip our readers with the basic knowledge of how AMD Display Core Next (DCN) works, we need to start with an overview of the hardware pipeline. Below you can see a picture that provides a DCN overview, keep in mind that this is a generic diagram, and we have variations per ASIC.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubkfigure kernel_figure)}(hhh]hfigure)}(hhh]himage)}(h,.. kernel-figure:: dc_pipeline_overview.svg h]h}(h]h ]h"]h$]h&]uri+gpu/amdgpu/display/dc_pipeline_overview.svg candidates}*hsuh1hhhhhhKubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hPBased on this diagram, we can pass through each block and briefly describe them:h]hPBased on this diagram, we can pass through each block and briefly describe them:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h**Display Controller Hub (DCHUB)**: This is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation. h]h)}(h**Display Controller Hub (DCHUB)**: This is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.h](hstrong)}(h"**Display Controller Hub (DCHUB)**h]hDisplay Controller Hub (DCHUB)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: This is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h**Display Pipe and Plane (DPP)**: This block provides pre-blend pixel processing such as color space conversion, linearization of pixel data, tone mapping, and gamut mapping. h]h)}(h**Display Pipe and Plane (DPP)**: This block provides pre-blend pixel processing such as color space conversion, linearization of pixel data, tone mapping, and gamut mapping.h](j)}(h **Display Pipe and Plane (DPP)**h]hDisplay Pipe and Plane (DPP)}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh: This block provides pre-blend pixel processing such as color space conversion, linearization of pixel data, tone mapping, and gamut mapping.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h~**Multiple Pipe/Plane Combined (MPC)**: This component performs blending of multiple planes, using global or per-pixel alpha. h]h)}(h}**Multiple Pipe/Plane Combined (MPC)**: This component performs blending of multiple planes, using global or per-pixel alpha.h](j)}(h&**Multiple Pipe/Plane Combined (MPC)**h]h"Multiple Pipe/Plane Combined (MPC)}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubhW: This component performs blending of multiple planes, using global or per-pixel alpha.}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj`ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hX**Output Pixel Processing (OPP)**: Process and format pixels to be sent to the display. h]h)}(hW**Output Pixel Processing (OPP)**: Process and format pixels to be sent to the display.h](j)}(h!**Output Pixel Processing (OPP)**h]hOutput Pixel Processing (OPP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh6: Process and format pixels to be sent to the display.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h**Output Pipe Timing Combiner (OPTC)**: It generates time output to combine streams or divide capabilities. CRC values are generated in this block. h]h)}(h**Output Pipe Timing Combiner (OPTC)**: It generates time output to combine streams or divide capabilities. CRC values are generated in this block.h](j)}(h&**Output Pipe Timing Combiner (OPTC)**h]h"Output Pipe Timing Combiner (OPTC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhm: It generates time output to combine streams or divide capabilities. CRC values are generated in this block.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hQ**Display Output (DIO)**: Codify the output to the display connected to our GPU. h]h)}(hP**Display Output (DIO)**: Codify the output to the display connected to our GPU.h](j)}(h**Display Output (DIO)**h]hDisplay Output (DIO)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh8: Codify the output to the display connected to our GPU.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h}**Display Writeback (DWB)**: It provides the ability to write the output of the display pipe back to memory as video frames. h]h)}(h|**Display Writeback (DWB)**: It provides the ability to write the output of the display pipe back to memory as video frames.h](j)}(h**Display Writeback (DWB)**h]hDisplay Writeback (DWB)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubha: It provides the ability to write the output of the display pipe back to memory as video frames.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hq**Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB (Note that DWB is not hooked yet). h]h)}(hp**Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB (Note that DWB is not hooked yet).h](j)}(h**Multi-Media HUB (MMHUBBUB)**h]hMulti-Media HUB (MMHUBBUB)}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubhR: Memory controller interface for DMCUB and DWB (Note that DWB is not hooked yet).}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h**DCN Management Unit (DMU)**: It provides registers with access control and interrupts the controller to the SOC host interrupt unit. This block includes the Display Micro-Controller Unit - version B (DMCUB), which is handled via firmware. h]h)}(h**DCN Management Unit (DMU)**: It provides registers with access control and interrupts the controller to the SOC host interrupt unit. This block includes the Display Micro-Controller Unit - version B (DMCUB), which is handled via firmware.h](j)}(h**DCN Management Unit (DMU)**h]hDCN Management Unit (DMU)}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh: It provides registers with access control and interrupts the controller to the SOC host interrupt unit. This block includes the Display Micro-Controller Unit - version B (DMCUB), which is handled via firmware.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK+hjDubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hy**DCN Clock Generator Block (DCCG)**: It provides the clocks and resets for all of the display controller clock domains. h]h)}(hx**DCN Clock Generator Block (DCCG)**: It provides the clocks and resets for all of the display controller clock domains.h](j)}(h$**DCN Clock Generator Block (DCCG)**h]h DCN Clock Generator Block (DCCG)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubhT: It provides the clocks and resets for all of the display controller clock domains.}(hjnhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK0hjjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h**Azalia (AZ)**: Audio engine. h]h)}(h**Azalia (AZ)**: Audio engine.h](j)}(h**Azalia (AZ)**h]h Azalia (AZ)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: Audio engine.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]bullethuh1j hhhKhhhhubh)}(hX,The above diagram is an architecture generalization of DCN, which means that every ASIC has variations around this base model. Notice that the display pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see the SDP as the element from our Data Fabric that feeds the display pipe.h]hX,The above diagram is an architecture generalization of DCN, which means that every ASIC has variations around this base model. Notice that the display pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see the SDP as the element from our Data Fabric that feeds the display pipe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hhhhubh)}(hXoAlways approach the DCN architecture as something flexible that can be configured and reconfigured in multiple ways; in other words, each block can be setup or ignored accordingly with userspace demands. For example, if we want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2 OPP. It is DC's responsibility to drive the best configuration for each specific scenario. Orchestrate all of these components together requires a sophisticated communication interface which is highlighted in the diagram by the edges that connect each block; from the chart, each connection between these blocks represents:h](hAlways approach the DCN architecture as something flexible that can be configured and reconfigured in multiple ways; in other words, each block can be setup or ignored accordingly with userspace demands. For example, if we want to drive an }(hjhhhNhNubh reference)}(h8k@60Hzh]h8k@60Hz}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:8k@60Hzuh1jhjubhXz with a DSC enabled, our DCN may require 4 DPP and 2 OPP. It is DC’s responsibility to drive the best configuration for each specific scenario. Orchestrate all of these components together requires a sophisticated communication interface which is highlighted in the diagram by the edges that connect each block; from the chart, each connection between these blocks represents:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK:hhhhubhenumerated_list)}(hhh](j)}(h;Pixel data interface (red): Represents the pixel data flow;h]h)}(hjh]h;Pixel data interface (red): Represents the pixel data flow;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hnGlobal sync signals (green): It is a set of synchronization signals composed by VStartup, VUpdate, and VReady;h]h)}(hnGlobal sync signals (green): It is a set of synchronization signals composed by VStartup, VUpdate, and VReady;h]hnGlobal sync signals (green): It is a set of synchronization signals composed by VStartup, VUpdate, and VReady;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h2Config interface: Responsible to configure blocks;h]h)}(hj%h]h2Config interface: Responsible to configure blocks;}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj#ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hFSideband signals: All other signals that do not fit the previous one. h]h)}(hESideband signals: All other signals that do not fit the previous one.h]hESideband signals: All other signals that do not fit the previous one.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhj:ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhhhhhhhKDubh)}(hThese signals are essential and play an important role in DCN. Nevertheless, the Global Sync deserves an extra level of detail described in the next section.h]hThese signals are essential and play an important role in DCN. Nevertheless, the Global Sync deserves an extra level of detail described in the next section.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhhhhubh)}(hXAll of these components are represented by a data structure named dc_state. From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC, we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind that HUBP accesses a surface using a specific format read from memory, and our dc_plane should work to convert all pixels in the plane to something that can be sent to the display via dc_stream and dc_link.h]hXAll of these components are represented by a data structure named dc_state. From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC, we have dc_stream, and the output (DIO) is handled by dc_link. Keep in mind that HUBP accesses a surface using a specific format read from memory, and our dc_plane should work to convert all pixels in the plane to something that can be sent to the display via dc_stream and dc_link.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhhhhubh)}(hhh](h)}(hFront End and Back Endh]hFront End and Back End}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhhhhhKVubh)}(hDisplay pipeline can be broken down into two components that are usually referred as **Front End (FE)** and **Back End (BE)**, where FE consists of:h](hUDisplay pipeline can be broken down into two components that are usually referred as }(hjhhhNhNubj)}(h**Front End (FE)**h]hFront End (FE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h**Back End (BE)**h]h Back End (BE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, where FE consists of:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKXhjyhhubj )}(hhh](j)}(h5DCHUB (Mainly referring to a subcomponent named HUBP)h]h)}(hjh]h5DCHUB (Mainly referring to a subcomponent named HUBP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hDPPh]h)}(hjh]hDPP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMPC h]h)}(hMPCh]hMPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jhuh1j hhhK[hjyhhubh)}(h On the other hand, BE consist ofh]h On the other hand, BE consist of}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjyhhubj )}(hhh](j)}(hOPPh]h)}(hjh]hOPP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hOPTCh]h)}(hj5h]hOPTC}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhj3ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h.DIO (DP/HDMI stream encoder and link encoder) h]h)}(h-DIO (DP/HDMI stream encoder and link encoder)h]h-DIO (DP/HDMI stream encoder and link encoder)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjJubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jhuh1j hhhKahjyhhubh)}(hXoOPP and OPTC are two joining blocks between FE and BE. On a side note, this is a one-to-one mapping of the link encoder to PHY, but we can configure the DCN to choose which link encoder to connect to which PHY. FE's main responsibility is to change, blend and compose pixel data, while BE's job is to frame a generic pixel stream to a specific display's pixel stream.h]hXuOPP and OPTC are two joining blocks between FE and BE. On a side note, this is a one-to-one mapping of the link encoder to PHY, but we can configure the DCN to choose which link encoder to connect to which PHY. FE’s main responsibility is to change, blend and compose pixel data, while BE’s job is to frame a generic pixel stream to a specific display’s pixel stream.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjyhhubeh}(h]front-end-and-back-endah ]h"]front end and back endah$]h&]uh1hhhhhhhhKVubh)}(hhh](h)}(h Data Flowh]h Data Flow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhKlubh)}(hXInitially, data is passed in from VRAM through Data Fabric (DF) in native pixel formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks different pixel formats and outputs them to DPP in uniform streams through 4 channels (1 for alpha + 3 for colors).h]hXInitially, data is passed in from VRAM through Data Fabric (DF) in native pixel formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks different pixel formats and outputs them to DPP in uniform streams through 4 channels (1 for alpha + 3 for colors).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhj~hhubh)}(hXThe Converter and Cursor (CNVC) in DPP would then normalize the data representation and convert them to a DCN specific floating-point format (i.e., different from the IEEE floating-point format). In the process, CNVC also applies a degamma function to transform the data from non-linear to linear space to relax the floating-point calculations following. Data would stay in this floating-point format from DPP to OPP.h]hXThe Converter and Cursor (CNVC) in DPP would then normalize the data representation and convert them to a DCN specific floating-point format (i.e., different from the IEEE floating-point format). In the process, CNVC also applies a degamma function to transform the data from non-linear to linear space to relax the floating-point calculations following. Data would stay in this floating-point format from DPP to OPP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshj~hhubh)}(hXStarting OPP, because color transformation and blending have been completed (i.e alpha can be dropped), and the end sinks do not require the precision and dynamic range that floating points provide (i.e. all displays are in integer depth format), bit-depth reduction/dithering would kick in. In OPP, we would also apply a regamma function to introduce the gamma removed earlier back. Eventually, we output data in integer format at DIO.h]hXStarting OPP, because color transformation and blending have been completed (i.e alpha can be dropped), and the end sinks do not require the precision and dynamic range that floating points provide (i.e. all displays are in integer depth format), bit-depth reduction/dithering would kick in. In OPP, we would also apply a regamma function to introduce the gamma removed earlier back. Eventually, we output data in integer format at DIO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhj~hhubeh}(h] data-flowah ]h"] data flowah$]h&]uh1hhhhhhhhKlubh)}(hhh](h)}(hAMD Hardware Pipelineh]hAMD Hardware Pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXWhen discussing graphics on Linux, the **pipeline** term can sometimes be overloaded with multiple meanings, so it is important to define what we mean when we say **pipeline**. In the DCN driver, we use the term **hardware pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a sequence of DCN blocks instantiated to address some specific configuration. DC core treats DCN blocks as individual resources, meaning we can build a pipeline by taking resources for all individual hardware blocks to compose one pipeline. In actuality, we can't connect an arbitrary block from one pipe to a block from another pipe; they are routed linearly, except for DSC, which can be arbitrarily assigned as needed. We have this pipeline concept for trying to optimize bandwidth utilization.h](h'When discussing graphics on Linux, the }(hjhhhNhNubj)}(h **pipeline**h]hpipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhp term can sometimes be overloaded with multiple meanings, so it is important to define what we mean when we say }(hjhhhNhNubj)}(h **pipeline**h]hpipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh%. In the DCN driver, we use the term }(hjhhhNhNubj)}(h**hardware pipeline**h]hhardware pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or }(hjhhhNhNubj)}(h **pipeline**h]hpipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh or just }(hjhhhNhNubj)}(h**pipe**h]hpipe}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX as an abstraction to indicate a sequence of DCN blocks instantiated to address some specific configuration. DC core treats DCN blocks as individual resources, meaning we can build a pipeline by taking resources for all individual hardware blocks to compose one pipeline. In actuality, we can’t connect an arbitrary block from one pipe to a block from another pipe; they are routed linearly, except for DSC, which can be arbitrarily assigned as needed. We have this pipeline concept for trying to optimize bandwidth utilization.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh]h)}(hhh]h)}(h,.. kernel-figure:: pipeline_4k_no_split.svg h]h}(h]h ]h"]h$]h&]uri+gpu/amdgpu/display/pipeline_4k_no_split.svgh}hjKsuh1hhj=hhhKubah}(h]h ]h"]h$]h&]uh1hhj:ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hAdditionally, let's take a look at parts of the DTN log (see 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since this log can help us to see part of this pipeline behavior in real-time::h]hAdditionally, let’s take a look at parts of the DTN log (see ‘Documentation/gpu/amdgpu/display/dc-debug.rst’ for more information) since this log can help us to see part of this pipeline behavior in real-time:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh literal_block)}(hXHUBP: format addr_hi width height ... [ 0]: 8h 81h 3840 2160 [ 1]: 0h 0h 0 0 [ 2]: 0h 0h 0 0 [ 3]: 0h 0h 0 0 [ 4]: 0h 0h 0 0 ... MPCC: OPP DPP ... [ 0]: 0h 0h ...h]hXHUBP: format addr_hi width height ... [ 0]: 8h 81h 3840 2160 [ 1]: 0h 0h 0 0 [ 2]: 0h 0h 0 0 [ 3]: 0h 0h 0 0 [ 4]: 0h 0h 0 0 ... MPCC: OPP DPP ... [ 0]: 0h 0h ...}hjisbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jghhhKhjhhubh)}(hXThe first thing to notice from the diagram and DTN log it is the fact that we have different clock domains for each part of the DCN blocks. In this example, we have just a single **pipeline** where the data flows from DCHUB to DIO, as we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and we can split this single pipe differently, as described in the below diagram:h](hThe first thing to notice from the diagram and DTN log it is the fact that we have different clock domains for each part of the DCN blocks. In this example, we have just a single }(hjyhhhNhNubj)}(h **pipeline**h]hpipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh where the data flows from DCHUB to DIO, as we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and we can split this single pipe differently, as described in the below diagram:}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh]h)}(hhh]h)}(h).. kernel-figure:: pipeline_4k_split.svg h]h}(h]h ]h"]h$]h&]uri(gpu/amdgpu/display/pipeline_4k_split.svgh}hjsuh1hhjhhhKubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hJNow, if we inspect the DTN log again we can see some interesting changes::h]hINow, if we inspect the DTN log again we can see some interesting changes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjh)}(hHUBP: format addr_hi width height ... [ 0]: 8h 81h 1920 2160 ... ... [ 4]: 0h 0h 0 0 ... [ 5]: 8h 81h 1920 2160 ... ... MPCC: OPP DPP ... [ 0]: 0h 0h ... [ 5]: 0h 5h ...h]hHUBP: format addr_hi width height ... [ 0]: 8h 81h 1920 2160 ... ... [ 4]: 0h 0h 0 0 ... [ 5]: 8h 81h 1920 2160 ... ... MPCC: OPP DPP ... [ 0]: 0h 0h ... [ 5]: 0h 5h ...}hjsbah}(h]h ]h"]h$]h&]jwjxuh1jghhhKhjhhubh)}(hX From the above example, we now split the display pipeline into two vertical parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the clock frequency in the DPP part. This is not only useful for saving power but also to better handle the required throughput. The idea to keep in mind here is that the pipe configuration can vary a lot according to the display configuration, and it is the DML's responsibility to set up all required configuration parameters for multiple scenarios supported by our hardware.h]hXFrom the above example, we now split the display pipeline into two vertical parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the clock frequency in the DPP part. This is not only useful for saving power but also to better handle the required throughput. The idea to keep in mind here is that the pipe configuration can vary a lot according to the display configuration, and it is the DML’s responsibility to set up all required configuration parameters for multiple scenarios supported by our hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]amd-hardware-pipelineah ]h"]amd hardware pipelineah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Global Synch]h Global Sync}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hMany DCN registers are double buffered, most importantly the surface address. This allows us to update DCN hardware atomically for page flips, as well as for most other updates that don't require enabling or disabling of new pipes.h]hMany DCN registers are double buffered, most importantly the surface address. This allows us to update DCN hardware atomically for page flips, as well as for most other updates that don’t require enabling or disabling of new pipes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h(Note: There are many scenarios when DC will decide to reserve extra pipes in order to support outputs that need a very high pixel clock, or for power saving purposes.)h]h(Note: There are many scenarios when DC will decide to reserve extra pipes in order to support outputs that need a very high pixel clock, or for power saving purposes.)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThese atomic register updates are driven by global sync signals in DCN. In order to understand how atomic updates interact with DCN hardware, and how DCN signals page flip and vblank events it is helpful to understand how global sync is programmed.h]hThese atomic register updates are driven by global sync signals in DCN. In order to understand how atomic updates interact with DCN hardware, and how DCN signals page flip and vblank events it is helpful to understand how global sync is programmed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXGlobal sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml) based on a large number of parameters and ensure our hardware is able to feed the DCN pipeline without underflows or hangs in any given system configuration. The global sync signals always happen during VBlank, are independent from the VSync signal, and do not overlap each other.h]hXGlobal sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml) based on a large number of parameters and ensure our hardware is able to feed the DCN pipeline without underflows or hangs in any given system configuration. The global sync signals always happen during VBlank, are independent from the VSync signal, and do not overlap each other.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX{VUPDATE is the only signal that is of interest to the rest of the driver stack or userspace clients as it signals the point at which hardware latches to atomically programmed (i.e. double buffered) registers. Even though it is independent of the VSync signal we use VUPDATE to signal the VSync event as it provides the best indication of how atomic commits and hardware interact.h]hX{VUPDATE is the only signal that is of interest to the rest of the driver stack or userspace clients as it signals the point at which hardware latches to atomically programmed (i.e. double buffered) registers. Even though it is independent of the VSync signal we use VUPDATE to signal the VSync event as it provides the best indication of how atomic commits and hardware interact.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hrSince DCN hardware is double-buffered the DC driver is able to program the hardware at any point during the frame.h]hrSince DCN hardware is double-buffered the DC driver is able to program the hardware at any point during the frame.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h6The below picture illustrates the global sync signals:h]h6The below picture illustrates the global sync signals:}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh]h)}(hhh]h)}(h*.. kernel-figure:: global_sync_vblank.svg h]h}(h]h ]h"]h$]h&]uri)gpu/amdgpu/display/global_sync_vblank.svgh}hjnsuh1hhj`hhhKubah}(h]h ]h"]h$]h&]uh1hhj]ubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThese signals affect core DCN behavior. Programming them incorrectly will lead to a number of negative consequences, most of them quite catastrophic.h]hThese signals affect core DCN behavior. Programming them incorrectly will lead to a number of negative consequences, most of them quite catastrophic.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThe following picture shows how global sync allows for a mailbox style of updates, i.e. it allows for multiple re-configurations between VUpdate events where only the last configuration programmed before the VUpdate signal becomes effective.h]hThe following picture shows how global sync allows for a mailbox style of updates, i.e. it allows for multiple re-configurations between VUpdate events where only the last configuration programmed before the VUpdate signal becomes effective.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh]h)}(hhh]h)}(h%.. kernel-figure:: config_example.svgh]h}(h]h ]h"]h$]h&]uri%gpu/amdgpu/display/config_example.svgh}hjsuh1hhjhhhKubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubeh}(h] global-syncah ]h"] global syncah$]h&]uh1hhhhhhhhKubeh}(h](display-core-next-dcnheh ]h"](display core next (dcn) dcn_overvieweh$]h&]uh1hhhhhhhhKexpect_referenced_by_name}jhsexpect_referenced_by_id}hhsubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}h]hasnameids}(jhjjj{jxjjjjjju nametypes}(jjj{jjjuh}(hhjhjxjyjj~jjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages]hsystem_message)}(hhh]h)}(hhh]h2Hyperlink target "dcn-overview" is not referenced.}hjYsbah}(h]h ]h"]h$]h&]uh1hhjVubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1jTuba transformerN include_log] decorationNhhub.