^sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget1/translations/zh_CN/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/zh_TW/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/it_IT/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ja_JP/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ko_KR/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/pt_BR/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/sp_SP/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhtarget)}(h.. _dcn_blocks:h]h}(h]h ]h"]h$]h&]refid dcn-blocksuh1hhKhhhhhK/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks.rstubhsection)}(hhh](htitle)}(h DCN Blocksh]h DCN Blocks}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hIn this section, you will find some extra details about some of the DCN blocks and the code documentation when it is automatically generated.h]hIn this section, you will find some extra details about some of the DCN blocks and the code documentation when it is automatically generated.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hDCHUBBUBh]hDCHUBBUB}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hThere is only one common DCHUBBUB. It contains the common request and return blocks for the Data Fabric Interface that are not clock/power gated.h]hThere is only one common DCHUBBUB. It contains the common request and return blocks for the Data Fabric Interface that are not clock/power gated.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh~/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:13: ./drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.hhKhhhhubeh}(h]dchubbubah ]h"]dchubbubah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hHUBPh]hHUBP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hDisplay Controller Hub (DCHUB) is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.h]hDisplay Controller Hub (DCHUB) is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhz/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:19: ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.hhKhjhhubh)}(hThere is one HUBP allocated per pipe, which fetches data and converts different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved and fixed-depth streams of pixel data.h]hThere is one HUBP allocated per pipe, which fetches data and converts different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved and fixed-depth streams of pixel data.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhz/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:19: ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.hhK"hjhhubeh}(h]hubpah ]h"]hubpah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDPPh]hDPP}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhhhhhKubh)}(hX/The DPP (Display Pipe and Plane) block is the unified display data processing engine in DCN for processing graphic or video data on per DPP rectangle base. This rectangle can be a part of SLS (Single Large Surface), or a layer to be blended with other DPP, or a rectangle associated with a display tile.h]hX/The DPP (Display Pipe and Plane) block is the unified display data processing engine in DCN for processing graphic or video data on per DPP rectangle base. This rectangle can be a part of SLS (Single Large Surface), or a layer to be blended with other DPP, or a rectangle associated with a display tile.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjHhhubh)}(hXIIt provides various functions including: - graphic color keyer - graphic cursor compositing - graphic or video image source to destination scaling - image sharping - video format conversion from 4:2:0 or 4:2:2 to 4:4:4 - Color Space Conversion - Host LUT gamma adjustment - Color Gamut Remap - brightness and contrast adjustment.h]hXIIt provides various functions including: - graphic color keyer - graphic cursor compositing - graphic or video image source to destination scaling - image sharping - video format conversion from 4:2:0 or 4:2:2 to 4:4:4 - Color Space Conversion - Host LUT gamma adjustment - Color Gamut Remap - brightness and contrast adjustment.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhK%hjHhhubh)}(hDPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module connected in a video/graphics pipeline.h]hDPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module connected in a video/graphics pipeline.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhK0hjHhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlecnv_alpha_2bit_lut (C struct)c.cnv_alpha_2bit_luthNtauh1jhjHhhhNhNubhdesc)}(hhh](hdesc_signature)}(hcnv_alpha_2bit_luth]hdesc_signature_line)}(hstruct cnv_alpha_2bit_luth](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hcnv_alpha_2bit_luth]h desc_sig_name)}(hjh]hcnv_alpha_2bit_lut}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(h2Set the 8bit alpha values based on the 2 bit alphah]h2Set the 8bit alpha values based on the 2 bit alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhjHhNhNubh container)}(hX**Definition**:: struct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; }; **Members** ``lut0`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000 ``lut1`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101 ``lut2`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010 ``lut3`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j1hj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj)ubh literal_block)}(hVstruct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; };h]hVstruct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; };}hjNsbah}(h]h ]h"]h$]h&]jjuh1jLhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj)ubh)}(h **Members**h]j2)}(hj_h]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j1hj]ubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj)ubhdefinition_list)}(hhh](hdefinition_list_item)}(h>``lut0`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000 h](hterm)}(h``lut0``h]hliteral)}(hjh]hlut0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj|ubh definition)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jzhjhKhjwubj{)}(h>``lut1`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101 h](j)}(h``lut1``h]j)}(hjh]hlut1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhKhjwubj{)}(h>``lut2`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010 h](j)}(h``lut2``h]j)}(hjh]hlut2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhKhjwubj{)}(h=``lut3`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h](j)}(h``lut3``h]j)}(hj3h]hlut3}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj-ubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jzhjHhKhjwubeh}(h]h ]h"]h$]h&]uh1juhj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hjHhhhNhNubeh}(h]dppah ]h"]dppah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMPCh]hMPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhhhK ubh)}(hX7Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline that performs blending of multiple planes, using global and per-pixel alpha. It also performs post-blending color correction operations according to the hardware capabilities, such as color transformation matrix and gamma 1D and 3D LUT.h]hX7Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline that performs blending of multiple planes, using global and per-pixel alpha. It also performs post-blending color correction operations according to the hardware capabilities, such as color transformation matrix and gamma 1D and 3D LUT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhj|hhubh)}(hMPC receives output from all DPP pipes and combines them to multiple outputs supporting "M MPC inputs -> N MPC outputs" flexible composition architecture. It features:h]hMPC receives output from all DPP pipes and combines them to multiple outputs supporting “M MPC inputs -> N MPC outputs” flexible composition architecture. It features:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK!hj|hhubh bullet_list)}(hhh](h list_item)}(hTProgrammable blending structure to allow software controlled blending and cascading;h]h)}(hTProgrammable blending structure to allow software controlled blending and cascading;h]hTProgrammable blending structure to allow software controlled blending and cascading;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hEProgrammable window location of each DPP in active region of display;h]h)}(hjh]hEProgrammable window location of each DPP in active region of display;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;h]h)}(hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;h]hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h8Combining multiple DPP from different SLS with blending;h]h)}(hjh]h8Combining multiple DPP from different SLS with blending;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hCStereo formats from single DPP in top-bottom or side-by-side modes;h]h)}(hjh]hCStereo formats from single DPP in top-bottom or side-by-side modes;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hStereo formats from 2 DPPs;h]h)}(hj.h]hStereo formats from 2 DPPs;}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK,hj,ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h;Alpha blending of multiple layers from different DPP pipes;h]h)}(hjFh]h;Alpha blending of multiple layers from different DPP pipes;}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK-hjDubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h Programmable background color; h]h)}(hProgrammable background color;h]hProgrammable background color;}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK.hj\ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhK%hj|hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpcc (C struct)c.mpcchNtauh1jhj|hhhNhNubj)}(hhh](j)}(hmpcch]j)}(h struct mpcch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hmpcch]j)}(hjh]hmpcc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hFMPCC connection and blending configuration for a single MPCC instance.h]hFMPCC connection and blending configuration for a single MPCC instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j!jj"jj#jj$j%j&uh1jhhhj|hNhNubj()}(hX,**Definition**:: struct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; }; **Members** ``mpcc_id`` MPCC physical instance. ``dpp_id`` DPP input to this MPCC ``mpcc_bot`` Pointer to bottom layer MPCC. NULL when not connected. ``blnd_cfg`` The blending configuration for this MPCC. ``sm_cfg`` stereo mix setting for this MPCC ``shared_bottom`` If MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h](h)}(h**Definition**::h](j2)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubjM)}(hstruct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; };h]hstruct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jLhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubh)}(h **Members**h]j2)}(hj&h]hMembers}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j1hj$ubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubjv)}(hhh](j{)}(h$``mpcc_id`` MPCC physical instance. h](j)}(h ``mpcc_id``h]j)}(hjEh]hmpcc_id}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hj?ubj)}(hhh]h)}(hMPCC physical instance.h]hMPCC physical instance.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhM hj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jzhjZhM hj<ubj{)}(h"``dpp_id`` DPP input to this MPCC h](j)}(h ``dpp_id``h]j)}(hj~h]hdpp_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjxubj)}(hhh]h)}(hDPP input to this MPCCh]hDPP input to this MPCC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jzhjhMhj<ubj{)}(hD``mpcc_bot`` Pointer to bottom layer MPCC. NULL when not connected. h](j)}(h ``mpcc_bot``h]j)}(hjh]hmpcc_bot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(h6Pointer to bottom layer MPCC. NULL when not connected.h]h6Pointer to bottom layer MPCC. NULL when not connected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhj<ubj{)}(h7``blnd_cfg`` The blending configuration for this MPCC. h](j)}(h ``blnd_cfg``h]j)}(hjh]hblnd_cfg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(h)The blending configuration for this MPCC.h]h)The blending configuration for this MPCC.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhj<ubj{)}(h,``sm_cfg`` stereo mix setting for this MPCC h](j)}(h ``sm_cfg``h]j)}(hj)h]hsm_cfg}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM!hj#ubj)}(hhh]h)}(h stereo mix setting for this MPCCh]h stereo mix setting for this MPCC}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hM!hj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jzhj>hM!hj<ubj{)}(hW``shared_bottom`` If MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h](j)}(h``shared_bottom``h]j)}(hjbh]h shared_bottom}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM%hj\ubj)}(hhh]h)}(hEIf MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h]hEIf MPCC output to both OPP and DWB endpoints, true. Otherwise, false.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM&hjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jzhjwhM%hj<ubeh}(h]h ]h"]h$]h&]uh1juhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj|hhhNhNubh)}(h**Description**h]j2)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM)hj|hhubh)}(h-This struct is used as a node in an MPC tree.h]h-This struct is used as a node in an MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj|hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_tree (C struct) c.mpc_treehNtauh1jhj|hhhNhNubj)}(hhh](j)}(hmpc_treeh]j)}(hstruct mpc_treeh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubj)}(hmpc_treeh]j)}(hjh]hmpc_tree}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhM hjhhubj)}(hhh]h)}(h4MPC tree represents all MPCC connections for a pipe.h]h4MPC tree represents all MPCC connections for a pipe.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hj"hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jstructeh"]h$]h&]j!jj"j=j#j=j$j%j&uh1jhhhj|hNhNubj()}(h**Definition**:: struct mpc_tree { int opp_id; struct mpcc *opp_list; }; **Members** ``opp_id`` The OPP instance that owns this MPC tree. ``opp_list`` the top MPCC layer of the MPC tree that outputs to OPP endpointh](h)}(h**Definition**::h](j2)}(h**Definition**h]h Definition}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjEubh:}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM1hjAubjM)}(h?struct mpc_tree { int opp_id; struct mpcc *opp_list; };h]h?struct mpc_tree { int opp_id; struct mpcc *opp_list; };}hjbsbah}(h]h ]h"]h$]h&]jjuh1jLhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM3hjAubh)}(h **Members**h]j2)}(hjsh]hMembers}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjqubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM8hjAubjv)}(hhh](j{)}(h5``opp_id`` The OPP instance that owns this MPC tree. h](j)}(h ``opp_id``h]j)}(hjh]hopp_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM4hjubj)}(hhh]h)}(h)The OPP instance that owns this MPC tree.h]h)The OPP instance that owns this MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM4hjubj{)}(hL``opp_list`` the top MPCC layer of the MPC tree that outputs to OPP endpointh](j)}(h ``opp_list``h]j)}(hjh]hopp_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM8hjubj)}(hhh]h)}(h?the top MPCC layer of the MPC tree that outputs to OPP endpointh]h?the top MPCC layer of the MPC tree that outputs to OPP endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM8hjubeh}(h]h ]h"]h$]h&]uh1juhjAubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj|hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_funcs (C struct) c.mpc_funcshNtauh1jhj|hhhNhNubj)}(hhh](j)}(h mpc_funcsh]j)}(hstruct mpc_funcsh](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM?ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhj2hM?ubj)}(h mpc_funcsh]j)}(hjh]h mpc_funcs}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ](jjeh"]h$]h&]jjuh1jhj!hhhj2hM?ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj2hM?ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj2hM?hjhhubj)}(hhh]h)}(hfuncsh]hfuncs}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMdhjdhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj2hM?ubeh}(h]h ](jstructeh"]h$]h&]j!jj"jj#jj$j%j&uh1jhhhj|hNhNubj()}(hX>**Definition**:: struct mpc_funcs { void (*read_mpcc_state)( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s); void (*mpc_read_reg_state)( struct mpc *mpc, int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state); struct mpcc* (*insert_plane)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)( struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)( struct mpc *mpc, int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)( struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)( struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)( struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc, int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)( struct mpc *mpc, int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)( struct mpc *mpc, int mpcc_id, bool power_on); void (*set_dwb_mux)( struct mpc *mpc, int dwb_id, int mpcc_id); void (*disable_dwb_mux)( struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)( struct mpc *mpc, int dwb_id); void (*set_out_rate_control)( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)( struct mpc *mpc, const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)( struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params *params, const bool lut_bank_a, const int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool lut_bank_a, const unsigned int bit_depth, const int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool enable, const bool lut_bank_a, const enum dc_cm_lut_size size, const int mpcc_id); void (*get_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const int mpcc_id, bool *enable, bool *lut_bank_a); struct { void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id); void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, bool enable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on); void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*get_3dlut_mode)(struct mpc *mpc, int mpcc_id, bool *enable, bool *lut_bank_a); } rmcm; }; **Members** ``read_mpcc_state`` Read register content from given MPCC physical instance. Parameters: - [in/out] mpc - MPC context - [in] mpcc_instance - MPC context instance - [in] mpcc_state - MPC context state Return: void ``mpc_read_reg_state`` Read MPC register state for debugging underflow purposes. Parameters: - [in] mpc - MPC context - [out] reg_state - MPC register state structure Return: void ``insert_plane`` Insert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. ``remove_mpcc`` Remove a specified MPCC from the MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in/out] mpcc - MPCC to be removed from tree. Return: void ``mpc_init`` Reset the MPCC HW status by disconnecting all muxes. Parameters: - [in/out] mpc - MPC context. Return: void ``mpc_init_single_inst`` Initialize given MPCC physical instance. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized. ``update_blending`` Update the blending configuration for a specified MPCC. Parameters: - [in/out] mpc - MPC context. - [in] blnd_cfg - MPCC blending configuration. - [in] mpcc_id - The MPCC physical instance. Return: void ``cursor_lock`` Lock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor. Parameters: - [in] mpc - MPC context. - [in] opp_id - The OPP to lock cursor updates on - [in] lock - lock/unlock the OPP Return: void ``insert_plane_to_secondary`` Add DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. ``remove_mpcc_from_secondary`` Remove a specified DPP from the 'secondary' MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in] mpcc - MPCC to be removed from tree. Return: void ``get_mpcc_for_dpp_from_secondary`` Find, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. ``get_mpcc_for_dpp`` Find, if it exists, a MPCC from a given MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. ``wait_for_idle`` Wait for a MPCC in MPC context to enter idle state. Parameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state. Return: void ``assert_mpcc_idle_before_connect`` Assert if MPCC in MPC context is in idle state. Parameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state. Return: void ``init_mpcc_list_from_hw`` Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values. Parameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. Return: void ``set_denorm`` Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode. Return: void ``set_denorm_clamp`` Set denorm clamp values on corresponding OPP DENORM CONTROL register. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set. Return: void ``set_output_csc`` Set the Output Color Space Conversion matrix with given values and mode. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC. Return: void ``set_ocsc_default`` Set the Output Color Space Conversion matrix to default values according to color space. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC. Return: void ``set_output_gamma`` Set Output Gamma with given curve parameters. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters. Return: void ``power_on_mpc_mem_pwr`` Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on Return: void ``set_dwb_mux`` Set corresponding Display Writeback mux MPC register field to given MPCC id. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register. Return: void ``disable_dwb_mux`` Reset corresponding Display Writeback mux MPC register field. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. Return: void ``is_dwb_idle`` Check DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked. Return: bool - wheter DWB is idle or not ``set_out_rate_control`` Set display output rate control. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control Return: void ``set_gamut_remap`` Set post-blending CTM for given MPCC. Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust Return: void ``program_1dlut`` Set 1 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). ``program_shaper`` Set shaper. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx Return: bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). ``acquire_rmu`` Set given MPCC to be multiplexed to given RMU unit. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. Return: unit32_t - rmu_idx if operation was successful, -1 else. ``program_3dlut`` Set 3 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). ``release_rmu`` For a given MPCC, release the RMU unit it muliplexes to. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC Return: int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. ``get_mpc_out_mux`` Return MPC out mux. Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP Return: unsigned int - Out Mux ``set_bg_color`` Find corresponding bottommost MPCC and set its bg color. Parameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id Return: void ``set_mpc_mem_lp_mode`` Set mpc_mem_lp_mode. Parameters: - [in/out] mpc - MPC context. Return: void ``set_movable_cm_location`` Set Movable CM Location. Parameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id Return: void ``update_3dlut_fast_load_select`` Update 3D LUT fast load select. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx Return: void ``get_3dlut_fast_load_status`` Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow Return: void ``populate_lut`` Populate LUT with given tetrahedral parameters. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id Return: void ``program_lut_read_write_control`` Program LUT RW control. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] bit_depth - [in] mpcc_id Return: void ``program_lut_mode`` Program LUT mode. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] enable - [in] lut_bank_a - [in] size - [in] mpcc_id Return: void ``get_lut_mode`` Obtains enablement and ram bank status. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] mpcc_id - [out] enable - [out] lut_bank_a Return: void ``rmcm`` MPC RMCM new HW sequential programming functionsh](h)}(h**Definition**::h](j2)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhhjubjM)}(hX"struct mpc_funcs { void (*read_mpcc_state)( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s); void (*mpc_read_reg_state)( struct mpc *mpc, int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state); struct mpcc* (*insert_plane)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)( struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)( struct mpc *mpc, int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)( struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)( struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)( struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc, int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)( struct mpc *mpc, int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)( struct mpc *mpc, int mpcc_id, bool power_on); void (*set_dwb_mux)( struct mpc *mpc, int dwb_id, int mpcc_id); void (*disable_dwb_mux)( struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)( struct mpc *mpc, int dwb_id); void (*set_out_rate_control)( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)( struct mpc *mpc, const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)( struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params *params, const bool lut_bank_a, const int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool lut_bank_a, const unsigned int bit_depth, const int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool enable, const bool lut_bank_a, const enum dc_cm_lut_size size, const int mpcc_id); void (*get_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const int mpcc_id, bool *enable, bool *lut_bank_a); struct { void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id); void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, bool enable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on); void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*get_3dlut_mode)(struct mpc *mpc, int mpcc_id, bool *enable, bool *lut_bank_a); } rmcm; };h]hX"struct mpc_funcs { void (*read_mpcc_state)( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s); void (*mpc_read_reg_state)( struct mpc *mpc, int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state); struct mpcc* (*insert_plane)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)( struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)( struct mpc *mpc, int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc_blnd_cfg *blnd_cfg, struct mpcc_sm_cfg *sm_cfg, struct mpcc *insert_above_mpcc, int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)( struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)( struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)( struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc, int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)( struct mpc *mpc, int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)( struct mpc *mpc, int mpcc_id, bool power_on); void (*set_dwb_mux)( struct mpc *mpc, int dwb_id, int mpcc_id); void (*disable_dwb_mux)( struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)( struct mpc *mpc, int dwb_id); void (*set_out_rate_control)( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)( struct mpc *mpc, const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)( struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params *params, const bool lut_bank_a, const int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool lut_bank_a, const unsigned int bit_depth, const int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const bool enable, const bool lut_bank_a, const enum dc_cm_lut_size size, const int mpcc_id); void (*get_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const int mpcc_id, bool *enable, bool *lut_bank_a); struct { void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id); void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, bool enable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on); void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*get_3dlut_mode)(struct mpc *mpc, int mpcc_id, bool *enable, bool *lut_bank_a); } rmcm; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jLhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMjhjubh)}(h **Members**h]j2)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubjv)}(hhh](j{)}(h``read_mpcc_state`` Read register content from given MPCC physical instance. Parameters: - [in/out] mpc - MPC context - [in] mpcc_instance - MPC context instance - [in] mpcc_state - MPC context state Return: void h](j)}(h``read_mpcc_state``h]j)}(hjh]hread_mpcc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMshjubj)}(hhh](h)}(h8Read register content from given MPCC physical instance.h]h8Read register content from given MPCC physical instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMihjubh)}(h Parameters:h]h Parameters:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMkhjubj)}(hhh](j)}(h[in/out] mpc - MPC contexth]h)}(hj h]h[in/out] mpc - MPC context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMmhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h)[in] mpcc_instance - MPC context instanceh]h)}(hj( h]h)[in] mpcc_instance - MPC context instance}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMnhj& ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h$[in] mpcc_state - MPC context state h]h)}(h#[in] mpcc_state - MPC context stateh]h#[in] mpcc_state - MPC context state}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMohj> ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]j{j|uh1jhj hMmhjubh)}(hReturn:h]hReturn:}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMqhjubh)}(hvoidh]hvoid}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMshjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMshjubj{)}(h``mpc_read_reg_state`` Read MPC register state for debugging underflow purposes. Parameters: - [in] mpc - MPC context - [out] reg_state - MPC register state structure Return: void h](j)}(h``mpc_read_reg_state``h]j)}(hj h]hmpc_read_reg_state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h9Read MPC register state for debugging underflow purposes.h]h9Read MPC register state for debugging underflow purposes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM|hj ubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM~hj ubj)}(hhh](j)}(h[in] mpc - MPC contexth]h)}(hj h]h[in] mpc - MPC context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h/[out] reg_state - MPC register state structure h]h)}(h.[out] reg_state - MPC register state structureh]h.[out] reg_state - MPC register state structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]j{j|uh1jhj hMhj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhjubj{)}(hX``insert_plane`` Insert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. ph](j)}(h``insert_plane``h]j)}(hj, h]h insert_plane}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj* ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj& ubj)}(hhh](h)}(hInsert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP outputh]hInsert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjB ubh)}(h Parameters:h]h Parameters:}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjB ubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hjh h]h[in/out] mpc - MPC context.}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjf ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(h?[in/out] tree - MPC tree structure that plane will be added to.h]h)}(hj h]h?[in/out] tree - MPC tree structure that plane will be added to.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj~ ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.h]h)}(hj h]hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h]jv)}(hhh]j{)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h](j)}(hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.h]hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh]h)}(hEstereo mix must disable for the very bottom layer of the tree config.h]hEstereo mix must disable for the very bottom layer of the tree config.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhj ubah}(h]h ]h"]h$]h&]uh1juhj ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(hr[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h]jv)}(hhh]j{)}(h[[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h](j)}(h:[in] insert_above_mpcc - Insert new plane above this MPCC.h]h:[in] insert_above_mpcc - Insert new plane above this MPCC.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh]h)}(h If NULL, insert as bottom plane.h]h If NULL, insert as bottom plane.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhj ubah}(h]h ]h"]h$]h&]uh1juhj ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(h6[in] dpp_id - DPP instance for the plane to be added.h]h)}(hj8 h]h6[in] dpp_id - DPP instance for the plane to be added.}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj6 ubah}(h]h ]h"]h$]h&]uh1jhjc ubj)}(h?[in] mpcc_id - The MPCC physical instance to use for blending. h]h)}(h>[in] mpcc_id - The MPCC physical instance to use for blending.h]h>[in] mpcc_id - The MPCC physical instance to use for blending.}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjN ubah}(h]h ]h"]h$]h&]uh1jhjc ubeh}(h]h ]h"]h$]h&]j{j|uh1jhjw hMhjB ubh)}(hReturn:h]hReturn:}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjB ubh)}(h#struct mpcc* - MPCC that was added.h]h#struct mpcc* - MPCC that was added.}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA hMhjB ubeh}(h]h ]h"]h$]h&]uh1jhj& ubeh}(h]h ]h"]h$]h&]uh1jzhjA hMhjubj{)}(h``remove_mpcc`` Remove a specified MPCC from the MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in/out] mpcc - MPCC to be removed from tree. Return: void h](j)}(h``remove_mpcc``h]j)}(hj h]h remove_mpcc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h*Remove a specified MPCC from the MPC tree.h]h*Remove a specified MPCC from the MPC tree.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hj h]h[in/out] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hD[in/out] tree - MPC tree structure that plane will be removed from.h]h)}(hj h]hD[in/out] tree - MPC tree structure that plane will be removed from.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h/[in/out] mpcc - MPCC to be removed from tree. h]h)}(h.[in/out] mpcc - MPCC to be removed from tree.h]h.[in/out] mpcc - MPCC to be removed from tree.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]j{j|uh1jhj hMhj ubh)}(hReturn:h]hReturn:}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhjubj{)}(h}``mpc_init`` Reset the MPCC HW status by disconnecting all muxes. Parameters: - [in/out] mpc - MPC context. Return: void h](j)}(h ``mpc_init``h]j)}(hjT h]hmpc_init}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjN ubj)}(hhh](h)}(h4Reset the MPCC HW status by disconnecting all muxes.h]h4Reset the MPCC HW status by disconnecting all muxes.}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjj ubh)}(h Parameters:h]h Parameters:}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjj ubj)}(hhh]j)}(h[in/out] mpc - MPC context. h]h)}(hn/out] mpc - MPC context.h]hn/out] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]j{j|uh1jhj hMhjj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjj ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhji hMhjj ubeh}(h]h ]h"]h$]h&]uh1jhjN ubeh}(h]h ]h"]h$]h&]uh1jzhji hMhjubj{)}(h``mpc_init_single_inst`` Initialize given MPCC physical instance. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized. h](j)}(h``mpc_init_single_inst``h]j)}(hj h]hmpc_init_single_inst}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h(Initialize given MPCC physical instance.h]h(Initialize given MPCC physical instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hhParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized.h]hhParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhjubj{)}(h``update_blending`` Update the blending configuration for a specified MPCC. Parameters: - [in/out] mpc - MPC context. - [in] blnd_cfg - MPCC blending configuration. - [in] mpcc_id - The MPCC physical instance. Return: void h](j)}(h``update_blending``h]j)}(hj% h]hupdate_blending}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj# ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h7Update the blending configuration for a specified MPCC.h]h7Update the blending configuration for a specified MPCC.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj; ubh)}(h Parameters:h]h Parameters:}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj; ubj)}(hhh](j)}(hn/out] mpc - MPC context.h]h)}(hja h]hn/out] mpc - MPC context.}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj_ ubah}(h]h ]h"]h$]h&]uh1jhj\ ubj)}(h,[in] blnd_cfg - MPCC blending configuration.h]h)}(hjy h]h,[in] blnd_cfg - MPCC blending configuration.}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjw ubah}(h]h ]h"]h$]h&]uh1jhj\ ubj)}(h,[in] mpcc_id - The MPCC physical instance. h]h)}(h+[in] mpcc_id - The MPCC physical instance.h]h+[in] mpcc_id - The MPCC physical instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj\ ubeh}(h]h ]h"]h$]h&]j{j|uh1jhjp hMhj; ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj; ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj: hMhj; ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj: hMhjubj{)}(hX``cursor_lock`` Lock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor. Parameters: - [in] mpc - MPC context. - [in] opp_id - The OPP to lock cursor updates on - [in] lock - lock/unlock the OPP Return: void h](j)}(h``cursor_lock``h]j)}(hj h]h cursor_lock}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(hkLock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor.h]hkLock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(h Parameters:h]h Parameters:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](j)}(h[in] mpc - MPC context.h]h)}(hjh]h[in] mpc - MPC context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h0[in] opp_id - The OPP to lock cursor updates onh]h)}(hj1h]h0[in] opp_id - The OPP to lock cursor updates on}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj/ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h [in] lock - lock/unlock the OPP h]h)}(h[in] lock - lock/unlock the OPPh]h[in] lock - lock/unlock the OPP}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjGubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j{j|uh1jhj(hMhj ubh)}(hReturn:h]hReturn:}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jzhj hMhjubj{)}(hX ``insert_plane_to_secondary`` Add DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. h](j)}(h``insert_plane_to_secondary``h]j)}(hjh]hinsert_plane_to_secondary}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hAdd DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB outputh]hAdd DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h Parameters:h]h Parameters:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hjh]h[in/out] mpc - MPC context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h?[in/out] tree - MPC tree structure that plane will be added to.h]h)}(hjh]h?[in/out] tree - MPC tree structure that plane will be added to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.h]h)}(hjh]hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h]jv)}(hhh]j{)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h](j)}(hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.h]hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(hEstereo mix must disable for the very bottom layer of the tree config.h]hEstereo mix must disable for the very bottom layer of the tree config.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhj0hMhjubah}(h]h ]h"]h$]h&]uh1juhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hc[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h]jv)}(hhh]j{)}(h\[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h](j)}(h>[in] insert_above_mpcc - Insert new plane above this MPCC. Ifh]h>[in] insert_above_mpcc - Insert new plane above this MPCC. If}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjbubj)}(hhh]h)}(hNULL, insert as bottom plane.h]hNULL, insert as bottom plane.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjuubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jzhjthMhj_ubah}(h]h ]h"]h$]h&]uh1juhj[ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h5[in] dpp_id - DPP instance for the plane to be added.h]h)}(hjh]h5[in] dpp_id - DPP instance for the plane to be added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h?[in] mpcc_id - The MPCC physical instance to use for blending. h]h)}(h>[in] mpcc_id - The MPCC physical instance to use for blending.h]h>[in] mpcc_id - The MPCC physical instance to use for blending.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j{j|uh1jhjhM hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h#struct mpcc* - MPCC that was added.h]h#struct mpcc* - MPCC that was added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX``remove_mpcc_from_secondary`` Remove a specified DPP from the 'secondary' MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in] mpcc - MPCC to be removed from tree. Return: void h](j)}(h``remove_mpcc_from_secondary``h]j)}(hjh]hremove_mpcc_from_secondary}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM1hjubj)}(hhh](h)}(h5Remove a specified DPP from the 'secondary' MPC tree.h]h9Remove a specified DPP from the ‘secondary’ MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM'hjubh)}(h Parameters:h]h Parameters:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM)hjubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hjAh]h[in/out] mpc - MPC context.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM+hj?ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hC[in/out] tree - MPC tree structure that plane will be removed from.h]h)}(hjYh]hC[in/out] tree - MPC tree structure that plane will be removed from.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM,hjWubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(h.[in] mpcc - MPCC to be removed from tree. h]h)}(h-[in] mpcc - MPCC to be removed from tree.h]h-[in] mpcc - MPCC to be removed from tree.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hjoubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]j{j|uh1jhjPhM+hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM/hjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM1hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM1hjubj{)}(hX:``get_mpcc_for_dpp_from_secondary`` Find, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. h](j)}(h#``get_mpcc_for_dpp_from_secondary``h]j)}(hjh]hget_mpcc_for_dpp_from_secondary}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMDhjubj)}(hhh](h)}(heFind, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane.h]hiFind, if it exists, a MPCC from a given ‘secondary’ MPC tree that is associated with specified plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM;hjubh)}(hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.h]hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM>hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMBhjubh)}(h:struct mpcc* - pointer to plane or NULL if no plane found.h]h:struct mpcc* - pointer to plane or NULL if no plane found.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMDhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMDhjubj{)}(hX``get_mpcc_for_dpp`` Find, if it exists, a MPCC from a given MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. h](j)}(h``get_mpcc_for_dpp``h]j)}(hj#h]hget_mpcc_for_dpp}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMVhjubj)}(hhh](h)}(hYFind, if it exists, a MPCC from a given MPC tree that is associated with specified plane.h]hYFind, if it exists, a MPCC from a given MPC tree that is associated with specified plane.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMMhj9ubh)}(hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.h]hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMPhj9ubh)}(hReturn:h]hReturn:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMThj9ubh)}(h:struct mpcc* - pointer to plane or NULL if no plane found.h]h:struct mpcc* - pointer to plane or NULL if no plane found.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMVhj9ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhj8hMVhjubj{)}(h``wait_for_idle`` Wait for a MPCC in MPC context to enter idle state. Parameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state. Return: void h](j)}(h``wait_for_idle``h]j)}(hjh]h wait_for_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMghjubj)}(hhh](h)}(h3Wait for a MPCC in MPC context to enter idle state.h]h3Wait for a MPCC in MPC context to enter idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM_hjubh)}(hRParameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state.h]hRParameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMahjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMehjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMghjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMghjubj{)}(h``assert_mpcc_idle_before_connect`` Assert if MPCC in MPC context is in idle state. Parameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state. Return: void h](j)}(h#``assert_mpcc_idle_before_connect``h]j)}(hjh]hassert_mpcc_idle_before_connect}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMvhjubj)}(hhh](h)}(h/Assert if MPCC in MPC context is in idle state.h]h/Assert if MPCC in MPC context is in idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMnhjubh)}(hPParameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state.h]hPParameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMphjubh)}(hReturn:h]hReturn:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMthjubh)}(hvoidh]hvoid}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMvhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMvhjubj{)}(hX6``init_mpcc_list_from_hw`` Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values. Parameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. Return: void h](j)}(h``init_mpcc_list_from_hw``h]j)}(hjUh]hinit_mpcc_list_from_hw}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjOubj)}(hhh](h)}(hzIterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values.h]h|Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers’ values.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM}hjkubh)}(hParameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize.h]hParameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjkubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjkubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhMhjkubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jzhjjhMhjubj{)}(hX'``set_denorm`` Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode. Return: void h](j)}(h``set_denorm``h]j)}(hjh]h set_denorm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hgSet corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth.h]hgSet corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX``set_denorm_clamp`` Set denorm clamp values on corresponding OPP DENORM CONTROL register. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set. Return: void h](j)}(h``set_denorm_clamp``h]j)}(hj!h]hset_denorm_clamp}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hESet denorm clamp values on corresponding OPP DENORM CONTROL register.h]hESet denorm clamp values on corresponding OPP DENORM CONTROL register.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(hReturn:h]hReturn:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(hvoidh]hvoid}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhj6hMhjubj{)}(hX``set_output_csc`` Set the Output Color Space Conversion matrix with given values and mode. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC. Return: void h](j)}(h``set_output_csc``h]j)}(hjh]hset_output_csc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hHSet the Output Color Space Conversion matrix with given values and mode.h]hHSet the Output Color Space Conversion matrix with given values and mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX)``set_ocsc_default`` Set the Output Color Space Conversion matrix to default values according to color space. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC. Return: void h](j)}(h``set_ocsc_default``h]j)}(hjh]hset_ocsc_default}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hXSet the Output Color Space Conversion matrix to default values according to color space.h]hXSet the Output Color Space Conversion matrix to default values according to color space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``set_output_gamma`` Set Output Gamma with given curve parameters. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters. Return: void h](j)}(h``set_output_gamma``h]j)}(hjSh]hset_output_gamma}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjMubj)}(hhh](h)}(h-Set Output Gamma with given curve parameters.h]h-Set Output Gamma with given curve parameters.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjiubh)}(h}Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters.h]h}Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjiubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjiubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhMhjiubeh}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jzhjhhMhjubj{)}(hX``power_on_mpc_mem_pwr`` Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on Return: void h](j)}(h``power_on_mpc_mem_pwr``h]j)}(hjh]hpower_on_mpc_mem_pwr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h{Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode.h]h{Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h\Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_onh]h\Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``set_dwb_mux`` Set corresponding Display Writeback mux MPC register field to given MPCC id. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register. Return: void h](j)}(h``set_dwb_mux``h]j)}(hjh]h set_dwb_mux}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hLSet corresponding Display Writeback mux MPC register field to given MPCC id.h]hLSet corresponding Display Writeback mux MPC register field to given MPCC id.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj5ubh)}(hParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register.h]hParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hj5ubh)}(hReturn:h]hReturn:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj5ubh)}(hvoidh]hvoid}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMhj5ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhj4hMhjubj{)}(h``disable_dwb_mux`` Reset corresponding Display Writeback mux MPC register field. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. Return: void h](j)}(h``disable_dwb_mux``h]j)}(hjh]hdisable_dwb_mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM$hjubj)}(hhh](h)}(h=Reset corresponding Display Writeback mux MPC register field.h]h=Reset corresponding Display Writeback mux MPC register field.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set.h]hHParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM"hjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM$hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM$hjubj{)}(h``is_dwb_idle`` Check DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked. Return: bool - wheter DWB is idle or not h](j)}(h``is_dwb_idle``h]j)}(hjh]h is_dwb_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM6hjubj)}(hhh](h)}(hMCheck DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null.h]hMCheck DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hjubh)}(hLParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked.h]hLParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM0hjubh)}(hReturn:h]hReturn:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM4hjubh)}(h bool - wheter DWB is idle or noth]h bool - wheter DWB is idle or not}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM6hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM6hjubj{)}(h``set_out_rate_control`` Set display output rate control. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control Return: void h](j)}(h``set_out_rate_control``h]j)}(hjQh]hset_out_rate_control}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMJhjKubj)}(hhh](h)}(h Set display output rate control.h]h Set display output rate control.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM?hjgubh)}(h~Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_controlh]h~Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMAhjgubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMHhjgubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMJhjgubeh}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jzhjfhMJhjubj{)}(h``set_gamut_remap`` Set post-blending CTM for given MPCC. Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust Return: void h](j)}(h``set_gamut_remap``h]j)}(hjh]hset_gamut_remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM_hjubj)}(hhh](h)}(h%Set post-blending CTM for given MPCC.h]h%Set post-blending CTM for given MPCC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMVhjubh)}(h[Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjusth]h[Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMXhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM]hjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM_hjubj{)}(hX ``program_1dlut`` Set 1 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). h](j)}(h``program_1dlut``h]j)}(hjh]h program_1dlut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMphjubj)}(hhh](h)}(hSet 1 dimensional Lookup Table.h]hSet 1 dimensional Lookup Table.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMihj3ubh)}(hrParameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idxh]hrParameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMkhj3ubh)}(hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMphj3ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhj2hMphjubj{)}(h``program_shaper`` Set shaper. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx Return: bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). h](j)}(h``program_shaper``h]j)}(hjth]hprogram_shaper}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjnubj)}(hhh](h)}(h Set shaper.h]h Set shaper.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMzhjubh)}(hbParameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idxh]hbParameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM|hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hebool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hebool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX ``acquire_rmu`` Set given MPCC to be multiplexed to given RMU unit. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. Return: unit32_t - rmu_idx if operation was successful, -1 else. h](j)}(h``acquire_rmu``h]j)}(hjh]h acquire_rmu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h3Set given MPCC to be multiplexed to given RMU unit.h]h3Set given MPCC to be multiplexed to given RMU unit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hParameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to.h]hParameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h8unit32_t - rmu_idx if operation was successful, -1 else.h]h8unit32_t - rmu_idx if operation was successful, -1 else.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX``program_3dlut`` Set 3 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). h](j)}(h``program_3dlut``h]j)}(hj@h]h program_3dlut}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj:ubj)}(hhh](h)}(hSet 3 dimensional Lookup Table.h]hSet 3 dimensional Lookup Table.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjVubh)}(hxParameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idxh]hxParameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjVubh)}(hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMhjVubeh}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jzhjUhMhjubj{)}(h``release_rmu`` For a given MPCC, release the RMU unit it muliplexes to. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC Return: int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. h](j)}(h``release_rmu``h]j)}(hjh]h release_rmu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h8For a given MPCC, release the RMU unit it muliplexes to.h]h8For a given MPCC, release the RMU unit it muliplexes to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h>Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCCh]h>Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h_int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release.h]h_int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``get_mpc_out_mux`` Return MPC out mux. Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP Return: unsigned int - Out Mux h](j)}(h``get_mpc_out_mux``h]j)}(hjh]hget_mpc_out_mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hReturn MPC out mux.h]hReturn MPC out mux.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h9Parameters: - [in] mpc - MPC context. - [in] opp_id - OPPh]h9Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hunsigned int - Out Muxh]hunsigned int - Out Mux}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``set_bg_color`` Find corresponding bottommost MPCC and set its bg color. Parameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id Return: void h](j)}(h``set_bg_color``h]j)}(hjch]h set_bg_color}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj]ubj)}(hhh](h)}(h8Find corresponding bottommost MPCC and set its bg color.h]h8Find corresponding bottommost MPCC and set its bg color.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjyubh)}(hfParameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_idh]hfParameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjyubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjyubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhMhjyubeh}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jzhjxhMhjubj{)}(hg``set_mpc_mem_lp_mode`` Set mpc_mem_lp_mode. Parameters: - [in/out] mpc - MPC context. Return: void h](j)}(h``set_mpc_mem_lp_mode``h]j)}(hjh]hset_mpc_mem_lp_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hSet mpc_mem_lp_mode.h]hSet mpc_mem_lp_mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h)Parameters: - [in/out] mpc - MPC context.h]h)Parameters: - [in/out] mpc - MPC context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``set_movable_cm_location`` Set Movable CM Location. Parameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id Return: void h](j)}(h``set_movable_cm_location``h]j)}(hj/h]hset_movable_cm_location}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj)ubj)}(hhh](h)}(hSet Movable CM Location.h]hSet Movable CM Location.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjEubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_idh]hHParameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjEubh)}(hReturn:h]hReturn:}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjEubh)}(hvoidh]hvoid}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhMhjEubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jzhjDhMhjubj{)}(h``update_3dlut_fast_load_select`` Update 3D LUT fast load select. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx Return: void h](j)}(h!``update_3dlut_fast_load_select``h]j)}(hjh]hupdate_3dlut_fast_load_select}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hUpdate 3D LUT fast load select.h]hUpdate 3D LUT fast load select.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idxh]hHParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(hX``get_3dlut_fast_load_status`` Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow Return: void h](j)}(h``get_3dlut_fast_load_status``h]j)}(hjh]hget_3dlut_fast_load_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(heGet 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.h]heGet 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h|Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflowh]h|Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMhjubj{)}(h``populate_lut`` Populate LUT with given tetrahedral parameters. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id Return: void h](j)}(h``populate_lut``h]j)}(hjah]h populate_lut}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hj[ubj)}(hhh](h)}(h/Populate LUT with given tetrahedral parameters.h]h/Populate LUT with given tetrahedral parameters.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM"hjwubh)}(hbParameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_idh]hbParameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM$hjwubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM+hjwubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhM-hjwubeh}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jzhjvhM-hjubj{)}(h``program_lut_read_write_control`` Program LUT RW control. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] bit_depth - [in] mpcc_id Return: void h](j)}(h"``program_lut_read_write_control``h]j)}(hjh]hprogram_lut_read_write_control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMChjubj)}(hhh](h)}(hProgram LUT RW control.h]hProgram LUT RW control.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM8hjubh)}(heParameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] bit_depth - [in] mpcc_idh]heParameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] bit_depth - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM:hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMAhjubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMChjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMChjubj{)}(h``program_lut_mode`` Program LUT mode. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] enable - [in] lut_bank_a - [in] size - [in] mpcc_id Return: void h](j)}(h``program_lut_mode``h]j)}(hj-h]hprogram_lut_mode}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMZhj'ubj)}(hhh](h)}(hProgram LUT mode.h]hProgram LUT mode.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMNhjCubh)}(hnParameters: - [in/out] mpc - MPC context. - [in] id - [in] enable - [in] lut_bank_a - [in] size - [in] mpcc_idh]hnParameters: - [in/out] mpc - MPC context. - [in] id - [in] enable - [in] lut_bank_a - [in] size - [in] mpcc_id}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMPhjCubh)}(hReturn:h]hReturn:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMXhjCubh)}(hvoidh]hvoid}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhMZhjCubeh}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jzhjBhMZhjubj{)}(h``get_lut_mode`` Obtains enablement and ram bank status. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] mpcc_id - [out] enable - [out] lut_bank_a Return: void h](j)}(h``get_lut_mode``h]j)}(hjh]h get_lut_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMrhjubj)}(hhh](h)}(h'Obtains enablement and ram bank status.h]h'Obtains enablement and ram bank status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMghjubh)}(hdParameters: - [in/out] mpc - MPC context. - [in] id - [in] mpcc_id - [out] enable - [out] lut_bank_ah]hdParameters: - [in/out] mpc - MPC context. - [in] id - [in] mpcc_id - [out] enable - [out] lut_bank_a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMihjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMphjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMrhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhMrhjubj{)}(h9``rmcm`` MPC RMCM new HW sequential programming functionsh](j)}(h``rmcm``h]j)}(hjh]hrmcm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM|hjubj)}(hhh]h)}(h0MPC RMCM new HW sequential programming functionsh]h0MPC RMCM new HW sequential programming functions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jzhjhM|hjubeh}(h]h ]h"]h$]h&]uh1juhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj|hhhNhNubeh}(h]mpcah ]h"]mpcah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hOPPh]hOPP}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhK*ubh)}(hThe Output Plane Processor (OPP) block groups have functions that format pixel streams such that they are suitable for display at the display device. The key functions contained in the OPP are:h]hThe Output Plane Processor (OPP) block groups have functions that format pixel streams such that they are suitable for display at the display device. The key functions contained in the OPP are:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjBhhubj)}(hhh](j)}(h#Adaptive Backlight Modulation (ABM)h]h)}(hjgh]h#Adaptive Backlight Modulation (ABM)}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjeubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.h]h)}(h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.h]h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK hj}ubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(h>Output Buffer that provide pixel replication, and overlapping.h]h)}(hjh]h>Output Buffer that provide pixel replication, and overlapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK"hjubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hInterface between MPC and OPTC.h]h)}(hjh]hInterface between MPC and OPTC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK#hjubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hClock and reset generation.h]h)}(hjh]hClock and reset generation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK$hjubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hCRC generation. h]h)}(hCRC generation.h]hCRC generation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK%hjubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]j{j|uh1jhjvhKhjBhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jpwl_float_data (C struct)c.pwl_float_datahNtauh1jhjBhhhNhNubj)}(hhh](j)}(hpwl_float_datah]j)}(hstruct pwl_float_datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKubj)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj#hKubj)}(hpwl_float_datah]j)}(hjh]hpwl_float_data}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj#hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj#hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj#hKhj hhubj)}(hhh]h)}(hFixed point RGB colorh]hFixed point RGB color}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjUhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj#hKubeh}(h]h ](jstructeh"]h$]h&]j!jj"jpj#jpj$j%j&uh1jhhhjBhNhNubj()}(h**Definition**:: struct pwl_float_data { struct fixed31_32 r; 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](jfunctioneh"]h$]h&]j!jj"jK!j#jK!j$j%j&uh1jhhhjhNhNubj()}(hX&**Parameters** ``const struct dc_link *link`` Reference a link struct containing one or more sinks and the connective status. ``const struct link_resource *link_res`` Mappable hardware resource used to enable a link. **Return** Return true if the link encoder is accessible from link.h](h)}(h**Parameters**h]j2)}(hjU!h]h Parameters}(hjW!hhhNhNubah}(h]h ]h"]h$]h&]uh1j1hjS!ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMGhjO!ubjv)}(hhh](j{)}(ho``const struct dc_link *link`` Reference a link struct containing one or more sinks and the connective status. h](j)}(h``const struct dc_link *link``h]j)}(hjt!h]hconst struct dc_link *link}(hjv!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr!ubah}(h]h ]h"]h$]h&]uh1jh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: 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link.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMGhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jzhj!hMGhjk!ubeh}(h]h ]h"]h$]h&]uh1juhjO!ubh)}(h **Return**h]j2)}(hj!h]hReturn}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j1hj!ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMIhjO!ubh)}(h8Return true if the link encoder is accessible from link.h]h8Return true if the link encoder is accessible from link.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMIhjO!ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jget_dio_link_hwss (C function)c.get_dio_link_hwsshNtauh1jhjhhhNhNubj)}(hhh](j)}(h1const struct link_hwss * get_dio_link_hwss (void)h]j)}(h/const struct link_hwss *get_dio_link_hwss(void)h](j)}(hjh]hconst}(hj."hhhNhNubah}(h]h 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