sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget1/translations/zh_CN/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/zh_TW/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/it_IT/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ja_JP/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ko_KR/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/sp_SP/gpu/amdgpu/display/dcn-blocksmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhtarget)}(h.. _dcn_blocks:h]h}(h]h ]h"]h$]h&]refid dcn-blocksuh1hhKhhhhhK/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks.rstubhsection)}(hhh](htitle)}(h DCN Blocksh]h DCN Blocks}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hIn this section, you will find some extra details about some of the DCN blocks and the code documentation when it is automatically generated.h]hIn this section, you will find some extra details about some of the DCN blocks and the code documentation when it is automatically generated.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hDCHUBBUBh]hDCHUBBUB}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hThere is only one common DCHUBBUB. It contains the common request and return blocks for the Data Fabric Interface that are not clock/power gated.h]hThere is only one common DCHUBBUB. It contains the common request and return blocks for the Data Fabric Interface that are not clock/power gated.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hh~/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:13: ./drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.hhKhhhhubeh}(h]dchubbubah ]h"]dchubbubah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hHUBPh]hHUBP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hDisplay Controller Hub (DCHUB) is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.h]hDisplay Controller Hub (DCHUB) is the gateway between the Scalable Data Port (SDP) and DCN. This component has multiple features, such as memory arbitration, rotation, and cursor manipulation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhz/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:19: ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.hhKhhhhubh)}(hThere is one HUBP allocated per pipe, which fetches data and converts different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved and fixed-depth streams of pixel data.h]hThere is one HUBP allocated per pipe, which fetches data and converts different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved and fixed-depth streams of pixel data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhz/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:19: ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.hhK"hhhhubeh}(h]hubpah ]h"]hubpah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDPPh]hDPP}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhKubh)}(hX/The DPP (Display Pipe and Plane) block is the unified display data processing engine in DCN for processing graphic or video data on per DPP rectangle base. This rectangle can be a part of SLS (Single Large Surface), or a layer to be blended with other DPP, or a rectangle associated with a display tile.h]hX/The DPP (Display Pipe and Plane) block is the unified display data processing engine in DCN for processing graphic or video data on per DPP rectangle base. This rectangle can be a part of SLS (Single Large Surface), or a layer to be blended with other DPP, or a rectangle associated with a display tile.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj4hhubh)}(hXIIt provides various functions including: - graphic color keyer - graphic cursor compositing - graphic or video image source to destination scaling - image sharping - video format conversion from 4:2:0 or 4:2:2 to 4:4:4 - Color Space Conversion - Host LUT gamma adjustment - Color Gamut Remap - brightness and contrast adjustment.h]hXIIt provides various functions including: - graphic color keyer - graphic cursor compositing - graphic or video image source to destination scaling - image sharping - video format conversion from 4:2:0 or 4:2:2 to 4:4:4 - Color Space Conversion - Host LUT gamma adjustment - Color Gamut Remap - brightness and contrast adjustment.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhK%hj4hhubh)}(hDPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module connected in a video/graphics pipeline.h]hDPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module connected in a video/graphics pipeline.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:25: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhK0hj4hhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlecnv_alpha_2bit_lut (C struct)c.cnv_alpha_2bit_luthNtauh1jrhj4hhhNhNubhdesc)}(hhh](hdesc_signature)}(hcnv_alpha_2bit_luth]hdesc_signature_line)}(hstruct cnv_alpha_2bit_luth](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hcnv_alpha_2bit_luth]h desc_sig_name)}(hjh]hcnv_alpha_2bit_lut}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(h2Set the 8bit alpha values based on the 2 bit alphah]h2Set the 8bit alpha values based on the 2 bit alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypej desctypej noindex noindexentrynocontentsentryuh1jhhhj4hNhNubh container)}(hX**Definition**:: struct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; }; **Members** ``lut0`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000 ``lut1`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101 ``lut2`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010 ``lut3`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubh literal_block)}(hVstruct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; };h]hVstruct cnv_alpha_2bit_lut { int lut0; int lut1; int lut2; int lut3; };}hj:sbah}(h]h ]h"]h$]h&]jjuh1j8hy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubh)}(h **Members**h]j)}(hjKh]hMembers}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubhdefinition_list)}(hhh](hdefinition_list_item)}(h>``lut0`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000 h](hterm)}(h``lut0``h]hliteral)}(hjph]hlut0}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjnubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjhubh definition)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jfhjhKhjcubjg)}(h>``lut1`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101 h](jm)}(h``lut1``h]js)}(hjh]hlut1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhKhjcubjg)}(h>``lut2`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010 h](jm)}(h``lut2``h]js)}(hjh]hlut2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhKhjcubjg)}(h=``lut3`` ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h](jm)}(h``lut3``h]js)}(hjh]hlut3}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhjubj)}(hhh]h)}(h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111h]h4ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:28: ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.hhKhj5ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj4hKhjcubeh}(h]h ]h"]h$]h&]uh1jahjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj4hhhNhNubeh}(h]dppah ]h"]dppah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMPCh]hMPC}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhK ubh)}(hX7Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline that performs blending of multiple planes, using global and per-pixel alpha. It also performs post-blending color correction operations according to the hardware capabilities, such as color transformation matrix and gamma 1D and 3D LUT.h]hX7Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline that performs blending of multiple planes, using global and per-pixel alpha. It also performs post-blending color correction operations according to the hardware capabilities, such as color transformation matrix and gamma 1D and 3D LUT.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjhhhubh)}(hMPC receives output from all DPP pipes and combines them to multiple outputs supporting "M MPC inputs -> N MPC outputs" flexible composition architecture. It features:h]hMPC receives output from all DPP pipes and combines them to multiple outputs supporting “M MPC inputs -> N MPC outputs” flexible composition architecture. It features:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK!hjhhhubh bullet_list)}(hhh](h list_item)}(hTProgrammable blending structure to allow software controlled blending and cascading;h]h)}(hTProgrammable blending structure to allow software controlled blending and cascading;h]hTProgrammable blending structure to allow software controlled blending and cascading;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hEProgrammable window location of each DPP in active region of display;h]h)}(hjh]hEProgrammable window location of each DPP in active region of display;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;h]h)}(hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;h]hkCombining multiple DPP pipes in one active region when a single DPP pipe cannot process very large surface;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h8Combining multiple DPP from different SLS with blending;h]h)}(hjh]h8Combining multiple DPP from different SLS with blending;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hCStereo formats from single DPP in top-bottom or side-by-side modes;h]h)}(hjh]hCStereo formats from single DPP in top-bottom or side-by-side modes;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK+hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hStereo formats from 2 DPPs;h]h)}(hjh]hStereo formats from 2 DPPs;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h;Alpha blending of multiple layers from different DPP pipes;h]h)}(hj2h]h;Alpha blending of multiple layers from different DPP pipes;}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK-hj0ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hProgrammable background color; h]h)}(hProgrammable background color;h]hProgrammable background color;}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:34: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhK.hjHubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhK%hjhhhubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpcc (C struct)c.mpcchNtauh1jrhjhhhhNhNubj)}(hhh](j)}(hmpcch]j)}(h struct mpcch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhjhKubj)}(hmpcch]j)}(hj|h]hmpcc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj~hhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjzhhhjhKubah}(h]juah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjwhhubj)}(hhh]h)}(hFMPCC connection and blending configuration for a single MPCC instance.h]hFMPCC connection and blending configuration for a single MPCC instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j jjjjjjjjuh1jhhhjhhNhNubj)}(hX,**Definition**:: struct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; }; **Members** ``mpcc_id`` MPCC physical instance. ``dpp_id`` DPP input to this MPCC ``mpcc_bot`` Pointer to bottom layer MPCC. NULL when not connected. ``blnd_cfg`` The blending configuration for this MPCC. ``sm_cfg`` stereo mix setting for this MPCC ``shared_bottom`` If MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubj9)}(hstruct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; };h]hstruct mpcc { int mpcc_id; int dpp_id; struct mpcc *mpcc_bot; struct mpcc_blnd_cfg blnd_cfg; struct mpcc_sm_cfg sm_cfg; bool shared_bottom; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j8hy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubjb)}(hhh](jg)}(h$``mpcc_id`` MPCC physical instance. h](jm)}(h ``mpcc_id``h]js)}(hj1h]hmpcc_id}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj/ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhj+ubj)}(hhh]h)}(hMPCC physical instance.h]hMPCC physical instance.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jfhjFhKhj(ubjg)}(h"``dpp_id`` DPP input to this MPCC h](jm)}(h ``dpp_id``h]js)}(hjjh]hdpp_id}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjhubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjdubj)}(hhh]h)}(hDPP input to this MPCCh]hDPP input to this MPCC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jfhjhKhj(ubjg)}(hD``mpcc_bot`` Pointer to bottom layer MPCC. NULL when not connected. h](jm)}(h ``mpcc_bot``h]js)}(hjh]hmpcc_bot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubj)}(hhh]h)}(h6Pointer to bottom layer MPCC. NULL when not connected.h]h6Pointer to bottom layer MPCC. NULL when not connected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhKhj(ubjg)}(h7``blnd_cfg`` The blending configuration for this MPCC. h](jm)}(h ``blnd_cfg``h]js)}(hjh]hblnd_cfg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubj)}(hhh]h)}(h)The blending configuration for this MPCC.h]h)The blending configuration for this MPCC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhKhj(ubjg)}(h,``sm_cfg`` stereo mix setting for this MPCC h](jm)}(h ``sm_cfg``h]js)}(hjh]hsm_cfg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjubj)}(hhh]h)}(h stereo mix setting for this MPCCh]h stereo mix setting for this MPCC}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj*hKhj(ubjg)}(hW``shared_bottom`` If MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h](jm)}(h``shared_bottom``h]js)}(hjNh]h shared_bottom}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjLubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjHubj)}(hhh]h)}(hEIf MPCC output to both OPP and DWB endpoints, true. Otherwise, false.h]hEIf MPCC output to both OPP and DWB endpoints, true. Otherwise, false.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jfhjchKhj(ubeh}(h]h ]h"]h$]h&]uh1jahjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjhhhubh)}(h-This struct is used as a node in an MPC tree.h]h-This struct is used as a node in an MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKhjhhhubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_tree (C struct) c.mpc_treehNtauh1jrhjhhhhNhNubj)}(hhh](j)}(hmpc_treeh]j)}(hstruct mpc_treeh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hmpc_treeh]j)}(hjh]hmpc_tree}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h4MPC tree represents all MPCC connections for a pipe.h]h4MPC tree represents all MPCC connections for a pipe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j jjj)jj)jjjuh1jhhhjhhNhNubj)}(h**Definition**:: struct mpc_tree { int opp_id; struct mpcc *opp_list; }; **Members** ``opp_id`` The OPP instance that owns this MPC tree. ``opp_list`` the top MPCC layer of the MPC tree that outputs to OPP endpointh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh:}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hj-ubj9)}(h?struct mpc_tree { int opp_id; struct mpcc *opp_list; };h]h?struct mpc_tree { int opp_id; struct mpcc *opp_list; };}hjNsbah}(h]h ]h"]h$]h&]jjuh1j8hy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hj-ubh)}(h **Members**h]j)}(hj_h]hMembers}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj-ubjb)}(hhh](jg)}(h5``opp_id`` The OPP instance that owns this MPC tree. h](jm)}(h ``opp_id``h]js)}(hj~h]hopp_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj|ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjxubj)}(hhh]h)}(h)The OPP instance that owns this MPC tree.h]h)The OPP instance that owns this MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jfhjhM hjuubjg)}(hL``opp_list`` the top MPCC layer of the MPC tree that outputs to OPP endpointh](jm)}(h ``opp_list``h]js)}(hjh]hopp_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(h?the top MPCC layer of the MPC tree that outputs to OPP endpointh]h?the top MPCC layer of the MPC tree that outputs to OPP endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjuubeh}(h]h ]h"]h$]h&]uh1jahj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhhNhNubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjhhhubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](jmpc_funcs (C struct) c.mpc_funcshNtauh1jrhjhhhhNhNubj)}(hhh](j)}(h mpc_funcsh]j)}(hstruct mpc_funcsh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%hhhj6hM ubj)}(h mpc_funcsh]j)}(hj#h]h mpc_funcs}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]jjuh1jhj%hhhj6hM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj!hhhj6hM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj6hM hjhhubj)}(hhh]h)}(hfuncsh]hfuncs}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM3hjhhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj6hM ubeh}(h]h ](jstructeh"]h$]h&]j jjjjjjjjuh1jhhhjhhNhNubj)}(hX 8**Definition**:: struct mpc_funcs { void (*read_mpcc_state)(struct mpc *mpc,int mpcc_inst, struct mpcc_state *s); struct mpcc* (*insert_plane)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)(struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)(struct mpc *mpc,struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)(struct mpc *mpc,int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)(struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)(struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)(struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc,int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)(struct mpc *mpc,int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc,int opp_id,const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc,int opp_id,enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)(struct mpc *mpc,int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)(struct mpc *mpc,int mpcc_id, bool power_on); void (*set_dwb_mux)(struct mpc *mpc,int dwb_id, int mpcc_id); void (*disable_dwb_mux)(struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)(struct mpc *mpc, int dwb_id); void (*set_out_rate_control)(struct mpc *mpc,int opp_id,bool enable,bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)(struct mpc *mpc,int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)(struct mpc *mpc,const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)(struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc,struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int mpcc_id); }; **Members** ``read_mpcc_state`` Read register content from given MPCC physical instance. Parameters: - [in/out] mpc - MPC context - [in] mpcc_instance - MPC context instance - [in] mpcc_state - MPC context state Return: void ``insert_plane`` Insert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. ``remove_mpcc`` Remove a specified MPCC from the MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in/out] mpcc - MPCC to be removed from tree. Return: void ``mpc_init`` Reset the MPCC HW status by disconnecting all muxes. Parameters: - [in/out] mpc - MPC context. Return: void ``mpc_init_single_inst`` Initialize given MPCC physical instance. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized. ``update_blending`` Update the blending configuration for a specified MPCC. Parameters: - [in/out] mpc - MPC context. - [in] blnd_cfg - MPCC blending configuration. - [in] mpcc_id - The MPCC physical instance. Return: void ``cursor_lock`` Lock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor. Parameters: - [in] mpc - MPC context. - [in] opp_id - The OPP to lock cursor updates on - [in] lock - lock/unlock the OPP Return: void ``insert_plane_to_secondary`` Add DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. ``remove_mpcc_from_secondary`` Remove a specified DPP from the 'secondary' MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in] mpcc - MPCC to be removed from tree. Return: void ``get_mpcc_for_dpp_from_secondary`` Find, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. ``get_mpcc_for_dpp`` Find, if it exists, a MPCC from a given MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. ``wait_for_idle`` Wait for a MPCC in MPC context to enter idle state. Parameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state. Return: void ``assert_mpcc_idle_before_connect`` Assert if MPCC in MPC context is in idle state. Parameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state. Return: void ``init_mpcc_list_from_hw`` Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values. Parameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. Return: void ``set_denorm`` Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode. Return: void ``set_denorm_clamp`` Set denorm clamp values on corresponding OPP DENORM CONTROL register. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set. Return: void ``set_output_csc`` Set the Output Color Space Conversion matrix with given values and mode. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC. Return: void ``set_ocsc_default`` Set the Output Color Space Conversion matrix to default values according to color space. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC. Return: void ``set_output_gamma`` Set Output Gamma with given curve parameters. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters. Return: void ``power_on_mpc_mem_pwr`` Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on Return: void ``set_dwb_mux`` Set corresponding Display Writeback mux MPC register field to given MPCC id. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register. Return: void ``disable_dwb_mux`` Reset corresponding Display Writeback mux MPC register field. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. Return: void ``is_dwb_idle`` Check DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked. Return: bool - wheter DWB is idle or not ``set_out_rate_control`` Set display output rate control. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control Return: void ``set_gamut_remap`` Set post-blending CTM for given MPCC. Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust Return: void ``program_1dlut`` Set 1 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). ``program_shaper`` Set shaper. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx Return: bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). ``acquire_rmu`` Set given MPCC to be multiplexed to given RMU unit. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. Return: unit32_t - rmu_idx if operation was successful, -1 else. ``program_3dlut`` Set 3 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). ``release_rmu`` For a given MPCC, release the RMU unit it muliplexes to. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC Return: int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. ``get_mpc_out_mux`` Return MPC out mux. Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP Return: unsigned int - Out Mux ``set_bg_color`` Find corresponding bottommost MPCC and set its bg color. Parameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id Return: void ``set_mpc_mem_lp_mode`` Set mpc_mem_lp_mode. Parameters: - [in/out] mpc - MPC context. Return: void ``set_movable_cm_location`` Set Movable CM Location. Parameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id Return: void ``update_3dlut_fast_load_select`` Update 3D LUT fast load select. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx Return: void ``get_3dlut_fast_load_status`` Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow Return: void ``populate_lut`` Populate LUT with given tetrahedral parameters. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id Return: void ``program_lut_read_write_control`` Program LUT RW control. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] mpcc_id Return: void ``program_lut_mode`` Program LUT mode. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] xable - [in] lut_bank_a - [in] mpcc_id Return: void ``program_3dlut_size`` Program 3D LUT size. Parameters: - [in/out] mpc - MPC context. - [in] is_17x17x17 - is 3dlut 17x17x17 - [in] mpcc_id Return: voidh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM7hjubj9)}(hXstruct mpc_funcs { void (*read_mpcc_state)(struct mpc *mpc,int mpcc_inst, struct mpcc_state *s); struct mpcc* (*insert_plane)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)(struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)(struct mpc *mpc,struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)(struct mpc *mpc,int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)(struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)(struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)(struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc,int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)(struct mpc *mpc,int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc,int opp_id,const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc,int opp_id,enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)(struct mpc *mpc,int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)(struct mpc *mpc,int mpcc_id, bool power_on); void (*set_dwb_mux)(struct mpc *mpc,int dwb_id, int mpcc_id); void (*disable_dwb_mux)(struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)(struct mpc *mpc, int dwb_id); void (*set_out_rate_control)(struct mpc *mpc,int opp_id,bool enable,bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)(struct mpc *mpc,int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)(struct mpc *mpc,const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)(struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc,struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int mpcc_id); };h]hXstruct mpc_funcs { void (*read_mpcc_state)(struct mpc *mpc,int mpcc_inst, struct mpcc_state *s); struct mpcc* (*insert_plane)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); void (*mpc_init)(struct mpc *mpc); void (*mpc_init_single_inst)(struct mpc *mpc, unsigned int mpcc_id); void (*update_blending)(struct mpc *mpc,struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); void (*cursor_lock)(struct mpc *mpc,int opp_id, bool lock); struct mpcc* (*insert_plane_to_secondary)(struct mpc *mpc,struct mpc_tree *tree,struct mpcc_blnd_cfg *blnd_cfg,struct mpcc_sm_cfg *sm_cfg,struct mpcc *insert_above_mpcc,int dpp_id, int mpcc_id); void (*remove_mpcc_from_secondary)(struct mpc *mpc,struct mpc_tree *tree, struct mpcc *mpcc); struct mpcc* (*get_mpcc_for_dpp_from_secondary)(struct mpc_tree *tree, int dpp_id); struct mpcc* (*get_mpcc_for_dpp)(struct mpc_tree *tree, int dpp_id); void (*wait_for_idle)(struct mpc *mpc, int id); void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); void (*init_mpcc_list_from_hw)(struct mpc *mpc, struct mpc_tree *tree); void (*set_denorm)(struct mpc *mpc,int opp_id, enum dc_color_depth output_depth); void (*set_denorm_clamp)(struct mpc *mpc,int opp_id, struct mpc_denorm_clamp denorm_clamp); void (*set_output_csc)(struct mpc *mpc,int opp_id,const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); void (*set_ocsc_default)(struct mpc *mpc,int opp_id,enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); void (*set_output_gamma)(struct mpc *mpc,int mpcc_id, const struct pwl_params *params); void (*power_on_mpc_mem_pwr)(struct mpc *mpc,int mpcc_id, bool power_on); void (*set_dwb_mux)(struct mpc *mpc,int dwb_id, int mpcc_id); void (*disable_dwb_mux)(struct mpc *mpc, int dwb_id); bool (*is_dwb_idle)(struct mpc *mpc, int dwb_id); void (*set_out_rate_control)(struct mpc *mpc,int opp_id,bool enable,bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); void (*set_gamut_remap)(struct mpc *mpc,int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); bool (*program_1dlut)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); bool (*program_shaper)(struct mpc *mpc,const struct pwl_params *params, uint32_t rmu_idx); uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); bool (*program_3dlut)(struct mpc *mpc,const struct tetrahedral_params *params, int rmu_idx); int (*release_rmu)(struct mpc *mpc, int mpcc_id); unsigned int (*get_mpc_out_mux)(struct mpc *mpc, int opp_id); void (*set_bg_color)(struct mpc *mpc,struct tg_color *bg_color, int mpcc_id); void (*set_mpc_mem_lp_mode)(struct mpc *mpc); void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int mpcc_id); };}hjsbah}(h]h ]h"]h$]h&]jjuh1j8hy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM9hjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMdhjubjb)}(hhh](jg)}(h``read_mpcc_state`` Read register content from given MPCC physical instance. Parameters: - [in/out] mpc - MPC context - [in] mpcc_instance - MPC context instance - [in] mpcc_state - MPC context state Return: void h](jm)}(h``read_mpcc_state``h]js)}(hjh]hread_mpcc_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMBhjubj)}(hhh](h)}(h8Read register content from given MPCC physical instance.h]h8Read register content from given MPCC physical instance.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM8hjubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM:hjubj)}(hhh](j)}(h[in/out] mpc - MPC contexth]h)}(hj h]h[in/out] mpc - MPC context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM<hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h)[in] mpcc_instance - MPC context instanceh]h)}(hj, h]h)[in] mpcc_instance - MPC context instance}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM=hj* ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h$[in] mpcc_state - MPC context state h]h)}(h#[in] mpcc_state - MPC context stateh]h#[in] mpcc_state - MPC context state}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM>hjB ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]jgjhuh1jhj# hM<hjubh)}(hReturn:h]hReturn:}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM@hjubh)}(hvoidh]hvoid}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMBhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMBhjubjg)}(hX``insert_plane`` Insert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. h](jm)}(h``insert_plane``h]js)}(hj h]h insert_plane}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM]hj ubj)}(hhh](h)}(hInsert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP outputh]hInsert DPP into MPC tree based on specified blending position. Only used for planes that are part of blending chain for OPP output}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMLhj ubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMOhj ubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hj h]h[in/out] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMQhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h?[in/out] tree - MPC tree structure that plane will be added to.h]h)}(hj h]h?[in/out] tree - MPC tree structure that plane will be added to.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMRhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.h]h)}(hj h]hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMShj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h]jb)}(hhh]jg)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h](jm)}(hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.h]hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMThj ubj)}(hhh]h)}(hEstereo mix must disable for the very bottom layer of the tree config.h]hEstereo mix must disable for the very bottom layer of the tree config.}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMUhj, ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj+ hMThj ubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hr[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h]jb)}(hhh]jg)}(h[[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h](jm)}(h:[in] insert_above_mpcc - Insert new plane above this MPCC.h]h:[in] insert_above_mpcc - Insert new plane above this MPCC.}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMVhj] ubj)}(hhh]h)}(h If NULL, insert as bottom plane.h]h If NULL, insert as bottom plane.}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMWhjp ubah}(h]h ]h"]h$]h&]uh1jhj] ubeh}(h]h ]h"]h$]h&]uh1jfhjo hMVhjZ ubah}(h]h ]h"]h$]h&]uh1jahjV ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h6[in] dpp_id - DPP instance for the plane to be added.h]h)}(hj h]h6[in] dpp_id - DPP instance for the plane to be added.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMXhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h?[in] mpcc_id - The MPCC physical instance to use for blending. h]h)}(h>[in] mpcc_id - The MPCC physical instance to use for blending.h]h>[in] mpcc_id - The MPCC physical instance to use for blending.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMYhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]jgjhuh1jhj hMQhj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM[hj ubh)}(h#struct mpcc* - MPCC that was added.h]h#struct mpcc* - MPCC that was added.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hM]hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hM]hjubjg)}(h``remove_mpcc`` Remove a specified MPCC from the MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in/out] mpcc - MPCC to be removed from tree. Return: void h](jm)}(h``remove_mpcc``h]js)}(hj h]h remove_mpcc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMuhj ubj)}(hhh](h)}(h*Remove a specified MPCC from the MPC tree.h]h*Remove a specified MPCC from the MPC tree.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMkhj ubh)}(h Parameters:h]h Parameters:}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMmhj ubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hj< h]h[in/out] mpc - MPC context.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMohj: ubah}(h]h ]h"]h$]h&]uh1jhj7 ubj)}(hD[in/out] tree - MPC tree structure that plane will be removed from.h]h)}(hjT h]hD[in/out] tree - MPC tree structure that plane will be removed from.}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMphjR ubah}(h]h ]h"]h$]h&]uh1jhj7 ubj)}(h/[in/out] mpcc - MPCC to be removed from tree. h]h)}(h.[in/out] mpcc - MPCC to be removed from tree.h]h.[in/out] mpcc - MPCC to be removed from tree.}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMqhjj ubah}(h]h ]h"]h$]h&]uh1jhj7 ubeh}(h]h ]h"]h$]h&]jgjhuh1jhjK hMohj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMshj ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMuhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hMuhjubjg)}(h}``mpc_init`` Reset the MPCC HW status by disconnecting all muxes. Parameters: - [in/out] mpc - MPC context. Return: void h](jm)}(h ``mpc_init``h]js)}(hj h]hmpc_init}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h4Reset the MPCC HW status by disconnecting all muxes.h]h4Reset the MPCC HW status by disconnecting all muxes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh]j)}(h[in/out] mpc - MPC context. h]h)}(hn/out] mpc - MPC context.h]hn/out] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]jgjhuh1jhj hMhj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hMhjubjg)}(h``mpc_init_single_inst`` Initialize given MPCC physical instance. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized. h](jm)}(h``mpc_init_single_inst``h]js)}(hj@ h]hmpc_init_single_inst}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj> ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj: ubj)}(hhh](h)}(h(Initialize given MPCC physical instance.h]h(Initialize given MPCC physical instance.}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjV ubh)}(hhParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized.h]hhParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - The MPCC physical instance to be initialized.}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjV ubeh}(h]h ]h"]h$]h&]uh1jhj: ubeh}(h]h ]h"]h$]h&]uh1jfhjU hMhjubjg)}(h``update_blending`` Update the blending configuration for a specified MPCC. Parameters: - [in/out] mpc - MPC context. - [in] blnd_cfg - MPCC blending configuration. - [in] mpcc_id - The MPCC physical instance. Return: void h](jm)}(h``update_blending``h]js)}(hj h]hupdate_blending}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(h7Update the blending configuration for a specified MPCC.h]h7Update the blending configuration for a specified MPCC.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(h Parameters:h]h Parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](j)}(hn/out] mpc - MPC context.h]h)}(hj h]hn/out] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h,[in] blnd_cfg - MPCC blending configuration.h]h)}(hj h]h,[in] blnd_cfg - MPCC blending configuration.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(h,[in] mpcc_id - The MPCC physical instance. h]h)}(h+[in] mpcc_id - The MPCC physical instance.h]h+[in] mpcc_id - The MPCC physical instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]jgjhuh1jhj hMhj ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hMhjubjg)}(hX``cursor_lock`` Lock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor. Parameters: - [in] mpc - MPC context. - [in] opp_id - The OPP to lock cursor updates on - [in] lock - lock/unlock the OPP Return: void h](jm)}(h``cursor_lock``h]js)}(hjA h]h cursor_lock}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj? ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj; ubj)}(hhh](h)}(hkLock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor.h]hkLock cursor updates for the specified OPP. OPP defines the set of MPCC that are locked together for cursor.}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjW ubh)}(h Parameters:h]h Parameters:}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjW ubj)}(hhh](j)}(h[in] mpc - MPC context.h]h)}(hj} h]h[in] mpc - MPC context.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj{ ubah}(h]h ]h"]h$]h&]uh1jhjx ubj)}(h0[in] opp_id - The OPP to lock cursor updates onh]h)}(hj h]h0[in] opp_id - The OPP to lock cursor updates on}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhjx ubj)}(h [in] lock - lock/unlock the OPP h]h)}(h[in] lock - lock/unlock the OPPh]h[in] lock - lock/unlock the OPP}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubah}(h]h ]h"]h$]h&]uh1jhjx ubeh}(h]h ]h"]h$]h&]jgjhuh1jhj hMhjW ubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjW ubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hMhjW ubeh}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jfhjV hMhjubjg)}(hX ``insert_plane_to_secondary`` Add DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be added to. - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config. - [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane. - [in] dpp_id - DPP instance for the plane to be added. - [in] mpcc_id - The MPCC physical instance to use for blending. Return: struct mpcc* - MPCC that was added. h](jm)}(h``insert_plane_to_secondary``h]js)}(hj h]hinsert_plane_to_secondary}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubj)}(hhh](h)}(hAdd DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB outputh]hAdd DPP into secondary MPC tree based on specified blending position. Only used for planes that are part of blending chain for DWB output}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h Parameters:h]h Parameters:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hj5h]h[in/out] mpc - MPC context.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj3ubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(h?[in/out] tree - MPC tree structure that plane will be added to.h]h)}(hjMh]h?[in/out] tree - MPC tree structure that plane will be added to.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjKubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.h]h)}(hjeh]hG[in] blnd_cfg - MPCC blending configuration for the new blending layer.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjcubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h]jb)}(hhh]jg)}(h[in] sm_cfg - MPCC stereo mix configuration for the new blending layer. stereo mix must disable for the very bottom layer of the tree config.h](jm)}(hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.h]hI[in] sm_cfg - MPCC stereo mix configuration for the new blending layer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(hEstereo mix must disable for the very bottom layer of the tree config.h]hEstereo mix must disable for the very bottom layer of the tree config.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubah}(h]h ]h"]h$]h&]uh1jahj{ubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(hc[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h]jb)}(hhh]jg)}(h\[in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.h](jm)}(h>[in] insert_above_mpcc - Insert new plane above this MPCC. Ifh]h>[in] insert_above_mpcc - Insert new plane above this MPCC. If}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh]h)}(hNULL, insert as bottom plane.h]hNULL, insert as bottom plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubah}(h]h ]h"]h$]h&]uh1jahjubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(h5[in] dpp_id - DPP instance for the plane to be added.h]h)}(hjh]h5[in] dpp_id - DPP instance for the plane to be added.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhj0ubj)}(h?[in] mpcc_id - The MPCC physical instance to use for blending. h]h)}(h>[in] mpcc_id - The MPCC physical instance to use for blending.h]h>[in] mpcc_id - The MPCC physical instance to use for blending.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]jgjhuh1jhjDhMhjubh)}(hReturn:h]hReturn:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h#struct mpcc* - MPCC that was added.h]h#struct mpcc* - MPCC that was added.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(hX``remove_mpcc_from_secondary`` Remove a specified DPP from the 'secondary' MPC tree. Parameters: - [in/out] mpc - MPC context. - [in/out] tree - MPC tree structure that plane will be removed from. - [in] mpcc - MPCC to be removed from tree. Return: void h](jm)}(h``remove_mpcc_from_secondary``h]js)}(hjih]hremove_mpcc_from_secondary}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjgubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjcubj)}(hhh](h)}(h5Remove a specified DPP from the 'secondary' MPC tree.h]h9Remove a specified DPP from the ‘secondary’ MPC tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h Parameters:h]h Parameters:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](j)}(h[in/out] mpc - MPC context.h]h)}(hjh]h[in/out] mpc - MPC context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hC[in/out] tree - MPC tree structure that plane will be removed from.h]h)}(hjh]hC[in/out] tree - MPC tree structure that plane will be removed from.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h.[in] mpcc - MPCC to be removed from tree. h]h)}(h-[in] mpcc - MPCC to be removed from tree.h]h-[in] mpcc - MPCC to be removed from tree.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jgjhuh1jhjhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hMhjubeh}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jfhj~hMhjubjg)}(hX:``get_mpcc_for_dpp_from_secondary`` Find, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. h](jm)}(h#``get_mpcc_for_dpp_from_secondary``h]js)}(hj!h]hget_mpcc_for_dpp_from_secondary}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(heFind, if it exists, a MPCC from a given 'secondary' MPC tree that is associated with specified plane.h]hiFind, if it exists, a MPCC from a given ‘secondary’ MPC tree that is associated with specified plane.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.h]hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(hReturn:h]hReturn:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj7ubh)}(h:struct mpcc* - pointer to plane or NULL if no plane found.h]h:struct mpcc* - pointer to plane or NULL if no plane found.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj6hMhjubjg)}(hX``get_mpcc_for_dpp`` Find, if it exists, a MPCC from a given MPC tree that is associated with specified plane. Parameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched. Return: struct mpcc* - pointer to plane or NULL if no plane found. h](jm)}(h``get_mpcc_for_dpp``h]js)}(hjh]hget_mpcc_for_dpp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hYFind, if it exists, a MPCC from a given MPC tree that is associated with specified plane.h]hYFind, if it exists, a MPCC from a given MPC tree that is associated with specified plane.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubh)}(hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.h]hiParameters: - [in/out] tree - MPC tree structure to search for plane. - [in] dpp_id - DPP to be searched.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h:struct mpcc* - pointer to plane or NULL if no plane found.h]h:struct mpcc* - pointer to plane or NULL if no plane found.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``wait_for_idle`` Wait for a MPCC in MPC context to enter idle state. Parameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state. Return: void h](jm)}(h``wait_for_idle``h]js)}(hjh]h wait_for_idle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM$hjubj)}(hhh](h)}(h3Wait for a MPCC in MPC context to enter idle state.h]h3Wait for a MPCC in MPC context to enter idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hRParameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state.h]hRParameters: - [in/out] mpc - MPC Context. - [in] id - MPCC to wait for idle state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM"hjubh)}(hvoidh]hvoid}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM$hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhM$hjubjg)}(h``assert_mpcc_idle_before_connect`` Assert if MPCC in MPC context is in idle state. Parameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state. Return: void h](jm)}(h#``assert_mpcc_idle_before_connect``h]js)}(hjSh]hassert_mpcc_idle_before_connect}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjQubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM3hjMubj)}(hhh](h)}(h/Assert if MPCC in MPC context is in idle state.h]h/Assert if MPCC in MPC context is in idle state.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM+hjiubh)}(hPParameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state.h]hPParameters: - [in/out] mpc - MPC context. - [in] id - MPCC to assert idle state.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hjiubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM1hjiubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhM3hjiubeh}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jfhjhhM3hjubjg)}(hX6``init_mpcc_list_from_hw`` Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values. Parameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. Return: void h](jm)}(h``init_mpcc_list_from_hw``h]js)}(hjh]hinit_mpcc_list_from_hw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMChjubj)}(hhh](h)}(hzIterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers' values.h]h|Iterate through the MPCC array from a given MPC context struct and configure each MPCC according to its registers’ values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM:hjubh)}(hParameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize.h]hParameters: - [in/out] mpc - MPC context to initialize MPCC array. - [in/out] tree - MPC tree structure containing MPCC contexts to initialize.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM=hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMAhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMChjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMChjubjg)}(hX'``set_denorm`` Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode. Return: void h](jm)}(h``set_denorm``h]js)}(hjh]h set_denorm}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMVhjubj)}(hhh](h)}(hgSet corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth.h]hgSet corresponding OPP DENORM_CONTROL register value to specific denorm_mode based on given color depth.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMLhj5ubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] output_depth - Arbitrary color depth to set denorm_mode.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMOhj5ubh)}(hReturn:h]hReturn:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMThj5ubh)}(hvoidh]hvoid}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hMVhj5ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj4hMVhjubjg)}(hX``set_denorm_clamp`` Set denorm clamp values on corresponding OPP DENORM CONTROL register. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set. Return: void h](jm)}(h``set_denorm_clamp``h]js)}(hjh]hset_denorm_clamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhhjubj)}(hhh](h)}(hESet denorm clamp values on corresponding OPP DENORM CONTROL register.h]hESet denorm clamp values on corresponding OPP DENORM CONTROL register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM_hjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] denorm_clamp - Arbitrary denorm clamp to be set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMahjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMfhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhhjubjg)}(hX``set_output_csc`` Set the Output Color Space Conversion matrix with given values and mode. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC. Return: void h](jm)}(h``set_output_csc``h]js)}(hjh]hset_output_csc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM}hjubj)}(hhh](h)}(hHSet the Output Color Space Conversion matrix with given values and mode.h]hHSet the Output Color Space Conversion matrix with given values and mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMrhjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] regval - Values to set in CSC matrix. - [in] ocsc_mode - Mode to set CSC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMuhjubh)}(hReturn:h]hReturn:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM{hjubh)}(hvoidh]hvoid}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM}hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhM}hjubjg)}(hX)``set_ocsc_default`` Set the Output Color Space Conversion matrix to default values according to color space. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC. Return: void h](jm)}(h``set_ocsc_default``h]js)}(hjQh]hset_ocsc_default}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjOubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjKubj)}(hhh](h)}(hXSet the Output Color Space Conversion matrix to default values according to color space.h]hXSet the Output Color Space Conversion matrix to default values according to color space.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjgubh)}(hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC.h]hParameters: - [in/out] mpc - MPC context. - [in] opp_id - Corresponding OPP to update register. - [in] color_space - OCSC color space. - [in] ocsc_mode - Mode to set CSC.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjgubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjgubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhMhjgubeh}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jfhjfhMhjubjg)}(h``set_output_gamma`` Set Output Gamma with given curve parameters. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters. Return: void h](jm)}(h``set_output_gamma``h]js)}(hjh]hset_output_gamma}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h-Set Output Gamma with given curve parameters.h]h-Set Output Gamma with given curve parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h}Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters.h]h}Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - Corresponding MPC to update registers. - [in] params - Parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(hX``power_on_mpc_mem_pwr`` Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on Return: void h](jm)}(h``power_on_mpc_mem_pwr``h]js)}(hjh]hpower_on_mpc_mem_pwr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h{Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode.h]h{Power on/off memory LUT for given MPCC. Powering on enables LUT to be updated. Powering off allows entering low power mode.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj3ubh)}(h\Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_onh]h\Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - MPCC to power on. - [in] power_on}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj3ubh)}(hReturn:h]hReturn:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj3ubh)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj3ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj2hMhjubjg)}(h``set_dwb_mux`` Set corresponding Display Writeback mux MPC register field to given MPCC id. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register. Return: void h](jm)}(h``set_dwb_mux``h]js)}(hjh]h set_dwb_mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj}ubj)}(hhh](h)}(hLSet corresponding Display Writeback mux MPC register field to given MPCC id.h]hLSet corresponding Display Writeback mux MPC register field to given MPCC id.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register.h]hParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. - [in] mpcc_id - MPCC id to be stored in DWB mux register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``disable_dwb_mux`` Reset corresponding Display Writeback mux MPC register field. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set. Return: void h](jm)}(h``disable_dwb_mux``h]js)}(hjh]hdisable_dwb_mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h=Reset corresponding Display Writeback mux MPC register field.h]h=Reset corresponding Display Writeback mux MPC register field.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set.h]hHParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``is_dwb_idle`` Check DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null. Parameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked. Return: bool - wheter DWB is idle or not h](jm)}(h``is_dwb_idle``h]js)}(hjOh]h is_dwb_idle}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjMubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjIubj)}(hhh](h)}(hMCheck DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null.h]hMCheck DWB status on MPC_DWB0_MUX_STATUS register field. Return if it is null.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjeubh)}(hLParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked.h]hLParameters: - [in/out] mpc - MPC context. - [in] dwb_id - DWB to be checked.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjeubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjeubh)}(h bool - wheter DWB is idle or noth]h bool - wheter DWB is idle or not}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMhjeubeh}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jfhjdhMhjubjg)}(h``set_out_rate_control`` Set display output rate control. Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control Return: void h](jm)}(h``set_out_rate_control``h]js)}(hjh]hset_out_rate_control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h Set display output rate control.h]h Set display output rate control.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(h~Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_controlh]h~Parameters: - [in/out] mpc - MPC context. - [in] opp_id - OPP to be set. - [in] enable - [in] rate_2x_mode - [in] flow_control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``set_gamut_remap`` Set post-blending CTM for given MPCC. Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust Return: void h](jm)}(h``set_gamut_remap``h]js)}(hjh]hset_gamut_remap}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h%Set post-blending CTM for given MPCC.h]h%Set post-blending CTM for given MPCC.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj1ubh)}(h[Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjusth]h[Parameters: - [in] mpc - MPC context. - [in] mpcc_id - MPCC to set gamut map. - [in] adjust}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj1ubh)}(hReturn:h]hReturn:}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj1ubh)}(hvoidh]hvoid}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj1ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj0hMhjubjg)}(hX ``program_1dlut`` Set 1 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). h](jm)}(h``program_1dlut``h]js)}(hjh]h program_1dlut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM-hj{ubj)}(hhh](h)}(hSet 1 dimensional Lookup Table.h]hSet 1 dimensional Lookup Table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM&hjubh)}(hrParameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idxh]hrParameters: - [in/out] mpc - MPC context - [in] params - curve parameters for the LUT configuration - [in] rmu_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM(hjubh)}(hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM-hjubeh}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jfhjhM-hjubjg)}(h``program_shaper`` Set shaper. Parameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx Return: bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). h](jm)}(h``program_shaper``h]js)}(hjh]hprogram_shaper}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM@hjubj)}(hhh](h)}(h Set shaper.h]h Set shaper.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM7hjubh)}(hbParameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idxh]hbParameters: - [in/out] mpc - MPC context - [in] params - curve parameters to be set - [in] rmu_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM9hjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM>hjubh)}(hebool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hebool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM@hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhM@hjubjg)}(hX ``acquire_rmu`` Set given MPCC to be multiplexed to given RMU unit. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. Return: unit32_t - rmu_idx if operation was successful, -1 else. h](jm)}(h``acquire_rmu``h]js)}(hj>h]h acquire_rmu}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj<ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMShj8ubj)}(hhh](h)}(h3Set given MPCC to be multiplexed to given RMU unit.h]h3Set given MPCC to be multiplexed to given RMU unit.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMJhjTubh)}(hParameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to.h]hParameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMLhjTubh)}(hReturn:h]hReturn:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMQhjTubh)}(h8unit32_t - rmu_idx if operation was successful, -1 else.h]h8unit32_t - rmu_idx if operation was successful, -1 else.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMShjTubeh}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jfhjShMShjubjg)}(hX``program_3dlut`` Set 3 dimensional Lookup Table. Parameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). h](jm)}(h``program_3dlut``h]js)}(hjh]h program_3dlut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMahjubj)}(hhh](h)}(hSet 3 dimensional Lookup Table.h]hSet 3 dimensional Lookup Table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMZhjubh)}(hxParameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idxh]hxParameters: - [in/out] mpc - MPC context - [in] params - tetrahedral parameters for the LUT configuration - [in] rmu_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM\hjubh)}(hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).h]hbbool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMahjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMahjubjg)}(h``release_rmu`` For a given MPCC, release the RMU unit it muliplexes to. Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC Return: int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. h](jm)}(h``release_rmu``h]js)}(hjh]h release_rmu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMshjubj)}(hhh](h)}(h8For a given MPCC, release the RMU unit it muliplexes to.h]h8For a given MPCC, release the RMU unit it muliplexes to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMkhjubh)}(h>Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCCh]h>Parameters: - [in/out] mpc - MPC context - [in] mpcc_id - MPCC}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMmhjubh)}(hReturn:h]hReturn:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMqhjubh)}(h_int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release.h]h_int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMshjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMshjubjg)}(h``get_mpc_out_mux`` Return MPC out mux. Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP Return: unsigned int - Out Mux h](jm)}(h``get_mpc_out_mux``h]js)}(hjah]hget_mpc_out_mux}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj_ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj[ubj)}(hhh](h)}(hReturn MPC out mux.h]hReturn MPC out mux.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMzhjwubh)}(h9Parameters: - [in] mpc - MPC context. - [in] opp_id - OPPh]h9Parameters: - [in] mpc - MPC context. - [in] opp_id - OPP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM|hjwubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjwubh)}(hunsigned int - Out Muxh]hunsigned int - Out Mux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjwubeh}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jfhjvhMhjubjg)}(h``set_bg_color`` Find corresponding bottommost MPCC and set its bg color. Parameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id Return: void h](jm)}(h``set_bg_color``h]js)}(hjh]h set_bg_color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h8Find corresponding bottommost MPCC and set its bg color.h]h8Find corresponding bottommost MPCC and set its bg color.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hfParameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_idh]hfParameters: - [in/out] mpc - MPC context. - [in] bg_color - background color to be set. - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(hg``set_mpc_mem_lp_mode`` Set mpc_mem_lp_mode. Parameters: - [in/out] mpc - MPC context. Return: void h](jm)}(h``set_mpc_mem_lp_mode``h]js)}(hj-h]hset_mpc_mem_lp_mode}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj+ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj'ubj)}(hhh](h)}(hSet mpc_mem_lp_mode.h]hSet mpc_mem_lp_mode.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjCubh)}(h)Parameters: - [in/out] mpc - MPC context.h]h)Parameters: - [in/out] mpc - MPC context.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjCubh)}(hReturn:h]hReturn:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjCubh)}(hvoidh]hvoid}(hjshhhNhNubah}(h]h ُ]h"]h$]h&]uh1hhjBhMhjCubeh}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jfhjBhMhjubjg)}(h``set_movable_cm_location`` Set Movable CM Location. Parameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id Return: void h](jm)}(h``set_movable_cm_location``h]js)}(hjh]hset_movable_cm_location}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hSet Movable CM Location.h]hSet Movable CM Location.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_idh]hHParameters: - [in/out] mpc - MPC context. - [in] location - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``update_3dlut_fast_load_select`` Update 3D LUT fast load select. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx Return: void h](jm)}(h!``update_3dlut_fast_load_select``h]js)}(hjh]hupdate_3dlut_fast_load_select}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hUpdate 3D LUT fast load select.h]hUpdate 3D LUT fast load select.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hHParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idxh]hHParameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in] hubp_idx}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(hX``get_3dlut_fast_load_status`` Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow Return: void h](jm)}(h``get_3dlut_fast_load_status``h]js)}(hj_h]hget_3dlut_fast_load_status}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj]ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjYubj)}(hhh](h)}(heGet 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.h]heGet 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjuubh)}(h|Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflowh]h|Parameters: - [in/out] mpc - MPC context. - [in] mpcc_id - [in/out] done - [in/out] soft_underflow - [in/out] hard_underflow}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjuubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjuubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjuubeh}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jfhjthMhjubjg)}(h``populate_lut`` Populate LUT with given tetrahedral parameters. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id Return: void h](jm)}(h``populate_lut``h]js)}(hjh]h populate_lut}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(h/Populate LUT with given tetrahedral parameters.h]h/Populate LUT with given tetrahedral parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hbParameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_idh]hbParameters: - [in/out] mpc - MPC context. - [in] id - [in] params - [in] lut_bank_a - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhMhjubjg)}(h``program_lut_read_write_control`` Program LUT RW control. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] mpcc_id Return: void h](jm)}(h"``program_lut_read_write_control``h]js)}(hj+h]hprogram_lut_read_write_control}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj)ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj%ubj)}(hhh](h)}(hProgram LUT RW control.h]hProgram LUT RW control.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjAubh)}(hTParameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] mpcc_idh]hTParameters: - [in/out] mpc - MPC context. - [in] id - [in] lut_bank_a - [in] mpcc_id}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjAubh)}(hReturn:h]hReturn:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjAubh)}(hvoidh]hvoid}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hMhjAubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jfhj@hMhjubjg)}(h``program_lut_mode`` Program LUT mode. Parameters: - [in/out] mpc - MPC context. - [in] id - [in] xable - [in] lut_bank_a - [in] mpcc_id Return: void h](jm)}(h``program_lut_mode``h]js)}(hjh]hprogram_lut_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubj)}(hhh](h)}(hProgram LUT mode.h]hProgram LUT mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(haParameters: - [in/out] mpc - MPC context. - [in] id - [in] xable - [in] lut_bank_a - [in] mpcc_idh]haParameters: - [in/out] mpc - MPC context. - [in] id - [in] xable - [in] lut_bank_a - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubh)}(hReturn:h]hReturn:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhM hjubh)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhM hjubjg)}(h``program_3dlut_size`` Program 3D LUT size. Parameters: - [in/out] mpc - MPC context. - [in] is_17x17x17 - is 3dlut 17x17x17 - [in] mpcc_id Return: voidh](jm)}(h``program_3dlut_size``h]js)}(hjh]hprogram_3dlut_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhjubj)}(hhh](h)}(hProgram 3D LUT size.h]hProgram 3D LUT size.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(h_Parameters: - [in/out] mpc - MPC context. - [in] is_17x17x17 - is 3dlut 17x17x17 - [in] mpcc_idh]h_Parameters: - [in/out] mpc - MPC context. - [in] is_17x17x17 - is 3dlut 17x17x17 - [in] mpcc_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hReturn:h]hReturn:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubh)}(hvoidh]hvoid}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:37: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.hhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhj hMhjubeh}(h]h ]h"]h$]h&]uh1jahjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhhNhNubeh}(h]mpcah ]h"]mpcah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hOPPh]hOPP}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhhhhhK*ubh)}(hThe Output Plane Processor (OPP) block groups have functions that format pixel streams such that they are suitable for display at the display device. The key functions contained in the OPP are:h]hThe Output Plane Processor (OPP) block groups have functions that format pixel streams such that they are suitable for display at the display device. The key functions contained in the OPP are:}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjmhhubj)}(hhh](j)}(h#Adaptive Backlight Modulation (ABM)h]h)}(hjh]h#Adaptive Backlight Modulation (ABM)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.h]h)}(h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.h]h]Formatter (FMT) which provide pixel-by-pixel operations for format the incoming pixel stream.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h>Output Buffer that provide pixel replication, and overlapping.h]h)}(hjh]h>Output Buffer that provide pixel replication, and overlapping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK"hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hInterface between MPC and OPTC.h]h)}(hjh]hInterface between MPC and OPTC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hClock and reset generation.h]h)}(hjh]hClock and reset generation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK$hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hCRC generation. h]h)}(hCRC generation.h]hCRC generation.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:44: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhK%hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jgjhuh1jhjhKhjmhhubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](jpwl_float_data (C struct)c.pwl_float_datahNtauh1jrhjmhhhNhNubj)}(hhh](j)}(hpwl_float_datah]j)}(hstruct pwl_float_datah](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKubj)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhjNhKubj)}(hpwl_float_datah]j)}(hj;h]hpwl_float_data}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj=hhhjNhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj9hhhjNhKubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1jhjNhKhj6hhubj)}(hhh]h)}(hFixed point RGB colorh]hFixed point RGB color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjNhKubeh}(h]h ](jstructeh"]h$]h&]j jjjjjjjjuh1jhhhjmhNhNubj)}(h**Definition**:: struct pwl_float_data { struct fixed31_32 r; struct fixed31_32 g; struct fixed31_32 b; }; **Members** ``r`` Component Red. ``g`` Component Green. ``b`` Component Blue.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjubj9)}(hestruct pwl_float_data { struct fixed31_32 r; struct fixed31_32 g; struct fixed31_32 b; };h]hestruct pwl_float_data { struct fixed31_32 r; struct fixed31_32 g; struct fixed31_32 b; };}hjsbah}(h]h ]h"]h$]h&]jjuh1j8hy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjubjb)}(hhh](jg)}(h``r`` Component Red. h](jm)}(h``r``h]js)}(hjh]hr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjubj)}(hhh]h)}(hComponent Red.h]hComponent Red.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jfhjhKhjubjg)}(h``g`` Component Green. h](jm)}(h``g``h]js)}(hj)h]hg}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj'ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhj#ubj)}(hhh]h)}(hComponent Green.h]hComponent Green.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jfhj>hKhjubjg)}(h``b`` Component Blue.h](jm)}(h``b``h]js)}(hjbh]hb}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj`ubah}(h]h ]h"]h$]h&]uh1jlhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhj\ubj)}(hhh]h)}(hComponent Blue.h]hComponent Blue.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhy/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:47: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.hhKhjxubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jfhjwhKhjubeh}(h]h ]h"]h$]h&]uh1jahjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjmhhhNhNubeh}(h]oppah ]h"]oppah$]h&]uh1hhhhhhhhK*ubh)}(hhh](h)}(hDIOh]hDIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK3ubh)}(hXDisplay Input Output (DIO), is the display input and output unit in DCN. It includes output encoders to support different display output, like DisplayPort, HDMI, DVI interface, and others. It also includes the control and status channels for these interfaces.h]hXDisplay Input Output (DIO), is the display input and output unit in DCN. It includes output encoders to support different display output, like DisplayPort, HDMI, DVI interface, and others. It also includes the control and status channels for these interfaces.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:53: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chKhjhhubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](j"can_use_dio_link_hwss (C function)c.can_use_dio_link_hwsshNtauh1jrhjhhhNhNubj)}(hhh](j)}(h]bool can_use_dio_link_hwss (const struct dc_link *link, const struct link_resource *link_res)h]j)}(h\bool can_use_dio_link_hwss(const struct dc_link *link, const struct link_resource *link_res)h](hdesc_sig_keyword_type)}(hboolh]hbool}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjhhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMHubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMHubj)}(hcan_use_dio_link_hwssh]j)}(hcan_use_dio_link_hwssh]hcan_use_dio_link_hwss}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMHubhdesc_parameterlist)}(hB(const struct dc_link *link, const struct link_resource *link_res)h](hdesc_parameter)}(hconst struct dc_link *linkh](j)}(hconsth]hconst}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubh)}(hhh]j)}(hdc_linkh]hdc_link}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&] refdomainjreftype identifier reftargetjdmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j} ASTIdentifier)}jxj sbc.can_use_dio_link_hwssasbuh1hhj$ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj$ubj)}(hlinkh]hlink}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphjjuh1j"hjubj#)}(h$const struct link_resource *link_resh](j)}(hj*h]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h link_resourceh]h link_resource}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypejx reftargetjmodnameN classnameNj|j)}j]jc.can_use_dio_link_hwssasbuh1hhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]h*}(hj' hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hlink_resh]hlink_res}(hj4 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j"hjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMHubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMHubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMHhjhhubj)}(hhh]h)}(h$Check if the link_hwss is accessibleh]h$Check if the link_hwss is accessible}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chM?hj[ hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMHubeh}(h]h ](jfunctioneh"]h$]h&]j jjjv jjv jjjuh1jhhhjhNhNubj)}(hX&**Parameters** ``const struct dc_link *link`` Reference a link struct containing one or more sinks and the connective status. ``const struct link_resource *link_res`` Mappable hardware resource used to enable a link. **Return** Return true if the link encoder is accessible from link.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMChjz ubjb)}(hhh](jg)}(ho``const struct dc_link *link`` Reference a link struct containing one or more sinks and the connective status. h](jm)}(h``const struct dc_link *link``h]js)}(hj h]hconst struct dc_link *link}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMBhj ubj)}(hhh]h)}(hOReference a link struct containing one or more sinks and the connective status.h]hOReference a link struct containing one or more sinks and the connective status.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMAhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hMBhj ubjg)}(h[``const struct link_resource *link_res`` Mappable hardware resource used to enable a link. h](jm)}(h(``const struct link_resource *link_res``h]js)}(hj h]h$const struct link_resource *link_res}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhj ubah}(h]h ]h"]h$]h&]uh1jlh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMChj ubj)}(hhh]h)}(h1Mappable hardware resource used to enable a link.h]h1Mappable hardware resource used to enable a link.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMChj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jfhj hMChj ubeh}(h]h ]h"]h$]h&]uh1jahjz ubh)}(h **Return**h]j)}(hj!h]hReturn}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMEhjz ubh)}(h8Return true if the link encoder is accessible from link.h]h8Return true if the link encoder is accessible from link.}(hj*!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMEhjz ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjs)}(hhh]h}(h]h ]h"]h$]h&]entries](jget_dio_link_hwss (C function)c.get_dio_link_hwsshNtauh1jrhjhhhNhNubj)}(hhh](j)}(h1const struct link_hwss * get_dio_link_hwss (void)h]j)}(h/const struct link_hwss *get_dio_link_hwss(void)h](j)}(hj*h]hconst}(hjY!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMZubj)}(h h]h }(hjg!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhhjf!hMZubj)}(hjh]hstruct}(hju!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhhjf!hMZubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhhjf!hMZubh)}(hhh]j)}(h link_hwssh]h link_hwss}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainjreftypejx reftargetj!modnameN classnameNj|j)}j]j)}jxget_dio_link_hwsssbc.get_dio_link_hwssasbuh1hhjU!hhhjf!hMZubj)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhhjf!hMZubj)}(hjh]h*}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU!hhhjf!hMZubj)}(hget_dio_link_hwssh]j)}(hj!h]hget_dio_link_hwss}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjU!hhhjf!hMZubj)}(h(void)h]j#)}(hvoidh]j)}(hvoidh]hvoid}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]noemphjjuh1j"hj!ubah}(h]h ]h"]h$]h&]jjuh1jhjU!hhhjf!hMZubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjQ!hhhjf!hMZubah}(h]jL!ah ](jjeh"]h$]h&]jj)jhuh1jhjf!hMZhjN!hhubj)}(hhh]h)}(hReturn link_hwss referenceh]hReturn link_hwss reference}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMRhj"hhubah}(h]h ]h"]h$]h&]uh1jhjN!hhhjf!hMZubeh}(h]h ](jfunctioneh"]h$]h&]j jjj0"jj0"jjjuh1jhhhjhNhNubj)}(h**Parameters** ``void`` no arguments **Description** This function behaves like a get function to return the link_hwss populated in the link_hwss_dio.c file. **Return** Return the reference to the filled struct of link_hwss.h](h)}(h**Parameters**h]j)}(hj:"h]h Parameters}(hj<"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8"ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMVhj4"ubjb)}(hhh]jg)}(h``void`` no arguments h](jm)}(h``void``h]js)}(hjY"h]hvoid}(hj["hhhNhNubah}(h]h ]h"]h$]h&]uh1jrhjW"ubah}(h]h ]h"]h$]h&]uh1jlh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMYhjS"ubj)}(hhh]h)}(h no argumentsh]h no arguments}(hjr"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn"hMYhjo"ubah}(h]h ]h"]h$]h&]uh1jhjS"ubeh}(h]h ]h"]h$]h&]uh1jfhjn"hMYhjP"ubah}(h]h ]h"]h$]h&]uh1jahj4"ubh)}(h**Description**h]j)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chM[hj4"ubh)}(hhThis function behaves like a get function to return the link_hwss populated in the link_hwss_dio.c file.h]hhThis function behaves like a get function to return the link_hwss populated in the link_hwss_dio.c file.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMShj4"ubh)}(h **Return**h]j)}(hj"h]hReturn}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMVhj4"ubh)}(h7Return the reference to the filled struct of link_hwss.h]h7Return the reference to the filled struct of link_hwss.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/display/dcn-blocks:56: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.chMWhj4"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h]dioah ]h"]dioah$]h&]uh1hhhhhhhhK3ubeh}(h](hid1eh ]h"]( dcn blocks dcn_blockseh$]h&]uh1hhhhhhhhKexpect_referenced_by_name}j"hsexpect_referenced_by_id}hhsubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj#error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}h]hasnameids}(j"hj"j"hhj1j.jejbjjjgjjj"j"u nametypes}(j"j"hj1jejjjj"uh}(hhj"hhhj.hjbj4jjjgjhjujzjjjj!jjmj4j9j"jjjjL!jQ!u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}j-#KsRparse_messages]transform_messages]hsystem_message)}(hhh]h)}(hhh]h0Hyperlink target "dcn-blocks" is not referenced.}hj#sbah}(h]h ]h"]h$]h&]uh1hhj#ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1j#uba transformerN include_log] decorationNhhub.