€•6iŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ&/translations/zh_CN/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/zh_TW/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/it_IT/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ja_JP/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ko_KR/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/sp_SP/gpu/amdgpu/debugfs”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒAMDGPU DebugFS”h]”hŒAMDGPU DebugFS”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒ@/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/debugfs.rst”h KubhŒ paragraph”“”)”}”(hŒ—The amdgpu driver provides a number of debugfs files to aid in debugging issues in the driver. These are usually found in /sys/kernel/debug/dri/.”h]”hŒ—The amdgpu driver provides a number of debugfs files to aid in debugging issues in the driver. These are usually found in /sys/kernel/debug/dri/.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒ DebugFS Files”h]”hŒ DebugFS Files”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÇhžhhŸh¶h K ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_benchmark”h]”hŒamdgpu_benchmark”…””}”(hhÛhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhØhžhhŸh¶h K ubh¸)”}”(hXQRun benchmarks using the DMA engine the driver uses for GPU memory paging. Write a number to the file to run the test. The results are written to the kernel log. VRAM is on device memory (dGPUs) or carve out (APUs) and GTT (Graphics Translation Tables) is system memory that is accessible by the GPU. The following tests are available:”h]”hXQRun benchmarks using the DMA engine the driver uses for GPU memory paging. Write a number to the file to run the test. The results are written to the kernel log. VRAM is on device memory (dGPUs) or carve out (APUs) and GTT (Graphics Translation Tables) is system memory that is accessible by the GPU. The following tests are available:”…””}”(hhéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhØhžhubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ+1: simple test, VRAM to GTT and GTT to VRAM”h]”h¸)”}”(hjh]”hŒ+1: simple test, VRAM to GTT and GTT to VRAM”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhþubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ2: simple test, VRAM to VRAM”h]”h¸)”}”(hjh]”hŒ2: simple test, VRAM to VRAM”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ.3: GTT to VRAM, buffer size sweep, powers of 2”h]”h¸)”}”(hj.h]”hŒ.3: GTT to VRAM, buffer size sweep, powers of 2”…””}”(hj0hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj,ubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ.4: VRAM to GTT, buffer size sweep, powers of 2”h]”h¸)”}”(hjEh]”hŒ.4: VRAM to GTT, buffer size sweep, powers of 2”…””}”(hjGhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjCubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ/5: VRAM to VRAM, buffer size sweep, powers of 2”h]”h¸)”}”(hj\h]”hŒ/5: VRAM to VRAM, buffer size sweep, powers of 2”…””}”(hj^hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjZubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ76: GTT to VRAM, buffer size sweep, common display sizes”h]”h¸)”}”(hjsh]”hŒ76: GTT to VRAM, buffer size sweep, common display sizes”…””}”(hjuhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjqubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ77: VRAM to GTT, buffer size sweep, common display sizes”h]”h¸)”}”(hjŠh]”hŒ77: VRAM to GTT, buffer size sweep, common display sizes”…””}”(hjŒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjˆubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubhý)”}”(hŒ98: VRAM to VRAM, buffer size sweep, common display sizes ”h]”h¸)”}”(hŒ88: VRAM to VRAM, buffer size sweep, common display sizes”h]”hŒ88: VRAM to VRAM, buffer size sweep, common display sizes”…””}”(hj£hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjŸubah}”(h]”h ]”h"]”h$]”h&]”uh1hühhùhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1h÷hŸh¶h KhhØhžhubeh}”(h]”Œamdgpu-benchmark”ah ]”h"]”Œamdgpu_benchmark”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_test_ib”h]”hŒamdgpu_test_ib”…””}”(hjÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÇhžhhŸh¶h Kubh¸)”}”(hXgRead this file to run simple IB (Indirect Buffer) tests on all kernel managed rings. IBs are command buffers usually generated by userspace applications which are submitted to the kernel for execution on an particular GPU engine. This just runs the simple IB tests included in the kernel. These tests are engine specific and verify that IB submission works.”h]”hXgRead this file to run simple IB (Indirect Buffer) tests on all kernel managed rings. IBs are command buffers usually generated by userspace applications which are submitted to the kernel for execution on an particular GPU engine. This just runs the simple IB tests included in the kernel. These tests are engine specific and verify that IB submission works.”…””}”(hjØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K!hjÇhžhubeh}”(h]”Œamdgpu-test-ib”ah ]”h"]”Œamdgpu_test_ib”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_discovery”h]”hŒamdgpu_discovery”…””}”(hjñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjîhžhhŸh¶h K(ubh¸)”}”(hŒÉProvides raw access to the IP discovery binary provided by the GPU. Read this file to access the raw binary. This is useful for verifying the contents of the IP discovery table. It is chip specific.”h]”hŒÉProvides raw access to the IP discovery binary provided by the GPU. Read this file to access the raw binary. This is useful for verifying the contents of the IP discovery table. It is chip specific.”…””}”(hjÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K*hjîhžhubeh}”(h]”Œamdgpu-discovery”ah ]”h"]”Œamdgpu_discovery”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K(ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_vbios”h]”hŒ amdgpu_vbios”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjhžhhŸh¶h K/ubh¸)”}”(hŒ¼Provides raw access to the ROM binary image from the GPU. Read this file to access the raw binary. This is useful for verifying the contents of the video BIOS ROM. It is board specific.”h]”hŒ¼Provides raw access to the ROM binary image from the GPU. Read this file to access the raw binary. This is useful for verifying the contents of the video BIOS ROM. It is board specific.”…””}”(hj&hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K1hjhžhubeh}”(h]”Œ amdgpu-vbios”ah ]”h"]”Œ amdgpu_vbios”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K/ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_evict_gtt”h]”hŒamdgpu_evict_gtt”…””}”(hj?hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj<hžhhŸh¶h K6ubh¸)”}”(hŒ`Evict all buffers from the GTT memory pool. Read this file to evict all buffers from this pool.”h]”hŒ`Evict all buffers from the GTT memory pool. Read this file to evict all buffers from this pool.”…””}”(hjMhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K8hj<hžhubeh}”(h]”Œamdgpu-evict-gtt”ah ]”h"]”Œamdgpu_evict_gtt”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K6ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_evict_vram”h]”hŒamdgpu_evict_vram”…””}”(hjfhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjchžhhŸh¶h Khjchžhubeh}”(h]”Œamdgpu-evict-vram”ah ]”h"]”Œamdgpu_evict_vram”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K”h]”hŒamdgpu_ring_”…””}”(hj´hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj±hžhhŸh¶h KHubh¸)”}”(hX“Provides read access to the kernel managed ring buffers for each ring . These are useful for debugging problems on a particular ring. The ring buffer is how the CPU sends commands to the GPU. The CPU writes commands into the buffer and then asks the GPU engine to process it. This is the raw binary contents of the ring buffer. Use a tool like UMR to decode the rings into human readable form.”h]”hX“Provides read access to the kernel managed ring buffers for each ring . These are useful for debugging problems on a particular ring. The ring buffer is how the CPU sends commands to the GPU. The CPU writes commands into the buffer and then asks the GPU engine to process it. This is the raw binary contents of the ring buffer. Use a tool like UMR to decode the rings into human readable form.”…””}”(hjÂhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KJhj±hžhubeh}”(h]”Œamdgpu-ring-name”ah ]”h"]”Œamdgpu_ring_”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h KHubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_mqd_”h]”hŒamdgpu_mqd_”…””}”(hjÛhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjØhžhhŸh¶h KRubh¸)”}”(hX$Provides read access to the kernel managed MQD (Memory Queue Descriptor) for ring managed by the kernel driver. MQDs define the features of the ring and are used to store the ring's state when it is not connected to hardware. The driver writes the requested ring features and metadata (GPU addresses of the ring itself and associated buffers) to the MQD and the firmware uses the MQD to populate the hardware when the ring is mapped to a hardware slot. Only available on engines which use MQDs. This provides access to the raw MQD binary.”h]”hX&Provides read access to the kernel managed MQD (Memory Queue Descriptor) for ring managed by the kernel driver. MQDs define the features of the ring and are used to store the ring’s state when it is not connected to hardware. The driver writes the requested ring features and metadata (GPU addresses of the ring itself and associated buffers) to the MQD and the firmware uses the MQD to populate the hardware when the ring is mapped to a hardware slot. Only available on engines which use MQDs. This provides access to the raw MQD binary.”…””}”(hjéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KThjØhžhubeh}”(h]”Œamdgpu-mqd-name”ah ]”h"]”Œamdgpu_mqd_”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h KRubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_error_”h]”hŒamdgpu_error_”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÿhžhhŸh¶h K^ubh¸)”}”(hŒØProvides an interface to set an error code on the dma fences associated with ring . The error code specified is propogated to all fences associated with the ring. Use this to inject a fence error into a ring.”h]”hŒØProvides an interface to set an error code on the dma fences associated with ring . The error code specified is propogated to all fences associated with the ring. Use this to inject a fence error into a ring.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K`hjÿhžhubeh}”(h]”Œamdgpu-error-name”ah ]”h"]”Œamdgpu_error_”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K^ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_pm_info”h]”hŒamdgpu_pm_info”…””}”(hj)hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj&hžhhŸh¶h Keubh¸)”}”(hXProvides human readable information about the power management features and state of the GPU. This includes current GFX clock, Memory clock, voltages, average SoC power, temperature, GFX load, Memory load, SMU feature mask, VCN power state, clock and power gating features.”h]”hXProvides human readable information about the power management features and state of the GPU. This includes current GFX clock, Memory clock, voltages, average SoC power, temperature, GFX load, Memory load, SMU feature mask, VCN power state, clock and power gating features.”…””}”(hj7hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kghj&hžhubeh}”(h]”Œamdgpu-pm-info”ah ]”h"]”Œamdgpu_pm_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Keubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_firmware_info”h]”hŒamdgpu_firmware_info”…””}”(hjPhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjMhžhhŸh¶h Kmubh¸)”}”(hŒ©Lists the firmware versions for all firmwares used by the GPU. Only entries with a non-0 version are valid. If the version is 0, the firmware is not valid for the GPU.”h]”hŒ©Lists the firmware versions for all firmwares used by the GPU. Only entries with a non-0 version are valid. If the version is 0, the firmware is not valid for the GPU.”…””}”(hj^hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KohjMhžhubeh}”(h]”Œamdgpu-firmware-info”ah ]”h"]”Œamdgpu_firmware_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Kmubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_fence_info”h]”hŒamdgpu_fence_info”…””}”(hjwhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjthžhhŸh¶h Ktubh¸)”}”(hXÆShows the last signalled and emitted fence sequence numbers for each kernel driver managed ring. Fences are associated with submissions to the engine. Emitted fences have been submitted to the ring and signalled fences have been signalled by the GPU. Rings with a larger emitted fence value have outstanding work that is still being processed by the engine that owns that ring. When the emitted and signalled fence values are equal, the ring is idle.”h]”hXÆShows the last signalled and emitted fence sequence numbers for each kernel driver managed ring. Fences are associated with submissions to the engine. Emitted fences have been submitted to the ring and signalled fences have been signalled by the GPU. Rings with a larger emitted fence value have outstanding work that is still being processed by the engine that owns that ring. When the emitted and signalled fence values are equal, the ring is idle.”…””}”(hj…hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kvhjthžhubeh}”(h]”Œamdgpu-fence-info”ah ]”h"]”Œamdgpu_fence_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Ktubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_gem_info”h]”hŒamdgpu_gem_info”…””}”(hjžhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj›hžhhŸh¶h Kubh¸)”}”(hŒÏLists all of the PIDs using the GPU and the GPU buffers that they have allocated. This lists the buffer size, pool (VRAM, GTT, etc.), and buffer attributes (CPU access required, CPU cache attributes, etc.).”h]”hŒÏLists all of the PIDs using the GPU and the GPU buffers that they have allocated. This lists the buffer size, pool (VRAM, GTT, etc.), and buffer attributes (CPU access required, CPU cache attributes, etc.).”…””}”(hj¬hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj›hžhubeh}”(h]”Œamdgpu-gem-info”ah ]”h"]”Œamdgpu_gem_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_vm_info”h]”hŒamdgpu_vm_info”…””}”(hjÅhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÂhžhhŸh¶h K†ubh¸)”}”(hŒÕLists all of the PIDs using the GPU and the GPU buffers that they have allocated as well as the status of those buffers relative to that process' GPU virtual address space (e.g., evicted, idle, invalidated, etc.).”h]”hŒ×Lists all of the PIDs using the GPU and the GPU buffers that they have allocated as well as the status of those buffers relative to that process’ GPU virtual address space (e.g., evicted, idle, invalidated, etc.).”…””}”(hjÓhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KˆhjÂhžhubeh}”(h]”Œamdgpu-vm-info”ah ]”h"]”Œamdgpu_vm_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K†ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_sa_info”h]”hŒamdgpu_sa_info”…””}”(hjìhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjéhžhhŸh¶h Kubh¸)”}”(hXPrints out all of the suballocations (sa) by the suballocation manager in the kernel driver. Prints the GPU address, size, and fence info associated with each suballocation. The suballocations are used internally within the kernel driver for various things.”h]”hXPrints out all of the suballocations (sa) by the suballocation manager in the kernel driver. Prints the GPU address, size, and fence info associated with each suballocation. The suballocations are used internally within the kernel driver for various things.”…””}”(hjúhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjéhžhubeh}”(h]”Œamdgpu-sa-info”ah ]”h"]”Œamdgpu_sa_info”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu__mm”h]”hŒamdgpu__mm”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjhžhhŸh¶h K•ubh¸)”}”(hŒ4Prints TTM information about the memory pool .”h]”hŒ4Prints TTM information about the memory pool .”…””}”(hj!hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K—hjhžhubeh}”(h]”Œamdgpu-pool-mm”ah ]”h"]”Œamdgpu__mm”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K•ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_vram”h]”hŒ amdgpu_vram”…””}”(hj:hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj7hžhhŸh¶h Kšubh¸)”}”(hŒSProvides direct access to VRAM. Used by tools like UMR to inspect objects in VRAM.”h]”hŒSProvides direct access to VRAM. Used by tools like UMR to inspect objects in VRAM.”…””}”(hjHhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kœhj7hžhubeh}”(h]”Œ amdgpu-vram”ah ]”h"]”Œ amdgpu_vram”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h Kšubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_iomem”h]”hŒ amdgpu_iomem”…””}”(hjahžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj^hžhhŸh¶h K ubh¸)”}”(hŒTProvides direct access to GTT memory. Used by tools like UMR to inspect GTT memory.”h]”hŒTProvides direct access to GTT memory. Used by tools like UMR to inspect GTT memory.”…””}”(hjohžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¢hj^hžhubeh}”(h]”Œ amdgpu-iomem”ah ]”h"]”Œ amdgpu_iomem”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_regs_*”h]”hŒ amdgpu_regs_*”…””}”(hjˆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj…hžhhŸh¶h K¦ubh¸)”}”(hŒrProvides direct access to various register aperatures on the GPU. Used by tools like UMR to access GPU registers.”h]”hŒrProvides direct access to various register aperatures on the GPU. Used by tools like UMR to access GPU registers.”…””}”(hj–hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¨hj…hžhubeh}”(h]”Œ amdgpu-regs”ah ]”h"]”Œ amdgpu_regs_*”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K¦ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_regs2”h]”hŒ amdgpu_regs2”…””}”(hj¯hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¬hžhhŸh¶h K¬ubh¸)”}”(hŒKProvides an IOCTL interface used by UMR for interacting with GPU registers.”h]”hŒKProvides an IOCTL interface used by UMR for interacting with GPU registers.”…””}”(hj½hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K®hj¬hžhubeh}”(h]”Œ amdgpu-regs2”ah ]”h"]”Œ amdgpu_regs2”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K¬ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_sensors”h]”hŒamdgpu_sensors”…””}”(hjÖhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÓhžhhŸh¶h K²ubh¸)”}”(hŒˆProvides an interface to query GPU power metrics (temperature, average power, etc.). Used by tools like UMR to query GPU power metrics.”h]”hŒˆProvides an interface to query GPU power metrics (temperature, average power, etc.). Used by tools like UMR to query GPU power metrics.”…””}”(hjähžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K´hjÓhžhubeh}”(h]”Œamdgpu-sensors”ah ]”h"]”Œamdgpu_sensors”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K²ubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_gca_config”h]”hŒamdgpu_gca_config”…””}”(hjýhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjúhžhhŸh¶h K¹ubh¸)”}”(hŒ—Provides an interface to query GPU details (Graphics/Compute Array config, PCI config, GPU family, etc.). Used by tools like UMR to query GPU details.”h]”hŒ—Provides an interface to query GPU details (Graphics/Compute Array config, PCI config, GPU family, etc.). Used by tools like UMR to query GPU details.”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K»hjúhžhubeh}”(h]”Œamdgpu-gca-config”ah ]”h"]”Œamdgpu_gca_config”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K¹ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_wave”h]”hŒ amdgpu_wave”…””}”(hj$hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj!hžhhŸh¶h K¿ubh¸)”}”(hŒ|Used to query GFX/compute wave information from the hardware. Used by tools like UMR to query GFX/compute wave information.”h]”hŒ|Used to query GFX/compute wave information from the hardware. Used by tools like UMR to query GFX/compute wave information.”…””}”(hj2hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÁhj!hžhubeh}”(h]”Œ amdgpu-wave”ah ]”h"]”Œ amdgpu_wave”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h K¿ubh¢)”}”(hhh]”(h§)”}”(hŒ amdgpu_gpr”h]”hŒ amdgpu_gpr”…””}”(hjKhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjHhžhhŸh¶h KÅubh¸)”}”(hŒ•Used to query GFX/compute GPR (General Purpose Register) information from the hardware. Used by tools like UMR to query GPRs when debugging shaders.”h]”hŒ•Used to query GFX/compute GPR (General Purpose Register) information from the hardware. Used by tools like UMR to query GPRs when debugging shaders.”…””}”(hjYhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÇhjHhžhubeh}”(h]”Œ amdgpu-gpr”ah ]”h"]”Œ amdgpu_gpr”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h KÅubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_gprwave”h]”hŒamdgpu_gprwave”…””}”(hjrhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjohžhhŸh¶h KËubh¸)”}”(hŒJProvides an IOCTL interface used by UMR for interacting with shader waves.”h]”hŒJProvides an IOCTL interface used by UMR for interacting with shader waves.”…””}”(hj€hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÍhjohžhubeh}”(h]”Œamdgpu-gprwave”ah ]”h"]”Œamdgpu_gprwave”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h KËubh¢)”}”(hhh]”(h§)”}”(hŒamdgpu_fw_attestation”h]”hŒamdgpu_fw_attestation”…””}”(hj™hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj–hžhhŸh¶h KÐubh¸)”}”(hŒDProvides an interface for reading back firmware attestation records.”h]”hŒDProvides an interface for reading back firmware attestation records.”…””}”(hj§hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÒhj–hžhubeh}”(h]”Œamdgpu-fw-attestation”ah ]”h"]”Œamdgpu_fw_attestation”ah$]”h&]”uh1h¡hhÇhžhhŸh¶h KÐubeh}”(h]”Œ debugfs-files”ah ]”h"]”Œ debugfs files”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K ubeh}”(h]”Œamdgpu-debugfs”ah ]”h"]”Œamdgpu debugfs”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jðŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jÊjÇjÂj¿jÄjÁjëjèjjj9j6j`j]j‡j„j®j«jÕjÒjüjùj#j jJjGjqjnj˜j•j¿j¼jæjãj j j4j1j[jXj‚jj©j¦jÐjÍj÷jôjjjEjBjljij“jjºj·uŒ nametypes”}”(jʉj‰jĉjë‰j‰j9‰j`‰j‡‰j®‰jÕ‰jü‰j#‰jJ‰jq‰j˜‰j¿‰jæ‰j ‰j4‰j[‰j‚‰j©‰jЉj÷‰j‰jE‰jl‰j“‰jº‰uh}”(jÇh£j¿hÇjÁhØjèjÇjjîj6jj]j<j„jcj«jŠjÒj±jùjØj jÿjGj&jnjMj•jtj¼j›jãjÂj jéj1jjXj7jj^j¦j…jÍj¬jôjÓjjújBj!jijHjjoj·j–uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.