sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget./translations/zh_CN/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/zh_TW/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/it_IT/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ja_JP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ko_KR/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/pt_BR/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/sp_SP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDGPU Glossaryh]hAMDGPU Glossary}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhH/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/amdgpu-glossary.rsthKubh paragraph)}(hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.h]hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at ‘Documentation/gpu/amdgpu/display/dc-glossary.rst’.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhglossary)}(hhh]hdefinition_list)}(hhh](hdefinition_list_item)}(hhh](hterm)}(hactive_cu_numberh](hactive_cu_number}(hhhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleactive_cu_numberterm-active_cu_numbermainNtauh1hhhhK hhubeh}(h]jah ]h"]h$]h&]uh1hhhhK hhubh definition)}(hhh]h)}(hThe number of CUs that are active on the system. The number of active CUs may be less than SE * SH * CU depending on the board configuration.h]hThe number of CUs that are active on the system. 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Bufferh]h Depth Buffer}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjHubah}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hDFSh](hDFS}(hjhhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jDFSterm-DFSjNtauh1hhhhK8hjhubeh}(h]j{ah ]h"]h$]h&]uh1hhhhK8hjeubj )}(hhh]h)}(hDigital Frequency Synthesizerh]hDigital Frequency Synthesizer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1j hjeubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hECPh](hECP}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jECPterm-ECPjNtauh1hhhhK;hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK;hjubj )}(hhh]h)}(hEnhanced Content Protectionh]hEnhanced Content Protection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hEOPh](hEOP}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jEOPterm-EOPjNtauh1hhhhK>hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK>hjubj )}(hhh]h)}(hEnd Of Pipe/Pipelineh]hEnd Of Pipe/Pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h 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This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU's address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.h]hXGraphics Address Remapping Table. This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU’s address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjoubah}(h]h ]h"]h$]h&]uh1j hjQubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGCh](hGC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGCterm-GCjNtauh1hhhhKMhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKMhjubj )}(hhh]h)}(hGraphics and Computeh]hGraphics and Compute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGDSh](hGDS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGDSterm-GDSjNtauh1hhhhKPhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKPhjubj )}(hhh]h)}(hGlobal Data Shareh]hGlobal Data Share}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGEh](hGE}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGEterm-GEjNtauh1hhhhKShjubeh}(h]jah ]h"]h$]h&]uh1hhhhKShjubj )}(hhh]h)}(hGeometry Engineh]hGeometry Engine}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhj ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGMCh](hGMC}(hj@hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGMCterm-GMCjNtauh1hhhhKVhj@ubeh}(h]jSah ]h"]h$]h&]uh1hhhhKVhj=ubj )}(hhh]h)}(hGraphic Memory Controllerh]hGraphic Memory Controller}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj[ubah}(h]h ]h"]h$]h&]uh1j hj=ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGPRh](hGPR}(hj{hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGPRterm-GPRjNtauh1hhhhKYhj{ubeh}(h]jah ]h"]h$]h&]uh1hhhhKYhjxubj )}(hhh]h)}(hGeneral Purpose Registerh]hGeneral Purpose Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1j hjxubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGPUVMh](hGPUVM}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGPUVM term-GPUVMjNtauh1hhhhK\hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK\hjubj )}(hhh]h)}(hXiGPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.h]hXkGPU Virtual Memory. This is the GPU’s MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGTTh](hGTT}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](jGTTterm-GTTjNtauh1hhhhKchjubeh}(h]jah ]h"]h$]h&]uh1hhhhKchjubj )}(hhh]h)}(hX5Graphics Translation Tables. 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UTC is equivalent to TLB. You might see a variation of this acronym with L at the end, i.e., UTCL followed by a number; L means the cache level (e.g., UTCL1 and UTCL2).h]hUnified Translation Cache. UTC is equivalent to TLB. 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