sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget./translations/zh_CN/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/zh_TW/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/it_IT/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ja_JP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ko_KR/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/sp_SP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDGPU Glossaryh]hAMDGPU Glossary}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhH/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/amdgpu-glossary.rsthKubh paragraph)}(hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.h]hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at ‘Documentation/gpu/amdgpu/display/dc-glossary.rst’.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhglossary)}(hhh]hdefinition_list)}(hhh](hdefinition_list_item)}(hhh](hterm)}(hactive_cu_numberh](hactive_cu_number}(hhhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleactive_cu_numberterm-active_cu_numbermainNtauh1hhhhK hhubeh}(h]hah ]h"]h$]h&]uh1hhhhK hhubh definition)}(hhh]h)}(hThe number of CUs that are active on the system. The number of active CUs may be less than SE * SH * CU depending on the board configuration.h]hThe number of CUs that are active on the system. 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This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU's address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.h]hXGraphics Address Remapping Table. This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU’s address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGCh](hGC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGCterm-GChNtauh1hhhhKDhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKDhjubh)}(hhh]h)}(hGraphics and Computeh]hGraphics and Compute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGDSh](hGDS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGDSterm-GDShNtauh1hhhhKGhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKGhjubh)}(hhh]h)}(hGlobal Data Shareh]hGlobal Data Share}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGEh](hGE}(hj@hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGEterm-GEhNtauh1hhhhKJhj@ubeh}(h]jSah ]h"]h$]h&]uh1hhhhKJhj=ubh)}(hhh]h)}(hGeometry Engineh]hGeometry Engine}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj[ubah}(h]h ]h"]h$]h&]uh1hhj=ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGMCh](hGMC}(hj{hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGMCterm-GMChNtauh1hhhhKMhj{ubeh}(h]jah ]h"]h$]h&]uh1hhhhKMhjxubh)}(hhh]h)}(hGraphic Memory Controllerh]hGraphic Memory Controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1hhjxubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGPUVMh](hGPUVM}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGPUVM term-GPUVMhNtauh1hhhhKPhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKPhjubh)}(hhh]h)}(hXiGPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.h]hXkGPU Virtual Memory. This is the GPU’s MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGTTh](hGTT}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGTTterm-GTThNtauh1hhhhKWhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKWhjubh)}(hhh]h)}(hX5Graphics Translation Tables. This is a memory pool managed through TTM which provides access to system resources (memory or MMIO space) for use by the GPU. These addresses can be mapped into the "GART" GPUVM page table for use by the kernel driver or into per process GPUVM page tables for application usage.h]hX9Graphics Translation Tables. This is a memory pool managed through TTM which provides access to system resources (memory or MMIO space) for use by the GPU. These addresses can be mapped into the “GART” GPUVM page table for use by the kernel driver or into per process GPUVM page tables for application usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIHh](hIH}(hj,hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIHterm-IHhNtauh1hhhhK^hj,ubeh}(h]j?ah ]h"]h$]h&]uh1hhhhK^hj)ubh)}(hhh]h)}(hInterrupt Handlerh]hInterrupt Handler}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjGubah}(h]h ]h"]h$]h&]uh1hhj)ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hHQDh](hHQD}(hjghhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hHQDterm-HQDhNtauh1hhhhKahjgubeh}(h]jzah ]h"]h$]h&]uh1hhhhKahjdubh)}(hhh]h)}(hHardware Queue Descriptorh]hHardware Queue Descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKchjubah}(h]h ]h"]h$]h&]uh1hhjdubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIBh](hIB}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIBterm-IBhNtauh1hhhhKdhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKdhjubh)}(hhh]h)}(hIndirect Bufferh]hIndirect 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