sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget./translations/zh_CN/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/zh_TW/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/it_IT/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ja_JP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/ko_KR/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget./translations/sp_SP/gpu/amdgpu/amdgpu-glossarymodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hAMDGPU Glossaryh]hAMDGPU Glossary}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhH/var/lib/git/docbuild/linux/Documentation/gpu/amdgpu/amdgpu-glossary.rsthKubh paragraph)}(hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.h]hHere you can find some generic acronyms used in the amdgpu driver. Notice that we have a dedicated glossary for Display Core at ‘Documentation/gpu/amdgpu/display/dc-glossary.rst’.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhglossary)}(hhh]hdefinition_list)}(hhh](hdefinition_list_item)}(hhh](hterm)}(hactive_cu_numberh](hactive_cu_number}(hhhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleactive_cu_numberterm-active_cu_numbermainNtauh1hhhhK hhubeh}(h]hah ]h"]h$]h&]uh1hhhhK hhubh definition)}(hhh]h)}(hThe number of CUs that are active on the system. The number of active CUs may be less than SE * SH * CU depending on the board configuration.h]hThe number of CUs that are active on the system. The number of active CUs may be less than SE * SH * CU depending on the board configuration.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hBACOh](hBACO}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hBACO term-BACOhNtauh1hhhhKhjubeh}(h]j-ah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hBus Alive, Chip Offh]hBus Alive, Chip Off}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hBOCOh](hBOCO}(hjUhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hBOCO term-BOCOhNtauh1hhhhKhjUubeh}(h]jhah ]h"]h$]h&]uh1hhhhKhjRubh)}(hhh]h)}(hBus Off, Chip Offh]hBus Off, Chip Off}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjpubah}(h]h ]h"]h$]h&]uh1hhjRubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCEh](hCE}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCEterm-CEhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hConstant Engineh]hConstant Engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCIKh](hCIK}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCIKterm-CIKhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(h Sea Islandsh]h Sea Islands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCBh](hCB}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCBterm-CBhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(h Color Bufferh]h Color Buffer}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj!ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCPh](hCP}(hjAhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCPterm-CPhNtauh1hhhhKhjAubeh}(h]jTah ]h"]h$]h&]uh1hhhhKhj>ubh)}(hhh]h)}(hCommand Processorh]hCommand Processor}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\ubah}(h]h ]h"]h$]h&]uh1hhj>ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCPCh](hCPC}(hj|hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCPCterm-CPChNtauh1hhhhK hj|ubeh}(h]jah ]h"]h$]h&]uh1hhhhK hjyubh)}(hhh]h)}(hCommand Processor Computeh]hCommand Processor Compute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjyubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCPFh](hCPF}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCPFterm-CPFhNtauh1hhhhK#hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK#hjubh)}(hhh]h)}(hCommand Processor Fetchh]hCommand Processor Fetch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCPGh](hCPG}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCPGterm-CPGhNtauh1hhhhK&hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK&hjubh)}(hhh]h)}(hCommand Processor Graphicsh]hCommand Processor Graphics}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCPLIBh](hCPLIB}(hj-hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCPLIB term-CPLIBhNtauh1hhhhK)hj-ubeh}(h]j@ah ]h"]h$]h&]uh1hhhhK)hj*ubh)}(hhh]h)}(hContent Protection Libraryh]hContent Protection Library}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjHubah}(h]h ]h"]h$]h&]uh1hhj*ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCSh](hCS}(hjhhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCSterm-CShNtauh1hhhhK,hjhubeh}(h]j{ah ]h"]h$]h&]uh1hhhhK,hjeubh)}(hhh]h)}(hCommand Submissionh]hCommand Submission}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1hhjeubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCSBh](hCSB}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCSBterm-CSBhNtauh1hhhhK/hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK/hjubh)}(hhh]h)}(hClear State Indirect Bufferh]hClear State Indirect Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hCUh](hCU}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hCUterm-CUhNtauh1hhhhK2hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK2hjubh)}(hhh]h)}(h Compute Unith]h Compute Unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hDBh](hDB}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hDBterm-DBhNtauh1hhhhK5hjubeh}(h]j,ah ]h"]h$]h&]uh1hhhhK5hjubh)}(hhh]h)}(h Depth Bufferh]h Depth Buffer}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj4ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hDFSh](hDFS}(hjThhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hDFSterm-DFShNtauh1hhhhK8hjTubeh}(h]jgah ]h"]h$]h&]uh1hhhhK8hjQubh)}(hhh]h)}(hDigital Frequency Synthesizerh]hDigital Frequency Synthesizer}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjoubah}(h]h ]h"]h$]h&]uh1hhjQubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hECPh](hECP}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hECPterm-ECPhNtauh1hhhhK;hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK;hjubh)}(hhh]h)}(hEnhanced Content Protectionh]hEnhanced Content Protection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hEOPh](hEOP}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hEOPterm-EOPhNtauh1hhhhK>hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK>hjubh)}(hhh]h)}(hEnd Of Pipe/Pipelineh]hEnd Of Pipe/Pipeline}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hFLRh](hFLR}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hFLRterm-FLRhNtauh1hhhhKAhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKAhjubh)}(hhh]h)}(hFunction Level Reseth]hFunction Level Reset}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGARTh](hGART}(hj@hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGART term-GARThNtauh1hhhhKDhj@ubeh}(h]jSah ]h"]h$]h&]uh1hhhhKDhj=ubh)}(hhh]h)}(hXGraphics Address Remapping Table. This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU's address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.h]hXGraphics Address Remapping Table. This is the name we use for the GPUVM page table used by the GPU kernel driver. It remaps system resources (memory or MMIO space) into the GPU’s address space so the GPU can access them. The name GART harkens back to the days of AGP when the platform provided an MMU that the GPU could use to get a contiguous view of scattered pages for DMA. The MMU has since moved on to the GPU, but the name stuck.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhj[ubah}(h]h ]h"]h$]h&]uh1hhj=ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGCh](hGC}(hj{hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGCterm-GChNtauh1hhhhKMhj{ubeh}(h]jah ]h"]h$]h&]uh1hhhhKMhjxubh)}(hhh]h)}(hGraphics and Computeh]hGraphics and Compute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1hhjxubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGDSh](hGDS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGDSterm-GDShNtauh1hhhhKPhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKPhjubh)}(hhh]h)}(hGlobal Data Shareh]hGlobal Data Share}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGEh](hGE}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGEterm-GEhNtauh1hhhhKShjubeh}(h]jah ]h"]h$]h&]uh1hhhhKShjubh)}(hhh]h)}(hGeometry Engineh]hGeometry Engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGMCh](hGMC}(hj,hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGMCterm-GMChNtauh1hhhhKVhj,ubeh}(h]j?ah ]h"]h$]h&]uh1hhhhKVhj)ubh)}(hhh]h)}(hGraphic Memory Controllerh]hGraphic Memory Controller}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjGubah}(h]h ]h"]h$]h&]uh1hhj)ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGPRh](hGPR}(hjghhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGPRterm-GPRhNtauh1hhhhKYhjgubeh}(h]jzah ]h"]h$]h&]uh1hhhhKYhjdubh)}(hhh]h)}(hGeneral Purpose Registerh]hGeneral Purpose Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1hhjdubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGPUVMh](hGPUVM}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGPUVM term-GPUVMhNtauh1hhhhK\hjubeh}(h]jah ]h"]h$]h&]uh1hhhhK\hjubh)}(hhh]h)}(hXiGPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.h]hXkGPU Virtual Memory. This is the GPU’s MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These allow the GPU to remap VRAM and system resources into GPU virtual address spaces for use by the GPU kernel driver and applications using the GPU. These provide memory protection for different applications using the GPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGTTh](hGTT}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGTTterm-GTThNtauh1hhhhKchjubeh}(h]jah ]h"]h$]h&]uh1hhhhKchjubh)}(hhh]h)}(hX5Graphics Translation Tables. This is a memory pool managed through TTM which provides access to system resources (memory or MMIO space) for use by the GPU. These addresses can be mapped into the "GART" GPUVM page table for use by the kernel driver or into per process GPUVM page tables for application usage.h]hX9Graphics Translation Tables. This is a memory pool managed through TTM which provides access to system resources (memory or MMIO space) for use by the GPU. These addresses can be mapped into the “GART” GPUVM page table for use by the kernel driver or into per process GPUVM page tables for application usage.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hGWSh](hGWS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hGWSterm-GWShNtauh1hhhhKjhjubeh}(h]j+ah ]h"]h$]h&]uh1hhhhKjhjubh)}(hhh]h)}(hGlobal Wave Synch]hGlobal Wave Sync}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhj3ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIHh](hIH}(hjShhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIHterm-IHhNtauh1hhhhKmhjSubeh}(h]jfah ]h"]h$]h&]uh1hhhhKmhjPubh)}(hhh]h)}(hInterrupt Handlerh]hInterrupt Handler}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjnubah}(h]h ]h"]h$]h&]uh1hhjPubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIVh](hIV}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIVterm-IVhNtauh1hhhhKphjubeh}(h]jah ]h"]h$]h&]uh1hhhhKphjubh)}(hhh]h)}(hInterrupt Vectorh]hInterrupt Vector}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hHQDh](hHQD}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hHQDterm-HQDhNtauh1hhhhKshjubeh}(h]jah ]h"]h$]h&]uh1hhhhKshjubh)}(hhh]h)}(hHardware Queue Descriptorh]hHardware Queue Descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIBh](hIB}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIBterm-IBhNtauh1hhhhKvhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKvhjubh)}(hhh]h)}(hIndirect Bufferh]hIndirect Buffer}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIMUh](hIMU}(hj?hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIMUterm-IMUhNtauh1hhhhKyhj?ubeh}(h]jRah ]h"]h$]h&]uh1hhhhKyhj<ubh)}(hhh]h)}(h5Integrated Management Unit (Power Management support)h]h5Integrated Management Unit (Power Management support)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjZubah}(h]h ]h"]h$]h&]uh1hhj<ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hIPh](hIP}(hjzhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hIPterm-IPhNtauh1hhhhK|hjzubeh}(h]jah ]h"]h$]h&]uh1hhhhK|hjwubh)}(hhh]h)}(hIntellectual Property blocksh]hIntellectual Property blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1hhjwubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hKCQh](hKCQ}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hKCQterm-KCQhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hKernel Compute Queueh]hKernel Compute Queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hKFDh](hKFD}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hKFDterm-KFDhNtauh1hhhhKhjubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hKernel Fusion Driverh]hKernel Fusion Driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hKGQh](hKGQ}(hj+ hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hKGQterm-KGQhNtauh1hhhhKhj+ ubeh}(h]j> ah ]h"]h$]h&]uh1hhhhKhj( ubh)}(hhh]h)}(hKernel Graphics Queueh]hKernel Graphics Queue}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjF ubah}(h]h ]h"]h$]h&]uh1hhj( ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hKIQh](hKIQ}(hjf hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hKIQterm-KIQhNtauh1hhhhKhjf ubeh}(h]jy ah ]h"]h$]h&]uh1hhhhKhjc ubh)}(hhh]h)}(hKernel Interface Queueh]hKernel Interface Queue}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjc ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMCh](hMC}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMCterm-MChNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMemory Controllerh]hMemory Controller}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMCBPh](hMCBP}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMCBP term-MCBPhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMid Command Buffer Preemptionh]hMid Command Buffer Preemption}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMEh](hME}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMEterm-MEhNtauh1hhhhKhj ubeh}(h]j* ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMicroEngine (Graphics)h]hMicroEngine (Graphics)}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2 ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMECh](hMEC}(hjR hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMECterm-MEChNtauh1hhhhKhjR ubeh}(h]je ah ]h"]h$]h&]uh1hhhhKhjO ubh)}(hhh]h)}(hMicroEngine Computeh]hMicroEngine Compute}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjm ubah}(h]h ]h"]h$]h&]uh1hhjO ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMESh](hMES}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMESterm-MEShNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMicroEngine Schedulerh]hMicroEngine Scheduler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMMHUBh](hMMHUB}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMMHUB term-MMHUBhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMulti-Media HUBh]hMulti-Media HUB}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hMQDh](hMQD}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hMQDterm-MQDhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hMemory Queue Descriptorh]hMemory Queue Descriptor}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPAh](hPA}(hj> hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPAterm-PAhNtauh1hhhhKhj> ubeh}(h]jQ ah ]h"]h$]h&]uh1hhhhKhj; ubh)}(hhh]h)}(h&Primitive Assembler / Physical Addressh]h&Primitive Assembler / Physical Address}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjY ubah}(h]h ]h"]h$]h&]uh1hhj; ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPDEh](hPDE}(hjy hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPDEterm-PDEhNtauh1hhhhKhjy ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhjv ubh)}(hhh]h)}(hPage Directory Entryh]hPage Directory Entry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjv ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPFPh](hPFP}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPFPterm-PFPhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hPre-Fetch Parser (Graphics)h]hPre-Fetch Parser (Graphics)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPPLibh](hPPLib}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPPLib term-PPLibhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h@PowerPlay Library - PowerPlay is the power management component.h]h@PowerPlay Library - PowerPlay is the power management component.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPRTh](hPRT}(hj* hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPRTterm-PRThNtauh1hhhhKhj* ubeh}(h]j= ah ]h"]h$]h&]uh1hhhhKhj' ubh)}(hhh]h)}(h;Partially Resident Texture (also known as sparse residency)h]h;Partially Resident Texture (also known as sparse residency)}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjE ubah}(h]h ]h"]h$]h&]uh1hhj' ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPSPh](hPSP}(hje hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPSPterm-PSPhNtauh1hhhhKhje ubeh}(h]jx ah ]h"]h$]h&]uh1hhhhKhjb ubh)}(hhh]h)}(hPlatform Security Processorh]hPlatform Security Processor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjb ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hPTEh](hPTE}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hPTEterm-PTEhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hPage Table Entryh]hPage Table Entry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hRBh](hRB}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hRBterm-RBhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h,Render Backends. Some people called it ROPs.h]h,Render Backends. Some people called it ROPs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hRLCh](hRLC}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hRLCterm-RLChNtauh1hhhhKhj ubeh}(h]j) ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(hRunList Controller. This name is a remnant of past ages and doesn't have much meaning today. It's a group of general-purpose helper engines for the GFX block. It's involved in GFX power management and SR-IOV, among other things.h]hRunList Controller. This name is a remnant of past ages and doesn’t have much meaning today. It’s a group of general-purpose helper engines for the GFX block. It’s involved in GFX power management and SR-IOV, among other things.}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj1 ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSCh](hSC}(hjQ hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSCterm-SChNtauh1hhhhKhjQ ubeh}(h]jd ah ]h"]h$]h&]uh1hhhhKhjN ubh)}(hhh]h)}(hScan Converterh]hScan Converter}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjl ubah}(h]h ]h"]h$]h&]uh1hhjN ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSDMAh](hSDMA}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSDMA term-SDMAhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h System DMAh]h System DMA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSEh](hSE}(hj hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSEterm-SEhNtauh1hhhhKhj ubeh}(h]j ah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h Shader Engineh]h Shader Engine}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSGPRh](hSGPR}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSGPR term-SGPRhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h Scalar General-Purpose Registersh]h Scalar General-Purpose Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSHh](hSH}(hj=hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSHterm-SHhNtauh1hhhhKhj=ubeh}(h]jPah ]h"]h$]h&]uh1hhhhKhj:ubh)}(hhh]h)}(h SHader arrayh]h SHader array}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXubah}(h]h ]h"]h$]h&]uh1hhj:ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSIh](hSI}(hjxhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSIterm-SIhNtauh1hhhhKhjxubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjuubh)}(hhh]h)}(hSouthern Islandsh]hSouthern Islands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjuubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSMU/SMCh](hSMU/SMC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSMU/SMC term-SMU-SMChNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(h5System Management Unit / System Management Controllerh]h5System Management Unit / System Management Controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(h SPI (AMDGPU)h](h SPI (AMDGPU)}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](h SPI (AMDGPU)term-SPI-AMDGPUhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hShader Processor Inputh]hShader Processor Input}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSRLCh](hSRLC}(hj)hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSRLC term-SRLChNtauh1hhhhKhj)ubeh}(h]j<ah ]h"]h$]h&]uh1hhhhKhj&ubh)}(hhh]h)}(hSave/Restore List Controlh]hSave/Restore List Control}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjDubah}(h]h ]h"]h$]h&]uh1hhj&ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSRLGh](hSRLG}(hjdhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSRLG term-SRLGhNtauh1hhhhKhjdubeh}(h]jwah ]h"]h$]h&]uh1hhhhKhjaubh)}(hhh]h)}(hSave/Restore List GPM_MEMh]hSave/Restore List GPM_MEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjaubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSRLSh](hSRLS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSRLS term-SRLShNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hSave/Restore List SRM_MEMh]hSave/Restore List SRM_MEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSSh](hSS}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSSterm-SShNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hSpread Spectrumh]hSpread Spectrum}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hSXh](hSX}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hSXterm-SXhNtauh1hhhhKhjubeh}(h]j(ah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(h Shader Exporth]h Shader Export}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj0ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hTAh](hTA}(hjPhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hTAterm-TAhNtauh1hhhhKhjPubeh}(h]jcah ]h"]h$]h&]uh1hhhhKhjMubh)}(hhh]h)}(hTrusted Applicationh]hTrusted Application}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1hhjMubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hTCh](hTC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hTCterm-TChNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(h Texture Cacheh]h Texture Cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(h TCP (AMDGPU)h](h TCP (AMDGPU)}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](h TCP (AMDGPU)term-TCP-AMDGPUhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hX/Texture Cache per Pipe. Even though the name "Texture" is part of this acronym, the TCP represents the path to memory shaders; i.e., it is not related to texture. The name is a leftover from older designs where shader stages had different cache designs; it refers to the L1 cache in older architectures.h]hX3Texture Cache per Pipe. Even though the name “Texture” is part of this acronym, the TCP represents the path to memory shaders; i.e., it is not related to texture. The name is a leftover from older designs where shader stages had different cache designs; it refers to the L1 cache in older architectures.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hTMRh](hTMR}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hTMRterm-TMRhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hTrusted Memory Regionh]hTrusted Memory Region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hTMZh](hTMZ}(hj<hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hTMZterm-TMZhNtauh1hhhhKhj<ubeh}(h]jOah ]h"]h$]h&]uh1hhhhKhj9ubh)}(hhh]h)}(hTrusted Memory Zoneh]hTrusted Memory Zone}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjWubah}(h]h ]h"]h$]h&]uh1hhj9ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hTOCh](hTOC}(hjwhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hTOCterm-TOChNtauh1hhhhKhjwubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjtubh)}(hhh]h)}(hTable of Contentsh]hTable of Contents}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjtubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hUMCh](hUMC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hUMCterm-UMChNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hUnified Memory Controllerh]hUnified Memory Controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hUMSCHh](hUMSCH}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hUMSCH term-UMSCHhNtauh1hhhhKhjubeh}(h]jah ]h"]h$]h&]uh1hhhhKhjubh)}(hhh]h)}(hUser Mode Schedulerh]hUser Mode Scheduler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(h UTC (AMDGPU)h](h UTC (AMDGPU)}(hj(hhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](h UTC (AMDGPU)term-UTC-AMDGPUhNtauh1hhhhMhj(ubeh}(h]j;ah ]h"]h$]h&]uh1hhhhMhj%ubh)}(hhh]h)}(hUnified Translation Cache. UTC is equivalent to TLB. You might see a variation of this acronym with L at the end, i.e., UTCL followed by a number; L means the cache level (e.g., UTCL1 and UTCL2).h]hUnified Translation Cache. UTC is equivalent to TLB. You might see a variation of this acronym with L at the end, i.e., UTCL followed by a number; L means the cache level (e.g., UTCL1 and UTCL2).}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjCubah}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hUVDh](hUVD}(hjchhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hUVDterm-UVDhNtauh1hhhhMhjcubeh}(h]jvah ]h"]h$]h&]uh1hhhhMhj`ubh)}(hhh]h)}(hUnified Video Decoderh]hUnified Video Decoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj~ubah}(h]h ]h"]h$]h&]uh1hhj`ubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hVCEh](hVCE}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hVCEterm-VCEhNtauh1hhhhM hjubeh}(h]jah ]h"]h$]h&]uh1hhhhM hjubh)}(hhh]h)}(hVideo Compression Engineh]hVideo Compression Engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hVCNh](hVCN}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hVCNterm-VCNhNtauh1hhhhM hjubeh}(h]jah ]h"]h$]h&]uh1hhhhM hjubh)}(hhh]h)}(hVideo Codec Nexth]hVideo Codec Next}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hVGPRh](hVGPR}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hVGPR term-VGPRhNtauh1hhhhMhjubeh}(h]j'ah ]h"]h$]h&]uh1hhhhMhjubh)}(hhh]h)}(h Vector General-Purpose Registersh]h Vector General-Purpose Registers}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hVMIDh](hVMID}(hjOhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hVMID term-VMIDhNtauh1hhhhMhjOubeh}(h]jbah ]h"]h$]h&]uh1hhhhMhjLubh)}(hhh]h)}(hVirtual Memory IDh]hVirtual Memory ID}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjubah}(h]h ]h"]h$]h&]uh1hhjLubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hVPEh](hVPE}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hVPEterm-VPEhNtauh1hhhhMhjubeh}(h]jah ]h"]h$]h&]uh1hhhhMhjubh)}(hhh]h)}(hVideo Processing Engineh]hVideo Processing Engine}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hXCCh](hXCC}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hXCCterm-XCChNtauh1hhhhMhjubeh}(h]jah ]h"]h$]h&]uh1hhhhMhjubh)}(hhh]h)}(hAccelerator Core Complexh]hAccelerator Core Complex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubh)}(hhh](h)}(hXCPh](hXCP}(hjhhhNhNubh)}(hhh]h}(h]h ]h"]h$]h&]h](hXCPterm-XCPhNtauh1hhhhMhjubeh}(h]jah ]h"]h$]h&]uh1hhhhMhjubh)}(hhh]h)}(hAccelerator Core Partitionh]hAccelerator Core Partition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]hah"]h$]h&]uh1hhhhhhhhNubah}(h]h ]h"]h$]h&]sorteduh1hhhhhhhhNubeh}(h]amdgpu-glossaryah ]h"]amdgpu glossaryah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjperror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}jJjGs nametypes}jJsh}(jGhhhj-jjhjUjjjjjjjTjAjj|jjjjj@j-j{jhjjjjj,jjgjTjjjjjjjSj@jj{jjjjj?j,jzjgjjjjj+jjfjSjjjjjjjRj?jjzjjj jj> j+ jy jf j j j j j* j je jR j j j j j j jQ j> j jy j j j j j= j* jx je j j j j j) j jd jQ j j j j jjjPj=jjxjjjjj<j)jwjdjjjjj(jjcjPjjjjjjjOj<jjwjjjjj;j(jvjcjjjjj'jjbjOjjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.