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AMD refers to this feature as AMD Platform Quality of Service(AMD QoS).}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj]hhubj)}(hZThis feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo flag bits:h]hZThis feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo flag bits:}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj]hhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK?uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]j)}(h-RDT (Resource Director Technology) Allocationh]h-RDT (Resource Director Technology) Allocation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h"rdt_a"h]h “rdt_a”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h!CAT (Cache Allocation Technology)h]h!CAT (Cache Allocation Technology)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h"cat_l3", "cat_l2"h]h“cat_l3”, “cat_l2”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h"CDP (Code and Data Prioritization)h]h"CDP (Code and Data Prioritization)}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h"cdp_l3", "cdp_l2"h]h“cdp_l3”, “cdp_l2”}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(hCQM (Cache QoS Monitoring)h]hCQM (Cache QoS Monitoring)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjVubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hhh]j)}(h"cqm_llc", "cqm_occup_llc"h]h"“cqm_llc”, “cqm_occup_llc”}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjmubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h!MBM (Memory Bandwidth Monitoring)h]h!MBM (Memory Bandwidth Monitoring)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h "cqm_mbm_total", "cqm_mbm_local"h]h(“cqm_mbm_total”, “cqm_mbm_local”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h!MBA (Memory Bandwidth Allocation)h]h!MBA (Memory Bandwidth Allocation)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h"mba"h]h “mba”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h'SMBA (Slow Memory Bandwidth Allocation)h]h'SMBA (Slow Memory Bandwidth Allocation)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h""h]h“”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h/BMEC (Bandwidth Monitoring Event Configuration)h]h/BMEC (Bandwidth Monitoring Event Configuration)}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]j)}(h""h]h“”}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjIubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h/ABMC (Assignable Bandwidth Monitoring Counters)h]h/ABMC (Assignable Bandwidth Monitoring Counters)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjiubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]j)}(h""h]h“”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h:SDCIAE (Smart Data Cache Injection Allocation Enforcement)h]h:SDCIAE (Smart Data Cache Injection Allocation Enforcement)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h""h]h“”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj]hhhhhNubj)}(hXHistorically, new features were made visible by default in /proc/cpuinfo. This resulted in the feature flags becoming hard to parse by humans. Adding a new flag to /proc/cpuinfo should be avoided if user space can obtain information about the feature from resctrl's info directory.h]hXHistorically, new features were made visible by default in /proc/cpuinfo. This resulted in the feature flags becoming hard to parse by humans. Adding a new flag to /proc/cpuinfo should be avoided if user space can obtain information about the feature from resctrl’s info directory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK!hj]hhubj)}(h*To use the feature mount the file system::h]h)To use the feature mount the file system:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK&hj]hhubh literal_block)}(hN# mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrlh]hN# mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl}hj sbah}(h]h ]h"]h$]h&]hhuh1j hhhK(hj]hhubj)}(hmount options are:h]hmount options are:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK*hj]hhubhdefinition_list)}(hhh](hdefinition_list_item)}(h?"cdp": Enable code/data prioritization in L3 cache allocations.h](hterm)}(h"cdp":h]h “cdp”:}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK,hj( ubh definition)}(hhh]j)}(h8Enable code/data prioritization in L3 cache allocations.h]h8Enable code/data prioritization in L3 cache allocations.}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK-hj> ubah}(h]h ]h"]h$]h&]uh1j< hj( ubeh}(h]h ]h"]h$]h&]uh1j& hhhK,hj# ubj' )}(hA"cdpl2": Enable code/data prioritization in L2 cache allocations.h](j- )}(h"cdpl2":h]h “cdpl2”:}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK.hj[ ubj= )}(hhh]j)}(h8Enable code/data prioritization in L2 cache allocations.h]h8Enable code/data prioritization in L2 cache allocations.}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK/hjm ubah}(h]h ]h"]h$]h&]uh1j< hj[ ubeh}(h]h ]h"]h$]h&]uh1j& hhhK.hj# hhubj' )}(hX"mba_MBps": Enable the MBA Software Controller(mba_sc) to specify MBA bandwidth in MiBpsh](j- )}(h "mba_MBps":h]h“mba_MBps”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK1hj ubj= )}(hhh]j)}(hLEnable the MBA Software Controller(mba_sc) to specify MBA bandwidth in MiBpsh]hLEnable the MBA Software Controller(mba_sc) to specify MBA bandwidth in MiBps}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK1hj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhK1hj# hhubj' )}(hs"debug": Make debug files accessible. Available debug files are annotated with "Available only with debug option". h](j- )}(h"debug":h]h “debug”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK5hj ubj= )}(hhh]j)}(hiMake debug files accessible. Available debug files are annotated with "Available only with debug option".h]hmMake debug files accessible. Available debug files are annotated with “Available only with debug option”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK4hj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhK5hj# hhubeh}(h]h ]h"]h$]h&]uh1j! hj]hhhhhNubj)}(h(L2 and L3 CDP are controlled separately.h]h(L2 and L3 CDP are controlled separately.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK7hj]hhubj)}(hXRDT features are orthogonal. A particular system may support only monitoring, only control, or both monitoring and control. Cache pseudo-locking is a unique way of using cache control to "pin" or "lock" data in the cache. Details can be found in "Cache Pseudo-Locking".h]hXRDT features are orthogonal. A particular system may support only monitoring, only control, or both monitoring and control. Cache pseudo-locking is a unique way of using cache control to “pin” or “lock” data in the cache. Details can be found in “Cache Pseudo-Locking”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK9hj]hhubj)}(hXThe mount succeeds if either of allocation or monitoring is present, but only those files and directories supported by the system will be created. For more details on the behavior of the interface during monitoring and allocation, see the "Resource alloc and monitor groups" section.h]hXThe mount succeeds if either of allocation or monitoring is present, but only those files and directories supported by the system will be created. For more details on the behavior of the interface during monitoring and allocation, see the “Resource alloc and monitor groups” section.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK@hj]hhubj\)}(hhh](ja)}(hInfo directoryh]hInfo directory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKFubj)}(hThe 'info' directory contains information about the enabled resources. Each resource has its own subdirectory. The subdirectory names reflect the resource names.h]hThe ‘info’ directory contains information about the enabled resources. Each resource has its own subdirectory. The subdirectory names reflect the resource names.}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKHhj hhubj)}(hMost of the files in the resource's subdirectory are read-only, and describe properties of the resource. Resources that support global configuration options also include writable files that can be used to modify those settings.h]hMost of the files in the resource’s subdirectory are read-only, and describe properties of the resource. Resources that support global configuration options also include writable files that can be used to modify those settings.}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKLhj hhubj)}(hJEach subdirectory contains the following files with respect to allocation:h]hJEach subdirectory contains the following files with respect to allocation:}(hjE hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKQhj hhubj)}(hWCache resource(L3/L2) subdirectory contains the following files related to allocation:h]hWCache resource(L3/L2) subdirectory contains the following files related to allocation:}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKThj hhubj" )}(hhh](j' )}(h"num_closids": The number of CLOSIDs which are valid for this resource. The kernel uses the smallest number of CLOSIDs of all enabled resources as limit.h](j- )}(h"num_closids":h]h“num_closids”:}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKYhjd ubj= )}(hhh]j)}(hThe number of CLOSIDs which are valid for this resource. The kernel uses the smallest number of CLOSIDs of all enabled resources as limit.h]hThe number of CLOSIDs which are valid for this resource. The kernel uses the smallest number of CLOSIDs of all enabled resources as limit.}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKXhjv ubah}(h]h ]h"]h$]h&]uh1j< hjd ubeh}(h]h ]h"]h$]h&]uh1j& hhhKYhja ubj' )}(hZ"cbm_mask": The bitmask which is valid for this resource. This mask is equivalent to 100%.h](j- )}(h "cbm_mask":h]h“cbm_mask”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK\hj ubj= )}(hhh]j)}(hNThe bitmask which is valid for this resource. This mask is equivalent to 100%.h]hNThe bitmask which is valid for this resource. This mask is equivalent to 100%.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK\hj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhK\hja hhubj' )}(h^"min_cbm_bits": The minimum number of consecutive bits which must be set when writing a mask. h](j- )}(h"min_cbm_bits":h]h“min_cbm_bits”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhK`hj ubj= )}(hhh]j)}(hMThe minimum number of consecutive bits which must be set when writing a mask.h]hMThe minimum number of consecutive bits which must be set when writing a mask.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK_hj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhK`hja hhubj' )}(hX"shareable_bits": Bitmask of shareable resource with other executing entities (e.g. I/O). Applies to all instances of this resource. User can use this when setting up exclusive cache partitions. Note that some platforms support devices that have their own settings for cache use which can over-ride these bits. When "io_alloc" is enabled, a portion of each cache instance can be configured for shared use between hardware and software. "bit_usage" should be used to see which portions of each cache instance is configured for hardware use via "io_alloc" feature because every cache instance can have its "io_alloc" bitmask configured independently via "io_alloc_cbm". h](j- )}(h"shareable_bits":h]h“shareable_bits”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKnhj ubj= )}(hhh](j)}(hX$Bitmask of shareable resource with other executing entities (e.g. I/O). Applies to all instances of this resource. User can use this when setting up exclusive cache partitions. Note that some platforms support devices that have their own settings for cache use which can over-ride these bits.h]hX$Bitmask of shareable resource with other executing entities (e.g. I/O). Applies to all instances of this resource. User can use this when setting up exclusive cache partitions. Note that some platforms support devices that have their own settings for cache use which can over-ride these bits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKchj ubj)}(hXdWhen "io_alloc" is enabled, a portion of each cache instance can be configured for shared use between hardware and software. "bit_usage" should be used to see which portions of each cache instance is configured for hardware use via "io_alloc" feature because every cache instance can have its "io_alloc" bitmask configured independently via "io_alloc_cbm".h]hXxWhen “io_alloc” is enabled, a portion of each cache instance can be configured for shared use between hardware and software. “bit_usage” should be used to see which portions of each cache instance is configured for hardware use via “io_alloc” feature because every cache instance can have its “io_alloc” bitmask configured independently via “io_alloc_cbm”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKihj ubeh}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKnhja hhubj' )}(hXJ"bit_usage": Annotated capacity bitmasks showing how all instances of the resource are used. The legend is: "0": Corresponding region is unused. When the system's resources have been allocated and a "0" is found in "bit_usage" it is a sign that resources are wasted. "H": Corresponding region is used by hardware only but available for software use. If a resource has bits set in "shareable_bits" or "io_alloc_cbm" but not all of these bits appear in the resource groups' schemata then the bits appearing in "shareable_bits" or "io_alloc_cbm" but no resource group will be marked as "H". "X": Corresponding region is available for sharing and used by hardware and software. These are the bits that appear in "shareable_bits" or "io_alloc_cbm" as well as a resource group's allocation. "S": Corresponding region is used by software and available for sharing. "E": Corresponding region is used exclusively by one resource group. No sharing allowed. "P": Corresponding region is pseudo-locked. No sharing allowed.h](j- )}(h "bit_usage":h]h“bit_usage”:}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj. ubj= )}(hhh](j)}(h^Annotated capacity bitmasks showing how all instances of the resource are used. The legend is:h]h^Annotated capacity bitmasks showing how all instances of the resource are used. The legend is:}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKqhj@ ubh block_quote)}(hX"0": Corresponding region is unused. When the system's resources have been allocated and a "0" is found in "bit_usage" it is a sign that resources are wasted. "H": Corresponding region is used by hardware only but available for software use. If a resource has bits set in "shareable_bits" or "io_alloc_cbm" but not all of these bits appear in the resource groups' schemata then the bits appearing in "shareable_bits" or "io_alloc_cbm" but no resource group will be marked as "H". "X": Corresponding region is available for sharing and used by hardware and software. These are the bits that appear in "shareable_bits" or "io_alloc_cbm" as well as a resource group's allocation. "S": Corresponding region is used by software and available for sharing. "E": Corresponding region is used exclusively by one resource group. No sharing allowed. "P": Corresponding region is pseudo-locked. No sharing allowed.h]j" )}(hhh](j' )}(h"0": Corresponding region is unused. When the system's resources have been allocated and a "0" is found in "bit_usage" it is a sign that resources are wasted. h](j- )}(h"0":h]h“0”:}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKxhjZ ubj= )}(hhh]j)}(hCorresponding region is unused. When the system's resources have been allocated and a "0" is found in "bit_usage" it is a sign that resources are wasted.h]hCorresponding region is unused. When the system’s resources have been allocated and a “0” is found in “bit_usage” it is a sign that resources are wasted.}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKuhjl ubah}(h]h ]h"]h$]h&]uh1j< hjZ ubeh}(h]h ]h"]h$]h&]uh1j& hhhKxhjW ubj' )}(hX@"H": Corresponding region is used by hardware only but available for software use. If a resource has bits set in "shareable_bits" or "io_alloc_cbm" but not all of these bits appear in the resource groups' schemata then the bits appearing in "shareable_bits" or "io_alloc_cbm" but no resource group will be marked as "H".h](j- )}(h"H":h]h“H”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(hX;Corresponding region is used by hardware only but available for software use. If a resource has bits set in "shareable_bits" or "io_alloc_cbm" but not all of these bits appear in the resource groups' schemata then the bits appearing in "shareable_bits" or "io_alloc_cbm" but no resource group will be marked as "H".h]hXQCorresponding region is used by hardware only but available for software use. If a resource has bits set in “shareable_bits” or “io_alloc_cbm” but not all of these bits appear in the resource groups’ schemata then the bits appearing in “shareable_bits” or “io_alloc_cbm” but no resource group will be marked as “H”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK{hj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjW ubj' )}(h"X": Corresponding region is available for sharing and used by hardware and software. These are the bits that appear in "shareable_bits" or "io_alloc_cbm" as well as a resource group's allocation.h](j- )}(h"X":h]h“X”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(hCorresponding region is available for sharing and used by hardware and software. These are the bits that appear in "shareable_bits" or "io_alloc_cbm" as well as a resource group's allocation.h]hCorresponding region is available for sharing and used by hardware and software. These are the bits that appear in “shareable_bits” or “io_alloc_cbm” as well as a resource group’s allocation.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjW ubj' )}(hH"S": Corresponding region is used by software and available for sharing.h](j- )}(h"S":h]h“S”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(hCCorresponding region is used by software and available for sharing.h]hCCorresponding region is used by software and available for sharing.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjW ubj' )}(hX"E": Corresponding region is used exclusively by one resource group. No sharing allowed.h](j- )}(h"E":h]h“E”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(hSCorresponding region is used exclusively by one resource group. No sharing allowed.h]hSCorresponding region is used exclusively by one resource group. No sharing allowed.}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj( ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjW ubj' )}(h?"P": Corresponding region is pseudo-locked. No sharing allowed.h](j- )}(h"P":h]h“P”:}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhjE ubj= )}(hhh]j)}(h:Corresponding region is pseudo-locked. No sharing allowed.h]h:Corresponding region is pseudo-locked. No sharing allowed.}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjW ubah}(h]h ]h"]h$]h&]uh1j< hjE ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjW ubeh}(h]h ]h"]h$]h&]uh1j! hjS ubah}(h]h ]h"]h$]h&]uh1jQ hhhKthj@ ubeh}(h]h ]h"]h$]h&]uh1j< hj. ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhja hhubj' )}(h"sparse_masks": Indicates if non-contiguous 1s value in CBM is supported. "0": Only contiguous 1s value in CBM is supported. "1": Non-contiguous 1s value in CBM is supported. h](j- )}(h"sparse_masks":h]h“sparse_masks”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh](j)}(h9Indicates if non-contiguous 1s value in CBM is supported.h]h9Indicates if non-contiguous 1s value in CBM is supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubjR )}(hq"0": Only contiguous 1s value in CBM is supported. "1": Non-contiguous 1s value in CBM is supported. h]j" )}(hhh](j' )}(h2"0": Only contiguous 1s value in CBM is supported.h](j- )}(h"0":h]h“0”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(h-Only contiguous 1s value in CBM is supported.h]h-Only contiguous 1s value in CBM is supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhj ubj' )}(h2"1": Non-contiguous 1s value in CBM is supported. h](j- )}(h"1":h]h“1”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(h,Non-contiguous 1s value in CBM is supported.h]h,Non-contiguous 1s value in CBM is supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhj ubeh}(h]h ]h"]h$]h&]uh1j! hj ubah}(h]h ]h"]h$]h&]uh1jQ hhhKhj ubeh}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhja hhubj' )}(hX6"io_alloc": "io_alloc" enables system software to configure the portion of the cache allocated for I/O traffic. File may only exist if the system supports this feature on some of its cache resources. "disabled": Resource supports "io_alloc" but the feature is disabled. Portions of cache used for allocation of I/O traffic cannot be configured. "enabled": Portions of cache used for allocation of I/O traffic can be configured using "io_alloc_cbm". "not supported": Support not available for this resource. The feature can be modified by writing to the interface, for example: To enable:: # echo 1 > /sys/fs/resctrl/info/L3/io_alloc To disable:: # echo 0 > /sys/fs/resctrl/info/L3/io_alloc The underlying implementation may reduce resources available to general (CPU) cache allocation. See architecture specific notes below. Depending on usage requirements the feature can be enabled or disabled. On AMD systems, io_alloc feature is supported by the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for io_alloc is the highest CLOSID supported by the resource. When io_alloc is enabled, the highest CLOSID is dedicated to io_alloc and no longer available for general (CPU) cache allocation. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (CDP_CODE), making this CLOSID no longer available for general (CPU) cache allocation for both the CDP_CODE and CDP_DATA resources. h](j- )}(h "io_alloc":h]h“io_alloc”:}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj, ubj= )}(hhh](j)}(h"io_alloc" enables system software to configure the portion of the cache allocated for I/O traffic. File may only exist if the system supports this feature on some of its cache resources.h]h“io_alloc” enables system software to configure the portion of the cache allocated for I/O traffic. File may only exist if the system supports this feature on some of its cache resources.}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubjR )}(hXW"disabled": Resource supports "io_alloc" but the feature is disabled. Portions of cache used for allocation of I/O traffic cannot be configured. "enabled": Portions of cache used for allocation of I/O traffic can be configured using "io_alloc_cbm". "not supported": Support not available for this resource. h]j" )}(hhh](j' )}(h"disabled": Resource supports "io_alloc" but the feature is disabled. Portions of cache used for allocation of I/O traffic cannot be configured.h](j- )}(h "disabled":h]h“disabled”:}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhjV ubj= )}(hhh]j)}(hResource supports "io_alloc" but the feature is disabled. Portions of cache used for allocation of I/O traffic cannot be configured.h]hResource supports “io_alloc” but the feature is disabled. Portions of cache used for allocation of I/O traffic cannot be configured.}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjh ubah}(h]h ]h"]h$]h&]uh1j< hjV ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjS ubj' )}(hg"enabled": Portions of cache used for allocation of I/O traffic can be configured using "io_alloc_cbm".h](j- )}(h "enabled":h]h“enabled”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(h\Portions of cache used for allocation of I/O traffic can be configured using "io_alloc_cbm".h]h`Portions of cache used for allocation of I/O traffic can be configured using “io_alloc_cbm”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjS ubj' )}(h:"not supported": Support not available for this resource. h](j- )}(h"not supported":h]h“not supported”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj ubj= )}(hhh]j)}(h(Support not available for this resource.h]h(Support not available for this resource.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubah}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjS ubeh}(h]h ]h"]h$]h&]uh1j! hjO ubah}(h]h ]h"]h$]h&]uh1jQ hhhKhj> ubj)}(hEThe feature can be modified by writing to the interface, for example:h]hEThe feature can be modified by writing to the interface, for example:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubj)}(h To enable::h]h To enable:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubj )}(h+# echo 1 > /sys/fs/resctrl/info/L3/io_alloch]h+# echo 1 > /sys/fs/resctrl/info/L3/io_alloc}hj sbah}(h]h ]h"]h$]h&]hhuh1j hhhKhj> ubj)}(h To disable::h]h To disable:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubj )}(h+# echo 0 > /sys/fs/resctrl/info/L3/io_alloch]h+# echo 0 > /sys/fs/resctrl/info/L3/io_alloc}hj'sbah}(h]h ]h"]h$]h&]hhuh1j hhhKhj> ubj)}(hThe underlying implementation may reduce resources available to general (CPU) cache allocation. See architecture specific notes below. Depending on usage requirements the feature can be enabled or disabled.h]hThe underlying implementation may reduce resources available to general (CPU) cache allocation. See architecture specific notes below. Depending on usage requirements the feature can be enabled or disabled.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubj)}(hX0On AMD systems, io_alloc feature is supported by the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for io_alloc is the highest CLOSID supported by the resource. When io_alloc is enabled, the highest CLOSID is dedicated to io_alloc and no longer available for general (CPU) cache allocation. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (CDP_CODE), making this CLOSID no longer available for general (CPU) cache allocation for both the CDP_CODE and CDP_DATA resources.h]hX0On AMD systems, io_alloc feature is supported by the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for io_alloc is the highest CLOSID supported by the resource. When io_alloc is enabled, the highest CLOSID is dedicated to io_alloc and no longer available for general (CPU) cache allocation. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (CDP_CODE), making this CLOSID no longer available for general (CPU) cache allocation for both the CDP_CODE and CDP_DATA resources.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj> ubeh}(h]h ]h"]h$]h&]uh1j< hj, ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhja hhubj' )}(hX"io_alloc_cbm": Capacity bitmasks that describe the portions of cache instances to which I/O traffic from supported I/O devices are routed when "io_alloc" is enabled. CBMs are displayed in the following format: =;=;... Example:: # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=ffff CBMs can be configured by writing to the interface. Example:: # echo 1=ff > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=00ff # echo "0=ff;1=f" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=00ff;1=000f An ID of "*" configures all domains with the provided CBM. Example on a system that does not require a minimum number of consecutive bits in the mask:: # echo "*=0" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=0;1=0 When CDP is enabled "io_alloc_cbm" associated with the CDP_DATA and CDP_CODE resources may reflect the same values. For example, values read from and written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by /sys/fs/resctrl/info/L3CODE/io_alloc_cbm and vice versa. h](j- )}(h"io_alloc_cbm":h]h“io_alloc_cbm”:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhj]ubj= )}(hhh](j)}(hCapacity bitmasks that describe the portions of cache instances to which I/O traffic from supported I/O devices are routed when "io_alloc" is enabled.h]hCapacity bitmasks that describe the portions of cache instances to which I/O traffic from supported I/O devices are routed when “io_alloc” is enabled.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj)}(h+CBMs are displayed in the following format:h]h+CBMs are displayed in the following format:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubjR )}(h(=;=;... h]j)}(h'=;=;...h]h'=;=;...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jQ hhhKhjoubj)}(h Example::h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj )}(h8# cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=ffffh]h8# cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=ffff}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhKhjoubj)}(h3CBMs can be configured by writing to the interface.h]h3CBMs can be configured by writing to the interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj)}(h Example::h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj )}(h# echo 1=ff > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=00ff # echo "0=ff;1=f" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=00ff;1=000fh]h# echo 1=ff > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=ffff;1=00ff # echo "0=ff;1=f" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=00ff;1=000f}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhKhjoubj)}(h:An ID of "*" configures all domains with the provided CBM.h]h>An ID of “*” configures all domains with the provided CBM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj)}(h\Example on a system that does not require a minimum number of consecutive bits in the mask::h]h[Example on a system that does not require a minimum number of consecutive bits in the mask:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubj )}(hf# echo "*=0" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=0;1=0h]hf# echo "*=0" > /sys/fs/resctrl/info/L3/io_alloc_cbm # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=0;1=0}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhKhjoubj)}(hXWhen CDP is enabled "io_alloc_cbm" associated with the CDP_DATA and CDP_CODE resources may reflect the same values. For example, values read from and written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by /sys/fs/resctrl/info/L3CODE/io_alloc_cbm and vice versa.h]hXWhen CDP is enabled “io_alloc_cbm” associated with the CDP_DATA and CDP_CODE resources may reflect the same values. For example, values read from and written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by /sys/fs/resctrl/info/L3CODE/io_alloc_cbm and vice versa.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjoubeh}(h]h ]h"]h$]h&]uh1j< hj]ubeh}(h]h ]h"]h$]h&]uh1j& hhhKhja hhubeh}(h]h ]h"]h$]h&]uh1j! hj hhhhhNubj)}(hZMemory bandwidth(MB) subdirectory contains the following files with respect to allocation:h]hZMemory bandwidth(MB) subdirectory contains the following files with respect to allocation:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj" )}(hhh](j' )}(hQ"min_bandwidth": The minimum memory bandwidth percentage which user can request. h](j- )}(h"min_bandwidth":h]h“min_bandwidth”:}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhjGubj= )}(hhh]j)}(h?The minimum memory bandwidth percentage which user can request.h]h?The minimum memory bandwidth percentage which user can request.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjYubah}(h]h ]h"]h$]h&]uh1j< hjGubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjDubj' )}(hX"bandwidth_gran": The granularity in which the memory bandwidth percentage is allocated. The allocated b/w percentage is rounded off to the next control step available on the hardware. The available bandwidth control steps are: min_bandwidth + N * bandwidth_gran. h](j- )}(h"bandwidth_gran":h]h“bandwidth_gran”:}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhjvubj= )}(hhh]j)}(hThe granularity in which the memory bandwidth percentage is allocated. The allocated b/w percentage is rounded off to the next control step available on the hardware. The available bandwidth control steps are: min_bandwidth + N * bandwidth_gran.h]hThe granularity in which the memory bandwidth percentage is allocated. The allocated b/w percentage is rounded off to the next control step available on the hardware. The available bandwidth control steps are: min_bandwidth + N * bandwidth_gran.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1j< hjvubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjDhhubj' )}(ho"delay_linear": Indicates if the delay scale is linear or non-linear. This field is purely informational only. h](j- )}(h"delay_linear":h]h“delay_linear”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhKhjubj= )}(hhh]j)}(h^Indicates if the delay scale is linear or non-linear. This field is purely informational only.h]h^Indicates if the delay scale is linear or non-linear. This field is purely informational only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhKhjDhhubj' )}(hXn"thread_throttle_mode": Indicator on Intel systems of how tasks running on threads of a physical core are throttled in cases where they request different memory bandwidth percentages: "max": the smallest percentage is applied to all threads "per-thread": bandwidth percentages are directly applied to the threads running on the core h](j- )}(h"thread_throttle_mode":h]h“thread_throttle_mode”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hIndicator on Intel systems of how tasks running on threads of a physical core are throttled in cases where they request different memory bandwidth percentages:h]hIndicator on Intel systems of how tasks running on threads of a physical core are throttled in cases where they request different memory bandwidth percentages:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj" )}(hhh](j' )}(h8"max": the smallest percentage is applied to all threadsh](j- )}(h"max":h]h “max”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh]j)}(h1the smallest percentage is applied to all threadsh]h1the smallest percentage is applied to all threads}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubj' )}(h\"per-thread": bandwidth percentages are directly applied to the threads running on the core h](j- )}(h "per-thread":h]h“per-thread”:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj)ubj= )}(hhh]j)}(hMbandwidth percentages are directly applied to the threads running on the coreh]hMbandwidth percentages are directly applied to the threads running on the core}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj;ubah}(h]h ]h"]h$]h&]uh1j< hj)ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubeh}(h]h ]h"]h$]h&]uh1j! hjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjDhhubeh}(h]h ]h"]h$]h&]uh1j! hj hhhhhNubj)}(h[If L3 monitoring is available there will be an "L3_MON" directory with the following files:h]h_If L3 monitoring is available there will be an “L3_MON” directory with the following files:}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj" )}(hhh](j' )}(hQ"num_rmids": The number of RMIDs supported by hardware for L3 monitoring events. h](j- )}(h "num_rmids":h]h“num_rmids”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhM hjubj= )}(hhh]j)}(hCThe number of RMIDs supported by hardware for L3 monitoring events.h]hCThe number of RMIDs supported by hardware for L3 monitoring events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhM hj~ubj' )}(hX)"mon_features": Lists the monitoring events if monitoring is enabled for the resource. Example:: # cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytes If the system supports Bandwidth Monitoring Event Configuration (BMEC), then the bandwidth events will be configurable. The output will be:: # cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_bytes_config mbm_local_bytes mbm_local_bytes_config h](j- )}(h"mon_features":h]h“mon_features”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhM!hjubj= )}(hhh](j)}(hPLists the monitoring events if monitoring is enabled for the resource. Example::h]hOLists the monitoring events if monitoring is enabled for the resource. Example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h\# cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytesh]h\# cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_local_bytes}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubj)}(hIf the system supports Bandwidth Monitoring Event Configuration (BMEC), then the bandwidth events will be configurable. The output will be::h]hIf the system supports Bandwidth Monitoring Event Configuration (BMEC), then the bandwidth events will be configurable. The output will be:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h# cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_bytes_config mbm_local_bytes mbm_local_bytes_configh]h# cat /sys/fs/resctrl/info/L3_MON/mon_features llc_occupancy mbm_total_bytes mbm_total_bytes_config mbm_local_bytes mbm_local_bytes_config}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhM!hj~hhubj' )}(hX@ "mbm_total_bytes_config", "mbm_local_bytes_config": Read/write files containing the configuration for the mbm_total_bytes and mbm_local_bytes events, respectively, when the Bandwidth Monitoring Event Configuration (BMEC) feature is supported. The event configuration settings are domain specific and affect all the CPUs in the domain. When either event configuration is changed, the bandwidth counters for all RMIDs of both events (mbm_total_bytes as well as mbm_local_bytes) are cleared for that domain. The next read for every RMID will report "Unavailable" and subsequent reads will report the valid value. Following are the types of events supported: ==== ======================================================== Bits Description ==== ======================================================== 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain ==== ======================================================== By default, the mbm_total_bytes configuration is set to 0x7f to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. Examples: * To view the current configuration:: :: # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x7f;1=0x7f;2=0x7f;3=0x7f # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x15;1=0x15;3=0x15;4=0x15 * To change the mbm_total_bytes to count only reads on domain 0, the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary (in hexadecimal 0x33): :: # echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x33;1=0x7f;2=0x7f;3=0x7f * To change the mbm_local_bytes to count all the slow memory reads on domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b in binary (in hexadecimal 0x30): :: # echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15 h](j- )}(h3"mbm_total_bytes_config", "mbm_local_bytes_config":h]h;“mbm_total_bytes_config”, “mbm_local_bytes_config”:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhM]hj ubj= )}(hhh](j)}(hX-Read/write files containing the configuration for the mbm_total_bytes and mbm_local_bytes events, respectively, when the Bandwidth Monitoring Event Configuration (BMEC) feature is supported. The event configuration settings are domain specific and affect all the CPUs in the domain. When either event configuration is changed, the bandwidth counters for all RMIDs of both events (mbm_total_bytes as well as mbm_local_bytes) are cleared for that domain. The next read for every RMID will report "Unavailable" and subsequent reads will report the valid value.h]hX1Read/write files containing the configuration for the mbm_total_bytes and mbm_local_bytes events, respectively, when the Bandwidth Monitoring Event Configuration (BMEC) feature is supported. The event configuration settings are domain specific and affect all the CPUs in the domain. When either event configuration is changed, the bandwidth counters for all RMIDs of both events (mbm_total_bytes as well as mbm_local_bytes) are cleared for that domain. The next read for every RMID will report “Unavailable” and subsequent reads will report the valid value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM$hjubj)}(h,Following are the types of events supported:h]h,Following are the types of events supported:}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM.hjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj=ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK8uh1jhj=ubhthead)}(hhh]j)}(hhh](j)}(hhh]j)}(hBitsh]hBits}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM1hj\ubah}(h]h ]h"]h$]h&]uh1jhjYubj)}(hhh]j)}(h Descriptionh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM1hjsubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jThj=ubj)}(hhh](j)}(hhh](j)}(hhh]j)}(h6h]h6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h8Dirty Victims from the QOS domain to all types of memoryh]h8Dirty Victims from the QOS domain to all types of memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h5h]h5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h1Reads to slow memory in the non-local NUMA domainh]h1Reads to slow memory in the non-local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h4h]h4}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM5hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h-Reads to slow memory in the local NUMA domainh]h-Reads to slow memory in the local NUMA domain}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM5hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h3h]h3}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM6hjAubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]j)}(h,Non-temporal writes to non-local NUMA domainh]h,Non-temporal writes to non-local NUMA domain}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM6hjXubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h2h]h2}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM7hjxubah}(h]h ]h"]h$]h&]uh1jhjuubj)}(hhh]j)}(h(Non-temporal writes to local NUMA domainh]h(Non-temporal writes to local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM7hjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM8hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h,Reads to memory in the non-local NUMA domainh]h,Reads to memory in the non-local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h0h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h(Reads to memory in the local NUMA domainh]h(Reads to memory in the local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM9hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]colsKuh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hBy default, the mbm_total_bytes configuration is set to 0x7f to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events.h]hBy default, the mbm_total_bytes configuration is set to 0x7f to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM<hjubj)}(h Examples:h]h Examples:}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM@hjubj)}(hhh](j)}(hTo view the current configuration:: :: # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x7f;1=0x7f;2=0x7f;3=0x7f # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x15;1=0x15;3=0x15;4=0x15 h](j)}(h&To view the current configuration:: ::h]h#To view the current configuration::}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMBhjLubj )}(h# cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x7f;1=0x7f;2=0x7f;3=0x7f # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x15;1=0x15;3=0x15;4=0x15h]h# cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x7f;1=0x7f;2=0x7f;3=0x7f # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x15;1=0x15;3=0x15;4=0x15}hj^sbah}(h]h ]h"]h$]h&]hhuh1j hhhMEhjLubeh}(h]h ]h"]h$]h&]uh1jhjIubj)}(hX?To change the mbm_total_bytes to count only reads on domain 0, the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary (in hexadecimal 0x33): :: # echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x33;1=0x7f;2=0x7f;3=0x7f h](j)}(hTo change the mbm_total_bytes to count only reads on domain 0, the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary (in hexadecimal 0x33): ::h]hTo change the mbm_total_bytes to count only reads on domain 0, the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary (in hexadecimal 0x33):}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMKhjrubj )}(h# echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x33;1=0x7f;2=0x7f;3=0x7fh]h# echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config 0=0x33;1=0x7f;2=0x7f;3=0x7f}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMPhjrubeh}(h]h ]h"]h$]h&]uh1jhjIubj)}(hXUTo change the mbm_local_bytes to count all the slow memory reads on domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b in binary (in hexadecimal 0x30): :: # echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15 h](j)}(hTo change the mbm_local_bytes to count all the slow memory reads on domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b in binary (in hexadecimal 0x30): ::h]hTo change the mbm_local_bytes to count all the slow memory reads on domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b in binary (in hexadecimal 0x30):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMUhjubj )}(h# echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15h]h# echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMZhjubeh}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]jU*uh1jhhhMBhjubeh}(h]h ]h"]h$]h&]uh1j< hj ubeh}(h]h ]h"]h$]h&]uh1j& hhhM]hj~hhubj' )}(hXC"mbm_assign_mode": The supported counter assignment modes. The enclosed brackets indicate which mode is enabled. The MBM events associated with counters may reset when "mbm_assign_mode" is changed. :: # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] default "mbm_event": mbm_event mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Each event within a resctrl group can be assigned independently. In this mode, a monitoring event can only accumulate data while it is backed by a hardware counter. Use "mbm_L3_assignments" found in each CTRL_MON and MON group to specify which of the events should have a counter assigned. The number of counters available is described in the "num_mbm_cntrs" file. Changing the mode may cause all counters on the resource to reset. Moving to mbm_event counter assignment mode requires users to assign the counters to the events. Otherwise, the MBM event counters will return 'Unassigned' when read. The mode is beneficial for AMD platforms that support more CTRL_MON and MON groups than available hardware counters. By default, this feature is enabled on AMD platforms with the ABMC (Assignable Bandwidth Monitoring Counters) capability, ensuring counters remain assigned even when the corresponding RMID is not actively used by any processor. "default": In default mode, resctrl assumes there is a hardware counter for each event within every CTRL_MON and MON group. On AMD platforms, it is recommended to use the mbm_event mode, if supported, to prevent reset of MBM events between reads resulting from hardware re-allocating counters. This can result in misleading values or display "Unavailable" if no counter is assigned to the event. * To enable "mbm_event" counter assignment mode: :: # echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode * To enable "default" monitoring mode: :: # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode h](j- )}(h"mbm_assign_mode":h]h“mbm_assign_mode”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hThe supported counter assignment modes. The enclosed brackets indicate which mode is enabled. The MBM events associated with counters may reset when "mbm_assign_mode" is changed. ::h]hThe supported counter assignment modes. The enclosed brackets indicate which mode is enabled. The MBM events associated with counters may reset when “mbm_assign_mode” is changed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM`hjubj )}(hE# cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] defaulth]hE# cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] default}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMehjubj)}(h "mbm_event":h]h“mbm_event”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMihjubj)}(hX/mbm_event mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Each event within a resctrl group can be assigned independently.h]hX/mbm_event mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Each event within a resctrl group can be assigned independently.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMkhjubj)}(hXnIn this mode, a monitoring event can only accumulate data while it is backed by a hardware counter. Use "mbm_L3_assignments" found in each CTRL_MON and MON group to specify which of the events should have a counter assigned. The number of counters available is described in the "num_mbm_cntrs" file. Changing the mode may cause all counters on the resource to reset.h]hXvIn this mode, a monitoring event can only accumulate data while it is backed by a hardware counter. Use “mbm_L3_assignments” found in each CTRL_MON and MON group to specify which of the events should have a counter assigned. The number of counters available is described in the “num_mbm_cntrs” file. Changing the mode may cause all counters on the resource to reset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMphjubj)}(hMoving to mbm_event counter assignment mode requires users to assign the counters to the events. Otherwise, the MBM event counters will return 'Unassigned' when read.h]hMoving to mbm_event counter assignment mode requires users to assign the counters to the events. Otherwise, the MBM event counters will return ‘Unassigned’ when read.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMvhjubj)}(hXXThe mode is beneficial for AMD platforms that support more CTRL_MON and MON groups than available hardware counters. By default, this feature is enabled on AMD platforms with the ABMC (Assignable Bandwidth Monitoring Counters) capability, ensuring counters remain assigned even when the corresponding RMID is not actively used by any processor.h]hXXThe mode is beneficial for AMD platforms that support more CTRL_MON and MON groups than available hardware counters. By default, this feature is enabled on AMD platforms with the ABMC (Assignable Bandwidth Monitoring Counters) capability, ensuring counters remain assigned even when the corresponding RMID is not actively used by any processor.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMyhjubj)}(h "default":h]h“default”:}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hXIn default mode, resctrl assumes there is a hardware counter for each event within every CTRL_MON and MON group. On AMD platforms, it is recommended to use the mbm_event mode, if supported, to prevent reset of MBM events between reads resulting from hardware re-allocating counters. This can result in misleading values or display "Unavailable" if no counter is assigned to the event.h]hXIn default mode, resctrl assumes there is a hardware counter for each event within every CTRL_MON and MON group. On AMD platforms, it is recommended to use the mbm_event mode, if supported, to prevent reset of MBM events between reads resulting from hardware re-allocating counters. This can result in misleading values or display “Unavailable” if no counter is assigned to the event.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh](j)}(hvTo enable "mbm_event" counter assignment mode: :: # echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode h](j)}(h1To enable "mbm_event" counter assignment mode: ::h]h2To enable “mbm_event” counter assignment mode:}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjgubj )}(h@# echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_modeh]h@# echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode}hjysbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjgubeh}(h]h ]h"]h$]h&]uh1jhjdubj)}(hjTo enable "default" monitoring mode: :: # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode h](j)}(h'To enable "default" monitoring mode: ::h]h(To enable “default” monitoring mode:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h># echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_modeh]h># echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]jUjuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubj' )}(hXB"num_mbm_cntrs": The maximum number of counters (total of available and assigned counters) in each domain when the system supports mbm_event mode. For example, on a system with maximum of 32 memory bandwidth monitoring counters in each of its L3 domains: :: # cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs 0=32;1=32 h](j- )}(h"num_mbm_cntrs":h]h“num_mbm_cntrs”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hThe maximum number of counters (total of available and assigned counters) in each domain when the system supports mbm_event mode.h]hThe maximum number of counters (total of available and assigned counters) in each domain when the system supports mbm_event mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hnFor example, on a system with maximum of 32 memory bandwidth monitoring counters in each of its L3 domains: ::h]hkFor example, on a system with maximum of 32 memory bandwidth monitoring counters in each of its L3 domains:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h9# cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs 0=32;1=32h]h9# cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs 0=32;1=32}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubj' )}(hX2"available_mbm_cntrs": The number of counters available for assignment in each domain when mbm_event mode is enabled on the system. For example, on a system with 30 available [hardware] assignable counters in each of its L3 domains: :: # cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs 0=30;1=30 h](j- )}(h"available_mbm_cntrs":h]h“available_mbm_cntrs”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hlThe number of counters available for assignment in each domain when mbm_event mode is enabled on the system.h]hlThe number of counters available for assignment in each domain when mbm_event mode is enabled on the system.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"ubj)}(hgFor example, on a system with 30 available [hardware] assignable counters in each of its L3 domains: ::h]hdFor example, on a system with 30 available [hardware] assignable counters in each of its L3 domains:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"ubj )}(h?# cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs 0=30;1=30h]h?# cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs 0=30;1=30}hjAsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj"ubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubj' )}(hXT"event_configs": Directory that exists when "mbm_event" counter assignment mode is supported. Contains a sub-directory for each MBM event that can be assigned to a counter. Two MBM events are supported by default: mbm_local_bytes and mbm_total_bytes. Each MBM event's sub-directory contains a file named "event_filter" that is used to view and (if writable) modify which memory transactions the MBM event is configured with. The file is accessible only when "mbm_event" counter assignment mode is enabled. List of memory transaction types supported: ========================== ======================================================== Name Description ========================== ======================================================== dirty_victim_writes_all Dirty Victims from the QOS domain to all types of memory remote_reads_slow_memory Reads to slow memory in the non-local NUMA domain local_reads_slow_memory Reads to slow memory in the local NUMA domain remote_non_temporal_writes Non-temporal writes to non-local NUMA domain local_non_temporal_writes Non-temporal writes to local NUMA domain remote_reads Reads to memory in the non-local NUMA domain local_reads Reads to memory in the local NUMA domain ========================== ======================================================== For example:: # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory The memory transactions the MBM event is configured with can be changed if "event_filter" is writable. For example:: # echo "local_reads, local_non_temporal_writes" > /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,local_non_temporal_writes h](j- )}(h"event_configs":h]h“event_configs”:}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj[ubj= )}(hhh](j)}(hDirectory that exists when "mbm_event" counter assignment mode is supported. Contains a sub-directory for each MBM event that can be assigned to a counter.h]hDirectory that exists when “mbm_event” counter assignment mode is supported. Contains a sub-directory for each MBM event that can be assigned to a counter.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj)}(hXLTwo MBM events are supported by default: mbm_local_bytes and mbm_total_bytes. Each MBM event's sub-directory contains a file named "event_filter" that is used to view and (if writable) modify which memory transactions the MBM event is configured with. The file is accessible only when "mbm_event" counter assignment mode is enabled.h]hXVTwo MBM events are supported by default: mbm_local_bytes and mbm_total_bytes. Each MBM event’s sub-directory contains a file named “event_filter” that is used to view and (if writable) modify which memory transactions the MBM event is configured with. The file is accessible only when “mbm_event” counter assignment mode is enabled.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj)}(h+List of memory transaction types supported:h]h+List of memory transaction types supported:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK8uh1jhjubjU)}(hhh]j)}(hhh](j)}(hhh]j)}(hNameh]hName}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jThjubj)}(hhh](j)}(hhh](j)}(hhh]j)}(hdirty_victim_writes_allh]hdirty_victim_writes_all}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h8Dirty Victims from the QOS domain to all types of memoryh]h8Dirty Victims from the QOS domain to all types of memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(hremote_reads_slow_memoryh]hremote_reads_slow_memory}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh]j)}(h1Reads to slow memory in the non-local NUMA domainh]h1Reads to slow memory in the non-local NUMA domain}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(hlocal_reads_slow_memoryh]hlocal_reads_slow_memory}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]j)}(h-Reads to slow memory in the local NUMA domainh]h-Reads to slow memory in the local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(hremote_non_temporal_writesh]hremote_non_temporal_writes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h,Non-temporal writes to non-local NUMA domainh]h,Non-temporal writes to non-local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(hlocal_non_temporal_writesh]hlocal_non_temporal_writes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(h(Non-temporal writes to local NUMA domainh]h(Non-temporal writes to local NUMA domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h remote_readsh]h remote_reads}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]j)}(h,Reads to memory in the non-local NUMA domainh]h,Reads to memory in the non-local NUMA domain}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]j)}(h local_readsh]h local_reads}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhjAubj)}(hhh]j)}(h(Reads to memory in the local NUMA domainh]h(Reads to memory in the local NUMA domain}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjmubj)}(h For example::h]h For example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj )}(hXp# cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memoryh]hXp# cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjmubj)}(hfThe memory transactions the MBM event is configured with can be changed if "event_filter" is writable.h]hjThe memory transactions the MBM event is configured with can be changed if “event_filter” is writable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj)}(h For example::h]h For example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjmubj )}(h# echo "local_reads, local_non_temporal_writes" > /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,local_non_temporal_writesh]h# echo "local_reads, local_non_temporal_writes" > /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,local_non_temporal_writes}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjmubeh}(h]h ]h"]h$]h&]uh1j< hj[ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubj' )}(hX"mbm_assign_on_mkdir": Exists when "mbm_event" counter assignment mode is supported. Accessible only when "mbm_event" counter assignment mode is enabled. Determines if a counter will automatically be assigned to an RMID, MBM event pair when its associated monitor group is created via mkdir. Enabled by default on boot, also when switched from "default" mode to "mbm_event" counter assignment mode. Users can disable this capability by writing to the interface. "0": Auto assignment is disabled. "1": Auto assignment is enabled. Automatic counter assignment is done with best effort. If auto assignment is enabled but there are not enough available counters then monitor group creation could succeed while one or more events belonging to the group may not have a counter assigned in all domains. Consult mbm_L3_assignments for counter assignment states of the new groups. Example:: # echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir 0 h](j- )}(h"mbm_assign_on_mkdir":h]h“mbm_assign_on_mkdir”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hExists when "mbm_event" counter assignment mode is supported. Accessible only when "mbm_event" counter assignment mode is enabled.h]hExists when “mbm_event” counter assignment mode is supported. Accessible only when “mbm_event” counter assignment mode is enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hX3Determines if a counter will automatically be assigned to an RMID, MBM event pair when its associated monitor group is created via mkdir. Enabled by default on boot, also when switched from "default" mode to "mbm_event" counter assignment mode. Users can disable this capability by writing to the interface.h]hX;Determines if a counter will automatically be assigned to an RMID, MBM event pair when its associated monitor group is created via mkdir. Enabled by default on boot, also when switched from “default” mode to “mbm_event” counter assignment mode. Users can disable this capability by writing to the interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj" )}(hhh](j' )}(h!"0": Auto assignment is disabled.h](j- )}(h"0":h]h“0”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh]j)}(hAuto assignment is disabled.h]hAuto assignment is disabled.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj#ubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubj' )}(h!"1": Auto assignment is enabled. h](j- )}(h"1":h]h“1”:}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj@ubj= )}(hhh]j)}(hAuto assignment is enabled.h]hAuto assignment is enabled.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjRubah}(h]h ]h"]h$]h&]uh1j< hj@ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubeh}(h]h ]h"]h$]h&]uh1j! hjubj)}(hXVAutomatic counter assignment is done with best effort. If auto assignment is enabled but there are not enough available counters then monitor group creation could succeed while one or more events belonging to the group may not have a counter assigned in all domains. Consult mbm_L3_assignments for counter assignment states of the new groups.h]hXVAutomatic counter assignment is done with best effort. If auto assignment is enabled but there are not enough available counters then monitor group creation could succeed while one or more events belonging to the group may not have a counter assigned in all domains. Consult mbm_L3_assignments for counter assignment states of the new groups.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(h Example::h]hExample:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(hr# echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir 0h]hr# echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir 0}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubj' )}(h"max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy counter can be considered for reuse. h](j- )}(h"max_threshold_occupancy":h]h“max_threshold_occupancy”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh]j)}(hRead/write file provides the largest value (in bytes) at which a previously used LLC_occupancy counter can be considered for reuse.h]hRead/write file provides the largest value (in bytes) at which a previously used LLC_occupancy counter can be considered for reuse.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj~hhubeh}(h]h ]h"]h$]h&]uh1j! hj hhhhhNubj)}(hgIf telemetry monitoring is available there will be a "PERF_PKG_MON" directory with the following files:h]hkIf telemetry monitoring is available there will be a “PERF_PKG_MON” directory with the following files:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj" )}(hhh](j' )}(hXq"num_rmids": The number of RMIDs for telemetry monitoring events. On Intel resctrl will not enable telemetry events if the number of RMIDs that can be tracked concurrently is lower than the total number of RMIDs supported. Telemetry events can be force-enabled with the "rdt=" kernel parameter, but this may reduce the number of monitoring groups that can be created. h](j- )}(h "num_rmids":h]h“num_rmids”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(h4The number of RMIDs for telemetry monitoring events.h]h4The number of RMIDs for telemetry monitoring events.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hX-On Intel resctrl will not enable telemetry events if the number of RMIDs that can be tracked concurrently is lower than the total number of RMIDs supported. Telemetry events can be force-enabled with the "rdt=" kernel parameter, but this may reduce the number of monitoring groups that can be created.h]hX1On Intel resctrl will not enable telemetry events if the number of RMIDs that can be tracked concurrently is lower than the total number of RMIDs supported. Telemetry events can be force-enabled with the “rdt=” kernel parameter, but this may reduce the number of monitoring groups that can be created.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubj' )}(hW"mon_features": Lists the telemetry monitoring events that are enabled on this system. h](j- )}(h"mon_features":h]h“mon_features”:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj.ubj= )}(hhh]j)}(hFLists the telemetry monitoring events that are enabled on this system.h]hFLists the telemetry monitoring events that are enabled on this system.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj@ubah}(h]h ]h"]h$]h&]uh1j< hj.ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjhhubeh}(h]h ]h"]h$]h&]uh1j! hj hhhhhNubj)}(hThe upper bound for how many "CTRL_MON" + "MON" can be created is the smaller of the L3_MON and PERF_PKG_MON "num_rmids" values.h]hThe upper bound for how many “CTRL_MON” + “MON” can be created is the smaller of the L3_MON and PERF_PKG_MON “num_rmids” values.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hXFinally, in the top level of the "info" directory there is a file named "last_cmd_status". This is reset with every "command" issued via the file system (making new directories or writing to any of the control files). If the command was successful, it will read as "ok". If the command failed, it will provide more information that can be conveyed in the error returns from file operations. E.g. ::h]hXFinally, in the top level of the “info” directory there is a file named “last_cmd_status”. This is reset with every “command” issued via the file system (making new directories or writing to any of the control files). If the command was successful, it will read as “ok”. If the command failed, it will provide more information that can be conveyed in the error returns from file operations. E.g.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj )}(h# echo L3:0=f7 > schemata bash: echo: write error: Invalid argument # cat info/last_cmd_status mask f7 has non-consecutive 1-bitsh]h# echo L3:0=f7 > schemata bash: echo: write error: Invalid argument # cat info/last_cmd_status mask f7 has non-consecutive 1-bits}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhM hj hhubeh}(h]info-directoryah ]h"]info directoryah$]h&]uh1j[hj]hhhhhKFubj\)}(hhh](ja)}(h!Resource alloc and monitor groupsh]h!Resource alloc and monitor groups}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMubj)}(hResource groups are represented as directories in the resctrl file system. The default group is the root directory which, immediately after mounting, owns all the tasks and cpus in the system and can make full use of all resources.h]hResource groups are represented as directories in the resctrl file system. The default group is the root directory which, immediately after mounting, owns all the tasks and cpus in the system and can make full use of all resources.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hX On a system with RDT control features additional directories can be created in the root directory that specify different amounts of each resource (see "schemata" below). The root and these additional top level directories are referred to as "CTRL_MON" groups below.h]hXOn a system with RDT control features additional directories can be created in the root directory that specify different amounts of each resource (see “schemata” below). The root and these additional top level directories are referred to as “CTRL_MON” groups below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hX.On a system with RDT monitoring the root directory and other top level directories contain a directory named "mon_groups" in which additional directories can be created to monitor subsets of tasks in the CTRL_MON group that is their ancestor. These are called "MON" groups in the rest of this document.h]hX6On a system with RDT monitoring the root directory and other top level directories contain a directory named “mon_groups” in which additional directories can be created to monitor subsets of tasks in the CTRL_MON group that is their ancestor. These are called “MON” groups in the rest of this document.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hRemoving a directory will move all tasks and cpus owned by the group it represents to the parent. Removing one of the created CTRL_MON groups will automatically remove all MON groups below it.h]hRemoving a directory will move all tasks and cpus owned by the group it represents to the parent. Removing one of the created CTRL_MON groups will automatically remove all MON groups below it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM%hjhhubj)}(hXgMoving MON group directories to a new parent CTRL_MON group is supported for the purpose of changing the resource allocations of a MON group without impacting its monitoring data or assigned tasks. This operation is not allowed for MON groups which monitor CPUs. No other move operation is currently allowed other than simply renaming a CTRL_MON or MON group.h]hXgMoving MON group directories to a new parent CTRL_MON group is supported for the purpose of changing the resource allocations of a MON group without impacting its monitoring data or assigned tasks. This operation is not allowed for MON groups which monitor CPUs. No other move operation is currently allowed other than simply renaming a CTRL_MON or MON group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM)hjhhubj)}(h'All groups contain the following files:h]h'All groups contain the following files:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM0hjhhubj" )}(hhh](j' )}(hXa"tasks": Reading this file shows the list of all tasks that belong to this group. Writing a task id to the file will add a task to the group. Multiple tasks can be added by separating the task ids with commas. Tasks will be assigned sequentially. Multiple failures are not supported. A single failure encountered while attempting to assign a task will cause the operation to abort and already added tasks before the failure will remain in the group. Failures will be logged to /sys/fs/resctrl/info/last_cmd_status. If the group is a CTRL_MON group the task is removed from whichever previous CTRL_MON group owned the task and also from any MON group that owned the task. If the group is a MON group, then the task must already belong to the CTRL_MON parent of this group. The task is removed from any previous MON group. When writing to this file, a task id of 0 is interpreted as the task id of the currently running task. On reading the file, a task id of 0 will never be shown and there is no representation of the idle tasks. Instead, a CPU's idle task is always considered as a member of the group owning the CPU. h](j- )}(h"tasks":h]h “tasks”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMFhjubj= )}(hhh](j)}(hXReading this file shows the list of all tasks that belong to this group. Writing a task id to the file will add a task to the group. Multiple tasks can be added by separating the task ids with commas. Tasks will be assigned sequentially. Multiple failures are not supported. A single failure encountered while attempting to assign a task will cause the operation to abort and already added tasks before the failure will remain in the group. Failures will be logged to /sys/fs/resctrl/info/last_cmd_status.h]hXReading this file shows the list of all tasks that belong to this group. Writing a task id to the file will add a task to the group. Multiple tasks can be added by separating the task ids with commas. Tasks will be assigned sequentially. Multiple failures are not supported. A single failure encountered while attempting to assign a task will cause the operation to abort and already added tasks before the failure will remain in the group. Failures will be logged to /sys/fs/resctrl/info/last_cmd_status.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM3hjubj)}(hX1If the group is a CTRL_MON group the task is removed from whichever previous CTRL_MON group owned the task and also from any MON group that owned the task. If the group is a MON group, then the task must already belong to the CTRL_MON parent of this group. The task is removed from any previous MON group.h]hX1If the group is a CTRL_MON group the task is removed from whichever previous CTRL_MON group owned the task and also from any MON group that owned the task. If the group is a MON group, then the task must already belong to the CTRL_MON parent of this group. The task is removed from any previous MON group.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM<hjubj)}(hX)When writing to this file, a task id of 0 is interpreted as the task id of the currently running task. On reading the file, a task id of 0 will never be shown and there is no representation of the idle tasks. Instead, a CPU's idle task is always considered as a member of the group owning the CPU.h]hX+When writing to this file, a task id of 0 is interpreted as the task id of the currently running task. On reading the file, a task id of 0 will never be shown and there is no representation of the idle tasks. Instead, a CPU’s idle task is always considered as a member of the group owning the CPU.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMBhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMFhjubj' )}(hX"cpus": Reading this file shows a bitmask of the logical CPUs owned by this group. Writing a mask to this file will add and remove CPUs to/from this group. As with the tasks file a hierarchy is maintained where MON groups may only include CPUs owned by the parent CTRL_MON group. When the resource group is in pseudo-locked mode this file will only be readable, reflecting the CPUs associated with the pseudo-locked region. h](j- )}(h"cpus":h]h “cpus”:}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMQhjHubj= )}(hhh]j)}(hXReading this file shows a bitmask of the logical CPUs owned by this group. Writing a mask to this file will add and remove CPUs to/from this group. As with the tasks file a hierarchy is maintained where MON groups may only include CPUs owned by the parent CTRL_MON group. When the resource group is in pseudo-locked mode this file will only be readable, reflecting the CPUs associated with the pseudo-locked region.h]hXReading this file shows a bitmask of the logical CPUs owned by this group. Writing a mask to this file will add and remove CPUs to/from this group. As with the tasks file a hierarchy is maintained where MON groups may only include CPUs owned by the parent CTRL_MON group. When the resource group is in pseudo-locked mode this file will only be readable, reflecting the CPUs associated with the pseudo-locked region.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMIhjZubah}(h]h ]h"]h$]h&]uh1j< hjHubeh}(h]h ]h"]h$]h&]uh1j& hhhMQhjhhubj' )}(hO"cpus_list": Just like "cpus", only using ranges of CPUs instead of bitmasks. h](j- )}(h "cpus_list":h]h“cpus_list”:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMUhjwubj= )}(hhh]j)}(h@Just like "cpus", only using ranges of CPUs instead of bitmasks.h]hDJust like “cpus”, only using ranges of CPUs instead of bitmasks.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMThjubah}(h]h ]h"]h$]h&]uh1j< hjwubeh}(h]h ]h"]h$]h&]uh1j& hhhMUhjhhubeh}(h]h ]h"]h$]h&]uh1j! hjhhhhhNubj)}(h>When control is enabled all CTRL_MON groups will also contain:h]h>When control is enabled all CTRL_MON groups will also contain:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMWhjhhubj" )}(hhh](j' )}(h"schemata": A list of all the resources available to this group. Each resource has its own line and format - see below for details. h](j- )}(h "schemata":h]h“schemata”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhM[hjubj= )}(hhh]j)}(hwA list of all the resources available to this group. Each resource has its own line and format - see below for details.h]hwA list of all the resources available to this group. Each resource has its own line and format - see below for details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMZhjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhM[hjubj' )}(h"size": Mirrors the display of the "schemata" file to display the size in bytes of each allocation instead of the bits representing the allocation. h](j- )}(h"size":h]h “size”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhM`hjubj= )}(hhh]j)}(hMirrors the display of the "schemata" file to display the size in bytes of each allocation instead of the bits representing the allocation.h]hMirrors the display of the “schemata” file to display the size in bytes of each allocation instead of the bits representing the allocation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM^hjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhM`hjhhubj' )}(hX"mode": The "mode" of the resource group dictates the sharing of its allocations. A "shareable" resource group allows sharing of its allocations while an "exclusive" resource group does not. A cache pseudo-locked region is created by first writing "pseudo-locksetup" to the "mode" file before writing the cache pseudo-locked region's schemata to the resource group's "schemata" file. On successful pseudo-locked region creation the mode will automatically change to "pseudo-locked". h](j- )}(h"mode":h]h “mode”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMjhjubj= )}(hhh]j)}(hXThe "mode" of the resource group dictates the sharing of its allocations. A "shareable" resource group allows sharing of its allocations while an "exclusive" resource group does not. A cache pseudo-locked region is created by first writing "pseudo-locksetup" to the "mode" file before writing the cache pseudo-locked region's schemata to the resource group's "schemata" file. On successful pseudo-locked region creation the mode will automatically change to "pseudo-locked".h]hXThe “mode” of the resource group dictates the sharing of its allocations. A “shareable” resource group allows sharing of its allocations while an “exclusive” resource group does not. A cache pseudo-locked region is created by first writing “pseudo-locksetup” to the “mode” file before writing the cache pseudo-locked region’s schemata to the resource group’s “schemata” file. On successful pseudo-locked region creation the mode will automatically change to “pseudo-locked”.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMchj-ubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMjhjhhubj' )}(h"ctrl_hw_id": Available only with debug option. The identifier used by hardware for the control group. On x86 this is the CLOSID. h](j- )}(h "ctrl_hw_id":h]h“ctrl_hw_id”:}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMnhjJubj= )}(hhh]j)}(hsAvailable only with debug option. The identifier used by hardware for the control group. On x86 this is the CLOSID.h]hsAvailable only with debug option. The identifier used by hardware for the control group. On x86 this is the CLOSID.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMmhj\ubah}(h]h ]h"]h$]h&]uh1j< hjJubeh}(h]h ]h"]h$]h&]uh1j& hhhMnhjhhubeh}(h]h ]h"]h$]h&]uh1j! hjhhhhhNubj)}(h:=;= Event: A valid MBM event in the /sys/fs/resctrl/info/L3_MON/event_configs directory. Domain ID: A valid domain ID. When writing, '*' applies the changes to all the domains. Assignment states: _ : No counter assigned. e : Counter assigned exclusively. Example: To display the counter assignment states for the default group. :: # cd /sys/fs/resctrl # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e Assignments can be modified by writing to the interface. Examples: To unassign the counter associated with the mbm_total_bytes event on domain 0: :: # echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=e To unassign the counter associated with the mbm_total_bytes event on all the domains: :: # echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=e To assign a counter associated with the mbm_total_bytes event on all domains in exclusive mode: :: # echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e {h](j- )}(h"mbm_L3_assignments":h]h“mbm_L3_assignments”:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh](j)}(hrExists when "mbm_event" counter assignment mode is supported and lists the counter assignment states of the group.h]hvExists when “mbm_event” counter assignment mode is supported and lists the counter assignment states of the group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(h9The assignment list is displayed in the following format:h]h9The assignment list is displayed in the following format:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hE:=;=h]hE:=;=}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj" )}(hhh](j' )}(hUEvent: A valid MBM event in the /sys/fs/resctrl/info/L3_MON/event_configs directory. h](j- )}(hEvent: A valid MBM event in theh]hEvent: A valid MBM event in the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh]j)}(h4/sys/fs/resctrl/info/L3_MON/event_configs directory.h]h4/sys/fs/resctrl/info/L3_MON/event_configs directory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubj' )}(hXDomain ID: A valid domain ID. When writing, '*' applies the changes to all the domains. h](j- )}(hCDomain ID: A valid domain ID. When writing, '*' applies the changesh]hGDomain ID: A valid domain ID. When writing, ‘*’ applies the changes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjubj= )}(hhh]j)}(hto all the domains.h]hto all the domains.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj(ubah}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubeh}(h]h ]h"]h$]h&]uh1j! hjubj)}(hAssignment states:h]hAssignment states:}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(h_ : No counter assigned.h]h_ : No counter assigned.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(h!e : Counter assigned exclusively.h]h!e : Counter assigned exclusively.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hExample:h]hExample:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hBTo display the counter assignment states for the default group. ::h]h?To display the counter assignment states for the default group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(hq# cd /sys/fs/resctrl # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=eh]hq# cd /sys/fs/resctrl # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubj)}(h8Assignments can be modified by writing to the interface.h]h8Assignments can be modified by writing to the interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(h Examples:h]h Examples:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hQTo unassign the counter associated with the mbm_total_bytes event on domain 0: ::h]hNTo unassign the counter associated with the mbm_total_bytes event on domain 0:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h# echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=e}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubj)}(hXTo unassign the counter associated with the mbm_total_bytes event on all the domains: ::h]hUTo unassign the counter associated with the mbm_total_bytes event on all the domains:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h# echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=e}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubj)}(hbTo assign a counter associated with the mbm_total_bytes event on all domains in exclusive mode: ::h]h_To assign a counter associated with the mbm_total_bytes event on all domains in exclusive mode:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj )}(h# echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e}hjsbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1j< hjubeh}(h]h ]h"]h$]h&]uh1j& hhhMhjubah}(h]h ]h"]h$]h&]uh1j! hjhhhhhNubj)}(hOWhen the "mba_MBps" mount option is used all CTRL_MON groups will also contain:h]hSWhen the “mba_MBps” mount option is used all CTRL_MON groups will also contain:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj" )}(hhh]j' )}(hXN"mba_MBps_event": Reading this file shows which memory bandwidth event is used as input to the software feedback loop that keeps memory bandwidth below the value specified in the schemata file. Writing the name of one of the supported memory bandwidth events found in /sys/fs/resctrl/info/L3_MON/mon_features changes the input event. h](j- )}(h"mba_MBps_event":h]h“mba_MBps_event”:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj2ubj= )}(hhh]j)}(hX;Reading this file shows which memory bandwidth event is used as input to the software feedback loop that keeps memory bandwidth below the value specified in the schemata file. Writing the name of one of the supported memory bandwidth events found in /sys/fs/resctrl/info/L3_MON/mon_features changes the input event.h]hX;Reading this file shows which memory bandwidth event is used as input to the software feedback loop that keeps memory bandwidth below the value specified in the schemata file. Writing the name of one of the supported memory bandwidth events found in /sys/fs/resctrl/info/L3_MON/mon_features changes the input event.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjDubah}(h]h ]h"]h$]h&]uh1j< hj2ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj/ubah}(h]h ]h"]h$]h&]uh1j! hjhhhhhNubj\)}(hhh](ja)}(hResource allocation rulesh]hResource allocation rules}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjghhhhhMubj)}(hVWhen a task is running the following rules define which resources are available to it:h]hVWhen a task is running the following rules define which resources are available to it:}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjghhubhenumerated_list)}(hhh](j)}(hZIf the task is a member of a non-default group, then the schemata for that group is used. h]j)}(hYIf the task is a member of a non-default group, then the schemata for that group is used.h]hYIf the task is a member of a non-default group, then the schemata for that group is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hElse if the task belongs to the default group, but is running on a CPU that is assigned to some specific group, then the schemata for the CPU's group is used. h]j)}(hElse if the task belongs to the default group, but is running on a CPU that is assigned to some specific group, then the schemata for the CPU's group is used.h]hElse if the task belongs to the default group, but is running on a CPU that is assigned to some specific group, then the schemata for the CPU’s group is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h6Otherwise the schemata for the default group is used. h]j)}(h5Otherwise the schemata for the default group is used.h]h5Otherwise the schemata for the default group is used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jhjghhhhhMubeh}(h]resource-allocation-rulesah ]h"]resource allocation rulesah$]h&]uh1j[hjhhhhhMubj\)}(hhh](ja)}(hResource monitoring rulesh]hResource monitoring rules}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhMubj)}(hhh](j)}(hIf a task is a member of a MON group, or non-default CTRL_MON group then RDT events for the task will be reported in that group. h]j)}(hIf a task is a member of a MON group, or non-default CTRL_MON group then RDT events for the task will be reported in that group.h]hIf a task is a member of a MON group, or non-default CTRL_MON group then RDT events for the task will be reported in that group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hIf a task is a member of the default CTRL_MON group, but is running on a CPU that is assigned to some specific group, then the RDT events for the task will be reported in that group. h]j)}(hIf a task is a member of the default CTRL_MON group, but is running on a CPU that is assigned to some specific group, then the RDT events for the task will be reported in that group.h]hIf a task is a member of the default CTRL_MON group, but is running on a CPU that is assigned to some specific group, then the RDT events for the task will be reported in that group.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXOtherwise RDT events for the task will be reported in the root level "mon_data" group. h]j)}(hVOtherwise RDT events for the task will be reported in the root level "mon_data" group.h]hZOtherwise RDT events for the task will be reported in the root level “mon_data” group.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhjhhhhhMubeh}(h]resource-monitoring-rulesah ]h"]resource monitoring rulesah$]h&]uh1j[hjhhhhhMubeh}(h]!resource-alloc-and-monitor-groupsah ]h"]!resource alloc and monitor groupsah$]h&]uh1j[hj]hhhhhMubj\)}(hhh](ja)}(h/Notes on cache occupancy monitoring and controlh]h/Notes on cache occupancy monitoring and control}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjXhhhhhMubj)}(hXWhen moving a task from one group to another you should remember that this only affects *new* cache allocations by the task. E.g. you may have a task in a monitor group showing 3 MB of cache occupancy. If you move to a new group and immediately check the occupancy of the old and new groups you will likely see that the old group is still showing 3 MB and the new group zero. When the task accesses locations still in cache from before the move, the h/w does not update any counters. On a busy system you will likely see the occupancy in the old group go down as cache lines are evicted and re-used while the occupancy in the new group rises as the task accesses memory and loads into the cache are counted based on membership in the new group.h](hXWhen moving a task from one group to another you should remember that this only affects }(hjihhhNhNubhemphasis)}(h*new*h]hnew}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jqhjiubhX cache allocations by the task. E.g. you may have a task in a monitor group showing 3 MB of cache occupancy. If you move to a new group and immediately check the occupancy of the old and new groups you will likely see that the old group is still showing 3 MB and the new group zero. When the task accesses locations still in cache from before the move, the h/w does not update any counters. On a busy system you will likely see the occupancy in the old group go down as cache lines are evicted and re-used while the occupancy in the new group rises as the task accesses memory and loads into the cache are counted based on membership in the new group.}(hjihhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM hjXhhubj)}(hThe same applies to cache allocation control. Moving a task to a group with a smaller cache partition will not evict any cache lines. The process may continue to use them from the old partition.h]hThe same applies to cache allocation control. Moving a task to a group with a smaller cache partition will not evict any cache lines. The process may continue to use them from the old partition.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjXhhubj)}(hXHardware uses CLOSid(Class of service ID) and an RMID(Resource monitoring ID) to identify a control group and a monitoring group respectively. Each of the resource groups are mapped to these IDs based on the kind of group. The number of CLOSid and RMID are limited by the hardware and hence the creation of a "CTRL_MON" directory may fail if we run out of either CLOSID or RMID and creation of "MON" group may fail if we run out of RMIDs.h]hXHardware uses CLOSid(Class of service ID) and an RMID(Resource monitoring ID) to identify a control group and a monitoring group respectively. Each of the resource groups are mapped to these IDs based on the kind of group. The number of CLOSid and RMID are limited by the hardware and hence the creation of a “CTRL_MON” directory may fail if we run out of either CLOSID or RMID and creation of “MON” group may fail if we run out of RMIDs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjXhhubj\)}(hhh](ja)}(h*max_threshold_occupancy - generic conceptsh]h*max_threshold_occupancy - generic concepts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhM!ubj)}(hXqNote that an RMID once freed may not be immediately available for use as the RMID is still tagged the cache lines of the previous user of RMID. Hence such RMIDs are placed on limbo list and checked back if the cache occupancy has gone down. If there is a time when system has a lot of limbo RMIDs but which are not ready to be used, user may see an -EBUSY during mkdir.h]hXqNote that an RMID once freed may not be immediately available for use as the RMID is still tagged the cache lines of the previous user of RMID. Hence such RMIDs are placed on limbo list and checked back if the cache occupancy has gone down. If there is a time when system has a lot of limbo RMIDs but which are not ready to be used, user may see an -EBUSY during mkdir.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM#hjhhubj)}(hnmax_threshold_occupancy is a user configurable value to determine the occupancy at which an RMID can be freed.h]hnmax_threshold_occupancy is a user configurable value to determine the occupancy at which an RMID can be freed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM*hjhhubj)}(hXlThe mon_llc_occupancy_limbo tracepoint gives the precise occupancy in bytes for a subset of RMID that are not immediately available for allocation. This can't be relied on to produce output every second, it may be necessary to attempt to create an empty monitor group to force an update. Output may only be produced if creation of a control or monitor group fails.h]hXnThe mon_llc_occupancy_limbo tracepoint gives the precise occupancy in bytes for a subset of RMID that are not immediately available for allocation. This can’t be relied on to produce output every second, it may be necessary to attempt to create an empty monitor group to force an update. Output may only be produced if creation of a control or monitor group fails.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM-hjhhubeh}(h](max-threshold-occupancy-generic-conceptsah ]h"]*max_threshold_occupancy - generic conceptsah$]h&]uh1j[hjXhhhhhM!ubj\)}(hhh](ja)}(h!Schemata files - general conceptsh]h!Schemata files - general concepts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhM4ubj)}(hEach line in the file describes one resource. The line starts with the name of the resource, followed by specific values to be applied in each of the instances of that resource on the system.h]hEach line in the file describes one resource. The line starts with the name of the resource, followed by specific values to be applied in each of the instances of that resource on the system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM5hjhhubeh}(h]schemata-files-general-conceptsah ]h"]!schemata files - general conceptsah$]h&]uh1j[hjXhhhhhM4ubj\)}(hhh](ja)}(h Cache IDsh]h Cache IDs}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhM:ubj)}(hXrOn current generation systems there is one L3 cache per socket and L2 caches are generally just shared by the hyperthreads on a core, but this isn't an architectural requirement. We could have multiple separate L3 caches on a socket, multiple cores could share an L2 cache. So instead of using "socket" or "core" to define the set of logical cpus sharing a resource we use a "Cache ID". At a given cache level this will be a unique number across the whole system (but it isn't guaranteed to be a contiguous sequence, there may be gaps). To find the ID for each logical CPU look in /sys/devices/system/cpu/cpu*/cache/index*/idh]hXOn current generation systems there is one L3 cache per socket and L2 caches are generally just shared by the hyperthreads on a core, but this isn’t an architectural requirement. We could have multiple separate L3 caches on a socket, multiple cores could share an L2 cache. So instead of using “socket” or “core” to define the set of logical cpus sharing a resource we use a “Cache ID”. At a given cache level this will be a unique number across the whole system (but it isn’t guaranteed to be a contiguous sequence, there may be gaps). To find the ID for each logical CPU look in /sys/devices/system/cpu/cpu*/cache/index*/id}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM;hj hhubeh}(h] cache-idsah ]h"] cache idsah$]h&]uh1j[hjXhhhhhM:ubj\)}(hhh](ja)}(hCache Bit Masks (CBM)h]hCache Bit Masks (CBM)}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj8 hhhhhMFubj)}(hXFor cache resources we describe the portion of the cache that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the "info" directory of the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware requires that these masks have all the '1' bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks if non-contiguous 1s value is supported. On a system with a 20-bit mask each bit represents 5% of the capacity of the cache. You could partition the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.h]hX(For cache resources we describe the portion of the cache that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the “info” directory of the resctrl file system in “info/{resource}/cbm_mask”. Some Intel hardware requires that these masks have all the ‘1’ bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks if non-contiguous 1s value is supported. On a system with a 20-bit mask each bit represents 5% of the capacity of the cache. You could partition the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMGhj8 hhubeh}(h]cache-bit-masks-cbmah ]h"]cache bit masks (cbm)ah$]h&]uh1j[hjXhhhhhMFubeh}(h]/notes-on-cache-occupancy-monitoring-and-controlah ]h"]/notes on cache occupancy monitoring and controlah$]h&]uh1j[hj]hhhhhMubj\)}(hhh](ja)}(hNotes on Sub-NUMA Cluster modeh]hNotes on Sub-NUMA Cluster mode}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjg hhhhhMTubj)}(hX0When SNC mode is enabled, Linux may load balance tasks between Sub-NUMA nodes much more readily than between regular NUMA nodes since the CPUs on Sub-NUMA nodes share the same L3 cache and the system may report the NUMA distance between Sub-NUMA nodes with a lower value than used for regular NUMA nodes.h]hX0When SNC mode is enabled, Linux may load balance tasks between Sub-NUMA nodes much more readily than between regular NUMA nodes since the CPUs on Sub-NUMA nodes share the same L3 cache and the system may report the NUMA distance between Sub-NUMA nodes with a lower value than used for regular NUMA nodes.}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMUhjg hhubj)}(hXFThe top-level monitoring files in each "mon_L3_XX" directory provide the sum of data across all SNC nodes sharing an L3 cache instance. Users who bind tasks to the CPUs of a specific Sub-NUMA node can read the "llc_occupancy", "mbm_total_bytes", and "mbm_local_bytes" in the "mon_sub_L3_YY" directories to get node local data.h]hXZThe top-level monitoring files in each “mon_L3_XX” directory provide the sum of data across all SNC nodes sharing an L3 cache instance. Users who bind tasks to the CPUs of a specific Sub-NUMA node can read the “llc_occupancy”, “mbm_total_bytes”, and “mbm_local_bytes” in the “mon_sub_L3_YY” directories to get node local data.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM[hjg hhubj)}(h|Memory bandwidth allocation is still performed at the L3 cache level. I.e. throttling controls are applied to all SNC nodes.h]h|Memory bandwidth allocation is still performed at the L3 cache level. I.e. throttling controls are applied to all SNC nodes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMahjg hhubj)}(hXbL3 cache allocation bitmaps also apply to all SNC nodes. But note that the amount of L3 cache represented by each bit is divided by the number of SNC nodes per L3 cache. E.g. with a 100MB cache on a system with 10-bit allocation masks each bit normally represents 10MB. With SNC mode enabled with two SNC nodes per L3 cache, each bit only represents 5MB.h]hXbL3 cache allocation bitmaps also apply to all SNC nodes. But note that the amount of L3 cache represented by each bit is divided by the number of SNC nodes per L3 cache. E.g. with a 100MB cache on a system with 10-bit allocation masks each bit normally represents 10MB. With SNC mode enabled with two SNC nodes per L3 cache, each bit only represents 5MB.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMdhjg hhubeh}(h]notes-on-sub-numa-cluster-modeah ]h"]notes on sub-numa cluster modeah$]h&]uh1j[hj]hhhhhMTubj\)}(hhh](ja)}(h*Memory bandwidth Allocation and monitoringh]h*Memory bandwidth Allocation and monitoring}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhMkubj)}(hFor Memory bandwidth resource, by default the user controls the resource by indicating the percentage of total memory bandwidth.h]hFor Memory bandwidth resource, by default the user controls the resource by indicating the percentage of total memory bandwidth.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMmhj hhubj)}(hXThe minimum bandwidth percentage value for each cpu model is predefined and can be looked up through "info/MB/min_bandwidth". The bandwidth granularity that is allocated is also dependent on the cpu model and can be looked up at "info/MB/bandwidth_gran". The available bandwidth control steps are: min_bw + N * bw_gran. Intermediate values are rounded to the next control step available on the hardware.h]hXThe minimum bandwidth percentage value for each cpu model is predefined and can be looked up through “info/MB/min_bandwidth”. The bandwidth granularity that is allocated is also dependent on the cpu model and can be looked up at “info/MB/bandwidth_gran”. The available bandwidth control steps are: min_bw + N * bw_gran. Intermediate values are rounded to the next control step available on the hardware.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMphj hhubj)}(hThe bandwidth throttling is a core specific mechanism on some of Intel SKUs. Using a high bandwidth and a low bandwidth setting on two threads sharing a core may result in both threads being throttled to use the low bandwidth (see "thread_throttle_mode").h]hXThe bandwidth throttling is a core specific mechanism on some of Intel SKUs. Using a high bandwidth and a low bandwidth setting on two threads sharing a core may result in both threads being throttled to use the low bandwidth (see “thread_throttle_mode”).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMwhj hhubj)}(hX7The fact that Memory bandwidth allocation(MBA) may be a core specific mechanism where as memory bandwidth monitoring(MBM) is done at the package level may lead to confusion when users try to apply control via the MBA and then monitor the bandwidth to see if the controls are effective. Below are such scenarios:h]hX7The fact that Memory bandwidth allocation(MBA) may be a core specific mechanism where as memory bandwidth monitoring(MBM) is done at the package level may lead to confusion when users try to apply control via the MBA and then monitor the bandwidth to see if the controls are effective. Below are such scenarios:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM|hj hhubj)}(hhh]j)}(hVUser may *not* see increase in actual bandwidth when percentage values are increased: h]j)}(hUUser may *not* see increase in actual bandwidth when percentage values are increased:h](h User may }(hj!hhhNhNubjr)}(h*not*h]hnot}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jqhj!ubhG see increase in actual bandwidth when percentage values are increased:}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!hhhhhNubah}(h]h ]h"]h$]h&]jjjhj.uh1jhj hhhhhMubj)}(hXThis can occur when aggregate L2 external bandwidth is more than L3 external bandwidth. Consider an SKL SKU with 24 cores on a package and where L2 external is 10GBps (hence aggregate L2 external bandwidth is 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3 bandwidth of 100GBps although the percentage value specified is only 50% << 100%. Hence increasing the bandwidth percentage will not yield any more bandwidth. This is because although the L2 external bandwidth still has capacity, the L3 external bandwidth is fully used. Also note that this would be dependent on number of cores the benchmark is run on.h]hXThis can occur when aggregate L2 external bandwidth is more than L3 external bandwidth. Consider an SKL SKU with 24 cores on a package and where L2 external is 10GBps (hence aggregate L2 external bandwidth is 240GBps) and L3 external bandwidth is 100GBps. Now a workload with ‘20 threads, having 50% bandwidth, each consuming 5GBps’ consumes the max L3 bandwidth of 100GBps although the percentage value specified is only 50% << 100%. Hence increasing the bandwidth percentage will not yield any more bandwidth. This is because although the L2 external bandwidth still has capacity, the L3 external bandwidth is fully used. Also note that this would be dependent on number of cores the benchmark is run on.}(hj5!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hhh]j)}(hYSame bandwidth percentage may mean different actual bandwidth depending on # of threads: h]j)}(hXSame bandwidth percentage may mean different actual bandwidth depending on # of threads:h]hXSame bandwidth percentage may mean different actual bandwidth depending on # of threads:}(hjJ!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjF!ubah}(h]h ]h"]h$]h&]uh1jhjC!hhhhhNubah}(h]h ]h"]h$]h&]jjjhjj4!startKuh1jhj hhhhhMubj)}(hXbFor the same SKU in #1, a 'single thread, with 10% bandwidth' and '4 thread, with 10% bandwidth' can consume up to 10GBps and 40GBps although they have same percentage bandwidth of 10%. This is simply because as threads start using more cores in an rdtgroup, the actual bandwidth may increase or vary although user specified bandwidth percentage is same.h]hXjFor the same SKU in #1, a ‘single thread, with 10% bandwidth’ and ‘4 thread, with 10% bandwidth’ can consume up to 10GBps and 40GBps although they have same percentage bandwidth of 10%. This is simply because as threads start using more cores in an rdtgroup, the actual bandwidth may increase or vary although user specified bandwidth percentage is same.}(hje!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hXWIn order to mitigate this and make the interface more user friendly, resctrl added support for specifying the bandwidth in MiBps as well. The kernel underneath would use a software feedback mechanism or a "Software Controller(mba_sc)" which reads the actual bandwidth using MBM counters and adjust the memory bandwidth percentages to ensure::h]hXZIn order to mitigate this and make the interface more user friendly, resctrl added support for specifying the bandwidth in MiBps as well. The kernel underneath would use a software feedback mechanism or a “Software Controller(mba_sc)” which reads the actual bandwidth using MBM counters and adjust the memory bandwidth percentages to ensure:}(hjs!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj )}(h."actual bandwidth < user specified bandwidth".h]h."actual bandwidth < user specified bandwidth".}hj!sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj hhubj)}(hBy default, the schemata would take the bandwidth percentage values where as user can switch to the "MBA software controller" mode using a mount option 'mba_MBps'. The schemata format is specified in the below sections.h]hBy default, the schemata would take the bandwidth percentage values where as user can switch to the “MBA software controller” mode using a mount option ‘mba_MBps’. The schemata format is specified in the below sections.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj\)}(hhh](ja)}(h@L3 schemata file details (code and data prioritization disabled)h]h@L3 schemata file details (code and data prioritization disabled)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj!hhhhhMubj)}(h-With CDP disabled the L3 schemata format is::h]h,With CDP disabled the L3 schemata format is:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj!hhubj )}(h*L3:=;=;...h]h*L3:=;=;...}hj!sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj!hhubeh}(h]>l3-schemata-file-details-code-and-data-prioritization-disabledah ]h"]@l3 schemata file details (code and data prioritization disabled)ah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hBL3 schemata file details (CDP enabled via mount option to resctrl)h]hBL3 schemata file details (CDP enabled via mount option to resctrl)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj!hhhhhMubj)}(hWhen CDP is enabled L3 control is split into two separate resources so you can specify independent masks for code and data like this::h]hWhen CDP is enabled L3 control is split into two separate resources so you can specify independent masks for code and data like this:}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj!hhubj )}(h]L3DATA:=;=;... L3CODE:=;=;...h]h]L3DATA:=;=;... L3CODE:=;=;...}hj!sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj!hhubeh}(h]@l3-schemata-file-details-cdp-enabled-via-mount-option-to-resctrlah ]h"]Bl3 schemata file details (cdp enabled via mount option to resctrl)ah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hL2 schemata file detailsh]hL2 schemata file details}(hj "hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj"hhhhhMubj)}(hVCDP is supported at L2 using the 'cdpl2' mount option. The schemata format is either::h]hYCDP is supported at L2 using the ‘cdpl2’ mount option. The schemata format is either:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubj )}(h*L2:=;=;...h]h*L2:=;=;...}hj&"sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj"hhubj)}(horh]hor}(hj4"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubjR )}(h_L2DATA:=;=;... L2CODE:=;=;... h]j)}(h]L2DATA:=;=;... L2CODE:=;=;...h]h]L2DATA:=;=;... L2CODE:=;=;...}(hjF"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjB"ubah}(h]h ]h"]h$]h&]uh1jQ hhhMhj"hhubeh}(h]l2-schemata-file-detailsah ]h"]l2 schemata file detailsah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h*Memory bandwidth Allocation (default mode)h]h*Memory bandwidth Allocation (default mode)}(hje"hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjb"hhhhhMubj)}(h!Memory b/w domain is L3 cache. ::h]hMemory b/w domain is L3 cache.}(hjs"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjb"hhubj )}(h4MB:=bandwidth0;=bandwidth1;...h]h4MB:=bandwidth0;=bandwidth1;...}hj"sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjb"hhubeh}(h](memory-bandwidth-allocation-default-modeah ]h"]*memory bandwidth allocation (default mode)ah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h.Memory bandwidth Allocation specified in MiBpsh]h.Memory bandwidth Allocation specified in MiBps}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj"hhhhhMubj)}(h'Memory bandwidth domain is L3 cache. ::h]h$Memory bandwidth domain is L3 cache.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubj )}(h2MB:=bw_MiBps0;=bw_MiBps1;...h]h2MB:=bw_MiBps0;=bw_MiBps1;...}hj"sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj"hhubeh}(h].memory-bandwidth-allocation-specified-in-mibpsah ]h"].memory bandwidth allocation specified in mibpsah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h'Slow Memory Bandwidth Allocation (SMBA)h]h'Slow Memory Bandwidth Allocation (SMBA)}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj"hhhhhMubj)}(hXkAMD hardware supports Slow Memory Bandwidth Allocation (SMBA). CXL.memory is the only supported "slow" memory device. With the support of SMBA, the hardware enables bandwidth allocation on the slow memory devices. If there are multiple such devices in the system, the throttling logic groups all the slow sources together and applies the limit on them as a whole.h]hXoAMD hardware supports Slow Memory Bandwidth Allocation (SMBA). CXL.memory is the only supported “slow” memory device. With the support of SMBA, the hardware enables bandwidth allocation on the slow memory devices. If there are multiple such devices in the system, the throttling logic groups all the slow sources together and applies the limit on them as a whole.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubj)}(hThe presence of SMBA (with CXL.memory) is independent of slow memory devices presence. If there are no such devices on the system, then configuring SMBA will have no impact on the performance of the system.h]hThe presence of SMBA (with CXL.memory) is independent of slow memory devices presence. If there are no such devices on the system, then configuring SMBA will have no impact on the performance of the system.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubj)}(hWThe bandwidth domain for slow memory is L3 cache. Its schemata file is formatted as: ::h]hTThe bandwidth domain for slow memory is L3 cache. Its schemata file is formatted as:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"hhubj )}(h6SMBA:=bandwidth0;=bandwidth1;...h]h6SMBA:=bandwidth0;=bandwidth1;...}hj#sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj"hhubeh}(h]%slow-memory-bandwidth-allocation-smbaah ]h"]'slow memory bandwidth allocation (smba)ah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h!Reading/writing the schemata fileh]h!Reading/writing the schemata file}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj#hhhhhMubj)}(hReading the schemata file will show the state of all resources on all domains. When writing you only need to specify those values which you wish to change. E.g. ::h]hReading the schemata file will show the state of all resources on all domains. When writing you only need to specify those values which you wish to change. E.g.}(hj.#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj#hhubj )}(h# cat schemata L3DATA:0=fffff;1=fffff;2=fffff;3=fffff L3CODE:0=fffff;1=fffff;2=fffff;3=fffff # echo "L3DATA:2=3c0;" > schemata # cat schemata L3DATA:0=fffff;1=fffff;2=3c0;3=fffff L3CODE:0=fffff;1=fffff;2=fffff;3=fffffh]h# cat schemata L3DATA:0=fffff;1=fffff;2=fffff;3=fffff L3CODE:0=fffff;1=fffff;2=fffff;3=fffff # echo "L3DATA:2=3c0;" > schemata # cat schemata L3DATA:0=fffff;1=fffff;2=3c0;3=fffff L3CODE:0=fffff;1=fffff;2=fffff;3=fffff}hj<#sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj#hhubeh}(h]!reading-writing-the-schemata-fileah ]h"]!reading/writing the schemata fileah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(h2Reading/writing the schemata file (on AMD systems)h]h2Reading/writing the schemata file (on AMD systems)}(hjU#hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjR#hhhhhMubj)}(hReading the schemata file will show the current bandwidth limit on all domains. The allocated resources are in multiples of one eighth GB/s. When writing to the file, you need to specify what cache id you wish to configure the bandwidth limit.h]hReading the schemata file will show the current bandwidth limit on all domains. The allocated resources are in multiples of one eighth GB/s. When writing to the file, you need to specify what cache id you wish to configure the bandwidth limit.}(hjc#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjR#hhubj)}(h;For example, to allocate 2GB/s limit on the first cache id:h]h;For example, to allocate 2GB/s limit on the first cache id:}(hjq#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjR#hhubj )}(h# cat schemata MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff # echo "MB:1=16" > schemata # cat schemata MB:0=2048;1= 16;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffffh]h# cat schemata MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff # echo "MB:1=16" > schemata # cat schemata MB:0=2048;1= 16;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff}hj#sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjR#hhubeh}(h]0reading-writing-the-schemata-file-on-amd-systemsah ]h"]2reading/writing the schemata file (on amd systems)ah$]h&]uh1j[hj hhhhhMubj\)}(hhh](ja)}(hDReading/writing the schemata file (on AMD systems) with SMBA featureh]hDReading/writing the schemata file (on AMD systems) with SMBA feature}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj#hhhhhMubj)}(hSReading and writing the schemata file is the same as without SMBA in above section.h]hSReading and writing the schemata file is the same as without SMBA in above section.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj#hhubj)}(h;For example, to allocate 8GB/s limit on the first cache id:h]h;For example, to allocate 8GB/s limit on the first cache id:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj#hhubj )}(hX# cat schemata SMBA:0=2048;1=2048;2=2048;3=2048 MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff # echo "SMBA:1=64" > schemata # cat schemata SMBA:0=2048;1= 64;2=2048;3=2048 MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffffh]hX# cat schemata SMBA:0=2048;1=2048;2=2048;3=2048 MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff # echo "SMBA:1=64" > schemata # cat schemata SMBA:0=2048;1= 64;2=2048;3=2048 MB:0=2048;1=2048;2=2048;3=2048 L3:0=ffff;1=ffff;2=ffff;3=ffff}hj#sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj#hhubeh}(h]Breading-writing-the-schemata-file-on-amd-systems-with-smba-featureah ]h"]Dreading/writing the schemata file (on amd systems) with smba featureah$]h&]uh1j[hj hhhhhMubeh}(h]*memory-bandwidth-allocation-and-monitoringah ]h"]*memory bandwidth allocation and monitoringah$]h&]uh1j[hj]hhhhhMkubj\)}(hhh](ja)}(hCache Pseudo-Lockingh]hCache Pseudo-Locking}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj#hhhhhMubj)}(hXMCAT enables a user to specify the amount of cache space that an application can fill. Cache pseudo-locking builds on the fact that a CPU can still read and write data pre-allocated outside its current allocated area on a cache hit. With cache pseudo-locking, data can be preloaded into a reserved portion of cache that no application can fill, and from that point on will only serve cache hits. The cache pseudo-locked memory is made accessible to user space where an application can map it into its virtual address space and thus have a region of memory with reduced average read latency.h]hXMCAT enables a user to specify the amount of cache space that an application can fill. Cache pseudo-locking builds on the fact that a CPU can still read and write data pre-allocated outside its current allocated area on a cache hit. With cache pseudo-locking, data can be preloaded into a reserved portion of cache that no application can fill, and from that point on will only serve cache hits. The cache pseudo-locked memory is made accessible to user space where an application can map it into its virtual address space and thus have a region of memory with reduced average read latency.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj#hhubj)}(hThe creation of a cache pseudo-locked region is triggered by a request from the user to do so that is accompanied by a schemata of the region to be pseudo-locked. The cache pseudo-locked region is created as follows:h]hThe creation of a cache pseudo-locked region is triggered by a request from the user to do so that is accompanied by a schemata of the region to be pseudo-locked. The cache pseudo-locked region is created as follows:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM'hj#hhubj)}(hhh](j)}(hX=Create a CAT allocation CLOSNEW with a CBM matching the schemata from the user of the cache region that will contain the pseudo-locked memory. This region must not overlap with any current CAT allocation/CLOS on the system and no future overlap with this cache region is allowed while the pseudo-locked region exists.h]j)}(hX=Create a CAT allocation CLOSNEW with a CBM matching the schemata from the user of the cache region that will contain the pseudo-locked memory. This region must not overlap with any current CAT allocation/CLOS on the system and no future overlap with this cache region is allowed while the pseudo-locked region exists.h]hX=Create a CAT allocation CLOSNEW with a CBM matching the schemata from the user of the cache region that will contain the pseudo-locked memory. This region must not overlap with any current CAT allocation/CLOS on the system and no future overlap with this cache region is allowed while the pseudo-locked region exists.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM+hj$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(hJCreate a contiguous region of memory of the same size as the cache region.h]j)}(hJCreate a contiguous region of memory of the same size as the cache region.h]hJCreate a contiguous region of memory of the same size as the cache region.}(hj,$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM0hj($ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(hBFlush the cache, disable hardware prefetchers, disable preemption.h]j)}(hjB$h]hBFlush the cache, disable hardware prefetchers, disable preemption.}(hjD$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM2hj@$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(hVMake CLOSNEW the active CLOS and touch the allocated memory to load it into the cache.h]j)}(hVMake CLOSNEW the active CLOS and touch the allocated memory to load it into the cache.h]hVMake CLOSNEW the active CLOS and touch the allocated memory to load it into the cache.}(hj[$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM3hjW$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(h Set the previous CLOS as active.h]j)}(hjq$h]h Set the previous CLOS as active.}(hjs$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM5hjo$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(hXAt this point the closid CLOSNEW can be released - the cache pseudo-locked region is protected as long as its CBM does not appear in any CAT allocation. Even though the cache pseudo-locked region will from this point on not appear in any CBM of any CLOS an application running with any CLOS will be able to access the memory in the pseudo-locked region since the region continues to serve cache hits.h]j)}(hXAt this point the closid CLOSNEW can be released - the cache pseudo-locked region is protected as long as its CBM does not appear in any CAT allocation. Even though the cache pseudo-locked region will from this point on not appear in any CBM of any CLOS an application running with any CLOS will be able to access the memory in the pseudo-locked region since the region continues to serve cache hits.h]hXAt this point the closid CLOSNEW can be released - the cache pseudo-locked region is protected as long as its CBM does not appear in any CAT allocation. Even though the cache pseudo-locked region will from this point on not appear in any CBM of any CLOS an application running with any CLOS will be able to access the memory in the pseudo-locked region since the region continues to serve cache hits.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM6hj$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubj)}(hfThe contiguous region of memory loaded into the cache is exposed to user-space as a character device. h]j)}(heThe contiguous region of memory loaded into the cache is exposed to user-space as a character device.h]heThe contiguous region of memory loaded into the cache is exposed to user-space as a character device.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM<hj$ubah}(h]h ]h"]h$]h&]uh1jhj $hhhhhNubeh}(h]h ]h"]h$]h&]jUjVuh1jhhhM+hj#hhubj)}(hXCache pseudo-locking increases the probability that data will remain in the cache via carefully configuring the CAT feature and controlling application behavior. There is no guarantee that data is placed in cache. Instructions like INVD, WBINVD, CLFLUSH, etc. can still evict “locked” data from cache. Power management C-states may shrink or power off cache. Deeper C-states will automatically be restricted on pseudo-locked region creation.h]hXCache pseudo-locking increases the probability that data will remain in the cache via carefully configuring the CAT feature and controlling application behavior. There is no guarantee that data is placed in cache. Instructions like INVD, WBINVD, CLFLUSH, etc. can still evict “locked” data from cache. Power management C-states may shrink or power off cache. Deeper C-states will automatically be restricted on pseudo-locked region creation.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM?hj#hhubj)}(hX9It is required that an application using a pseudo-locked region runs with affinity to the cores (or a subset of the cores) associated with the cache on which the pseudo-locked region resides. A sanity check within the code will not allow an application to map pseudo-locked memory unless it runs with affinity to cores associated with the cache on which the pseudo-locked region resides. The sanity check is only done during the initial mmap() handling, there is no enforcement afterwards and the application self needs to ensure it remains affine to the correct cores.h]hX9It is required that an application using a pseudo-locked region runs with affinity to the cores (or a subset of the cores) associated with the cache on which the pseudo-locked region resides. A sanity check within the code will not allow an application to map pseudo-locked memory unless it runs with affinity to cores associated with the cache on which the pseudo-locked region resides. The sanity check is only done during the initial mmap() handling, there is no enforcement afterwards and the application self needs to ensure it remains affine to the correct cores.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMGhj#hhubj)}(h-Pseudo-locking is accomplished in two stages:h]h-Pseudo-locking is accomplished in two stages:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMPhj#hhubj)}(hhh](j)}(hDuring the first stage the system administrator allocates a portion of cache that should be dedicated to pseudo-locking. At this time an equivalent portion of memory is allocated, loaded into allocated cache portion, and exposed as a character device.h]j)}(hDuring the first stage the system administrator allocates a portion of cache that should be dedicated to pseudo-locking. At this time an equivalent portion of memory is allocated, loaded into allocated cache portion, and exposed as a character device.h]hDuring the first stage the system administrator allocates a portion of cache that should be dedicated to pseudo-locking. At this time an equivalent portion of memory is allocated, loaded into allocated cache portion, and exposed as a character device.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMRhj$ubah}(h]h ]h"]h$]h&]uh1jhj$hhhhhNubj)}(hpDuring the second stage a user-space application maps (mmap()) the pseudo-locked memory into its address space. h]j)}(hoDuring the second stage a user-space application maps (mmap()) the pseudo-locked memory into its address space.h]hoDuring the second stage a user-space application maps (mmap()) the pseudo-locked memory into its address space.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMVhj%ubah}(h]h ]h"]h$]h&]uh1jhj$hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhj#hhhhhMRubj\)}(hhh](ja)}(hCache Pseudo-Locking Interfaceh]hCache Pseudo-Locking Interface}(hj"%hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj%hhhhhMZubj)}(hIA pseudo-locked region is created using the resctrl interface as follows:h]hIA pseudo-locked region is created using the resctrl interface as follows:}(hj0%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM[hj%hhubj)}(hhh](j)}(hKCreate a new resource group by creating a new directory in /sys/fs/resctrl.h]j)}(hjC%h]hKCreate a new resource group by creating a new directory in /sys/fs/resctrl.}(hjE%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM]hjA%ubah}(h]h ]h"]h$]h&]uh1jhj>%hhhhhNubj)}(hlChange the new resource group's mode to "pseudo-locksetup" by writing "pseudo-locksetup" to the "mode" file.h]j)}(hlChange the new resource group's mode to "pseudo-locksetup" by writing "pseudo-locksetup" to the "mode" file.h]hzChange the new resource group’s mode to “pseudo-locksetup” by writing “pseudo-locksetup” to the “mode” file.}(hj\%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM^hjX%ubah}(h]h ]h"]h$]h&]uh1jhj>%hhhhhNubj)}(hWrite the schemata of the pseudo-locked region to the "schemata" file. All bits within the schemata should be "unused" according to the "bit_usage" file. h]j)}(hWrite the schemata of the pseudo-locked region to the "schemata" file. All bits within the schemata should be "unused" according to the "bit_usage" file.h]hWrite the schemata of the pseudo-locked region to the “schemata” file. All bits within the schemata should be “unused” according to the “bit_usage” file.}(hjt%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM`hjp%ubah}(h]h ]h"]h$]h&]uh1jhj>%hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhj%hhhhhM]ubj)}(hX/On successful pseudo-locked region creation the "mode" file will contain "pseudo-locked" and a new character device with the same name as the resource group will exist in /dev/pseudo_lock. This character device can be mmap()'ed by user space in order to obtain access to the pseudo-locked memory region.h]hX9On successful pseudo-locked region creation the “mode” file will contain “pseudo-locked” and a new character device with the same name as the resource group will exist in /dev/pseudo_lock. This character device can be mmap()’ed by user space in order to obtain access to the pseudo-locked memory region.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMdhj%hhubj)}(hOAn example of cache pseudo-locked region creation and usage can be found below.h]hOAn example of cache pseudo-locked region creation and usage can be found below.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMihj%hhubeh}(h]cache-pseudo-locking-interfaceah ]h"]cache pseudo-locking interfaceah$]h&]uh1j[hj#hhhhhMZubj\)}(hhh](ja)}(h(Cache Pseudo-Locking Debugging Interfaceh]h(Cache Pseudo-Locking Debugging Interface}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj%hhhhhMlubj)}(hThe pseudo-locking debugging interface is enabled by default (if CONFIG_DEBUG_FS is enabled) and can be found in /sys/kernel/debug/resctrl.h]hThe pseudo-locking debugging interface is enabled by default (if CONFIG_DEBUG_FS is enabled) and can be found in /sys/kernel/debug/resctrl.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMmhj%hhubj)}(hThere is no explicit way for the kernel to test if a provided memory location is present in the cache. The pseudo-locking debugging interface uses the tracing infrastructure to provide two ways to measure cache residency of the pseudo-locked region:h]hThere is no explicit way for the kernel to test if a provided memory location is present in the cache. The pseudo-locking debugging interface uses the tracing infrastructure to provide two ways to measure cache residency of the pseudo-locked region:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMphj%hhubj)}(hhh](j)}(hXiMemory access latency using the pseudo_lock_mem_latency tracepoint. Data from these measurements are best visualized using a hist trigger (see example below). In this test the pseudo-locked region is traversed at a stride of 32 bytes while hardware prefetchers and preemption are disabled. This also provides a substitute visualization of cache hits and misses.h]j)}(hXiMemory access latency using the pseudo_lock_mem_latency tracepoint. Data from these measurements are best visualized using a hist trigger (see example below). In this test the pseudo-locked region is traversed at a stride of 32 bytes while hardware prefetchers and preemption are disabled. This also provides a substitute visualization of cache hits and misses.h]hXiMemory access latency using the pseudo_lock_mem_latency tracepoint. Data from these measurements are best visualized using a hist trigger (see example below). In this test the pseudo-locked region is traversed at a stride of 32 bytes while hardware prefetchers and preemption are disabled. This also provides a substitute visualization of cache hits and misses.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMuhj%ubah}(h]h ]h"]h$]h&]uh1jhj%hhhhhNubj)}(hCache hit and miss measurements using model specific precision counters if available. Depending on the levels of cache on the system the pseudo_lock_l2 and pseudo_lock_l3 tracepoints are available. h]j)}(hCache hit and miss measurements using model specific precision counters if available. Depending on the levels of cache on the system the pseudo_lock_l2 and pseudo_lock_l3 tracepoints are available.h]hCache hit and miss measurements using model specific precision counters if available. Depending on the levels of cache on the system the pseudo_lock_l2 and pseudo_lock_l3 tracepoints are available.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM{hj%ubah}(h]h ]h"]h$]h&]uh1jhj%hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jhj%hhhhhMuubj)}(hX/When a pseudo-locked region is created a new debugfs directory is created for it in debugfs as /sys/kernel/debug/resctrl/. A single write-only file, pseudo_lock_measure, is present in this directory. The measurement of the pseudo-locked region depends on the number written to this debugfs file:h]hX/When a pseudo-locked region is created a new debugfs directory is created for it in debugfs as /sys/kernel/debug/resctrl/. A single write-only file, pseudo_lock_measure, is present in this directory. The measurement of the pseudo-locked region depends on the number written to this debugfs file:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj%hhubj" )}(hhh](j' )}(h1: writing "1" to the pseudo_lock_measure file will trigger the latency measurement captured in the pseudo_lock_mem_latency tracepoint. See example below.h](j- )}(h1:h]h1:}(hj-&hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj)&ubj= )}(hhh]j)}(hwriting "1" to the pseudo_lock_measure file will trigger the latency measurement captured in the pseudo_lock_mem_latency tracepoint. See example below.h]hwriting “1” to the pseudo_lock_measure file will trigger the latency measurement captured in the pseudo_lock_mem_latency tracepoint. See example below.}(hj>&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj;&ubah}(h]h ]h"]h$]h&]uh1j< hj)&ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj&&ubj' )}(h2: writing "2" to the pseudo_lock_measure file will trigger the L2 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l2 tracepoint. See example below.h](j- )}(h2:h]h2:}(hj\&hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhjX&ubj= )}(hhh]j)}(hwriting "2" to the pseudo_lock_measure file will trigger the L2 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l2 tracepoint. See example below.h]hwriting “2” to the pseudo_lock_measure file will trigger the L2 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l2 tracepoint. See example below.}(hjm&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjj&ubah}(h]h ]h"]h$]h&]uh1j< hjX&ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj&&hhubj' )}(h3: writing "3" to the pseudo_lock_measure file will trigger the L3 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l3 tracepoint. h](j- )}(h3:h]h3:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j, hhhMhj&ubj= )}(hhh]j)}(hwriting "3" to the pseudo_lock_measure file will trigger the L3 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l3 tracepoint.h]hwriting “3” to the pseudo_lock_measure file will trigger the L3 cache residency (cache hits and misses) measurement captured in the pseudo_lock_l3 tracepoint.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j< hj&ubeh}(h]h ]h"]h$]h&]uh1j& hhhMhj&&hhubeh}(h]h ]h"]h$]h&]uh1j! hj%hhhhhNubj)}(hAll measurements are recorded with the tracing infrastructure. This requires the relevant tracepoints to be enabled before the measurement is triggered.h]hAll measurements are recorded with the tracing infrastructure. This requires the relevant tracepoints to be enabled before the measurement is triggered.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj%hhubj\)}(hhh](ja)}(h&Example of latency debugging interfaceh]h&Example of latency debugging interface}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj&hhhhhMubj)}(hIn this example a pseudo-locked region named "newlock" was created. Here is how we can measure the latency in cycles of reading from this region and visualize this data with a histogram that is available if CONFIG_HIST_TRIGGERS is set::h]hIn this example a pseudo-locked region named “newlock” was created. Here is how we can measure the latency in cycles of reading from this region and visualize this data with a histogram that is available if CONFIG_HIST_TRIGGERS is set:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj&hhubj )}(hX# :> /sys/kernel/tracing/trace # echo 'hist:keys=latency' > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/trigger # echo 1 > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/enable # echo 1 > /sys/kernel/debug/resctrl/newlock/pseudo_lock_measure # echo 0 > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/enable # cat /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/hist # event histogram # # trigger info: hist:keys=latency:vals=hitcount:sort=hitcount:size=2048 [active] # { latency: 456 } hitcount: 1 { latency: 50 } hitcount: 83 { latency: 36 } hitcount: 96 { latency: 44 } hitcount: 174 { latency: 48 } hitcount: 195 { latency: 46 } hitcount: 262 { latency: 42 } hitcount: 693 { latency: 40 } hitcount: 3204 { latency: 38 } hitcount: 3484 Totals: Hits: 8192 Entries: 9 Dropped: 0h]hX# :> /sys/kernel/tracing/trace # echo 'hist:keys=latency' > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/trigger # echo 1 > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/enable # echo 1 > /sys/kernel/debug/resctrl/newlock/pseudo_lock_measure # echo 0 > /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/enable # cat /sys/kernel/tracing/events/resctrl/pseudo_lock_mem_latency/hist # event histogram # # trigger info: hist:keys=latency:vals=hitcount:sort=hitcount:size=2048 [active] # { latency: 456 } hitcount: 1 { latency: 50 } hitcount: 83 { latency: 36 } hitcount: 96 { latency: 44 } hitcount: 174 { latency: 48 } hitcount: 195 { latency: 46 } hitcount: 262 { latency: 42 } hitcount: 693 { latency: 40 } hitcount: 3204 { latency: 38 } hitcount: 3484 Totals: Hits: 8192 Entries: 9 Dropped: 0}hj&sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj&hhubeh}(h]&example-of-latency-debugging-interfaceah ]h"]&example of latency debugging interfaceah$]h&]uh1j[hj%hhhhhMubj\)}(hhh](ja)}(h&Example of cache hits/misses debuggingh]h&Example of cache hits/misses debugging}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj&hhhhhMubj)}(hIn this example a pseudo-locked region named "newlock" was created on the L2 cache of a platform. Here is how we can obtain details of the cache hits and misses using the platform's precision counters. ::h]hIn this example a pseudo-locked region named “newlock” was created on the L2 cache of a platform. Here is how we can obtain details of the cache hits and misses using the platform’s precision counters.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj&hhubj )}(hX# :> /sys/kernel/tracing/trace # echo 1 > /sys/kernel/tracing/events/resctrl/pseudo_lock_l2/enable # echo 2 > /sys/kernel/debug/resctrl/newlock/pseudo_lock_measure # echo 0 > /sys/kernel/tracing/events/resctrl/pseudo_lock_l2/enable # cat /sys/kernel/tracing/trace # tracer: nop # # _-----=> irqs-off # / _----=> need-resched # | / _---=> hardirq/softirq # || / _--=> preempt-depth # ||| / delay # TASK-PID CPU# |||| TIMESTAMP FUNCTION # | | | |||| | | pseudo_lock_mea-1672 [002] .... 3132.860500: pseudo_lock_l2: hits=4097 miss=0h]hX# :> /sys/kernel/tracing/trace # echo 1 > /sys/kernel/tracing/events/resctrl/pseudo_lock_l2/enable # echo 2 > /sys/kernel/debug/resctrl/newlock/pseudo_lock_measure # echo 0 > /sys/kernel/tracing/events/resctrl/pseudo_lock_l2/enable # cat /sys/kernel/tracing/trace # tracer: nop # # _-----=> irqs-off # / _----=> need-resched # | / _---=> hardirq/softirq # || / _--=> preempt-depth # ||| / delay # TASK-PID CPU# |||| TIMESTAMP FUNCTION # | | | |||| | | pseudo_lock_mea-1672 [002] .... 3132.860500: pseudo_lock_l2: hits=4097 miss=0}hj'sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj&hhubeh}(h]&example-of-cache-hits-misses-debuggingah ]h"]&example of cache hits/misses debuggingah$]h&]uh1j[hj%hhhhhMubj\)}(hhh](ja)}(h!Examples for RDT allocation usageh]h!Examples for RDT allocation usage}(hj7'hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj4'hhhhhMubj)}(hhh]j)}(h Example 1 h]j)}(h Example 1h]h Example 1}(hjL'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjH'ubah}(h]h ]h"]h$]h&]uh1jhjE'hhhhhNubah}(h]h ]h"]h$]h&]jjjhjjuh1jhj4'hhhhhMubj)}(hOn a two socket machine (one L3 cache per socket) with just four bits for cache bit masks, minimum b/w of 10% with a memory bandwidth granularity of 10%. ::h]hOn a two socket machine (one L3 cache per socket) with just four bits for cache bit masks, minimum b/w of 10% with a memory bandwidth granularity of 10%.}(hjf'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1 # echo "L3:0=3;1=c\nMB:0=50;1=50" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3\nMB:0=50;1=50" > /sys/fs/resctrl/p1/schematah]h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1 # echo "L3:0=3;1=c\nMB:0=50;1=50" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3\nMB:0=50;1=50" > /sys/fs/resctrl/p1/schemata}hjt'sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(h~The default resource group is unmodified, so we have access to all parts of all caches (its schemata file reads "L3:0=f;1=f").h]hThe default resource group is unmodified, so we have access to all parts of all caches (its schemata file reads “L3:0=f;1=f”).}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj)}(hTasks that are under the control of group "p0" may only allocate from the "lower" 50% on cache ID 0, and the "upper" 50% of cache ID 1. Tasks in group "p1" use the "lower" 50% of cache on both sockets.h]hTasks that are under the control of group “p0” may only allocate from the “lower” 50% on cache ID 0, and the “upper” 50% of cache ID 1. Tasks in group “p1” use the “lower” 50% of cache on both sockets.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj)}(hXSimilarly, tasks that are under the control of group "p0" may use a maximum memory b/w of 50% on socket0 and 50% on socket 1. Tasks in group "p1" may also use 50% memory b/w on both sockets. Note that unlike cache masks, memory b/w cannot specify whether these allocations can overlap or not. The allocations specifies the maximum b/w that the group may be able to use and the system admin can configure the b/w accordingly.h]hXSimilarly, tasks that are under the control of group “p0” may use a maximum memory b/w of 50% on socket0 and 50% on socket 1. Tasks in group “p1” may also use 50% memory b/w on both sockets. Note that unlike cache masks, memory b/w cannot specify whether these allocations can overlap or not. The allocations specifies the maximum b/w that the group may be able to use and the system admin can configure the b/w accordingly.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj)}(hIf resctrl is using the software controller (mba_sc) then user can enter the max b/w in MB rather than the percentage values. ::h]h}If resctrl is using the software controller (mba_sc) then user can enter the max b/w in MB rather than the percentage values.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h# echo "L3:0=3;1=c\nMB:0=1024;1=500" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3\nMB:0=1024;1=500" > /sys/fs/resctrl/p1/schematah]h# echo "L3:0=3;1=c\nMB:0=1024;1=500" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3\nMB:0=1024;1=500" > /sys/fs/resctrl/p1/schemata}hj'sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hIn the above example the tasks in "p1" and "p0" on socket 0 would use a max b/w of 1024MB where as on socket 1 they would use 500MB.h]hIn the above example the tasks in “p1” and “p0” on socket 0 would use a max b/w of 1024MB where as on socket 1 they would use 500MB.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj)}(hhh]j)}(h Example 2 h]j)}(h Example 2h]h Example 2}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhj'hhhhhNubah}(h]h ]h"]h$]h&]jjjhjjjd!Kuh1jhj4'hhhhhMubj)}(hCAgain two sockets, but this time with a more realistic 20-bit mask.h]hCAgain two sockets, but this time with a more realistic 20-bit mask.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj)}(hTwo real time tasks pid=1234 running on processor 0 and pid=5678 running on processor 1 on socket 0 on a 2-socket and dual core machine. To avoid noisy neighbors, each of the two real-time tasks exclusively occupies one quarter of L3 cache on socket 0. ::h]hTwo real time tasks pid=1234 running on processor 0 and pid=5678 running on processor 1 on socket 0 on a 2-socket and dual core machine. To avoid noisy neighbors, each of the two real-time tasks exclusively occupies one quarter of L3 cache on socket 0.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h?# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrlh]h?# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl}hj(sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hFirst we reset the schemata for the default group so that the "upper" 50% of the L3 cache on socket 0 and 50% of memory b/w cannot be used by ordinary tasks::h]hFirst we reset the schemata for the default group so that the “upper” 50% of the L3 cache on socket 0 and 50% of memory b/w cannot be used by ordinary tasks:}(hj!(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h3# echo "L3:0=3ff;1=fffff\nMB:0=50;1=100" > schematah]h3# echo "L3:0=3ff;1=fffff\nMB:0=50;1=100" > schemata}hj/(sbah}(h]h ]h"]h$]h&]hhuh1j hhhM hj4'hhubj)}(h{Next we make a resource group for our first real time task and give it access to the "top" 25% of the cache on socket 0. ::h]h|Next we make a resource group for our first real time task and give it access to the “top” 25% of the cache on socket 0.}(hj=(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj4'hhubj )}(h4# mkdir p0 # echo "L3:0=f8000;1=fffff" > p0/schematah]h4# mkdir p0 # echo "L3:0=f8000;1=fffff" > p0/schemata}hjK(sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hFinally we move our first real time task into this resource group. We also use taskset(1) to ensure the task always runs on a dedicated CPU on socket 0. Most uses of resource groups will also constrain which processors tasks run on. ::h]hFinally we move our first real time task into this resource group. We also use taskset(1) to ensure the task always runs on a dedicated CPU on socket 0. Most uses of resource groups will also constrain which processors tasks run on.}(hjY(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h+# echo 1234 > p0/tasks # taskset -cp 1 1234h]h+# echo 1234 > p0/tasks # taskset -cp 1 1234}hjg(sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hGDitto for the second real time task (with the remaining 25% of cache)::h]hFDitto for the second real time task (with the remaining 25% of cache):}(hju(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h_# mkdir p1 # echo "L3:0=7c00;1=fffff" > p1/schemata # echo 5678 > p1/tasks # taskset -cp 2 5678h]h_# mkdir p1 # echo "L3:0=7c00;1=fffff" > p1/schemata # echo 5678 > p1/tasks # taskset -cp 2 5678}hj(sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hFor the same 2 socket system with memory b/w resource and CAT L3 the schemata would look like(Assume min_bandwidth 10 and bandwidth_gran is 10):h]hFor the same 2 socket system with memory b/w resource and CAT L3 the schemata would look like(Assume min_bandwidth 10 and bandwidth_gran is 10):}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM#hj4'hhubj)}(hNFor our first real time task this would request 20% memory b/w on socket 0. ::h]hKFor our first real time task this would request 20% memory b/w on socket 0.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM'hj4'hhubj )}(h;# echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schematah]h;# echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata}hj(sbah}(h]h ]h"]h$]h&]hhuh1j hhhM*hj4'hhubj)}(hXFor our second real time task this would request an other 20% memory b/w on socket 0. ::h]hUFor our second real time task this would request an other 20% memory b/w on socket 0.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM,hj4'hhubj )}(h;# echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schematah]h;# echo -e "L3:0=f8000;1=fffff\nMB:0=20;1=100" > p0/schemata}hj(sbah}(h]h ]h"]h$]h&]hhuh1j hhhM0hj4'hhubj)}(hhh]j)}(h Example 3 h]j)}(h Example 3h]h Example 3}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM2hj(ubah}(h]h ]h"]h$]h&]uh1jhj(hhhhhNubah}(h]h ]h"]h$]h&]jjjhjjjd!Kuh1jhj4'hhhhhM2ubj)}(hX8A single socket system which has real-time tasks running on core 4-7 and non real-time workload assigned to core 0-3. The real-time tasks share text and data, so a per task association is not required and due to interaction with the kernel it's desired that the kernel on these cores shares L3 with the tasks. ::h]hX7A single socket system which has real-time tasks running on core 4-7 and non real-time workload assigned to core 0-3. The real-time tasks share text and data, so a per task association is not required and due to interaction with the kernel it’s desired that the kernel on these cores shares L3 with the tasks.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM4hj4'hhubj )}(h?# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrlh]h?# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl}hj)sbah}(h]h ]h"]h$]h&]hhuh1j hhhM;hj4'hhubj)}(hFirst we reset the schemata for the default group so that the "upper" 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0 cannot be used by ordinary tasks::h]hFirst we reset the schemata for the default group so that the “upper” 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0 cannot be used by ordinary tasks:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM>hj4'hhubj )}(h%# echo "L3:0=3ff\nMB:0=50" > schematah]h%# echo "L3:0=3ff\nMB:0=50" > schemata}hj")sbah}(h]h ]h"]h$]h&]hhuh1j hhhMBhj4'hhubj)}(hNext we make a resource group for our real time cores and give it access to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on socket 0. ::h]hNext we make a resource group for our real time cores and give it access to the “top” 50% of the cache on socket 0 and 50% of memory bandwidth on socket 0.}(hj0)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMDhj4'hhubj )}(h5# mkdir p0 # echo "L3:0=ffc00\nMB:0=50" > p0/schematah]h5# mkdir p0 # echo "L3:0=ffc00\nMB:0=50" > p0/schemata}hj>)sbah}(h]h ]h"]h$]h&]hhuh1j hhhMIhj4'hhubj)}(hXFinally we move core 4-7 over to the new group and make sure that the kernel and the tasks running there get 50% of the cache. They should also get 50% of memory bandwidth assuming that the cores 4-7 are SMT siblings and only the real time threads are scheduled on the cores 4-7. ::h]hXFinally we move core 4-7 over to the new group and make sure that the kernel and the tasks running there get 50% of the cache. They should also get 50% of memory bandwidth assuming that the cores 4-7 are SMT siblings and only the real time threads are scheduled on the cores 4-7.}(hjL)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMLhj4'hhubj )}(h# echo F0 > p0/cpush]h# echo F0 > p0/cpus}hjZ)sbah}(h]h ]h"]h$]h&]hhuh1j hhhMRhj4'hhubj)}(hhh]j)}(h Example 4 h]j)}(h Example 4h]h Example 4}(hjo)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMThjk)ubah}(h]h ]h"]h$]h&]uh1jhjh)hhhhhNubah}(h]h ]h"]h$]h&]jjjhjjjd!Kuh1jhj4'hhhhhMTubj)}(hXThe resource groups in previous examples were all in the default "shareable" mode allowing sharing of their cache allocations. If one resource group configures a cache allocation then nothing prevents another resource group to overlap with that allocation.h]hXThe resource groups in previous examples were all in the default “shareable” mode allowing sharing of their cache allocations. If one resource group configures a cache allocation then nothing prevents another resource group to overlap with that allocation.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMVhj4'hhubj)}(hIn this example a new exclusive resource group will be created on a L2 CAT system with two L2 cache instances that can be configured with an 8-bit capacity bitmask. The new exclusive resource group will be configured to use 25% of each cache instance. ::h]hIn this example a new exclusive resource group will be created on a L2 CAT system with two L2 cache instances that can be configured with an 8-bit capacity bitmask. The new exclusive resource group will be configured to use 25% of each cache instance.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM[hj4'hhubj )}(h@# mount -t resctrl resctrl /sys/fs/resctrl/ # cd /sys/fs/resctrlh]h@# mount -t resctrl resctrl /sys/fs/resctrl/ # cd /sys/fs/resctrl}hj)sbah}(h]h ]h"]h$]h&]hhuh1j hhhMahj4'hhubj)}(hTFirst, we observe that the default group is configured to allocate to all L2 cache::h]hSFirst, we observe that the default group is configured to allocate to all L2 cache:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMdhj4'hhubj )}(h# cat schemata L2:0=ff;1=ffh]h# cat schemata L2:0=ff;1=ff}hj)sbah}(h]h ]h"]h$]h&]hhuh1j hhhMghj4'hhubj)}(hWe could attempt to create the new resource group at this point, but it will fail because of the overlap with the schemata of the default group::h]hWe could attempt to create the new resource group at this point, but it will fail because of the overlap with the schemata of the default group:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMjhj4'hhubj )}(h# mkdir p0 # echo 'L2:0=0x3;1=0x3' > p0/schemata # cat p0/mode shareable # echo exclusive > p0/mode -sh: echo: write error: Invalid argument # cat info/last_cmd_status schemata overlapsh]h# mkdir p0 # echo 'L2:0=0x3;1=0x3' > p0/schemata # cat p0/mode shareable # echo exclusive > p0/mode -sh: echo: write error: Invalid argument # cat info/last_cmd_status schemata overlaps}hj)sbah}(h]h ]h"]h$]h&]hhuh1j hhhMmhj4'hhubj)}(hTo ensure that there is no overlap with another resource group the default resource group's schemata has to change, making it possible for the new resource group to become exclusive. ::h]hTo ensure that there is no overlap with another resource group the default resource group’s schemata has to change, making it possible for the new resource group to become exclusive.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMvhj4'hhubj )}(h# echo 'L2:0=0xfc;1=0xfc' > schemata # echo exclusive > p0/mode # grep . p0/* p0/cpus:0 p0/mode:exclusive p0/schemata:L2:0=03;1=03 p0/size:L2:0=262144;1=262144h]h# echo 'L2:0=0xfc;1=0xfc' > schemata # echo exclusive > p0/mode # grep . p0/* p0/cpus:0 p0/mode:exclusive p0/schemata:L2:0=03;1=03 p0/size:L2:0=262144;1=262144}hj)sbah}(h]h ]h"]h$]h&]hhuh1j hhhM{hj4'hhubj)}(hTA new resource group will on creation not overlap with an exclusive resource group::h]hSA new resource group will on creation not overlap with an exclusive resource group:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(hj# mkdir p1 # grep . p1/* p1/cpus:0 p1/mode:shareable p1/schemata:L2:0=fc;1=fc p1/size:L2:0=786432;1=786432h]hj# mkdir p1 # grep . p1/* p1/cpus:0 p1/mode:shareable p1/schemata:L2:0=fc;1=fc p1/size:L2:0=786432;1=786432}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(h2The bit_usage will reflect how the cache is used::h]h1The bit_usage will reflect how the cache is used:}(hj#*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h-# cat info/L2/bit_usage 0=SSSSSSEE;1=SSSSSSEEh]h-# cat info/L2/bit_usage 0=SSSSSSEE;1=SSSSSSEE}hj1*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubj)}(hOA resource group cannot be forced to overlap with an exclusive resource group::h]hNA resource group cannot be forced to overlap with an exclusive resource group:}(hj?*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj4'hhubj )}(h# echo 'L2:0=0x1;1=0x1' > p1/schemata -sh: echo: write error: Invalid argument # cat info/last_cmd_status overlaps with exclusive grouph]h# echo 'L2:0=0x1;1=0x1' > p1/schemata -sh: echo: write error: Invalid argument # cat info/last_cmd_status overlaps with exclusive group}hjM*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj4'hhubeh}(h]!examples-for-rdt-allocation-usageah ]h"]!examples for rdt allocation usageah$]h&]uh1j[hj%hhhhhMubj\)}(hhh](ja)}(hExample of Cache Pseudo-Lockingh]hExample of Cache Pseudo-Locking}(hjf*hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjc*hhhhhMubj)}(hLock portion of L2 cache from cache id 1 using CBM 0x3. Pseudo-locked region is exposed at /dev/pseudo_lock/newlock that can be provided to application for argument to mmap(). ::h]hLock portion of L2 cache from cache id 1 using CBM 0x3. Pseudo-locked region is exposed at /dev/pseudo_lock/newlock that can be provided to application for argument to mmap().}(hjt*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjc*hhubj )}(h@# mount -t resctrl resctrl /sys/fs/resctrl/ # cd /sys/fs/resctrlh]h@# mount -t resctrl resctrl /sys/fs/resctrl/ # cd /sys/fs/resctrl}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjc*hhubj)}(hEnsure that there are bits available that can be pseudo-locked, since only unused bits can be pseudo-locked the bits to be pseudo-locked needs to be removed from the default resource group's schemata::h]hEnsure that there are bits available that can be pseudo-locked, since only unused bits can be pseudo-locked the bits to be pseudo-locked needs to be removed from the default resource group’s schemata:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjc*hhubj )}(hy# cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSSSS # echo 'L2:1=0xfc' > schemata # cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSS00h]hy# cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSSSS # echo 'L2:1=0xfc' > schemata # cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSS00}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjc*hhubj)}(hCreate a new resource group that will be associated with the pseudo-locked region, indicate that it will be used for a pseudo-locked region, and configure the requested pseudo-locked region capacity bitmask::h]hCreate a new resource group that will be associated with the pseudo-locked region, indicate that it will be used for a pseudo-locked region, and configure the requested pseudo-locked region capacity bitmask:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjc*hhubj )}(h[# mkdir newlock # echo pseudo-locksetup > newlock/mode # echo 'L2:1=0x3' > newlock/schematah]h[# mkdir newlock # echo pseudo-locksetup > newlock/mode # echo 'L2:1=0x3' > newlock/schemata}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjc*hhubj)}(hOn success the resource group's mode will change to pseudo-locked, the bit_usage will reflect the pseudo-locked region, and the character device exposing the pseudo-locked region will exist::h]hOn success the resource group’s mode will change to pseudo-locked, the bit_usage will reflect the pseudo-locked region, and the character device exposing the pseudo-locked region will exist:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjc*hhubj )}(h# cat newlock/mode pseudo-locked # cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSSPP # ls -l /dev/pseudo_lock/newlock crw------- 1 root root 243, 0 Apr 3 05:01 /dev/pseudo_lock/newlockh]h# cat newlock/mode pseudo-locked # cat info/L2/bit_usage 0=SSSSSSSS;1=SSSSSSPP # ls -l /dev/pseudo_lock/newlock crw------- 1 root root 243, 0 Apr 3 05:01 /dev/pseudo_lock/newlock}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjc*hhubj )}(hX/* * Example code to access one page of pseudo-locked cache region * from user space. */ #define _GNU_SOURCE #include #include #include #include #include #include /* * It is required that the application runs with affinity to only * cores associated with the pseudo-locked region. Here the cpu * is hardcoded for convenience of example. */ static int cpuid = 2; int main(int argc, char *argv[]) { cpu_set_t cpuset; long page_size; void *mapping; int dev_fd; int ret; page_size = sysconf(_SC_PAGESIZE); CPU_ZERO(&cpuset); CPU_SET(cpuid, &cpuset); ret = sched_setaffinity(0, sizeof(cpuset), &cpuset); if (ret < 0) { perror("sched_setaffinity"); exit(EXIT_FAILURE); } dev_fd = open("/dev/pseudo_lock/newlock", O_RDWR); if (dev_fd < 0) { perror("open"); exit(EXIT_FAILURE); } mapping = mmap(0, page_size, PROT_READ | PROT_WRITE, MAP_SHARED, dev_fd, 0); if (mapping == MAP_FAILED) { perror("mmap"); close(dev_fd); exit(EXIT_FAILURE); } /* Application interacts with pseudo-locked memory @mapping */ ret = munmap(mapping, page_size); if (ret < 0) { perror("munmap"); close(dev_fd); exit(EXIT_FAILURE); } close(dev_fd); exit(EXIT_SUCCESS); }h]hX/* * Example code to access one page of pseudo-locked cache region * from user space. */ #define _GNU_SOURCE #include #include #include #include #include #include /* * It is required that the application runs with affinity to only * cores associated with the pseudo-locked region. Here the cpu * is hardcoded for convenience of example. */ static int cpuid = 2; int main(int argc, char *argv[]) { cpu_set_t cpuset; long page_size; void *mapping; int dev_fd; int ret; page_size = sysconf(_SC_PAGESIZE); CPU_ZERO(&cpuset); CPU_SET(cpuid, &cpuset); ret = sched_setaffinity(0, sizeof(cpuset), &cpuset); if (ret < 0) { perror("sched_setaffinity"); exit(EXIT_FAILURE); } dev_fd = open("/dev/pseudo_lock/newlock", O_RDWR); if (dev_fd < 0) { perror("open"); exit(EXIT_FAILURE); } mapping = mmap(0, page_size, PROT_READ | PROT_WRITE, MAP_SHARED, dev_fd, 0); if (mapping == MAP_FAILED) { perror("mmap"); close(dev_fd); exit(EXIT_FAILURE); } /* Application interacts with pseudo-locked memory @mapping */ ret = munmap(mapping, page_size); if (ret < 0) { perror("munmap"); close(dev_fd); exit(EXIT_FAILURE); } close(dev_fd); exit(EXIT_SUCCESS); }}hj*sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhjc*hhubeh}(h]example-of-cache-pseudo-lockingah ]h"]example of cache pseudo-lockingah$]h&]uh1j[hj%hhhhhMubeh}(h](cache-pseudo-locking-debugging-interfaceah ]h"](cache pseudo-locking debugging interfaceah$]h&]uh1j[hj#hhhhhMlubj\)}(hhh](ja)}(hLocking between applicationsh]hLocking between applications}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj+hhhhhMubj)}(hmCertain operations on the resctrl filesystem, composed of read/writes to/from multiple files, must be atomic.h]hmCertain operations on the resctrl filesystem, composed of read/writes to/from multiple files, must be atomic.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubj)}(hOAs an example, the allocation of an exclusive reservation of L3 cache involves:h]hOAs an example, the allocation of an exclusive reservation of L3 cache involves:}(hj!+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubjR )}(hX1. Read the cbmmasks from each directory or the per-resource "bit_usage" 2. Find a contiguous set of bits in the global CBM bitmask that is clear in any of the directory cbmmasks 3. Create a new directory 4. Set the bits found in step 2 to the new directory "schemata" file h]j)}(hhh](j)}(hERead the cbmmasks from each directory or the per-resource "bit_usage"h]j)}(hj8+h]hIRead the cbmmasks from each directory or the per-resource “bit_usage”}(hj:+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj6+ubah}(h]h ]h"]h$]h&]uh1jhj3+ubj)}(hfFind a contiguous set of bits in the global CBM bitmask that is clear in any of the directory cbmmasksh]j)}(hfFind a contiguous set of bits in the global CBM bitmask that is clear in any of the directory cbmmasksh]hfFind a contiguous set of bits in the global CBM bitmask that is clear in any of the directory cbmmasks}(hjQ+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjM+ubah}(h]h ]h"]h$]h&]uh1jhj3+ubj)}(hCreate a new directoryh]j)}(hjg+h]hCreate a new directory}(hji+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhje+ubah}(h]h ]h"]h$]h&]uh1jhj3+ubj)}(hBSet the bits found in step 2 to the new directory "schemata" file h]j)}(hASet the bits found in step 2 to the new directory "schemata" fileh]hESet the bits found in step 2 to the new directory “schemata” file}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj|+ubah}(h]h ]h"]h$]h&]uh1jhj3+ubeh}(h]h ]h"]h$]h&]jjjhjj4!uh1jhj/+ubah}(h]h ]h"]h$]h&]uh1jQ hhhM hj+hhubj)}(hIf two applications attempt to allocate space concurrently then they can end up allocating the same bits so the reservations are shared instead of exclusive.h]hIf two applications attempt to allocate space concurrently then they can end up allocating the same bits so the reservations are shared instead of exclusive.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubj)}(hTo coordinate atomic operations on the resctrlfs and to avoid the problem above, the following locking procedure is recommended:h]hTo coordinate atomic operations on the resctrlfs and to avoid the problem above, the following locking procedure is recommended:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubj)}(hXLocking is based on flock, which is available in libc and also as a shell script commandh]hXLocking is based on flock, which is available in libc and also as a shell script command}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubj)}(h Write lock:h]h Write lock:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+hhubjR )}(h\A) Take flock(LOCK_EX) on /sys/fs/resctrl B) Read/write the directory structure. C) funlock h]j)}(hhh](j)}(h&Take flock(LOCK_EX) on /sys/fs/resctrlh]j)}(hj+h]h&Take flock(LOCK_EX) on /sys/fs/resctrl}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(h#Read/write the directory structure.h]j)}(hj+h]h#Read/write the directory structure.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hfunlock h]j)}(hfunlockh]hfunlock}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ,ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]j upperalphajhjjuh1jhj+ubah}(h]h ]h"]h$]h&]uh1jQ hhhMhj+hhubj)}(h Read lock:h]h Read lock:}(hj2,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM!hj+hhubjR )}(haA) Take flock(LOCK_SH) on /sys/fs/resctrl B) If success read the directory structure. C) funlock h]j)}(hhh](j)}(h&Take flock(LOCK_SH) on /sys/fs/resctrlh]j)}(hjI,h]h&Take flock(LOCK_SH) on /sys/fs/resctrl}(hjK,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM#hjG,ubah}(h]h ]h"]h$]h&]uh1jhjD,ubj)}(h(If success read the directory structure.h]j)}(hj`,h]h(If success read the directory structure.}(hjb,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM$hj^,ubah}(h]h ]h"]h$]h&]uh1jhjD,ubj)}(hfunlock h]j)}(hfunlockh]hfunlock}(hjy,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM%hju,ubah}(h]h ]h"]h$]h&]uh1jhjD,ubeh}(h]h ]h"]h$]h&]jj+,jhjjuh1jhj@,ubah}(h]h ]h"]h$]h&]uh1jQ hhhM#hj+hhubj)}(hExample with bash::h]hExample with bash:}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM'hj+hhubj )}(hXX# Atomically read directory structure $ flock -s /sys/fs/resctrl/ find /sys/fs/resctrl # Read directory contents and create new subdirectory $ cat create-dir.sh find /sys/fs/resctrl/ > output.txt mask = function-of(output.txt) mkdir /sys/fs/resctrl/newres/ echo mask > /sys/fs/resctrl/newres/schemata $ flock /sys/fs/resctrl/ ./create-dir.shh]hXX# Atomically read directory structure $ flock -s /sys/fs/resctrl/ find /sys/fs/resctrl # Read directory contents and create new subdirectory $ cat create-dir.sh find /sys/fs/resctrl/ > output.txt mask = function-of(output.txt) mkdir /sys/fs/resctrl/newres/ echo mask > /sys/fs/resctrl/newres/schemata $ flock /sys/fs/resctrl/ ./create-dir.sh}hj,sbah}(h]h ]h"]h$]h&]hhuh1j hhhM)hj+hhubj)}(hExample with C::h]hExample with C:}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM6hj+hhubj )}(hX/* * Example code do take advisory locks * before accessing resctrl filesystem */ #include #include void resctrl_take_shared_lock(int fd) { int ret; /* take shared lock on resctrl filesystem */ ret = flock(fd, LOCK_SH); if (ret) { perror("flock"); exit(-1); } } void resctrl_take_exclusive_lock(int fd) { int ret; /* release lock on resctrl filesystem */ ret = flock(fd, LOCK_EX); if (ret) { perror("flock"); exit(-1); } } void resctrl_release_lock(int fd) { int ret; /* take shared lock on resctrl filesystem */ ret = flock(fd, LOCK_UN); if (ret) { perror("flock"); exit(-1); } } void main(void) { int fd, ret; fd = open("/sys/fs/resctrl", O_DIRECTORY); if (fd == -1) { perror("open"); exit(-1); } resctrl_take_shared_lock(fd); /* code to read directory contents */ resctrl_release_lock(fd); resctrl_take_exclusive_lock(fd); /* code to read and write directory contents */ resctrl_release_lock(fd); }h]hX/* * Example code do take advisory locks * before accessing resctrl filesystem */ #include #include void resctrl_take_shared_lock(int fd) { int ret; /* take shared lock on resctrl filesystem */ ret = flock(fd, LOCK_SH); if (ret) { perror("flock"); exit(-1); } } void resctrl_take_exclusive_lock(int fd) { int ret; /* release lock on resctrl filesystem */ ret = flock(fd, LOCK_EX); if (ret) { perror("flock"); exit(-1); } } void resctrl_release_lock(int fd) { int ret; /* take shared lock on resctrl filesystem */ ret = flock(fd, LOCK_UN); if (ret) { perror("flock"); exit(-1); } } void main(void) { int fd, ret; fd = open("/sys/fs/resctrl", O_DIRECTORY); if (fd == -1) { perror("open"); exit(-1); } resctrl_take_shared_lock(fd); /* code to read directory contents */ resctrl_release_lock(fd); resctrl_take_exclusive_lock(fd); /* code to read and write directory contents */ resctrl_release_lock(fd); }}hj,sbah}(h]h ]h"]h$]h&]hhuh1j hhhM8hj+hhubeh}(h]locking-between-applicationsah ]h"]locking between applicationsah$]h&]uh1j[hj#hhhhhMubeh}(h]cache-pseudo-lockingah ]h"]cache pseudo-lockingah$]h&]uh1j[hj]hhhhhMubj\)}(hhh](ja)}(h7Examples for RDT Monitoring along with allocation usageh]h7Examples for RDT Monitoring along with allocation usage}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj,hhhhhMvubj\)}(hhh](ja)}(hReading monitored datah]hReading monitored data}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj,hhhhhMxubj)}(hReading an event file (for ex: mon_data/mon_L3_00/llc_occupancy) would show the current snapshot of LLC occupancy of the corresponding MON group or CTRL_MON group.h]hReading an event file (for ex: mon_data/mon_L3_00/llc_occupancy) would show the current snapshot of LLC occupancy of the corresponding MON group or CTRL_MON group.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMyhj,hhubeh}(h]reading-monitored-dataah ]h"]reading monitored dataah$]h&]uh1j[hj,hhhhhMxubj\)}(hhh](ja)}(hHExample 1 (Monitor CTRL_MON group and subset of tasks in CTRL_MON group)h]hHExample 1 (Monitor CTRL_MON group and subset of tasks in CTRL_MON group)}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj-hhhhhMubj)}(h[On a two socket machine (one L3 cache per socket) with just four bits for cache bit masks::h]hZOn a two socket machine (one L3 cache per socket) with just four bits for cache bit masks:}(hj*-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1 # echo "L3:0=3;1=c" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3" > /sys/fs/resctrl/p1/schemata # echo 5678 > p1/tasks # echo 5679 > p1/tasksh]h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1 # echo "L3:0=3;1=c" > /sys/fs/resctrl/p0/schemata # echo "L3:0=3;1=3" > /sys/fs/resctrl/p1/schemata # echo 5678 > p1/tasks # echo 5679 > p1/tasks}hj8-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubj)}(h~The default resource group is unmodified, so we have access to all parts of all caches (its schemata file reads "L3:0=f;1=f").h]hThe default resource group is unmodified, so we have access to all parts of all caches (its schemata file reads “L3:0=f;1=f”).}(hjF-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj)}(hTasks that are under the control of group "p0" may only allocate from the "lower" 50% on cache ID 0, and the "upper" 50% of cache ID 1. Tasks in group "p1" use the "lower" 50% of cache on both sockets.h]hTasks that are under the control of group “p0” may only allocate from the “lower” 50% on cache ID 0, and the “upper” 50% of cache ID 1. Tasks in group “p1” use the “lower” 50% of cache on both sockets.}(hjT-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj)}(hLCreate monitor groups and assign a subset of tasks to each monitor group. ::h]hICreate monitor groups and assign a subset of tasks to each monitor group.}(hjb-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(hb# cd /sys/fs/resctrl/p1/mon_groups # mkdir m11 m12 # echo 5678 > m11/tasks # echo 5679 > m12/tasksh]hb# cd /sys/fs/resctrl/p1/mon_groups # mkdir m11 m12 # echo 5678 > m11/tasks # echo 5679 > m12/tasks}hjp-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubj)}(h#fetch data (data shown in bytes) ::h]h fetch data (data shown in bytes)}(hj~-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(h# cat m11/mon_data/mon_L3_00/llc_occupancy 16234000 # cat m11/mon_data/mon_L3_01/llc_occupancy 14789000 # cat m12/mon_data/mon_L3_00/llc_occupancy 16789000h]h# cat m11/mon_data/mon_L3_00/llc_occupancy 16234000 # cat m11/mon_data/mon_L3_01/llc_occupancy 14789000 # cat m12/mon_data/mon_L3_00/llc_occupancy 16789000}hj-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubj)}(h7The parent ctrl_mon group shows the aggregated data. ::h]h4The parent ctrl_mon group shows the aggregated data.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(hB# cat /sys/fs/resctrl/p1/mon_data/mon_l3_00/llc_occupancy 31234000h]hB# cat /sys/fs/resctrl/p1/mon_data/mon_l3_00/llc_occupancy 31234000}hj-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubeh}(h]Fexample-1-monitor-ctrl-mon-group-and-subset-of-tasks-in-ctrl-mon-groupah ]h"]Hexample 1 (monitor ctrl_mon group and subset of tasks in ctrl_mon group)ah$]h&]uh1j[hj,hhhhhMubj\)}(hhh](ja)}(h,Example 2 (Monitor a task from its creation)h]h,Example 2 (Monitor a task from its creation)}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj-hhhhhMubj)}(h3On a two socket machine (one L3 cache per socket)::h]h2On a two socket machine (one L3 cache per socket):}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(hM# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1h]hM# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p0 p1}hj-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubj)}(hoAn RMID is allocated to the group once its created and hence the below is monitored from its creation. ::h]hlAn RMID is allocated to the group once its created and hence the below is monitored from its creation.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(h,# echo $$ > /sys/fs/resctrl/p1/tasks # h]h,# echo $$ > /sys/fs/resctrl/p1/tasks # }hj-sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubj)}(hFetch the data::h]hFetch the data:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj-hhubj )}(hB# cat /sys/fs/resctrl/p1/mon_data/mon_l3_00/llc_occupancy 31789000h]hB# cat /sys/fs/resctrl/p1/mon_data/mon_l3_00/llc_occupancy 31789000}hj.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj-hhubeh}(h]*example-2-monitor-a-task-from-its-creationah ]h"],example 2 (monitor a task from its creation)ah$]h&]uh1j[hj,hhhhhMubj\)}(hhh](ja)}(hEExample 3 (Monitor without CAT support or before creating CAT groups)h]hEExample 3 (Monitor without CAT support or before creating CAT groups)}(hj..hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj+.hhhhhMubj)}(hXAssume a system like HSW has only CQM and no CAT support. In this case the resctrl will still mount but cannot create CTRL_MON directories. But user can create different MON groups within the root group thereby able to monitor all tasks including kernel threads.h]hXAssume a system like HSW has only CQM and no CAT support. In this case the resctrl will still mount but cannot create CTRL_MON directories. But user can create different MON groups within the root group thereby able to monitor all tasks including kernel threads.}(hj<.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+.hhubj)}(hThis can also be used to profile jobs cache size footprint before being able to allocate them to different allocation groups. ::h]h}This can also be used to profile jobs cache size footprint before being able to allocate them to different allocation groups.}(hjJ.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+.hhubj )}(h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir mon_groups/m01 # mkdir mon_groups/m02 # echo 3478 > /sys/fs/resctrl/mon_groups/m01/tasks # echo 2467 > /sys/fs/resctrl/mon_groups/m02/tasksh]h# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir mon_groups/m01 # mkdir mon_groups/m02 # echo 3478 > /sys/fs/resctrl/mon_groups/m01/tasks # echo 2467 > /sys/fs/resctrl/mon_groups/m02/tasks}hjX.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj+.hhubj)}(hMonitor the groups separately and also get per domain data. From the below its apparent that the tasks are mostly doing work on domain(socket) 0. ::h]hMonitor the groups separately and also get per domain data. From the below its apparent that the tasks are mostly doing work on domain(socket) 0.}(hjf.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+.hhubj )}(hX# cat /sys/fs/resctrl/mon_groups/m01/mon_L3_00/llc_occupancy 31234000 # cat /sys/fs/resctrl/mon_groups/m01/mon_L3_01/llc_occupancy 34555 # cat /sys/fs/resctrl/mon_groups/m02/mon_L3_00/llc_occupancy 31234000 # cat /sys/fs/resctrl/mon_groups/m02/mon_L3_01/llc_occupancy 32789h]hX# cat /sys/fs/resctrl/mon_groups/m01/mon_L3_00/llc_occupancy 31234000 # cat /sys/fs/resctrl/mon_groups/m01/mon_L3_01/llc_occupancy 34555 # cat /sys/fs/resctrl/mon_groups/m02/mon_L3_00/llc_occupancy 31234000 # cat /sys/fs/resctrl/mon_groups/m02/mon_L3_01/llc_occupancy 32789}hjt.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj+.hhubeh}(h]Cexample-3-monitor-without-cat-support-or-before-creating-cat-groupsah ]h"]Eexample 3 (monitor without cat support or before creating cat groups)ah$]h&]uh1j[hj,hhhhhMubj\)}(hhh](ja)}(h#Example 4 (Monitor real time tasks)h]h#Example 4 (Monitor real time tasks)}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj.hhhhhMubj)}(hA single socket system which has real time tasks running on cores 4-7 and non real time tasks on other cpus. We want to monitor the cache occupancy of the real time threads on these cores. ::h]hA single socket system which has real time tasks running on cores 4-7 and non real time tasks on other cpus. We want to monitor the cache occupancy of the real time threads on these cores.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(hJ# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p1h]hJ# mount -t resctrl resctrl /sys/fs/resctrl # cd /sys/fs/resctrl # mkdir p1}hj.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(hMove the cpus 4-7 over to p1::h]hMove the cpus 4-7 over to p1:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(h# echo f0 > p1/cpush]h# echo f0 > p1/cpus}hj.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(h!View the llc occupancy snapshot::h]h View the llc occupancy snapshot:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(hB# cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/llc_occupancy 11234000h]hB# cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/llc_occupancy 11234000}hj.sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubeh}(h]!example-4-monitor-real-time-tasksah ]h"]#example 4 (monitor real time tasks)ah$]h&]uh1j[hj,hhhhhMubeh}(h]7examples-for-rdt-monitoring-along-with-allocation-usageah ]h"]7examples for rdt monitoring along with allocation usageah$]h&]uh1j[hj]hhhhhMvubj\)}(hhh](ja)}(h(Examples on working with mbm_assign_modeh]h(Examples on working with mbm_assign_mode}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj.hhhhhMubj)}(h8a. Check if MBM counter assignment mode is supported. ::h]h5a. Check if MBM counter assignment mode is supported.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(hr# mount -t resctrl resctrl /sys/fs/resctrl/ # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] defaulth]hr# mount -t resctrl resctrl /sys/fs/resctrl/ # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] default}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(h-The "mbm_event" mode is detected and enabled.h]h1The “mbm_event” mode is detected and enabled.}(hj,/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj)}(h7b. Check how many assignable counters are supported. ::h]h4b. Check how many assignable counters are supported.}(hj:/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(h9# cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs 0=32;1=32h]h9# cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs 0=32;1=32}hjH/sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(hUc. Check how many assignable counters are available for assignment in each domain. ::h]hRc. Check how many assignable counters are available for assignment in each domain.}(hjV/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj.hhubj )}(h?# cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs 0=30;1=30h]h?# cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs 0=30;1=30}hjd/sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(h0d. To list the default group's assign states. ::h]h/d. To list the default group’s assign states.}(hjr/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(hX# cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=eh]hX# cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(hUe. To unassign the counter associated with the mbm_total_bytes event on domain 0. ::h]hRe. To unassign the counter associated with the mbm_total_bytes event on domain 0.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj.hhubj )}(h# echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=e}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhMhj.hhubj)}(hWf. To unassign the counter associated with the mbm_total_bytes event on all domains. ::h]hTf. To unassign the counter associated with the mbm_total_bytes event on all domains.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj.hhubj )}(h# echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignment mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignment mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=e}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhM#hj.hhubj)}(heg. To assign a counter associated with the mbm_total_bytes event on all domains in exclusive mode. ::h]hbg. To assign a counter associated with the mbm_total_bytes event on all domains in exclusive mode.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM(hj.hhubj )}(h# echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=eh]h# echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments # cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhM,hj.hhubj)}(hh. Read the events mbm_total_bytes and mbm_local_bytes of the default group. There is no change in reading the events with the assignment. ::h]hh. Read the events mbm_total_bytes and mbm_local_bytes of the default group. There is no change in reading the events with the assignment.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM1hj.hhubj )}(hX # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_bytes 779247936 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_total_bytes 562324232 # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes 212122123 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes 121212144h]hX # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_bytes 779247936 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_total_bytes 562324232 # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes 212122123 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes 121212144}hj/sbah}(h]h ]h"]h$]h&]hhuh1j hhhM5hj.hhubj)}(h%i. Check the event configurations. ::h]h"i. Check the event configurations.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM>hj.hhubj )}(hXp# cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memoryh]hXp# cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory}hj 0sbah}(h]h ]h"]h$]h&]hhuh1j hhhMAhj.hhubj)}(h9j. Change the event configuration for mbm_local_bytes. ::h]h6j. Change the event configuration for mbm_local_bytes.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMHhj.hhubj )}(hX8# echo "local_reads, local_non_temporal_writes, local_reads_slow_memory, remote_reads" > /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory,remote_readsh]hX8# echo "local_reads, local_non_temporal_writes, local_reads_slow_memory, remote_reads" > /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory,remote_reads}hj(0sbah}(h]h ]h"]h$]h&]hhuh1j hhhMKhj.hhubj)}(hk. Now read the local events again. The first read may come back with "Unavailable" status. The subsequent read of mbm_local_bytes will display the current value. ::h]hk. Now read the local events again. The first read may come back with “Unavailable” status. The subsequent read of mbm_local_bytes will display the current value.}(hj60hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMQhj.hhubj )}(hX # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes Unavailable # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes 2252323 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes Unavailable # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes 1566565h]hX # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes Unavailable # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes 2252323 # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes Unavailable # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes 1566565}hjD0sbah}(h]h ]h"]h$]h&]hhuh1j hhhMUhj.hhubj)}(hl. Users have the option to go back to 'default' mbm_assign_mode if required. This can be done using the following command. Note that switching the mbm_assign_mode may reset all the MBM counters (and thus all MBM events) of all the resctrl groups. ::h]hl. Users have the option to go back to ‘default’ mbm_assign_mode if required. This can be done using the following command. Note that switching the mbm_assign_mode may reset all the MBM counters (and thus all MBM events) of all the resctrl groups.}(hjR0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM^hj.hhubj )}(h# echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode mbm_event [default]h]h# echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode mbm_event [default]}hj`0sbah}(h]h ]h"]h$]h&]hhuh1j hhhMchj.hhubj)}(h%m. Unmount the resctrl filesystem. ::h]h"m. Unmount the resctrl filesystem.}(hjn0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhhj.hhubj )}(h# umount /sys/fs/resctrl/h]h# umount /sys/fs/resctrl/}hj|0sbah}(h]h ]h"]h$]h&]hhuh1j hhhMkhj.hhubeh}(h](examples-on-working-with-mbm-assign-modeah ]h"](examples on working with mbm_assign_modeah$]h&]uh1j[hj]hhhhhMubj\)}(hhh](ja)}(hIntel RDT Erratah]hIntel RDT Errata}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj0hhhhhMnubj\)}(hhh](ja)}(hAIntel MBM Counters May Report System Memory Bandwidth Incorrectlyh]hAIntel MBM Counters May Report System Memory Bandwidth Incorrectly}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj0hhhhhMqubj)}(h@Errata SKX99 for Skylake server and BDF102 for Broadwell server.h]h@Errata SKX99 for Skylake server and BDF102 for Broadwell server.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMshj0hhubj)}(hXProblem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics according to the assigned Resource Monitor ID (RMID) for that logical core. The IA32_QM_CTR register (MSR 0xC8E), used to report these metrics, may report incorrect system bandwidth for certain RMID values.h]hXProblem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics according to the assigned Resource Monitor ID (RMID) for that logical core. The IA32_QM_CTR register (MSR 0xC8E), used to report these metrics, may report incorrect system bandwidth for certain RMID values.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMuhj0hhubj)}(hWImplication: Due to the errata, system memory bandwidth may not match what is reported.h]hWImplication: Due to the errata, system memory bandwidth may not match what is reported.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMzhj0hhubj)}(hjWorkaround: MBM total and local readings are corrected according to the following correction factor table:h]hjWorkaround: MBM total and local readings are corrected according to the following correction factor table:}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM}hj0hhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj0ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj0ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj0ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj0ubj)}(hhh](j)}(hhh](j)}(hhh]j)}(h core counth]h core count}(hj#1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj 1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(h rmid counth]h rmid count}(hj:1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj71ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(hrmid thresholdh]hrmid threshold}(hjQ1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjN1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(hcorrection factorh]hcorrection factor}(hjh1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhje1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hjh]h1}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(h8h]h8}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(hjh]h0}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(h1.000000h]h1.000000}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hj}h]h2}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(h16h]h16}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(hjh]h0}(hj2hhhNh`Nubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]j)}(h1.000000h]h1.000000}(hj.2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj+2ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hjFh]h3}(hjN2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjK2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubj)}(hhh]j)}(h24h]h24}(hjd2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhja2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubj)}(hhh]j)}(h15h]h15}(hj{2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjx2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubj)}(hhh]j)}(h0.969650h]h0.969650}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hjh]h4}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]j)}(h32h]h32}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]j)}(hjh]h0}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]j)}(h1.000000h]h1.000000}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hjh]h6}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]j)}(h48h]h48}(hj+3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj(3ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]j)}(h31h]h31}(hjB3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj?3ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]j)}(h0.969650h]h0.969650}(hjY3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjV3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(h7h]h7}(hjy3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjv3ubah}(h]h ]h"]h$]h&]uh1jhjs3ubj)}(hhh]j)}(h56h]h56}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhjs3ubj)}(hhh]j)}(h47h]h47}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhjs3ubj)}(hhh]j)}(h1.142857h]h1.142857}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhjs3ubeh}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh](j)}(hhh]j)}(hj1h]h8}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj3ubah}(h]h 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values should be multiplied by the correction factor.h]hcIf rmid > rmid threshold, MBM total and local values should be multiplied by the correction factor.}(hj,<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj0hhubj)}(hSee:h]hSee:}(hj:<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj0hhubj)}(h1. Erratum SKX99 in Intel Xeon Processor Scalable Family Specification Update: http://web.archive.org/web/20200716124958/https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.htmlh](hO1. Erratum SKX99 in Intel Xeon Processor Scalable Family Specification Update: }(hjH<hhhNhNubj)}(hhttp://web.archive.org/web/20200716124958/https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.htmlh]hhttp://web.archive.org/web/20200716124958/https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.html}(hjP<hhhNhNubah}(h]h ]h"]h$]h&]refurijR<uh1jhjH<ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj0hhubj)}(h2. Erratum BDF102 in Intel Xeon E5-2600 v4 Processor Product Family Specification Update: http://web.archive.org/web/20191125200531/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v4-spec-update.pdfh](hZ2. Erratum BDF102 in Intel Xeon E5-2600 v4 Processor Product Family Specification Update: }(hje<hhhNhNubj)}(hhttp://web.archive.org/web/20191125200531/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v4-spec-update.pdfh]hhttp://web.archive.org/web/20191125200531/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v4-spec-update.pdf}(hjm<hhhNhNubah}(h]h ]h"]h$]h&]refurijo<uh1jhje<ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj0hhubj)}(h3. The errata in Intel Resource Director Technology (Intel RDT) on 2nd Generation Intel Xeon Scalable Processors Reference Manual: https://software.intel.com/content/www/us/en/develop/articles/intel-resource-director-technology-rdt-reference-manual.htmlh](h3. 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Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]levelKtypeINFOlineKsourcehuh1j=hjubj=)}(hhh]j)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]levelKtypej=lineKsourcehuh1j=hjIubj=)}(hhh]j)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]levelKtypej=lineKsourcehuh1j=hjubj=)}(hhh]j)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]levelKtypej=lineKsourcehuh1j=hjubj=)}(hhh]j)}(h:Enumerated list start value not ordinal-1: "2" (ordinal 2)h]h>Enumerated list start value not ordinal-1: “2” (ordinal 2)}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=sourcehnjlineKuh1j=hj hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj">hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hjb"hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj=>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:>ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj"hhhhhMubj=)}(hhh]j)}(h:Enumerated list start value not ordinal-1: "2" (ordinal 2)h]h>Enumerated list start value not ordinal-1: “2” (ordinal 2)}(hjX>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU>ubah}(h]h ]h"]h$]h&]levelKtypej=sourcehnjlineKuh1j=hj4'hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hjs>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjp>ubah}(h]h ]h"]h$]h&]levelKtypej=lineM(sourcehuh1j=hj4'hhhhhM(ubj=)}(hhh]j)}(h:Enumerated list start value not ordinal-1: "3" (ordinal 3)h]h>Enumerated list start value not ordinal-1: “3” (ordinal 3)}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=sourcehnjlineKuh1j=hj4'hhhhhM2ubj=)}(hhh]j)}(h:Enumerated list start value not ordinal-1: "4" (ordinal 4)h]h>Enumerated list start value not ordinal-1: “4” (ordinal 4)}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=sourcehnjlineKuh1j=hj4'hhhhhMTubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj-hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj-hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj-hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj.hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hj0?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-?ubah}(h]h ]h"]h$]h&]levelKtypej=lineMsourcehuh1j=hj.hhhhhMubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. Treating it as ordinary text because it’s so short.}(hjK?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjH?ubah}(h]h ]h"]h$]h&]levelKtypej=lineM sourcehuh1j=hj.hhhhhM ubj=)}(hhh]j)}(hfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.h]hhPossible title underline, too short for the title. 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