€•½fŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ&/translations/zh_CN/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/zh_TW/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/it_IT/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ja_JP/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ko_KR/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/pt_BR/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/sp_SP/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒCSPDX-License-Identifier: GPL-2.0 OR GFDL-1.2-no-invariants-or-later”h]”hŒCSPDX-License-Identifier: GPL-2.0 OR GFDL-1.2-no-invariants-or-later”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œ@/var/lib/git/docbuild/linux/Documentation/edac/memory_repair.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒEDAC Memory Repair Control”h]”hŒEDAC Memory Repair Control”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hŒ*Copyright (c) 2024-2025 HiSilicon Limited.”h]”hŒ*Copyright (c) 2024-2025 HiSilicon Limited.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒ field_list”“”)”}”(hhh]”(hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hhùh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h÷hhôh³hÇh´KubhŒ field_body”“”)”}”(hŒ"Shiju Jose ”h]”hÞ)”}”(hj h]”(hŒ Shiju Jose <”…””}”(hj h²hh³Nh´NubhŒ reference”“”)”}”(hŒshiju.jose@huawei.com”h]”hŒshiju.jose@huawei.com”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:shiju.jose@huawei.com”uh1jhj ubhŒ>”…””}”(hj h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhhôubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòh³hÇh´K hhïh²hubhó)”}”(hhh]”(hø)”}”(hŒLicense”h]”hŒLicense”…””}”(hj?h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h÷hj<h³hÇh´Kubj)”}”(hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”h]”hÞ)”}”(hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”h]”hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”…””}”(hjQh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjMubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj<ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòh³hÇh´K hhïh²hubhó)”}”(hhh]”(hø)”}”(hŒOriginal Reviewers”h]”hŒOriginal Reviewers”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h÷hjkh³hÇh´Kubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1jhjkubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòh³hÇh´K hhïh²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1híhhÊh²hh³hÇh´K ubhŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒWritten for: 6.15 ”h]”hÞ)”}”(hŒWritten for: 6.15”h]”hŒWritten for: 6.15”…””}”(hjœh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj˜ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj“h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j‘h³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Introduction”h]”hŒ Introduction”…””}”(hj»h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¸h²hh³hÇh´KubhÞ)”}”(hŒ¢Some memory devices support repair operations to address issues in their memory media. Post Package Repair (PPR) and memory sparing are examples of such features.”h]”hŒ¢Some memory devices support repair operations to address issues in their memory media. Post Package Repair (PPR) and memory sparing are examples of such features.”…””}”(hjÉh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj¸h²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒPost Package Repair (PPR)”h]”hŒPost Package Repair (PPR)”…””}”(hjÚh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj×h²hh³hÇh´KubhÞ)”}”(hŒõPost Package Repair is a maintenance operation which requests the memory device to perform repair operation on its media. It is a memory self-healing feature that fixes a failing memory location by replacing it with a spare row in a DRAM device.”h]”hŒõPost Package Repair is a maintenance operation which requests the memory device to perform repair operation on its media. It is a memory self-healing feature that fixes a failing memory location by replacing it with a spare row in a DRAM device.”…””}”(hjèh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj×h²hubhÞ)”}”(hŒ¨For example, a CXL memory device with DRAM components that support PPR features implements maintenance operations. DRAM components support those types of PPR functions:”h]”hŒ¨For example, a CXL memory device with DRAM components that support PPR features implements maintenance operations. DRAM components support those types of PPR functions:”…””}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hj×h²hubhŒ block_quote”“”)”}”(hŒT- hard PPR, for a permanent row repair, and - soft PPR, for a temporary row repair. ”h]”j’)”}”(hhh]”(j—)”}”(hŒ)hard PPR, for a permanent row repair, and”h]”hÞ)”}”(hjh]”hŒ)hard PPR, for a permanent row repair, and”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K$hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj ubj—)”}”(hŒ&soft PPR, for a temporary row repair. ”h]”hÞ)”}”(hŒ%soft PPR, for a temporary row repair.”h]”hŒ%soft PPR, for a temporary row repair.”…””}”(hj(h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K%hj$ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj ubeh}”(h]”h ]”h"]”h$]”h&]”j¶j·uh1j‘h³hÇh´K$hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K$hj×h²hubhÞ)”}”(hŒRSoft PPR is much faster than hard PPR, but the repair is lost after a power cycle.”h]”hŒRSoft PPR is much faster than hard PPR, but the repair is lost after a power cycle.”…””}”(hjHh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K'hj×h²hubhÞ)”}”(hŒ°The data may not be retained and memory requests may not be correctly processed during a repair operation. In such case, the repair operation should not be executed at runtime.”h]”hŒ°The data may not be retained and memory requests may not be correctly processed during a repair operation. In such case, the repair operation should not be executed at runtime.”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K*hj×h²hubhÞ)”}”(hŒÓFor example, for CXL memory devices, see CXL spec rev 3.1 [1]_ sections 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.”h]”(hŒ:For example, for CXL memory devices, see CXL spec rev 3.1 ”…””}”(hjdh²hh³Nh´NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hjnh²hh³Nh´Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid3”Œdocname”Œedac/memory_repair”uh1jlhjdŒresolved”KubhŒ• sections 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.”…””}”(hjdh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K.hj×h²hubeh}”(h]”Œpost-package-repair-ppr”ah ]”h"]”Œpost package repair (ppr)”ah$]”h&]”uh1hÈhj¸h²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒMemory Sparing”h]”hŒMemory Sparing”…””}”(hj—h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj”h²hh³hÇh´K3ubhÞ)”}”(hXKMemory sparing is a repair function that replaces a portion of memory with a portion of functional memory at a particular granularity. Memory sparing has cacheline/row/bank/rank sparing granularities. For example, in rank memory-sparing mode, one memory rank serves as a spare for other ranks on the same channel in case they fail.”h]”hXKMemory sparing is a repair function that replaces a portion of memory with a portion of functional memory at a particular granularity. Memory sparing has cacheline/row/bank/rank sparing granularities. For example, in rank memory-sparing mode, one memory rank serves as a spare for other ranks on the same channel in case they fail.”…””}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K5hj”h²hubhÞ)”}”(hŒ®The spare rank is held in reserve and not used as active memory until a failure is indicated, with reserved capacity subtracted from the total available memory in the system.”h]”hŒ®The spare rank is held in reserve and not used as active memory until a failure is indicated, with reserved capacity subtracted from the total available memory in the system.”…””}”(hj³h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K;hj”h²hubhÞ)”}”(hXAfter an error threshold is surpassed in a system protected by memory sparing, the content of a failing rank of DIMMs is copied to the spare rank. The failing rank is then taken offline and the spare rank placed online for use as active memory in place of the failed rank.”h]”hXAfter an error threshold is surpassed in a system protected by memory sparing, the content of a failing rank of DIMMs is copied to the spare rank. The failing rank is then taken offline and the spare rank placed online for use as active memory in place of the failed rank.”…””}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K?hj”h²hubhÞ)”}”(hŒFor example, CXL memory devices can support various subclasses for sparing operation vary in terms of the scope of the sparing being performed.”h]”hŒFor example, CXL memory devices can support various subclasses for sparing operation vary in terms of the scope of the sparing being performed.”…””}”(hjÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KDhj”h²hubhÞ)”}”(hXJCacheline sparing subclass refers to a sparing action that can replace a full cacheline. Row sparing is provided as an alternative to PPR sparing functions and its scope is that of a single DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing is defined as an operation in which an entire DDR rank is replaced.”h]”hXJCacheline sparing subclass refers to a sparing action that can replace a full cacheline. Row sparing is provided as an alternative to PPR sparing functions and its scope is that of a single DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing is defined as an operation in which an entire DDR rank is replaced.”…””}”(hjÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KGhj”h²hubhÞ)”}”(hŒaSee CXL spec 3.1 [1]_ section 8.2.9.7.1.4 Memory Sparing Maintenance Operations for more details.”h]”(hŒSee CXL spec 3.1 ”…””}”(hjëh²hh³Nh´Nubjm)”}”(hŒ[1]_”h]”hŒ1”…””}”(hjóh²hh³Nh´Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”j}j~jj€uh1jlhjëjKubhŒL section 8.2.9.7.1.4 Memory Sparing Maintenance Operations for more details.”…””}”(hjëh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KMhj”h²hubhŒfootnote”“”)”}”(hŒ2https://computeexpresslink.org/cxl-specification/ ”h]”(hŒlabel”“”)”}”(hŒ1”h]”hŒ1”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhÞ)”}”(hŒ1https://computeexpresslink.org/cxl-specification/”h]”j)”}”(hj$h]”hŒ1https://computeexpresslink.org/cxl-specification/”…””}”(hj&h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j$uh1jhj"ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KPhjubeh}”(h]”j~ah ]”h"]”Œ1”ah$]”h&]”(jxjýejj€uh1j h³hÇh´KPhj”h²hjKubeh}”(h]”Œmemory-sparing”ah ]”h"]”Œmemory sparing”ah$]”h&]”uh1hÈhj¸h²hh³hÇh´K3ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ3Use cases of generic memory repair features control”h]”hŒ3Use cases of generic memory repair features control”…””}”(hjLh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjIh²hh³hÇh´KSubhŒenumerated_list”“”)”}”(hhh]”(j—)”}”(hŒíThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools. ”h]”hÞ)”}”(hŒìThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools.”h]”hŒìThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools.”…””}”(hjch²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KUhj_ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj\h²hh³hÇh´Nubj—)”}”(hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the "maintenance needed" flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control. ”h]”hÞ)”}”(hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the "maintenance needed" flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control.”h]”hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the “maintenance needed†flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control.”…””}”(hj{h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KZhjwubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj\h²hh³hÇh´Nubj—)”}”(hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory. ”h]”hÞ)”}”(hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory.”h]”hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory.”…””}”(hj“h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kchjubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj\h²hh³hÇh´Nubj—)”}”(hŒAMultiple PPR/sparing instances may be present per memory device. ”h]”hÞ)”}”(hŒ@Multiple PPR/sparing instances may be present per memory device.”h]”hŒ@Multiple PPR/sparing instances may be present per memory device.”…””}”(hj«h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhj§ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj\h²hh³hÇh´Nubj—)”}”(hŒèDrivers should enforce that live repair is safe. In systems where memory mapping functions can change between boots, one approach to this is to log memory errors seen on this boot against which to check live memory repair requests. ”h]”hÞ)”}”(hŒçDrivers should enforce that live repair is safe. In systems where memory mapping functions can change between boots, one approach to this is to log memory errors seen on this boot against which to check live memory repair requests.”h]”hŒçDrivers should enforce that live repair is safe. In systems where memory mapping functions can change between boots, one approach to this is to log memory errors seen on this boot against which to check live memory repair requests.”…””}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kjhj¿ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj\h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jZhjIh²hh³hÇh´KUubeh}”(h]”Œ3use-cases-of-generic-memory-repair-features-control”ah ]”h"]”Œ3use cases of generic memory repair features control”ah$]”h&]”uh1hÈhj¸h²hh³hÇh´KSubeh}”(h]”Œ introduction”ah ]”h"]”Œ introduction”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒThe File System”h]”hŒThe File System”…””}”(hjõh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjòh²hh³hÇh´KpubhÞ)”}”(hŒ„The control attributes of a registered memory repair instance could be accessed in the /sys/bus/edac/devices//mem_repairX/”h]”hŒ„The control attributes of a registered memory repair instance could be accessed in the /sys/bus/edac/devices//mem_repairX/”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Krhjòh²hubeh}”(h]”Œthe-file-system”ah ]”h"]”Œthe file system”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KpubhÉ)”}”(hhh]”(hÎ)”}”(hŒsysfs”h]”hŒsysfs”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´KvubhÞ)”}”(hŒSSysfs files are documented in `Documentation/ABI/testing/sysfs-edac-memory-repair`.”h]”(hŒSysfs files are documented in ”…””}”(hj*h²hh³Nh´NubhŒtitle_reference”“”)”}”(hŒ4`Documentation/ABI/testing/sysfs-edac-memory-repair`”h]”hŒ2Documentation/ABI/testing/sysfs-edac-memory-repair”…””}”(hj4h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j2hj*ubhŒ.”…””}”(hj*h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kxhjh²hubeh}”(h]”Œsysfs”ah ]”h"]”Œsysfs”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KvubhÉ)”}”(hhh]”(hÎ)”}”(hŒExamples”h]”hŒExamples”…””}”(hjWh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjTh²hh³hÇh´K|ubhÞ)”}”(hŒ=The memory repair usage takes the form shown in this example:”h]”hŒ=The memory repair usage takes the form shown in this example:”…””}”(hjeh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K~hjTh²hubj[)”}”(hhh]”j—)”}”(hŒCXL memory sparing ”h]”hÞ)”}”(hŒCXL memory sparing”h]”hŒCXL memory sparing”…””}”(hjzh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K€hjvubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hjsh²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”jÝjÞjßhjàjáuh1jZhjTh²hh³hÇh´K€ubhÞ)”}”(hXMemory sparing is defined as a repair function that replaces a portion of memory with a portion of functional memory at that same DPA. The subclass for this operation, cacheline/row/bank/rank sparing, vary in terms of the scope of the sparing being performed.”h]”hXMemory sparing is defined as a repair function that replaces a portion of memory with a portion of functional memory at that same DPA. The subclass for this operation, cacheline/row/bank/rank sparing, vary in terms of the scope of the sparing being performed.”…””}”(hj”h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‚hjTh²hubhÞ)”}”(hXLMemory sparing maintenance operations may be supported by CXL devices that implement CXL.mem protocol. A sparing maintenance operation requests the CXL device to perform a repair operation on its media. For example, a CXL device with DRAM components that support memory sparing features may implement sparing maintenance operations.”h]”hXLMemory sparing maintenance operations may be supported by CXL devices that implement CXL.mem protocol. A sparing maintenance operation requests the CXL device to perform a repair operation on its media. For example, a CXL device with DRAM components that support memory sparing features may implement sparing maintenance operations.”…””}”(hj¢h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‡hjTh²hubj[)”}”(hhh]”j—)”}”(hŒ+CXL memory Soft Post Package Repair (sPPR) ”h]”hÞ)”}”(hŒ*CXL memory Soft Post Package Repair (sPPR)”h]”hŒ*CXL memory Soft Post Package Repair (sPPR)”…””}”(hj·h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj³ubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hj°h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”jÝjÞjßhjàjáŒstart”Kuh1jZhjTh²hh³hÇh´KubhÞ)”}”(hX²Post Package Repair (PPR) maintenance operations may be supported by CXL devices that implement CXL.mem protocol. A PPR maintenance operation requests the CXL device to perform a repair operation on its media. For example, a CXL device with DRAM components that support PPR features may implement PPR Maintenance operations. Soft PPR (sPPR) is a temporary row repair. Soft PPR may be faster, but the repair is lost with a power cycle.”h]”hX²Post Package Repair (PPR) maintenance operations may be supported by CXL devices that implement CXL.mem protocol. A PPR maintenance operation requests the CXL device to perform a repair operation on its media. For example, a CXL device with DRAM components that support PPR features may implement PPR Maintenance operations. Soft PPR (sPPR) is a temporary row repair. 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