€•ÕTŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ&/translations/zh_CN/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/zh_TW/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/it_IT/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ja_JP/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ko_KR/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/sp_SP/edac/memory_repair”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒCSPDX-License-Identifier: GPL-2.0 OR GFDL-1.2-no-invariants-or-later”h]”hŒCSPDX-License-Identifier: GPL-2.0 OR GFDL-1.2-no-invariants-or-later”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h¡hhhžhhŸŒ@/var/lib/git/docbuild/linux/Documentation/edac/memory_repair.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒEDAC Memory Repair Control”h]”hŒEDAC Memory Repair Control”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ paragraph”“”)”}”(hŒ*Copyright (c) 2024-2025 HiSilicon Limited.”h]”hŒ*Copyright (c) 2024-2025 HiSilicon Limited.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhŒ field_list”“”)”}”(hhh]”(hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hhåhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhàhŸh³h KubhŒ field_body”“”)”}”(hŒ"Shiju Jose ”h]”hÊ)”}”(hh÷h]”(hŒ Shiju Jose <”…””}”(hhùhžhhŸNh NubhŒ reference”“”)”}”(hŒshiju.jose@huawei.com”h]”hŒshiju.jose@huawei.com”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:shiju.jose@huawei.com”uh1jhhùubhŒ>”…””}”(hhùhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hhõubah}”(h]”h ]”h"]”h$]”h&]”uh1hóhhàubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÞhŸh³h K hhÛhžhubhß)”}”(hhh]”(hä)”}”(hŒLicense”h]”hŒLicense”…””}”(hj+hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhj(hŸh³h Kubhô)”}”(hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”h]”hÊ)”}”(hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”h]”hŒ”The GNU Free Documentation License, Version 1.2 without Invariant Sections, Front-Cover Texts nor Back-Cover Texts. (dual licensed under the GPL v2)”…””}”(hj=hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hj9ubah}”(h]”h ]”h"]”h$]”h&]”uh1hóhj(ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÞhŸh³h K hhÛhžhubhß)”}”(hhh]”(hä)”}”(hŒOriginal Reviewers”h]”hŒOriginal Reviewers”…””}”(hjZhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhjWhŸh³h Kubhô)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1hóhjWubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÞhŸh³h K hhÛhžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÙhh¶hžhhŸh³h K ubhŒ bullet_list”“”)”}”(hhh]”hŒ list_item”“”)”}”(hŒWritten for: 6.15 ”h]”hÊ)”}”(hŒWritten for: 6.15”h]”hŒWritten for: 6.15”…””}”(hjˆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj„ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjhžhhŸh³h Nubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j}hŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒ Introduction”h]”hŒ Introduction”…””}”(hj§hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj¤hžhhŸh³h KubhÊ)”}”(hŒ¢Some memory devices support repair operations to address issues in their memory media. Post Package Repair (PPR) and memory sparing are examples of such features.”h]”hŒ¢Some memory devices support repair operations to address issues in their memory media. Post Package Repair (PPR) and memory sparing are examples of such features.”…””}”(hjµhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj¤hžhubhµ)”}”(hhh]”(hº)”}”(hŒPost Package Repair (PPR)”h]”hŒPost Package Repair (PPR)”…””}”(hjÆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjÃhžhhŸh³h KubhÊ)”}”(hŒõPost Package Repair is a maintenance operation which requests the memory device to perform repair operation on its media. It is a memory self-healing feature that fixes a failing memory location by replacing it with a spare row in a DRAM device.”h]”hŒõPost Package Repair is a maintenance operation which requests the memory device to perform repair operation on its media. It is a memory self-healing feature that fixes a failing memory location by replacing it with a spare row in a DRAM device.”…””}”(hjÔhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjÃhžhubhÊ)”}”(hŒ¨For example, a CXL memory device with DRAM components that support PPR features implements maintenance operations. DRAM components support those types of PPR functions:”h]”hŒ¨For example, a CXL memory device with DRAM components that support PPR features implements maintenance operations. DRAM components support those types of PPR functions:”…””}”(hjâhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hjÃhžhubhŒ block_quote”“”)”}”(hŒT- hard PPR, for a permanent row repair, and - soft PPR, for a temporary row repair. ”h]”j~)”}”(hhh]”(jƒ)”}”(hŒ)hard PPR, for a permanent row repair, and”h]”hÊ)”}”(hjûh]”hŒ)hard PPR, for a permanent row repair, and”…””}”(hjýhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K$hjùubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjöubjƒ)”}”(hŒ&soft PPR, for a temporary row repair. ”h]”hÊ)”}”(hŒ%soft PPR, for a temporary row repair.”h]”hŒ%soft PPR, for a temporary row repair.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K%hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjöubeh}”(h]”h ]”h"]”h$]”h&]”j¢j£uh1j}hŸh³h K$hjòubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhŸh³h K$hjÃhžhubhÊ)”}”(hŒRSoft PPR is much faster than hard PPR, but the repair is lost after a power cycle.”h]”hŒRSoft PPR is much faster than hard PPR, but the repair is lost after a power cycle.”…””}”(hj4hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K'hjÃhžhubhÊ)”}”(hŒ°The data may not be retained and memory requests may not be correctly processed during a repair operation. In such case, the repair operation should not be executed at runtime.”h]”hŒ°The data may not be retained and memory requests may not be correctly processed during a repair operation. In such case, the repair operation should not be executed at runtime.”…””}”(hjBhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K*hjÃhžhubhÊ)”}”(hŒÓFor example, for CXL memory devices, see CXL spec rev 3.1 [1]_ sections 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.”h]”(hŒ:For example, for CXL memory devices, see CXL spec rev 3.1 ”…””}”(hjPhžhhŸNh NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hjZhžhhŸNh Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid3”Œdocname”Œedac/memory_repair”uh1jXhjPŒresolved”KubhŒ• sections 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.”…””}”(hjPhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K.hjÃhžhubeh}”(h]”Œpost-package-repair-ppr”ah ]”h"]”Œpost package repair (ppr)”ah$]”h&]”uh1h´hj¤hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒMemory Sparing”h]”hŒMemory Sparing”…””}”(hjƒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj€hžhhŸh³h K3ubhÊ)”}”(hXKMemory sparing is a repair function that replaces a portion of memory with a portion of functional memory at a particular granularity. Memory sparing has cacheline/row/bank/rank sparing granularities. For example, in rank memory-sparing mode, one memory rank serves as a spare for other ranks on the same channel in case they fail.”h]”hXKMemory sparing is a repair function that replaces a portion of memory with a portion of functional memory at a particular granularity. Memory sparing has cacheline/row/bank/rank sparing granularities. For example, in rank memory-sparing mode, one memory rank serves as a spare for other ranks on the same channel in case they fail.”…””}”(hj‘hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K5hj€hžhubhÊ)”}”(hŒ®The spare rank is held in reserve and not used as active memory until a failure is indicated, with reserved capacity subtracted from the total available memory in the system.”h]”hŒ®The spare rank is held in reserve and not used as active memory until a failure is indicated, with reserved capacity subtracted from the total available memory in the system.”…””}”(hjŸhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K;hj€hžhubhÊ)”}”(hXAfter an error threshold is surpassed in a system protected by memory sparing, the content of a failing rank of DIMMs is copied to the spare rank. The failing rank is then taken offline and the spare rank placed online for use as active memory in place of the failed rank.”h]”hXAfter an error threshold is surpassed in a system protected by memory sparing, the content of a failing rank of DIMMs is copied to the spare rank. The failing rank is then taken offline and the spare rank placed online for use as active memory in place of the failed rank.”…””}”(hj­hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K?hj€hžhubhÊ)”}”(hŒFor example, CXL memory devices can support various subclasses for sparing operation vary in terms of the scope of the sparing being performed.”h]”hŒFor example, CXL memory devices can support various subclasses for sparing operation vary in terms of the scope of the sparing being performed.”…””}”(hj»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KDhj€hžhubhÊ)”}”(hXJCacheline sparing subclass refers to a sparing action that can replace a full cacheline. Row sparing is provided as an alternative to PPR sparing functions and its scope is that of a single DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing is defined as an operation in which an entire DDR rank is replaced.”h]”hXJCacheline sparing subclass refers to a sparing action that can replace a full cacheline. Row sparing is provided as an alternative to PPR sparing functions and its scope is that of a single DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing is defined as an operation in which an entire DDR rank is replaced.”…””}”(hjÉhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KGhj€hžhubhÊ)”}”(hŒaSee CXL spec 3.1 [1]_ section 8.2.9.7.1.4 Memory Sparing Maintenance Operations for more details.”h]”(hŒSee CXL spec 3.1 ”…””}”(hj×hžhhŸNh NubjY)”}”(hŒ[1]_”h]”hŒ1”…””}”(hjßhžhhŸNh Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”jijjjkjluh1jXhj×jmKubhŒL section 8.2.9.7.1.4 Memory Sparing Maintenance Operations for more details.”…””}”(hj×hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KMhj€hžhubhŒfootnote”“”)”}”(hŒ2https://computeexpresslink.org/cxl-specification/ ”h]”(hŒlabel”“”)”}”(hŒ1”h]”hŒ1”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jþhjúubhÊ)”}”(hŒ1https://computeexpresslink.org/cxl-specification/”h]”j)”}”(hjh]”hŒ1https://computeexpresslink.org/cxl-specification/”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”juh1jhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KPhjúubeh}”(h]”jjah ]”h"]”Œ1”ah$]”h&]”(jdjéejkjluh1jøhŸh³h KPhj€hžhjmKubeh}”(h]”Œmemory-sparing”ah ]”h"]”Œmemory sparing”ah$]”h&]”uh1h´hj¤hžhhŸh³h K3ubhµ)”}”(hhh]”(hº)”}”(hŒ3Use cases of generic memory repair features control”h]”hŒ3Use cases of generic memory repair features control”…””}”(hj8hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj5hžhhŸh³h KSubhŒenumerated_list”“”)”}”(hhh]”(jƒ)”}”(hŒíThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools. ”h]”hÊ)”}”(hŒìThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools.”h]”hŒìThe soft PPR, hard PPR and memory-sparing features share similar control attributes. Therefore, there is a need for a standardized, generic sysfs repair control that is exposed to userspace and used by administrators, scripts and tools.”…””}”(hjOhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KUhjKubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjHhžhhŸh³h Nubjƒ)”}”(hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the "maintenance needed" flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control. ”h]”hÊ)”}”(hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the "maintenance needed" flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control.”h]”hXWhen a CXL device detects an error in a memory component, it informs the host of the need for a repair maintenance operation by using an event record where the “maintenance needed†flag is set. The event record specifies the device physical address (DPA) and attributes of the memory that requires repair. The kernel reports the corresponding CXL general media or DRAM trace event to userspace, and userspace tools (e.g. rasdaemon) initiate a repair maintenance operation in response to the device request using the sysfs repair control.”…””}”(hjghžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KZhjcubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjHhžhhŸh³h Nubjƒ)”}”(hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory. ”h]”hÊ)”}”(hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory.”h]”hXUserspace tools, such as rasdaemon, request a repair operation on a memory region when maintenance need flag set or an uncorrected memory error or excess of corrected memory errors above a threshold value is reported or an exceed corrected errors threshold flag set for that memory.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kchj{ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjHhžhhŸh³h Nubjƒ)”}”(hŒAMultiple PPR/sparing instances may be present per memory device. ”h]”hÊ)”}”(hŒ@Multiple PPR/sparing instances may be present per memory device.”h]”hŒ@Multiple PPR/sparing instances may be present per memory device.”…””}”(hj—hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khhj“ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‚hjHhžhhŸh³h Nubjƒ)”}”(hŒèDrivers should enforce that live repair is safe. In systems where memory mapping functions can change between boots, one approach to this is to log memory errors seen on this boot against which to check live memory repair requests. ”h]”hÊ)”}”(hŒçDrivers should enforce that live repair is safe. In systems where memory mapping functions can change between boots, one approach to this is to log memory errors seen on this boot against which to check live memory repair requests.”h]”hŒçDrivers should enforce that live repair is safe. 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