€•      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ#/translations/zh_CN/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/zh_TW/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/it_IT/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/ja_JP/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/ko_KR/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/sp_SP/driver-api/vfio”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ"VFIO - "Virtual Function I/O" [1]_”h]”(hŒ"VFIO - â€œVirtual Function I/Oâ€ ”…””}”(hh¨hžhhŸNh NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hh²hžhhŸNh Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid7”Œdocname”Œdriver-api/vfio”uh1h°hh¨Œresolved”Kubeh}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒ=/var/lib/git/docbuild/linux/Documentation/driver-api/vfio.rst”h KubhŒ	paragraph”“”)”}”(hX  Many modern systems now provide DMA and interrupt remapping facilities
to help ensure I/O devices behave within the boundaries they've been
allotted.  This includes x86 hardware with AMD-Vi and Intel VT-d,
POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC
systems such as Freescale PAMU.  The VFIO driver is an IOMMU/device
agnostic framework for exposing direct device access to userspace, in
a secure, IOMMU protected environment.  In other words, this allows
safe [2]_, non-privileged, userspace drivers.”h]”(hXé  Many modern systems now provide DMA and interrupt remapping facilities
to help ensure I/O devices behave within the boundaries theyâ€™ve been
allotted.  This includes x86 hardware with AMD-Vi and Intel VT-d,
POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC
systems such as Freescale PAMU.  The VFIO driver is an IOMMU/device
agnostic framework for exposing direct device access to userspace, in
a secure, IOMMU protected environment.  In other words, this allows
safe ”…””}”(hhÏhžhhŸNh Nubh±)”}”(hŒ[2]_”h]”hŒ2”…””}”(hh×hžhhŸNh Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”hÁŒid8”hÃhÄuh1h°hhÏhÅKubhŒ$, non-privileged, userspace drivers.”…””}”(hhÏhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Khh£hžhubhÎ)”}”(hXl  Why do we want that?  Virtual machines often make use of direct device
access ("device assignment") when configured for the highest possible
I/O performance.  From a device and host perspective, this simply
turns the VM into a userspace driver, with the benefits of
significantly reduced latency, higher bandwidth, and direct use of
bare-metal device drivers [3]_.”h]”(hXk  Why do we want that?  Virtual machines often make use of direct device
access (â€œdevice assignmentâ€) when configured for the highest possible
I/O performance.  From a device and host perspective, this simply
turns the VM into a userspace driver, with the benefits of
significantly reduced latency, higher bandwidth, and direct use of
bare-metal device drivers ”…””}”(hhñhžhhŸNh Nubh±)”}”(hŒ[3]_”h]”hŒ3”…””}”(hhùhžhhŸNh Nubah}”(h]”Œid3”ah ]”h"]”h$]”h&]”hÁŒid9”hÃhÄuh1h°hhñhÅKubhŒ.”…””}”(hhñhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Khh£hžhubhÎ)”}”(hX$  Some applications, particularly in the high performance computing
field, also benefit from low-overhead, direct device access from
userspace.  Examples include network adapters (often non-TCP/IP based)
and compute accelerators.  Prior to VFIO, these drivers had to either
go through the full development cycle to become proper upstream
driver, be maintained out of tree, or make use of the UIO framework,
which has no notion of IOMMU protection, limited interrupt support,
and requires root privileges to access things like PCI configuration
space.”h]”hX$  Some applications, particularly in the high performance computing
field, also benefit from low-overhead, direct device access from
userspace.  Examples include network adapters (often non-TCP/IP based)
and compute accelerators.  Prior to VFIO, these drivers had to either
go through the full development cycle to become proper upstream
driver, be maintained out of tree, or make use of the UIO framework,
which has no notion of IOMMU protection, limited interrupt support,
and requires root privileges to access things like PCI configuration
space.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Khh£hžhubhÎ)”}”(hŒÅThe VFIO driver framework intends to unify these, replacing both the
KVM PCI specific device assignment code as well as provide a more
secure, more featureful userspace driver environment than UIO.”h]”hŒÅThe VFIO driver framework intends to unify these, replacing both the
KVM PCI specific device assignment code as well as provide a more
secure, more featureful userspace driver environment than UIO.”…””}”(hj!  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒGroups, Devices, and IOMMUs”h]”hŒGroups, Devices, and IOMMUs”…””}”(hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj/  hžhhŸhÌh K$ubhÎ)”}”(hX}  Devices are the main target of any I/O driver.  Devices typically
create a programming interface made up of I/O access, interrupts,
and DMA.  Without going into the details of each of these, DMA is
by far the most critical aspect for maintaining a secure environment
as allowing a device read-write access to system memory imposes the
greatest risk to the overall system integrity.”h]”hX}  Devices are the main target of any I/O driver.  Devices typically
create a programming interface made up of I/O access, interrupts,
and DMA.  Without going into the details of each of these, DMA is
by far the most critical aspect for maintaining a secure environment
as allowing a device read-write access to system memory imposes the
greatest risk to the overall system integrity.”…””}”(hj@  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K&hj/  hžhubhÎ)”}”(hX–  To help mitigate this risk, many modern IOMMUs now incorporate
isolation properties into what was, in many cases, an interface only
meant for translation (ie. solving the addressing problems of devices
with limited address spaces).  With this, devices can now be isolated
from each other and from arbitrary memory access, thus allowing
things like secure direct assignment of devices into virtual machines.”h]”hX–  To help mitigate this risk, many modern IOMMUs now incorporate
isolation properties into what was, in many cases, an interface only
meant for translation (ie. solving the addressing problems of devices
with limited address spaces).  With this, devices can now be isolated
from each other and from arbitrary memory access, thus allowing
things like secure direct assignment of devices into virtual machines.”…””}”(hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K-hj/  hžhubhÎ)”}”(hXs  This isolation is not always at the granularity of a single device
though.  Even when an IOMMU is capable of this, properties of devices,
interconnects, and IOMMU topologies can each reduce this isolation.
For instance, an individual device may be part of a larger multi-
function enclosure.  While the IOMMU may be able to distinguish
between devices within the enclosure, the enclosure may not require
transactions between devices to reach the IOMMU.  Examples of this
could be anything from a multi-function PCI device with backdoors
between functions to a non-PCI-ACS (Access Control Services) capable
bridge allowing redirection without reaching the IOMMU.  Topology
can also play a factor in terms of hiding devices.  A PCIe-to-PCI
bridge masks the devices behind it, making transaction appear as if
from the bridge itself.  Obviously IOMMU design plays a major factor
as well.”h]”hXs  This isolation is not always at the granularity of a single device
though.  Even when an IOMMU is capable of this, properties of devices,
interconnects, and IOMMU topologies can each reduce this isolation.
For instance, an individual device may be part of a larger multi-
function enclosure.  While the IOMMU may be able to distinguish
between devices within the enclosure, the enclosure may not require
transactions between devices to reach the IOMMU.  Examples of this
could be anything from a multi-function PCI device with backdoors
between functions to a non-PCI-ACS (Access Control Services) capable
bridge allowing redirection without reaching the IOMMU.  Topology
can also play a factor in terms of hiding devices.  A PCIe-to-PCI
bridge masks the devices behind it, making transaction appear as if
from the bridge itself.  Obviously IOMMU design plays a major factor
as well.”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K4hj/  hžhubhÎ)”}”(hXM  Therefore, while for the most part an IOMMU may have device level
granularity, any system is susceptible to reduced granularity.  The
IOMMU API therefore supports a notion of IOMMU groups.  A group is
a set of devices which is isolatable from all other devices in the
system.  Groups are therefore the unit of ownership used by VFIO.”h]”hXM  Therefore, while for the most part an IOMMU may have device level
granularity, any system is susceptible to reduced granularity.  The
IOMMU API therefore supports a notion of IOMMU groups.  A group is
a set of devices which is isolatable from all other devices in the
system.  Groups are therefore the unit of ownership used by VFIO.”…””}”(hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KChj/  hžhubhÎ)”}”(hXL  While the group is the minimum granularity that must be used to
ensure secure user access, it's not necessarily the preferred
granularity.  In IOMMUs which make use of page tables, it may be
possible to share a set of page tables between different groups,
reducing the overhead both to the platform (reduced TLB thrashing,
reduced duplicate page tables), and to the user (programming only
a single set of translations).  For this reason, VFIO makes use of
a container class, which may hold one or more groups.  A container
is created by simply opening the /dev/vfio/vfio character device.”h]”hXN  While the group is the minimum granularity that must be used to
ensure secure user access, itâ€™s not necessarily the preferred
granularity.  In IOMMUs which make use of page tables, it may be
possible to share a set of page tables between different groups,
reducing the overhead both to the platform (reduced TLB thrashing,
reduced duplicate page tables), and to the user (programming only
a single set of translations).  For this reason, VFIO makes use of
a container class, which may hold one or more groups.  A container
is created by simply opening the /dev/vfio/vfio character device.”…””}”(hjx  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KIhj/  hžhubhÎ)”}”(hXÅ  On its own, the container provides little functionality, with all
but a couple version and extension query interfaces locked away.
The user needs to add a group into the container for the next level
of functionality.  To do this, the user first needs to identify the
group associated with the desired device.  This can be done using
the sysfs links described in the example below.  By unbinding the
device from the host driver and binding it to a VFIO driver, a new
VFIO group will appear for the group as /dev/vfio/$GROUP, where
$GROUP is the IOMMU group number of which the device is a member.
If the IOMMU group contains multiple devices, each will need to
be bound to a VFIO driver before operations on the VFIO group
are allowed (it's also sufficient to only unbind the device from
host drivers if a VFIO driver is unavailable; this will make the
group available, but not that particular device).  TBD - interface
for disabling driver probing/locking a device.”h]”hXÇ  On its own, the container provides little functionality, with all
but a couple version and extension query interfaces locked away.
The user needs to add a group into the container for the next level
of functionality.  To do this, the user first needs to identify the
group associated with the desired device.  This can be done using
the sysfs links described in the example below.  By unbinding the
device from the host driver and binding it to a VFIO driver, a new
VFIO group will appear for the group as /dev/vfio/$GROUP, where
$GROUP is the IOMMU group number of which the device is a member.
If the IOMMU group contains multiple devices, each will need to
be bound to a VFIO driver before operations on the VFIO group
are allowed (itâ€™s also sufficient to only unbind the device from
host drivers if a VFIO driver is unavailable; this will make the
group available, but not that particular device).  TBD - interface
for disabling driver probing/locking a device.”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KShj/  hžhubhÎ)”}”(hXå  Once the group is ready, it may be added to the container by opening
the VFIO group character device (/dev/vfio/$GROUP) and using the
VFIO_GROUP_SET_CONTAINER ioctl, passing the file descriptor of the
previously opened container file.  If desired and if the IOMMU driver
supports sharing the IOMMU context between groups, multiple groups may
be set to the same container.  If a group fails to set to a container
with existing groups, a new empty container will need to be used
instead.”h]”hXå  Once the group is ready, it may be added to the container by opening
the VFIO group character device (/dev/vfio/$GROUP) and using the
VFIO_GROUP_SET_CONTAINER ioctl, passing the file descriptor of the
previously opened container file.  If desired and if the IOMMU driver
supports sharing the IOMMU context between groups, multiple groups may
be set to the same container.  If a group fails to set to a container
with existing groups, a new empty container will need to be used
instead.”…””}”(hj”  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Kchj/  hžhubhÎ)”}”(hX  With a group (or groups) attached to a container, the remaining
ioctls become available, enabling access to the VFIO IOMMU interfaces.
Additionally, it now becomes possible to get file descriptors for each
device within a group using an ioctl on the VFIO group file descriptor.”h]”hX  With a group (or groups) attached to a container, the remaining
ioctls become available, enabling access to the VFIO IOMMU interfaces.
Additionally, it now becomes possible to get file descriptors for each
device within a group using an ioctl on the VFIO group file descriptor.”…””}”(hj¢  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Klhj/  hžhubhÎ)”}”(hŒØThe VFIO device API includes ioctls for describing the device, the I/O
regions and their read/write/mmap offsets on the device descriptor, as
well as mechanisms for describing and registering interrupt
notifications.”h]”hŒØThe VFIO device API includes ioctls for describing the device, the I/O
regions and their read/write/mmap offsets on the device descriptor, as
well as mechanisms for describing and registering interrupt
notifications.”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Kqhj/  hžhubeh}”(h]”Œgroups-devices-and-iommus”ah ]”h"]”Œgroups, devices, and iommus”ah$]”h&]”uh1h¡hh£hžhhŸhÌh K$ubh¢)”}”(hhh]”(h§)”}”(hŒVFIO Usage Example”h]”hŒVFIO Usage Example”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÆ  hžhhŸhÌh KwubhÎ)”}”(hŒ5Assume user wants to access PCI device 0000:06:0d.0::”h]”hŒ4Assume user wants to access PCI device 0000:06:0d.0:”…””}”(hj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KyhjÆ  hžhubhŒliteral_block”“”)”}”(hŒ[$ readlink /sys/bus/pci/devices/0000:06:0d.0/iommu_group
../../../../kernel/iommu_groups/26”h]”hŒ[$ readlink /sys/bus/pci/devices/0000:06:0d.0/iommu_group
../../../../kernel/iommu_groups/26”…””}”hjç  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jå  hŸhÌh K{hjÆ  hžhubhÎ)”}”(hŒŽThis device is therefore in IOMMU group 26.  This device is on the
pci bus, therefore the user will make use of vfio-pci to manage the
group::”h]”hŒThis device is therefore in IOMMU group 26.  This device is on the
pci bus, therefore the user will make use of vfio-pci to manage the
group:”…””}”(hj÷  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K~hjÆ  hžhubjæ  )”}”(hŒ# modprobe vfio-pci”h]”hŒ# modprobe vfio-pci”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh K‚hjÆ  hžhubhÎ)”}”(hŒdBinding this device to the vfio-pci driver creates the VFIO group
character devices for this group::”h]”hŒcBinding this device to the vfio-pci driver creates the VFIO group
character devices for this group:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K„hjÆ  hžhubjæ  )”}”(hŒ¹$ lspci -n -s 0000:06:0d.0
06:0d.0 0401: 1102:0002 (rev 08)
# echo 0000:06:0d.0 > /sys/bus/pci/devices/0000:06:0d.0/driver/unbind
# echo 1102 0002 > /sys/bus/pci/drivers/vfio-pci/new_id”h]”hŒ¹$ lspci -n -s 0000:06:0d.0
06:0d.0 0401: 1102:0002 (rev 08)
# echo 0000:06:0d.0 > /sys/bus/pci/devices/0000:06:0d.0/driver/unbind
# echo 1102 0002 > /sys/bus/pci/drivers/vfio-pci/new_id”…””}”hj!  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh K‡hjÆ  hžhubhÎ)”}”(hŒWNow we need to look at what other devices are in the group to free
it for use by VFIO::”h]”hŒVNow we need to look at what other devices are in the group to free
it for use by VFIO:”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KŒhjÆ  hžhubjæ  )”}”(hX   $ ls -l /sys/bus/pci/devices/0000:06:0d.0/iommu_group/devices
total 0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:00:1e.0 ->
        ../../../../devices/pci0000:00/0000:00:1e.0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.0 ->
        ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.1 ->
        ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.1”h]”hX   $ ls -l /sys/bus/pci/devices/0000:06:0d.0/iommu_group/devices
total 0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:00:1e.0 ->
        ../../../../devices/pci0000:00/0000:00:1e.0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.0 ->
        ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.0
lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.1 ->
        ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.1”…””}”hj=  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh KhjÆ  hžhubhÎ)”}”(hX]  This device is behind a PCIe-to-PCI bridge [4]_, therefore we also
need to add device 0000:06:0d.1 to the group following the same
procedure as above.  Device 0000:00:1e.0 is a bridge that does
not currently have a host driver, therefore it's not required to
bind this device to the vfio-pci driver (vfio-pci does not currently
support PCI bridges).”h]”(hŒ+This device is behind a PCIe-to-PCI bridge ”…””}”(hjK  hžhhŸNh Nubh±)”}”(hŒ[4]_”h]”hŒ4”…””}”(hjS  hžhhŸNh Nubah}”(h]”Œid4”ah ]”h"]”h$]”h&]”hÁŒid10”hÃhÄuh1h°hjK  hÅKubhX0  , therefore we also
need to add device 0000:06:0d.1 to the group following the same
procedure as above.  Device 0000:00:1e.0 is a bridge that does
not currently have a host driver, therefore itâ€™s not required to
bind this device to the vfio-pci driver (vfio-pci does not currently
support PCI bridges).”…””}”(hjK  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K˜hjÆ  hžhubhÎ)”}”(hŒãThe final step is to provide the user with access to the group if
unprivileged operation is desired (note that /dev/vfio/vfio provides
no capabilities on its own and is therefore expected to be set to
mode 0666 by the system)::”h]”hŒâThe final step is to provide the user with access to the group if
unprivileged operation is desired (note that /dev/vfio/vfio provides
no capabilities on its own and is therefore expected to be set to
mode 0666 by the system):”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh KŸhjÆ  hžhubjæ  )”}”(hŒ# chown user:user /dev/vfio/26”h]”hŒ# chown user:user /dev/vfio/26”…””}”hj{  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh K¤hjÆ  hžhubhÎ)”}”(hŒmThe user now has full access to all the devices and the iommu for this
group and can access them as follows::”h]”hŒlThe user now has full access to all the devices and the iommu for this
group and can access them as follows:”…””}”(hj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh K¦hjÆ  hžhubjæ  )”}”(hX]	  int container, group, device, i;
struct vfio_group_status group_status =
                                { .argsz = sizeof(group_status) };
struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
struct vfio_iommu_type1_dma_map dma_map = { .argsz = sizeof(dma_map) };
struct vfio_device_info device_info = { .argsz = sizeof(device_info) };

/* Create a new container */
container = open("/dev/vfio/vfio", O_RDWR);

if (ioctl(container, VFIO_GET_API_VERSION) != VFIO_API_VERSION)
        /* Unknown API version */

if (!ioctl(container, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU))
        /* Doesn't support the IOMMU driver we want. */

/* Open the group */
group = open("/dev/vfio/26", O_RDWR);

/* Test the group is viable and available */
ioctl(group, VFIO_GROUP_GET_STATUS, &group_status);

if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE))
        /* Group is not viable (ie, not all devices bound for vfio) */

/* Add the group to the container */
ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);

/* Enable the IOMMU model we want */
ioctl(container, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);

/* Get addition IOMMU info */
ioctl(container, VFIO_IOMMU_GET_INFO, &iommu_info);

/* Allocate some space and setup a DMA mapping */
dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                     MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
dma_map.size = 1024 * 1024;
dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;

ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);

/* Get a file descriptor for the device */
device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");

/* Test and setup the device */
ioctl(device, VFIO_DEVICE_GET_INFO, &device_info);

for (i = 0; i < device_info.num_regions; i++) {
        struct vfio_region_info reg = { .argsz = sizeof(reg) };

        reg.index = i;

        ioctl(device, VFIO_DEVICE_GET_REGION_INFO, &reg);

        /* Setup mappings... read/write offsets, mmaps
         * For PCI devices, config space is a region */
}

for (i = 0; i < device_info.num_irqs; i++) {
        struct vfio_irq_info irq = { .argsz = sizeof(irq) };

        irq.index = i;

        ioctl(device, VFIO_DEVICE_GET_IRQ_INFO, &irq);

        /* Setup IRQs... eventfds, VFIO_DEVICE_SET_IRQS */
}

/* Gratuitous device reset and go... */
ioctl(device, VFIO_DEVICE_RESET);”h]”hX]	  int container, group, device, i;
struct vfio_group_status group_status =
                                { .argsz = sizeof(group_status) };
struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
struct vfio_iommu_type1_dma_map dma_map = { .argsz = sizeof(dma_map) };
struct vfio_device_info device_info = { .argsz = sizeof(device_info) };

/* Create a new container */
container = open("/dev/vfio/vfio", O_RDWR);

if (ioctl(container, VFIO_GET_API_VERSION) != VFIO_API_VERSION)
        /* Unknown API version */

if (!ioctl(container, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU))
        /* Doesn't support the IOMMU driver we want. */

/* Open the group */
group = open("/dev/vfio/26", O_RDWR);

/* Test the group is viable and available */
ioctl(group, VFIO_GROUP_GET_STATUS, &group_status);

if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE))
        /* Group is not viable (ie, not all devices bound for vfio) */

/* Add the group to the container */
ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);

/* Enable the IOMMU model we want */
ioctl(container, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);

/* Get addition IOMMU info */
ioctl(container, VFIO_IOMMU_GET_INFO, &iommu_info);

/* Allocate some space and setup a DMA mapping */
dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                     MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
dma_map.size = 1024 * 1024;
dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;

ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);

/* Get a file descriptor for the device */
device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");

/* Test and setup the device */
ioctl(device, VFIO_DEVICE_GET_INFO, &device_info);

for (i = 0; i < device_info.num_regions; i++) {
        struct vfio_region_info reg = { .argsz = sizeof(reg) };

        reg.index = i;

        ioctl(device, VFIO_DEVICE_GET_REGION_INFO, &reg);

        /* Setup mappings... read/write offsets, mmaps
         * For PCI devices, config space is a region */
}

for (i = 0; i < device_info.num_irqs; i++) {
        struct vfio_irq_info irq = { .argsz = sizeof(irq) };

        irq.index = i;

        ioctl(device, VFIO_DEVICE_GET_IRQ_INFO, &irq);

        /* Setup IRQs... eventfds, VFIO_DEVICE_SET_IRQS */
}

/* Gratuitous device reset and go... */
ioctl(device, VFIO_DEVICE_RESET);”…””}”hj—  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh K©hjÆ  hžhubeh}”(h]”Œvfio-usage-example”ah ]”h"]”Œvfio usage example”ah$]”h&]”uh1h¡hh£hžhhŸhÌh Kwubh¢)”}”(hhh]”(h§)”}”(hŒIOMMUFD and vfio_iommu_type1”h]”hŒIOMMUFD and vfio_iommu_type1”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj­  hžhhŸhÌh KóubhÎ)”}”(hX›  IOMMUFD is the new user API to manage I/O page tables from userspace.
It intends to be the portal of delivering advanced userspace DMA
features (nested translation [5]_, PASID [6]_, etc.) while also providing
a backwards compatibility interface for existing VFIO_TYPE1v2_IOMMU use
cases.  Eventually the vfio_iommu_type1 driver, as well as the legacy
vfio container and group model is intended to be deprecated.”h]”(hŒ¤IOMMUFD is the new user API to manage I/O page tables from userspace.
It intends to be the portal of delivering advanced userspace DMA
features (nested translation ”…””}”(hj¾  hžhhŸNh Nubh±)”}”(hŒ[5]_”h]”hŒ5”…””}”(hjÆ  hžhhŸNh Nubah}”(h]”Œid5”ah ]”h"]”h$]”h&]”hÁŒid11”hÃhÄuh1h°hj¾  hÅKubhŒ, PASID ”…””}”(hj¾  hžhhŸNh Nubh±)”}”(hŒ[6]_”h]”hŒ6”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”Œid6”ah ]”h"]”h$]”h&]”hÁŒid12”hÃhÄuh1h°hj¾  hÅKubhŒç, etc.) while also providing
a backwards compatibility interface for existing VFIO_TYPE1v2_IOMMU use
cases.  Eventually the vfio_iommu_type1 driver, as well as the legacy
vfio container and group model is intended to be deprecated.”…””}”(hj¾  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Kõhj­  hžhubhÎ)”}”(hX  The IOMMUFD backwards compatibility interface can be enabled two ways.
In the first method, the kernel can be configured with
CONFIG_IOMMUFD_VFIO_CONTAINER, in which case the IOMMUFD subsystem
transparently provides the entire infrastructure for the VFIO
container and IOMMU backend interfaces.  The compatibility mode can
also be accessed if the VFIO container interface, ie. /dev/vfio/vfio is
simply symlink'd to /dev/iommu.  Note that at the time of writing, the
compatibility mode is not entirely feature complete relative to
VFIO_TYPE1v2_IOMMU (ex. DMA mapping MMIO) and does not attempt to
provide compatibility to the VFIO_SPAPR_TCE_IOMMU interface.  Therefore
it is not generally advisable at this time to switch from native VFIO
implementations to the IOMMUFD compatibility interfaces.”h]”hX  The IOMMUFD backwards compatibility interface can be enabled two ways.
In the first method, the kernel can be configured with
CONFIG_IOMMUFD_VFIO_CONTAINER, in which case the IOMMUFD subsystem
transparently provides the entire infrastructure for the VFIO
container and IOMMU backend interfaces.  The compatibility mode can
also be accessed if the VFIO container interface, ie. /dev/vfio/vfio is
simply symlinkâ€™d to /dev/iommu.  Note that at the time of writing, the
compatibility mode is not entirely feature complete relative to
VFIO_TYPE1v2_IOMMU (ex. DMA mapping MMIO) and does not attempt to
provide compatibility to the VFIO_SPAPR_TCE_IOMMU interface.  Therefore
it is not generally advisable at this time to switch from native VFIO
implementations to the IOMMUFD compatibility interfaces.”…””}”(hjô  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Kühj­  hžhubhÎ)”}”(hŒœLong term, VFIO users should migrate to device access through the cdev
interface described below, and native access through the IOMMUFD
provided interfaces.”h]”hŒœLong term, VFIO users should migrate to device access through the cdev
interface described below, and native access through the IOMMUFD
provided interfaces.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M	hj­  hžhubeh}”(h]”Œiommufd-and-vfio-iommu-type1”ah ]”h"]”Œiommufd and vfio_iommu_type1”ah$]”h&]”uh1h¡hh£hžhhŸhÌh Kóubh¢)”}”(hhh]”(h§)”}”(hŒVFIO Device cdev”h]”hŒVFIO Device cdev”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸhÌh MubhÎ)”}”(hŒUTraditionally user acquires a device fd via VFIO_GROUP_GET_DEVICE_FD
in a VFIO group.”h]”hŒUTraditionally user acquires a device fd via VFIO_GROUP_GET_DEVICE_FD
in a VFIO group.”…””}”(hj)  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj  hžhubhÎ)”}”(hXB  With CONFIG_VFIO_DEVICE_CDEV=y the user can now acquire a device fd
by directly opening a character device /dev/vfio/devices/vfioX where
"X" is the number allocated uniquely by VFIO for registered devices.
cdev interface does not support noiommu devices, so user should use
the legacy group interface if noiommu is wanted.”h]”hXF  With CONFIG_VFIO_DEVICE_CDEV=y the user can now acquire a device fd
by directly opening a character device /dev/vfio/devices/vfioX where
â€œXâ€ is the number allocated uniquely by VFIO for registered devices.
cdev interface does not support noiommu devices, so user should use
the legacy group interface if noiommu is wanted.”…””}”(hj7  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj  hžhubhÎ)”}”(hX*  The cdev only works with IOMMUFD.  Both VFIO drivers and applications
must adapt to the new cdev security model which requires using
VFIO_DEVICE_BIND_IOMMUFD to claim DMA ownership before starting to
actually use the device.  Once BIND succeeds then a VFIO device can
be fully accessed by the user.”h]”hX*  The cdev only works with IOMMUFD.  Both VFIO drivers and applications
must adapt to the new cdev security model which requires using
VFIO_DEVICE_BIND_IOMMUFD to claim DMA ownership before starting to
actually use the device.  Once BIND succeeds then a VFIO device can
be fully accessed by the user.”…””}”(hjE  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj  hžhubhÎ)”}”(hŒ­VFIO device cdev doesn't rely on VFIO group/container/iommu drivers.
Hence those modules can be fully compiled out in an environment
where no legacy VFIO application exists.”h]”hŒ¯VFIO device cdev doesnâ€™t rely on VFIO group/container/iommu drivers.
Hence those modules can be fully compiled out in an environment
where no legacy VFIO application exists.”…””}”(hjS  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj  hžhubhÎ)”}”(hŒTSo far SPAPR does not support IOMMUFD yet.  So it cannot support device
cdev either.”h]”hŒTSo far SPAPR does not support IOMMUFD yet.  So it cannot support device
cdev either.”…””}”(hja  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M#hj  hžhubhÎ)”}”(hX©  vfio device cdev access is still bound by IOMMU group semantics, ie. there
can be only one DMA owner for the group.  Devices belonging to the same
group can not be bound to multiple iommufd_ctx or shared between native
kernel and vfio bus driver or other driver supporting the driver_managed_dma
flag.  A violation of this ownership requirement will fail at the
VFIO_DEVICE_BIND_IOMMUFD ioctl, which gates full device access.”h]”hX©  vfio device cdev access is still bound by IOMMU group semantics, ie. there
can be only one DMA owner for the group.  Devices belonging to the same
group can not be bound to multiple iommufd_ctx or shared between native
kernel and vfio bus driver or other driver supporting the driver_managed_dma
flag.  A violation of this ownership requirement will fail at the
VFIO_DEVICE_BIND_IOMMUFD ioctl, which gates full device access.”…””}”(hjo  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M&hj  hžhubeh}”(h]”Œvfio-device-cdev”ah ]”h"]”Œvfio device cdev”ah$]”h&]”uh1h¡hh£hžhhŸhÌh Mubh¢)”}”(hhh]”(h§)”}”(hŒDevice cdev Example”h]”hŒDevice cdev Example”…””}”(hjˆ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj…  hžhhŸhÌh M.ubhÎ)”}”(hŒ5Assume user wants to access PCI device 0000:6a:01.0::”h]”hŒ4Assume user wants to access PCI device 0000:6a:01.0:”…””}”(hj–  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M0hj…  hžhubjæ  )”}”(hŒ6$ ls /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/
vfio0”h]”hŒ6$ ls /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/
vfio0”…””}”hj¤  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M2hj…  hžhubhÎ)”}”(hŒSThis device is therefore represented as vfio0.  The user can verify
its existence::”h]”hŒRThis device is therefore represented as vfio0.  The user can verify
its existence:”…””}”(hj²  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M5hj…  hžhubjæ  )”}”(hX  $ ls -l /dev/vfio/devices/vfio0
crw------- 1 root root 511, 0 Feb 16 01:22 /dev/vfio/devices/vfio0
$ cat /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/vfio0/dev
511:0
$ ls -l /dev/char/511\:0
lrwxrwxrwx 1 root root 21 Feb 16 01:22 /dev/char/511:0 -> ../vfio/devices/vfio0”h]”hX  $ ls -l /dev/vfio/devices/vfio0
crw------- 1 root root 511, 0 Feb 16 01:22 /dev/vfio/devices/vfio0
$ cat /sys/bus/pci/devices/0000:6a:01.0/vfio-dev/vfio0/dev
511:0
$ ls -l /dev/char/511\:0
lrwxrwxrwx 1 root root 21 Feb 16 01:22 /dev/char/511:0 -> ../vfio/devices/vfio0”…””}”hjÀ  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M8hj…  hžhubhÎ)”}”(hŒVThen provide the user with access to the device if unprivileged
operation is desired::”h]”hŒUThen provide the user with access to the device if unprivileged
operation is desired:”…””}”(hjÎ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M?hj…  hžhubjæ  )”}”(hŒ)$ chown user:user /dev/vfio/devices/vfio0”h]”hŒ)$ chown user:user /dev/vfio/devices/vfio0”…””}”hjÜ  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh MBhj…  hžhubhÎ)”}”(hŒ'Finally the user could get cdev fd by::”h]”hŒ&Finally the user could get cdev fd by:”…””}”(hjê  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MDhj…  hžhubjæ  )”}”(hŒ2cdev_fd = open("/dev/vfio/devices/vfio0", O_RDWR);”h]”hŒ2cdev_fd = open("/dev/vfio/devices/vfio0", O_RDWR);”…””}”hjø  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh MFhj…  hžhubhÎ)”}”(hŒ÷An opened cdev_fd doesn't give the user any permission of accessing
the device except binding the cdev_fd to an iommufd.  After that point
then the device is fully accessible including attaching it to an
IOMMUFD IOAS/HWPT to enable userspace DMA::”h]”hŒøAn opened cdev_fd doesnâ€™t give the user any permission of accessing
the device except binding the cdev_fd to an iommufd.  After that point
then the device is fully accessible including attaching it to an
IOMMUFD IOAS/HWPT to enable userspace DMA:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MHhj…  hžhubjæ  )”}”(hX¯  struct vfio_device_bind_iommufd bind = {
        .argsz = sizeof(bind),
        .flags = 0,
};
struct iommu_ioas_alloc alloc_data  = {
        .size = sizeof(alloc_data),
        .flags = 0,
};
struct vfio_device_attach_iommufd_pt attach_data = {
        .argsz = sizeof(attach_data),
        .flags = 0,
};
struct iommu_ioas_map map = {
        .size = sizeof(map),
        .flags = IOMMU_IOAS_MAP_READABLE |
                 IOMMU_IOAS_MAP_WRITEABLE |
                 IOMMU_IOAS_MAP_FIXED_IOVA,
        .__reserved = 0,
};

iommufd = open("/dev/iommu", O_RDWR);

bind.iommufd = iommufd;
ioctl(cdev_fd, VFIO_DEVICE_BIND_IOMMUFD, &bind);

ioctl(iommufd, IOMMU_IOAS_ALLOC, &alloc_data);
attach_data.pt_id = alloc_data.out_ioas_id;
ioctl(cdev_fd, VFIO_DEVICE_ATTACH_IOMMUFD_PT, &attach_data);

/* Allocate some space and setup a DMA mapping */
map.user_va = (int64_t)mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                            MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
map.iova = 0; /* 1MB starting at 0x0 from device view */
map.length = 1024 * 1024;
map.ioas_id = alloc_data.out_ioas_id;

ioctl(iommufd, IOMMU_IOAS_MAP, &map);

/* Other device operations as stated in "VFIO Usage Example" */”h]”hX¯  struct vfio_device_bind_iommufd bind = {
        .argsz = sizeof(bind),
        .flags = 0,
};
struct iommu_ioas_alloc alloc_data  = {
        .size = sizeof(alloc_data),
        .flags = 0,
};
struct vfio_device_attach_iommufd_pt attach_data = {
        .argsz = sizeof(attach_data),
        .flags = 0,
};
struct iommu_ioas_map map = {
        .size = sizeof(map),
        .flags = IOMMU_IOAS_MAP_READABLE |
                 IOMMU_IOAS_MAP_WRITEABLE |
                 IOMMU_IOAS_MAP_FIXED_IOVA,
        .__reserved = 0,
};

iommufd = open("/dev/iommu", O_RDWR);

bind.iommufd = iommufd;
ioctl(cdev_fd, VFIO_DEVICE_BIND_IOMMUFD, &bind);

ioctl(iommufd, IOMMU_IOAS_ALLOC, &alloc_data);
attach_data.pt_id = alloc_data.out_ioas_id;
ioctl(cdev_fd, VFIO_DEVICE_ATTACH_IOMMUFD_PT, &attach_data);

/* Allocate some space and setup a DMA mapping */
map.user_va = (int64_t)mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                            MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
map.iova = 0; /* 1MB starting at 0x0 from device view */
map.length = 1024 * 1024;
map.ioas_id = alloc_data.out_ioas_id;

ioctl(iommufd, IOMMU_IOAS_MAP, &map);

/* Other device operations as stated in "VFIO Usage Example" */”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh MMhj…  hžhubeh}”(h]”Œdevice-cdev-example”ah ]”h"]”Œdevice cdev example”ah$]”h&]”uh1h¡hh£hžhhŸhÌh M.ubh¢)”}”(hhh]”(h§)”}”(hŒVFIO User API”h]”hŒVFIO User API”…””}”(hj-  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj*  hžhhŸhÌh MvubhÎ)”}”(hŒDPlease see include/uapi/linux/vfio.h for complete API documentation.”h]”hŒDPlease see include/uapi/linux/vfio.h for complete API documentation.”…””}”(hj;  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mxhj*  hžhubeh}”(h]”Œvfio-user-api”ah ]”h"]”Œvfio user api”ah$]”h&]”uh1h¡hh£hžhhŸhÌh Mvubh¢)”}”(hhh]”(h§)”}”(hŒVFIO bus driver API”h]”hŒVFIO bus driver API”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjQ  hžhhŸhÌh M{ubhÎ)”}”(hŒßVFIO bus drivers, such as vfio-pci make use of only a few interfaces
into VFIO core.  When devices are bound and unbound to the driver,
Following interfaces are called when devices are bound to and
unbound from the driver::”h]”hŒÞVFIO bus drivers, such as vfio-pci make use of only a few interfaces
into VFIO core.  When devices are bound and unbound to the driver,
Following interfaces are called when devices are bound to and
unbound from the driver:”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M}hjQ  hžhubjæ  )”}”(hŒ¶int vfio_register_group_dev(struct vfio_device *device);
int vfio_register_emulated_iommu_dev(struct vfio_device *device);
void vfio_unregister_group_dev(struct vfio_device *device);”h]”hŒ¶int vfio_register_group_dev(struct vfio_device *device);
int vfio_register_emulated_iommu_dev(struct vfio_device *device);
void vfio_unregister_group_dev(struct vfio_device *device);”…””}”hjp  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M‚hjQ  hžhubhÎ)”}”(hŒÔThe driver should embed the vfio_device in its own structure and use
vfio_alloc_device() to allocate the structure, and can register
@init/@release callbacks to manage any private state wrapping the
vfio_device::”h]”hŒÓThe driver should embed the vfio_device in its own structure and use
vfio_alloc_device() to allocate the structure, and can register
@init/@release callbacks to manage any private state wrapping the
vfio_device:”…””}”(hj~  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M†hjQ  hžhubjæ  )”}”(hŒbvfio_alloc_device(dev_struct, member, dev, ops);
void vfio_put_device(struct vfio_device *device);”h]”hŒbvfio_alloc_device(dev_struct, member, dev, ops);
void vfio_put_device(struct vfio_device *device);”…””}”hjŒ  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M‹hjQ  hžhubhÎ)”}”(hX¡  vfio_register_group_dev() indicates to the core to begin tracking the
iommu_group of the specified dev and register the dev as owned by a VFIO bus
driver. Once vfio_register_group_dev() returns it is possible for userspace to
start accessing the driver, thus the driver should ensure it is completely
ready before calling it. The driver provides an ops structure for callbacks
similar to a file operations structure::”h]”hX   vfio_register_group_dev() indicates to the core to begin tracking the
iommu_group of the specified dev and register the dev as owned by a VFIO bus
driver. Once vfio_register_group_dev() returns it is possible for userspace to
start accessing the driver, thus the driver should ensure it is completely
ready before calling it. The driver provides an ops structure for callbacks
similar to a file operations structure:”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MŽhjQ  hžhubjæ  )”}”(hXl  struct vfio_device_ops {
        char    *name;
        int     (*init)(struct vfio_device *vdev);
        void    (*release)(struct vfio_device *vdev);
        int     (*bind_iommufd)(struct vfio_device *vdev,
                                struct iommufd_ctx *ictx, u32 *out_device_id);
        void    (*unbind_iommufd)(struct vfio_device *vdev);
        int     (*attach_ioas)(struct vfio_device *vdev, u32 *pt_id);
        void    (*detach_ioas)(struct vfio_device *vdev);
        int     (*open_device)(struct vfio_device *vdev);
        void    (*close_device)(struct vfio_device *vdev);
        ssize_t (*read)(struct vfio_device *vdev, char __user *buf,
                        size_t count, loff_t *ppos);
        ssize_t (*write)(struct vfio_device *vdev, const char __user *buf,
                 size_t count, loff_t *size);
        long    (*ioctl)(struct vfio_device *vdev, unsigned int cmd,
                         unsigned long arg);
        int     (*mmap)(struct vfio_device *vdev, struct vm_area_struct *vma);
        void    (*request)(struct vfio_device *vdev, unsigned int count);
        int     (*match)(struct vfio_device *vdev, char *buf);
        void    (*dma_unmap)(struct vfio_device *vdev, u64 iova, u64 length);
        int     (*device_feature)(struct vfio_device *device, u32 flags,
                                  void __user *arg, size_t argsz);
};”h]”hXl  struct vfio_device_ops {
        char    *name;
        int     (*init)(struct vfio_device *vdev);
        void    (*release)(struct vfio_device *vdev);
        int     (*bind_iommufd)(struct vfio_device *vdev,
                                struct iommufd_ctx *ictx, u32 *out_device_id);
        void    (*unbind_iommufd)(struct vfio_device *vdev);
        int     (*attach_ioas)(struct vfio_device *vdev, u32 *pt_id);
        void    (*detach_ioas)(struct vfio_device *vdev);
        int     (*open_device)(struct vfio_device *vdev);
        void    (*close_device)(struct vfio_device *vdev);
        ssize_t (*read)(struct vfio_device *vdev, char __user *buf,
                        size_t count, loff_t *ppos);
        ssize_t (*write)(struct vfio_device *vdev, const char __user *buf,
                 size_t count, loff_t *size);
        long    (*ioctl)(struct vfio_device *vdev, unsigned int cmd,
                         unsigned long arg);
        int     (*mmap)(struct vfio_device *vdev, struct vm_area_struct *vma);
        void    (*request)(struct vfio_device *vdev, unsigned int count);
        int     (*match)(struct vfio_device *vdev, char *buf);
        void    (*dma_unmap)(struct vfio_device *vdev, u64 iova, u64 length);
        int     (*device_feature)(struct vfio_device *device, u32 flags,
                                  void __user *arg, size_t argsz);
};”…””}”hj¨  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M•hjQ  hžhubhÎ)”}”(hŒÞEach function is passed the vdev that was originally registered
in the vfio_register_group_dev() or vfio_register_emulated_iommu_dev()
call above. This allows the bus driver to obtain its private data using
container_of().”h]”hŒÞEach function is passed the vdev that was originally registered
in the vfio_register_group_dev() or vfio_register_emulated_iommu_dev()
call above. This allows the bus driver to obtain its private data using
container_of().”…””}”(hj¶  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M®hjQ  hžhubjæ  )”}”(hX  - The init/release callbacks are issued when vfio_device is initialized
  and released.

- The open/close device callbacks are issued when the first
  instance of a file descriptor for the device is created (eg.
  via VFIO_GROUP_GET_DEVICE_FD) for a user session.

- The ioctl callback provides a direct pass through for some VFIO_DEVICE_*
  ioctls.

- The [un]bind_iommufd callbacks are issued when the device is bound to
  and unbound from iommufd.

- The [de]attach_ioas callback is issued when the device is attached to
  and detached from an IOAS managed by the bound iommufd. However, the
  attached IOAS can also be automatically detached when the device is
  unbound from iommufd.

- The read/write/mmap callbacks implement the device region access defined
  by the device's own VFIO_DEVICE_GET_REGION_INFO ioctl.

- The request callback is issued when device is going to be unregistered,
  such as when trying to unbind the device from the vfio bus driver.

- The dma_unmap callback is issued when a range of iovas are unmapped
  in the container or IOAS attached by the device. Drivers which make
  use of the vfio page pinning interface must implement this callback in
  order to unpin pages within the dma_unmap range. Drivers must tolerate
  this callback even before calls to open_device().”h]”hX  - The init/release callbacks are issued when vfio_device is initialized
  and released.

- The open/close device callbacks are issued when the first
  instance of a file descriptor for the device is created (eg.
  via VFIO_GROUP_GET_DEVICE_FD) for a user session.

- The ioctl callback provides a direct pass through for some VFIO_DEVICE_*
  ioctls.

- The [un]bind_iommufd callbacks are issued when the device is bound to
  and unbound from iommufd.

- The [de]attach_ioas callback is issued when the device is attached to
  and detached from an IOAS managed by the bound iommufd. However, the
  attached IOAS can also be automatically detached when the device is
  unbound from iommufd.

- The read/write/mmap callbacks implement the device region access defined
  by the device's own VFIO_DEVICE_GET_REGION_INFO ioctl.

- The request callback is issued when device is going to be unregistered,
  such as when trying to unbind the device from the vfio bus driver.

- The dma_unmap callback is issued when a range of iovas are unmapped
  in the container or IOAS attached by the device. Drivers which make
  use of the vfio page pinning interface must implement this callback in
  order to unpin pages within the dma_unmap range. Drivers must tolerate
  this callback even before calls to open_device().”…””}”hjÄ  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh MµhjQ  hžhubeh}”(h]”Œvfio-bus-driver-api”ah ]”h"]”Œvfio bus driver api”ah$]”h&]”uh1h¡hh£hžhhŸhÌh M{ubh¢)”}”(hhh]”(h§)”}”(hŒPPC64 sPAPR implementation note”h]”hŒPPC64 sPAPR implementation note”…””}”(hjÝ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÚ  hžhhŸhÌh MÔubhÎ)”}”(hŒ'This implementation has some specifics:”h]”hŒ'This implementation has some specifics:”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MÖhjÚ  hžhubhŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX˜  On older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
container is supported as an IOMMU table is allocated at the boot time,
one table per a IOMMU group which is a Partitionable Endpoint (PE)
(PE is often a PCI domain but not always).

Newer systems (POWER8 with IODA2) have improved hardware design which allows
to remove this limitation and have multiple IOMMU groups per a VFIO
container.
”h]”(hÎ)”}”(hŒúOn older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
container is supported as an IOMMU table is allocated at the boot time,
one table per a IOMMU group which is a Partitionable Endpoint (PE)
(PE is often a PCI domain but not always).”h]”hŒúOn older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
container is supported as an IOMMU table is allocated at the boot time,
one table per a IOMMU group which is a Partitionable Endpoint (PE)
(PE is often a PCI domain but not always).”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MØhj   ubhÎ)”}”(hŒ›Newer systems (POWER8 with IODA2) have improved hardware design which allows
to remove this limitation and have multiple IOMMU groups per a VFIO
container.”h]”hŒ›Newer systems (POWER8 with IODA2) have improved hardware design which allows
to remove this limitation and have multiple IOMMU groups per a VFIO
container.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MÝhj   ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubjÿ  )”}”(hŒÁThe hardware supports so called DMA windows - the PCI address range
within which DMA transfer is allowed, any attempt to access address space
out of the window leads to the whole PE isolation.
”h]”hÎ)”}”(hŒÀThe hardware supports so called DMA windows - the PCI address range
within which DMA transfer is allowed, any attempt to access address space
out of the window leads to the whole PE isolation.”h]”hŒÀThe hardware supports so called DMA windows - the PCI address range
within which DMA transfer is allowed, any attempt to access address space
out of the window leads to the whole PE isolation.”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Máhj&  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubjÿ  )”}”(hX¡  PPC64 guests are paravirtualized but not fully emulated. There is an API
to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
currently there is no way to reduce the number of calls. In order to make
things faster, the map/unmap handling has been implemented in real mode
which provides an excellent performance which has limitations such as
inability to do locked pages accounting in real time.
”h]”hÎ)”}”(hX   PPC64 guests are paravirtualized but not fully emulated. There is an API
to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
currently there is no way to reduce the number of calls. In order to make
things faster, the map/unmap handling has been implemented in real mode
which provides an excellent performance which has limitations such as
inability to do locked pages accounting in real time.”h]”hX   PPC64 guests are paravirtualized but not fully emulated. There is an API
to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
currently there is no way to reduce the number of calls. In order to make
things faster, the map/unmap handling has been implemented in real mode
which provides an excellent performance which has limitations such as
inability to do locked pages accounting in real time.”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Måhj>  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubjÿ  )”}”(hXû  According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
subtree that can be treated as a unit for the purposes of partitioning and
error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
function of a multi-function IOA, or multiple IOAs (possibly including
switch and bridge structures above the multiple IOAs). PPC64 guests detect
PCI errors and recover from them via EEH RTAS services, which works on the
basis of additional ioctl commands.

So 4 additional ioctls have been added:

     VFIO_IOMMU_SPAPR_TCE_GET_INFO
             returns the size and the start of the DMA window on the PCI bus.

     VFIO_IOMMU_ENABLE
             enables the container. The locked pages accounting
             is done at this point. This lets user first to know what
             the DMA window is and adjust rlimit before doing any real job.

     VFIO_IOMMU_DISABLE
             disables the container.

     VFIO_EEH_PE_OP
             provides an API for EEH setup, error detection and recovery.

The code flow from the example above should be slightly changed::

     struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 };

     .....
     /* Add the group to the container */
     ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);

     /* Enable the IOMMU model we want */
     ioctl(container, VFIO_SET_IOMMU, VFIO_SPAPR_TCE_IOMMU)

     /* Get addition sPAPR IOMMU info */
     vfio_iommu_spapr_tce_info spapr_iommu_info;
     ioctl(container, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &spapr_iommu_info);

     if (ioctl(container, VFIO_IOMMU_ENABLE))
             /* Cannot enable container, may be low rlimit */

     /* Allocate some space and setup a DMA mapping */
     dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                          MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);

     dma_map.size = 1024 * 1024;
     dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
     dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;

     /* Check here is .iova/.size are within DMA window from spapr_iommu_info */
     ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);

     /* Get a file descriptor for the device */
     device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");

     ....

     /* Gratuitous device reset and go... */
     ioctl(device, VFIO_DEVICE_RESET);

     /* Make sure EEH is supported */
     ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH);

     /* Enable the EEH functionality on the device */
     pe_op.op = VFIO_EEH_PE_ENABLE;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /* You're suggested to create additional data struct to represent
      * PE, and put child devices belonging to same IOMMU group to the
      * PE instance for later reference.
      */

     /* Check the PE's state and make sure it's in functional state */
     pe_op.op = VFIO_EEH_PE_GET_STATE;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /* Save device state using pci_save_state().
      * EEH should be enabled on the specified device.
      */

     ....

     /* Inject EEH error, which is expected to be caused by 32-bits
      * config load.
      */
     pe_op.op = VFIO_EEH_PE_INJECT_ERR;
     pe_op.err.type = EEH_ERR_TYPE_32;
     pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
     pe_op.err.addr = 0ul;
     pe_op.err.mask = 0ul;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     ....

     /* When 0xFF's returned from reading PCI config space or IO BARs
      * of the PCI device. Check the PE's state to see if that has been
      * frozen.
      */
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /* Waiting for pending PCI transactions to be completed and don't
      * produce any more PCI traffic from/to the affected PE until
      * recovery is finished.
      */

     /* Enable IO for the affected PE and collect logs. Usually, the
      * standard part of PCI config space, AER registers are dumped
      * as logs for further analysis.
      */
     pe_op.op = VFIO_EEH_PE_UNFREEZE_IO;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /*
      * Issue PE reset: hot or fundamental reset. Usually, hot reset
      * is enough. However, the firmware of some PCI adapters would
      * require fundamental reset.
      */
     pe_op.op = VFIO_EEH_PE_RESET_HOT;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);
     pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /* Configure the PCI bridges for the affected PE */
     pe_op.op = VFIO_EEH_PE_CONFIGURE;
     ioctl(container, VFIO_EEH_PE_OP, &pe_op);

     /* Restored state we saved at initialization time. pci_restore_state()
      * is good enough as an example.
      */

     /* Hopefully, error is recovered successfully. Now, you can resume to
      * start PCI traffic to/from the affected PE.
      */

     ....
”h]”(hÎ)”}”(hXà  According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
subtree that can be treated as a unit for the purposes of partitioning and
error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
function of a multi-function IOA, or multiple IOAs (possibly including
switch and bridge structures above the multiple IOAs). PPC64 guests detect
PCI errors and recover from them via EEH RTAS services, which works on the
basis of additional ioctl commands.”h]”hXà  According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
subtree that can be treated as a unit for the purposes of partitioning and
error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
function of a multi-function IOA, or multiple IOAs (possibly including
switch and bridge structures above the multiple IOAs). PPC64 guests detect
PCI errors and recover from them via EEH RTAS services, which works on the
basis of additional ioctl commands.”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MìhjV  ubhÎ)”}”(hŒ'So 4 additional ioctls have been added:”h]”hŒ'So 4 additional ioctls have been added:”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MôhjV  ubhŒblock_quote”“”)”}”(hXÆ  VFIO_IOMMU_SPAPR_TCE_GET_INFO
        returns the size and the start of the DMA window on the PCI bus.

VFIO_IOMMU_ENABLE
        enables the container. The locked pages accounting
        is done at this point. This lets user first to know what
        the DMA window is and adjust rlimit before doing any real job.

VFIO_IOMMU_DISABLE
        disables the container.

VFIO_EEH_PE_OP
        provides an API for EEH setup, error detection and recovery.
”h]”hŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒ_VFIO_IOMMU_SPAPR_TCE_GET_INFO
returns the size and the start of the DMA window on the PCI bus.
”h]”(hŒterm”“”)”}”(hŒVFIO_IOMMU_SPAPR_TCE_GET_INFO”h]”hŒVFIO_IOMMU_SPAPR_TCE_GET_INFO”…””}”(hj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‡  hŸhÌh M÷hjƒ  ubhŒ
definition”“”)”}”(hhh]”hÎ)”}”(hŒ@returns the size and the start of the DMA window on the PCI bus.”h]”hŒ@returns the size and the start of the DMA window on the PCI bus.”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M÷hj™  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j—  hjƒ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸhÌh M÷hj~  ubj‚  )”}”(hŒ½VFIO_IOMMU_ENABLE
enables the container. The locked pages accounting
is done at this point. This lets user first to know what
the DMA window is and adjust rlimit before doing any real job.
”h]”(jˆ  )”}”(hŒVFIO_IOMMU_ENABLE”h]”hŒVFIO_IOMMU_ENABLE”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‡  hŸhÌh Mühj¶  ubj˜  )”}”(hhh]”hÎ)”}”(hŒªenables the container. The locked pages accounting
is done at this point. This lets user first to know what
the DMA window is and adjust rlimit before doing any real job.”h]”hŒªenables the container. The locked pages accounting
is done at this point. This lets user first to know what
the DMA window is and adjust rlimit before doing any real job.”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MúhjÈ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j—  hj¶  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸhÌh Mühj~  ubj‚  )”}”(hŒ+VFIO_IOMMU_DISABLE
disables the container.
”h]”(jˆ  )”}”(hŒVFIO_IOMMU_DISABLE”h]”hŒVFIO_IOMMU_DISABLE”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‡  hŸhÌh Mÿhjå  ubj˜  )”}”(hhh]”hÎ)”}”(hŒdisables the container.”h]”hŒdisables the container.”…””}”(hjú  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mÿhj÷  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j—  hjå  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸhÌh Mÿhj~  ubj‚  )”}”(hŒLVFIO_EEH_PE_OP
provides an API for EEH setup, error detection and recovery.
”h]”(jˆ  )”}”(hŒVFIO_EEH_PE_OP”h]”hŒVFIO_EEH_PE_OP”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j‡  hŸhÌh Mhj  ubj˜  )”}”(hhh]”hÎ)”}”(hŒ<provides an API for EEH setup, error detection and recovery.”h]”hŒ<provides an API for EEH setup, error detection and recovery.”…””}”(hj)  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj&  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j—  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸhÌh Mhj~  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j|  hjx  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jv  hŸhÌh MöhjV  ubhÎ)”}”(hŒAThe code flow from the example above should be slightly changed::”h]”hŒ@The code flow from the example above should be slightly changed:”…””}”(hjO  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MhjV  ubjæ  )”}”(hX  struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 };

.....
/* Add the group to the container */
ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);

/* Enable the IOMMU model we want */
ioctl(container, VFIO_SET_IOMMU, VFIO_SPAPR_TCE_IOMMU)

/* Get addition sPAPR IOMMU info */
vfio_iommu_spapr_tce_info spapr_iommu_info;
ioctl(container, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &spapr_iommu_info);

if (ioctl(container, VFIO_IOMMU_ENABLE))
        /* Cannot enable container, may be low rlimit */

/* Allocate some space and setup a DMA mapping */
dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                     MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);

dma_map.size = 1024 * 1024;
dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;

/* Check here is .iova/.size are within DMA window from spapr_iommu_info */
ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);

/* Get a file descriptor for the device */
device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");

....

/* Gratuitous device reset and go... */
ioctl(device, VFIO_DEVICE_RESET);

/* Make sure EEH is supported */
ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH);

/* Enable the EEH functionality on the device */
pe_op.op = VFIO_EEH_PE_ENABLE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* You're suggested to create additional data struct to represent
 * PE, and put child devices belonging to same IOMMU group to the
 * PE instance for later reference.
 */

/* Check the PE's state and make sure it's in functional state */
pe_op.op = VFIO_EEH_PE_GET_STATE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Save device state using pci_save_state().
 * EEH should be enabled on the specified device.
 */

....

/* Inject EEH error, which is expected to be caused by 32-bits
 * config load.
 */
pe_op.op = VFIO_EEH_PE_INJECT_ERR;
pe_op.err.type = EEH_ERR_TYPE_32;
pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
pe_op.err.addr = 0ul;
pe_op.err.mask = 0ul;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

....

/* When 0xFF's returned from reading PCI config space or IO BARs
 * of the PCI device. Check the PE's state to see if that has been
 * frozen.
 */
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Waiting for pending PCI transactions to be completed and don't
 * produce any more PCI traffic from/to the affected PE until
 * recovery is finished.
 */

/* Enable IO for the affected PE and collect logs. Usually, the
 * standard part of PCI config space, AER registers are dumped
 * as logs for further analysis.
 */
pe_op.op = VFIO_EEH_PE_UNFREEZE_IO;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/*
 * Issue PE reset: hot or fundamental reset. Usually, hot reset
 * is enough. However, the firmware of some PCI adapters would
 * require fundamental reset.
 */
pe_op.op = VFIO_EEH_PE_RESET_HOT;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);
pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Configure the PCI bridges for the affected PE */
pe_op.op = VFIO_EEH_PE_CONFIGURE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Restored state we saved at initialization time. pci_restore_state()
 * is good enough as an example.
 */

/* Hopefully, error is recovered successfully. Now, you can resume to
 * start PCI traffic to/from the affected PE.
 */

....”•ŠT      h]”hX  struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 };

.....
/* Add the group to the container */
ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);

/* Enable the IOMMU model we want */
ioctl(container, VFIO_SET_IOMMU, VFIO_SPAPR_TCE_IOMMU)

/* Get addition sPAPR IOMMU info */
vfio_iommu_spapr_tce_info spapr_iommu_info;
ioctl(container, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &spapr_iommu_info);

if (ioctl(container, VFIO_IOMMU_ENABLE))
        /* Cannot enable container, may be low rlimit */

/* Allocate some space and setup a DMA mapping */
dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
                     MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);

dma_map.size = 1024 * 1024;
dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;

/* Check here is .iova/.size are within DMA window from spapr_iommu_info */
ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);

/* Get a file descriptor for the device */
device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");

....

/* Gratuitous device reset and go... */
ioctl(device, VFIO_DEVICE_RESET);

/* Make sure EEH is supported */
ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH);

/* Enable the EEH functionality on the device */
pe_op.op = VFIO_EEH_PE_ENABLE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* You're suggested to create additional data struct to represent
 * PE, and put child devices belonging to same IOMMU group to the
 * PE instance for later reference.
 */

/* Check the PE's state and make sure it's in functional state */
pe_op.op = VFIO_EEH_PE_GET_STATE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Save device state using pci_save_state().
 * EEH should be enabled on the specified device.
 */

....

/* Inject EEH error, which is expected to be caused by 32-bits
 * config load.
 */
pe_op.op = VFIO_EEH_PE_INJECT_ERR;
pe_op.err.type = EEH_ERR_TYPE_32;
pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
pe_op.err.addr = 0ul;
pe_op.err.mask = 0ul;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

....

/* When 0xFF's returned from reading PCI config space or IO BARs
 * of the PCI device. Check the PE's state to see if that has been
 * frozen.
 */
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Waiting for pending PCI transactions to be completed and don't
 * produce any more PCI traffic from/to the affected PE until
 * recovery is finished.
 */

/* Enable IO for the affected PE and collect logs. Usually, the
 * standard part of PCI config space, AER registers are dumped
 * as logs for further analysis.
 */
pe_op.op = VFIO_EEH_PE_UNFREEZE_IO;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/*
 * Issue PE reset: hot or fundamental reset. Usually, hot reset
 * is enough. However, the firmware of some PCI adapters would
 * require fundamental reset.
 */
pe_op.op = VFIO_EEH_PE_RESET_HOT;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);
pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Configure the PCI bridges for the affected PE */
pe_op.op = VFIO_EEH_PE_CONFIGURE;
ioctl(container, VFIO_EEH_PE_OP, &pe_op);

/* Restored state we saved at initialization time. pci_restore_state()
 * is good enough as an example.
 */

/* Hopefully, error is recovered successfully. Now, you can resume to
 * start PCI traffic to/from the affected PE.
 */

....”…””}”hj]  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh MhjV  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubjÿ  )”}”(hX…  There is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
VFIO_IOMMU_DISABLE and implements 2 new ioctls:
VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
(which are unsupported in v1 IOMMU).

PPC64 paravirtualized guests generate a lot of map/unmap requests,
and the handling of those includes pinning/unpinning pages and updating
mm::locked_vm counter to make sure we do not exceed the rlimit.
The v2 IOMMU splits accounting and pinning into separate operations:

- VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
  receive a user space address and size of the block to be pinned.
  Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
  be called with the exact address and size used for registering
  the memory block. The userspace is not expected to call these often.
  The ranges are stored in a linked list in a VFIO container.

- VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
  IOMMU table and do not do pinning; instead these check that the userspace
  address is from pre-registered range.

This separation helps in optimizing DMA for guests.
”h]”(hÎ)”}”(hŒÝThere is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
VFIO_IOMMU_DISABLE and implements 2 new ioctls:
VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
(which are unsupported in v1 IOMMU).”h]”hŒÝThere is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
VFIO_IOMMU_DISABLE and implements 2 new ioctls:
VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
(which are unsupported in v1 IOMMU).”…””}”(hju  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Muhjq  ubhÎ)”}”(hX  PPC64 paravirtualized guests generate a lot of map/unmap requests,
and the handling of those includes pinning/unpinning pages and updating
mm::locked_vm counter to make sure we do not exceed the rlimit.
The v2 IOMMU splits accounting and pinning into separate operations:”h]”hX  PPC64 paravirtualized guests generate a lot of map/unmap requests,
and the handling of those includes pinning/unpinning pages and updating
mm::locked_vm counter to make sure we do not exceed the rlimit.
The v2 IOMMU splits accounting and pinning into separate operations:”…””}”(hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mzhjq  ubhŒbullet_list”“”)”}”(hhh]”(jÿ  )”}”(hX—  VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
receive a user space address and size of the block to be pinned.
Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
be called with the exact address and size used for registering
the memory block. The userspace is not expected to call these often.
The ranges are stored in a linked list in a VFIO container.
”h]”hÎ)”}”(hX–  VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
receive a user space address and size of the block to be pinned.
Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
be called with the exact address and size used for registering
the memory block. The userspace is not expected to call these often.
The ranges are stored in a linked list in a VFIO container.”h]”hX–  VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
receive a user space address and size of the block to be pinned.
Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
be called with the exact address and size used for registering
the memory block. The userspace is not expected to call these often.
The ranges are stored in a linked list in a VFIO container.”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mhj–  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hj“  ubjÿ  )”}”(hŒ¶VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
IOMMU table and do not do pinning; instead these check that the userspace
address is from pre-registered range.
”h]”hÎ)”}”(hŒµVFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
IOMMU table and do not do pinning; instead these check that the userspace
address is from pre-registered range.”h]”hŒµVFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
IOMMU table and do not do pinning; instead these check that the userspace
address is from pre-registered range.”…””}”(hj²  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M†hj®  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hj“  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j‘  hŸhÌh Mhjq  ubhÎ)”}”(hŒ3This separation helps in optimizing DMA for guests.”h]”hŒ3This separation helps in optimizing DMA for guests.”…””}”(hjÎ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MŠhjq  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubjÿ  )”}”(hX<  sPAPR specification allows guests to have an additional DMA window(s) on
a PCI bus with a variable page size. Two ioctls have been added to support
this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
The platform has to support the functionality or error will be returned to
the userspace. The existing hardware supports up to 2 DMA windows, one is
2GB long, uses 4K pages and called "default 32bit window"; the other can
be as big as entire RAM, use different page size, it is optional - guests
create those in run-time if the guest driver supports 64bit DMA.

VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
a number of TCE table levels (if a TCE table is going to be big enough and
the kernel may not be able to allocate enough of physically contiguous
memory). It creates a new window in the available slot and returns the bus
address where the new window starts. Due to hardware limitation, the user
space cannot choose the location of DMA windows.

VFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
and removes it.
”h]”(hÎ)”}”(hX?  sPAPR specification allows guests to have an additional DMA window(s) on
a PCI bus with a variable page size. Two ioctls have been added to support
this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
The platform has to support the functionality or error will be returned to
the userspace. The existing hardware supports up to 2 DMA windows, one is
2GB long, uses 4K pages and called "default 32bit window"; the other can
be as big as entire RAM, use different page size, it is optional - guests
create those in run-time if the guest driver supports 64bit DMA.”h]”hXC  sPAPR specification allows guests to have an additional DMA window(s) on
a PCI bus with a variable page size. Two ioctls have been added to support
this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
The platform has to support the functionality or error will be returned to
the userspace. The existing hardware supports up to 2 DMA windows, one is
2GB long, uses 4K pages and called â€œdefault 32bit windowâ€; the other can
be as big as entire RAM, use different page size, it is optional - guests
create those in run-time if the guest driver supports 64bit DMA.”…””}”(hjæ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MŒhjâ  ubhÎ)”}”(hX   VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
a number of TCE table levels (if a TCE table is going to be big enough and
the kernel may not be able to allocate enough of physically contiguous
memory). It creates a new window in the available slot and returns the bus
address where the new window starts. Due to hardware limitation, the user
space cannot choose the location of DMA windows.”h]”hX   VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
a number of TCE table levels (if a TCE table is going to be big enough and
the kernel may not be able to allocate enough of physically contiguous
memory). It creates a new window in the available slot and returns the bus
address where the new window starts. Due to hardware limitation, the user
space cannot choose the location of DMA windows.”…””}”(hjô  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M•hjâ  ubhÎ)”}”(hŒXVFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
and removes it.”h]”hŒXVFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
and removes it.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mœhjâ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jþ  hjû  hžhhŸhÌh Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ)”uh1jù  hjÚ  hžhhŸhÌh MØubhŒ
transition”“”)”}”(hŒO-------------------------------------------------------------------------------”h]”h}”(h]”h ]”h"]”h$]”h&]”uh1j!  hŸhÌh MŸhjÚ  hžhubhŒfootnote”“”)”}”(hŒ¨VFIO was originally an acronym for "Virtual Function I/O" in its
initial implementation by Tom Lyon while as Cisco.  We've since
outgrown the acronym, but it's catchy.
”h]”(hŒlabel”“”)”}”(hŒ1”h]”hŒ1”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hj/  ubhÎ)”}”(hŒ§VFIO was originally an acronym for "Virtual Function I/O" in its
initial implementation by Tom Lyon while as Cisco.  We've since
outgrown the acronym, but it's catchy.”h]”hŒ¯VFIO was originally an acronym for â€œVirtual Function I/Oâ€ in its
initial implementation by Tom Lyon while as Cisco.  Weâ€™ve since
outgrown the acronym, but itâ€™s catchy.”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M¡hj/  ubeh}”(h]”hÂah ]”h"]”Œ1”ah$]”h&]”h¼ahÃhÄuh1j-  hŸhÌh M¡hjÚ  hžhhÅKubj.  )”}”(hXd  "safe" also depends upon a device being "well behaved".  It's
possible for multi-function devices to have backdoors between
functions and even for single function devices to have alternative
access to things like PCI config space through MMIO registers.  To
guard against the former we can include additional precautions in the
IOMMU driver to group multi-function PCI devices together
(iommu=group_mf).  The latter we can't prevent, but the IOMMU should
still provide isolation.  For PCI, SR-IOV Virtual Functions are the
best indicator of "well behaved", as these are designed for
virtualization usage models.
”h]”(j4  )”}”(hŒ2”h]”hŒ2”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hjX  ubhÎ)”}”(hXc  "safe" also depends upon a device being "well behaved".  It's
possible for multi-function devices to have backdoors between
functions and even for single function devices to have alternative
access to things like PCI config space through MMIO registers.  To
guard against the former we can include additional precautions in the
IOMMU driver to group multi-function PCI devices together
(iommu=group_mf).  The latter we can't prevent, but the IOMMU should
still provide isolation.  For PCI, SR-IOV Virtual Functions are the
best indicator of "well behaved", as these are designed for
virtualization usage models.”h]”hXs  â€œsafeâ€ also depends upon a device being â€œwell behavedâ€.  Itâ€™s
possible for multi-function devices to have backdoors between
functions and even for single function devices to have alternative
access to things like PCI config space through MMIO registers.  To
guard against the former we can include additional precautions in the
IOMMU driver to group multi-function PCI devices together
(iommu=group_mf).  The latter we canâ€™t prevent, but the IOMMU should
still provide isolation.  For PCI, SR-IOV Virtual Functions are the
best indicator of â€œwell behavedâ€, as these are designed for
virtualization usage models.”…””}”(hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M¥hjX  ubeh}”(h]”hæah ]”h"]”Œ2”ah$]”h&]”háahÃhÄuh1j-  hŸhÌh M¥hjÚ  hžhhÅKubj.  )”}”(hŒÏAs always there are trade-offs to virtual machine device
assignment that are beyond the scope of VFIO.  It's expected that
future IOMMU technologies will reduce some, but maybe not all, of
these trade-offs.
”h]”(j4  )”}”(hŒ3”h]”hŒ3”…””}”(hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hj  ubhÎ)”}”(hŒÎAs always there are trade-offs to virtual machine device
assignment that are beyond the scope of VFIO.  It's expected that
future IOMMU technologies will reduce some, but maybe not all, of
these trade-offs.”h]”hŒÐAs always there are trade-offs to virtual machine device
assignment that are beyond the scope of VFIO.  Itâ€™s expected that
future IOMMU technologies will reduce some, but maybe not all, of
these trade-offs.”…””}”(hj‘  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M°hj  ubeh}”(h]”j  ah ]”h"]”Œ3”ah$]”h&]”j  ahÃhÄuh1j-  hŸhÌh M°hjÚ  hžhhÅKubj.  )”}”(hX  In this case the device is below a PCI bridge, so transactions
from either function of the device are indistinguishable to the iommu::

     -[0000:00]-+-1e.0-[06]--+-0d.0
                             \-0d.1

     00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)
”h]”(j4  )”}”(hŒ4”h]”hŒ4”…””}”(hjª  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hj¦  ubhÎ)”}”(hŒ†In this case the device is below a PCI bridge, so transactions
from either function of the device are indistinguishable to the iommu::”h]”hŒ…In this case the device is below a PCI bridge, so transactions
from either function of the device are indistinguishable to the iommu:”…””}”(hj¸  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh Mµhj¦  ubjæ  )”}”(hŒ~-[0000:00]-+-1e.0-[06]--+-0d.0
                        \-0d.1

00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)”h]”hŒ~-[0000:00]-+-1e.0-[06]--+-0d.0
                        \-0d.1

00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)”…””}”hjÆ  sbah}”(h]”h ]”h"]”h$]”h&]”jõ  jö  uh1jå  hŸhÌh M¸hj¦  ubeh}”(h]”jb  ah ]”h"]”Œ4”ah$]”h&]”j]  ahÃhÄuh1j-  hŸhÌh MµhjÚ  hžhhÅKubj.  )”}”(hŒ¡Nested translation is an IOMMU feature which supports two stage
address translations.  This improves the address translation efficiency
in IOMMU virtualization.
”h]”(j4  )”}”(hŒ5”h]”hŒ5”…””}”(hjß  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hjÛ  ubhÎ)”}”(hŒ Nested translation is an IOMMU feature which supports two stage
address translations.  This improves the address translation efficiency
in IOMMU virtualization.”h]”hŒ Nested translation is an IOMMU feature which supports two stage
address translations.  This improves the address translation efficiency
in IOMMU virtualization.”…””}”(hjí  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh M½hjÛ  ubeh}”(h]”jÕ  ah ]”h"]”Œ5”ah$]”h&]”jÐ  ahÃhÄuh1j-  hŸhÌh M½hjÚ  hžhhÅKubj.  )”}”(hŒ¯PASID stands for Process Address Space ID, introduced by PCI
Express.  It is a prerequisite for Shared Virtual Addressing (SVA)
and Scalable I/O Virtualization (Scalable IOV).”h]”(j4  )”}”(hŒ6”h]”hŒ6”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j3  hj  ubhÎ)”}”(hŒ¯PASID stands for Process Address Space ID, introduced by PCI
Express.  It is a prerequisite for Shared Virtual Addressing (SVA)
and Scalable I/O Virtualization (Scalable IOV).”h]”hŒ¯PASID stands for Process Address Space ID, introduced by PCI
Express.  It is a prerequisite for Shared Virtual Addressing (SVA)
and Scalable I/O Virtualization (Scalable IOV).”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhŸhÌh MÁhj  ubeh}”(h]”jé  ah ]”h"]”Œ6”ah$]”h&]”jä  ahÃhÄuh1j-  hŸhÌh MÁhjÚ  hžhhÅKubeh}”(h]”Œppc64-spapr-implementation-note”ah ]”h"]”Œppc64 spapr implementation note”ah$]”h&]”uh1h¡hh£hžhhŸhÌh MÔubeh}”(h]”Œvfio-virtual-function-i-o-1”ah ]”h"]”Œvfio - "virtual function i/o" 1”ah$]”h&]”uh1h¡hhhžhhŸhÌh Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÌuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j\  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÌŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”(Œ1”]”h²aŒ2”]”h×aŒ3”]”hùaŒ4”]”jS  aŒ5”]”jÆ  aŒ6”]”jÚ  auŒrefids”}”Œnameids”}”(j6  j3  jÃ  jÀ  jª  j§  j  j  j‚  j  j'  j$  jN  jK  j×  jÔ  j.  j+  jU  hÂj|  hæj£  j  jØ  jb  jÿ  jÕ  j&  jé  uŒ	nametypes”}”(j6  ‰jÃ  ‰jª  ‰j  ‰j‚  ‰j'  ‰jN  ‰j×  ‰j.  ‰jU  ˆj|  ˆj£  ˆjØ  ˆjÿ  ˆj&  ˆuh}”(h¼h²j3  h£háh×j  hùjÀ  j/  j§  jÆ  j]  jS  j  j­  jÐ  jÆ  jä  jÚ  j  j  j$  j…  jK  j*  jÔ  jQ  j+  jÚ  hÂj/  hæjX  j  j  jb  j¦  jÕ  jÛ  jé  j  uŒfootnote_refs”}”(jœ  ]”h²ajž  ]”h×aj   ]”hùaj¢  ]”jS  aj¤  ]”jÆ  aj¦  ]”jÚ  auŒcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”(j/  jX  j  j¦  jÛ  j  eŒ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”jj  Ks…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.