sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget1/translations/zh_CN/driver-api/thermal/intel_dptfmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/zh_TW/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/it_IT/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ja_JP/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ko_KR/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/pt_BR/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/sp_SP/driver-api/thermal/intel_dptfmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhK/var/lib/git/docbuild/linux/Documentation/driver-api/thermal/intel_dptf.rsthKubhsection)}(hhh](htitle)}(h?Intel(R) Dynamic Platform and Thermal Framework Sysfs Interfaceh]h?Intel(R) Dynamic Platform and Thermal Framework Sysfs Interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h© 2022 Intel Corporation h]h paragraph)}(h© 2022 Intel Corporationh]h© 2022 Intel Corporation}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hAuthorh]hAuthor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h:Srinivas Pandruvada h]h)}(h9Srinivas Pandruvada h](hSrinivas Pandruvada <}(hj.hhhNhNubh reference)}(h#srinivas.pandruvada@linux.intel.comh]h#srinivas.pandruvada@linux.intel.com}(hj8hhhNhNubah}(h]h ]h"]h$]h&]refuri*mailto:srinivas.pandruvada@linux.intel.comuh1j6hj.ubh>}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hj*ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Introductionh]h Introduction}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhK ubh)}(hIntel(R) Dynamic Platform and Thermal Framework (DPTF) is a platform level hardware/software solution for power and thermal management.h]hIntel(R) Dynamic Platform and Thermal Framework (DPTF) is a platform level hardware/software solution for power and thermal management.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hAs a container for multiple power/thermal technologies, DPTF provides a coordinated approach for different policies to effect the hardware state of a system.h]hAs a container for multiple power/thermal technologies, DPTF provides a coordinated approach for different policies to effect the hardware state of a system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hXSince it is a platform level framework, this has several components. Some parts of the technology is implemented in the firmware and uses ACPI and PCI devices to expose various features for monitoring and control. Linux has a set of kernel drivers exposing hardware interface to user space. This allows user space thermal solutions like "Linux Thermal Daemon" to read platform specific thermal and power tables to deliver adequate performance while keeping the system under thermal limits.h]hXSince it is a platform level framework, this has several components. Some parts of the technology is implemented in the firmware and uses ACPI and PCI devices to expose various features for monitoring and control. Linux has a set of kernel drivers exposing hardware interface to user space. This allows user space thermal solutions like “Linux Thermal Daemon” to read platform specific thermal and power tables to deliver adequate performance while keeping the system under thermal limits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hDPTF ACPI Drivers interfaceh]hDPTF ACPI Drivers interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hZ:file:`/sys/bus/platform/devices//uuids`, where =INT3400|INTC1040|INTC1041|INTC10A0h](hliteral)}(h+:file:`/sys/bus/platform/devices//uuids`h]h#/sys/bus/platform/devices//uuids}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjubh/, where =INT3400|INTC1040|INTC1041|INTC10A0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK!hjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hX``available_uuids`` (RO) A set of UUIDs strings presenting available policies which should be notified to the firmware when the user space can support those policies. UUID strings: "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss "6ED722A7-9240-48A5-B479-31EEF723D7CF" : Virtual Sensor "16CAF1B7-DD38-40ED-B1C1-1B8A1913D531" : Cooling mode "BE84BABF-C4D4-403D-B495-3128FD44dAC1" : HDC h](hterm)}(h``available_uuids`` (RO)h](j)}(h``available_uuids``h]havailable_uuids}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhK=hjubh definition)}(hhh](h)}(hA set of UUIDs strings presenting available policies which should be notified to the firmware when the user space can support those policies.h]hA set of UUIDs strings presenting available policies which should be notified to the firmware when the user space can support those policies.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubh)}(h UUID strings:h]h UUID strings:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubh)}(h2"42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1h]h6“42A441D6-AE6A-462b-A84B-4A8CE79027D3” : Passive 1}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubh)}(h/"3A95C389-E4B8-4629-A526-C52C88626BAE" : Activeh]h3“3A95C389-E4B8-4629-A526-C52C88626BAE” : Active}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubh)}(h1"97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Criticalh]h5“97C68AE7-15FA-499c-B8C9-5DA81D606E0A” : Critical}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubh)}(h="63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performanceh]hA“63BE270F-1C11-48FD-A6F7-3AF253FF3E2D” : Adaptive performance}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubh)}(h7"5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency callh]h;“5349962F-71E6-431D-9AE8-0A635B710AEE” : Emergency call}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubh)}(h2"9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2h]h6“9E04115A-AE87-4D1C-9500-0F3E340BFE75” : Passive 2}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubh)}(h3"F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Bossh]h7“F5A35014-C209-46A4-993A-EB56DE7530A1” : Power Boss}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubh)}(h7"6ED722A7-9240-48A5-B479-31EEF723D7CF" : Virtual Sensorh]h;“6ED722A7-9240-48A5-B479-31EEF723D7CF” : Virtual Sensor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubh)}(h5"16CAF1B7-DD38-40ED-B1C1-1B8A1913D531" : Cooling modeh]h9“16CAF1B7-DD38-40ED-B1C1-1B8A1913D531” : Cooling mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjubh)}(h,"BE84BABF-C4D4-403D-B495-3128FD44dAC1" : HDCh]h0“BE84BABF-C4D4-403D-B495-3128FD44dAC1” : HDC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK=hjubj)}(hX``current_uuid`` (RW) User space can write strings from available UUIDs, one at a time. h](j)}(h``current_uuid`` (RW)h](j)}(h``current_uuid``h]h current_uuid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKAhjubj)}(hhh]h)}(hAUser space can write strings from available UUIDs, one at a time.h]hAUser space can write strings from available UUIDs, one at a time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKAhjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hU:file:`/sys/bus/platform/devices//`, where =INT3400|INTC1040|INTC1041|INTC10A0h](j)}(h&:file:`/sys/bus/platform/devices//`h]h/sys/bus/platform/devices//}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjubh/, where =INT3400|INTC1040|INTC1041|INTC10A0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKChjhhubj)}(hhh](j)}(h``imok`` (WO) User space daemon write 1 to respond to firmware event for sending keep alive notification. User space receives THERMAL_EVENT_KEEP_ALIVE kobject uevent notification when firmware calls for user space to respond with imok ACPI method. h](j)}(h ``imok`` (WO)h](j)}(h``imok``h]himok}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh (WO)}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKKhj ubj)}(hhh]h)}(hUser space daemon write 1 to respond to firmware event for sending keep alive notification. User space receives THERMAL_EVENT_KEEP_ALIVE kobject uevent notification when firmware calls for user space to respond with imok ACPI method.h]hUser space daemon write 1 to respond to firmware event for sending keep alive notification. User space receives THERMAL_EVENT_KEEP_ALIVE kobject uevent notification when firmware calls for user space to respond with imok ACPI method.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj@ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKKhjubj)}(h``odvp*`` (RO) Firmware thermal status variable values. Thermal tables calls for different processing based on these variable values. h](j)}(h``odvp*`` (RO)h](j)}(h ``odvp*``h]hodvp*}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh (RO)}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKPhj]ubj)}(hhh]h)}(hvFirmware thermal status variable values. Thermal tables calls for different processing based on these variable values.h]hvFirmware thermal status variable values. Thermal tables calls for different processing based on these variable values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhj}ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhhhKPhjhhubj)}(hv``data_vault`` (RO) Binary thermal table. Refer to https:/github.com/intel/thermal_daemon for decoding thermal table. h](j)}(h``data_vault`` (RO)h](j)}(h``data_vault``h]h data_vault}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKUhjubj)}(hhh]h)}(haBinary thermal table. Refer to https:/github.com/intel/thermal_daemon for decoding thermal table.h](hBinary thermal table. Refer to }(hjhhhNhNubj7)}(h&https:/github.com/intel/thermal_daemonh]h&https:/github.com/intel/thermal_daemon}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1j6hjubh for decoding thermal table.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKShjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKUhjhhubj)}(hs``production_mode`` (RO) When different from zero, manufacturer locked thermal configuration from further changes. h](j)}(h``production_mode`` (RO)h](j)}(h``production_mode``h]hproduction_mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKYhjubj)}(hhh]h)}(hYWhen different from zero, manufacturer locked thermal configuration from further changes.h]hYWhen different from zero, manufacturer locked thermal configuration from further changes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKYhjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]dptf-acpi-drivers-interfaceah ]h"]dptf acpi drivers interfaceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h)ACPI Thermal Relationship table interfaceh]h)ACPI Thermal Relationship table interface}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhK\ubh)}(h:file:`/dev/acpi_thermal_rel`h]j)}(hjHh]h/dev/acpi_thermal_rel}(hjJhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjFubah}(h]h ]h"]h$]h&]uh1hhhhK^hj5hhubh block_quote)}(hXwThis device provides IOCTL interface to read standard ACPI thermal relationship tables via ACPI methods _TRT and _ART. These IOCTLs are defined in drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h IOCTLs: ACPI_THERMAL_GET_TRT_LEN: Get length of TRT table ACPI_THERMAL_GET_ART_LEN: Get length of ART table ACPI_THERMAL_GET_TRT_COUNT: Number of records in TRT table ACPI_THERMAL_GET_ART_COUNT: Number of records in ART table ACPI_THERMAL_GET_TRT: Read binary TRT table, length to read is provided via argument to ioctl(). ACPI_THERMAL_GET_ART: Read binary ART table, length to read is provided via argument to ioctl(). h](h)}(hThis device provides IOCTL interface to read standard ACPI thermal relationship tables via ACPI methods _TRT and _ART. These IOCTLs are defined in drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.hh]hThis device provides IOCTL interface to read standard ACPI thermal relationship tables via ACPI methods _TRT and _ART. These IOCTLs are defined in drivers/thermal/intel/int340x_thermal/acpi_thermal_rel.h}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjbubh)}(hIOCTLs:h]hIOCTLs:}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjbubh)}(h1ACPI_THERMAL_GET_TRT_LEN: Get length of TRT tableh]h1ACPI_THERMAL_GET_TRT_LEN: Get length of TRT table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjbubh)}(h1ACPI_THERMAL_GET_ART_LEN: Get length of ART tableh]h1ACPI_THERMAL_GET_ART_LEN: Get length of ART table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjbubh)}(h:ACPI_THERMAL_GET_TRT_COUNT: Number of records in TRT tableh]h:ACPI_THERMAL_GET_TRT_COUNT: Number of records in TRT table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjbubh)}(h:ACPI_THERMAL_GET_ART_COUNT: Number of records in ART tableh]h:ACPI_THERMAL_GET_ART_COUNT: Number of records in ART table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjbubh)}(h`ACPI_THERMAL_GET_TRT: Read binary TRT table, length to read is provided via argument to ioctl().h]h`ACPI_THERMAL_GET_TRT: Read binary TRT table, length to read is provided via argument to ioctl().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjbubh)}(h`ACPI_THERMAL_GET_ART: Read binary ART table, length to read is provided via argument to ioctl().h]h`ACPI_THERMAL_GET_ART: Read binary ART table, length to read is provided via argument to ioctl().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjbubeh}(h]h ]h"]h$]h&]uh1j`hhhK`hj5hhubeh}(h])acpi-thermal-relationship-table-interfaceah ]h"])acpi thermal relationship table interfaceah$]h&]uh1hhhhhhhhK\ubh)}(hhh](h)}(hDPTF ACPI Sensor driversh]hDPTF ACPI Sensor drivers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKvubh)}(hIDPTF Sensor drivers are presented as standard thermal sysfs thermal_zone.h]hIDPTF Sensor drivers are presented as standard thermal sysfs thermal_zone.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjhhubeh}(h]dptf-acpi-sensor-driversah ]h"]dptf acpi sensor driversah$]h&]uh1hhhhhhhhKvubh)}(hhh](h)}(hDPTF ACPI Cooling driversh]hDPTF ACPI Cooling drivers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhK|ubh)}(hLDPTF cooling drivers are presented as standard thermal sysfs cooling_device.h]hLDPTF cooling drivers are presented as standard thermal sysfs cooling_device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hj hhubeh}(h]dptf-acpi-cooling-driversah ]h"]dptf acpi cooling driversah$]h&]uh1hhhhhhhhK|ubh)}(hhh](h)}(h+DPTF Processor thermal PCI Driver interfaceh]h+DPTF Processor thermal PCI Driver interface}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhKubh)}(h9:file:`/sys/bus/pci/devices/0000\:00\:04.0/power_limits/`h]j)}(h9:file:`/sys/bus/pci/devices/0000\:00\:04.0/power_limits/`h]h//sys/bus/pci/devices/0000:00:04.0/power_limits/}(hjGhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjCubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubh)}(hDRefer to Documentation/power/powercap/powercap.rst for powercap ABI.h]hDRefer to Documentation/power/powercap/powercap.rst for powercap ABI.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubj)}(hhh](j)}(h```power_limit_0_max_uw`` (RO) Maximum powercap sysfs constraint_0_power_limit_uw for Intel RAPL h](j)}(h``power_limit_0_max_uw`` (RO)h](j)}(h``power_limit_0_max_uw``h]hpower_limit_0_max_uw}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubh (RO)}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjoubj)}(hhh]h)}(hAMaximum powercap sysfs constraint_0_power_limit_uw for Intel RAPLh]hAMaximum powercap sysfs constraint_0_power_limit_uw for Intel RAPL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlubj)}(hh``power_limit_0_step_uw`` (RO) Power limit increment/decrements for Intel RAPL constraint 0 power limit h](j)}(h``power_limit_0_step_uw`` (RO)h](j)}(h``power_limit_0_step_uw``h]hpower_limit_0_step_uw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hHPower limit increment/decrements for Intel RAPL constraint 0 power limith]hHPower limit increment/decrements for Intel RAPL constraint 0 power limit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(h```power_limit_0_min_uw`` (RO) Minimum powercap sysfs constraint_0_power_limit_uw for Intel RAPL h](j)}(h``power_limit_0_min_uw`` (RO)h](j)}(h``power_limit_0_min_uw``h]hpower_limit_0_min_uw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hAMinimum powercap sysfs constraint_0_power_limit_uw for Intel RAPLh]hAMinimum powercap sysfs constraint_0_power_limit_uw for Intel RAPL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(ha``power_limit_0_tmin_us`` (RO) Minimum powercap sysfs constraint_0_time_window_us for Intel RAPL h](j)}(h``power_limit_0_tmin_us`` (RO)h](j)}(h``power_limit_0_tmin_us``h]hpower_limit_0_tmin_us}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh (RO)}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj&ubj)}(hhh]h)}(hAMinimum powercap sysfs constraint_0_time_window_us for Intel RAPLh]hAMinimum powercap sysfs constraint_0_time_window_us for Intel RAPL}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjFubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(ha``power_limit_0_tmax_us`` (RO) Maximum powercap sysfs constraint_0_time_window_us for Intel RAPL h](j)}(h``power_limit_0_tmax_us`` (RO)h](j)}(h``power_limit_0_tmax_us``h]hpower_limit_0_tmax_us}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubh (RO)}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjcubj)}(hhh]h)}(hAMaximum powercap sysfs constraint_0_time_window_us for Intel RAPLh]hAMaximum powercap sysfs constraint_0_time_window_us for Intel RAPL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(h```power_limit_1_max_uw`` (RO) Maximum powercap sysfs constraint_1_power_limit_uw for Intel RAPL h](j)}(h``power_limit_1_max_uw`` (RO)h](j)}(h``power_limit_1_max_uw``h]hpower_limit_1_max_uw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hAMaximum powercap sysfs constraint_1_power_limit_uw for Intel RAPLh]hAMaximum powercap sysfs constraint_1_power_limit_uw for Intel RAPL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(hh``power_limit_1_step_uw`` (RO) Power limit increment/decrements for Intel RAPL constraint 1 power limit h](j)}(h``power_limit_1_step_uw`` (RO)h](j)}(h``power_limit_1_step_uw``h]hpower_limit_1_step_uw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hHPower limit increment/decrements for Intel RAPL constraint 1 power limith]hHPower limit increment/decrements for Intel RAPL constraint 1 power limit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(h```power_limit_1_min_uw`` (RO) Minimum powercap sysfs constraint_1_power_limit_uw for Intel RAPL h](j)}(h``power_limit_1_min_uw`` (RO)h](j)}(h``power_limit_1_min_uw``h]hpower_limit_1_min_uw}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hAMinimum powercap sysfs constraint_1_power_limit_uw for Intel RAPLh]hAMinimum powercap sysfs constraint_1_power_limit_uw for Intel RAPL}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(ha``power_limit_1_tmin_us`` (RO) Minimum powercap sysfs constraint_1_time_window_us for Intel RAPL h](j)}(h``power_limit_1_tmin_us`` (RO)h](j)}(h``power_limit_1_tmin_us``h]hpower_limit_1_tmin_us}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubh (RO)}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjWubj)}(hhh]h)}(hAMinimum powercap sysfs constraint_1_time_window_us for Intel RAPLh]hAMinimum powercap sysfs constraint_1_time_window_us for Intel RAPL}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjwubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(ha``power_limit_1_tmax_us`` (RO) Maximum powercap sysfs constraint_1_time_window_us for Intel RAPL h](j)}(h``power_limit_1_tmax_us`` (RO)h](j)}(h``power_limit_1_tmax_us``h]hpower_limit_1_tmax_us}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hAMaximum powercap sysfs constraint_1_time_window_us for Intel RAPLh]hAMaximum powercap sysfs constraint_1_time_window_us for Intel RAPL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(h``power_floor_status`` (RO) When set to 1, the power floor of the system in the current configuration has been reached. It needs to be reconfigured to allow power to be reduced any further. h](j)}(h``power_floor_status`` (RO)h](j)}(h``power_floor_status``h]hpower_floor_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hWhen set to 1, the power floor of the system in the current configuration has been reached. It needs to be reconfigured to allow power to be reduced any further.h]hWhen set to 1, the power floor of the system in the current configuration has been reached. It needs to be reconfigured to allow power to be reduced any further.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubj)}(h``power_floor_enable`` (RW) When set to 1, enable reading and notification of the power floor status. Notifications are triggered for the power_floor_status attribute value changes. h](j)}(h``power_floor_enable`` (RW)h](j)}(h``power_floor_enable``h]hpower_floor_enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hWhen set to 1, enable reading and notification of the power floor status. Notifications are triggered for the power_floor_status attribute value changes.h]hWhen set to 1, enable reading and notification of the power floor status. Notifications are triggered for the power_floor_status attribute value changes.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlhhubeh}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubh)}(h,:file:`/sys/bus/pci/devices/0000\:00\:04.0/`h]j)}(h,:file:`/sys/bus/pci/devices/0000\:00\:04.0/`h]h"/sys/bus/pci/devices/0000:00:04.0/}(hjUhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjQubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubj)}(hhh]j)}(hn``tcc_offset_degree_celsius`` (RW) TCC offset from the critical temperature where hardware will throttle CPU. h](j)}(h"``tcc_offset_degree_celsius`` (RW)h](j)}(h``tcc_offset_degree_celsius``h]htcc_offset_degree_celsius}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubh (RW)}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjoubj)}(hhh]h)}(hJTCC offset from the critical temperature where hardware will throttle CPU.h]hJTCC offset from the critical temperature where hardware will throttle CPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhhhKhjlubah}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubh)}(h<:file:`/sys/bus/pci/devices/0000\:00\:04.0/workload_request`h]j)}(h<:file:`/sys/bus/pci/devices/0000\:00\:04.0/workload_request`h]h2/sys/bus/pci/devices/0000:00:04.0/workload_request}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubj)}(hhh](j)}(h``workload_available_types`` (RO) Available workload types. User space can specify one of the workload type it is currently executing via workload_type. For example: idle, bursty, sustained etc. h](j)}(h!``workload_available_types`` (RO)h](j)}(h``workload_available_types``h]hworkload_available_types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hAvailable workload types. User space can specify one of the workload type it is currently executing via workload_type. For example: idle, bursty, sustained etc.h]hAvailable workload types. User space can specify one of the workload type it is currently executing via workload_type. For example: idle, bursty, sustained etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hk``workload_type`` (RW) User space can specify any one of the available workload type using this interface. h](j)}(h``workload_type`` (RW)h](j)}(h``workload_type``h]h workload_type}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(hSUser space can specify any one of the available workload type using this interface.h]hSUser space can specify any one of the available workload type using this interface.}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj- ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubh)}(h:file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_0_control` :file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_1_control` :file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_2_control`h](j)}(h9:file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_0_control`h]h//sys/bus/pci/devices/0000:00:04.0/ptc_0_control}(hjT hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjP ubh }(hjP hhhNhNubj)}(h9:file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_1_control`h]h//sys/bus/pci/devices/0000:00:04.0/ptc_1_control}(hji hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjP ubh }hjP sbj)}(h9:file:`/sys/bus/pci/devices/0000\:00\:04.0/ptc_2_control`h]h//sys/bus/pci/devices/0000:00:04.0/ptc_2_control}(hj~ hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjP ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubh)}(h3All these controls needs admin privilege to update.h]h3All these controls needs admin privilege to update.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubj)}(hhh](j)}(h``enable`` (RW) 1 for enable, 0 for disable. Shows the current enable status of platform temperature control feature. User space can enable/disable hardware controls. h](j)}(h``enable`` (RW)h](j)}(h ``enable``h]henable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(h1 for enable, 0 for disable. Shows the current enable status of platform temperature control feature. User space can enable/disable hardware controls.h]h1 for enable, 0 for disable. Shows the current enable status of platform temperature control feature. User space can enable/disable hardware controls.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(h``temperature_target`` (RW) Update a new temperature target in milli degree celsius for hardware to use for the temperature control. h](j)}(h``temperature_target`` (RW)h](j)}(h``temperature_target``h]htemperature_target}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(hhUpdate a new temperature target in milli degree celsius for hardware to use for the temperature control.h]hhUpdate a new temperature target in milli degree celsius for hardware to use for the temperature control.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubj)}(hX``thermal_tolerance`` (RW) This attribute ranges from 0 to 7, where 0 represents the most aggressive control to avoid any temperature overshoots, and 7 represents a more graceful approach, favoring performance even at the expense of temperature overshoots. Note: This level may not scale linearly. For example, a value of 3 does not necessarily imply a 50% improvement in performance compared to a value of 0. h](j)}(h``thermal_tolerance`` (RW)h](j)}(h``thermal_tolerance``h]hthermal_tolerance}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ ubh (RW)}(hj$ hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubj)}(hhh]h)}(hX~This attribute ranges from 0 to 7, where 0 represents the most aggressive control to avoid any temperature overshoots, and 7 represents a more graceful approach, favoring performance even at the expense of temperature overshoots. Note: This level may not scale linearly. For example, a value of 3 does not necessarily imply a 50% improvement in performance compared to a value of 0.h]hX~This attribute ranges from 0 to 7, where 0 represents the most aggressive control to avoid any temperature overshoots, and 7 represents a more graceful approach, favoring performance even at the expense of temperature overshoots. Note: This level may not scale linearly. For example, a value of 3 does not necessarily imply a 50% improvement in performance compared to a value of 0.}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubh)}(hGiven that this is platform temperature control, it is expected that a single user-level manager owns and manages the controls. If multiple user-level software applications attempt to write different targets, it can lead to unexpected behavior.h]hGiven that this is platform temperature control, it is expected that a single user-level manager owns and manages the controls. If multiple user-level software applications attempt to write different targets, it can lead to unexpected behavior.}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2hhubeh}(h]+dptf-processor-thermal-pci-driver-interfaceah ]h"]+dptf processor thermal pci driver interfaceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h%DPTF Processor thermal RFIM interfaceh]h%DPTF Processor thermal RFIM interface}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy hhhhhKubh)}(hRFIM interface allows adjustment of FIVR (Fully Integrated Voltage Regulator), DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator) frequencies to avoid RF interference with WiFi and 5G.h]hRFIM interface allows adjustment of FIVR (Fully Integrated Voltage Regulator), DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator) frequencies to avoid RF interference with WiFi and 5G.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy hhubh)}(hX.Switching voltage regulators (VR) generate radiated EMI or RFI at the fundamental frequency and its harmonics. Some harmonics may interfere with very sensitive wireless receivers such as Wi-Fi and cellular that are integrated into host systems like notebook PCs. One of mitigation methods is requesting SOC integrated VR (IVR) switching frequency to a small % and shift away the switching noise harmonic interference from radio channels. OEM or ODMs can use the driver to control SOC IVR operation within the range where it does not impact IVR performance.h]hX.Switching voltage regulators (VR) generate radiated EMI or RFI at the fundamental frequency and its harmonics. Some harmonics may interfere with very sensitive wireless receivers such as Wi-Fi and cellular that are integrated into host systems like notebook PCs. One of mitigation methods is requesting SOC integrated VR (IVR) switching frequency to a small % and shift away the switching noise harmonic interference from radio channels. OEM or ODMs can use the driver to control SOC IVR operation within the range where it does not impact IVR performance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy hhubh)}(hSome products use DLVR instead of FIVR as switching voltage regulator. In this case attributes of DLVR must be adjusted instead of FIVR.h]hSome products use DLVR instead of FIVR as switching voltage regulator. In this case attributes of DLVR must be adjusted instead of FIVR.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy hhubh)}(hXKWhile shifting the frequencies additional clock noise can be introduced, which is compensated by adjusting Spread spectrum percent. This helps to reduce the clock noise to meet regulatory compliance. This spreading % increases bandwidth of signal transmission and hence reduces the effects of interference, noise and signal fading.h]hXKWhile shifting the frequencies additional clock noise can be introduced, which is compensated by adjusting Spread spectrum percent. This helps to reduce the clock noise to meet regulatory compliance. This spreading % increases bandwidth of signal transmission and hence reduces the effects of interference, noise and signal fading.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy hhubh)}(hXDRAM devices of DDR IO interface and their power plane can generate EMI at the data rates. Similar to IVR control mechanism, Intel offers a mechanism by which DDR data rates can be changed if several conditions are met: there is strong RFI interference because of DDR; CPU power management has no other restriction in changing DDR data rates; PC ODMs enable this feature (real time DDR RFI Mitigation referred to as DDR-RFIM) for Wi-Fi from BIOS.h]hXDRAM devices of DDR IO interface and their power plane can generate EMI at the data rates. Similar to IVR control mechanism, Intel offers a mechanism by which DDR data rates can be changed if several conditions are met: there is strong RFI interference because of DDR; CPU power management has no other restriction in changing DDR data rates; PC ODMs enable this feature (real time DDR RFI Mitigation referred to as DDR-RFIM) for Wi-Fi from BIOS.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy hhubh)}(hFIVR attributesh]hFIVR attributes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjy hhubh)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/fivr/`h]j)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/fivr/`h]h'/sys/bus/pci/devices/0000:00:04.0/fivr/}(hj hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhjy hhubj)}(hhh](j)}(h``vco_ref_code_lo`` (RW) The VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 3-bit LSB field. h](j)}(h``vco_ref_code_lo`` (RW)h](j)}(h``vco_ref_code_lo``h]hvco_ref_code_lo}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(hqThe VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 3-bit LSB field.h]hqThe VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 3-bit LSB field.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(h``vco_ref_code_hi`` (RW) The VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 8-bit MSB field. h](j)}(h``vco_ref_code_hi`` (RW)h](j)}(h``vco_ref_code_hi``h]hvco_ref_code_hi}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj= ubh (RW)}(hj= hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM hj9 ubj)}(hhh]h)}(hqThe VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 8-bit MSB field.h]hqThe VCO reference code is an 11-bit field and controls the FIVR switching frequency. This is the 8-bit MSB field.}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjY ubah}(h]h ]h"]h$]h&]uh1jhj9 ubeh}(h]h ]h"]h$]h&]uh1jhhhM hj hhubj)}(hN``spread_spectrum_pct`` (RW) Set the FIVR spread spectrum clocking percentage h](j)}(h``spread_spectrum_pct`` (RW)h](j)}(h``spread_spectrum_pct``h]hspread_spectrum_pct}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz ubh (RW)}(hjz hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjv ubj)}(hhh]h)}(h0Set the FIVR spread spectrum clocking percentageh]h0Set the FIVR spread spectrum clocking percentage}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjv ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(h```spread_spectrum_clk_enable`` (RW) Enable/disable of the FIVR spread spectrum clocking feature h](j)}(h#``spread_spectrum_clk_enable`` (RW)h](j)}(h``spread_spectrum_clk_enable``h]hspread_spectrum_clk_enable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(h;Enable/disable of the FIVR spread spectrum clocking featureh]h;Enable/disable of the FIVR spread spectrum clocking feature}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hx``rfi_vco_ref_code`` (RW) This field is a read only status register which reflects the current FIVR switching frequency h](j)}(h``rfi_vco_ref_code`` (RW)h](j)}(h``rfi_vco_ref_code``h]hrfi_vco_ref_code}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(h]This field is a read only status register which reflects the current FIVR switching frequencyh]h]This field is a read only status register which reflects the current FIVR switching frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hJ``fivr_fffc_rev`` (RW) This field indicated the revision of the FIVR HW. h](j)}(h``fivr_fffc_rev`` (RW)h](j)}(h``fivr_fffc_rev``h]h fivr_fffc_rev}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1 ubh (RW)}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj- ubj)}(hhh]h)}(h1This field indicated the revision of the FIVR HW.h]h1This field indicated the revision of the FIVR HW.}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjM ubah}(h]h ]h"]h$]h&]uh1jhj- ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj hhubeh}(h]h ]h"]h$]h&]uh1jhjy hhhhhNubh)}(hDVFS attributesh]hDVFS attributes}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjy hhubh)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/dvfs/`h]j)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/dvfs/`h]h'/sys/bus/pci/devices/0000:00:04.0/dvfs/}(hj hhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhj~ ubah}(h]h ]h"]h$]h&]uh1hhhhMhjy hhubj)}(hhh](j)}(h``rfi_restriction_run_busy`` (RW) Request the restriction of specific DDR data rate and set this value 1. Self reset to 0 after operation. h](j)}(h!``rfi_restriction_run_busy`` (RW)h](j)}(h``rfi_restriction_run_busy``h]hrfi_restriction_run_busy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM"hj ubj)}(hhh]h)}(hhRequest the restriction of specific DDR data rate and set this value 1. Self reset to 0 after operation.h]hhRequest the restriction of specific DDR data rate and set this value 1. Self reset to 0 after operation.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM"hj ubj)}(h``rfi_restriction_err_code`` (RW) 0 :Request is accepted, 1:Feature disabled, 2: the request restricts more points than it is allowed h](j)}(h!``rfi_restriction_err_code`` (RW)h](j)}(h``rfi_restriction_err_code``h]hrfi_restriction_err_code}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM&hj ubj)}(hhh]h)}(hc0 :Request is accepted, 1:Feature disabled, 2: the request restricts more points than it is allowedh]hc0 :Request is accepted, 1:Feature disabled, 2: the request restricts more points than it is allowed}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM&hj hhubj)}(hb``rfi_restriction_data_rate_Delta`` (RW) Restricted DDR data rate for RFI protection: Lower Limit h](j)}(h(``rfi_restriction_data_rate_Delta`` (RW)h](j)}(h#``rfi_restriction_data_rate_Delta``h]hrfi_restriction_data_rate_Delta}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RW)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM)hj ubj)}(hhh]h)}(h8Restricted DDR data rate for RFI protection: Lower Limith]h8Restricted DDR data rate for RFI protection: Lower Limit}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj6 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM)hj hhubj)}(ha``rfi_restriction_data_rate_Base`` (RW) Restricted DDR data rate for RFI protection: Upper Limit h](j)}(h'``rfi_restriction_data_rate_Base`` (RW)h](j)}(h"``rfi_restriction_data_rate_Base``h]hrfi_restriction_data_rate_Base}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjW ubh (RW)}(hjW hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM,hjS ubj)}(hhh]h)}(h8Restricted DDR data rate for RFI protection: Upper Limith]h8Restricted DDR data rate for RFI protection: Upper Limit}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjs ubah}(h]h ]h"]h$]h&]uh1jhjS ubeh}(h]h ]h"]h$]h&]uh1jhhhM,hj hhubj)}(hA``ddr_data_rate_point_0`` (RO) DDR data rate selection 1st point h](j)}(h``ddr_data_rate_point_0`` (RO)h](j)}(h``ddr_data_rate_point_0``h]hddr_data_rate_point_0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RO)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM/hj ubj)}(hhh]h)}(h!DDR data rate selection 1st pointh]h!DDR data rate selection 1st point}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM/hj hhubj)}(hA``ddr_data_rate_point_1`` (RO) DDR data rate selection 2nd point h](j)}(h``ddr_data_rate_point_1`` (RO)h](j)}(h``ddr_data_rate_point_1``h]hddr_data_rate_point_1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (RO)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM2hj ubj)}(hhh]h)}(h!DDR data rate selection 2nd pointh]h!DDR data rate selection 2nd point}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM2hj hhubj)}(hA``ddr_data_rate_point_2`` (RO) DDR data rate selection 3rd point h](j)}(h``ddr_data_rate_point_2`` (RO)h](j)}(h``ddr_data_rate_point_2``h]hddr_data_rate_point_2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM5hj ubj)}(hhh]h)}(h!DDR data rate selection 3rd pointh]h!DDR data rate selection 3rd point}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj*ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhM5hj hhubj)}(hA``ddr_data_rate_point_3`` (RO) DDR data rate selection 4th point h](j)}(h``ddr_data_rate_point_3`` (RO)h](j)}(h``ddr_data_rate_point_3``h]hddr_data_rate_point_3}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubh (RO)}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM8hjGubj)}(hhh]h)}(h!DDR data rate selection 4th pointh]h!DDR data rate selection 4th point}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjgubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhhhM8hj hhubj)}(h5``rfi_disable (RW)`` Disable DDR rate change feature h](j)}(h``rfi_disable (RW)``h]j)}(hjh]hrfi_disable (RW)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhM;hjubj)}(hhh]h)}(hDisable DDR rate change featureh]hDisable DDR rate change feature}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM;hj hhubeh}(h]h ]h"]h$]h&]uh1jhjy hhhhhNubh)}(hDLVR attributesh]hDLVR attributes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjy hhubh)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/dlvr/`h]j)}(h1:file:`/sys/bus/pci/devices/0000\:00\:04.0/dlvr/`h]h'/sys/bus/pci/devices/0000:00:04.0/dlvr/}(hjhhhNhNubah}(h]h ]fileah"]h$]h&]rolefileuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM?hjy hhubj)}(hhh](j)}(h3``dlvr_hardware_rev`` (RO) DLVR hardware revision. h](j)}(h``dlvr_hardware_rev`` (RO)h](j)}(h``dlvr_hardware_rev``h]hdlvr_hardware_rev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMBhjubj)}(hhh]h)}(hDLVR hardware revision.h]hDLVR hardware revision.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMBhjubj)}(h:``dlvr_freq_mhz`` (RO) Current DLVR PLL frequency in MHz. h](j)}(h``dlvr_freq_mhz`` (RO)h](j)}(h``dlvr_freq_mhz``h]h dlvr_freq_mhz}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubh (RO)}(hj/hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMEhj+ubj)}(hhh]h)}(h"Current DLVR PLL frequency in MHz.h]h"Current DLVR PLL frequency in MHz.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjKubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhhhMEhjhhubj)}(h``dlvr_freq_select`` (RW) Sets DLVR PLL clock frequency. Once set, and enabled via dlvr_rfim_enable, the dlvr_freq_mhz will show the current DLVR PLL frequency. h](j)}(h``dlvr_freq_select`` (RW)h](j)}(h``dlvr_freq_select``h]hdlvr_freq_select}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubh (RW)}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMJhjhubj)}(hhh]h)}(hSets DLVR PLL clock frequency. Once set, and enabled via dlvr_rfim_enable, the dlvr_freq_mhz will show the current DLVR PLL frequency.h]hSets DLVR PLL clock frequency. Once set, and enabled via dlvr_rfim_enable, the dlvr_freq_mhz will show the current DLVR PLL frequency.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhhhMJhjhhubj)}(hC``dlvr_pll_busy`` (RO) PLL can't accept frequency change when set. h](j)}(h``dlvr_pll_busy`` (RO)h](j)}(h``dlvr_pll_busy``h]h dlvr_pll_busy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RO)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMMhjubj)}(hhh]h)}(h+PLL can't accept frequency change when set.h]h-PLL can’t accept frequency change when set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMMhjhhubj)}(h[``dlvr_rfim_enable`` (RW) 0: Disable RF frequency hopping, 1: Enable RF frequency hopping. h](j)}(h``dlvr_rfim_enable`` (RW)h](j)}(h``dlvr_rfim_enable``h]hdlvr_rfim_enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMPhjubj)}(hhh]h)}(h@0: Disable RF frequency hopping, 1: Enable RF frequency hopping.h]h@0: Disable RF frequency hopping, 1: Enable RF frequency hopping.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMPhjhhubj)}(hK``dlvr_spread_spectrum_pct`` (RW) Sets DLVR spread spectrum percent value. h](j)}(h!``dlvr_spread_spectrum_pct`` (RW)h](j)}(h``dlvr_spread_spectrum_pct``h]hdlvr_spread_spectrum_pct}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubh (RW)}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMShjubj)}(hhh]h)}(h(Sets DLVR spread spectrum percent value.h]h(Sets DLVR spread spectrum percent value.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj?ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMShjhhubj)}(h``dlvr_control_mode`` (RW) Specifies how frequencies are spread using spread spectrum. 0: Down spread, 1: Spread in the Center. h](j)}(h``dlvr_control_mode`` (RW)h](j)}(h``dlvr_control_mode``h]hdlvr_control_mode}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh (RW)}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMXhj\ubj)}(hhh]h)}(hdSpecifies how frequencies are spread using spread spectrum. 0: Down spread, 1: Spread in the Center.h]hdSpecifies how frequencies are spread using spread spectrum. 0: Down spread, 1: Spread in the Center.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj|ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhhhMXhjhhubj)}(h9``dlvr_control_lock`` (RW) 1: future writes are ignored. h](j)}(h``dlvr_control_lock`` (RW)h](j)}(h``dlvr_control_lock``h]hdlvr_control_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM[hjubj)}(hhh]h)}(h1: future writes are ignored.h]h1: future writes are ignored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM[hjhhubeh}(h]h ]h"]h$]h&]uh1jhjy hhhhhNubeh}(h]%dptf-processor-thermal-rfim-interfaceah ]h"]%dptf processor thermal rfim interfaceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h'DPTF Power supply and Battery Interfaceh]h'DPTF Power supply and Battery Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM^ubh)}(h6Refer to Documentation/ABI/testing/sysfs-platform-dptfh]h6Refer to Documentation/ABI/testing/sysfs-platform-dptf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjhhubeh}(h]'dptf-power-supply-and-battery-interfaceah ]h"]'dptf power supply and battery interfaceah$]h&]uh1hhhhhhhhM^ubh)}(hhh](h)}(hDPTF Fan Controlh]hDPTF Fan Control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMcubh)}(hBRefer to Documentation/admin-guide/acpi/fan_performance_states.rsth]hBRefer to Documentation/admin-guide/acpi/fan_performance_states.rst}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj hhubeh}(h]dptf-fan-controlah ]h"]dptf fan controlah$]h&]uh1hhhhhhhhMcubh)}(hhh](h)}(hWorkload Type Hintsh]hWorkload Type Hints}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhMhubh)}(hXThe firmware in Meteor Lake processor generation is capable of identifying workload type and passing hints regarding it to the OS. A special sysfs interface is provided to allow user space to obtain workload type hints from the firmware and control the rate at which they are provided.h]hXThe firmware in Meteor Lake processor generation is capable of identifying workload type and passing hints regarding it to the OS. A special sysfs interface is provided to allow user space to obtain workload type hints from the firmware and control the rate at which they are provided.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj2hhubh)}(hUser space can poll attribute "workload_type_index" for the current hint or can receive a notification whenever the value of this attribute is updated.h]hUser space can poll attribute “workload_type_index” for the current hint or can receive a notification whenever the value of this attribute is updated.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj2hhubh)}(hfile:`/sys/bus/pci/devices/0000:00:04.0/workload_hint/` Segment 0, bus 0, device 4, function 0 is reserved for the processor thermal device on all Intel client processors. So, the above path doesn't change based on the processor generation.h](hfile:}(hj_hhhNhNubhtitle_reference)}(h2`/sys/bus/pci/devices/0000:00:04.0/workload_hint/`h]h0/sys/bus/pci/devices/0000:00:04.0/workload_hint/}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jghj_ubh Segment 0, bus 0, device 4, function 0 is reserved for the processor thermal device on all Intel client processors. So, the above path doesn’t change based on the processor generation.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMrhj2hhubj)}(hhh](j)}(hY``workload_hint_enable`` (RW) Enable firmware to send workload type hints to user space. h](j)}(h``workload_hint_enable`` (RW)h](j)}(h``workload_hint_enable``h]hworkload_hint_enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMxhjubj)}(hhh]h)}(h:Enable firmware to send workload type hints to user space.h]h:Enable firmware to send workload type hints to user space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMxhjubj)}(hc``workload_slow_hint_enable`` (RW) Enable firmware to send slow workload type hints to user space. h](j)}(h"``workload_slow_hint_enable`` (RW)h](j)}(h``workload_slow_hint_enable``h]hworkload_slow_hint_enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhM{hjubj)}(hhh]h)}(h?Enable firmware to send slow workload type hints to user space.h]h?Enable firmware to send slow workload type hints to user space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM{hjhhubj)}(hX``notification_delay_ms`` (RW) Minimum delay in milliseconds before firmware will notify OS. This is for the rate control of notifications. This delay is between changing the workload type prediction in the firmware and notifying the OS about the change. The default delay is 1024 ms. The delay of 0 is invalid. The delay is rounded up to the nearest power of 2 to simplify firmware programming of the delay value. The read of notification_delay_ms attribute shows the effective value used. 3h](j)}(h``notification_delay_ms`` (RW)h](j)}(h``notification_delay_ms``h]hnotification_delay_ms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (RW)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(hXMinimum delay in milliseconds before firmware will notify OS. This is for the rate control of notifications. This delay is between changing the workload type prediction in the firmware and notifying the OS about the change. The default delay is 1024 ms. The delay of 0 is invalid. The delay is rounded up to the nearest power of 2 to simplify firmware programming of the delay value. The read of notification_delay_ms attribute shows the effective value used.h]hXMinimum delay in milliseconds before firmware will notify OS. This is for the rate control of notifications. This delay is between changing the workload type prediction in the firmware and notifying the OS about the change. The default delay is 1024 ms. The delay of 0 is invalid. The delay is rounded up to the nearest power of 2 to simplify firmware programming of the delay value. The read of notification_delay_ms attribute shows the effective value used.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hX``workload_type_index`` (RO) Predicted workload type index. User space can get notification of change via existing sysfs attribute change notification mechanism. The supported index values and their meaning for the Meteor Lake processor generation are as follows: 0 - Idle: System performs no tasks, power and idle residency are consistently low for long periods of time. 1 – Battery Life: Power is relatively low, but the processor may still be actively performing a task, such as video playback for a long period of time. 2 – Sustained: Power level that is relatively high for a long period of time, with very few to no periods of idleness, which will eventually exhaust RAPL Power Limit 1 and 2. 3 – Bursty: Consumes a relatively constant average amount of power, but periods of relative idleness are interrupted by bursts of activity. The bursts are relatively short and the periods of relative idleness between them typically prevent RAPL Power Limit 1 from being exhausted. 4 – Unknown: Can't classify. On processors starting from Panther Lake additional hints are provided. The hardware analyzes workload residencies over an extended period to determine whether the workload classification tends toward idle/battery life states or sustained/performance states. Based on this long-term analysis, it classifies: Power Classification: If the workload exhibits more idle or battery life residencies, it is classified as "power". Performance Classification: If the workload exhibits more sustained or performance residencies, it is classified as "performance". This approach enables applications to ignore short-term workload fluctuations and instead respond to longer-term power vs. performance trends. Residency thresholds for this classification are CPU generation-specific. Classification is reported via bit 4 of the workload_type_index: Bit 4 = 1: Power classification Bit 4 = 0: Performance classificationh](j)}(h``workload_type_index`` (RO)h](j)}(h``workload_type_index``h]hworkload_type_index}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh (RO)}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj;ubj)}(hhh](h)}(hPredicted workload type index. User space can get notification of change via existing sysfs attribute change notification mechanism.h]hPredicted workload type index. User space can get notification of change via existing sysfs attribute change notification mechanism.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(heThe supported index values and their meaning for the Meteor Lake processor generation are as follows:h]heThe supported index values and their meaning for the Meteor Lake processor generation are as follows:}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubj)}(hhh](j)}(hm0 - Idle: System performs no tasks, power and idle residency are consistently low for long periods of time. h](j)}(hA0 - Idle: System performs no tasks, power and idle residency areh]hA0 - Idle: System performs no tasks, power and idle residency are}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj}ubj)}(hhh]h)}(h*consistently low for long periods of time.h]h*consistently low for long periods of time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjzubj)}(h1 – Battery Life: Power is relatively low, but the processor may still be actively performing a task, such as video playback for a long period of time. h](j)}(hB1 – Battery Life: Power is relatively low, but the processor mayh]hB1 – Battery Life: Power is relatively low, but the processor may}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(hVstill be actively performing a task, such as video playback for a long period of time.h]hVstill be actively performing a task, such as video playback for a long period of time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjzubj)}(h2 – Sustained: Power level that is relatively high for a long period of time, with very few to no periods of idleness, which will eventually exhaust RAPL Power Limit 1 and 2. h](j)}(hF2 – Sustained: Power level that is relatively high for a long periodh]hF2 – Sustained: Power level that is relatively high for a long period}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(hiof time, with very few to no periods of idleness, which will eventually exhaust RAPL Power Limit 1 and 2.h]hiof time, with very few to no periods of idleness, which will eventually exhaust RAPL Power Limit 1 and 2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjzubj)}(hX3 – Bursty: Consumes a relatively constant average amount of power, but periods of relative idleness are interrupted by bursts of activity. The bursts are relatively short and the periods of relative idleness between them typically prevent RAPL Power Limit 1 from being exhausted. h](j)}(hI3 – Bursty: Consumes a relatively constant average amount of power, buth]hI3 – Bursty: Consumes a relatively constant average amount of power, but}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(hperiods of relative idleness are interrupted by bursts of activity. The bursts are relatively short and the periods of relative idleness between them typically prevent RAPL Power Limit 1 from being exhausted.h]hperiods of relative idleness are interrupted by bursts of activity. The bursts are relatively short and the periods of relative idleness between them typically prevent RAPL Power Limit 1 from being exhausted.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjzubeh}(h]h ]h"]h$]h&]uh1jhj[ubh)}(h4 – Unknown: Can't classify.h]h 4 – Unknown: Can’t classify.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hX3On processors starting from Panther Lake additional hints are provided. The hardware analyzes workload residencies over an extended period to determine whether the workload classification tends toward idle/battery life states or sustained/performance states. Based on this long-term analysis, it classifies:h]hX3On processors starting from Panther Lake additional hints are provided. The hardware analyzes workload residencies over an extended period to determine whether the workload classification tends toward idle/battery life states or sustained/performance states. Based on this long-term analysis, it classifies:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hrPower Classification: If the workload exhibits more idle or battery life residencies, it is classified as "power".h]hvPower Classification: If the workload exhibits more idle or battery life residencies, it is classified as “power”.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hPerformance Classification: If the workload exhibits more sustained or performance residencies, it is classified as "performance".h]hPerformance Classification: If the workload exhibits more sustained or performance residencies, it is classified as “performance”.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hThis approach enables applications to ignore short-term workload fluctuations and instead respond to longer-term power vs. performance trends.h]hThis approach enables applications to ignore short-term workload fluctuations and instead respond to longer-term power vs. performance trends.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hResidency thresholds for this classification are CPU generation-specific. Classification is reported via bit 4 of the workload_type_index:h]hResidency thresholds for this classification are CPU generation-specific. Classification is reported via bit 4 of the workload_type_index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hBit 4 = 1: Power classificationh]hBit 4 = 1: Power classification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(h%Bit 4 = 0: Performance classificationh]h%Bit 4 = 0: Performance classification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubeh}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jhj2hhhhhNubeh}(h]workload-type-hintsah ]h"]workload type hintsah$]h&]uh1hhhhhhhhMhubeh}(h]>intel-r-dynamic-platform-and-thermal-framework-sysfs-interfaceah ]h"]?intel(r) dynamic platform and thermal framework sysfs interfaceah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjjjj2j/jjjjj/j,jv js jjjjj/j,jju nametypes}(jjj2jjj/jv jjj/juh}(jhjjdj/jjj5jjj,j js j2jjy jjj,j jj2u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.