€•      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ//translations/zh_CN/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/zh_TW/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/it_IT/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/ja_JP/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/ko_KR/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ//translations/sp_SP/driver-api/soundwire/stream”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒAudio Stream in SoundWire”h]”hŒAudio Stream in SoundWire”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒI/var/lib/git/docbuild/linux/Documentation/driver-api/soundwire/stream.rst”h KubhŒ	paragraph”“”)”}”(hŒBAn audio stream is a logical or virtual connection created between”h]”hŒBAn audio stream is a logical or virtual connection created between”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒblock_quote”“”)”}”(hŒ…(1) System memory buffer(s) and Codec(s)

(2) DSP memory buffer(s) and Codec(s)

(3) FIFO(s) and Codec(s)

(4) Codec(s) and Codec(s)
”h]”hŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ%System memory buffer(s) and Codec(s)
”h]”h¸)”}”(hŒ$System memory buffer(s) and Codec(s)”h]”hŒ$System memory buffer(s) and Codec(s)”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÔubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhhÏubhÓ)”}”(hŒ"DSP memory buffer(s) and Codec(s)
”h]”h¸)”}”(hŒ!DSP memory buffer(s) and Codec(s)”h]”hŒ!DSP memory buffer(s) and Codec(s)”…””}”(hhðhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K	hhìubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhhÏubhÓ)”}”(hŒFIFO(s) and Codec(s)
”h]”h¸)”}”(hŒFIFO(s) and Codec(s)”h]”hŒFIFO(s) and Codec(s)”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhhÏubhÓ)”}”(hŒCodec(s) and Codec(s)
”h]”h¸)”}”(hŒCodec(s) and Codec(s)”h]”hŒCodec(s) and Codec(s)”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhhÏubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”Œ(”Œsuffix”Œ)”uh1hÍhhÉubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h Khh£hžhubh¸)”}”(hŒÇwhich is typically driven by a DMA(s) channel through the data link. An
audio stream contains one or more channels of data. All channels within
stream must have same sample rate and same sample size.”h]”hŒÇwhich is typically driven by a DMA(s) channel through the data link. An
audio stream contains one or more channels of data. All channels within
stream must have same sample rate and same sample size.”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒ“Assume a stream with two channels (Left & Right) is opened using SoundWire
interface. Below are some ways a stream can be represented in SoundWire.”h]”hŒ“Assume a stream with two channels (Left & Right) is opened using SoundWire
interface. Below are some ways a stream can be represented in SoundWire.”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒ?Stream Sample in memory (System memory, DSP memory or FIFOs) ::”h]”hŒ<Stream Sample in memory (System memory, DSP memory or FIFOs)”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒliteral_block”“”)”}”(hŒM-------------------------
| L | R | L | R | L | R |
-------------------------”h]”hŒM-------------------------
| L | R | L | R | L | R |
-------------------------”…””}”hjr  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jp  hŸh¶h Khh£hžhubh¸)”}”(hŒExample 1: Stereo Stream with L and R channels is rendered from Master to
Slave. Both Master and Slave is using single port. ::”h]”hŒ|Example 1: Stereo Stream with L and R channels is rendered from Master to
Slave. Both Master and Slave is using single port.”…””}”(hj‚  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubjq  )”}”(hX'  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|               |                                  |       1       |
|               |                     Data Signal  |               |
|    L  +  R    +----------------------------------+    L  +  R    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”h]”hX'  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|               |                                  |       1       |
|               |                     Data Signal  |               |
|    L  +  R    +----------------------------------+    L  +  R    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h Khh£hžhubh¸)”}”(hŒExample 2: Stereo Stream with L and R channels is captured from Slave to
Master. Both Master and Slave is using single port. ::”h]”hŒ|Example 2: Stereo Stream with L and R channels is captured from Slave to
Master. Both Master and Slave is using single port.”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K)hh£hžhubjq  )”}”(hX'  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|               |                                  |       1       |
|               |                     Data Signal  |               |
|    L  +  R    +----------------------------------+    L  +  R    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  <-----------------------+       +---------------+”h]”hX'  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|               |                                  |       1       |
|               |                     Data Signal  |               |
|    L  +  R    +----------------------------------+    L  +  R    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  <-----------------------+       +---------------+”…””}”hj¬  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h K-hh£hžhubh¸)”}”(hŒ·Example 3: Stereo Stream with L and R channels is rendered by Master. Each
of the L and R channel is received by two different Slaves. Master and both
Slaves are using single port. ::”h]”hŒ´Example 3: Stereo Stream with L and R channels is rendered by Master. Each
of the L and R channel is received by two different Slaves. Master and both
Slaves are using single port.”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K7hh£hžhubjq  )”}”(hX‡  +---------------+                    Clock Signal  +---------------+
|    Master     +---------+------------------------+     Slave     |
|   Interface   |         |                        |   Interface   |
|               |         |                        |       1       |
|               |         |           Data Signal  |               |
|    L  +  R    +---+------------------------------+       L       |
|     (Data)    |   |     |    Data Direction      |     (Data)    |
+---------------+   |     |   +------------->      +---------------+
                    |     |
                    |     |
                    |     |                        +---------------+
                    |     +----------------------> |     Slave     |
                    |                              |   Interface   |
                    |                              |       2       |
                    |                              |               |
                    +----------------------------> |       R       |
                                                   |     (Data)    |
                                                   +---------------+”h]”hX‡  +---------------+                    Clock Signal  +---------------+
|    Master     +---------+------------------------+     Slave     |
|   Interface   |         |                        |   Interface   |
|               |         |                        |       1       |
|               |         |           Data Signal  |               |
|    L  +  R    +---+------------------------------+       L       |
|     (Data)    |   |     |    Data Direction      |     (Data)    |
+---------------+   |     |   +------------->      +---------------+
                    |     |
                    |     |
                    |     |                        +---------------+
                    |     +----------------------> |     Slave     |
                    |                              |   Interface   |
                    |                              |       2       |
                    |                              |               |
                    +----------------------------> |       R       |
                                                   |     (Data)    |
                                                   +---------------+”…””}”hjÈ  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h K;hh£hžhubh¸)”}”(hX^  Example 4: Stereo Stream with L and R channels is rendered by
Master. Both of the L and R channels are received by two different
Slaves. Master and both Slaves are using single port handling
L+R. Each Slave device processes the L + R data locally, typically
based on static configuration or dynamic orientation, and may drive
one or more speakers. ::”h]”hX[  Example 4: Stereo Stream with L and R channels is rendered by
Master. Both of the L and R channels are received by two different
Slaves. Master and both Slaves are using single port handling
L+R. Each Slave device processes the L + R data locally, typically
based on static configuration or dynamic orientation, and may drive
one or more speakers.”…””}”(hjÖ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KNhh£hžhubjq  )”}”(hX‡  +---------------+                    Clock Signal  +---------------+
|    Master     +---------+------------------------+     Slave     |
|   Interface   |         |                        |   Interface   |
|               |         |                        |       1       |
|               |         |           Data Signal  |               |
|    L  +  R    +---+------------------------------+     L + R     |
|     (Data)    |   |     |    Data Direction      |     (Data)    |
+---------------+   |     |   +------------->      +---------------+
                    |     |
                    |     |
                    |     |                        +---------------+
                    |     +----------------------> |     Slave     |
                    |                              |   Interface   |
                    |                              |       2       |
                    |                              |               |
                    +----------------------------> |     L + R     |
                                                   |     (Data)    |
                                                   +---------------+”h]”hX‡  +---------------+                    Clock Signal  +---------------+
|    Master     +---------+------------------------+     Slave     |
|   Interface   |         |                        |   Interface   |
|               |         |                        |       1       |
|               |         |           Data Signal  |               |
|    L  +  R    +---+------------------------------+     L + R     |
|     (Data)    |   |     |    Data Direction      |     (Data)    |
+---------------+   |     |   +------------->      +---------------+
                    |     |
                    |     |
                    |     |                        +---------------+
                    |     +----------------------> |     Slave     |
                    |                              |   Interface   |
                    |                              |       2       |
                    |                              |               |
                    +----------------------------> |     L + R     |
                                                   |     (Data)    |
                                                   +---------------+”…””}”hjä  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h KUhh£hžhubh¸)”}”(hŒExample 5: Stereo Stream with L and R channel is rendered by two different
Ports of the Master and is received by only single Port of the Slave
interface. ::”h]”hŒšExample 5: Stereo Stream with L and R channel is rendered by two different
Ports of the Master and is received by only single Port of the Slave
interface.”…””}”(hjò  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhh£hžhubjq  )”}”(hX  +--------------------+
|                    |
|     +--------------+                             +----------------+
|     |             ||                             |                |
|     |  Data Port  ||  L Channel                  |                |
|     |      1      |------------+                 |                |
|     |  L Channel  ||           |                 +-----+----+     |
|     |   (Data)    ||           |   L + R Channel ||    Data |     |
| Master  +----------+           | +---+---------> ||    Port |     |
| Interface          |           |                 ||     1   |     |
|     +--------------+           |                 ||         |     |
|     |             ||           |                 +----------+     |
|     |  Data Port  |------------+                 |                |
|     |      2      ||  R Channel                  |     Slave      |
|     |  R Channel  ||                             |   Interface    |
|     |   (Data)    ||                             |       1        |
|     +--------------+         Clock Signal        |     L  +  R    |
|                    +---------------------------> |      (Data)    |
+--------------------+                             |                |
                                                   +----------------+”h]”hX  +--------------------+
|                    |
|     +--------------+                             +----------------+
|     |             ||                             |                |
|     |  Data Port  ||  L Channel                  |                |
|     |      1      |------------+                 |                |
|     |  L Channel  ||           |                 +-----+----+     |
|     |   (Data)    ||           |   L + R Channel ||    Data |     |
| Master  +----------+           | +---+---------> ||    Port |     |
| Interface          |           |                 ||     1   |     |
|     +--------------+           |                 ||         |     |
|     |             ||           |                 +----------+     |
|     |  Data Port  |------------+                 |                |
|     |      2      ||  R Channel                  |     Slave      |
|     |  R Channel  ||                             |   Interface    |
|     |   (Data)    ||                             |       1        |
|     +--------------+         Clock Signal        |     L  +  R    |
|                    +---------------------------> |      (Data)    |
+--------------------+                             |                |
                                                   +----------------+”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h Klhh£hžhubh¸)”}”(hŒßExample 6: Stereo Stream with L and R channel is rendered by 2 Masters, each
rendering one channel, and is received by two different Slaves, each
receiving one channel. Both Masters and both Slaves are using single port. ::”h]”hŒÜExample 6: Stereo Stream with L and R channel is rendered by 2 Masters, each
rendering one channel, and is received by two different Slaves, each
receiving one channel. Both Masters and both Slaves are using single port.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubjq  )”}”(hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|       L       +----------------------------------+       L       |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|       R       +----------------------------------+       R       |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”h]”hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|       L       +----------------------------------+       L       |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|       R       +----------------------------------+       R       |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h K…hh£hžhubh¸)”}”(hŒ×Example 7: Stereo Stream with L and R channel is rendered by 2
Masters, each rendering both channels. Each Slave receives L + R. This
is the same application as Example 4 but with Slaves placed on
separate links. ::”h]”hŒÔExample 7: Stereo Stream with L and R channel is rendered by 2
Masters, each rendering both channels. Each Slave receives L + R. This
is the same application as Example 4 but with Slaves placed on
separate links.”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K—hh£hžhubjq  )”}”(hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|     L + R     +----------------------------------+     L + R     |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|     L + R     +----------------------------------+     L + R     |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”h]”hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|     L + R     +----------------------------------+     L + R     |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|     L + R     +----------------------------------+     L + R     |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”…””}”hj8  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h Kœhh£hžhubh¸)”}”(hŒuExample 8: 4-channel Stream is rendered by 2 Masters, each rendering a
2 channels. Each Slave receives 2 channels. ::”h]”hŒrExample 8: 4-channel Stream is rendered by 2 Masters, each rendering a
2 channels. Each Slave receives 2 channels.”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K®hh£hžhubjq  )”}”(hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|    L1 + R1    +----------------------------------+    L1 + R1    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|     L2 + R2   +----------------------------------+    L2 + R2    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”h]”hXP  +---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       1       |                                  |       1       |
|               |                     Data Signal  |               |
|    L1 + R1    +----------------------------------+    L1 + R1    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+

+---------------+                    Clock Signal  +---------------+
|    Master     +----------------------------------+     Slave     |
|   Interface   |                                  |   Interface   |
|       2       |                                  |       2       |
|               |                     Data Signal  |               |
|     L2 + R2   +----------------------------------+    L2 + R2    |
|     (Data)    |     Data Direction               |     (Data)    |
+---------------+  +----------------------->       +---------------+”…””}”hjT  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h K±hh£hžhubh¸)”}”(hX,  Note1: In multi-link cases like above, to lock, one would acquire a global
lock and then go on locking bus instances. But, in this case the caller
framework(ASoC DPCM) guarantees that stream operations on a card are
always serialized. So, there is no race condition and hence no need for
global lock.”h]”hX,  Note1: In multi-link cases like above, to lock, one would acquire a global
lock and then go on locking bus instances. But, in this case the caller
framework(ASoC DPCM) guarantees that stream operations on a card are
always serialized. So, there is no race condition and hence no need for
global lock.”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÃhh£hžhubh¸)”}”(hX  Note2: A Slave device may be configured to receive all channels
transmitted on a link for a given Stream (Example 4) or just a subset
of the data (Example 3). The configuration of the Slave device is not
handled by a SoundWire subsystem API, but instead by the
snd_soc_dai_set_tdm_slot() API. The platform or machine driver will
typically configure which of the slots are used. For Example 4, the
same slots would be used by all Devices, while for Example 3 the Slave
Device1 would use e.g. Slot 0 and Slave device2 slot 1.”h]”hX  Note2: A Slave device may be configured to receive all channels
transmitted on a link for a given Stream (Example 4) or just a subset
of the data (Example 3). The configuration of the Slave device is not
handled by a SoundWire subsystem API, but instead by the
snd_soc_dai_set_tdm_slot() API. The platform or machine driver will
typically configure which of the slots are used. For Example 4, the
same slots would be used by all Devices, while for Example 3 the Slave
Device1 would use e.g. Slot 0 and Slave device2 slot 1.”…””}”(hjp  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÉhh£hžhubh¸)”}”(hŒúNote3: Multiple Sink ports can extract the same information for the
same bitSlots in the SoundWire frame, however multiple Source ports
shall be configured with different bitSlot configurations. This is the
same limitation as with I2S/PCM TDM usages.”h]”hŒúNote3: Multiple Sink ports can extract the same information for the
same bitSlots in the SoundWire frame, however multiple Source ports
shall be configured with different bitSlot configurations. This is the
same limitation as with I2S/PCM TDM usages.”…””}”(hj~  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÒhh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒ SoundWire Stream Management flow”h]”hŒ SoundWire Stream Management flow”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjŒ  hžhhŸh¶h KØubh¢)”}”(hhh]”(h§)”}”(hŒStream definitions”h]”hŒStream definitions”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h KÛubhÈ)”}”(hX7  (1) Current stream: This is classified as the stream on which operation has
    to be performed like prepare, enable, disable, de-prepare etc.

(2) Active stream: This is classified as the stream which is already active
    on Bus other than current stream. There can be multiple active streams
    on the Bus.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ‡Current stream: This is classified as the stream on which operation has
to be performed like prepare, enable, disable, de-prepare etc.
”h]”h¸)”}”(hŒ†Current stream: This is classified as the stream on which operation has
to be performed like prepare, enable, disable, de-prepare etc.”h]”hŒ†Current stream: This is classified as the stream on which operation has
to be performed like prepare, enable, disable, de-prepare etc.”…””}”(hj¹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÝhjµ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj²  ubhÓ)”}”(hŒ›Active stream: This is classified as the stream which is already active
on Bus other than current stream. There can be multiple active streams
on the Bus.
”h]”h¸)”}”(hŒšActive stream: This is classified as the stream which is already active
on Bus other than current stream. There can be multiple active streams
on the Bus.”h]”hŒšActive stream: This is classified as the stream which is already active
on Bus other than current stream. There can be multiple active streams
on the Bus.”…””}”(hjÑ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KàhjÍ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj²  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhj®  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h KÝhj  hžhubh¸)”}”(hX  SoundWire Bus manages stream operations for each stream getting
rendered/captured on the SoundWire Bus. This section explains Bus operations
done for each of the stream allocated/released on Bus. Following are the
stream states maintained by the Bus for each of the audio stream.”h]”hX  SoundWire Bus manages stream operations for each stream getting
rendered/captured on the SoundWire Bus. This section explains Bus operations
done for each of the stream allocated/released on Bus. Following are the
stream states maintained by the Bus for each of the audio stream.”…””}”(hjñ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kähj  hžhubeh}”(h]”Œstream-definitions”ah ]”h"]”Œstream definitions”ah$]”h&]”uh1h¡hjŒ  hžhhŸh¶h KÛubh¢)”}”(hhh]”(h§)”}”(hŒSoundWire stream states”h]”hŒSoundWire stream states”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h Këubh¸)”}”(hŒHBelow shows the SoundWire stream states and state transition diagram. ::”h]”hŒEBelow shows the SoundWire stream states and state transition diagram.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kíhj  hžhubjq  )”}”(hXH  +-----------+     +------------+     +----------+     +----------+
| ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED  |
|   STATE   |     |    STATE   |     |  STATE   |     |  STATE   |
+-----------+     +------------+     +---+--+---+     +----+-----+
                                         ^  ^              ^
                                         |  |              |
                                       __|  |___________   |
                                      |                 |  |
                                      v                 |  v
         +----------+           +-----+------+        +-+--+-----+
         | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
         |  STATE   |           |   STATE    |        |  STATE   |
         +----------+           +------------+        +----------+”h]”hXH  +-----------+     +------------+     +----------+     +----------+
| ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED  |
|   STATE   |     |    STATE   |     |  STATE   |     |  STATE   |
+-----------+     +------------+     +---+--+---+     +----+-----+
                                         ^  ^              ^
                                         |  |              |
                                       __|  |___________   |
                                      |                 |  |
                                      v                 |  v
         +----------+           +-----+------+        +-+--+-----+
         | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
         |  STATE   |           |   STATE    |        |  STATE   |
         +----------+           +------------+        +----------+”…””}”hj&  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  uh1jp  hŸh¶h Kïhj  hžhubh¸)”}”(hX  NOTE: State transitions between ``SDW_STREAM_ENABLED`` and
``SDW_STREAM_DISABLED`` are only relevant when then INFO_PAUSE flag is
supported at the ALSA/ASoC level. Likewise the transition between
``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STATE`` depends on the
INFO_RESUME flag.”h]”(hŒ NOTE: State transitions between ”…””}”(hj4  hžhhŸNh NubhŒliteral”“”)”}”(hŒ``SDW_STREAM_ENABLED``”h]”hŒSDW_STREAM_ENABLED”…””}”(hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj4  ubhŒ and
”…””}”(hj4  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DISABLED``”h]”hŒSDW_STREAM_DISABLED”…””}”(hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj4  ubhŒr are only relevant when then INFO_PAUSE flag is
supported at the ALSA/ASoC level. Likewise the transition between
”…””}”(hj4  hžhhŸNh Nubj=  )”}”(hŒ``SDW_DISABLED_STATE``”h]”hŒSDW_DISABLED_STATE”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj4  ubhŒ and ”…””}”(hj4  hžhhŸNh Nubj=  )”}”(hŒ``SDW_PREPARED_STATE``”h]”hŒSDW_PREPARED_STATE”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj4  ubhŒ! depends on the
INFO_RESUME flag.”…””}”(hj4  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kýhj  hžhubh¸)”}”(hŒÔNOTE2: The framework implements basic state transition checks, but
does not e.g. check if a transition from DISABLED to ENABLED is valid
on a specific platform. Such tests need to be added at the ALSA/ASoC
level.”h]”hŒÔNOTE2: The framework implements basic state transition checks, but
does not e.g. check if a transition from DISABLED to ENABLED is valid
on a specific platform. Such tests need to be added at the ALSA/ASoC
level.”…””}”(hjŒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj  hžhubeh}”(h]”Œsoundwire-stream-states”ah ]”h"]”Œsoundwire stream states”ah$]”h&]”uh1h¡hjŒ  hžhhŸh¶h Këubh¢)”}”(hhh]”(h§)”}”(hŒStream State Operations”h]”hŒStream State Operations”…””}”(hj¥  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¢  hžhhŸh¶h M	ubh¸)”}”(hŒtBelow section explains the operations done by the Bus on Master(s) and
Slave(s) as part of stream state transitions.”h]”hŒtBelow section explains the operations done by the Bus on Master(s) and
Slave(s) as part of stream state transitions.”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¢  hžhubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_ALLOCATED”h]”hŒSDW_STREAM_ALLOCATED”…””}”(hjÄ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÁ  hžhhŸh¶h Mubh¸)”}”(hŒwAllocation state for stream. This is the entry state
of the stream. Operations performed before entering in this state:”h]”hŒwAllocation state for stream. This is the entry state
of the stream. Operations performed before entering in this state:”…””}”(hjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjÁ  hžhubhÈ)”}”(hX¤  (1) A stream runtime is allocated for the stream. This stream
    runtime is used as a reference for all the operations performed
    on the stream.

(2) The resources required for holding stream runtime information are
    allocated and initialized. This holds all stream related information
    such as stream type (PCM/PDM) and parameters, Master and Slave
    interface associated with the stream, stream state etc.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ‰A stream runtime is allocated for the stream. This stream
runtime is used as a reference for all the operations performed
on the stream.
”h]”h¸)”}”(hŒˆA stream runtime is allocated for the stream. This stream
runtime is used as a reference for all the operations performed
on the stream.”h]”hŒˆA stream runtime is allocated for the stream. This stream
runtime is used as a reference for all the operations performed
on the stream.”…””}”(hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjç  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjä  ubhÓ)”}”(hŒþThe resources required for holding stream runtime information are
allocated and initialized. This holds all stream related information
such as stream type (PCM/PDM) and parameters, Master and Slave
interface associated with the stream, stream state etc.
”h]”h¸)”}”(hŒýThe resources required for holding stream runtime information are
allocated and initialized. This holds all stream related information
such as stream type (PCM/PDM) and parameters, Master and Slave
interface associated with the stream, stream state etc.”h]”hŒýThe resources required for holding stream runtime information are
allocated and initialized. This holds all stream related information
such as stream type (PCM/PDM) and parameters, Master and Slave
interface associated with the stream, stream state etc.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjÿ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjä  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhjà  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h MhjÁ  hžhubh¸)”}”(hŒ[After all above operations are successful, stream state is set to
``SDW_STREAM_ALLOCATED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hj#  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_ALLOCATED``”h]”hŒSDW_STREAM_ALLOCATED”…””}”(hj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj#  ubhŒ.”…””}”(hj#  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjÁ  hžhubh¸)”}”(hŒªBus implements below API for allocate a stream which needs to be called once
per stream. From ASoC DPCM framework, this stream state maybe linked to
.startup() operation.”h]”hŒªBus implements below API for allocate a stream which needs to be called once
per stream. From ASoC DPCM framework, this stream state maybe linked to
.startup() operation.”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M hjÁ  hžhubjq  )”}”(hŒDint sdw_alloc_stream(char * stream_name, enum sdw_stream_type type);”h]”hŒDint sdw_alloc_stream(char * stream_name, enum sdw_stream_type type);”…””}”hjQ  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  Œforce”‰Œlanguage”Œc”Œhighlight_args”}”uh1jp  hŸh¶h M$hjÁ  hžhubh¸)”}”(hŒÛThe SoundWire core provides a sdw_startup_stream() helper function,
typically called during a dailink .startup() callback, which performs
stream allocation and sets the stream pointer for all DAIs
connected to a stream.”h]”hŒÛThe SoundWire core provides a sdw_startup_stream() helper function,
typically called during a dailink .startup() callback, which performs
stream allocation and sets the stream pointer for all DAIs
connected to a stream.”…””}”(hjd  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M(hjÁ  hžhubeh}”(h]”Œsdw-stream-allocated”ah ]”h"]”Œsdw_stream_allocated”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h Mubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_CONFIGURED”h]”hŒSDW_STREAM_CONFIGURED”…””}”(hj}  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjz  hžhhŸh¶h M.ubh¸)”}”(hŒRConfiguration state of stream. Operations performed before entering in
this state:”h]”hŒRConfiguration state of stream. Operations performed before entering in
this state:”…””}”(hj‹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M0hjz  hžhubhÈ)”}”(hX±  (1) The resources allocated for stream information in SDW_STREAM_ALLOCATED
    state are updated here. This includes stream parameters, Master(s)
    and Slave(s) runtime information associated with current stream.

(2) All the Master(s) and Slave(s) associated with current stream provide
    the port information to Bus which includes port numbers allocated by
    Master(s) and Slave(s) for current stream and their channel mask.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒËThe resources allocated for stream information in SDW_STREAM_ALLOCATED
state are updated here. This includes stream parameters, Master(s)
and Slave(s) runtime information associated with current stream.
”h]”h¸)”}”(hŒÊThe resources allocated for stream information in SDW_STREAM_ALLOCATED
state are updated here. This includes stream parameters, Master(s)
and Slave(s) runtime information associated with current stream.”h]”hŒÊThe resources allocated for stream information in SDW_STREAM_ALLOCATED
state are updated here. This includes stream parameters, Master(s)
and Slave(s) runtime information associated with current stream.”…””}”(hj¤  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M3hj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj  ubhÓ)”}”(hŒÍAll the Master(s) and Slave(s) associated with current stream provide
the port information to Bus which includes port numbers allocated by
Master(s) and Slave(s) for current stream and their channel mask.
”h]”h¸)”}”(hŒÌAll the Master(s) and Slave(s) associated with current stream provide
the port information to Bus which includes port numbers allocated by
Master(s) and Slave(s) for current stream and their channel mask.”h]”hŒÌAll the Master(s) and Slave(s) associated with current stream provide
the port information to Bus which includes port numbers allocated by
Master(s) and Slave(s) for current stream and their channel mask.”…””}”(hj¼  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M7hj¸  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhj™  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h M3hjz  hžhubh¸)”}”(hŒ\After all above operations are successful, stream state is set to
``SDW_STREAM_CONFIGURED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hjÜ  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_CONFIGURED``”h]”hŒSDW_STREAM_CONFIGURED”…””}”(hjä  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hjÜ  ubhŒ.”…””}”(hjÜ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M;hjz  hžhubh¸)”}”(hX  Bus implements below APIs for CONFIG state which needs to be called by
the respective Master(s) and Slave(s) associated with stream. These APIs can
only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
framework, this stream state is linked to .hw_params() operation.”h]”hX  Bus implements below APIs for CONFIG state which needs to be called by
the respective Master(s) and Slave(s) associated with stream. These APIs can
only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
framework, this stream state is linked to .hw_params() operation.”…””}”(hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M>hjz  hžhubjq  )”}”(hX±  int sdw_stream_add_master(struct sdw_bus * bus,
              struct sdw_stream_config * stream_config,
              const struct sdw_ports_config * ports_config,
              struct sdw_stream_runtime * stream);

int sdw_stream_add_slave(struct sdw_slave * slave,
              struct sdw_stream_config * stream_config,
              const struct sdw_ports_config * ports_config,
              struct sdw_stream_runtime * stream);”h]”hX±  int sdw_stream_add_master(struct sdw_bus * bus,
              struct sdw_stream_config * stream_config,
              const struct sdw_ports_config * ports_config,
              struct sdw_stream_runtime * stream);

int sdw_stream_add_slave(struct sdw_slave * slave,
              struct sdw_stream_config * stream_config,
              const struct sdw_ports_config * ports_config,
              struct sdw_stream_runtime * stream);”…””}”hj
  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h MChjz  hžhubeh}”(h]”Œsdw-stream-configured”ah ]”h"]”Œsdw_stream_configured”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h M.ubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_PREPARED”h]”hŒSDW_STREAM_PREPARED”…””}”(hj$  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj!  hžhhŸh¶h MQubh¸)”}”(hŒLPrepare state of stream. Operations performed before entering in this state:”h]”hŒLPrepare state of stream. Operations performed before entering in this state:”…””}”(hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MShj!  hžhubhÈ)”}”(hXx  (0) Steps 1 and 2 are omitted in the case of a resume operation,
    where the bus bandwidth is known.

(1) Bus parameters such as bandwidth, frame shape, clock frequency,
    are computed based on current stream as well as already active
    stream(s) on Bus. Re-computation is required to accommodate current
    stream on the Bus.

(2) Transport and port parameters of all Master(s) and Slave(s) port(s) are
    computed for the current as well as already active stream based on frame
    shape and clock frequency computed in step 1.

(3) Computed Bus and transport parameters are programmed in Master(s) and
    Slave(s) registers. The banked registers programming is done on the
    alternate bank (bank currently unused). Port(s) are enabled for the
    already active stream(s) on the alternate bank (bank currently unused).
    This is done in order to not disrupt already active stream(s).

(4) Once all the values are programmed, Bus initiates switch to alternate
    bank where all new values programmed gets into effect.

(5) Ports of Master(s) and Slave(s) for current stream are prepared by
    programming PrepareCtrl register.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ_Steps 1 and 2 are omitted in the case of a resume operation,
where the bus bandwidth is known.
”h]”h¸)”}”(hŒ^Steps 1 and 2 are omitted in the case of a resume operation,
where the bus bandwidth is known.”h]”hŒ^Steps 1 and 2 are omitted in the case of a resume operation,
where the bus bandwidth is known.”…””}”(hjK  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MUhjG  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubhÓ)”}”(hŒÖBus parameters such as bandwidth, frame shape, clock frequency,
are computed based on current stream as well as already active
stream(s) on Bus. Re-computation is required to accommodate current
stream on the Bus.
”h]”h¸)”}”(hŒÕBus parameters such as bandwidth, frame shape, clock frequency,
are computed based on current stream as well as already active
stream(s) on Bus. Re-computation is required to accommodate current
stream on the Bus.”h]”hŒÕBus parameters such as bandwidth, frame shape, clock frequency,
are computed based on current stream as well as already active
stream(s) on Bus. Re-computation is required to accommodate current
stream on the Bus.”…””}”(hjc  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MXhj_  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubhÓ)”}”(hŒ¿Transport and port parameters of all Master(s) and Slave(s) port(s) are
computed for the current as well as already active stream based on frame
shape and clock frequency computed in step 1.
”h]”h¸)”}”(hŒ¾Transport and port parameters of all Master(s) and Slave(s) port(s) are
computed for the current as well as already active stream based on frame
shape and clock frequency computed in step 1.”h]”hŒ¾Transport and port parameters of all Master(s) and Slave(s) port(s) are
computed for the current as well as already active stream based on frame
shape and clock frequency computed in step 1.”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M]hjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubhÓ)”}”(hXU  Computed Bus and transport parameters are programmed in Master(s) and
Slave(s) registers. The banked registers programming is done on the
alternate bank (bank currently unused). Port(s) are enabled for the
already active stream(s) on the alternate bank (bank currently unused).
This is done in order to not disrupt already active stream(s).
”h]”h¸)”}”(hXT  Computed Bus and transport parameters are programmed in Master(s) and
Slave(s) registers. The banked registers programming is done on the
alternate bank (bank currently unused). Port(s) are enabled for the
already active stream(s) on the alternate bank (bank currently unused).
This is done in order to not disrupt already active stream(s).”h]”hXT  Computed Bus and transport parameters are programmed in Master(s) and
Slave(s) registers. The banked registers programming is done on the
alternate bank (bank currently unused). Port(s) are enabled for the
already active stream(s) on the alternate bank (bank currently unused).
This is done in order to not disrupt already active stream(s).”…””}”(hj“  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mahj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubhÓ)”}”(hŒ}Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect.
”h]”h¸)”}”(hŒ|Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect.”h]”hŒ|Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect.”…””}”(hj«  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mghj§  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubhÓ)”}”(hŒePorts of Master(s) and Slave(s) for current stream are prepared by
programming PrepareCtrl register.
”h]”h¸)”}”(hŒdPorts of Master(s) and Slave(s) for current stream are prepared by
programming PrepareCtrl register.”h]”hŒdPorts of Master(s) and Slave(s) for current stream are prepared by
programming PrepareCtrl register.”…””}”(hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mjhj¿  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjD  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  Œstart”K uh1hÍhj@  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h MUhj!  hžhubh¸)”}”(hŒZAfter all above operations are successful, stream state is set to
``SDW_STREAM_PREPARED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hjä  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_PREPARED``”h]”hŒSDW_STREAM_PREPARED”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hjä  ubhŒ.”…””}”(hjä  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mmhj!  hžhubh¸)”}”(hX<  Bus implements below API for PREPARE state which needs to be called
once per stream. From ASoC DPCM framework, this stream state is linked
to .prepare() operation. Since the .trigger() operations may not
follow the .prepare(), a direct transition from
``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREPARED`` is allowed.”h]”(hŒüBus implements below API for PREPARE state which needs to be called
once per stream. From ASoC DPCM framework, this stream state is linked
to .prepare() operation. Since the .trigger() operations may not
follow the .prepare(), a direct transition from
”…””}”(hj  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_PREPARED``”h]”hŒSDW_STREAM_PREPARED”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj  ubhŒ to ”…””}”(hj  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DEPREPARED``”h]”hŒSDW_STREAM_DEPREPARED”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj  ubhŒ is allowed.”…””}”(hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mphj!  hžhubjq  )”}”(hŒ;int sdw_prepare_stream(struct sdw_stream_runtime * stream);”h]”hŒ;int sdw_prepare_stream(struct sdw_stream_runtime * stream);”…””}”hj6  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h Mvhj!  hžhubeh}”(h]”Œsdw-stream-prepared”ah ]”h"]”Œsdw_stream_prepared”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h MQubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_ENABLED”h]”hŒSDW_STREAM_ENABLED”…””}”(hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjM  hžhhŸh¶h M|ubh¸)”}”(hŒ‚Enable state of stream. The data port(s) are enabled upon entering this state.
Operations performed before entering in this state:”h]”hŒ‚Enable state of stream. The data port(s) are enabled upon entering this state.
Operations performed before entering in this state:”…””}”(hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M~hjM  hžhubhÈ)”}”(hX  (1) All the values computed in SDW_STREAM_PREPARED state are programmed
    in alternate bank (bank currently unused). It includes programming of
    already active stream(s) as well.

(2) All the Master(s) and Slave(s) port(s) for the current stream are
    enabled on alternate bank (bank currently unused) by programming
    ChannelEn register.

(3) Once all the values are programmed, Bus initiates switch to alternate
    bank where all new values programmed gets into effect and port(s)
    associated with current stream are enabled.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ¬All the values computed in SDW_STREAM_PREPARED state are programmed
in alternate bank (bank currently unused). It includes programming of
already active stream(s) as well.
”h]”h¸)”}”(hŒ«All the values computed in SDW_STREAM_PREPARED state are programmed
in alternate bank (bank currently unused). It includes programming of
already active stream(s) as well.”h]”hŒ«All the values computed in SDW_STREAM_PREPARED state are programmed
in alternate bank (bank currently unused). It includes programming of
already active stream(s) as well.”…””}”(hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjs  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjp  ubhÓ)”}”(hŒ—All the Master(s) and Slave(s) port(s) for the current stream are
enabled on alternate bank (bank currently unused) by programming
ChannelEn register.
”h]”h¸)”}”(hŒ–All the Master(s) and Slave(s) port(s) for the current stream are
enabled on alternate bank (bank currently unused) by programming
ChannelEn register.”h]”hŒ–All the Master(s) and Slave(s) port(s) for the current stream are
enabled on alternate bank (bank currently unused) by programming
ChannelEn register.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M…hj‹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjp  ubhÓ)”}”(hŒ´Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s)
associated with current stream are enabled.
”h]”h¸)”}”(hŒ³Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s)
associated with current stream are enabled.”h]”hŒ³Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s)
associated with current stream are enabled.”…””}”(hj§  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M‰hj£  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhjp  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhjl  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h MhjM  hžhubh¸)”}”(hŒYAfter all above operations are successful, stream state is set to
``SDW_STREAM_ENABLED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hjÇ  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_ENABLED``”h]”hŒSDW_STREAM_ENABLED”…””}”(hjÏ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hjÇ  ubhŒ.”…””}”(hjÇ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjM  hžhubh¸)”}”(hŒ¨Bus implements below API for ENABLE state which needs to be called once per
stream. From ASoC DPCM framework, this stream state is linked to
.trigger() start operation.”h]”hŒ¨Bus implements below API for ENABLE state which needs to be called once per
stream. From ASoC DPCM framework, this stream state is linked to
.trigger() start operation.”…””}”(hjç  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjM  hžhubjq  )”}”(hŒ:int sdw_enable_stream(struct sdw_stream_runtime * stream);”h]”hŒ:int sdw_enable_stream(struct sdw_stream_runtime * stream);”…””}”hjõ  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h M”hjM  hžhubeh}”(h]”Œsdw-stream-enabled”ah ]”h"]”Œsdw_stream_enabled”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h M|ubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_DISABLED”h]”hŒSDW_STREAM_DISABLED”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h M™ubh¸)”}”(hŒƒDisable state of stream. The data port(s) are disabled upon exiting this state.
Operations performed before entering in this state:”h]”hŒƒDisable state of stream. The data port(s) are disabled upon exiting this state.
Operations performed before entering in this state:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M›hj  hžhubhÈ)”}”(hXå  (1) All the Master(s) and Slave(s) port(s) for the current stream are
    disabled on alternate bank (bank currently unused) by programming
    ChannelEn register.

(2) All the current configuration of Bus and active stream(s) are programmed
    into alternate bank (bank currently unused).

(3) Once all the values are programmed, Bus initiates switch to alternate
    bank where all new values programmed gets into effect and port(s) associated
    with current stream are disabled.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ˜All the Master(s) and Slave(s) port(s) for the current stream are
disabled on alternate bank (bank currently unused) by programming
ChannelEn register.
”h]”h¸)”}”(hŒ—All the Master(s) and Slave(s) port(s) for the current stream are
disabled on alternate bank (bank currently unused) by programming
ChannelEn register.”h]”hŒ—All the Master(s) and Slave(s) port(s) for the current stream are
disabled on alternate bank (bank currently unused) by programming
ChannelEn register.”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mžhj2  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj/  ubhÓ)”}”(hŒvAll the current configuration of Bus and active stream(s) are programmed
into alternate bank (bank currently unused).
”h]”h¸)”}”(hŒuAll the current configuration of Bus and active stream(s) are programmed
into alternate bank (bank currently unused).”h]”hŒuAll the current configuration of Bus and active stream(s) are programmed
into alternate bank (bank currently unused).”…””}”(hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¢hjJ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj/  ubhÓ)”}”(hŒµOnce all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s) associated
with current stream are disabled.
”h]”h¸)”}”(hŒ´Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s) associated
with current stream are disabled.”h]”hŒ´Once all the values are programmed, Bus initiates switch to alternate
bank where all new values programmed gets into effect and port(s) associated
with current stream are disabled.”…””}”(hjf  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¥hjb  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj/  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhj+  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h Mžhj  hžhubh¸)”}”(hŒZAfter all above operations are successful, stream state is set to
``SDW_STREAM_DISABLED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hj†  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DISABLED``”h]”hŒSDW_STREAM_DISABLED”…””}”(hjŽ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj†  ubhŒ.”…””}”(hj†  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M©hj  hžhubh¸)”}”(hŒ©Bus implements below API for DISABLED state which needs to be called once
per stream. From ASoC DPCM framework, this stream state is linked to
.trigger() stop operation.”h]”hŒ©Bus implements below API for DISABLED state which needs to be called once
per stream. From ASoC DPCM framework, this stream state is linked to
.trigger() stop operation.”…””}”(hj¦  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¬hj  hžhubh¸)”}”(hŒ`When the INFO_PAUSE flag is supported, a direct transition to
``SDW_STREAM_ENABLED`` is allowed.”h]”(hŒ>When the INFO_PAUSE flag is supported, a direct transition to
”…””}”(hj´  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_ENABLED``”h]”hŒSDW_STREAM_ENABLED”…””}”(hj¼  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj´  ubhŒ is allowed.”…””}”(hj´  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M°hj  hžhubh¸)”}”(hŒðFor resume operations where ASoC will use the .prepare() callback, the
stream can transition from ``SDW_STREAM_DISABLED`` to
``SDW_STREAM_PREPARED``, with all required settings restored but
without updating the bandwidth and bit allocation.”h]”(hŒbFor resume operations where ASoC will use the .prepare() callback, the
stream can transition from ”…””}”(hjÔ  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DISABLED``”h]”hŒSDW_STREAM_DISABLED”…””}”(hjÜ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hjÔ  ubhŒ to
”…””}”(hjÔ  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_PREPARED``”h]”hŒSDW_STREAM_PREPARED”…””}”(hjî  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hjÔ  ubhŒ\, with all required settings restored but
without updating the bandwidth and bit allocation.”…””}”(hjÔ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M³hj  hžhubjq  )”}”(hŒ;int sdw_disable_stream(struct sdw_stream_runtime * stream);”h]”hŒ;int sdw_disable_stream(struct sdw_stream_runtime * stream);”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h M¸hj  hžhubeh}”(h]”Œsdw-stream-disabled”ah ]”h"]”Œsdw_stream_disabled”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h M™ubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_DEPREPARED”h]”hŒSDW_STREAM_DEPREPARED”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h M¾ubh¸)”}”(hŒODe-prepare state of stream. Operations performed before entering in this
state:”h]”hŒODe-prepare state of stream. Operations performed before entering in this
state:”…””}”(hj.  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÀhj  hžhubhÈ)”}”(hX/  (1) All the port(s) of Master(s) and Slave(s) for current stream are
    de-prepared by programming PrepareCtrl register.

(2) The payload bandwidth of current stream is reduced from the total
    bandwidth requirement of bus and new parameters calculated and
    applied by performing bank switch etc.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒrAll the port(s) of Master(s) and Slave(s) for current stream are
de-prepared by programming PrepareCtrl register.
”h]”h¸)”}”(hŒqAll the port(s) of Master(s) and Slave(s) for current stream are
de-prepared by programming PrepareCtrl register.”h]”hŒqAll the port(s) of Master(s) and Slave(s) for current stream are
de-prepared by programming PrepareCtrl register.”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÃhjC  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj@  ubhÓ)”}”(hŒ¨The payload bandwidth of current stream is reduced from the total
bandwidth requirement of bus and new parameters calculated and
applied by performing bank switch etc.
”h]”h¸)”}”(hŒ§The payload bandwidth of current stream is reduced from the total
bandwidth requirement of bus and new parameters calculated and
applied by performing bank switch etc.”h]”hŒ§The payload bandwidth of current stream is reduced from the total
bandwidth requirement of bus and new parameters calculated and
applied by performing bank switch etc.”…””}”(hj_  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÆhj[  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj@  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhj<  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h MÃhj  hžhubh¸)”}”(hŒ\After all above operations are successful, stream state is set to
``SDW_STREAM_DEPREPARED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hj  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DEPREPARED``”h]”hŒSDW_STREAM_DEPREPARED”…””}”(hj‡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj  ubhŒ.”…””}”(hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÊhj  hžhubh¸)”}”(hŒåBus implements below API for DEPREPARED state which needs to be called
once per stream. ALSA/ASoC do not have a concept of 'deprepare', and
the mapping from this stream state to ALSA/ASoC operation may be
implementation specific.”h]”hŒéBus implements below API for DEPREPARED state which needs to be called
once per stream. ALSA/ASoC do not have a concept of â€˜deprepareâ€™, and
the mapping from this stream state to ALSA/ASoC operation may be
implementation specific.”…””}”(hjŸ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÍhj  hžhubh¸)”}”(hŒWhen the INFO_PAUSE flag is supported, the stream state is linked to
the .hw_free() operation - the stream is not deprepared on a
TRIGGER_STOP.”h]”hŒWhen the INFO_PAUSE flag is supported, the stream state is linked to
the .hw_free() operation - the stream is not deprepared on a
TRIGGER_STOP.”…””}”(hj­  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÒhj  hžhubh¸)”}”(hŒ¨Other implementations may transition to the ``SDW_STREAM_DEPREPARED``
state on TRIGGER_STOP, should they require a transition through the
``SDW_STREAM_PREPARED`` state.”h]”(hŒ,Other implementations may transition to the ”…””}”(hj»  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_DEPREPARED``”h]”hŒSDW_STREAM_DEPREPARED”…””•œ&      }”(hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj»  ubhŒE
state on TRIGGER_STOP, should they require a transition through the
”…””}”(hj»  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_PREPARED``”h]”hŒSDW_STREAM_PREPARED”…””}”(hjÕ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj»  ubhŒ state.”…””}”(hj»  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÖhj  hžhubjq  )”}”(hŒ=int sdw_deprepare_stream(struct sdw_stream_runtime * stream);”h]”hŒ=int sdw_deprepare_stream(struct sdw_stream_runtime * stream);”…””}”hjí  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h MÚhj  hžhubeh}”(h]”Œsdw-stream-deprepared”ah ]”h"]”Œsdw_stream_deprepared”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h M¾ubh¢)”}”(hhh]”(h§)”}”(hŒSDW_STREAM_RELEASED”h]”hŒSDW_STREAM_RELEASED”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj	  hžhhŸh¶h Màubh¸)”}”(hŒLRelease state of stream. Operations performed before entering in this state:”h]”hŒLRelease state of stream. Operations performed before entering in this state:”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mâhj	  hžhubhÈ)”}”(hX  (1) Release port resources for all Master(s) and Slave(s) port(s)
    associated with current stream.

(2) Release Master(s) and Slave(s) runtime resources associated with
    current stream.

(3) Release stream runtime resources associated with current stream.
”h]”hÎ)”}”(hhh]”(hÓ)”}”(hŒ^Release port resources for all Master(s) and Slave(s) port(s)
associated with current stream.
”h]”h¸)”}”(hŒ]Release port resources for all Master(s) and Slave(s) port(s)
associated with current stream.”h]”hŒ]Release port resources for all Master(s) and Slave(s) port(s)
associated with current stream.”…””}”(hj.	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mähj*	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj'	  ubhÓ)”}”(hŒQRelease Master(s) and Slave(s) runtime resources associated with
current stream.
”h]”h¸)”}”(hŒPRelease Master(s) and Slave(s) runtime resources associated with
current stream.”h]”hŒPRelease Master(s) and Slave(s) runtime resources associated with
current stream.”…””}”(hjF	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MçhjB	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj'	  ubhÓ)”}”(hŒARelease stream runtime resources associated with current stream.
”h]”h¸)”}”(hŒ@Release stream runtime resources associated with current stream.”h]”hŒ@Release stream runtime resources associated with current stream.”…””}”(hj^	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MêhjZ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj'	  ubeh}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  j=  j>  j?  uh1hÍhj#	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhŸh¶h Mähj	  hžhubh¸)”}”(hŒZAfter all above operations are successful, stream state is set to
``SDW_STREAM_RELEASED``.”h]”(hŒBAfter all above operations are successful, stream state is set to
”…””}”(hj~	  hžhhŸNh Nubj=  )”}”(hŒ``SDW_STREAM_RELEASED``”h]”hŒSDW_STREAM_RELEASED”…””}”(hj†	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<  hj~	  ubhŒ.”…””}”(hj~	  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mìhj	  hžhubh¸)”}”(hŒÍBus implements below APIs for RELEASE state which needs to be called by
all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
framework, this stream state is linked to .hw_free() operation.”h]”hŒÍBus implements below APIs for RELEASE state which needs to be called by
all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
framework, this stream state is linked to .hw_free() operation.”…””}”(hjž	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mïhj	  hžhubjq  )”}”(hŒÎint sdw_stream_remove_master(struct sdw_bus * bus,
              struct sdw_stream_runtime * stream);
int sdw_stream_remove_slave(struct sdw_slave * slave,
              struct sdw_stream_runtime * stream);”h]”hŒÎint sdw_stream_remove_master(struct sdw_bus * bus,
              struct sdw_stream_runtime * stream);
int sdw_stream_remove_slave(struct sdw_slave * slave,
              struct sdw_stream_runtime * stream);”…””}”hj¬	  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h Móhj	  hžhubh¸)”}”(hŒnThe .shutdown() ASoC DPCM operation calls below Bus API to release
stream assigned as part of ALLOCATED state.”h]”hŒnThe .shutdown() ASoC DPCM operation calls below Bus API to release
stream assigned as part of ALLOCATED state.”…””}”(hj»	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mûhj	  hžhubh¸)”}”(hŒHIn .shutdown() the data structure maintaining stream state are freed up.”h]”hŒHIn .shutdown() the data structure maintaining stream state are freed up.”…””}”(hjÉ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mþhj	  hžhubjq  )”}”(hŒ<void sdw_release_stream(struct sdw_stream_runtime * stream);”h]”hŒ<void sdw_release_stream(struct sdw_stream_runtime * stream);”…””}”hj×	  sbah}”(h]”h ]”h"]”h$]”h&]”j€  j  j_  ‰j`  ja  jb  }”uh1jp  hŸh¶h M hj	  hžhubh¸)”}”(hŒñThe SoundWire core provides a sdw_shutdown_stream() helper function,
typically called during a dailink .shutdown() callback, which clears
the stream pointer for all DAIS connected to a stream and releases the
memory allocated for the stream.”h]”hŒñThe SoundWire core provides a sdw_shutdown_stream() helper function,
typically called during a dailink .shutdown() callback, which clears
the stream pointer for all DAIS connected to a stream and releases the
memory allocated for the stream.”…””}”(hjæ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj	  hžhubeh}”(h]”Œsdw-stream-released”ah ]”h"]”Œsdw_stream_released”ah$]”h&]”uh1h¡hj¢  hžhhŸh¶h Màubeh}”(h]”Œstream-state-operations”ah ]”h"]”Œstream state operations”ah$]”h&]”uh1h¡hjŒ  hžhhŸh¶h M	ubeh}”(h]”Œ soundwire-stream-management-flow”ah ]”h"]”Œ soundwire stream management flow”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KØubh¢)”}”(hhh]”(h§)”}”(hŒNot Supported”h]”hŒNot Supported”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj
  hžhhŸh¶h M
ubhÎ)”}”(hhh]”hÓ)”}”(hŒîA single port with multiple channels supported cannot be used between two
streams or across stream. For example a port with 4 channels cannot be used
to handle 2 independent stereo streams even though it's possible in theory
in SoundWire.”h]”h¸)”}”(hŒîA single port with multiple channels supported cannot be used between two
streams or across stream. For example a port with 4 channels cannot be used
to handle 2 independent stereo streams even though it's possible in theory
in SoundWire.”h]”hŒðA single port with multiple channels supported cannot be used between two
streams or across stream. For example a port with 4 channels cannot be used
to handle 2 independent stereo streams even though itâ€™s possible in theory
in SoundWire.”…””}”(hj$
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj 
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÒhj
  hžhhŸh¶h Nubah}”(h]”h ]”h"]”h$]”h&]”j:  j;  j<  hj>  Œ.”uh1hÍhj
  hžhhŸh¶h Mubeh}”(h]”Œnot-supported”ah ]”h"]”Œnot supported”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M
ubeh}”(h]”Œaudio-stream-in-soundwire”ah ]”h"]”Œaudio stream in soundwire”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jr
  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jL
  jI
  j	
  j
  j  j  jŸ  jœ  j
  jþ	  jw  jt  j  j  jJ  jG  j	  j  j  j  j	  jþ  jù	  jö	  jD
  jA
  uŒ	nametypes”}”(jL
  ‰j	
  ‰j  ‰jŸ  ‰j
  ‰jw  ‰j  ‰jJ  ‰j	  ‰j  ‰j	  ‰jù	  ‰jD
  ‰uh}”(jI
  h£j
  jŒ  j  j  jœ  j  jþ	  j¢  jt  jÁ  j  jz  jG  j!  j  jM  j  j  jþ  j  jö	  j	  jA
  j
  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”hŒsystem_message”“”)”}”(hhh]”h¸)”}”(hŒ:Enumerated list start value not ordinal-1: "0" (ordinal 0)”h]”hŒ>Enumerated list start value not ordinal-1: â€œ0â€ (ordinal 0)”…””}”(hjÙ
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hjÖ
  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œsource”h¶Œline”Kuh1jÔ
  hj@  ubaŒtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.