€•ZØ      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ,/translations/zh_CN/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/zh_TW/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/it_IT/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/ja_JP/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/ko_KR/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/sp_SP/driver-api/soundwire/bra”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒBulk Register Access (BRA)”h]”hŒBulk Register Access (BRA)”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒF/var/lib/git/docbuild/linux/Documentation/driver-api/soundwire/bra.rst”h Kubh¢)”}”(hhh]”(h§)”}”(hŒConventions”h]”hŒConventions”…””}”(hhºhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh·hžhhŸh¶h KubhŒ	paragraph”“”)”}”(hŒvCapitalized words used in this documentation are intentional and refer
to concepts of the SoundWire 1.x specification.”h]”hŒvCapitalized words used in this documentation are intentional and refer
to concepts of the SoundWire 1.x specification.”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khh·hžhubeh}”(h]”Œconventions”ah ]”h"]”Œconventions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒIntroduction”h]”hŒIntroduction”…””}”(hhãhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhàhžhhŸh¶h KubhÉ)”}”(hŒüThe SoundWire 1.x specification provides a mechanism to speed-up
command/control transfers by reclaiming parts of the audio
bandwidth. The Bulk Register Access (BRA) protocol is a standard
solution based on the Bulk Payload Transport (BPT) definitions.”h]”hŒüThe SoundWire 1.x specification provides a mechanism to speed-up
command/control transfers by reclaiming parts of the audio
bandwidth. The Bulk Register Access (BRA) protocol is a standard
solution based on the Bulk Payload Transport (BPT) definitions.”…””}”(hhñhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KhhàhžhubhÉ)”}”(hŒ²The regular control channel uses Column 0 and can only send/retrieve
one byte per frame with write/read commands. With a typical 48kHz
frame rate, only 48kB/s can be transferred.”h]”hŒ²The regular control channel uses Column 0 and can only send/retrieve
one byte per frame with write/read commands. With a typical 48kHz
frame rate, only 48kB/s can be transferred.”…””}”(hhÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KhhàhžhubhÉ)”}”(hŒ©The optional Bulk Register Access capability can transmit up to 12
Mbits/s and reduce transfer times by several orders of magnitude, but
has multiple design constraints:”h]”hŒ©The optional Bulk Register Access capability can transmit up to 12
Mbits/s and reduce transfer times by several orders of magnitude, but
has multiple design constraints:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KhhàhžhubhŒblock_quote”“”)”}”(hX	  (1) Each frame can only support a read or a write transfer, with a
    10-byte overhead per frame (header and footer response).

(2) The read/writes SHALL be from/to contiguous register addresses
    in the same frame. A fragmented register space decreases the
    efficiency of the protocol by requiring multiple BRA transfers
    scheduled in different frames.

(3) The targeted Peripheral device SHALL support the optional Data
    Port 0, and likewise the Manager SHALL expose audio-like Ports
    to insert BRA packets in the audio payload using the concepts of
    Sample Interval, HSTART, HSTOP, etc.

(4) The BRA transport efficiency depends on the available
    bandwidth. If there are no on-going audio transfers, the entire
    frame minus Column 0 can be reclaimed for BRA. The frame shape
    also impacts efficiency: since Column0 cannot be used for
    BTP/BRA, the frame should rely on a large number of columns and
    minimize the number of rows. The bus clock should be as high as
    possible.

(5) The number of bits transferred per frame SHALL be a multiple of
    8 bits. Padding bits SHALL be inserted if necessary at the end
    of the data.

(6) The regular read/write commands can be issued in parallel with
    BRA transfers. This is convenient to e.g. deal with alerts, jack
    detection or change the volume during firmware download, but
    accessing the same address with two independent protocols has to
    be avoided to avoid undefined behavior.

(7) Some implementations may not be capable of handling the
    bandwidth of the BRA protocol, e.g. in the case of a slow I2C
    bus behind the SoundWire IP. In this case, the transfers may
    need to be spaced in time or flow-controlled.

(8) Each BRA packet SHALL be marked as 'Active' when valid data is
    to be transmitted. This allows for software to allocate a BRA
    stream but not transmit/discard data while processing the
    results or preparing the next batch of data, or allowing the
    peripheral to deal with the previous transfer. In addition BRA
    transfer can be started early on without data being ready.

(9) Up to 470 bytes may be transmitted per frame.

(10) The address is represented with 32 bits and does not rely on
     the paging registers used for the regular command/control
     protocol in Column 0.

”h]”hŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒxEach frame can only support a read or a write transfer, with a
10-byte overhead per frame (header and footer response).
”h]”hÉ)”}”(hŒwEach frame can only support a read or a write transfer, with a
10-byte overhead per frame (header and footer response).”h]”hŒwEach frame can only support a read or a write transfer, with a
10-byte overhead per frame (header and footer response).”…””}”(hj,  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khj(  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒÚThe read/writes SHALL be from/to contiguous register addresses
in the same frame. A fragmented register space decreases the
efficiency of the protocol by requiring multiple BRA transfers
scheduled in different frames.
”h]”hÉ)”}”(hŒÙThe read/writes SHALL be from/to contiguous register addresses
in the same frame. A fragmented register space decreases the
efficiency of the protocol by requiring multiple BRA transfers
scheduled in different frames.”h]”hŒÙThe read/writes SHALL be from/to contiguous register addresses
in the same frame. A fragmented register space decreases the
efficiency of the protocol by requiring multiple BRA transfers
scheduled in different frames.”…””}”(hjD  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Khj@  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒäThe targeted Peripheral device SHALL support the optional Data
Port 0, and likewise the Manager SHALL expose audio-like Ports
to insert BRA packets in the audio payload using the concepts of
Sample Interval, HSTART, HSTOP, etc.
”h]”hÉ)”}”(hŒãThe targeted Peripheral device SHALL support the optional Data
Port 0, and likewise the Manager SHALL expose audio-like Ports
to insert BRA packets in the audio payload using the concepts of
Sample Interval, HSTART, HSTOP, etc.”h]”hŒãThe targeted Peripheral device SHALL support the optional Data
Port 0, and likewise the Manager SHALL expose audio-like Ports
to insert BRA packets in the audio payload using the concepts of
Sample Interval, HSTART, HSTOP, etc.”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K#hjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hXy  The BRA transport efficiency depends on the available
bandwidth. If there are no on-going audio transfers, the entire
frame minus Column 0 can be reclaimed for BRA. The frame shape
also impacts efficiency: since Column0 cannot be used for
BTP/BRA, the frame should rely on a large number of columns and
minimize the number of rows. The bus clock should be as high as
possible.
”h]”hÉ)”}”(hXx  The BRA transport efficiency depends on the available
bandwidth. If there are no on-going audio transfers, the entire
frame minus Column 0 can be reclaimed for BRA. The frame shape
also impacts efficiency: since Column0 cannot be used for
BTP/BRA, the frame should rely on a large number of columns and
minimize the number of rows. The bus clock should be as high as
possible.”h]”hXx  The BRA transport efficiency depends on the available
bandwidth. If there are no on-going audio transfers, the entire
frame minus Column 0 can be reclaimed for BRA. The frame shape
also impacts efficiency: since Column0 cannot be used for
BTP/BRA, the frame should rely on a large number of columns and
minimize the number of rows. The bus clock should be as high as
possible.”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K(hjp  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒŒThe number of bits transferred per frame SHALL be a multiple of
8 bits. Padding bits SHALL be inserted if necessary at the end
of the data.
”h]”hÉ)”}”(hŒ‹The number of bits transferred per frame SHALL be a multiple of
8 bits. Padding bits SHALL be inserted if necessary at the end
of the data.”h]”hŒ‹The number of bits transferred per frame SHALL be a multiple of
8 bits. Padding bits SHALL be inserted if necessary at the end
of the data.”…””}”(hjŒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K0hjˆ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hX&  The regular read/write commands can be issued in parallel with
BRA transfers. This is convenient to e.g. deal with alerts, jack
detection or change the volume during firmware download, but
accessing the same address with two independent protocols has to
be avoided to avoid undefined behavior.
”h]”hÉ)”}”(hX%  The regular read/write commands can be issued in parallel with
BRA transfers. This is convenient to e.g. deal with alerts, jack
detection or change the volume during firmware download, but
accessing the same address with two independent protocols has to
be avoided to avoid undefined behavior.”h]”hX%  The regular read/write commands can be issued in parallel with
BRA transfers. This is convenient to e.g. deal with alerts, jack
detection or change the volume during firmware download, but
accessing the same address with two independent protocols has to
be avoided to avoid undefined behavior.”…””}”(hj¤  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K4hj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒáSome implementations may not be capable of handling the
bandwidth of the BRA protocol, e.g. in the case of a slow I2C
bus behind the SoundWire IP. In this case, the transfers may
need to be spaced in time or flow-controlled.
”h]”hÉ)”}”(hŒàSome implementations may not be capable of handling the
bandwidth of the BRA protocol, e.g. in the case of a slow I2C
bus behind the SoundWire IP. In this case, the transfers may
need to be spaced in time or flow-controlled.”h]”hŒàSome implementations may not be capable of handling the
bandwidth of the BRA protocol, e.g. in the case of a slow I2C
bus behind the SoundWire IP. In this case, the transfers may
need to be spaced in time or flow-controlled.”…””}”(hj¼  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K:hj¸  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hXn  Each BRA packet SHALL be marked as 'Active' when valid data is
to be transmitted. This allows for software to allocate a BRA
stream but not transmit/discard data while processing the
results or preparing the next batch of data, or allowing the
peripheral to deal with the previous transfer. In addition BRA
transfer can be started early on without data being ready.
”h]”hÉ)”}”(hXm  Each BRA packet SHALL be marked as 'Active' when valid data is
to be transmitted. This allows for software to allocate a BRA
stream but not transmit/discard data while processing the
results or preparing the next batch of data, or allowing the
peripheral to deal with the previous transfer. In addition BRA
transfer can be started early on without data being ready.”h]”hXq  Each BRA packet SHALL be marked as â€˜Activeâ€™ when valid data is
to be transmitted. This allows for software to allocate a BRA
stream but not transmit/discard data while processing the
results or preparing the next batch of data, or allowing the
peripheral to deal with the previous transfer. In addition BRA
transfer can be started early on without data being ready.”…””}”(hjÔ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K?hjÐ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒ.Up to 470 bytes may be transmitted per frame.
”h]”hÉ)”}”(hŒ-Up to 470 bytes may be transmitted per frame.”h]”hŒ-Up to 470 bytes may be transmitted per frame.”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KFhjè  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubj'  )”}”(hŒŽThe address is represented with 32 bits and does not rely on
the paging registers used for the regular command/control
protocol in Column 0.

”h]”hÉ)”}”(hŒŒThe address is represented with 32 bits and does not rely on
the paging registers used for the regular command/control
protocol in Column 0.”h]”hŒŒThe address is represented with 32 bits and does not rely on
the paging registers used for the regular command/control
protocol in Column 0.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KHhj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj#  ubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”Œ(”Œsuffix”Œ)”uh1j!  hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Khhàhžhubeh}”(h]”Œintroduction”ah ]”h"]”Œintroduction”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒError checking”h]”hŒError checking”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj2  hžhhŸh¶h KNubhÉ)”}”(hŒËFirmware download is one of the key usages of the Bulk Register Access
protocol. To make sure the binary data integrity is not compromised by
transmission or programming errors, each BRA packet provides:”h]”hŒËFirmware download is one of the key usages of the Bulk Register Access
protocol. To make sure the binary data integrity is not compromised by
transmission or programming errors, each BRA packet provides:”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KPhj2  hžhubj  )”}”(hX`  (1) A CRC on the 7-byte header. This CRC helps the Peripheral Device
    check if it is addressed and set the start address and number of
    bytes. The Peripheral Device provides a response in Byte 7.

(2) A CRC on the data block (header excluded). This CRC is
    transmitted as the last-but-one byte in the packet, prior to the
    footer response.
”h]”j"  )”}”(hhh]”(j'  )”}”(hŒ¾A CRC on the 7-byte header. This CRC helps the Peripheral Device
check if it is addressed and set the start address and number of
bytes. The Peripheral Device provides a response in Byte 7.
”h]”hÉ)”}”(hŒ½A CRC on the 7-byte header. This CRC helps the Peripheral Device
check if it is addressed and set the start address and number of
bytes. The Peripheral Device provides a response in Byte 7.”h]”hŒ½A CRC on the 7-byte header. This CRC helps the Peripheral Device
check if it is addressed and set the start address and number of
bytes. The Peripheral Device provides a response in Byte 7.”…””}”(hj\  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KThjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjU  ubj'  )”}”(hŒ‰A CRC on the data block (header excluded). This CRC is
transmitted as the last-but-one byte in the packet, prior to the
footer response.
”h]”hÉ)”}”(hŒˆA CRC on the data block (header excluded). This CRC is
transmitted as the last-but-one byte in the packet, prior to the
footer response.”h]”hŒˆA CRC on the data block (header excluded). This CRC is
transmitted as the last-but-one byte in the packet, prior to the
footer response.”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KXhjp  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjU  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j   j!  j"  j#  uh1j!  hjQ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h KThj2  hžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒAThe header response can be one of:
(a) Ack
(b) Nak
(c) Not Ready
”h]”(hŒterm”“”)”}”(hŒ"The header response can be one of:”h]”hŒ"The header response can be one of:”…””}”(hj¡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸ  hŸh¶h K_hj›  ubhŒ
definition”“”)”}”(hhh]”j"  )”}”(hhh]”(j'  )”}”(hŒAck”h]”hÉ)”}”(hj¹  h]”hŒAck”…””}”(hj»  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K]hj·  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj´  ubj'  )”}”(hŒNak”h]”hÉ)”}”(hjÐ  h]”hŒNak”…””}”(hjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K^hjÎ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj´  ubj'  )”}”(hŒ
Not Ready
”h]”hÉ)”}”(hŒ	Not Ready”h]”hŒ	Not Ready”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K_hjå  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj´  ubeh}”(h]”h ]”h"]”h$]”h&]”j  Œ
loweralpha”j   j!  j"  j#  uh1j!  hj±  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¯  hj›  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j™  hŸh¶h K_hj–  ubjš  )”}”(hŒ}The footer response can be one of:
(1) Ack
(2) Nak  (CRC failure)
(3) Good (operation completed)
(4) Bad  (operation failed)
”h]”(j   )”}”(hŒ"The footer response can be one of:”h]”hŒ"The footer response can be one of:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸ  hŸh¶h Kehj  ubj°  )”}”(hhh]”j"  )”}”(hhh]”(j'  )”}”(hŒAck”h]”hÉ)”}”(hj*  h]”hŒAck”…””}”(hj,  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kbhj(  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj%  ubj'  )”}”(hŒNak  (CRC failure)”h]”hÉ)”}”(hjA  h]”hŒNak  (CRC failure)”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kchj?  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj%  ubj'  )”}”(hŒGood (operation completed)”h]”hÉ)”}”(hjX  h]”hŒGood (operation completed)”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KdhjV  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj%  ubj'  )”}”(hŒBad  (operation failed)
”h]”hÉ)”}”(hŒBad  (operation failed)”h]”hŒBad  (operation failed)”…””}”(hjq  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kehjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj%  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j   j!  j"  j#  uh1j!  hj"  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¯  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j™  hŸh¶h Kehj–  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j”  hj2  hžhhŸNh Nubeh}”(h]”Œerror-checking”ah ]”h"]”Œerror checking”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KNubh¢)”}”(hhh]”(h§)”}”(hŒExample frame”h]”hŒExample frame”…””}”(hj¨  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¥  hžhhŸh¶h KhubhÉ)”}”(hŒÊThe example below is not to scale and makes simplifying assumptions
for clarity. The different chunks in the BRA packets are not required
to start on a new SoundWire Row, and the scale of data may vary.”h]”hŒÊThe example below is not to scale and makes simplifying assumptions
for clarity. The different chunks in the BRA packets are not required
to start on a new SoundWire Row, and the scale of data may vary.”…””}”(hj¶  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kjhj¥  hžhubj  )”}”(hX)  ::

  +---+--------------------------------------------+
  +   |                                            |
  +   |             BRA HEADER                     |
  +   |                                            |
  +   +--------------------------------------------+
  + C |             HEADER CRC                     |
  + O +--------------------------------------------+
  + M |             HEADER RESPONSE                |
  + M +--------------------------------------------+
  + A |                                            |
  + N |                                            |
  + D |                 DATA                       |
  +   |                                            |
  +   |                                            |
  +   |                                            |
  +   +--------------------------------------------+
  +   |             DATA CRC                       |
  +   +--------------------------------------------+
  +   |             FOOTER RESPONSE                |
  +---+--------------------------------------------+

”h]”hŒliteral_block”“”)”}”(hXû  +---+--------------------------------------------+
+   |                                            |
+   |             BRA HEADER                     |
+   |                                            |
+   +--------------------------------------------+
+ C |             HEADER CRC                     |
+ O +--------------------------------------------+
+ M |             HEADER RESPONSE                |
+ M +--------------------------------------------+
+ A |                                            |
+ N |                                            |
+ D |                 DATA                       |
+   |                                            |
+   |                                            |
+   |                                            |
+   +--------------------------------------------+
+   |             DATA CRC                       |
+   +--------------------------------------------+
+   |             FOOTER RESPONSE                |
+---+--------------------------------------------+”h]”hXû  +---+--------------------------------------------+
+   |                                            |
+   |             BRA HEADER                     |
+   |                                            |
+   +--------------------------------------------+
+ C |             HEADER CRC                     |
+ O +--------------------------------------------+
+ M |             HEADER RESPONSE                |
+ M +--------------------------------------------+
+ A |                                            |
+ N |                                            |
+ D |                 DATA                       |
+   |                                            |
+   |                                            |
+   |                                            |
+   +--------------------------------------------+
+   |             DATA CRC                       |
+   +--------------------------------------------+
+   |             FOOTER RESPONSE                |
+---+--------------------------------------------+”…””}”hjÊ  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jÈ  hŸh¶h KphjÄ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Knhj¥  hžhubhÉ)”}”(hŒsAssuming the frame uses N columns, the configuration shown above can
be programmed by setting the DP0 registers as:”h]”hŒsAssuming the frame uses N columns, the configuration shown above can
be programmed by setting the DP0 registers as:”…””}”(hjà  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K†hj¥  hžhubj  )”}”(hŒJ- HSTART = 1
- HSTOP = N - 1
- Sampling Interval = N
- WordLength = N - 1
”h]”hŒbullet_list”“”)”}”(hhh]”(j'  )”}”(hŒ
HSTART = 1”h]”hÉ)”}”(hjù  h]”hŒ
HSTART = 1”…””}”(hjû  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K‰hj÷  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjô  ubj'  )”}”(hŒHSTOP = N - 1”h]”hÉ)”}”(hj  h]”hŒHSTOP = N - 1”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KŠhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjô  ubj'  )”}”(hŒSampling Interval = N”h]”hÉ)”}”(hj'  h]”hŒSampling Interval = N”…””}”(hj)  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K‹hj%  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjô  ubj'  )”}”(hŒWordLength = N - 1
”h]”hÉ)”}”(hŒWordLength = N - 1”h]”hŒWordLength = N - 1”…””}”(hj@  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KŒhj<  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjô  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jò  hŸh¶h K‰hjî  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h K‰hj¥  hžhubeh}”(h]”Œexample-frame”ah ]”h"]”Œexample frame”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Khubh¢)”}”(hhh]”(h§)”}”(hŒAddressing restrictions”h]”hŒAddressing restrictions”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjj  hžhhŸh¶h KubhÉ)”}”(hX‹  The Device Number specified in the Header follows the SoundWire
definitions, and broadcast and group addressing are permitted. For now
the Linux implementation only allows for a single BPT transfer to a
single device at a time. This might be revisited at a later point as
an optimization to send the same firmware to multiple devices, but
this would only be beneficial for single-link solutions.”h]”hX‹  The Device Number specified in the Header follows the SoundWire
definitions, and broadcast and group addressing are permitted. For now
the Linux implementation only allows for a single BPT transfer to a
single device at a time. This might be revisited at a later point as
an optimization to send the same firmware to multiple devices, but
this would only be beneficial for single-link solutions.”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K‘hjj  hžhubhÉ)”}”(hX  In the case of multiple Peripheral devices attached to different
Managers, the broadcast and group addressing is not supported by the
SoundWire specification. Each device must be handled with separate BRA
streams, possibly in parallel - the links are really independent.”h]”hX  In the case of multiple Peripheral devices attached to different
Managers, the broadcast and group addressing is not supported by the
SoundWire specification. Each device must be handled with separate BRA
streams, possibly in parallel - the links are really independent.”…””}”(hj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K˜hjj  hžhubeh}”(h]”Œaddressing-restrictions”ah ]”h"]”Œaddressing restrictions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒUnsupported features”h]”hŒUnsupported features”…””}”(hj¢  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjŸ  hžhhŸh¶h KžubhÉ)”}”(hŒ‚The Bulk Register Access specification provides a number of
capabilities that are not supported in known implementations, such as:”h]”hŒ‚The Bulk Register Access specification provides a number of
capabilities that are not supported in known implementations, such as:”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K hjŸ  hžhubj  )”}”(hX  (1) Transfers initiated by a Peripheral Device. The BRA Initiator is
    always the Manager Device.

(2) Flow-control capabilities and retransmission based on the
    'NotReady' header response require extra buffering in the
    SoundWire IP and are not implemented.
”h]”j"  )”}”(hhh]”(j'  )”}”(hŒ\Transfers initiated by a Peripheral Device. The BRA Initiator is
always the Manager Device.
”h]”hÉ)”}”(hŒ[Transfers initiated by a Peripheral Device. The BRA Initiator is
always the Manager Device.”h]”hŒ[Transfers initiated by a Peripheral Device. The BRA Initiator is
always the Manager Device.”…””}”(hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K£hjÅ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjÂ  ubj'  )”}”(hŒšFlow-control capabilities and retransmission based on the
'NotReady' header response require extra buffering in the
SoundWire IP and are not implemented.
”h]”hÉ)”}”(hŒ™Flow-control capabilities and retransmission based on the
'NotReady' header response require extra buffering in the
SoundWire IP and are not implemented.”h]”hŒFlow-control capabilities and retransmission based on the
â€˜NotReadyâ€™ header response require extra buffering in the
SoundWire IP and are not implemented.”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K¦hjÝ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjÂ  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j   j!  j"  j#  uh1j!  hj¾  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h K£hjŸ  hžhubeh}”(h]”Œunsupported-features”ah ]”h"]”Œunsupported features”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kžubh¢)”}”(hhh]”(h§)”}”(hŒBi-directional handling”h]”hŒBi-directional handling”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj	  hžhhŸh¶h K«ubhÉ)”}”(hXf  The BRA protocol can handle writes as well as reads, and in each
packet the header and footer response are provided by the Peripheral
Target device. On the Peripheral device, the BRA protocol is handled
by a single DP0 data port, and at the low-level the bus ownership can
will change for header/footer response as well as the data transmitted
during a read.”h]”hXf  The BRA protocol can handle writes as well as reads, and in each
packet the header and footer response are provided by the Peripheral
Target device. On the Peripheral device, the BRA protocol is handled
by a single DP0 data port, and at the low-level the bus ownership can
will change for header/footer response as well as the data transmitted
during a read.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K­hj	  hžhubhÉ)”}”(hXS  On the host side, most implementations rely on a Port-like concept,
with two FIFOs consuming/generating data transfers in parallel
(Host->Peripheral and Peripheral->Host). The amount of data
consumed/produced by these FIFOs is not symmetrical, as a result
hardware typically inserts markers to help software and hardware
interpret raw data”h]”hXS  On the host side, most implementations rely on a Port-like concept,
with two FIFOs consuming/generating data transfers in parallel
(Host->Peripheral and Peripheral->Host). The amount of data
consumed/produced by these FIFOs is not symmetrical, as a result
hardware typically inserts markers to help software and hardware
interpret raw data”…””}”(hj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K´hj	  hžhubhÉ)”}”(hŒ Each packet will typically have:”h]”hŒ Each packet will typically have:”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K»hj	  hžhubj  )”}”(hŒ¸(1) a 'Start of Packet' indicator.

(2) an 'End of Packet' indicator.

(3) a packet identifier to correlate the data requested and
    transmitted, and the error status for each frame
”h]”j"  )”}”(hhh]”(j'  )”}”(hŒa 'Start of Packet' indicator.
”h]”hÉ)”}”(hŒa 'Start of Packet' indicator.”h]”hŒ"a â€˜Start of Packetâ€™ indicator.”…””}”(hjO  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K½hjK  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjH  ubj'  )”}”(hŒan 'End of Packet' indicator.
”h]”hÉ)”}”(hŒan 'End of Packet' indicator.”h]”hŒ!an â€˜End of Packetâ€™ indicator.”…””}”(hjg  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h K¿hjc  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjH  ubj'  )”}”(hŒia packet identifier to correlate the data requested and
transmitted, and the error status for each frame
”h]”hÉ)”}”(hŒha packet identifier to correlate the data requested and
transmitted, and the error status for each frame”h]”hŒha packet identifier to correlate the data requested and
transmitted, and the error status for each frame”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÁhj{  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjH  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j   j!  j"  j#  uh1j!  hjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h K½hj	  hžhubhÉ)”}”(hXC  Hardware implementations can check errors at the frame level, and
retry a transfer in case of errors. However, as for the flow-control
case, this requires extra buffering and intelligence in the
hardware. The Linux support assumes that the entire transfer is
cancelled if a single error is detected in one of the responses.”h]”hXC  Hardware implementations can check errors at the frame level, and
retry a transfer in case of errors. However, as for the flow-control
case, this requires extra buffering and intelligence in the
hardware. The Linux support assumes that the entire transfer is
cancelled if a single error is detected in one of the responses.”…””}”(hjŸ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÄhj	  hžhubh¢)”}”(hhh]”(h§)”}”(hŒAbstraction required”h]”hŒAbstraction required”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj­  hžhhŸh¶h KËubhÉ)”}”(hŒæThere are no standard registers or mandatory implementation at the
Manager level, so the low-level BPT/BRA details must be hidden in
Manager-specific code. For example the Cadence IP format above is not
known to the codec drivers.”h]”hŒæThere are no standard registers or mandatory implementation at the
Manager level, so the low-level BPT/BRA details must be hidden in
Manager-specific code. For example the Cadence IP format above is not
known to the codec drivers.”…””}”(hj¾  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÍhj­  hžhubhÉ)”}”(hŒ¡Likewise, codec drivers should not have to know the frame size. The
computation of CRC and handling of responses is handled in helpers and
Manager-specific code.”h]”hŒ¡Likewise, codec drivers should not have to know the frame size. The
computation of CRC and handling of responses is handled in helpers and
Manager-specific code.”…””}”(hjÌ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÒhj­  hžhubhÉ)”}”(hX  The host BRA driver may also have restrictions on pages allocated for
DMA, or other host-DSP communication protocols. The codec driver
should not be aware of any of these restrictions, since it might be
reused in combination with different implementations of Manager IPs.”h]”hX  The host BRA driver may also have restrictions on pages allocated for
DMA, or other host-DSP communication protocols. The codec driver
should not be aware of any of these restrictions, since it might be
reused in combination with different implementations of Manager IPs.”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÖhj­  hžhubeh}”(h]”Œabstraction-required”ah ]”h"]”Œabstraction required”ah$]”h&]”uh1h¡hj	  hžhhŸh¶h KËubh¢)”}”(hhh]”(h§)”}”(hŒ.Concurrency between BRA and regular read/write”h]”hŒ.Concurrency between BRA and regular read/write”…””}”(hjó  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjð  hžhhŸh¶h KÜubhÉ)”}”(hŒµThe existing 'nread/nwrite' API already relies on a notion of start
address and number of bytes, so it would be possible to extend this
API with a 'hint' requesting BPT/BRA be used.”h]”hŒ½The existing â€˜nread/nwriteâ€™ API already relies on a notion of start
address and number of bytes, so it would be possible to extend this
API with a â€˜hintâ€™ requesting BPT/BRA be used.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KÞhjð  hžhubhÉ)”}”(hXÊ  However BRA transfers could be quite long, and the use of a single
mutex for regular read/write and BRA is a show-stopper. Independent
operation of the control/command and BRA transfers is a fundamental
requirement, e.g. to change the volume level with the existing regmap
interface while downloading firmware. The integration must however
ensure that there are no concurrent access to the same address with
the command/control protocol and the BRA protocol.”h]”hXÊ  However BRA transfers could be quite long, and the use of a single
mutex for regular read/write and BRA is a show-stopper. Independent
operation of the control/command and BRA transfers is a fundamental
requirement, e.g. to change the volume level with the existing regmap
interface while downloading firmware. The integration must however
ensure that there are no concurrent access to the same address with
the command/control protocol and the BRA protocol.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kâhjð  hžhubhÉ)”}”(hŒàIn addition, the 'sdw_msg' structure hard-codes support for 16-bit
addresses and paging registers which are irrelevant for BPT/BRA
support based on native 32-bit addresses. A separate API with
'sdw_bpt_msg' makes more sense.”h]”hŒèIn addition, the â€˜sdw_msgâ€™ structure hard-codes support for 16-bit
addresses and paging registers which are irrelevant for BPT/BRA
support based on native 32-bit addresses. A separate API with
â€˜sdw_bpt_msgâ€™ makes more sense.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kêhjð  hžhubhÉ)”}”(hX¢  One possible strategy to speed-up all initialization tasks would be to
start a BRA transfer for firmware download, then deal with all the
"regular" read/writes in parallel with the command channel, and last
to wait for the BRA transfers to complete. This would allow for a
degree of overlap instead of a purely sequential solution. As such,
the BRA API must support async transfers and expose a separate wait
function.”h]”hX¦  One possible strategy to speed-up all initialization tasks would be to
start a BRA transfer for firmware download, then deal with all the
â€œregularâ€ read/writes in parallel with the command channel, and last
to wait for the BRA transfers to complete. This would allow for a
degree of overlap instead of a purely sequential solution. As such,
the BRA API must support async transfers and expose a separate wait
function.”…””}”(hj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kïhjð  hžhubeh}”(h]”Œ.concurrency-between-bra-and-regular-read-write”ah ]”h"]”Œ.concurrency between bra and regular read/write”ah$]”h&]”uh1h¡hj	  hžhhŸh¶h KÜubeh}”(h]”Œbi-directional-handling”ah ]”h"]”Œbi-directional handling”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K«ubh¢)”}”(hhh]”(h§)”}”(hŒPeripheral/bus interface”h]”hŒPeripheral/bus interface”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjI  hžhhŸh¶h KùubhÉ)”}”(hŒ7The bus interface for BPT/BRA is made of two functions:”h]”hŒ7The bus interface for BPT/BRA is made of two functions:”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h KûhjI  hžhubj  )”}”(hX   - sdw_bpt_send_async(bpt_message)

   This function sends the data using the Manager
   implementation-defined capabilities (typically DMA or IPC
   protocol).

   Queueing is currently not supported, the caller
   needs to wait for completion of the requested transfer.

- sdw_bpt_wait()

   This function waits for the entire message provided by the
   codec driver in the 'send_async' stage. Intermediate status for
   smaller chunks will not be provided back to the codec driver,
   only a return code will be provided.
”h]”(j  )”}”(hX
  - sdw_bpt_send_async(bpt_message)

  This function sends the data using the Manager
  implementation-defined capabilities (typically DMA or IPC
  protocol).

  Queueing is currently not supported, the caller
  needs to wait for completion of the requested transfer.
”h]”jó  )”}”(hhh]”j'  )”}”(hŒþsdw_bpt_send_async(bpt_message)

This function sends the data using the Manager
implementation-defined capabilities (typically DMA or IPC
protocol).

Queueing is currently not supported, the caller
needs to wait for completion of the requested transfer.
”h]”(hÉ)”}”(hŒsdw_bpt_send_async(bpt_message)”h]”hŒsdw_bpt_send_async(bpt_message)”…””}”(hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kýhjs  ubhÉ)”}”(hŒsThis function sends the data using the Manager
implementation-defined capabilities (typically DMA or IPC
protocol).”h]”hŒsThis function sends the data using the Manager
implementation-defined capabilities (typically DMA or IPC
protocol).”…””}”(hj…  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Kÿhjs  ubhÉ)”}”(hŒgQueueing is currently not supported, the caller
needs to wait for completion of the requested transfer.”h]”hŒgQueueing is currently not supported, the caller
needs to wait for completion of the requested transfer.”…””}”(hj“  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhjs  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j&  hjp  ubah}”(h]”h ]”h"]”h$]”h&]”jZ  j[  uh1jò  hŸh¶h Kýhjl  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Kýhjh  ubjó  )”}”(hhh]”j'  )”}”(hŒòsdw_bpt_wait()

 This function waits for the entire message provided by the
 codec driver in the 'send_async' stage. Intermediate status for
 smaller chunks will not be provided back to the codec driver,
 only a return code will be provided.
”h]”(hÉ)”}”(hŒsdw_bpt_wait()”h]”hŒsdw_bpt_wait()”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhj¶  ubj  )”}”(hŒÞThis function waits for the entire message provided by the
codec driver in the 'send_async' stage. Intermediate status for
smaller chunks will not be provided back to the codec driver,
only a return code will be provided.
”h]”hÉ)”}”(hŒÝThis function waits for the entire message provided by the
codec driver in the 'send_async' stage. Intermediate status for
smaller chunks will not be provided back to the codec driver,
only a return code will be provided.”h]”hŒáThis function waits for the entire message provided by the
codec driver in the â€˜send_asyncâ€™ stage. Intermediate status for
smaller chunks will not be provided back to the codec driver,
only a return code will be provided.”…””}”(hjÌ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h MhjÈ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Mhj¶  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj³  ubah}”(h]”h ]”h"]”h$]”h&]”jZ  j[  uh1jò  hŸh¶h Mhjh  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h KýhjI  hžhubh¢)”}”(hhh]”(h§)”}”(hŒ
Regmap use”h]”hŒ
Regmap use”…””}”(hjõ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjò  hžhhŸh¶h MubhÉ)”}”(hXX  Existing codec drivers rely on regmap to download firmware to
Peripherals. regmap exposes an async interface similar to the
send/wait API suggested above, so at a high-level it would seem
natural to combine BRA and regmap. The regmap layer could check if BRA
is available or not, and use a regular read-write command channel in
the latter case.”h]”hXX  Existing codec drivers rely on regmap to download firmware to
Peripherals. regmap exposes an async interface similar to the
send/wait API suggested above, so at a high-level it would seem
natural to combine BRA and regmap. The regmap layer could check if BRA
is available or not, and use a regular read-write command channel in
the latter case.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhjò  hžhubhÉ)”}”(hŒ8The regmap integration will be handled in a second step.”h]”hŒ8The regmap integration will be handled in a second step.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhjò  hžhubeh}”(h]”Œ
regmap-use”ah ]”h"]”Œ
regmap use”ah$]”h&]”uh1h¡hjI  hžhhŸh¶h Mubeh}”(h]”Œperipheral-bus-interface”ah ]”h"]”Œperipheral/bus interface”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kùubh¢)”}”(hhh]”(h§)”}”(hŒBRA stream model”h]”hŒBRA stream model”…””}”(hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj/  hžhhŸh¶h MubhÉ)”}”(hŒiFor regular audio transfers, the machine driver exposes a dailink
connecting CPU DAI(s) and Codec DAI(s).”h]”hŒiFor regular audio transfers, the machine driver exposes a dailink
connecting CPU DAI(s) and Codec DAI(s).”…””}”(hj@  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhj/  hžhubhÉ)”}”(hŒ'This model is not required BRA support:”h]”hŒ'This model is not required BRA support:”…””}”(hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h Mhj/  hžhubj  )”}”(hX¤  (1) The SoundWire DAIs are mainly wrappers for SoundWire Data
    Ports, with possibly some analog or audio conversion
    capabilities bolted behind the Data Port. In the context of
    BRA, the DP0 is the destination. DP0 registers are standard and
    can be programmed blindly without knowing what Peripheral is
    connected to each link. In addition, if there are multiple
    Peripherals on a link and some of them do not support DP0, the
    write commands to program DP0 registers will generate harmless
    COMMAND_IGNORED responses that will be wired-ORed with
    responses from Peripherals which support DP0. In other words,
    the DP0 programming can be done with broadcast commands, and
    the information on the Target device can be added only in the
    BRA Header.

(2) At the CPU level, the DAI concept is not useful for BRA; the
    machine driver will not create a dailink relying on DP0. The
    only concept that is needed is the notion of port.

(3) The stream concept relies on a set of master_rt and slave_rt
    concepts. All of these entities represent ports and not DAIs.

(4) With the assumption that a single BRA stream is used per link,
    that stream can connect master ports as well as all peripheral
    DP0 ports.

(5) BRA transfers only make sense in the context of one
    Manager/Link, so the BRA stream handling does not rely on the
    concept of multi-link aggregation allowed by regular DAI links.
”h]”j"  )”}”(hhh]”(j'  )”}”(hXÝ  The SoundWire DAIs are mainly wrappers for SoundWire Data
Ports, with possibly some analog or audio conversion
capabilities bolted behind the Data Port. In the context of
BRA, the DP0 is the destination. DP0 registers are standard and
can be programmed blindly without knowing what Peripheral is
connected to each link. In addition, if there are multiple
Peripherals on a link and some of them do not support DP0, the
write commands to program DP0 registers will generate harmless
COMMAND_IGNORED responses that will be wired-ORed with
responses from Peripherals which support DP0. In other words,
the DP0 programming can be done with broadcast commands, and
the information on the Target device can be added only in the
BRA Header.
”h]”hÉ)”}”(hXÜ  The SoundWire DAIs are mainly wrappers for SoundWire Data
Ports, with possibly some analog or audio conversion
capabilities bolted behind the Data Port. In the context of
BRA, the DP0 is the destination. DP0 registers are standard and
can be programmed blindly without knowing what Peripheral is
connected to each link. In addition, if there are multiple
Peripherals on a link and some of them do not support DP0, the
write commands to program DP0 registers will generate harmless
COMMAND_IGNORED responses that will be wired-ORed with
responses from Peripherals which support DP0. In other words,
the DP0 programming can be done with broadcast commands, and
the information on the Target device can be added only in the
BRA Header.”h]”hXÜ  The SoundWire DAIs are mainly wrappers for SoundWire Data
Ports, with possibly some analog or audio conversion
capabilities bolted behind the Data Port. In the context of
BRA, the DP0 is the destination. DP0 registers are standard and
can be programmed blindly without knowing what Peripheral is
connected to each link. In addition, if there are multiple
Peripherals on a link and some of them do not support DP0, the
write commands to program DP0 registers will generate harmless
COMMAND_IGNORED responses that will be wired-ORed with
responses from Peripherals which support DP0. In other words,
the DP0 programming can be done with broadcast commands, and
the information on the Target device can be added only in the
BRA Header.”…””}”(hjg  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h M!hjc  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj`  ubj'  )”}”(hŒ­At the CPU level, the DAI concept is not useful for BRA; the
machine driver will not create a dailink relying on DP0. The
only concept that is needed is the notion of port.
”h]”hÉ)”}”(hŒ¬At the CPU level, the DAI concept is not useful for BRA; the
machine driver will not create a dailink relying on DP0. The
only concept that is needed is the notion of port.”h]”hŒ¬At the CPU level, the DAI concept is not useful for BRA; the
machine driver will not create a dailink relying on DP0. The
only concept that is needed is the notion of port.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h M/hj{  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj`  ubj'  )”}”(hŒ{The stream concept relies on a set of master_rt and slave_rt
concepts. All of these entities represent ports and not DAIs.
”h]”hÉ)”}”(hŒzThe stream concept relies on a set of master_rt and slave_rt
concepts. All of these entities represent ports and not DAIs.”h]”hŒzThe stream concept relies on a set of master_rt and slave_rt
concepts. All of these entities represent ports and not DAIs.”…””}”(hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h M3hj“  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj`  ubj'  )”}”(hŒ‰With the assumption that a single BRA stream is used per link,
that stream can connect master ports as well as all peripheral
DP0 ports.
”h]”hÉ)”}”(hŒˆWith the assumption that a single BRA stream is used per link,
that stream can connect master ports as well as all peripheral
DP0 ports.”h]”hŒˆWith the assumption that a single BRA stream is used per link,
that stream can connect master ports as well as all peripheral
DP0 ports.”…””}”(hj¯  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h M6hj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj`  ubj'  )”}”(hŒ²BRA transfers only make sense in the context of one
Manager/Link, so the BRA stream handling does not rely on the
concept of multi-link aggregation allowed by regular DAI links.
”h]”hÉ)”}”(hŒ±BRA transfers only make sense in the context of one
Manager/Link, so the BRA stream handling does not rely on the
concept of multi-link aggregation allowed by regular DAI links.”h]”hŒ±BRA transfers only make sense in the context of one
Manager/Link, so the BRA stream handling does not rely on the
concept of multi-link aggregation allowed by regular DAI links.”…””}”(hjÇ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h M:hjÃ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j&  hj`  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j   j!  j"  j#  uh1j!  hj\  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h M!hj/  hžhubeh}”(h]”Œbra-stream-model”ah ]”h"]”Œbra stream model”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Mubh¢)”}”(hhh]”(h§)”}”(hŒAudio DMA support”h]”hŒAudio DMA support”…””}”(hjò  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjï  hžhhŸh¶h M?ubhÉ)”}”(hX  Some DMAs, such as HDaudio, require an audio format field to be
set. This format is in turn used to define acceptable bursts. BPT/BRA
support is not fully compatible with these definitions in that the
format and bandwidth may vary between read and write commands.”h]”hX  Some DMAs, such as HDaudio, require an audio format field to be
set. This format is in turn used to define acceptable bursts. BPT/BRA
support is not fully compatible with these definitions in that the
format and bandwidth may vary between read and write commands.”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h MAhjï  hžhubhÉ)”}”(hX¬  In addition, on Intel HDaudio Intel platforms the DMAs need to be
programmed with a PCM format matching the bandwidth of the BPT/BRA
transfer. The format is based on 192kHz 32-bit samples, and the number
of channels varies to adjust the bandwidth. The notion of channel is
completely notional since the data is not typical audio
PCM. Programming such channels helps reserve enough bandwidth and adjust
FIFO sizes to avoid xruns.”h]”hX¬  In addition, on Intel HDaudio Intel platforms the DMAs need to be
programmed with a PCM format matching the bandwidth of the BPT/BRA
transfer. The format is based on 192kHz 32-bit samples, and the number
of channels varies to adjust the bandwidth. The notion of channel is
completely notional since the data is not typical audio
PCM. Programming such channels helps reserve enough bandwidth and adjust
FIFO sizes to avoid xruns.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h MFhjï  hžhubhÉ)”}”(hŒ›Alignment requirements are currently not enforced at the core level
but at the platform-level, e.g. for Intel the data sizes must be
multiples of 32 bytes.”h]”hŒ›Alignment requirements are currently not enforced at the core level
but at the platform-level, e.g. for Intel the data sizes must be
multiples of 32 bytes.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÈhŸh¶h MNhjï  hžhubeh}”(h]”Œaudio-dma-support”ah ]”h"]”Œaudio dma support”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M?ubeh}”(h]”Œbulk-register-access-bra”ah ]”h"]”Œbulk register access (bra)”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j]  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j7  j4  hÝhÚj/  j,  j¢  jŸ  jg  jd  jœ  j™  j  j  jF  jC  jí  jê  j>  j;  j,  j)  j$  j!  jì  jé  j/  j,  uŒ	nametypes”}”(j7  ‰hÝ‰j/  ‰j¢  ‰jg  ‰jœ  ‰j  ‰jF  ‰jí  ‰j>  ‰j,  ‰j$  ‰jì  ‰j/  ‰uh}”(j4  h£hÚh·j,  hàjŸ  j2  jd  j¥  j™  jj  j  jŸ  jC  j	  jê  j­  j;  jð  j)  jI  j!  jò  jé  j/  j,  jï  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.