msphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget-/translations/zh_CN/driver-api/rapidio/tsi721modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/zh_TW/driver-api/rapidio/tsi721modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/it_IT/driver-api/rapidio/tsi721modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ja_JP/driver-api/rapidio/tsi721modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ko_KR/driver-api/rapidio/tsi721modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/sp_SP/driver-api/rapidio/tsi721modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hIRapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.h]hIRapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhG/var/lib/git/docbuild/linux/Documentation/driver-api/rapidio/tsi721.rsthKubh)}(hhh](h)}(h 1. Overviewh]h 1. Overview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThis driver implements all currently defined RapidIO mport callback functions. It supports maintenance read and write operations, inbound and outbound RapidIO doorbells, inbound maintenance port-writes and RapidIO messaging.h]hThis driver implements all currently defined RapidIO mport callback functions. It supports maintenance read and write operations, inbound and outbound RapidIO doorbells, inbound maintenance port-writes and RapidIO messaging.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hTo generate SRIO maintenance transactions this driver uses one of Tsi721 DMA channels. This mechanism provides access to larger range of hop counts and destination IDs without need for changes in outbound window translation.h]hTo generate SRIO maintenance transactions this driver uses one of Tsi721 DMA channels. This mechanism provides access to larger range of hop counts and destination IDs without need for changes in outbound window translation.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hX?RapidIO messaging support uses dedicated messaging channels for each mailbox. For inbound messages this driver uses destination ID matching to forward messages into the corresponding message queue. Messaging callbacks are implemented to be fully compatible with RIONET driver (Ethernet over RapidIO messaging services).h]hX?RapidIO messaging support uses dedicated messaging channels for each mailbox. For inbound messages this driver uses destination ID matching to forward messages into the corresponding message queue. Messaging callbacks are implemented to be fully compatible with RIONET driver (Ethernet over RapidIO messaging services).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhenumerated_list)}(hhh]h list_item)}(hModule parameters: h]h)}(hModule parameters:h]hModule parameters:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubah}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1hhhhhhhhKubh bullet_list)}(hhh](h)}(hX'dbg_level' - This parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of This parameter can be changed bit masks that correspond to the specific functional block. For mask definitions see 'drivers/rapidio/devices/tsi721.h' This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. h]hdefinition_list)}(hhh]hdefinition_list_item)}(hX'dbg_level' - This parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of This parameter can be changed bit masks that correspond to the specific functional block. For mask definitions see 'drivers/rapidio/devices/tsi721.h' This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. h](hterm)}(h 'dbg_level'h]h‘dbg_level’}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhKhj.ubh definition)}(hhh]j)}(hhh]h)}(hXThis parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of This parameter can be changed bit masks that correspond to the specific functional block. For mask definitions see 'drivers/rapidio/devices/tsi721.h' This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. h]h)}(hXThis parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of This parameter can be changed bit masks that correspond to the specific functional block. For mask definitions see 'drivers/rapidio/devices/tsi721.h' This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level.h]hXThis parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of This parameter can be changed bit masks that correspond to the specific functional block. For mask definitions see ‘drivers/rapidio/devices/tsi721.h’ This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1hhjGubah}(h]h ]h"]h$]h&]bullet-uh1jhhhKhjDubah}(h]h ]h"]h$]h&]uh1jBhj.ubeh}(h]h ]h"]h$]h&]uh1j,hhhKhj)ubah}(h]h ]h"]h$]h&]uh1j'hj#ubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubh)}(h'dma_desc_per_channel' - This parameter defines number of hardware buffer descriptors allocated for each registered Tsi721 DMA channel. Its default value is 128. h]j()}(hhh]j-)}(h'dma_desc_per_channel' - This parameter defines number of hardware buffer descriptors allocated for each registered Tsi721 DMA channel. Its default value is 128. h](j3)}(h'dma_desc_per_channel'h]h‘dma_desc_per_channel’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhK#hjubjC)}(hhh]j)}(hhh]h)}(hThis parameter defines number of hardware buffer descriptors allocated for each registered Tsi721 DMA channel. Its default value is 128. h]h)}(hThis parameter defines number of hardware buffer descriptors allocated for each registered Tsi721 DMA channel. Its default value is 128.h]hThis parameter defines number of hardware buffer descriptors allocated for each registered Tsi721 DMA channel. Its default value is 128.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jhjiuh1jhhhK!hjubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1j,hhhK#hjubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubh)}(h'dma_txqueue_sz' - DMA transactions queue size. Defines number of pending transaction requests that can be accepted by each DMA channel. Default value is 16. h]j()}(hhh]j-)}(h'dma_txqueue_sz' - DMA transactions queue size. Defines number of pending transaction requests that can be accepted by each DMA channel. Default value is 16. h](j3)}(h'dma_txqueue_sz'h]h‘dma_txqueue_sz’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhK(hjubjC)}(hhh]j)}(hhh]h)}(hDMA transactions queue size. Defines number of pending transaction requests that can be accepted by each DMA channel. Default value is 16. h]h)}(hDMA transactions queue size. Defines number of pending transaction requests that can be accepted by each DMA channel. Default value is 16.h]hDMA transactions queue size. Defines number of pending transaction requests that can be accepted by each DMA channel. Default value is 16.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jhjiuh1jhhhK&hjubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1j,hhhK(hjubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubh)}(hXf'dma_sel' - DMA channel selection mask. Bitmask that defines which hardware DMA channels (0 ... 6) will be registered with DmaEngine core. If bit is set to 1, the corresponding DMA channel will be registered. DMA channels not selected by this mask will not be used by this device driver. Default value is 0x7f (use all channels). h]j()}(hhh]j-)}(hXR'dma_sel' - DMA channel selection mask. Bitmask that defines which hardware DMA channels (0 ... 6) will be registered with DmaEngine core. If bit is set to 1, the corresponding DMA channel will be registered. DMA channels not selected by this mask will not be used by this device driver. Default value is 0x7f (use all channels). h](j3)}(h 'dma_sel'h]h ‘dma_sel’}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhK/hj3ubjC)}(hhh]j)}(hhh]h)}(hX>DMA channel selection mask. Bitmask that defines which hardware DMA channels (0 ... 6) will be registered with DmaEngine core. If bit is set to 1, the corresponding DMA channel will be registered. DMA channels not selected by this mask will not be used by this device driver. Default value is 0x7f (use all channels). h]h)}(hX=DMA channel selection mask. Bitmask that defines which hardware DMA channels (0 ... 6) will be registered with DmaEngine core. If bit is set to 1, the corresponding DMA channel will be registered. DMA channels not selected by this mask will not be used by this device driver. Default value is 0x7f (use all channels).h]hX=DMA channel selection mask. Bitmask that defines which hardware DMA channels (0 ... 6) will be registered with DmaEngine core. If bit is set to 1, the corresponding DMA channel will be registered. DMA channels not selected by this mask will not be used by this device driver. Default value is 0x7f (use all channels).}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjKubah}(h]h ]h"]h$]h&]uh1hhjHubah}(h]h ]h"]h$]h&]jhjiuh1jhhhK+hjEubah}(h]h ]h"]h$]h&]uh1jBhj3ubeh}(h]h ]h"]h$]h&]uh1j,hhhK/hj0ubah}(h]h ]h"]h$]h&]uh1j'hj,ubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubh)}(hX'pcie_mrrs' - override value for PCIe Maximum Read Request Size (MRRS). This parameter gives an ability to override MRRS value set during PCIe configuration process. Tsi721 supports read request sizes up to 4096B. Value for this parameter must be set as defined by PCIe specification: 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. Default value is '-1' (= keep platform setting). h]j()}(hhh]j-)}(hX'pcie_mrrs' - override value for PCIe Maximum Read Request Size (MRRS). This parameter gives an ability to override MRRS value set during PCIe configuration process. Tsi721 supports read request sizes up to 4096B. Value for this parameter must be set as defined by PCIe specification: 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. Default value is '-1' (= keep platform setting). h](j3)}(h 'pcie_mrrs'h]h‘pcie_mrrs’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhK7hjubjC)}(hhh]j)}(hhh]h)}(hXoverride value for PCIe Maximum Read Request Size (MRRS). This parameter gives an ability to override MRRS value set during PCIe configuration process. Tsi721 supports read request sizes up to 4096B. Value for this parameter must be set as defined by PCIe specification: 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. Default value is '-1' (= keep platform setting). h]h)}(hXoverride value for PCIe Maximum Read Request Size (MRRS). This parameter gives an ability to override MRRS value set during PCIe configuration process. Tsi721 supports read request sizes up to 4096B. Value for this parameter must be set as defined by PCIe specification: 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. Default value is '-1' (= keep platform setting).h]hXoverride value for PCIe Maximum Read Request Size (MRRS). This parameter gives an ability to override MRRS value set during PCIe configuration process. Tsi721 supports read request sizes up to 4096B. Value for this parameter must be set as defined by PCIe specification: 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. Default value is ‘-1’ (= keep platform setting).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jhjiuh1jhhhK2hjubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1j,hhhK7hjubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubh)}(hX,'mbox_sel' - RIO messaging MBOX selection mask. This is a bitmask that defines messaging MBOXes are managed by this device driver. Mask bits 0 - 3 correspond to MBOX0 - MBOX3. MBOX is under driver's control if the corresponding bit is set to '1'. Default value is 0x0f (= all). h]j()}(hhh]j-)}(hX'mbox_sel' - RIO messaging MBOX selection mask. This is a bitmask that defines messaging MBOXes are managed by this device driver. Mask bits 0 - 3 correspond to MBOX0 - MBOX3. MBOX is under driver's control if the corresponding bit is set to '1'. Default value is 0x0f (= all). h](j3)}(h 'mbox_sel'h]h‘mbox_sel’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhK=hjubjC)}(hhh]j)}(hhh]h)}(hX RIO messaging MBOX selection mask. This is a bitmask that defines messaging MBOXes are managed by this device driver. Mask bits 0 - 3 correspond to MBOX0 - MBOX3. MBOX is under driver's control if the corresponding bit is set to '1'. Default value is 0x0f (= all). h]h)}(hXRIO messaging MBOX selection mask. This is a bitmask that defines messaging MBOXes are managed by this device driver. Mask bits 0 - 3 correspond to MBOX0 - MBOX3. MBOX is under driver's control if the corresponding bit is set to '1'. Default value is 0x0f (= all).h]hXRIO messaging MBOX selection mask. This is a bitmask that defines messaging MBOXes are managed by this device driver. Mask bits 0 - 3 correspond to MBOX0 - MBOX3. MBOX is under driver’s control if the corresponding bit is set to ‘1’. Default value is 0x0f (= all).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jhjiuh1jhhhK:hjubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1j,hhhK=hjubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubeh}(h]h ]h"]h$]h&]jhjiuh1jhhhKhhhhubeh}(h]overviewah ]h"] 1. overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h2. Known problemsh]h2. Known problems}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhK@ubh block_quote)}(hNone. h]h)}(hNone.h]hNone.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjLubah}(h]h ]h"]h$]h&]uh1jJhhhKBhj9hhubeh}(h]known-problemsah ]h"]2. known problemsah$]h&]uh1hhhhhhhhK@ubh)}(hhh](h)}(h3. DMA Engine Supporth]h3. DMA Engine Support}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhhhhhKEubh)}(hTsi721 mport driver supports DMA data transfers between local system memory and remote RapidIO devices. This functionality is implemented according to SLAVE mode API defined by common Linux kernel DMA Engine framework.h]hTsi721 mport driver supports DMA data transfers between local system memory and remote RapidIO devices. This functionality is implemented according to SLAVE mode API defined by common Linux kernel DMA Engine framework.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjlhhubh)}(hX3Depending on system requirements RapidIO DMA operations can be included/excluded by setting CONFIG_RAPIDIO_DMA_ENGINE option. Tsi721 miniport driver uses seven out of eight available BDMA channels to support DMA data transfers. One BDMA channel is reserved for generation of maintenance read/write requests.h]hX3Depending on system requirements RapidIO DMA operations can be included/excluded by setting CONFIG_RAPIDIO_DMA_ENGINE option. Tsi721 miniport driver uses seven out of eight available BDMA channels to support DMA data transfers. One BDMA channel is reserved for generation of maintenance read/write requests.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjlhhubh)}(hIf Tsi721 mport driver have been built with RAPIDIO_DMA_ENGINE support included, this driver will accept DMA-specific module parameter:h]hIf Tsi721 mport driver have been built with RAPIDIO_DMA_ENGINE support included, this driver will accept DMA-specific module parameter:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjlhhubjK)}(h"dma_desc_per_channel" - defines number of hardware buffer descriptors used by each BDMA channel of Tsi721 (by default - 128). h]j()}(hhh]j-)}(h"dma_desc_per_channel" - defines number of hardware buffer descriptors used by each BDMA channel of Tsi721 (by default - 128). h](j3)}(h"dma_desc_per_channel"h]h“dma_desc_per_channel”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j2hhhKUhjubjC)}(hhh]j)}(hhh]h)}(hfdefines number of hardware buffer descriptors used by each BDMA channel of Tsi721 (by default - 128). h]h)}(hedefines number of hardware buffer descriptors used by each BDMA channel of Tsi721 (by default - 128).h]hedefines number of hardware buffer descriptors used by each BDMA channel of Tsi721 (by default - 128).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jhjiuh1jhhhKThjubah}(h]h ]h"]h$]h&]uh1jBhjubeh}(h]h ]h"]h$]h&]uh1j,hhhKUhjubah}(h]h ]h"]h$]h&]uh1j'hjubah}(h]h ]h"]h$]h&]uh1jJhhhKShjlhhubh)}(hhh]h)}(hVersion History h]h)}(hVersion Historyh]hVersion History}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubah}(h]h ]h"]h$]h&]jjjhjjstartKuh1hhjlhhhhhKWubjK)}(hX6===== ==================================================================== 1.1.0 DMA operations re-worked to support data scatter/gather lists larger than hardware buffer descriptors ring. 1.0.0 Initial driver release. ===== ==================================================================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j,hj)ubj-)}(hhh]h}(h]h ]h"]h$]h&]colwidthKDuh1j,hj)ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h1.1.0h]h1.1.0}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjNubah}(h]h ]h"]h$]h&]uh1jLhjIubjM)}(hhh]h)}(hkDMA operations re-worked to support data scatter/gather lists larger than hardware buffer descriptors ring.h]hkDMA operations re-worked to support data scatter/gather lists larger than hardware buffer descriptors ring.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjeubah}(h]h ]h"]h$]h&]uh1jLhjIubeh}(h]h ]h"]h$]h&]uh1jGhjDubjH)}(hhh](jM)}(hhh]h)}(h1.0.0h]h1.0.0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jLhjubjM)}(hhh]h)}(hInitial driver release.h]hInitial driver release.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubah}(h]h ]h"]h$]h&]uh1jLhjubeh}(h]h ]h"]h$]h&]uh1jGhjDubeh}(h]h ]h"]h$]h&]uh1jBhj)ubeh}(h]h ]h"]h$]h&]colsKuh1j'hj$ubah}(h]h ]h"]h$]h&]uh1j"hjubah}(h]h ]h"]h$]h&]uh1jJhhhKYhjlhhubeh}(h]dma-engine-supportah ]h"]3. dma engine supportah$]h&]uh1hhhhhhhhKEubh)}(hhh](h)}(h 5. Licenseh]h 5. License}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK`ubjK)}(hXCopyright(c) 2011 Integrated Device Technology, Inc. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.h](h)}(hICopyright(c) 2011 Integrated Device Technology, Inc. All rights reserved.h]hICopyright(c) 2011 Integrated Device Technology, Inc. All rights reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjubh)}(hThis program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.h]hThis program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubh)}(hThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.h]hThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubh)}(hYou should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.h]hYou should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubeh}(h]h ]h"]h$]h&]uh1jJhhhKbhjhhubeh}(h]licenseah ]h"] 5. licenseah$]h&]uh1hhhhhhhhK`ubeh}(h]Hrapidio-subsystem-mport-driver-for-idt-tsi721-pci-express-to-srio-bridgeah ]h"]Irapidio subsystem mport driver for idt tsi721 pci express-to-srio bridge.ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjLfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj_error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j:j7j6j3jijfjjj2j/u nametypes}(j:j6jijj2uh}(j7hj3hjfj9jjlj/ju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]hsystem_message)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "4" (ordinal 4)h]h>Enumerated list start value not ordinal-1: “4” (ordinal 4)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1jhjlhhhhhKWubatransform_messages] transformerN include_log] decorationNhhub.