€•Ì      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ"/translations/zh_CN/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/zh_TW/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/it_IT/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ja_JP/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ko_KR/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/sp_SP/driver-api/ptp”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒ</var/lib/git/docbuild/linux/Documentation/driver-api/ptp.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ+PTP hardware clock infrastructure for Linux”h]”hŒ+PTP hardware clock infrastructure for Linux”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒblock_quote”“”)”}”(hXB  This patch set introduces support for IEEE 1588 PTP clocks in
Linux. Together with the SO_TIMESTAMPING socket options, this
presents a standardized method for developing PTP user space
programs, synchronizing Linux with external clocks, and using the
ancillary features of PTP hardware clocks.

A new class driver exports a kernel interface for specific clock
drivers and a user space interface. The infrastructure supports a
complete set of PTP hardware clock functionality.

+ Basic clock operations
  - Set time
  - Get time
  - Shift the clock by a given offset atomically
  - Adjust clock frequency

+ Ancillary clock features
  - Time stamp external events
  - Period output signals configurable from user space
  - Low Pass Filter (LPF) access from user space
  - Synchronization of the Linux system time via the PPS subsystem
”h]”(hŒ	paragraph”“”)”}”(hX%  This patch set introduces support for IEEE 1588 PTP clocks in
Linux. Together with the SO_TIMESTAMPING socket options, this
presents a standardized method for developing PTP user space
programs, synchronizing Linux with external clocks, and using the
ancillary features of PTP hardware clocks.”h]”hX%  This patch set introduces support for IEEE 1588 PTP clocks in
Linux. Together with the SO_TIMESTAMPING socket options, this
presents a standardized method for developing PTP user space
programs, synchronizing Linux with external clocks, and using the
ancillary features of PTP hardware clocks.”…””}”(hhÑhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KhhËubhÐ)”}”(hŒ´A new class driver exports a kernel interface for specific clock
drivers and a user space interface. The infrastructure supports a
complete set of PTP hardware clock functionality.”h]”hŒ´A new class driver exports a kernel interface for specific clock
drivers and a user space interface. The infrastructure supports a
complete set of PTP hardware clock functionality.”…””}”(hhßhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KhhËubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒuBasic clock operations
- Set time
- Get time
- Shift the clock by a given offset atomically
- Adjust clock frequency
”h]”hÐ)”}”(hŒtBasic clock operations
- Set time
- Get time
- Shift the clock by a given offset atomically
- Adjust clock frequency”h]”hŒtBasic clock operations
- Set time
- Get time
- Shift the clock by a given offset atomically
- Adjust clock frequency”…””}”(hhøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Khhôubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïubhó)”}”(hŒÛAncillary clock features
- Time stamp external events
- Period output signals configurable from user space
- Low Pass Filter (LPF) access from user space
- Synchronization of the Linux system time via the PPS subsystem
”h]”hÐ)”}”(hŒÚAncillary clock features
- Time stamp external events
- Period output signals configurable from user space
- Low Pass Filter (LPF) access from user space
- Synchronization of the Linux system time via the PPS subsystem”h]”hŒÚAncillary clock features
- Time stamp external events
- Period output signals configurable from user space
- Low Pass Filter (LPF) access from user space
- Synchronization of the Linux system time via the PPS subsystem”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ+”uh1híhŸh³h KhhËubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒPTP hardware clock kernel API”h]”hŒPTP hardware clock kernel API”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj2  hžhhŸh³h KubhÊ)”}”(hXa  A PTP clock driver registers itself with the class driver. The
class driver handles all of the dealings with user space. The
author of a clock driver need only implement the details of
programming the clock hardware. The clock driver notifies the class
driver of asynchronous events (alarms and external time stamps) via
a simple message passing interface.

The class driver supports multiple PTP clock drivers. In normal use
cases, only one PTP clock is needed. However, for testing and
development, it can be useful to have more than one clock in a
single system, in order to allow performance comparisons.
”h]”(hÐ)”}”(hXd  A PTP clock driver registers itself with the class driver. The
class driver handles all of the dealings with user space. The
author of a clock driver need only implement the details of
programming the clock hardware. The clock driver notifies the class
driver of asynchronous events (alarms and external time stamps) via
a simple message passing interface.”h]”hXd  A PTP clock driver registers itself with the class driver. The
class driver handles all of the dealings with user space. The
author of a clock driver need only implement the details of
programming the clock hardware. The clock driver notifies the class
driver of asynchronous events (alarms and external time stamps) via
a simple message passing interface.”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K hjC  ubhÐ)”}”(hŒúThe class driver supports multiple PTP clock drivers. In normal use
cases, only one PTP clock is needed. However, for testing and
development, it can be useful to have more than one clock in a
single system, in order to allow performance comparisons.”h]”hŒúThe class driver supports multiple PTP clock drivers. In normal use
cases, only one PTP clock is needed. However, for testing and
development, it can be useful to have more than one clock in a
single system, in order to allow performance comparisons.”…””}”(hjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K'hjC  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hj2  hžhubeh}”(h]”Œptp-hardware-clock-kernel-api”ah ]”h"]”Œptp hardware clock kernel api”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒ!PTP hardware clock user space API”h]”hŒ!PTP hardware clock user space API”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjq  hžhhŸh³h K-ubhÊ)”}”(hXù  The class driver also creates a character device for each
registered clock. User space can use an open file descriptor from
the character device as a POSIX clock id and may call
clock_gettime, clock_settime, and clock_adjtime.  These calls
implement the basic clock operations.

User space programs may control the clock using standardized
ioctls. A program may query, enable, configure, and disable the
ancillary clock features. User space can receive time stamped
events via blocking read() and poll().
”h]”(hÐ)”}”(hX  The class driver also creates a character device for each
registered clock. User space can use an open file descriptor from
the character device as a POSIX clock id and may call
clock_gettime, clock_settime, and clock_adjtime.  These calls
implement the basic clock operations.”h]”hX  The class driver also creates a character device for each
registered clock. User space can use an open file descriptor from
the character device as a POSIX clock id and may call
clock_gettime, clock_settime, and clock_adjtime.  These calls
implement the basic clock operations.”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K/hj‚  ubhÐ)”}”(hŒáUser space programs may control the clock using standardized
ioctls. A program may query, enable, configure, and disable the
ancillary clock features. User space can receive time stamped
events via blocking read() and poll().”h]”hŒáUser space programs may control the clock using standardized
ioctls. A program may query, enable, configure, and disable the
ancillary clock features. User space can receive time stamped
events via blocking read() and poll().”…””}”(hj”  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K5hj‚  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K/hjq  hžhubeh}”(h]”Œ!ptp-hardware-clock-user-space-api”ah ]”h"]”Œ!ptp hardware clock user space api”ah$]”h&]”uh1h´hh¶hžhhŸh³h K-ubhµ)”}”(hhh]”(hº)”}”(hŒWriting clock drivers”h]”hŒWriting clock drivers”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj°  hžhhŸh³h K;ubhÊ)”}”(hXø  Clock drivers include include/linux/ptp_clock_kernel.h and register
themselves by presenting a 'struct ptp_clock_info' to the
registration method. Clock drivers must implement all of the
functions in the interface. If a clock does not offer a particular
ancillary feature, then the driver should just return -EOPNOTSUPP
from those functions.

Drivers must ensure that all of the methods in interface are
reentrant. Since most hardware implementations treat the time value
as a 64 bit integer accessed as two 32 bit registers, drivers
should use spin_lock_irqsave/spin_unlock_irqrestore to protect
against concurrent access. This locking cannot be accomplished in
class driver, since the lock may also be needed by the clock
driver's interrupt service routine.
”h]”(hÐ)”}”(hXU  Clock drivers include include/linux/ptp_clock_kernel.h and register
themselves by presenting a 'struct ptp_clock_info' to the
registration method. Clock drivers must implement all of the
functions in the interface. If a clock does not offer a particular
ancillary feature, then the driver should just return -EOPNOTSUPP
from those functions.”h]”hXY  Clock drivers include include/linux/ptp_clock_kernel.h and register
themselves by presenting a â€˜struct ptp_clock_infoâ€™ to the
registration method. Clock drivers must implement all of the
functions in the interface. If a clock does not offer a particular
ancillary feature, then the driver should just return -EOPNOTSUPP
from those functions.”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K=hjÁ  ubhÐ)”}”(hX   Drivers must ensure that all of the methods in interface are
reentrant. Since most hardware implementations treat the time value
as a 64 bit integer accessed as two 32 bit registers, drivers
should use spin_lock_irqsave/spin_unlock_irqrestore to protect
against concurrent access. This locking cannot be accomplished in
class driver, since the lock may also be needed by the clock
driver's interrupt service routine.”h]”hX¢  Drivers must ensure that all of the methods in interface are
reentrant. Since most hardware implementations treat the time value
as a 64 bit integer accessed as two 32 bit registers, drivers
should use spin_lock_irqsave/spin_unlock_irqrestore to protect
against concurrent access. This locking cannot be accomplished in
class driver, since the lock may also be needed by the clock
driverâ€™s interrupt service routine.”…””}”(hjÓ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KDhjÁ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K=hj°  hžhubhµ)”}”(hhh]”(hº)”}”(hŒ/PTP hardware clock requirements for '.adjphase'”h]”hŒ3PTP hardware clock requirements for â€˜.adjphaseâ€™”…””}”(hjê  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjç  hžhhŸh³h KMubhÊ)”}”(hX2  The 'struct ptp_clock_info' interface has a '.adjphase' function.
This function has a set of requirements from the PHC in order to be
implemented.

  * The PHC implements a servo algorithm internally that is used to
    correct the offset passed in the '.adjphase' call.
  * When other PTP adjustment functions are called, the PHC servo
    algorithm is disabled.

**NOTE:** '.adjphase' is not a simple time adjustment functionality
that 'jumps' the PHC clock time based on the provided offset. It
should correct the offset provided using an internal algorithm.
”h]”(hÐ)”}”(hŒ’The 'struct ptp_clock_info' interface has a '.adjphase' function.
This function has a set of requirements from the PHC in order to be
implemented.”h]”hŒšThe â€˜struct ptp_clock_infoâ€™ interface has a â€˜.adjphaseâ€™ function.
This function has a set of requirements from the PHC in order to be
implemented.”…””}”(hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KOhjø  ubhÊ)”}”(hŒÐ* The PHC implements a servo algorithm internally that is used to
  correct the offset passed in the '.adjphase' call.
* When other PTP adjustment functions are called, the PHC servo
  algorithm is disabled.
”h]”hî)”}”(hhh]”(hó)”}”(hŒrThe PHC implements a servo algorithm internally that is used to
correct the offset passed in the '.adjphase' call.”h]”hÐ)”}”(hŒrThe PHC implements a servo algorithm internally that is used to
correct the offset passed in the '.adjphase' call.”h]”hŒvThe PHC implements a servo algorithm internally that is used to
correct the offset passed in the â€˜.adjphaseâ€™ call.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KShj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒUWhen other PTP adjustment functions are called, the PHC servo
algorithm is disabled.
”h]”hÐ)”}”(hŒTWhen other PTP adjustment functions are called, the PHC servo
algorithm is disabled.”h]”hŒTWhen other PTP adjustment functions are called, the PHC servo
algorithm is disabled.”…””}”(hj-  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KUhj)  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  Œ*”uh1híhŸh³h KShj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KShjø  ubhÐ)”}”(hŒÄ**NOTE:** '.adjphase' is not a simple time adjustment functionality
that 'jumps' the PHC clock time based on the provided offset. It
should correct the offset provided using an internal algorithm.”h]”(hŒstrong”“”)”}”(hŒ	**NOTE:**”h]”hŒNOTE:”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jR  hjN  ubhŒÃ â€˜.adjphaseâ€™ is not a simple time adjustment functionality
that â€˜jumpsâ€™ the PHC clock time based on the provided offset. It
should correct the offset provided using an internal algorithm.”…””}”(hjN  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KXhjø  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KOhjç  hžhubeh}”(h]”Œ,ptp-hardware-clock-requirements-for-adjphase”ah ]”h"]”Œ/ptp hardware clock requirements for '.adjphase'”ah$]”h&]”uh1h´hj°  hžhhŸh³h KMubeh}”(h]”Œwriting-clock-drivers”ah ]”h"]”Œwriting clock drivers”ah$]”h&]”uh1h´hh¶hžhhŸh³h K;ubhµ)”}”(hhh]”(hº)”}”(hŒSupported hardware”h]”hŒSupported hardware”…””}”(hj…  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj‚  hžhhŸh³h K]ubhÊ)”}”(hXö  * Freescale eTSEC gianfar

  - 2 Time stamp external triggers, programmable polarity (opt. interrupt)
  - 2 Alarm registers (optional interrupt)
  - 3 Periodic signals (optional interrupt)

* National DP83640

  - 6 GPIOs programmable as inputs or outputs
  - 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
    used as general inputs or outputs
  - GPIO inputs can time stamp external triggers
  - GPIO outputs can produce periodic signals
  - 1 interrupt pin

* Intel IXP465

  - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
  - Target Time (optional interrupt)

* Renesas (IDT) ClockMatrixâ„¢

  - Up to 4 independent PHC channels
  - Integrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2)
  - Programmable output periodic signals
  - Programmable inputs can time stamp external triggers
  - Driver and/or hardware configuration through firmware (idtcm.bin)
       - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
       - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
       - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)

* NVIDIA Mellanox

  - GPIO
       - Certain variants of ConnectX-6 Dx and later products support one
         GPIO which can time stamp external triggers and one GPIO to produce
         periodic signals.
       - Certain variants of ConnectX-5 and older products support one GPIO,
         configured to either time stamp external triggers or produce
         periodic signals.
  - PHC instances
       - All ConnectX devices have a free-running counter
       - ConnectX-6 Dx and later devices have a UTC format counter”h]”hî)”}”(hhh]”(hó)”}”(hŒµFreescale eTSEC gianfar

- 2 Time stamp external triggers, programmable polarity (opt. interrupt)
- 2 Alarm registers (optional interrupt)
- 3 Periodic signals (optional interrupt)
”h]”(hÐ)”}”(hŒFreescale eTSEC gianfar”h]”hŒFreescale eTSEC gianfar”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K_hjš  ubhî)”}”(hhh]”(hó)”}”(hŒF2 Time stamp external triggers, programmable polarity (opt. interrupt)”h]”hÐ)”}”(hj±  h]”hŒF2 Time stamp external triggers, programmable polarity (opt. interrupt)”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kahj¯  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj¬  ubhó)”}”(hŒ&2 Alarm registers (optional interrupt)”h]”hÐ)”}”(hjÈ  h]”hŒ&2 Alarm registers (optional interrupt)”…””}”(hjÊ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KbhjÆ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj¬  ubhó)”}”(hŒ(3 Periodic signals (optional interrupt)
”h]”hÐ)”}”(hŒ'3 Periodic signals (optional interrupt)”h]”hŒ'3 Periodic signals (optional interrupt)”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KchjÝ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj¬  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  Œ-”uh1híhŸh³h Kahjš  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhj—  ubhó)”}”(hX  National DP83640

- 6 GPIOs programmable as inputs or outputs
- 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
  used as general inputs or outputs
- GPIO inputs can time stamp external triggers
- GPIO outputs can produce periodic signals
- 1 interrupt pin
”h]”(hÐ)”}”(hŒNational DP83640”h]”hŒNational DP83640”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kehj  ubhî)”}”(hhh]”(hó)”}”(hŒ)6 GPIOs programmable as inputs or outputs”h]”hÐ)”}”(hj  h]”hŒ)6 GPIOs programmable as inputs or outputs”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kghj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒ_6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
used as general inputs or outputs”h]”hÐ)”}”(hŒ_6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
used as general inputs or outputs”h]”hŒ_6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
used as general inputs or outputs”…””}”(hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Khhj.  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒ,GPIO inputs can time stamp external triggers”h]”hÐ)”}”(hjH  h]”hŒ,GPIO inputs can time stamp external triggers”…””}”(hjJ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KjhjF  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒ)GPIO outputs can produce periodic signals”h]”hÐ)”}”(hj_  h]”hŒ)GPIO outputs can produce periodic signals”…””}”(hja  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kkhj]  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒ1 interrupt pin
”h]”hÐ)”}”(hŒ1 interrupt pin”h]”hŒ1 interrupt pin”…””}”(hjx  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Klhjt  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Kghj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhj—  ubhó)”}”(hŒmIntel IXP465

- Auxiliary Slave/Master Mode Snapshot (optional interrupt)
- Target Time (optional interrupt)
”h]”(hÐ)”}”(hŒIntel IXP465”h]”hŒIntel IXP465”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Knhj˜  ubhî)”}”(hhh]”(hó)”}”(hŒ9Auxiliary Slave/Master Mode Snapshot (optional interrupt)”h]”hÐ)”}”(hj¯  h]”hŒ9Auxiliary Slave/Master Mode Snapshot (optional interrupt)”…””}”(hj±  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kphj­  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjª  ubhó)”}”(hŒ!Target Time (optional interrupt)
”h]”hÐ)”}”(hŒ Target Time (optional interrupt)”h]”hŒ Target Time (optional interrupt)”…””}”(hjÈ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KqhjÄ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjª  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Kphj˜  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhj—  ubhó)”}”(hX‰  Renesas (IDT) ClockMatrixâ„¢

- Up to 4 independent PHC channels
- Integrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2)
- Programmable output periodic signals
- Programmable inputs can time stamp external triggers
- Driver and/or hardware configuration through firmware (idtcm.bin)
     - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
     - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
     - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
”h]”(hÐ)”}”(hŒRenesas (IDT) ClockMatrixâ„¢”h]”hŒRenesas (IDT) ClockMatrixâ„¢”…””}”(hjì  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kshjè  ubhî)”}”(hhh]”(hó)”}”(hŒ Up to 4 independent PHC channels”h]”hÐ)”}”(hjÿ  h]”hŒ Up to 4 independent PHC channels”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kuhjý  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjú  ubhó)”}”(hŒTIntegrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2)”h]”hÐ)”}”(hj  h]”hŒTIntegrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2)”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kvhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjú  ubhó)”}”(hŒ$Programmable output periodic signals”h]”hÐ)”}”(hj-  h]”hŒ$Programmable output periodic signals”…””}”(hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kwhj+  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjú  ubhó)”}”(hŒ4Programmable inputs can time stamp external triggers”h]”hÐ)”}”(hjD  h]”hŒ4Programmable inputs can time stamp external triggers”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h KxhjB  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjú  ubhó)”}”(hX‹  Driver and/or hardware configuration through firmware (idtcm.bin)
   - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
   - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
   - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
”h]”hŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hX‚  Driver and/or hardware configuration through firmware (idtcm.bin)
- LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
- Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
- Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
”h]”(hŒterm”“”)”}”(hŒADriver and/or hardware configuration through firmware (idtcm.bin)”h]”hŒADriver and/or hardware configuration through firmware (idtcm.bin)”…””}”(hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh  hŸh³h K|hjd  ubhŒ
definition”“”)”}”(hhh]”hî)”}”(hhh]”(hó)”}”(hŒhLPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))”h]”hÐ)”}”(hj‚  h]”hŒhLPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))”…””}”(hj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kzhj€  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj}  ubhó)”}”(hŒuProgrammable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)”h]”hÐ)”}”(hj™  h]”hŒuProgrammable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K{hj—  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj}  ubhó)”}”(hŒ[Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
”h]”hÐ)”}”(hŒZLock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)”h]”hŒZLock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)”…””}”(hj²  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K|hj®  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj}  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Kzhjz  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jx  hjd  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jb  hŸh³h K|hj_  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjY  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjú  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Kuhjè  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhj—  ubhó)”}”(hXô  NVIDIA Mellanox

- GPIO
     - Certain variants of ConnectX-6 Dx and later products support one
       GPIO which can time stamp external triggers and one GPIO to produce
       periodic signals.
     - Certain variants of ConnectX-5 and older products support one GPIO,
       configured to either time stamp external triggers or produce
       periodic signals.
- PHC instances
     - All ConnectX devices have a free-running counter
     - ConnectX-6 Dx and later devices have a UTC format counter”h]”(hÐ)”}”(hŒNVIDIA Mellanox”h]”hŒNVIDIA Mellanox”…””}”(hjô  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K~hjð  ubhî)”}”(hhh]”(hó)”}”(hXL  GPIO
   - Certain variants of ConnectX-6 Dx and later products support one
     GPIO which can time stamp external triggers and one GPIO to produce
     periodic signals.
   - Certain variants of ConnectX-5 and older products support one GPIO,
     configured to either time stamp external triggers or produce
     periodic signals.”h]”j^  )”}”(hhh]”jc  )”}”(hX:  GPIO
- Certain variants of ConnectX-6 Dx and later products support one
  GPIO which can time stamp external triggers and one GPIO to produce
  periodic signals.
- Certain variants of ConnectX-5 and older products support one GPIO,
  configured to either time stamp external triggers or produce
  periodic signals.”h]”(ji  )”}”(hŒGPIO”h]”hŒGPIO”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh  hŸh³h K…hj  ubjy  )”}”(hhh]”hî)”}”(hhh]”(hó)”}”(hŒ–Certain variants of ConnectX-6 Dx and later products support one
GPIO which can time stamp external triggers and one GPIO to produce
periodic signals.”h]”hÐ)”}”(hŒ–Certain variants of ConnectX-6 Dx and later products support one
GPIO which can time stamp external triggers and one GPIO to produce
periodic signals.”h]”hŒ–Certain variants of ConnectX-6 Dx and later products support one
GPIO which can time stamp external triggers and one GPIO to produce
periodic signals.”…””}”(hj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Khj$  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj!  ubhó)”}”(hŒ’Certain variants of ConnectX-5 and older products support one GPIO,
configured to either time stamp external triggers or produce
periodic signals.”h]”hÐ)”}”(hŒ’Certain variants of ConnectX-5 and older products support one GPIO,
configured to either time stamp external triggers or produce
periodic signals.”h]”hŒ’Certain variants of ConnectX-5 and older products support one GPIO,
configured to either time stamp external triggers or produce
periodic signals.”…””}”(hj@  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K„hj<  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj!  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jx  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jb  hŸh³h K…hj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubhó)”}”(hŒ‚PHC instances
   - All ConnectX devices have a free-running counter
   - ConnectX-6 Dx and later devices have a UTC format counter”h]”j^  )”}”(hhh]”jc  )”}”(hŒ|PHC instances
- All ConnectX devices have a free-running counter
- ConnectX-6 Dx and later devices have a UTC format counter”h]”(ji  )”}”(hŒPHC instances”h]”hŒPHC instances”…””}”(hj}  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh  hŸh³h Kˆhjy  ubjy  )”}”(hhh]”hî)”}”(hhh]”(hó)”}”(hŒ0All ConnectX devices have a free-running counter”h]”hÐ)”}”(hj“  h]”hŒ0All ConnectX devices have a free-running counter”…””}”(hj•  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h Kˆhj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjŽ  ubhó)”}”(hŒ9ConnectX-6 Dx and later devices have a UTC format counter”h]”hÐ)”}”(hjª  h]”hŒ9ConnectX-6 Dx and later devices have a UTC format counter”…””}”(hj¬  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÏhŸh³h K‰hj¨  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhjŽ  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h Kˆhj‹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jx  hjy  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jb  hŸh³h Kˆhjv  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j]  hjr  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jû  uh1híhŸh³h K€hjð  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hòhj—  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  jG  uh1híhŸh³h K_hj“  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K_hj‚  hžhubeh}”(h]”Œsupported-hardware”ah ]”h"]”Œsupported hardware”ah$]”h&]”uh1h´hh¶hžhhŸh³h K]ubeh}”(h]”Œ+ptp-hardware-clock-infrastructure-for-linux”ah ]”h"]”Œ+ptp hardware clock infrastructure for linux”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
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