€•3      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”(hhŒparent”hubaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ*/translations/zh_CN/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”(hhhh2ubah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/zh_TW/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”(hhhhFubah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/it_IT/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”(hhhhZubah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ja_JP/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”(hhhhnubah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ko_KR/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”(hhhh‚ubah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/sp_SP/driver-api/pin-control”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒPINCTRL (PIN CONTROL) subsystem”h]”hŒPINCTRL (PIN CONTROL) subsystem”…””}”(hhªhh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒD/var/lib/git/docbuild/linux/Documentation/driver-api/pin-control.rst”h KubhŒ	paragraph”“”)”}”(hŒ9This document outlines the pin control subsystem in Linux”h]”hŒ9This document outlines the pin control subsystem in Linux”…””}”(hh»hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒThis subsystem deals with:”h]”hŒThis subsystem deals with:”…””}”(hhÉhhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ)Enumerating and naming controllable pins
”h]”h¸)”}”(hŒ(Enumerating and naming controllable pins”h]”hŒ(Enumerating and naming controllable pins”…””}”(hhâhhàhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K	hhÜubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhh×hžhhŸh¶h NubhÛ)”}”(hŒ@Multiplexing of pins, pads, fingers (etc) see below for details
”h]”h¸)”}”(hŒ?Multiplexing of pins, pads, fingers (etc) see below for details”h]”hŒ?Multiplexing of pins, pads, fingers (etc) see below for details”…””}”(hhúhhøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhôubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhh×hžhhŸh¶h NubhÛ)”}”(hŒ®Configuration of pins, pads, fingers (etc), such as software-controlled
biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
load capacitance etc.
”h]”h¸)”}”(hŒ­Configuration of pins, pads, fingers (etc), such as software-controlled
biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
load capacitance etc.”h]”hŒ­Configuration of pins, pads, fingers (etc), such as software-controlled
biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
load capacitance etc.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhh×hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hÕhŸh¶h K	hh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒTop-level interface”h]”hŒTop-level interface”…””}”(hj1  hj/  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj,  hžhhŸh¶h Kubh¸)”}”(hŒDefinitions:”h]”hŒDefinitions:”…””}”(hj?  hj=  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj,  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hŒÕA PIN CONTROLLER is a piece of hardware, usually a set of registers, that
can control PINs. It may be able to multiplex, bias, set load capacitance,
set drive strength, etc. for individual pins or groups of pins.
”h]”h¸)”}”(hŒÔA PIN CONTROLLER is a piece of hardware, usually a set of registers, that
can control PINs. It may be able to multiplex, bias, set load capacitance,
set drive strength, etc. for individual pins or groups of pins.”h]”hŒÔA PIN CONTROLLER is a piece of hardware, usually a set of registers, that
can control PINs. It may be able to multiplex, bias, set load capacitance,
set drive strength, etc. for individual pins or groups of pins.”…””}”(hjT  hjR  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjN  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjK  hžhhŸh¶h NubhÛ)”}”(hXx  PINS are equal to pads, fingers, balls or whatever packaging input or
output line you want to control and these are denoted by unsigned integers
in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
there may be several such number spaces in a system. This pin space may
be sparse - i.e. there may be gaps in the space with numbers where no
pin exists.
”h]”h¸)”}”(hXw  PINS are equal to pads, fingers, balls or whatever packaging input or
output line you want to control and these are denoted by unsigned integers
in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
there may be several such number spaces in a system. This pin space may
be sparse - i.e. there may be gaps in the space with numbers where no
pin exists.”h]”hXw  PINS are equal to pads, fingers, balls or whatever packaging input or
output line you want to control and these are denoted by unsigned integers
in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
there may be several such number spaces in a system. This pin space may
be sparse - i.e. there may be gaps in the space with numbers where no
pin exists.”…””}”(hjl  hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjf  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjK  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h Khj,  hžhubh¸)”}”(hŒØWhen a PIN CONTROLLER is instantiated, it will register a descriptor to the
pin control framework, and this descriptor contains an array of pin descriptors
describing the pins handled by this specific pin controller.”h]”hŒØWhen a PIN CONTROLLER is instantiated, it will register a descriptor to the
pin control framework, and this descriptor contains an array of pin descriptors
describing the pins handled by this specific pin controller.”…””}”(hj†  hj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K!hj,  hžhubh¸)”}”(hŒHHere is an example of a PGA (Pin Grid Array) chip seen from underneath::”h]”hŒGHere is an example of a PGA (Pin Grid Array) chip seen from underneath:”…””}”(hŒGHere is an example of a PGA (Pin Grid Array) chip seen from underneath:”hj’  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K%hj,  hžhubhŒliteral_block”“”)”}”(hXB       A   B   C   D   E   F   G   H

8    o   o   o   o   o   o   o   o

7    o   o   o   o   o   o   o   o

6    o   o   o   o   o   o   o   o

5    o   o   o   o   o   o   o   o

4    o   o   o   o   o   o   o   o

3    o   o   o   o   o   o   o   o

2    o   o   o   o   o   o   o   o

1    o   o   o   o   o   o   o   o”h]”hXB       A   B   C   D   E   F   G   H

8    o   o   o   o   o   o   o   o

7    o   o   o   o   o   o   o   o

6    o   o   o   o   o   o   o   o

5    o   o   o   o   o   o   o   o

4    o   o   o   o   o   o   o   o

3    o   o   o   o   o   o   o   o

2    o   o   o   o   o   o   o   o

1    o   o   o   o   o   o   o   o”…””}”(hhhj£  ubah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j¡  hŸh¶h K'hj,  hžhubh¸)”}”(hŒ`To register a pin controller and name all the pins on this package we can do
this in our driver:”h]”hŒ`To register a pin controller and name all the pins on this package we can do
this in our driver:”…””}”(hjµ  hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K9hj,  hžhubj¢  )”}”(hX²  #include <linux/pinctrl/pinctrl.h>

const struct pinctrl_pin_desc foo_pins[] = {
        PINCTRL_PIN(0, "A8"),
        PINCTRL_PIN(1, "B8"),
        PINCTRL_PIN(2, "C8"),
        ...
        PINCTRL_PIN(61, "F1"),
        PINCTRL_PIN(62, "G1"),
        PINCTRL_PIN(63, "H1"),
};

static struct pinctrl_desc foo_desc = {
        .name = "foo",
        .pins = foo_pins,
        .npins = ARRAY_SIZE(foo_pins),
        .owner = THIS_MODULE,
};

int __init foo_init(void)
{
        int error;

        struct pinctrl_dev *pctl;

        error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
        if (error)
                return error;

        return pinctrl_enable(pctl);
}”h]”hX²  #include <linux/pinctrl/pinctrl.h>

const struct pinctrl_pin_desc foo_pins[] = {
        PINCTRL_PIN(0, "A8"),
        PINCTRL_PIN(1, "B8"),
        PINCTRL_PIN(2, "C8"),
        ...
        PINCTRL_PIN(61, "F1"),
        PINCTRL_PIN(62, "G1"),
        PINCTRL_PIN(63, "H1"),
};

static struct pinctrl_desc foo_desc = {
        .name = "foo",
        .pins = foo_pins,
        .npins = ARRAY_SIZE(foo_pins),
        .owner = THIS_MODULE,
};

int __init foo_init(void)
{
        int error;

        struct pinctrl_dev *pctl;

        error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
        if (error)
                return error;

        return pinctrl_enable(pctl);
}”…””}”(hhhjÁ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  Œforce”‰Œlanguage”Œc”Œhighlight_args”}”uh1j¡  hŸh¶h K<hj,  hžhubh¸)”}”(hX  To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
selected drivers, you need to select them from your machine's Kconfig entry,
since these are so tightly integrated with the machines they are used on.
See ``arch/arm/mach-ux500/Kconfig`` for an example.”h]”(hŒêTo enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
selected drivers, you need to select them from your machineâ€™s Kconfig entry,
since these are so tightly integrated with the machines they are used on.
See ”…””}”(hŒèTo enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
selected drivers, you need to select them from your machine's Kconfig entry,
since these are so tightly integrated with the machines they are used on.
See ”hjÔ  hžhhŸNh NubhŒliteral”“”)”}”(hŒ``arch/arm/mach-ux500/Kconfig``”h]”hŒarch/arm/mach-ux500/Kconfig”…””}”(hhhjß  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÔ  ubhŒ for an example.”…””}”(hŒ for an example.”hjÔ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K^hj,  hžhubh¸)”}”(hXt  Pins usually have fancier names than this. You can find these in the datasheet
for your chip. Notice that the core pinctrl.h file provides a fancy macro
called ``PINCTRL_PIN()`` to create the struct entries. As you can see the pins are
enumerated from 0 in the upper left corner to 63 in the lower right corner.
This enumeration was arbitrarily chosen, in practice you need to think
through your numbering system so that it matches the layout of registers
and such things in your driver, or the code may become complicated. You must
also consider matching of offsets to the GPIO ranges that may be handled by
the pin controller.”h]”(hŒ Pins usually have fancier names than this. You can find these in the datasheet
for your chip. Notice that the core pinctrl.h file provides a fancy macro
called ”…””}”(hŒ Pins usually have fancier names than this. You can find these in the datasheet
for your chip. Notice that the core pinctrl.h file provides a fancy macro
called ”hjø  hžhhŸNh NubjÞ  )”}”(hŒ``PINCTRL_PIN()``”h]”hŒPINCTRL_PIN()”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjø  ubhXÃ   to create the struct entries. As you can see the pins are
enumerated from 0 in the upper left corner to 63 in the lower right corner.
This enumeration was arbitrarily chosen, in practice you need to think
through your numbering system so that it matches the layout of registers
and such things in your driver, or the code may become complicated. You must
also consider matching of offsets to the GPIO ranges that may be handled by
the pin controller.”…””}”(hXÃ   to create the struct entries. As you can see the pins are
enumerated from 0 in the upper left corner to 63 in the lower right corner.
This enumeration was arbitrarily chosen, in practice you need to think
through your numbering system so that it matches the layout of registers
and such things in your driver, or the code may become complicated. You must
also consider matching of offsets to the GPIO ranges that may be handled by
the pin controller.”hjø  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kchj,  hžhubh¸)”}”(hŒÉFor a padding with 467 pads, as opposed to actual pins, the enumeration will
be like this, walking around the edge of the chip, which seems to be industry
standard too (all these pads had names, too)::”h]”hŒÈFor a padding with 467 pads, as opposed to actual pins, the enumeration will
be like this, walking around the edge of the chip, which seems to be industry
standard too (all these pads had names, too):”…””}”(hŒÈFor a padding with 467 pads, as opposed to actual pins, the enumeration will
be like this, walking around the edge of the chip, which seems to be industry
standard too (all these pads had names, too):”hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kmhj,  hžhubj¢  )”}”(hŒS  0 ..... 104
466        105
  .        .
  .        .
358        224
 357 .... 225”h]”hŒS  0 ..... 104
466        105
  .        .
  .        .
358        224
 357 .... 225”…””}”(hhhj)  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  uh1j¡  hŸh¶h Krhj,  hžhubeh}”(h]”Œtop-level-interface”ah ]”h"]”Œtop-level interface”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒ
Pin groups”h]”hŒ
Pin groups”…””}”(hjD  hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj?  hžhhŸh¶h K{ubh¸)”}”(hŒÍMany controllers need to deal with groups of pins, so the pin controller
subsystem has a mechanism for enumerating groups of pins and retrieving the
actual enumerated pins that are part of a certain group.”h]”hŒÍMany controllers need to deal with groups of pins, so the pin controller
subsystem has a mechanism for enumerating groups of pins and retrieving the
actual enumerated pins that are part of a certain group.”…””}”(hjR  hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K}hj?  hžhubh¸)”}”(hŒ©For example, say that we have a group of pins dealing with an SPI interface
on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
on { 24, 25 }.”h]”hŒ©For example, say that we have a group of pins dealing with an SPI interface
on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
on { 24, 25 }.”…””}”(hj`  hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj?  hžhubh¸)”}”(hŒsThese two groups are presented to the pin control subsystem by implementing
some generic ``pinctrl_ops`` like this:”h]”(hŒYThese two groups are presented to the pin control subsystem by implementing
some generic ”…””}”(hŒYThese two groups are presented to the pin control subsystem by implementing
some generic ”hjl  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_ops``”h]”hŒpinctrl_ops”…””}”(hhhju  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjl  ubhŒ like this:”…””}”(hŒ like this:”hjl  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K…hj?  hžhubj¢  )”}”(hXÏ  #include <linux/pinctrl/pinctrl.h>

static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
static const unsigned int i2c0_pins[] = { 24, 25 };

static const struct pingroup foo_groups[] = {
        PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)),
        PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
};

static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_groups);
}

static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                      unsigned int selector)
{
        return foo_groups[selector].name;
}

static int foo_get_group_pins(struct pinctrl_dev *pctldev,
                              unsigned int selector,
                              const unsigned int **pins,
                              unsigned int *npins)
{
        *pins = foo_groups[selector].pins;
        *npins = foo_groups[selector].npins;
        return 0;
}

static struct pinctrl_ops foo_pctrl_ops = {
        .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
};

static struct pinctrl_desc foo_desc = {
        ...
        .pctlops = &foo_pctrl_ops,
};”h]”hXÏ  #include <linux/pinctrl/pinctrl.h>

static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
static const unsigned int i2c0_pins[] = { 24, 25 };

static const struct pingroup foo_groups[] = {
        PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)),
        PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
};

static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_groups);
}

static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                      unsigned int selector)
{
        return foo_groups[selector].name;
}

static int foo_get_group_pins(struct pinctrl_dev *pctldev,
                              unsigned int selector,
                              const unsigned int **pins,
                              unsigned int *npins)
{
        *pins = foo_groups[selector].pins;
        *npins = foo_groups[selector].npins;
        return 0;
}

static struct pinctrl_ops foo_pctrl_ops = {
        .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
};

static struct pinctrl_desc foo_desc = {
        ...
        .pctlops = &foo_pctrl_ops,
};”…””}”(hhhjŽ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Kˆhj?  hžhubh¸)”}”(hX¸  The pin control subsystem will call the ``.get_groups_count()`` function to
determine the total number of legal selectors, then it will call the other functions
to retrieve the name and pins of the group. Maintaining the data structure of
the groups is up to the driver, this is just a simple example - in practice you
may need more entries in your group structure, for example specific register
ranges associated with each group and so on.”h]”(hŒ(The pin control subsystem will call the ”…””}”(hŒ(The pin control subsystem will call the ”hj  hžhhŸNh NubjÞ  )”}”(hŒ``.get_groups_count()``”h]”hŒ.get_groups_count()”…””}”(hhhj¦  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj  ubhXy   function to
determine the total number of legal selectors, then it will call the other functions
to retrieve the name and pins of the group. Maintaining the data structure of
the groups is up to the driver, this is just a simple example - in practice you
may need more entries in your group structure, for example specific register
ranges associated with each group and so on.”…””}”(hXy   function to
determine the total number of legal selectors, then it will call the other functions
to retrieve the name and pins of the group. Maintaining the data structure of
the groups is up to the driver, this is just a simple example - in practice you
may need more entries in your group structure, for example specific register
ranges associated with each group and so on.”hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K´hj?  hžhubeh}”(h]”Œ
pin-groups”ah ]”h"]”Œ
pin groups”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K{ubh¢)”}”(hhh]”(h§)”}”(hŒPin configuration”h]”hŒPin configuration”…””}”(hjÌ  hjÊ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÇ  hžhhŸh¶h K½ubh¸)”}”(hXè  Pins can sometimes be software-configured in various ways, mostly related
to their electronic properties when used as inputs or outputs. For example you
may be able to make an output pin high impedance (Hi-Z), or "tristate" meaning it is
effectively disconnected. You may be able to connect an input pin to VDD or GND
using a certain resistor value - pull up and pull down - so that the pin has a
stable value when nothing is driving the rail it is connected to, or when it's
unconnected.”h]”hXî  Pins can sometimes be software-configured in various ways, mostly related
to their electronic properties when used as inputs or outputs. For example you
may be able to make an output pin high impedance (Hi-Z), or â€œtristateâ€ meaning it is
effectively disconnected. You may be able to connect an input pin to VDD or GND
using a certain resistor value - pull up and pull down - so that the pin has a
stable value when nothing is driving the rail it is connected to, or when itâ€™s
unconnected.”…””}”(hjÚ  hjØ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¿hjÇ  hžhubh¸)”}”(hŒPin configuration can be programmed by adding configuration entries into the
mapping table; see section `Board/machine configuration`_ below.”h]”(hŒhPin configuration can be programmed by adding configuration entries into the
mapping table; see section ”…””}”(hŒhPin configuration can be programmed by adding configuration entries into the
mapping table; see section ”hjæ  hžhhŸNh NubhŒ	reference”“”)”}”(hŒ`Board/machine configuration`_”h]”hŒBoard/machine configuration”…””}”(hŒBoard/machine configuration”hjñ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒBoard/machine configuration”Œrefid”Œboard-machine-configuration”uh1jï  hjæ  Œresolved”KubhŒ below.”…””}”(hŒ below.”hjæ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÇhjÇ  hžhubh¸)”}”(hŒ‚The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
above, is entirely defined by the pin controller driver.”h]”hŒ‚The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
above, is entirely defined by the pin controller driver.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÊhjÇ  hžhubh¸)”}”(hŒuThe pin configuration driver implements callbacks for changing pin
configuration in the pin controller ops like this:”h]”hŒuThe pin configuration driver implements callbacks for changing pin
configuration in the pin controller ops like this:”…””}”(hj   hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÍhjÇ  hžhubj¢  )”}”(hX  #include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>

#include "platform_x_pindefs.h"

static int foo_pin_config_get(struct pinctrl_dev *pctldev,
                              unsigned int offset,
                              unsigned long *config)
{
        struct my_conftype conf;

        /* ... Find setting for pin @ offset ... */

        *config = (unsigned long) conf;
}

static int foo_pin_config_set(struct pinctrl_dev *pctldev,
                              unsigned int offset,
                              unsigned long config)
{
        struct my_conftype *conf = (struct my_conftype *) config;

        switch (conf) {
                case PLATFORM_X_PULL_UP:
                ...
                break;
        }
}

static int foo_pin_config_group_get(struct pinctrl_dev *pctldev,
                                    unsigned selector,
                                    unsigned long *config)
{
        ...
}

static int foo_pin_config_group_set(struct pinctrl_dev *pctldev,
                                    unsigned selector,
                                    unsigned long config)
{
        ...
}

static struct pinconf_ops foo_pconf_ops = {
        .pin_config_get = foo_pin_config_get,
        .pin_config_set = foo_pin_config_set,
        .pin_config_group_get = foo_pin_config_group_get,
        .pin_config_group_set = foo_pin_config_group_set,
};

/* Pin config operations are handled by some pin controller */
static struct pinctrl_desc foo_desc = {
        ...
        .confops = &foo_pconf_ops,
};”h]”hX  #include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>

#include "platform_x_pindefs.h"

static int foo_pin_config_get(struct pinctrl_dev *pctldev,
                              unsigned int offset,
                              unsigned long *config)
{
        struct my_conftype conf;

        /* ... Find setting for pin @ offset ... */

        *config = (unsigned long) conf;
}

static int foo_pin_config_set(struct pinctrl_dev *pctldev,
                              unsigned int offset,
                              unsigned long config)
{
        struct my_conftype *conf = (struct my_conftype *) config;

        switch (conf) {
                case PLATFORM_X_PULL_UP:
                ...
                break;
        }
}

static int foo_pin_config_group_get(struct pinctrl_dev *pctldev,
                                    unsigned selector,
                                    unsigned long *config)
{
        ...
}

static int foo_pin_config_group_set(struct pinctrl_dev *pctldev,
                                    unsigned selector,
                                    unsigned long config)
{
        ...
}

static struct pinconf_ops foo_pconf_ops = {
        .pin_config_get = foo_pin_config_get,
        .pin_config_set = foo_pin_config_set,
        .pin_config_group_get = foo_pin_config_group_get,
        .pin_config_group_set = foo_pin_config_group_set,
};

/* Pin config operations are handled by some pin controller */
static struct pinctrl_desc foo_desc = {
        ...
        .confops = &foo_pconf_ops,
};”…””}”(hhhj,  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h KÐhjÇ  hžhubeh}”(h]”Œpin-configuration”ah ]”h"]”Œpin configuration”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K½ubh¢)”}”(hhh]”(h§)”}”(hŒ#Interaction with the GPIO subsystem”h]”hŒ#Interaction with the GPIO subsystem”…””}”(hjH  hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjC  hžhhŸh¶h Mubh¸)”}”(hŒ‹The GPIO drivers may want to perform operations of various types on the same
physical pins that are also registered as pin controller pins.”h]”hŒ‹The GPIO drivers may want to perform operations of various types on the same
physical pins that are also registered as pin controller pins.”…””}”(hjV  hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjC  hžhubh¸)”}”(hX  First and foremost, the two subsystems can be used as completely orthogonal,
see the section named `Pin control requests from drivers`_ and
`Drivers needing both pin control and GPIOs`_ below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.”h]”(hŒcFirst and foremost, the two subsystems can be used as completely orthogonal,
see the section named ”…””}”(hŒcFirst and foremost, the two subsystems can be used as completely orthogonal,
see the section named ”hjb  hžhhŸNh Nubjð  )”}”(hŒ$`Pin control requests from drivers`_”h]”hŒ!Pin control requests from drivers”…””}”(hŒ!Pin control requests from drivers”hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ!Pin control requests from drivers”j  Œ!pin-control-requests-from-drivers”uh1jï  hjb  j  KubhŒ and
”…””}”(hŒ and
”hjb  hžhhŸNh Nubjð  )”}”(hŒ-`Drivers needing both pin control and GPIOs`_”h]”hŒ*Drivers needing both pin control and GPIOs”…””}”(hŒ*Drivers needing both pin control and GPIOs”hj‚  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ*Drivers needing both pin control and GPIOs”j  Œ*drivers-needing-both-pin-control-and-gpios”uh1jï  hjb  j  KubhŒf below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.”…””}”(hŒf below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.”hjb  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjC  hžhubh¸)”}”(hXÙ  Since the pin controller subsystem has its pinspace local to the pin controller
we need a mapping so that the pin control subsystem can figure out which pin
controller handles control of a certain GPIO pin. Since a single pin controller
may be muxing several GPIO ranges (typically SoCs that have one set of pins,
but internally several GPIO silicon blocks, each modelled as a struct
gpio_chip) any number of GPIO ranges can be added to a pin controller instance
like this:”h]”hXÙ  Since the pin controller subsystem has its pinspace local to the pin controller
we need a mapping so that the pin control subsystem can figure out which pin
controller handles control of a certain GPIO pin. Since a single pin controller
may be muxing several GPIO ranges (typically SoCs that have one set of pins,
but internally several GPIO silicon blocks, each modelled as a struct
gpio_chip) any number of GPIO ranges can be added to a pin controller instance
like this:”…””}”(hj¡  hjŸ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjC  hžhubj¢  )”}”(hX©  #include <linux/gpio/driver.h>

#include <linux/pinctrl/pinctrl.h>

struct gpio_chip chip_a;
struct gpio_chip chip_b;

static struct pinctrl_gpio_range gpio_range_a = {
        .name = "chip a",
        .id = 0,
        .base = 32,
        .pin_base = 32,
        .npins = 16,
        .gc = &chip_a,
};

static struct pinctrl_gpio_range gpio_range_b = {
        .name = "chip b",
        .id = 0,
        .base = 48,
        .pin_base = 64,
        .npins = 8,
        .gc = &chip_b;
};

int __init foo_init(void)
{
        struct pinctrl_dev *pctl;
        ...
        pinctrl_add_gpio_range(pctl, &gpio_range_a);
        pinctrl_add_gpio_range(pctl, &gpio_range_b);
        ...
}”h]”hX©  #include <linux/gpio/driver.h>

#include <linux/pinctrl/pinctrl.h>

struct gpio_chip chip_a;
struct gpio_chip chip_b;

static struct pinctrl_gpio_range gpio_range_a = {
        .name = "chip a",
        .id = 0,
        .base = 32,
        .pin_base = 32,
        .npins = 16,
        .gc = &chip_a,
};

static struct pinctrl_gpio_range gpio_range_b = {
        .name = "chip b",
        .id = 0,
        .base = 48,
        .pin_base = 64,
        .npins = 8,
        .gc = &chip_b;
};

int __init foo_init(void)
{
        struct pinctrl_dev *pctl;
        ...
        pinctrl_add_gpio_range(pctl, &gpio_range_a);
        pinctrl_add_gpio_range(pctl, &gpio_range_b);
        ...
}”…””}”(hhhj­  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h MhjC  hžhubh¸)”}”(hŒçSo this complex system has one pin controller handling two different
GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
"chip b" have different ``pin_base``, which means a start pin number of the
GPIO range.”h]”(hŒ¸So this complex system has one pin controller handling two different
GPIO chips. â€œchip aâ€ has 16 pins and â€œchip bâ€ has 8 pins. The â€œchip aâ€ and
â€œchip bâ€ have different ”…””}”(hŒ¨So this complex system has one pin controller handling two different
GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
"chip b" have different ”hj¼  hžhhŸNh NubjÞ  )”}”(hŒ``pin_base``”h]”hŒpin_base”…””}”(hhhjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj¼  ubhŒ3, which means a start pin number of the
GPIO range.”…””}”(hŒ3, which means a start pin number of the
GPIO range.”hj¼  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MAhjC  hžhubh¸)”}”(hX  The GPIO range of "chip a" starts from the GPIO base of 32 and actual
pin range also starts from 32. However "chip b" has different starting
offset for the GPIO range and pin range. The GPIO range of "chip b" starts
from GPIO number 48, while the pin range of "chip b" starts from 64.”h]”hX,  The GPIO range of â€œchip aâ€ starts from the GPIO base of 32 and actual
pin range also starts from 32. However â€œchip bâ€ has different starting
offset for the GPIO range and pin range. The GPIO range of â€œchip bâ€ starts
from GPIO number 48, while the pin range of â€œchip bâ€ starts from 64.”…””}”(hjà  hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MFhjC  hžhubh¸)”}”(hŒ{We can convert a gpio number to actual pin number using this ``pin_base``.
They are mapped in the global GPIO pin space at:”h]”(hŒ=We can convert a gpio number to actual pin number using this ”…””}”(hŒ=We can convert a gpio number to actual pin number using this ”hjì  hžhhŸNh NubjÞ  )”}”(hŒ``pin_base``”h]”hŒpin_base”…””}”(hhhjõ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjì  ubhŒ2.
They are mapped in the global GPIO pin space at:”…””}”(hŒ2.
They are mapped in the global GPIO pin space at:”hjì  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MKhjC  hžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒ;chip a:
- GPIO range : [32 .. 47]
- pin range  : [32 .. 47]”h]”(hŒterm”“”)”}”(hŒchip a:”h]”hŒchip a:”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h MOhj  ubhŒ
definition”“”)”}”(hhh]”hÖ)”}”(hhh]”(hÛ)”}”(hŒGPIO range : [32 .. 47]”h]”h¸)”}”(hj3  h]”hŒGPIO range : [32 .. 47]”…””}”(hj3  hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MOhj1  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj.  ubhÛ)”}”(hŒpin range  : [32 .. 47]”h]”h¸)”}”(hjJ  h]”hŒpin range  : [32 .. 47]”…””}”(hjJ  hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MPhjH  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj.  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h MOhj+  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j)  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h MOhj  ubj  )”}”(hŒ<chip b:
- GPIO range : [48 .. 55]
- pin range  : [64 .. 71]
”h]”(j  )”}”(hŒchip b:”h]”hŒchip b:”…””}”(hjw  hju  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h MShjq  ubj*  )”}”(hhh]”hÖ)”}”(hhh]”(hÛ)”}”(hŒGPIO range : [48 .. 55]”h]”h¸)”}”(hj‹  h]”hŒGPIO range : [48 .. 55]”…””}”(hj‹  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MRhj‰  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj†  ubhÛ)”}”(hŒpin range  : [64 .. 71]
”h]”h¸)”}”(hŒpin range  : [64 .. 71]”h]”hŒpin range  : [64 .. 71]”…””}”(hj¦  hj¤  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MShj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj†  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h MRhjƒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j)  hjq  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h MShj  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjC  hžhhŸNh Nubh¸)”}”(hŒ»The above examples assume the mapping between the GPIOs and pins is
linear. If the mapping is sparse or haphazard, an array of arbitrary pin
numbers can be encoded in the range like this:”h]”hŒ»The above examples assume the mapping between the GPIOs and pins is
linear. If the mapping is sparse or haphazard, an array of arbitrary pin
numbers can be encoded in the range like this:”…””}”(hjÒ  hjÐ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MUhjC  hžhubj¢  )”}”(hX  static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };

static struct pinctrl_gpio_range gpio_range = {
        .name = "chip",
        .id = 0,
        .base = 32,
        .pins = &range_pins,
        .npins = ARRAY_SIZE(range_pins),
        .gc = &chip,
};”h]”hX  static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };

static struct pinctrl_gpio_range gpio_range = {
        .name = "chip",
        .id = 0,
        .base = 32,
        .pins = &range_pins,
        .npins = ARRAY_SIZE(range_pins),
        .gc = &chip,
};”…””}”(hhhjÞ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h MYhjC  hžhubh¸)”}”(hŒíIn this case the ``pin_base`` property will be ignored. If the name of a pin
group is known, the pins and npins elements of the above structure can be
initialised using the function ``pinctrl_get_group_pins()``, e.g. for pin
group "foo":”h]”(hŒIn this case the ”…””}”(hŒIn this case the ”hjí  hžhhŸNh NubjÞ  )”}”(hŒ``pin_base``”h]”hŒpin_base”…””}”(hhhjö  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjí  ubhŒ™ property will be ignored. If the name of a pin
group is known, the pins and npins elements of the above structure can be
initialised using the function ”…””}”(hŒ™ property will be ignored. If the name of a pin
group is known, the pins and npins elements of the above structure can be
initialised using the function ”hjí  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_get_group_pins()``”h]”hŒpinctrl_get_group_pins()”…””}”(hhhj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjí  ubhŒ, e.g. for pin
group â€œfooâ€:”…””}”(hŒ, e.g. for pin
group "foo":”hjí  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MfhjC  hžhubj¢  )”}”(hŒIpinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);”h]”hŒIpinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);”…””}”(hhhj"  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h MkhjC  hžhubh¸)”}”(hXZ  When GPIO-specific functions in the pin control subsystem are called, these
ranges will be used to look up the appropriate pin controller by inspecting
and matching the pin to the pin ranges across all controllers. When a
pin controller handling the matching range is found, GPIO-specific functions
will be called on that specific pin controller.”h]”hXZ  When GPIO-specific functions in the pin control subsystem are called, these
ranges will be used to look up the appropriate pin controller by inspecting
and matching the pin to the pin ranges across all controllers. When a
pin controller handling the matching range is found, GPIO-specific functions
will be called on that specific pin controller.”…””}”(hj3  hj1  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MohjC  hžhubh¸)”}”(hXÕ  For all functionalities dealing with pin biasing, pin muxing etc, the pin
controller subsystem will look up the corresponding pin number from the passed
in gpio number, and use the range's internals to retrieve a pin number. After
that, the subsystem passes it on to the pin control driver, so the driver
will get a pin number into its handled number range. Further it is also passed
the range ID value, so that the pin controller knows which range it should
deal with.”h]”hX×  For all functionalities dealing with pin biasing, pin muxing etc, the pin
controller subsystem will look up the corresponding pin number from the passed
in gpio number, and use the rangeâ€™s internals to retrieve a pin number. After
that, the subsystem passes it on to the pin control driver, so the driver
will get a pin number into its handled number range. Further it is also passed
the range ID value, so that the pin controller knows which range it should
deal with.”…””}”(hjA  hj?  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MuhjC  hžhubh¸)”}”(hŒ¾Calling ``pinctrl_add_gpio_range()`` from pinctrl driver is DEPRECATED. Please see
section 2.1 of ``Documentation/devicetree/bindings/gpio/gpio.txt`` on how to bind
pinctrl and gpio drivers.”h]”(hŒCalling ”…””}”(hŒCalling ”hjM  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_add_gpio_range()``”h]”hŒpinctrl_add_gpio_range()”…””}”(hhhjV  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjM  ubhŒ> from pinctrl driver is DEPRECATED. Please see
section 2.1 of ”…””}”(hŒ> from pinctrl driver is DEPRECATED. Please see
section 2.1 of ”hjM  hžhhŸNh NubjÞ  )”}”(hŒ3``Documentation/devicetree/bindings/gpio/gpio.txt``”h]”hŒ/Documentation/devicetree/bindings/gpio/gpio.txt”…””}”(hhhji  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjM  ubhŒ) on how to bind
pinctrl and gpio drivers.”…””}”(hŒ) on how to bind
pinctrl and gpio drivers.”hjM  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M}hjC  hžhubeh}”(h]”Œ#interaction-with-the-gpio-subsystem”ah ]”h"]”Œ#interaction with the gpio subsystem”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Mubh¢)”}”(hhh]”(h§)”}”(hŒPINMUX interfaces”h]”hŒPINMUX interfaces”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjŠ  hžhhŸh¶h Mƒubh¸)”}”(hŒSThese calls use the pinmux_* naming prefix.  No other calls should use that
prefix.”h]”hŒSThese calls use the pinmux_* naming prefix.  No other calls should use that
prefix.”…””}”(hj  hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M…hjŠ  hžhubeh}”(h]”Œpinmux-interfaces”ah ]”h"]”Œpinmux interfaces”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Mƒubh¢)”}”(hhh]”(h§)”}”(hŒWhat is pinmuxing?”h]”hŒWhat is pinmuxing?”…””}”(hj¶  hj´  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj±  hžhhŸh¶h MŠubh¸)”}”(hXÙ  PINMUX, also known as padmux, ballmux, alternate functions or mission modes
is a way for chip vendors producing some kind of electrical packages to use
a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
functions, depending on the application. By "application" in this context
we usually mean a way of soldering or wiring the package into an electronic
system, even though the framework makes it possible to also change the function
at runtime.”h]”hXÝ  PINMUX, also known as padmux, ballmux, alternate functions or mission modes
is a way for chip vendors producing some kind of electrical packages to use
a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
functions, depending on the application. By â€œapplicationâ€ in this context
we usually mean a way of soldering or wiring the package into an electronic
system, even though the framework makes it possible to also change the function
at runtime.”…””}”(hjÄ  hjÂ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MŒhj±  hžhubh¸)”}”(hŒHHere is an example of a PGA (Pin Grid Array) chip seen from underneath::”h]”hŒGHere is an example of a PGA (Pin Grid Array) chip seen from underneath:”…””}”(hŒGHere is an example of a PGA (Pin Grid Array) chip seen from underneath:”hjÐ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M”hj±  hžhubj¢  )”}”(hX       A   B   C   D   E   F   G   H
   +---+
8  | o | o   o   o   o   o   o   o
   |   |
7  | o | o   o   o   o   o   o   o
   |   |
6  | o | o   o   o   o   o   o   o
   +---+---+
5  | o | o | o   o   o   o   o   o
   +---+---+               +---+
4    o   o   o   o   o   o | o | o
                           |   |
3    o   o   o   o   o   o | o | o
                           |   |
2    o   o   o   o   o   o | o | o
   +-------+-------+-------+---+---+
1  | o   o | o   o | o   o | o | o |
   +-------+-------+-------+---+---+”h]”hX       A   B   C   D   E   F   G   H
   +---+
8  | o | o   o   o   o   o   o   o
   |   |
7  | o | o   o   o   o   o   o   o
   |   |
6  | o | o   o   o   o   o   o   o
   +---+---+
5  | o | o | o   o   o   o   o   o
   +---+---+               +---+
4    o   o   o   o   o   o | o | o
                           |   |
3    o   o   o   o   o   o | o | o
                           |   |
2    o   o   o   o   o   o | o | o
   +-------+-------+-------+---+---+
1  | o   o | o   o | o   o | o | o |
   +-------+-------+-------+---+---+”…””}”(hhhjß  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  uh1j¡  hŸh¶h M–hj±  hžhubh¸)”}”(hXÍ  This is not tetris. The game to think of is chess. Not all PGA/BGA packages
are chessboard-like, big ones have "holes" in some arrangement according to
different design patterns, but we're using this as a simple example. Of the
pins you see some will be taken by things like a few VCC and GND to feed power
to the chip, and quite a few will be taken by large ports like an external
memory interface. The remaining pins will often be subject to pin multiplexing.”h]”hXÓ  This is not tetris. The game to think of is chess. Not all PGA/BGA packages
are chessboard-like, big ones have â€œholesâ€ in some arrangement according to
different design patterns, but weâ€™re using this as a simple example. Of the
pins you see some will be taken by things like a few VCC and GND to feed power
to the chip, and quite a few will be taken by large ports like an external
memory interface. The remaining pins will often be subject to pin multiplexing.”…””}”(hjï  hjí  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M©hj±  hžhubh¸)”}”(hŒßThe example 8x8 PGA package above will have pin numbers 0 through 63 assigned
to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
pinctrl_register_pins() and a suitable data set as shown earlier.”h]”hŒßThe example 8x8 PGA package above will have pin numbers 0 through 63 assigned
to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
pinctrl_register_pins() and a suitable data set as shown earlier.”…””}”(hjý  hjû  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M°hj±  hžhubh¸)”}”(hXú  In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
we cannot use the SPI port and I2C port at the same time. However in the inside
of the package the silicon performing the SPI logic can alternatively be routed
out on pins { G4, G3, G2, G1 }.”h]”hXú  In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
we cannot use the SPI port and I2C port at the same time. However in the inside
of the package the silicon performing the SPI logic can alternatively be routed
out on pins { G4, G3, G2, G1 }.”…””}”(hj  hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M´hj±  hžhubh¸)”}”(hXZ  On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
port on pins { G4, G3, G2, G1 } of course.”h]”hX\  On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
special - itâ€™s an external MMC bus that can be 2, 4 or 8 bits wide, and it will
consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
port on pins { G4, G3, G2, G1 } of course.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¼hj±  hžhubh¸)”}”(hX	  This way the silicon blocks present inside the chip can be multiplexed "muxed"
out on different pin ranges. Often contemporary SoC (systems on chip) will
contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
different pins by pinmux settings.”h]”hX  This way the silicon blocks present inside the chip can be multiplexed â€œmuxedâ€
out on different pin ranges. Often contemporary SoC (systems on chip) will
contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
different pins by pinmux settings.”…””}”(hj'  hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÂhj±  hžhubh¸)”}”(hŒ¹Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
common to be able to use almost any pin as a GPIO pin if it is not currently
in use by some other I/O port.”h]”hŒ¹Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
common to be able to use almost any pin as a GPIO pin if it is not currently
in use by some other I/O port.”…””}”(hj5  hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÇhj±  hžhubeh}”(h]”Œwhat-is-pinmuxing”ah ]”h"]”Œwhat is pinmuxing?”ah$]”h&]”uh1h¡hh£hžhhŸh¶h MŠubh¢)”}”(hhh]”(h§)”}”(hŒPinmux conventions”h]”hŒPinmux conventions”…””}”(hjN  hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjI  hžhhŸh¶h MÍubh¸)”}”(hX]  The purpose of the pinmux functionality in the pin controller subsystem is to
abstract and provide pinmux settings to the devices you choose to instantiate
in your machine configuration. It is inspired by the clk, GPIO and regulator
subsystems, so devices will request their mux setting, but it's also possible
to request a single pin for e.g. GPIO.”h]”hX_  The purpose of the pinmux functionality in the pin controller subsystem is to
abstract and provide pinmux settings to the devices you choose to instantiate
in your machine configuration. It is inspired by the clk, GPIO and regulator
subsystems, so devices will request their mux setting, but itâ€™s also possible
to request a single pin for e.g. GPIO.”…””}”(hj\  hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÏhjI  hžhubh¸)”}”(hŒThe conventions are:”h]”hŒThe conventions are:”…””}”(hjj  hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÕhjI  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hX*  FUNCTIONS can be switched in and out by a driver residing with the pin
control subsystem in the ``drivers/pinctrl`` directory of the kernel. The
pin control driver knows the possible functions. In the example above you can
identify three pinmux functions, one for spi, one for i2c and one for mmc.
”h]”h¸)”}”(hX)  FUNCTIONS can be switched in and out by a driver residing with the pin
control subsystem in the ``drivers/pinctrl`` directory of the kernel. The
pin control driver knows the possible functions. In the example above you can
identify three pinmux functions, one for spi, one for i2c and one for mmc.”h]”(hŒ`FUNCTIONS can be switched in and out by a driver residing with the pin
control subsystem in the ”…””}”(hŒ`FUNCTIONS can be switched in and out by a driver residing with the pin
control subsystem in the ”hj}  hžhhŸNh NubjÞ  )”}”(hŒ``drivers/pinctrl``”h]”hŒdrivers/pinctrl”…””}”(hhhj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj}  ubhŒ¶ directory of the kernel. The
pin control driver knows the possible functions. In the example above you can
identify three pinmux functions, one for spi, one for i2c and one for mmc.”…””}”(hŒ¶ directory of the kernel. The
pin control driver knows the possible functions. In the example above you can
identify three pinmux functions, one for spi, one for i2c and one for mmc.”hj}  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M×hjy  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h NubhÛ)”}”(hŒµFUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
In this case the array could be something like: { spi0, i2c0, mmc0 }
for the three available functions.
”h]”h¸)”}”(hŒ´FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
In this case the array could be something like: { spi0, i2c0, mmc0 }
for the three available functions.”h]”hŒ´FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
In this case the array could be something like: { spi0, i2c0, mmc0 }
for the three available functions.”…””}”(hj«  hj©  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÜhj¥  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h NubhÛ)”}”(hXY  FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
function is *always* associated with a certain set of pin groups, could
be just a single one, but could also be many. In the example above the
function i2c is associated with the pins { A5, B5 }, enumerated as
{ 24, 25 } in the controller pin space.

The Function spi is associated with pin groups { A8, A7, A6, A5 }
and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
{ 38, 46, 54, 62 } respectively.

Group names must be unique per pin controller, no two groups on the same
controller may have the same name.
”h]”(h¸)”}”(hXB  FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
function is *always* associated with a certain set of pin groups, could
be just a single one, but could also be many. In the example above the
function i2c is associated with the pins { A5, B5 }, enumerated as
{ 24, 25 } in the controller pin space.”h]”(hŒUFUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
function is ”…””}”(hŒUFUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
function is ”hjÁ  hžhhŸNh NubhŒemphasis”“”)”}”(hŒ*always*”h]”hŒalways”…””}”(hhhjÌ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÊ  hjÁ  ubhŒå associated with a certain set of pin groups, could
be just a single one, but could also be many. In the example above the
function i2c is associated with the pins { A5, B5 }, enumerated as
{ 24, 25 } in the controller pin space.”…””}”(hŒå associated with a certain set of pin groups, could
be just a single one, but could also be many. In the example above the
function i2c is associated with the pins { A5, B5 }, enumerated as
{ 24, 25 } in the controller pin space.”hjÁ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Màhj½  ubh¸)”}”(hŒ§The Function spi is associated with pin groups { A8, A7, A6, A5 }
and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
{ 38, 46, 54, 62 } respectively.”h]”hŒ§The Function spi is associated with pin groups { A8, A7, A6, A5 }
and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
{ 38, 46, 54, 62 } respectively.”…””}”(hjç  hjå  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mæhj½  ubh¸)”}”(hŒkGroup names must be unique per pin controller, no two groups on the same
controller may have the same name.”h]”hŒkGroup names must be unique per pin controller, no two groups on the same
controller may have the same name.”…””}”(hjõ  hjó  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mêhj½  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h NubhÛ)”}”(hXƒ  The combination of a FUNCTION and a PIN GROUP determine a certain function
for a certain set of pins. The knowledge of the functions and pin groups
and their machine-specific particulars are kept inside the pinmux driver,
from the outside only the enumerators are known, and the driver core can
request:

- The name of a function with a certain selector (>= 0)
- A list of groups associated with a certain function
- That a certain group in that list to be activated for a certain function

As already described above, pin groups are in turn self-descriptive, so
the core will retrieve the actual pin range in a certain group from the
driver.
”h]”(h¸)”}”(hX/  The combination of a FUNCTION and a PIN GROUP determine a certain function
for a certain set of pins. The knowledge of the functions and pin groups
and their machine-specific particulars are kept inside the pinmux driver,
from the outside only the enumerators are known, and the driver core can
request:”h]”hX/  The combination of a FUNCTION and a PIN GROUP determine a certain function
for a certain set of pins. The knowledge of the functions and pin groups
and their machine-specific particulars are kept inside the pinmux driver,
from the outside only the enumerators are known, and the driver core can
request:”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Míhj  ubhÖ)”}”(hhh]”(hÛ)”}”(hŒ5The name of a function with a certain selector (>= 0)”h]”h¸)”}”(hj  h]”hŒ5The name of a function with a certain selector (>= 0)”…””}”(hj  hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Móhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj  ubhÛ)”}”(hŒ3A list of groups associated with a certain function”h]”h¸)”}”(hj5  h]”hŒ3A list of groups associated with a certain function”…””}”(hj5  hj7  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Môhj3  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj  ubhÛ)”}”(hŒIThat a certain group in that list to be activated for a certain function
”h]”h¸)”}”(hŒHThat a certain group in that list to be activated for a certain function”h]”hŒHThat a certain group in that list to be activated for a certain function”…””}”(hjP  hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MõhjJ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h Móhj  ubh¸)”}”(hŒ—As already described above, pin groups are in turn self-descriptive, so
the core will retrieve the actual pin range in a certain group from the
driver.”h]”hŒ—As already described above, pin groups are in turn self-descriptive, so
the core will retrieve the actual pin range in a certain group from the
driver.”…””}”(hjj  hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M÷hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h NubhÛ)”}”(hX]  FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
device by the board file, device tree or similar machine setup configuration
mechanism, similar to how regulators are connected to devices, usually by
name. Defining a pin controller, function and group thus uniquely identify
the set of pins to be used by a certain device. (If only one possible group
of pins is available for the function, no group name need to be supplied -
the core will simply select the first and only group available.)

In the example case we can define that this particular machine shall
use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
fi2c0 group gi2c0, on the primary pin controller, we get mappings
like these:

.. code-block:: c

      {
              {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
              {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
      }

Every map must be assigned a state name, pin controller, device and
function. The group is not compulsory - if it is omitted the first group
presented by the driver as applicable for the function will be selected,
which is useful for simple cases.

It is possible to map several groups to the same combination of device,
pin controller and function. This is for cases where a certain function on
a certain pin controller may use different sets of pins in different
configurations.
”h]”(h¸)”}”(hX  FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
device by the board file, device tree or similar machine setup configuration
mechanism, similar to how regulators are connected to devices, usually by
name. Defining a pin controller, function and group thus uniquely identify
the set of pins to be used by a certain device. (If only one possible group
of pins is available for the function, no group name need to be supplied -
the core will simply select the first and only group available.)”h]”hX  FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
device by the board file, device tree or similar machine setup configuration
mechanism, similar to how regulators are connected to devices, usually by
name. Defining a pin controller, function and group thus uniquely identify
the set of pins to be used by a certain device. (If only one possible group
of pins is available for the function, no group name need to be supplied -
the core will simply select the first and only group available.)”…””}”(hj‚  hj€  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mûhj|  ubh¸)”}”(hŒÞIn the example case we can define that this particular machine shall
use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
fi2c0 group gi2c0, on the primary pin controller, we get mappings
like these:”h]”hŒÞIn the example case we can define that this particular machine shall
use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
fi2c0 group gi2c0, on the primary pin controller, we get mappings
like these:”…””}”(hj  hjŽ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj|  ubj¢  )”}”(hŒk{
        {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
        {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
}”h]”hŒk{
        {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
        {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
}”…””}”(hhhjœ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mhj|  ubh¸)”}”(hŒ÷Every map must be assigned a state name, pin controller, device and
function. The group is not compulsory - if it is omitted the first group
presented by the driver as applicable for the function will be selected,
which is useful for simple cases.”h]”hŒ÷Every map must be assigned a state name, pin controller, device and
function. The group is not compulsory - if it is omitted the first group
presented by the driver as applicable for the function will be selected,
which is useful for simple cases.”…””}”(hj­  hj«  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj|  ubh¸)”}”(hŒçIt is possible to map several groups to the same combination of device,
pin controller and function. This is for cases where a certain function on
a certain pin controller may use different sets of pins in different
configurations.”h]”hŒçIt is possible to map several groups to the same combination of device,
pin controller and function. This is for cases where a certain function on
a certain pin controller may use different sets of pins in different
configurations.”…””}”(hj»  hj¹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj|  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h NubhÛ)”}”(hXQ  PINS for a certain FUNCTION using a certain PIN GROUP on a certain
PIN CONTROLLER are provided on a first-come first-serve basis, so if some
other device mux setting or GPIO pin request has already taken your physical
pin, you will be denied the use of it. To get (activate) a new setting, the
old one has to be put (deactivated) first.
”h]”h¸)”}”(hXP  PINS for a certain FUNCTION using a certain PIN GROUP on a certain
PIN CONTROLLER are provided on a first-come first-serve basis, so if some
other device mux setting or GPIO pin request has already taken your physical
pin, you will be denied the use of it. To get (activate) a new setting, the
old one has to be put (deactivated) first.”h]”hXP  PINS for a certain FUNCTION using a certain PIN GROUP on a certain
PIN CONTROLLER are provided on a first-come first-serve basis, so if some
other device mux setting or GPIO pin request has already taken your physical
pin, you will be denied the use of it. To get (activate) a new setting, the
old one has to be put (deactivated) first.”…””}”(hjÓ  hjÑ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjÍ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjv  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h M×hjI  hžhubh¸)”}”(hX  Sometimes the documentation and hardware registers will be oriented around
pads (or "fingers") rather than pins - these are the soldering surfaces on the
silicon inside the package, and may or may not match the actual number of
pins/balls underneath the capsule. Pick some enumeration that makes sense to
you. Define enumerators only for the pins you can control if that makes sense.”h]”hXƒ  Sometimes the documentation and hardware registers will be oriented around
pads (or â€œfingersâ€) rather than pins - these are the soldering surfaces on the
silicon inside the package, and may or may not match the actual number of
pins/balls underneath the capsule. Pick some enumeration that makes sense to
you. Define enumerators only for the pins you can control if that makes sense.”…””}”(hjí  hjë  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjI  hžhubh¸)”}”(hŒAssumptions:”h]”hŒAssumptions:”…””}”(hjû  hjù  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M%hjI  hžhubh¸)”}”(hX6  We assume that the number of possible function maps to pin groups is limited by
the hardware. I.e. we assume that there is no system where any function can be
mapped to any pin, like in a phone exchange. So the available pin groups for
a certain function will be limited to a few choices (say up to eight or so),
not hundreds or any amount of choices. This is the characteristic we have found
by inspecting available pinmux hardware, and a necessary assumption since we
expect pinmux drivers to present *all* possible function vs pin group mappings
to the subsystem.”h]”(hX÷  We assume that the number of possible function maps to pin groups is limited by
the hardware. I.e. we assume that there is no system where any function can be
mapped to any pin, like in a phone exchange. So the available pin groups for
a certain function will be limited to a few choices (say up to eight or so),
not hundreds or any amount of choices. This is the characteristic we have found
by inspecting available pinmux hardware, and a necessary assumption since we
expect pinmux drivers to present ”…””}”(hX÷  We assume that the number of possible function maps to pin groups is limited by
the hardware. I.e. we assume that there is no system where any function can be
mapped to any pin, like in a phone exchange. So the available pin groups for
a certain function will be limited to a few choices (say up to eight or so),
not hundreds or any amount of choices. This is the characteristic we have found
by inspecting available pinmux hardware, and a necessary assumption since we
expect pinmux drivers to present ”hj  hžhhŸNh NubjË  )”}”(hŒ*all*”h]”hŒall”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÊ  hj  ubhŒ: possible function vs pin group mappings
to the subsystem.”…””•      }”(hŒ: possible function vs pin group mappings
to the subsystem.”hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M'hjI  hžhubeh}”(h]”Œpinmux-conventions”ah ]”h"]”Œpinmux conventions”ah$]”h&]”uh1h¡hh£hžhhŸh¶h MÍubh¢)”}”(hhh]”(h§)”}”(hŒPinmux drivers”h]”hŒPinmux drivers”…””}”(hj6  hj4  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj1  hžhhŸh¶h M2ubh¸)”}”(hŒThe pinmux core takes care of preventing conflicts on pins and calling
the pin controller driver to execute different settings.”h]”hŒThe pinmux core takes care of preventing conflicts on pins and calling
the pin controller driver to execute different settings.”…””}”(hjD  hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M4hj1  hžhubh¸)”}”(hXB  It is the responsibility of the pinmux driver to impose further restrictions
(say for example infer electronic limitations due to load, etc.) to determine
whether or not the requested function can actually be allowed, and in case it
is possible to perform the requested mux setting, poke the hardware so that
this happens.”h]”hXB  It is the responsibility of the pinmux driver to impose further restrictions
(say for example infer electronic limitations due to load, etc.) to determine
whether or not the requested function can actually be allowed, and in case it
is possible to perform the requested mux setting, poke the hardware so that
this happens.”…””}”(hjR  hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M7hj1  hžhubh¸)”}”(hŒæPinmux drivers are required to supply a few callback functions, some are
optional. Usually the ``.set_mux()`` function is implemented, writing values into
some certain registers to activate a certain mux setting for a certain pin.”h]”(hŒ_Pinmux drivers are required to supply a few callback functions, some are
optional. Usually the ”…””}”(hŒ_Pinmux drivers are required to supply a few callback functions, some are
optional. Usually the ”hj^  hžhhŸNh NubjÞ  )”}”(hŒ``.set_mux()``”h]”hŒ
.set_mux()”…””}”(hhhjg  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj^  ubhŒy function is implemented, writing values into
some certain registers to activate a certain mux setting for a certain pin.”…””}”(hŒy function is implemented, writing values into
some certain registers to activate a certain mux setting for a certain pin.”hj^  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M=hj1  hžhubh¸)”}”(hŒÊA simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5
into some register named MUX to select a certain function with a certain
group of pins would work something like this:”h]”hŒÊA simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5
into some register named MUX to select a certain function with a certain
group of pins would work something like this:”…””}”(hj‚  hj€  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MAhj1  hžhubj¢  )”}”(hXL  #include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
static const unsigned int i2c0_pins[] = { 24, 25 };
static const unsigned int mmc0_1_pins[] = { 56, 57 };
static const unsigned int mmc0_2_pins[] = { 58, 59 };
static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 };

static const struct pingroup foo_groups[] = {
        PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)),
        PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)),
        PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
        PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)),
        PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)),
        PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)),
};

static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_groups);
}

static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                      unsigned int selector)
{
        return foo_groups[selector].name;
}

static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
                              const unsigned int **pins,
                              unsigned int *npins)
{
        *pins = foo_groups[selector].pins;
        *npins = foo_groups[selector].npins;
        return 0;
}

static struct pinctrl_ops foo_pctrl_ops = {
        .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
};

static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
static const char * const i2c0_groups[] = { "i2c0_grp" };
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" };

static const struct pinfunction foo_functions[] = {
        PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
        PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)),
        PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)),
};

static int foo_get_functions_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_functions);
}

static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
{
        return foo_functions[selector].name;
}

static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
                          const char * const **groups,
                          unsigned int * const ngroups)
{
        *groups = foo_functions[selector].groups;
        *ngroups = foo_functions[selector].ngroups;
        return 0;
}

static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
                       unsigned int group)
{
        u8 regbit = BIT(group);

        writeb((readb(MUX) | regbit), MUX);
        return 0;
}

static struct pinmux_ops foo_pmxops = {
        .get_functions_count = foo_get_functions_count,
        .get_function_name = foo_get_fname,
        .get_function_groups = foo_get_groups,
        .set_mux = foo_set_mux,
        .strict = true,
};

/* Pinmux operations are handled by some pin controller */
static struct pinctrl_desc foo_desc = {
        ...
        .pctlops = &foo_pctrl_ops,
        .pmxops = &foo_pmxops,
};”h]”hXL  #include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
static const unsigned int i2c0_pins[] = { 24, 25 };
static const unsigned int mmc0_1_pins[] = { 56, 57 };
static const unsigned int mmc0_2_pins[] = { 58, 59 };
static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 };

static const struct pingroup foo_groups[] = {
        PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)),
        PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)),
        PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
        PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)),
        PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)),
        PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)),
};

static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_groups);
}

static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                      unsigned int selector)
{
        return foo_groups[selector].name;
}

static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
                              const unsigned int **pins,
                              unsigned int *npins)
{
        *pins = foo_groups[selector].pins;
        *npins = foo_groups[selector].npins;
        return 0;
}

static struct pinctrl_ops foo_pctrl_ops = {
        .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
};

static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
static const char * const i2c0_groups[] = { "i2c0_grp" };
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" };

static const struct pinfunction foo_functions[] = {
        PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
        PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)),
        PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)),
};

static int foo_get_functions_count(struct pinctrl_dev *pctldev)
{
        return ARRAY_SIZE(foo_functions);
}

static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
{
        return foo_functions[selector].name;
}

static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
                          const char * const **groups,
                          unsigned int * const ngroups)
{
        *groups = foo_functions[selector].groups;
        *ngroups = foo_functions[selector].ngroups;
        return 0;
}

static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
                       unsigned int group)
{
        u8 regbit = BIT(group);

        writeb((readb(MUX) | regbit), MUX);
        return 0;
}

static struct pinmux_ops foo_pmxops = {
        .get_functions_count = foo_get_functions_count,
        .get_function_name = foo_get_fname,
        .get_function_groups = foo_get_groups,
        .set_mux = foo_set_mux,
        .strict = true,
};

/* Pinmux operations are handled by some pin controller */
static struct pinctrl_desc foo_desc = {
        ...
        .pctlops = &foo_pctrl_ops,
        .pmxops = &foo_pmxops,
};”…””}”(hhhjŽ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h MEhj1  hžhubh¸)”}”(hŒ½In the example activating muxing 0 and 2 at the same time setting bits
0 and 2, uses pin 24 in common so they would collide. All the same for
the muxes 1 and 5, which have pin 62 in common.”h]”hŒ½In the example activating muxing 0 and 2 at the same time setting bits
0 and 2, uses pin 24 in common so they would collide. All the same for
the muxes 1 and 5, which have pin 62 in common.”…””}”(hjŸ  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M©hj1  hžhubh¸)”}”(hX¼  The beauty of the pinmux subsystem is that since it keeps track of all
pins and who is using them, it will already have denied an impossible
request like that, so the driver does not need to worry about such
things - when it gets a selector passed in, the pinmux subsystem makes
sure no other device or GPIO assignment is already using the selected
pins. Thus bits 0 and 2, or 1 and 5 in the control register will never
be set at the same time.”h]”hX¼  The beauty of the pinmux subsystem is that since it keeps track of all
pins and who is using them, it will already have denied an impossible
request like that, so the driver does not need to worry about such
things - when it gets a selector passed in, the pinmux subsystem makes
sure no other device or GPIO assignment is already using the selected
pins. Thus bits 0 and 2, or 1 and 5 in the control register will never
be set at the same time.”…””}”(hj­  hj«  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M­hj1  hžhubh¸)”}”(hŒGAll the above functions are mandatory to implement for a pinmux driver.”h]”hŒGAll the above functions are mandatory to implement for a pinmux driver.”…””}”(hj»  hj¹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mµhj1  hžhubeh}”(h]”Œpinmux-drivers”ah ]”h"]”Œpinmux drivers”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M2ubh¢)”}”(hhh]”(h§)”}”(hŒ/Pin control interaction with the GPIO subsystem”h]”hŒ/Pin control interaction with the GPIO subsystem”…””}”(hjÔ  hjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÏ  hžhhŸh¶h M¹ubh¸)”}”(hX¨  Note that the following implies that the use case is to use a certain pin
from the Linux kernel using the API in ``<linux/gpio/consumer.h>`` with gpiod_get()
and similar functions. There are cases where you may be using something
that your datasheet calls "GPIO mode", but actually is just an electrical
configuration for a certain device. See the section below named
`GPIO mode pitfalls`_ for more details on this scenario.”h]”(hŒqNote that the following implies that the use case is to use a certain pin
from the Linux kernel using the API in ”…””}”(hŒqNote that the following implies that the use case is to use a certain pin
from the Linux kernel using the API in ”hjà  hžhhŸNh NubjÞ  )”}”(hŒ``<linux/gpio/consumer.h>``”h]”hŒ<linux/gpio/consumer.h>”…””}”(hhhjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjà  ubhŒè with gpiod_get()
and similar functions. There are cases where you may be using something
that your datasheet calls â€œGPIO modeâ€, but actually is just an electrical
configuration for a certain device. See the section below named
”…””}”(hŒä with gpiod_get()
and similar functions. There are cases where you may be using something
that your datasheet calls "GPIO mode", but actually is just an electrical
configuration for a certain device. See the section below named
”hjà  hžhhŸNh Nubjð  )”}”(hŒ`GPIO mode pitfalls`_”h]”hŒGPIO mode pitfalls”…””}”(hŒGPIO mode pitfalls”hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒGPIO mode pitfalls”j  Œgpio-mode-pitfalls”uh1jï  hjà  j  KubhŒ# for more details on this scenario.”…””}”(hŒ# for more details on this scenario.”hjà  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M»hjÏ  hžhubh¸)”}”(hX¶  The public pinmux API contains two functions named ``pinctrl_gpio_request()``
and ``pinctrl_gpio_free()``. These two functions shall *ONLY* be called from
gpiolib-based drivers as part of their ``.request()`` and ``.free()`` semantics.
Likewise the ``pinctrl_gpio_direction_input()`` / ``pinctrl_gpio_direction_output()``
shall only be called from within respective ``.direction_input()`` /
``.direction_output()`` gpiolib implementation.”h]”(hŒ3The public pinmux API contains two functions named ”…””}”(hŒ3The public pinmux API contains two functions named ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_gpio_request()``”h]”hŒpinctrl_gpio_request()”…””}”(hhhj"	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ
and ”…””}”(hŒ
and ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_gpio_free()``”h]”hŒpinctrl_gpio_free()”…””}”(hhhj5	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ. These two functions shall ”…””}”(hŒ. These two functions shall ”hj	  hžhhŸNh NubjË  )”}”(hŒ*ONLY*”h]”hŒONLY”…””}”(hhhjH	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÊ  hj	  ubhŒ7 be called from
gpiolib-based drivers as part of their ”…””}”(hŒ7 be called from
gpiolib-based drivers as part of their ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``.request()``”h]”hŒ
.request()”…””}”(hhhj[	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ and ”…””}”(hŒ and ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``.free()``”h]”hŒ.free()”…””}”(hhhjn	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ semantics.
Likewise the ”…””}”(hŒ semantics.
Likewise the ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ"``pinctrl_gpio_direction_input()``”h]”hŒpinctrl_gpio_direction_input()”…””}”(hhhj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ / ”…””}”(hŒ / ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ#``pinctrl_gpio_direction_output()``”h]”hŒpinctrl_gpio_direction_output()”…””}”(hhhj”	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ-
shall only be called from within respective ”…””}”(hŒ-
shall only be called from within respective ”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``.direction_input()``”h]”hŒ.direction_input()”…””}”(hhhj§	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ /
”…””}”(hŒ /
”hj	  hžhhŸNh NubjÞ  )”}”(hŒ``.direction_output()``”h]”hŒ.direction_output()”…””}”(hhhjº	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj	  ubhŒ gpiolib implementation.”…””}”(hŒ gpiolib implementation.”hj	  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÂhjÏ  hžhubh¸)”}”(hŒÞNOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
that driver request proper muxing and other control for its pins.”h]”(hŒ1NOTE that platforms and individual drivers shall ”…””}”(hŒ1NOTE that platforms and individual drivers shall ”hjÓ	  hžhhŸNh NubjË  )”}”(hŒ*NOT*”h]”hŒNOT”…””}”(hhhjÜ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÊ  hjÓ	  ubhŒ¨ request GPIO pins to be
controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
that driver request proper muxing and other control for its pins.”…””}”(hŒ¨ request GPIO pins to be
controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
that driver request proper muxing and other control for its pins.”hjÓ	  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÉhjÏ  hžhubh¸)”}”(hŒÃThe function list could become long, especially if you can convert every
individual pin into a GPIO pin independent of any other pins, and then try
the approach to define every pin as a function.”h]”hŒÃThe function list could become long, especially if you can convert every
individual pin into a GPIO pin independent of any other pins, and then try
the approach to define every pin as a function.”…””}”(hj÷	  hjõ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÍhjÏ  hžhubh¸)”}”(hŒmIn this case, the function array would become 64 entries for each GPIO
setting and then the device functions.”h]”hŒmIn this case, the function array would become 64 entries for each GPIO
setting and then the device functions.”…””}”(hj
  hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÑhjÏ  hžhubh¸)”}”(hŒ­For this reason there are two functions a pin control driver can implement
to enable only GPIO on an individual pin: ``.gpio_request_enable()`` and
``.gpio_disable_free()``.”h]”(hŒuFor this reason there are two functions a pin control driver can implement
to enable only GPIO on an individual pin: ”…””}”(hŒuFor this reason there are two functions a pin control driver can implement
to enable only GPIO on an individual pin: ”hj
  hžhhŸNh NubjÞ  )”}”(hŒ``.gpio_request_enable()``”h]”hŒ.gpio_request_enable()”…””}”(hhhj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj
  ubhŒ and
”…””}”(hŒ and
”hj
  hžhhŸNh NubjÞ  )”}”(hŒ``.gpio_disable_free()``”h]”hŒ.gpio_disable_free()”…””}”(hhhj-
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj
  ubhŒ.”…””}”(hŒ.”hj
  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÔhjÏ  hžhubh¸)”}”(hŒ¢This function will pass in the affected GPIO range identified by the pin
controller core, so you know which GPIO pins are being affected by the request
operation.”h]”hŒ¢This function will pass in the affected GPIO range identified by the pin
controller core, so you know which GPIO pins are being affected by the request
operation.”…””}”(hjH
  hjF
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MØhjÏ  hžhubh¸)”}”(hXP  If your driver needs to have an indication from the framework of whether the
GPIO pin shall be used for input or output you can implement the
``.gpio_set_direction()`` function. As described this shall be called from the
gpiolib driver and the affected GPIO range, pin offset and desired direction
will be passed along to this function.”h]”(hŒŽIf your driver needs to have an indication from the framework of whether the
GPIO pin shall be used for input or output you can implement the
”…””}”(hŒŽIf your driver needs to have an indication from the framework of whether the
GPIO pin shall be used for input or output you can implement the
”hjT
  hžhhŸNh NubjÞ  )”}”(hŒ``.gpio_set_direction()``”h]”hŒ.gpio_set_direction()”…””}”(hhhj]
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjT
  ubhŒ© function. As described this shall be called from the
gpiolib driver and the affected GPIO range, pin offset and desired direction
will be passed along to this function.”…””}”(hŒ© function. As described this shall be called from the
gpiolib driver and the affected GPIO range, pin offset and desired direction
will be passed along to this function.”hjT
  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÜhjÏ  hžhubh¸)”}”(hX
  Alternatively to using these special functions, it is fully allowed to use
named functions for each GPIO pin, the ``pinctrl_gpio_request()`` will attempt to
obtain the function "gpioN" where "N" is the global GPIO pin number if no
special GPIO-handler is registered.”h]”(hŒrAlternatively to using these special functions, it is fully allowed to use
named functions for each GPIO pin, the ”…””}”(hŒrAlternatively to using these special functions, it is fully allowed to use
named functions for each GPIO pin, the ”hjv
  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_gpio_request()``”h]”hŒpinctrl_gpio_request()”…””}”(hhhj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjv
  ubhŒ† will attempt to
obtain the function â€œgpioNâ€ where â€œNâ€ is the global GPIO pin number if no
special GPIO-handler is registered.”…””}”(hŒ~ will attempt to
obtain the function "gpioN" where "N" is the global GPIO pin number if no
special GPIO-handler is registered.”hjv
  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MâhjÏ  hžhubeh}”(h]”Œ/pin-control-interaction-with-the-gpio-subsystem”ah ]”h"]”Œ/pin control interaction with the gpio subsystem”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M¹Œ
referenced”Kubh¢)”}”(hhh]”(h§)”}”(hŒGPIO mode pitfalls”h]”hŒGPIO mode pitfalls”…””}”(hj¦
  hj¤
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¡
  hžhhŸh¶h Méubh¸)”}”(hX  Due to the naming conventions used by hardware engineers, where "GPIO"
is taken to mean different things than what the kernel does, the developer
may be confused by a datasheet talking about a pin being possible to set
into "GPIO mode". It appears that what hardware engineers mean with
"GPIO mode" is not necessarily the use case that is implied in the kernel
interface ``<linux/gpio/consumer.h>``: a pin that you grab from kernel code and then
either listen for input or drive high/low to assert/deassert some
external line.”h]”(hX  Due to the naming conventions used by hardware engineers, where â€œGPIOâ€
is taken to mean different things than what the kernel does, the developer
may be confused by a datasheet talking about a pin being possible to set
into â€œGPIO modeâ€. It appears that what hardware engineers mean with
â€œGPIO modeâ€ is not necessarily the use case that is implied in the kernel
interface ”…””}”(hXs  Due to the naming conventions used by hardware engineers, where "GPIO"
is taken to mean different things than what the kernel does, the developer
may be confused by a datasheet talking about a pin being possible to set
into "GPIO mode". It appears that what hardware engineers mean with
"GPIO mode" is not necessarily the use case that is implied in the kernel
interface ”hj²
  hžhhŸNh NubjÞ  )”}”(hŒ``<linux/gpio/consumer.h>``”h]”hŒ<linux/gpio/consumer.h>”…””}”(hhhj»
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj²
  ubhŒ€: a pin that you grab from kernel code and then
either listen for input or drive high/low to assert/deassert some
external line.”…””}”(hŒ€: a pin that you grab from kernel code and then
either listen for input or drive high/low to assert/deassert some
external line.”hj²
  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mëhj¡
  hžhubh¸)”}”(hŒãRather hardware engineers think that "GPIO mode" means that you can
software-control a few electrical properties of the pin that you would
not be able to control if the pin was in some other mode, such as muxed in
for a device.”h]”hŒçRather hardware engineers think that â€œGPIO modeâ€ means that you can
software-control a few electrical properties of the pin that you would
not be able to control if the pin was in some other mode, such as muxed in
for a device.”…””}”(hjÖ
  hjÔ
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Môhj¡
  hžhubh¸)”}”(hŒ¡The GPIO portions of a pin and its relation to a certain pin controller
configuration and muxing logic can be constructed in several ways. Here
are two examples.”h]”hŒ¡The GPIO portions of a pin and its relation to a certain pin controller
configuration and muxing logic can be constructed in several ways. Here
are two examples.”…””}”(hjä
  hjâ
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mùhj¡
  hžhubh¸)”}”(hŒExample **(A)**::”h]”(hŒExample ”…””}”(hŒExample ”hjð
  hžhhŸNh NubhŒstrong”“”)”}”(hŒ**(A)**”h]”hŒ(A)”…””}”(hhhjû
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jù
  hjð
  ubhŒ:”…””}”(hŒ:”hjð
  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mýhj¡
  hžhubj¢  )”}”(hXE                    pin config
                  logic regs
                  |               +- SPI
Physical pins --- pad --- pinmux -+- I2C
                          |       +- mmc
                          |       +- GPIO
                          pin
                          multiplex
                          logic regs”h]”hXE                    pin config
                  logic regs
                  |               +- SPI
Physical pins --- pad --- pinmux -+- I2C
                          |       +- mmc
                          |       +- GPIO
                          pin
                          multiplex
                          logic regs”…””}”(hhhj  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  uh1j¡  hŸh¶h Mÿhj¡
  hžhubh¸)”}”(hXˆ  Here some electrical properties of the pin can be configured no matter
whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
pin, you can also drive it high/low from "GPIO" registers.
Alternatively, the pin can be controlled by a certain peripheral, while
still applying desired pin config properties. GPIO functionality is thus
orthogonal to any other device using the pin.”h]”hXŒ  Here some electrical properties of the pin can be configured no matter
whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
pin, you can also drive it high/low from â€œGPIOâ€ registers.
Alternatively, the pin can be controlled by a certain peripheral, while
still applying desired pin config properties. GPIO functionality is thus
orthogonal to any other device using the pin.”…””}”(hj$  hj"  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M	hj¡
  hžhubh¸)”}”(hXc  In this arrangement the registers for the GPIO portions of the pin controller,
or the registers for the GPIO hardware module are likely to reside in a
separate memory range only intended for GPIO driving, and the register
range dealing with pin config and pin multiplexing get placed into a
different memory range and a separate section of the data sheet.”h]”hXc  In this arrangement the registers for the GPIO portions of the pin controller,
or the registers for the GPIO hardware module are likely to reside in a
separate memory range only intended for GPIO driving, and the register
range dealing with pin config and pin multiplexing get placed into a
different memory range and a separate section of the data sheet.”…””}”(hj2  hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¡
  hžhubh¸)”}”(hŒßA flag "strict" in struct pinmux_ops is available to check and deny
simultaneous access to the same pin from GPIO and pin multiplexing
consumers on hardware of this type. The pinctrl driver should set this flag
accordingly.”h]”hŒãA flag â€œstrictâ€ in struct pinmux_ops is available to check and deny
simultaneous access to the same pin from GPIO and pin multiplexing
consumers on hardware of this type. The pinctrl driver should set this flag
accordingly.”…””}”(hj@  hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¡
  hžhubh¸)”}”(hŒExample **(B)**::”h]”(hŒExample ”…””}”(hŒExample ”hjL  hžhhŸNh Nubjú
  )”}”(hŒ**(B)**”h]”hŒ(B)”…””}”(hhhjU  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jù
  hjL  ubhŒ:”…””}”(hj  hjL  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¡
  hžhubj¢  )”}”(hX7                    pin config
                  logic regs
                  |               +- SPI
Physical pins --- pad --- pinmux -+- I2C
                  |       |       +- mmc
                  |       |
                  GPIO    pin
                          multiplex
                          logic regs”h]”hX7                    pin config
                  logic regs
                  |               +- SPI
Physical pins --- pad --- pinmux -+- I2C
                  |       |       +- mmc
                  |       |
                  GPIO    pin
                          multiplex
                          logic regs”…””}”(hhhjm  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  uh1j¡  hŸh¶h Mhj¡
  hžhubh¸)”}”(hXá  In this arrangement, the GPIO functionality can always be enabled, such that
e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
pulsed out. It is likely possible to disrupt the traffic on the pin by doing
wrong things on the GPIO block, as it is never really disconnected. It is
possible that the GPIO, pin config and pin multiplex registers are placed into
the same memory range and the same section of the data sheet, although that
need not be the case.”h]”hXå  In this arrangement, the GPIO functionality can always be enabled, such that
e.g. a GPIO input can be used to â€œspyâ€ on the SPI/I2C/MMC signal while it is
pulsed out. It is likely possible to disrupt the traffic on the pin by doing
wrong things on the GPIO block, as it is never really disconnected. It is
possible that the GPIO, pin config and pin multiplex registers are placed into
the same memory range and the same section of the data sheet, although that
need not be the case.”…””}”(hj}  hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M'hj¡
  hžhubh¸)”}”(hX  In some pin controllers, although the physical pins are designed in the same
way as (B), the GPIO function still can't be enabled at the same time as the
peripheral functions. So again the "strict" flag should be set, denying
simultaneous activation by GPIO and other muxed in devices.”h]”hX#  In some pin controllers, although the physical pins are designed in the same
way as (B), the GPIO function still canâ€™t be enabled at the same time as the
peripheral functions. So again the â€œstrictâ€ flag should be set, denying
simultaneous activation by GPIO and other muxed in devices.”…””}”(hj‹  hj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M/hj¡
  hžhubh¸)”}”(hŒ}From a kernel point of view, however, these are different aspects of the
hardware and shall be put into different subsystems:”h]”hŒ}From a kernel point of view, however, these are different aspects of the
hardware and shall be put into different subsystems:”…””}”(hj™  hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M4hj¡
  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hŒÊRegisters (or fields within registers) that control electrical
properties of the pin such as biasing and drive strength should be
exposed through the pinctrl subsystem, as "pin configuration" settings.
”h]”h¸)”}”(hŒÉRegisters (or fields within registers) that control electrical
properties of the pin such as biasing and drive strength should be
exposed through the pinctrl subsystem, as "pin configuration" settings.”h]”hŒÍRegisters (or fields within registers) that control electrical
properties of the pin such as biasing and drive strength should be
exposed through the pinctrl subsystem, as â€œpin configurationâ€ settings.”…””}”(hj®  hj¬  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M7hj¨  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj¥  hžhhŸh¶h NubhÛ)”}”(hŒÉRegisters (or fields within registers) that control muxing of signals
from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
be exposed through the pinctrl subsystem, as mux functions.
”h]”h¸)”}”(hŒÈRegisters (or fields within registers) that control muxing of signals
from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
be exposed through the pinctrl subsystem, as mux functions.”h]”hŒÈRegisters (or fields within registers) that control muxing of signals
from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
be exposed through the pinctrl subsystem, as mux functions.”…””}”(hjÆ  hjÄ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M;hjÀ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj¥  hžhhŸh¶h NubhÛ)”}”(hX*  Registers (or fields within registers) that control GPIO functionality
such as setting a GPIO's output value, reading a GPIO's input value, or
setting GPIO pin direction should be exposed through the GPIO subsystem,
and if they also support interrupt capabilities, through the irqchip
abstraction.
”h]”h¸)”}”(hX)  Registers (or fields within registers) that control GPIO functionality
such as setting a GPIO's output value, reading a GPIO's input value, or
setting GPIO pin direction should be exposed through the GPIO subsystem,
and if they also support interrupt capabilities, through the irqchip
abstraction.”h]”hX-  Registers (or fields within registers) that control GPIO functionality
such as setting a GPIOâ€™s output value, reading a GPIOâ€™s input value, or
setting GPIO pin direction should be exposed through the GPIO subsystem,
and if they also support interrupt capabilities, through the irqchip
abstraction.”…””}”(hjÞ  hjÜ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M?hjØ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj¥  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h M7hj¡
  hžhubh¸)”}”(hXˆ  Depending on the exact HW register design, some functions exposed by the
GPIO subsystem may call into the pinctrl subsystem in order to
coordinate register settings across HW modules. In particular, this may
be needed for HW with separate GPIO and pin controller HW modules, where
e.g. GPIO direction is determined by a register in the pin controller HW
module rather than the GPIO HW module.”h]”hXˆ  Depending on the exact HW register design, some functions exposed by the
GPIO subsystem may call into the pinctrl subsystem in order to
coordinate register settings across HW modules. In particular, this may
be needed for HW with separate GPIO and pin controller HW modules, where
e.g. GPIO direction is determined by a register in the pin controller HW
module rather than the GPIO HW module.”…””}”(hjø  hjö  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MEhj¡
  hžhubh¸)”}”(hX  Electrical properties of the pin such as biasing and drive strength
may be placed at some pin-specific register in all cases or as part
of the GPIO register in case (B) especially. This doesn't mean that such
properties necessarily pertain to what the Linux kernel calls "GPIO".”h]”hX  Electrical properties of the pin such as biasing and drive strength
may be placed at some pin-specific register in all cases or as part
of the GPIO register in case (B) especially. This doesnâ€™t mean that such
properties necessarily pertain to what the Linux kernel calls â€œGPIOâ€.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MLhj¡
  hžhubh¸)”}”(hŒ‘Example: a pin is usually muxed in to be used as a UART TX line. But during
system sleep, we need to put this pin into "GPIO mode" and ground it.”h]”hŒ•Example: a pin is usually muxed in to be used as a UART TX line. But during
system sleep, we need to put this pin into â€œGPIO modeâ€ and ground it.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MQhj¡
  hžhubh¸)”}”(hX'  If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
to think that you need to come up with something really complex, that the
pin shall be used for UART TX and GPIO at the same time, that you will grab
a pin control handle and set it to a certain state to enable UART TX to be
muxed in, then twist it over to GPIO mode and use gpiod_direction_output()
to drive it low during sleep, then mux it over to UART TX again when you
wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This
all gets very complicated.”h]”hX'  If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
to think that you need to come up with something really complex, that the
pin shall be used for UART TX and GPIO at the same time, that you will grab
a pin control handle and set it to a certain state to enable UART TX to be
muxed in, then twist it over to GPIO mode and use gpiod_direction_output()
to drive it low during sleep, then mux it over to UART TX again when you
wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This
all gets very complicated.”…””}”(hj"  hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MThj¡
  hžhubh¸)”}”(hX  The solution is to not think that what the datasheet calls "GPIO mode"
has to be handled by the ``<linux/gpio/consumer.h>`` interface. Instead view this as
a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
and you find this in the documentation:”h]”(hŒdThe solution is to not think that what the datasheet calls â€œGPIO modeâ€
has to be handled by the ”…””}”(hŒ`The solution is to not think that what the datasheet calls "GPIO mode"
has to be handled by the ”hj.  hžhhŸNh NubjÞ  )”}”(hŒ``<linux/gpio/consumer.h>``”h]”hŒ<linux/gpio/consumer.h>”…””}”(hhhj7  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj.  ubhŒL interface. Instead view this as
a certain pin config setting. Look in e.g. ”…””}”(hŒL interface. Instead view this as
a certain pin config setting. Look in e.g. ”hj.  hžhhŸNh NubjÞ  )”}”(hŒ%``<linux/pinctrl/pinconf-generic.h>``”h]”hŒ!<linux/pinctrl/pinconf-generic.h>”…””}”(hhhjJ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj.  ubhŒ(
and you find this in the documentation:”…””}”(hŒ(
and you find this in the documentation:”hj.  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M]hj¡
  hžhubhŒblock_quote”“”)”}”(hhh]”j  )”}”(hhh]”j  )”}”(hŒƒPIN_CONFIG_OUTPUT:
this will configure the pin in output, use argument
1 to indicate high level, argument 0 to indicate low level.
”h]”(j  )”}”(hŒPIN_CONFIG_OUTPUT:”h]”hŒPIN_CONFIG_OUTPUT:”…””}”(hjq  hjo  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Mdhjk  ubj*  )”}”(hhh]”h¸)”}”(hŒothis will configure the pin in output, use argument
1 to indicate high level, argument 0 to indicate low level.”h]”hŒothis will configure the pin in output, use argument
1 to indicate high level, argument 0 to indicate low level.”…””}”(hj‚  hj€  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mchj}  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j)  hjk  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh¶h Mdhjh  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hje  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jc  hj¡
  hžhhŸNh Nubh¸)”}”(hŒ«So it is perfectly possible to push a pin into "GPIO mode" and drive the
line low as part of the usual pin control map. So for example your UART
driver may look like this:”h]”hŒ¯So it is perfectly possible to push a pin into â€œGPIO modeâ€ and drive the
line low as part of the usual pin control map. So for example your UART
driver may look like this:”…””}”(hj¨  hj¦  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mfhj¡
  hžhubj¢  )”}”(hX²  #include <linux/pinctrl/consumer.h>

struct pinctrl          *pinctrl;
struct pinctrl_state    *pins_default;
struct pinctrl_state    *pins_sleep;

pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);

/* Normal mode */
retval = pinctrl_select_state(pinctrl, pins_default);

/* Sleep mode */
retval = pinctrl_select_state(pinctrl, pins_sleep);”h]”hX²  #include <linux/pinctrl/consumer.h>

struct pinctrl          *pinctrl;
struct pinctrl_state    *pins_default;
struct pinctrl_state    *pins_sleep;

pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);

/* Normal mode */
retval = pinctrl_select_state(pinctrl, pins_default);

/* Sleep mode */
retval = pinctrl_select_state(pinctrl, pins_sleep);”…””}”(hhhj´  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mjhj¡
  hžhubh¸)”}”(hŒ2And your machine configuration may look like this:”h]”hŒ2And your machine configuration may look like this:”…””}”(hjÅ  hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M{hj¡
  hžhubj¢  )”}”(hXK  static unsigned long uart_default_mode[] = {
        PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
};

static unsigned long uart_sleep_mode[] = {
        PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
};

static struct pinctrl_map pinmap[] __initdata = {
        PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                          "u0_group", "u0"),
        PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                            "UART_TX_PIN", uart_default_mode),
        PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                          "u0_group", "gpio-mode"),
        PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                            "UART_TX_PIN", uart_sleep_mode),
};

foo_init(void)
{
        pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
}”h]”hXK  static unsigned long uart_default_mode[] = {
        PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
};

static unsigned long uart_sleep_mode[] = {
        PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
};

static struct pinctrl_map pinmap[] __initdata = {
        PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                          "u0_group", "u0"),
        PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                            "UART_TX_PIN", uart_default_mode),
        PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                          "u0_group", "gpio-mode"),
        PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                            "UART_TX_PIN", uart_sleep_mode),
};

foo_init(void)
{
        pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
}”…””}”(hhhjÑ  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M}hj¡
  hžhubh¸)”}”(hX,  Here the pins we want to control are in the "u0_group" and there is some
function called "u0" that can be enabled on this group of pins, and then
everything is UART business as usual. But there is also some function
named "gpio-mode" that can be mapped onto the same pins to move them into
GPIO mode.”h]”hX8  Here the pins we want to control are in the â€œu0_groupâ€ and there is some
function called â€œu0â€ that can be enabled on this group of pins, and then
everything is UART business as usual. But there is also some function
named â€œgpio-modeâ€ that can be mapped onto the same pins to move them into
GPIO mode.”…””}”(hjâ  hjà  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M—hj¡
  hžhubh¸)”}”(hXø  This will give the desired effect without any bogus interaction with the
GPIO subsystem. It is just an electrical configuration used by that device
when going to sleep, it might imply that the pin is set into something the
datasheet calls "GPIO mode", but that is not the point: it is still used
by that UART device to control the pins that pertain to that very UART
driver, putting them into modes needed by the UART. GPIO in the Linux
kernel sense are just some 1-bit line, and is a different use case.”h]”hXü  This will give the desired effect without any bogus interaction with the
GPIO subsystem. It is just an electrical configuration used by that device
when going to sleep, it might imply that the pin is set into something the
datasheet calls â€œGPIO modeâ€, but that is not the point: it is still used
by that UART device to control the pins that pertain to that very UART
driver, putting them into modes needed by the UART. GPIO in the Linux
kernel sense are just some 1-bit line, and is a different use case.”…””}”(hjð  hjî  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj¡
  hžhubh¸)”}”(hŒ²How the registers are poked to attain the push or pull, and output low
configuration and the muxing of the "u0" or "gpio-mode" group onto these
pins is a question for the driver.”h]”hŒºHow the registers are poked to attain the push or pull, and output low
configuration and the muxing of the â€œu0â€ or â€œgpio-modeâ€ group onto these
pins is a question for the driver.”…””}”(hjþ  hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¥hj¡
  hžhubh¸)”}”(hX`  Some datasheets will be more helpful and refer to the "GPIO mode" as
"low power mode" rather than anything to do with GPIO. This often means
the same thing electrically speaking, but in this latter case the
software engineers will usually quickly identify that this is some
specific muxing or configuration rather than anything related to the GPIO
API.”h]”hXh  Some datasheets will be more helpful and refer to the â€œGPIO modeâ€ as
â€œlow power modeâ€ rather than anything to do with GPIO. This often means
the same thing electrically speaking, but in this latter case the
software engineers will usually quickly identify that this is some
specific muxing or configuration rather than anything related to the GPIO
API.”…””}”(hj  hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M©hj¡
  hžhubeh}”(h]”j	  ah ]”h"]”Œgpio mode pitfalls”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Méj 
  Kubh¢)”}”(hhh]”(h§)”}”(hŒBoard/machine configuration”h]”hŒBoard/machine configuration”…””}”(hj$  hj"  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h M²ubh¸)”}”(hŒêBoards and machines define how a certain complete running system is put
together, including how GPIOs and devices are muxed, how regulators are
constrained and how the clock tree looks. Of course pinmux settings are also
part of this.”h]”hŒêBoards and machines define how a certain complete running system is put
together, including how GPIOs and devices are muxed, how regulators are
constrained and how the clock tree looks. Of course pinmux settings are also
part of this.”…””}”(hj2  hj0  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M´hj  hžhubh¸)”}”(hŒÂA pin controller configuration for a machine looks pretty much like a simple
regulator configuration, so for the example array above we want to enable i2c
and spi on the second function mapping:”h]”hŒÂA pin controller configuration for a machine looks pretty much like a simple
regulator configuration, so for the example array above we want to enable i2c
and spi on the second function mapping:”…””}”(hj@  hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¹hj  hžhubj¢  )”}”(hXN  #include <linux/pinctrl/machine.h>

static const struct pinctrl_map mapping[] __initconst = {
        {
                .dev_name = "foo-spi.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "spi0",
        },
        {
                .dev_name = "foo-i2c.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "i2c0",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "mmc0",
        },
};”h]”hXN  #include <linux/pinctrl/machine.h>

static const struct pinctrl_map mapping[] __initconst = {
        {
                .dev_name = "foo-spi.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "spi0",
        },
        {
                .dev_name = "foo-i2c.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "i2c0",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .data.mux.function = "mmc0",
        },
};”…””}”(hhhjL  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M½hj  hžhubh¸)”}”(hŒéThe dev_name here matches to the unique device name that can be used to look
up the device struct (just like with clockdev or regulators). The function name
must match a function provided by the pinmux driver handling this pin range.”h]”hŒéThe dev_name here matches to the unique device name that can be used to look
up the device struct (just like with clockdev or regulators). The function name
must match a function provided by the pinmux driver handling this pin range.”…””}”(hj]  hj[  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÙhj  hžhubh¸)”}”(hŒ•As you can see we may have several pin controllers on the system and thus
we need to specify which one of them contains the functions we wish to map.”h]”hŒ•As you can see we may have several pin controllers on the system and thus
we need to specify which one of them contains the functions we wish to map.”…””}”(hjk  hji  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÝhj  hžhubh¸)”}”(hŒCYou register this pinmux mapping to the pinmux subsystem by simply:”h]”hŒCYou register this pinmux mapping to the pinmux subsystem by simply:”…””}”(hjy  hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Màhj  hžhubj¢  )”}”(hŒ>ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));”h]”hŒ>ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));”…””}”(hhhj…  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mâhj  hžhubh¸)”}”(hŒ²Since the above construct is pretty common there is a helper macro to make
it even more compact which assumes you want to use pinctrl-foo and position
0 for mapping, for example:”h]”hŒ²Since the above construct is pretty common there is a helper macro to make
it even more compact which assumes you want to use pinctrl-foo and position
0 for mapping, for example:”…””}”(hj–  hj”  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mæhj  hžhubj¢  )”}”(hŒ«static struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT,
                          "pinctrl-foo", NULL, "i2c0"),
};”h]”hŒ«static struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT,
                          "pinctrl-foo", NULL, "i2c0"),
};”…””}”(hhhj¢  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mêhj  hžhubh¸)”}”(hX)  The mapping table may also contain pin configuration entries. It's common for
each pin/group to have a number of configuration entries that affect it, so
the table entries for configuration reference an array of config parameters
and values. An example using the convenience macros is shown below:”h]”hX+  The mapping table may also contain pin configuration entries. Itâ€™s common for
each pin/group to have a number of configuration entries that affect it, so
the table entries for configuration reference an array of config parameters
and values. An example using the convenience macros is shown below:”…””}”(hj³  hj±  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mñhj  hžhubj¢  )”}”(hX  static unsigned long i2c_grp_configs[] = {
        FOO_PIN_DRIVEN,
        FOO_PIN_PULLUP,
};

static unsigned long i2c_pin_configs[] = {
        FOO_OPEN_COLLECTOR,
        FOO_SLEW_RATE_SLOW,
};

static struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                          "pinctrl-foo", "i2c0", "i2c0"),
        PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                              "pinctrl-foo", "i2c0", i2c_grp_configs),
        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                            "pinctrl-foo", "i2c0scl", i2c_pin_configs),
        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                            "pinctrl-foo", "i2c0sda", i2c_pin_configs),
};”h]”hX  static unsigned long i2c_grp_configs[] = {
        FOO_PIN_DRIVEN,
        FOO_PIN_PULLUP,
};

static unsigned long i2c_pin_configs[] = {
        FOO_OPEN_COLLECTOR,
        FOO_SLEW_RATE_SLOW,
};

static struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                          "pinctrl-foo", "i2c0", "i2c0"),
        PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                              "pinctrl-foo", "i2c0", i2c_grp_configs),
        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                            "pinctrl-foo", "i2c0scl", i2c_pin_configs),
        PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                            "pinctrl-foo", "i2c0sda", i2c_pin_configs),
};”…””}”(hhhj¿  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Möhj  hžhubh¸)”}”(hXÄ  Finally, some devices expect the mapping table to contain certain specific
named states. When running on hardware that doesn't need any pin controller
configuration, the mapping table must still contain those named states, in
order to explicitly indicate that the states were provided and intended to
be empty. Table entry macro ``PIN_MAP_DUMMY_STATE()`` serves the purpose of defining
a named state without causing any pin controller to be programmed:”h]”(hXK  Finally, some devices expect the mapping table to contain certain specific
named states. When running on hardware that doesnâ€™t need any pin controller
configuration, the mapping table must still contain those named states, in
order to explicitly indicate that the states were provided and intended to
be empty. Table entry macro ”…””}”(hXI  Finally, some devices expect the mapping table to contain certain specific
named states. When running on hardware that doesn't need any pin controller
configuration, the mapping table must still contain those named states, in
order to explicitly indicate that the states were provided and intended to
be empty. Table entry macro ”hjÎ  hžhhŸNh NubjÞ  )”}”(hŒ``PIN_MAP_DUMMY_STATE()``”h]”hŒPIN_MAP_DUMMY_STATE()”…””}”(hhhj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÎ  ubhŒb serves the purpose of defining
a named state without causing any pin controller to be programmed:”…””}”(hŒb serves the purpose of defining
a named state without causing any pin controller to be programmed:”hjÎ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj  hžhubj¢  )”}”(hŒvstatic struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
};”h]”hŒvstatic struct pinctrl_map mapping[] __initdata = {
        PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
};”…””}”(hhhjð  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mhj  hžhubeh}”(h]”j  ah ]”h"]”Œboard/machine configuration”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M²j 
  Kubh¢)”}”(hhh]”(h§)”}”(hŒComplex mappings”h]”hŒComplex mappings”…””}”(hj  hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h Mubh¸)”}”(hŒnAs it is possible to map a function to different groups of pins an optional
.group can be specified like this:”h]”hŒnAs it is possible to map a function to different groups of pins an optional
.group can be specified like this:”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj  hžhubj¢  )”}”(hX¥  ...
{
        .dev_name = "foo-spi.0",
        .name = "spi0-pos-A",
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_0_grp",
},
{
        .dev_name = "foo-spi.0",
        .name = "spi0-pos-B",
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_1_grp",
},
...”h]”hX¥  ...
{
        .dev_name = "foo-spi.0",
        .name = "spi0-pos-A",
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_0_grp",
},
{
        .dev_name = "foo-spi.0",
        .name = "spi0-pos-B",
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_1_grp",
},
...”…””}”(hhhj%  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M!hj  hžhubh¸)”}”(hŒ”This example mapping is used to switch between two positions for spi0 at
runtime, as described further below under the heading `Runtime pinmuxing`_.”h]”(hŒThis example mapping is used to switch between two positions for spi0 at
runtime, as described further below under the heading ”…””}”(hŒThis example mapping is used to switch between two positions for spi0 at
runtime, as described further below under the heading ”hj4  hžhhŸNh Nubjð  )”}”(hŒ`Runtime pinmuxing`_”h]”hŒRuntime pinmuxing”…””}”(hŒRuntime pinmuxing”hj=  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒRuntime pinmuxing”j  Œruntime-pinmuxing”uh1jï  hj4  j  KubhŒ.”…””}”(hj?
  hj4  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M6hj  hžhubh¸)”}”(hXT  Further it is possible for one named state to affect the muxing of several
groups of pins, say for example in the mmc0 example above, where you can
additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the
case), we define a mapping like this:”h]”hXT  Further it is possible for one named state to affect the muxing of several
groups of pins, say for example in the mmc0 example above, where you can
additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the
case), we define a mapping like this:”…””}”(hj[  hjY  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M9hj  hžhubj¢  )”}”(hX·  ...
{
        .dev_name = "foo-mmc.0",
        .name = "2bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "4bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "4bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_2_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_2_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_3_grp",
},
...”h]”hX·  ...
{
        .dev_name = "foo-mmc.0",
        .name = "2bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "4bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "4bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_2_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_1_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_2_grp",
},
{
        .dev_name = "foo-mmc.0",
        .name = "8bit"
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
        .group = "mmc0_3_grp",
},
...”…””}”(hhhjg  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M?hj  hžhubh¸)”}”(hŒbThe result of grabbing this mapping from the device with something like
this (see next paragraph):”h]”hŒbThe result of grabbing this mapping from the device with something like
this (see next paragraph):”…””}”(hjx  hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mthj  hžhubj¢  )”}”(hŒap = devm_pinctrl_get(dev);
s = pinctrl_lookup_state(p, "8bit");
ret = pinctrl_select_state(p, s);”h]”hŒap = devm_pinctrl_get(dev);
s = pinctrl_lookup_state(p, "8bit");
ret = pinctrl_select_state(p, s);”…””}”(hhhj„  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mwhj  hžhubh¸)”}”(hŒor more simply:”h]”hŒor more simply:”…””}”(hj•  hj“  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M}hj  hžhubj¢  )”}”(hŒ)p = devm_pinctrl_get_select(dev, "8bit");”h]”hŒ)p = devm_pinctrl_get_select(dev, "8bit");”…””}”(hhhj¡  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mhj  hžhubh¸)”}”(hX9  Will be that you activate all the three bottom records in the mapping at
once. Since they share the same name, pin controller device, function and
device, and since we allow multiple groups to match to a single device, they
all get selected, and they all get enabled and disable simultaneously by the
pinmux core.”h]”hX9  Will be that you activate all the three bottom records in the mapping at
once. Since they share the same name, pin controller device, function and
device, and since we allow multiple groups to match to a single device, they
all get selected, and they all get enabled and disable simultaneously by the
pinmux core.”…””}”(hj²  hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mƒhj  hžhubeh}”(h]”Œcomplex-mappings”ah ]”h"]”Œcomplex mappings”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Mubh¢)”}”(hhh]”(h§)”}”(hŒ!Pin control requests from drivers”h]”hŒ!Pin control requests from drivers”…””}”(hjË  hjÉ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÆ  hžhhŸh¶h M‹ubh¸)”}”(hX’  When a device driver is about to probe the device core will automatically
attempt to issue ``pinctrl_get_select_default()`` on these devices.
This way driver writers do not need to add any of the boilerplate code
of the type found below. However when doing fine-grained state selection
and not using the "default" state, you may have to do some device driver
handling of the pinctrl handles and states.”h]”(hŒ[When a device driver is about to probe the device core will automatically
attempt to issue ”…””}”(hŒ[When a device driver is about to probe the device core will automatically
attempt to issue ”hj×  hžhhŸNh NubjÞ  )”}”(hŒ ``pinctrl_get_select_default()``”h]”hŒpinctrl_get_select_default()”…””}”(hhhjà  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj×  ubhX   on these devices.
This way driver writers do not need to add any of the boilerplate code
of the type found below. However when doing fine-grained state selection
and not using the â€œdefaultâ€ state, you may have to do some device driver
handling of the pinctrl handles and states.”…””}”(hX   on these devices.
This way driver writers do not need to add any of the boilerplate code
of the type found below. However when doing fine-grained state selection
and not using the "default" state, you may have to do some device driver
handling of the pinctrl handles and states.”hj×  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MhjÆ  hžhubh¸)”}”(hŒÜSo if you just want to put the pins for a certain device into the default
state and be done with it, there is nothing you need to do besides
providing the proper mapping table. The device core will take care of
the rest.”h]”hŒÜSo if you just want to put the pins for a certain device into the default
state and be done with it, there is nothing you need to do besides
providing the proper mapping table. The device core will take care of
the rest.”…””}”(hjû  hjù  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M”hjÆ  •¦      hžhubh¸)”}”(hXS  Generally it is discouraged to let individual drivers get and enable pin
control. So if possible, handle the pin control in platform code or some other
place where you have access to all the affected struct device * pointers. In
some cases where a driver needs to e.g. switch between different mux mappings
at runtime this is not possible.”h]”hXS  Generally it is discouraged to let individual drivers get and enable pin
control. So if possible, handle the pin control in platform code or some other
place where you have access to all the affected struct device * pointers. In
some cases where a driver needs to e.g. switch between different mux mappings
at runtime this is not possible.”…””}”(hj	  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M™hjÆ  hžhubh¸)”}”(hŒöA typical case is if a driver needs to switch bias of pins from normal
operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to
``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save
current in sleep mode.”h]”(hŒuA typical case is if a driver needs to switch bias of pins from normal
operation and going to sleep, moving from the ”…””}”(hŒuA typical case is if a driver needs to switch bias of pins from normal
operation and going to sleep, moving from the ”hj  hžhhŸNh NubjÞ  )”}”(hŒ``PINCTRL_STATE_DEFAULT``”h]”hŒPINCTRL_STATE_DEFAULT”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj  ubhŒ to
”…””}”(hŒ to
”hj  hžhhŸNh NubjÞ  )”}”(hŒ``PINCTRL_STATE_SLEEP``”h]”hŒPINCTRL_STATE_SLEEP”…””}”(hhhj1  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj  ubhŒM at runtime, re-biasing or even re-muxing pins to save
current in sleep mode.”…””}”(hŒM at runtime, re-biasing or even re-muxing pins to save
current in sleep mode.”hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MŸhjÆ  hžhubh¸)”}”(hŒgA driver may request a certain control state to be activated, usually just the
default state like this:”h]”hŒgA driver may request a certain control state to be activated, usually just the
default state like this:”…””}”(hjL  hjJ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¤hjÆ  hžhubj¢  )”}”(hXï  #include <linux/pinctrl/consumer.h>

struct foo_state {
struct pinctrl *p;
struct pinctrl_state *s;
...
};

foo_probe()
{
        /* Allocate a state holder named "foo" etc */
        struct foo_state *foo = ...;

        foo->p = devm_pinctrl_get(&device);
        if (IS_ERR(foo->p)) {
                /* FIXME: clean up "foo" here */
                return PTR_ERR(foo->p);
        }

        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
        if (IS_ERR(foo->s)) {
                /* FIXME: clean up "foo" here */
                return PTR_ERR(foo->s);
        }

        ret = pinctrl_select_state(foo->p, foo->s);
        if (ret < 0) {
                /* FIXME: clean up "foo" here */
                return ret;
        }
}”h]”hXï  #include <linux/pinctrl/consumer.h>

struct foo_state {
struct pinctrl *p;
struct pinctrl_state *s;
...
};

foo_probe()
{
        /* Allocate a state holder named "foo" etc */
        struct foo_state *foo = ...;

        foo->p = devm_pinctrl_get(&device);
        if (IS_ERR(foo->p)) {
                /* FIXME: clean up "foo" here */
                return PTR_ERR(foo->p);
        }

        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
        if (IS_ERR(foo->s)) {
                /* FIXME: clean up "foo" here */
                return PTR_ERR(foo->s);
        }

        ret = pinctrl_select_state(foo->p, foo->s);
        if (ret < 0) {
                /* FIXME: clean up "foo" here */
                return ret;
        }
}”…””}”(hhhjX  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M§hjÆ  hžhubh¸)”}”(hŒ­This get/lookup/select/put sequence can just as well be handled by bus drivers
if you don't want each and every driver to handle it and you know the
arrangement on your bus.”h]”hŒ¯This get/lookup/select/put sequence can just as well be handled by bus drivers
if you donâ€™t want each and every driver to handle it and you know the
arrangement on your bus.”…””}”(hji  hjg  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÉhjÆ  hžhubh¸)”}”(hŒ&The semantics of the pinctrl APIs are:”h]”hŒ&The semantics of the pinctrl APIs are:”…””}”(hjw  hju  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÍhjÆ  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hX  ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl
information for a given client device. It will allocate a struct from the
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.
”h]”h¸)”}”(hX  ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl
information for a given client device. It will allocate a struct from the
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.”h]”(jÞ  )”}”(hŒ``pinctrl_get()``”h]”hŒpinctrl_get()”…””}”(hhhjŽ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjŠ  ubhX   is called in process context to obtain a handle to all pinctrl
information for a given client device. It will allocate a struct from the
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.”…””}”(hX   is called in process context to obtain a handle to all pinctrl
information for a given client device. It will allocate a struct from the
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.”hjŠ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÏhj†  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h NubhÛ)”}”(hŒó``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()``
to be called automatically on the retrieved pointer when the associated
device is removed. It is recommended to use this function over plain
``pinctrl_get()``.
”h]”h¸)”}”(hŒò``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()``
to be called automatically on the retrieved pointer when the associated
device is removed. It is recommended to use this function over plain
``pinctrl_get()``.”h]”(jÞ  )”}”(hŒ``devm_pinctrl_get()``”h]”hŒdevm_pinctrl_get()”…””}”(hhhjµ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj±  ubhŒ+ is a variant of pinctrl_get() that causes ”…””}”(hŒ+ is a variant of pinctrl_get() that causes ”hj±  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_put()``”h]”hŒpinctrl_put()”…””}”(hhhjÈ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj±  ubhŒŽ
to be called automatically on the retrieved pointer when the associated
device is removed. It is recommended to use this function over plain
”…””}”(hŒŽ
to be called automatically on the retrieved pointer when the associated
device is removed. It is recommended to use this function over plain
”hj±  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_get()``”h]”hŒpinctrl_get()”…””}”(hhhjÛ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj±  ubhŒ.”…””}”(hj?
  hj±  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÔhj­  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h NubhÛ)”}”(hŒ•``pinctrl_lookup_state()`` is called in process context to obtain a handle to a
specific state for a client device. This operation may be slow, too.
”h]”h¸)”}”(hŒ”``pinctrl_lookup_state()`` is called in process context to obtain a handle to a
specific state for a client device. This operation may be slow, too.”h]”(jÞ  )”}”(hŒ``pinctrl_lookup_state()``”h]”hŒpinctrl_lookup_state()”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjý  ubhŒz is called in process context to obtain a handle to a
specific state for a client device. This operation may be slow, too.”…””}”(hŒz is called in process context to obtain a handle to a
specific state for a client device. This operation may be slow, too.”hjý  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÙhjù  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h NubhÛ)”}”(hX·  ``pinctrl_select_state()`` programs pin controller hardware according to the
definition of the state as given by the mapping table. In theory, this is a
fast-path operation, since it only involved blasting some register settings
into hardware. However, note that some pin controllers may have their
registers on a slow/IRQ-based bus, so client devices should not assume they
can call ``pinctrl_select_state()`` from non-blocking contexts.
”h]”h¸)”}”(hX¶  ``pinctrl_select_state()`` programs pin controller hardware according to the
definition of the state as given by the mapping table. In theory, this is a
fast-path operation, since it only involved blasting some register settings
into hardware. However, note that some pin controllers may have their
registers on a slow/IRQ-based bus, so client devices should not assume they
can call ``pinctrl_select_state()`` from non-blocking contexts.”h]”(jÞ  )”}”(hŒ``pinctrl_select_state()``”h]”hŒpinctrl_select_state()”…””}”(hhhj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj$  ubhXf   programs pin controller hardware according to the
definition of the state as given by the mapping table. In theory, this is a
fast-path operation, since it only involved blasting some register settings
into hardware. However, note that some pin controllers may have their
registers on a slow/IRQ-based bus, so client devices should not assume they
can call ”…””}”(hXf   programs pin controller hardware according to the
definition of the state as given by the mapping table. In theory, this is a
fast-path operation, since it only involved blasting some register settings
into hardware. However, note that some pin controllers may have their
registers on a slow/IRQ-based bus, so client devices should not assume they
can call ”hj$  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_select_state()``”h]”hŒpinctrl_select_state()”…””}”(hhhj;  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj$  ubhŒ from non-blocking contexts.”…””}”(hŒ from non-blocking contexts.”hj$  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MÜhj   ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h NubhÛ)”}”(hŒJ``pinctrl_put()`` frees all information associated with a pinctrl handle.
”h]”h¸)”}”(hŒI``pinctrl_put()`` frees all information associated with a pinctrl handle.”h]”(jÞ  )”}”(hŒ``pinctrl_put()``”h]”hŒpinctrl_put()”…””}”(hhhjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj^  ubhŒ8 frees all information associated with a pinctrl handle.”…””}”(hŒ8 frees all information associated with a pinctrl handle.”hj^  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MãhjZ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h NubhÛ)”}”(hX  ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to
explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``.
However, use of this function will be rare, due to the automatic cleanup
that will occur even without calling it.

``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``.
``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``.
``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``.
``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``.
”h]”(h¸)”}”(hX  ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to
explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``.
However, use of this function will be rare, due to the automatic cleanup
that will occur even without calling it.”h]”(jÞ  )”}”(hŒ``devm_pinctrl_put()``”h]”hŒdevm_pinctrl_put()”…””}”(hhhj‰  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj…  ubhŒ is a variant of ”…””}”(hŒ is a variant of ”hj…  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_put()``”h]”hŒpinctrl_put()”…””}”(hhhjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj…  ubhŒE that may be used to
explicitly destroy a pinctrl object returned by ”…””}”(hŒE that may be used to
explicitly destroy a pinctrl object returned by ”hj…  hžhhŸNh NubjÞ  )”}”(hŒ``devm_pinctrl_get()``”h]”hŒdevm_pinctrl_get()”…””}”(hhhj¯  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj…  ubhŒs.
However, use of this function will be rare, due to the automatic cleanup
that will occur even without calling it.”…””}”(hŒs.
However, use of this function will be rare, due to the automatic cleanup
that will occur even without calling it.”hj…  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Måhj  ubh¸)”}”(hX  ``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``.
``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``.
``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``.
``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``.”h]”(jÞ  )”}”(hŒ``pinctrl_get()``”h]”hŒpinctrl_get()”…””}”(hhhjÌ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ must be paired with a plain ”…””}”(hŒ must be paired with a plain ”hjÈ  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_put()``”h]”hŒpinctrl_put()”…””}”(hhhjß  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ.
”…””}”(hŒ.
”hjÈ  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_get()``”h]”hŒpinctrl_get()”…””}”(hhhjò  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ may not be paired with ”…””}”(hŒ may not be paired with ”hjÈ  hžhhŸNh NubjÞ  )”}”(hŒ``devm_pinctrl_put()``”h]”hŒdevm_pinctrl_put()”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ.
”…””}”(hŒ.
”hjÈ  ubjÞ  )”}”(hŒ``devm_pinctrl_get()``”h]”hŒdevm_pinctrl_get()”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ can optionally be paired with ”…””}”(hŒ can optionally be paired with ”hjÈ  hžhhŸNh NubjÞ  )”}”(hŒ``devm_pinctrl_put()``”h]”hŒdevm_pinctrl_put()”…””}”(hhhj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ.
”…””}”(hjñ  hjÈ  ubjÞ  )”}”(hŒ``devm_pinctrl_get()``”h]”hŒdevm_pinctrl_get()”…””}”(hhhj=  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ may not be paired with plain ”…””}”(hŒ may not be paired with plain ”hjÈ  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_put()``”h]”hŒpinctrl_put()”…””}”(hhhjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÈ  ubhŒ.”…””}”(hj?
  hjÈ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mêhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjƒ  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h MÏhjÆ  hžhubh¸)”}”(hXX  Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas ``pinctrl_select_state()`` pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.”h]”(hŒ´Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas ”…””}”(hŒ´Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas ”hjt  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_select_state()``”h]”hŒpinctrl_select_state()”…””}”(hhhj}  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjt  ubhŒŠ pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.”…””}”(hŒŠ pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.”hjt  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MïhjÆ  hžhubh¸)”}”(hŒ¤The pins are allocated for your device when you issue the ``devm_pinctrl_get()``
call, after this you should be able to see this in the debugfs listing of all
pins.”h]”(hŒ:The pins are allocated for your device when you issue the ”…””}”(hŒ:The pins are allocated for your device when you issue the ”hj–  hžhhŸNh NubjÞ  )”}”(hŒ``devm_pinctrl_get()``”h]”hŒdevm_pinctrl_get()”…””}”(hhhjŸ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj–  ubhŒT
call, after this you should be able to see this in the debugfs listing of all
pins.”…””}”(hŒT
call, after this you should be able to see this in the debugfs listing of all
pins.”hj–  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MõhjÆ  hžhubh¸)”}”(hX(  NOTE: the pinctrl system will return ``-EPROBE_DEFER`` if it cannot find the
requested pinctrl handles, for example if the pinctrl driver has not yet
registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process.”h]”(hŒ%NOTE: the pinctrl system will return ”…””}”(hŒ%NOTE: the pinctrl system will return ”hj¸  hžhhŸNh NubjÞ  )”}”(hŒ``-EPROBE_DEFER``”h]”hŒ-EPROBE_DEFER”…””}”(hhhjÁ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj¸  ubhŒò if it cannot find the
requested pinctrl handles, for example if the pinctrl driver has not yet
registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process.”…””}”(hŒò if it cannot find the
requested pinctrl handles, for example if the pinctrl driver has not yet
registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process.”hj¸  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MùhjÆ  hžhubeh}”(h]”j|  ah ]”h"]”Œ!pin control requests from drivers”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M‹j 
  Kubh¢)”}”(hhh]”(h§)”}”(hŒ*Drivers needing both pin control and GPIOs”h]”hŒ*Drivers needing both pin control and GPIOs”…””}”(hjæ  hjä  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjá  hžhhŸh¶h M ubh¸)”}”(hŒAgain, it is discouraged to let drivers lookup and select pin control states
themselves, but again sometimes this is unavoidable.”h]”hŒAgain, it is discouraged to let drivers lookup and select pin control states
themselves, but again sometimes this is unavoidable.”…””}”(hjô  hjò  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjá  hžhubh¸)”}”(hŒ<So say that your driver is fetching its resources like this:”h]”hŒ<So say that your driver is fetching its resources like this:”…””}”(hj  hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjá  hžhubj¢  )”}”(hŒÌ#include <linux/pinctrl/consumer.h>
#include <linux/gpio/consumer.h>

struct pinctrl *pinctrl;
struct gpio_desc *gpio;

pinctrl = devm_pinctrl_get_select_default(&dev);
gpio = devm_gpiod_get(&dev, "foo");”h]”hŒÌ#include <linux/pinctrl/consumer.h>
#include <linux/gpio/consumer.h>

struct pinctrl *pinctrl;
struct gpio_desc *gpio;

pinctrl = devm_pinctrl_get_select_default(&dev);
gpio = devm_gpiod_get(&dev, "foo");”…””}”(hhhj  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h Mhjá  hžhubh¸)”}”(hXÊ  Here we first request a certain pin state and then request GPIO "foo" to be
used. If you're using the subsystems orthogonally like this, you should
nominally always get your pinctrl handle and select the desired pinctrl
state BEFORE requesting the GPIO. This is a semantic convention to avoid
situations that can be electrically unpleasant, you will certainly want to
mux in and bias pins in a certain way before the GPIO subsystems starts to
deal with them.”h]”hXÐ  Here we first request a certain pin state and then request GPIO â€œfooâ€ to be
used. If youâ€™re using the subsystems orthogonally like this, you should
nominally always get your pinctrl handle and select the desired pinctrl
state BEFORE requesting the GPIO. This is a semantic convention to avoid
situations that can be electrically unpleasant, you will certainly want to
mux in and bias pins in a certain way before the GPIO subsystems starts to
deal with them.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjá  hžhubh¸)”}”(hŒÈThe above can be hidden: using the device core, the pinctrl core may be
setting up the config and muxing for the pins right before the device is
probing, nevertheless orthogonal to the GPIO subsystem.”h]”hŒÈThe above can be hidden: using the device core, the pinctrl core may be
setting up the config and muxing for the pins right before the device is
probing, nevertheless orthogonal to the GPIO subsystem.”…””}”(hj-  hj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjá  hžhubh¸)”}”(hXí  But there are also situations where it makes sense for the GPIO subsystem
to communicate directly with the pinctrl subsystem, using the latter as a
back-end. This is when the GPIO driver may call out to the functions
described in the section `Pin control interaction with the GPIO subsystem`_
above. This only involves per-pin multiplexing, and will be completely
hidden behind the gpiod_*() function namespace. In this case, the driver
need not interact with the pin control subsystem at all.”h]”(hŒòBut there are also situations where it makes sense for the GPIO subsystem
to communicate directly with the pinctrl subsystem, using the latter as a
back-end. This is when the GPIO driver may call out to the functions
described in the section ”…””}”(hŒòBut there are also situations where it makes sense for the GPIO subsystem
to communicate directly with the pinctrl subsystem, using the latter as a
back-end. This is when the GPIO driver may call out to the functions
described in the section ”hj9  hžhhŸNh Nubjð  )”}”(hŒ2`Pin control interaction with the GPIO subsystem`_”h]”hŒ/Pin control interaction with the GPIO subsystem”…””}”(hŒ/Pin control interaction with the GPIO subsystem”hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ/Pin control interaction with the GPIO subsystem”j  jš
  uh1jï  hj9  j  KubhŒÉ
above. This only involves per-pin multiplexing, and will be completely
hidden behind the gpiod_*() function namespace. In this case, the driver
need not interact with the pin control subsystem at all.”…””}”(hŒÉ
above. This only involves per-pin multiplexing, and will be completely
hidden behind the gpiod_*() function namespace. In this case, the driver
need not interact with the pin control subsystem at all.”hj9  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjá  hžhubh¸)”}”(hX  If a pin control driver and a GPIO driver is dealing with the same pins
and the use cases involve multiplexing, you MUST implement the pin controller
as a back-end for the GPIO driver like this, unless your hardware design
is such that the GPIO controller can override the pin controller's
multiplexing state through hardware without the need to interact with the
pin control system.”h]”hX  If a pin control driver and a GPIO driver is dealing with the same pins
and the use cases involve multiplexing, you MUST implement the pin controller
as a back-end for the GPIO driver like this, unless your hardware design
is such that the GPIO controller can override the pin controllerâ€™s
multiplexing state through hardware without the need to interact with the
pin control system.”…””}”(hj`  hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M&hjá  hžhubeh}”(h]”j“  ah ]”h"]”Œ*drivers needing both pin control and gpios”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M j 
  Kubh¢)”}”(hhh]”(h§)”}”(hŒSystem pin control hogging”h]”hŒSystem pin control hogging”…””}”(hjx  hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjs  hžhhŸh¶h M/ubh¸)”}”(hX  Pin control map entries can be hogged by the core when the pin controller
is registered. This means that the core will attempt to call ``pinctrl_get()``,
``pinctrl_lookup_state()`` and ``pinctrl_select_state()`` on it immediately after
the pin control device has been registered.”h]”(hŒ‡Pin control map entries can be hogged by the core when the pin controller
is registered. This means that the core will attempt to call ”…””}”(hŒ‡Pin control map entries can be hogged by the core when the pin controller
is registered. This means that the core will attempt to call ”hj„  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_get()``”h]”hŒpinctrl_get()”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj„  ubhŒ,
”…””}”(hŒ,
”hj„  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_lookup_state()``”h]”hŒpinctrl_lookup_state()”…””}”(hhhj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj„  ubhŒ and ”…””}”(hŒ and ”hj„  hžhhŸNh NubjÞ  )”}”(hŒ``pinctrl_select_state()``”h]”hŒpinctrl_select_state()”…””}”(hhhj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj„  ubhŒD on it immediately after
the pin control device has been registered.”…””}”(hŒD on it immediately after
the pin control device has been registered.”hj„  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M1hjs  hžhubh¸)”}”(hŒŸThis occurs for mapping table entries where the client device name is equal
to the pin controller device name, and the state name is ``PINCTRL_STATE_DEFAULT``:”h]”(hŒ…This occurs for mapping table entries where the client device name is equal
to the pin controller device name, and the state name is ”…””}”(hŒ…This occurs for mapping table entries where the client device name is equal
to the pin controller device name, and the state name is ”hjÌ  hžhhŸNh NubjÞ  )”}”(hŒ``PINCTRL_STATE_DEFAULT``”h]”hŒPINCTRL_STATE_DEFAULT”…””}”(hhhjÕ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÌ  ubhŒ:”…””}”(hj  hjÌ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M6hjs  hžhubj¢  )”}”(hŒÀ{
        .dev_name = "pinctrl-foo",
        .name = PINCTRL_STATE_DEFAULT,
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "power_func",
},”h]”hŒÀ{
        .dev_name = "pinctrl-foo",
        .name = PINCTRL_STATE_DEFAULT,
        .type = PIN_MAP_TYPE_MUX_GROUP,
        .ctrl_dev_name = "pinctrl-foo",
        .function = "power_func",
},”…””}”(hhhjí  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M9hjs  hžhubh¸)”}”(hŒœSince it may be common to request the core to hog a few always-applicable
mux settings on the primary pin controller, there is a convenience macro for
this:”h]”hŒœSince it may be common to request the core to hog a few always-applicable
mux settings on the primary pin controller, there is a convenience macro for
this:”…””}”(hjþ  hjü  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MChjs  hžhubj¢  )”}”(hŒjPIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
                              "power_func")”h]”hŒjPIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
                              "power_func")”…””}”(hhhj
  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h MGhjs  hžhubh¸)”}”(hŒ;This gives the exact same result as the above construction.”h]”hŒ;This gives the exact same result as the above construction.”…””}”(hj  hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MLhjs  hžhubeh}”(h]”Œsystem-pin-control-hogging”ah ]”h"]”Œsystem pin control hogging”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M/ubh¢)”}”(hhh]”(h§)”}”(hŒRuntime pinmuxing”h]”hŒRuntime pinmuxing”…””}”(hj4  hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj/  hžhhŸh¶h MPubh¸)”}”(hX  It is possible to mux a certain function in and out at runtime, say to move
an SPI port from one set of pins to another set of pins. Say for example for
spi0 in the example above, we expose two different groups of pins for the same
function, but with different named in the mapping as described under
"Advanced mapping" above. So that for an SPI device, we have two states named
"pos-A" and "pos-B".”h]”hX›  It is possible to mux a certain function in and out at runtime, say to move
an SPI port from one set of pins to another set of pins. Say for example for
spi0 in the example above, we expose two different groups of pins for the same
function, but with different named in the mapping as described under
â€œAdvanced mappingâ€ above. So that for an SPI device, we have two states named
â€œpos-Aâ€ and â€œpos-Bâ€.”…””}”(hjB  hj@  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MRhj/  hžhubh¸)”}”(hŒ¿This snippet first initializes a state object for both groups (in foo_probe()),
then muxes the function in the pins defined by group A, and finally muxes it in
on the pins defined by group B:”h]”hŒ¿This snippet first initializes a state object for both groups (in foo_probe()),
then muxes the function in the pins defined by group A, and finally muxes it in
on the pins defined by group B:”…””}”(hjP  hjN  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MYhj/  hžhubj¢  )”}”(hX   #include <linux/pinctrl/consumer.h>

struct pinctrl *p;
struct pinctrl_state *s1, *s2;

foo_probe()
{
        /* Setup */
        p = devm_pinctrl_get(&device);
        if (IS_ERR(p))
                ...

        s1 = pinctrl_lookup_state(p, "pos-A");
        if (IS_ERR(s1))
                ...

        s2 = pinctrl_lookup_state(p, "pos-B");
        if (IS_ERR(s2))
                ...
}

foo_switch()
{
        /* Enable on position A */
        ret = pinctrl_select_state(p, s1);
        if (ret < 0)
                ...

        ...

        /* Enable on position B */
        ret = pinctrl_select_state(p, s2);
        if (ret < 0)
                ...

        ...
}”h]”hX   #include <linux/pinctrl/consumer.h>

struct pinctrl *p;
struct pinctrl_state *s1, *s2;

foo_probe()
{
        /* Setup */
        p = devm_pinctrl_get(&device);
        if (IS_ERR(p))
                ...

        s1 = pinctrl_lookup_state(p, "pos-A");
        if (IS_ERR(s1))
                ...

        s2 = pinctrl_lookup_state(p, "pos-B");
        if (IS_ERR(s2))
                ...
}

foo_switch()
{
        /* Enable on position A */
        ret = pinctrl_select_state(p, s1);
        if (ret < 0)
                ...

        ...

        /* Enable on position B */
        ret = pinctrl_select_state(p, s2);
        if (ret < 0)
                ...

        ...
}”…””}”(hhhj\  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  jÑ  jÒ  }”uh1j¡  hŸh¶h M]hj/  hžhubh¸)”}”(hŒÝThe above has to be done from process context. The reservation of the pins
will be done when the state is activated, so in effect one specific pin
can be used by different functions at different times on a running system.”h]”hŒÝThe above has to be done from process context. The reservation of the pins
will be done when the state is activated, so in effect one specific pin
can be used by different functions at different times on a running system.”…””}”(hjm  hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M…hj/  hžhubeh}”(h]”jN  ah ]”h"]”Œruntime pinmuxing”ah$]”h&]”uh1h¡hh£hžhhŸh¶h MPj 
  Kubh¢)”}”(hhh]”(h§)”}”(hŒDebugfs files”h]”hŒDebugfs files”…””}”(hj…  hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj€  hžhhŸh¶h M‹ubh¸)”}”(hŒ9These files are created in ``/sys/kernel/debug/pinctrl``:”h]”(hŒThese files are created in ”…””}”(hŒThese files are created in ”hj‘  hžhhŸNh NubjÞ  )”}”(hŒ``/sys/kernel/debug/pinctrl``”h]”hŒ/sys/kernel/debug/pinctrl”…””}”(hhhjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj‘  ubhŒ:”…””}”(hj  hj‘  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj€  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hŒu``pinctrl-devices``: prints each pin controller device along with columns to
indicate support for pinmux and pinconf
”h]”h¸)”}”(hŒt``pinctrl-devices``: prints each pin controller device along with columns to
indicate support for pinmux and pinconf”h]”(jÞ  )”}”(hŒ``pinctrl-devices``”h]”hŒpinctrl-devices”…””}”(hhhj½  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj¹  ubhŒa: prints each pin controller device along with columns to
indicate support for pinmux and pinconf”…””}”(hŒa: prints each pin controller device along with columns to
indicate support for pinmux and pinconf”hj¹  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhjµ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj²  hžhhŸh¶h NubhÛ)”}”(hŒd``pinctrl-handles``: prints each configured pin controller handle and the
corresponding pinmux maps
”h]”h¸)”}”(hŒc``pinctrl-handles``: prints each configured pin controller handle and the
corresponding pinmux maps”h]”(jÞ  )”}”(hŒ``pinctrl-handles``”h]”hŒpinctrl-handles”…””}”(hhhjä  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjà  ubhŒP: prints each configured pin controller handle and the
corresponding pinmux maps”…””}”(hŒP: prints each configured pin controller handle and the
corresponding pinmux maps”hjà  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M’hjÜ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj²  hžhhŸh¶h NubhÛ)”}”(hŒ*``pinctrl-maps``: prints all pinctrl maps
”h]”h¸)”}”(hŒ)``pinctrl-maps``: prints all pinctrl maps”h]”(jÞ  )”}”(hŒ``pinctrl-maps``”h]”hŒpinctrl-maps”…””}”(hhhj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj  ubhŒ: prints all pinctrl maps”…””}”(hŒ: prints all pinctrl maps”hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M•hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj²  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h Mhj€  hžhubh¸)”}”(hŒyA sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin
controller device containing these files:”h]”(hŒ%A sub-directory is created inside of ”…””}”(hŒ%A sub-directory is created inside of ”hj0  hžhhŸNh NubjÞ  )”}”(hŒ``/sys/kernel/debug/pinctrl``”h]”hŒ/sys/kernel/debug/pinctrl”…””}”(hhhj9  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj0  ubhŒ7 for each pin
controller device containing these files:”…””}”(hŒ7 for each pin
controller device containing these files:”hj0  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M—hj€  hžhubhÖ)”}”(hhh]”(hÛ)”}”(hŒ”``pins``: prints a line for each pin registered on the pin controller. The
pinctrl driver may add additional information such as register contents.
”h]”h¸)”}”(hŒ“``pins``: prints a line for each pin registered on the pin controller. The
pinctrl driver may add additional information such as register contents.”h]”(jÞ  )”}”(hŒ``pins``”h]”hŒpins”…””}”(hhhj]  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjY  ubhŒ‹: prints a line for each pin registered on the pin controller. The
pinctrl driver may add additional information such as register contents.”…””}”(hŒ‹: prints a line for each pin registered on the pin controller. The
pinctrl driver may add additional information such as register contents.”hjY  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MšhjU  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒM``gpio-ranges``: prints ranges that map gpio lines to pins on the controller
”h]”h¸)”}”(hŒL``gpio-ranges``: prints ranges that map gpio lines to pins on the controller”h]”(jÞ  )”}”(hŒ``gpio-ranges``”h]”hŒgpio-ranges”…””}”(hhhj„  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj€  ubhŒ=: prints ranges that map gpio lines to pins on the controller”…””}”(hŒ=: prints ranges that map gpio lines to pins on the controller”hj€  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Mhj|  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒF``pingroups``: prints all pin groups registered on the pin controller
”h]”h¸)”}”(hŒE``pingroups``: prints all pin groups registered on the pin controller”h]”(jÞ  )”}”(hŒ``pingroups``”h]”hŒ	pingroups”…””}”(hhhj«  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj§  ubhŒ8: prints all pin groups registered on the pin controller”…””}”(hŒ8: prints all pin groups registered on the pin controller”hj§  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h MŸhj£  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒ:``pinconf-pins``: prints pin config settings for each pin
”h]”h¸)”}”(hŒ9``pinconf-pins``: prints pin config settings for each pin”h]”(jÞ  )”}”(hŒ``pinconf-pins``”h]”hŒpinconf-pins”…””}”(hhhjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjÎ  ubhŒ): prints pin config settings for each pin”…””}”(hŒ): prints pin config settings for each pin”hjÎ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¡hjÊ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒ=``pinconf-groups``: prints pin config settings per pin group
”h]”h¸)”}”(hŒ<``pinconf-groups``: prints pin config settings per pin group”h]”(jÞ  )”}”(hŒ``pinconf-groups``”h]”hŒpinconf-groups”…””}”(hhhjù  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjõ  ubhŒ*: prints pin config settings per pin group”…””}”(hŒ*: prints pin config settings per pin group”hjõ  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M£hjñ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒf``pinmux-functions``: prints each pin function along with the pin groups that
map to the pin function
”h]”h¸)”}”(hŒe``pinmux-functions``: prints each pin function along with the pin groups that
map to the pin function”h]”(jÞ  )”}”(hŒ``pinmux-functions``”h]”hŒpinmux-functions”…””}”(hhhj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hj  ubhŒQ: prints each pin function along with the pin groups that
map to the pin function”…””}”(hŒQ: prints each pin function along with the pin groups that
map to the pin function”hj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¥hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒd``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner
and if the pin is a hog
”h]”h¸)”}”(hŒc``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner
and if the pin is a hog”h]”(jÞ  )”}”(hŒ``pinmux-pins``”h]”hŒpinmux-pins”…””}”(hhhjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjC  ubhŒT: iterates through all pins and prints mux owner, gpio owner
and if the pin is a hog”…””}”(hŒT: iterates through all pins and prints mux owner, gpio owner
and if the pin is a hog”hjC  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M¨hj?  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸh¶h NubhÛ)”}”(hŒš``pinmux-select``: write to this file to activate a pin function for a group:

.. code-block:: sh

      echo "<group-name function-name>" > pinmux-select”h]”(h¸)”}”(hŒM``pinmux-select``: write to this file to activate a pin function for a group:”h]”(jÞ  )”}”(hŒ``pinmux-select``”h]”hŒpinmux-select”…””}”(hhhjn  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÝ  hjj  ubhŒ<: write to this file to activate a pin function for a group:”…””}”(hŒ<: write to this file to activate a pin function for a group:”hjj  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h M«hjf  ubj¢  )”}”(hŒ1echo "<group-name function-name>" > pinmux-select”h]”hŒ1echo "<group-name function-name>" > pinmux-select”…””}”(hhhj‡  ubah}”(h]”h ]”h"]”h$]”h&]”j±  j²  jÏ  ‰jÐ  Œsh”jÒ  }”uh1j¡  hŸh¶h M­hjf  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhjR  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”j*  j+  uh1hÕhŸh¶h Mšhj€  hžhubeh}”(h]”Œdebugfs-files”ah ]”h"]”Œdebugfs files”ah$]”h&]”uh1h¡hh£hžhhŸh¶h M‹ubeh}”(h]”Œpinctrl-pin-control-subsystem”ah ]”h"]”Œpinctrl (pin control) subsystem”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jÖ  Œerror_encoding”ŒUTF-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œembed_images”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”(Œboard/machine configuration”]”jñ  aŒ!pin control requests from drivers”]”jk  aŒ*drivers needing both pin control and gpios”]”j‚  aŒgpio mode pitfalls”]”jü  aŒruntime pinmuxing”]”j=  aŒ/pin control interaction with the gpio subsystem”]”jB  auŒrefids”}”Œnameids”}”(j°  j­  j<  j9  jÄ  jÁ  j@  j=  j‡  j„  j®  j«  jF  jC  j.  j+  jÌ  jÉ  j
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  Nj  Nj  NjÃ  NjÞ  Njp  Nj,  Nj}  Nj¨  Nuh}”(j­  h£j9  j,  jÁ  j?  j=  jÇ  j„  jC  j«  jŠ  jC  j±  j+  jI  jÉ  j1  jš
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
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