sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget&/translations/zh_CN/driver-api/mtdnandmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/zh_TW/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/it_IT/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ja_JP/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/ko_KR/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/pt_BR/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget&/translations/sp_SP/driver-api/mtdnandmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h%MTD NAND Driver Programming Interfaceh]h%MTD NAND Driver Programming Interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh@/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand.rsthKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(hThomas Gleixner h]h paragraph)}(hThomas Gleixnerh]hThomas Gleixner}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Introductionh]h Introduction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hThe generic NAND driver supports almost all NAND and AG-AND based chips and connects them to the Memory Technology Devices (MTD) subsystem of the Linux Kernel.h]hThe generic NAND driver supports almost all NAND and AG-AND based chips and connects them to the Memory Technology Devices (MTD) subsystem of the Linux Kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj hhubh)}(hThis documentation is provided for developers who want to implement board drivers or filesystem drivers suitable for NAND devices.h]hThis documentation is provided for developers who want to implement board drivers or filesystem drivers suitable for NAND devices.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h] introductionah ]h"] introductionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hKnown Bugs And Assumptionsh]hKnown Bugs And Assumptions}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhKubh)}(hNone.h]hNone.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjBhhubeh}(h]known-bugs-and-assumptionsah ]h"]known bugs and assumptionsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDocumentation hintsh]hDocumentation hints}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhhhhKubh)}(hThe function and structure docs are autogenerated. Each function and struct member has a short description which is marked with an [XXX] identifier. The following chapters explain the meaning of those identifiers.h]hThe function and structure docs are autogenerated. Each function and struct member has a short description which is marked with an [XXX] identifier. The following chapters explain the meaning of those identifiers.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjihhubh)}(hhh](h)}(hFunction identifiers [XXX]h]hFunction identifiers [XXX]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThe functions are marked with [XXX] identifiers in the short comment. The identifiers explain the usage and scope of the functions. Following identifiers are used:h]hThe functions are marked with [XXX] identifiers in the short comment. The identifiers explain the usage and scope of the functions. Following identifiers are used:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjhhubh bullet_list)}(hhh](h list_item)}(h[MTD Interface] These functions provide the interface to the MTD kernel API. They are not replaceable and provide functionality which is complete hardware independent. h](h)}(h[MTD Interface]h]h[MTD Interface]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubh)}(hThese functions provide the interface to the MTD kernel API. They are not replaceable and provide functionality which is complete hardware independent.h]hThese functions provide the interface to the MTD kernel API. They are not replaceable and provide functionality which is complete hardware independent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(ha[NAND Interface] These functions are exported and provide the interface to the NAND kernel API. h](h)}(h[NAND Interface]h]h[NAND Interface]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubh)}(hNThese functions are exported and provide the interface to the NAND kernel API.h]hNThese functions are exported and provide the interface to the NAND kernel API.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hs[GENERIC] Generic functions are not replaceable and provide functionality which is complete hardware independent. h](h)}(h [GENERIC]h]h [GENERIC]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubh)}(hgGeneric functions are not replaceable and provide functionality which is complete hardware independent.h]hgGeneric functions are not replaceable and provide functionality which is complete hardware independent.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX[DEFAULT] Default functions provide hardware related functionality which is suitable for most of the implementations. These functions can be replaced by the board driver if necessary. Those functions are called via pointers in the NAND chip description structure. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type. h](h)}(h [DEFAULT]h]h [DEFAULT]}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hj ubh)}(hX Default functions provide hardware related functionality which is suitable for most of the implementations. These functions can be replaced by the board driver if necessary. Those functions are called via pointers in the NAND chip description structure. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type.h]hX Default functions provide hardware related functionality which is suitable for most of the implementations. These functions can be replaced by the board driver if necessary. Those functions are called via pointers in the NAND chip description structure. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hj ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhK%hjhhubeh}(h]function-identifiers-xxxah ]h"]function identifiers [xxx]ah$]h&]uh1hhjihhhhhKubh)}(hhh](h)}(hStruct member identifiers [XXX]h]hStruct member identifiers [XXX]}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhKAubh)}(hThe struct members are marked with [XXX] identifiers in the comment. The identifiers explain the usage and scope of the members. Following identifiers are used:h]hThe struct members are marked with [XXX] identifiers in the comment. The identifiers explain the usage and scope of the members. Following identifiers are used:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjVhhubj)}(hhh](j)}(h[INTERN] These members are for NAND driver internal use only and must not be modified. Most of these values are calculated from the chip geometry information which is evaluated during nand_scan(). h](h)}(h[INTERN]h]h[INTERN]}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjxubh)}(hThese members are for NAND driver internal use only and must not be modified. Most of these values are calculated from the chip geometry information which is evaluated during nand_scan().h]hThese members are for NAND driver internal use only and must not be modified. Most of these values are calculated from the chip geometry information which is evaluated during nand_scan().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjxubeh}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubj)}(hX}[REPLACEABLE] Replaceable members hold hardware related functions which can be provided by the board driver. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type. h](h)}(h [REPLACEABLE]h]h [REPLACEABLE]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjubh)}(hXmReplaceable members hold hardware related functions which can be provided by the board driver. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type.h]hXmReplaceable members hold hardware related functions which can be provided by the board driver. The board driver can set the functions which should be replaced by board dependent functions before calling nand_scan(). If the function pointer is NULL on entry to nand_scan() then the pointer is set to the default function which is suitable for the detected chip type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubeh}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubj)}(h[BOARDSPECIFIC] Board specific members hold hardware related information which must be provided by the board driver. The board driver must set the function pointers and datafields before calling nand_scan(). h](h)}(h[BOARDSPECIFIC]h]h[BOARDSPECIFIC]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhjubh)}(hBoard specific members hold hardware related information which must be provided by the board driver. The board driver must set the function pointers and datafields before calling nand_scan().h]hBoard specific members hold hardware related information which must be provided by the board driver. The board driver must set the function pointers and datafields before calling nand_scan().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjubeh}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubj)}(h[OPTIONAL] Optional members can hold information relevant for the board driver. The generic NAND driver code does not use this information. h](h)}(h [OPTIONAL]h]h [OPTIONAL]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubh)}(hOptional members can hold information relevant for the board driver. The generic NAND driver code does not use this information.h]hOptional members can hold information relevant for the board driver. The generic NAND driver code does not use this information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubeh}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhKGhjVhhubeh}(h]struct-member-identifiers-xxxah ]h"]struct member identifiers [xxx]ah$]h&]uh1hhjihhhhhKAubeh}(h]documentation-hintsah ]h"]documentation hintsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hBasic board driverh]hBasic board driver}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhKbubh)}(hFor most boards it will be sufficient to provide just the basic functions and fill out some really board dependent members in the nand chip description structure.h]hFor most boards it will be sufficient to provide just the basic functions and fill out some really board dependent members in the nand chip description structure.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhj&hhubh)}(hhh](h)}(h Basic definesh]h Basic defines}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhhhhhKiubh)}(hXAt least you have to provide a nand_chip structure and a storage for the ioremap'ed chip address. You can allocate the nand_chip structure using kmalloc or you can allocate it statically. The NAND chip structure embeds an mtd structure which will be registered to the MTD subsystem. You can extract a pointer to the mtd structure from a nand_chip pointer using the nand_to_mtd() helper.h]hXAt least you have to provide a nand_chip structure and a storage for the ioremap’ed chip address. You can allocate the nand_chip structure using kmalloc or you can allocate it statically. The NAND chip structure embeds an mtd structure which will be registered to the MTD subsystem. You can extract a pointer to the mtd structure from a nand_chip pointer using the nand_to_mtd() helper.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjEhhubh)}(hKmalloc based exampleh]hKmalloc based example}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjEhhubh literal_block)}(hAstatic struct mtd_info *board_mtd; static void __iomem *baseaddr;h]hAstatic struct mtd_info *board_mtd; static void __iomem *baseaddr;}hjtsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jrhhhKvhjEhhubh)}(hStatic exampleh]hStatic example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjEhhubjs)}(hBstatic struct nand_chip board_chip; static void __iomem *baseaddr;h]hBstatic struct nand_chip board_chip; static void __iomem *baseaddr;}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhK~hjEhhubeh}(h] basic-definesah ]h"] basic definesah$]h&]uh1hhj&hhhhhKiubh)}(hhh](h)}(hPartition definesh]hPartition defines}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hlIf you want to divide your device into partitions, then define a partitioning scheme suitable to your board.h]hlIf you want to divide your device into partitions, then define a partitioning scheme suitable to your board.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjs)}(hX#define NUM_PARTITIONS 2 static struct mtd_partition partition_info[] = { { .name = "Flash partition 1", .offset = 0, .size = 8 * 1024 * 1024 }, { .name = "Flash partition 2", .offset = MTDPART_OFS_NEXT, .size = MTDPART_SIZ_FULL }, };h]hX#define NUM_PARTITIONS 2 static struct mtd_partition partition_info[] = { { .name = "Flash partition 1", .offset = 0, .size = 8 * 1024 * 1024 }, { .name = "Flash partition 2", .offset = MTDPART_OFS_NEXT, .size = MTDPART_SIZ_FULL }, };}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhKhjhhubeh}(h]partition-definesah ]h"]partition definesah$]h&]uh1hhj&hhhhhKubh)}(hhh](h)}(hHardware control functionh]hHardware control function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThe hardware control function provides access to the control pins of the NAND chip(s). The access can be done by GPIO pins or by address lines. If you use address lines, make sure that the timing requirements are met.h]hThe hardware control function provides access to the control pins of the NAND chip(s). The access can be done by GPIO pins or by address lines. If you use address lines, make sure that the timing requirements are met.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h*GPIO based example*h]hemphasis)}(hjh]hGPIO based example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjs)}(hXstatic void board_hwcontrol(struct mtd_info *mtd, int cmd) { switch(cmd){ case NAND_CTL_SETCLE: /* Set CLE pin high */ break; case NAND_CTL_CLRCLE: /* Set CLE pin low */ break; case NAND_CTL_SETALE: /* Set ALE pin high */ break; case NAND_CTL_CLRALE: /* Set ALE pin low */ break; case NAND_CTL_SETNCE: /* Set nCE pin low */ break; case NAND_CTL_CLRNCE: /* Set nCE pin high */ break; } }h]hXstatic void board_hwcontrol(struct mtd_info *mtd, int cmd) { switch(cmd){ case NAND_CTL_SETCLE: /* Set CLE pin high */ break; case NAND_CTL_CLRCLE: /* Set CLE pin low */ break; case NAND_CTL_SETALE: /* Set ALE pin high */ break; case NAND_CTL_CLRALE: /* Set ALE pin low */ break; case NAND_CTL_SETNCE: /* Set nCE pin low */ break; case NAND_CTL_CLRNCE: /* Set nCE pin high */ break; } }}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhKhjhhubh)}(h`*Address lines based example.* It's assumed that the nCE pin is driven by a chip select decoder.h](j)}(h*Address lines based example.*h]hAddress lines based example.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubhD It’s assumed that the nCE pin is driven by a chip select decoder.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjs)}(hXstatic void board_hwcontrol(struct mtd_info *mtd, int cmd) { struct nand_chip *this = mtd_to_nand(mtd); switch(cmd){ case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT; break; case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break; case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT; break; case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break; } }h]hXstatic void board_hwcontrol(struct mtd_info *mtd, int cmd) { struct nand_chip *this = mtd_to_nand(mtd); switch(cmd){ case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT; break; case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break; case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT; break; case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break; } }}hj?sbah}(h]h ]h"]h$]h&]jjuh1jrhhhKhjhhubeh}(h]hardware-control-functionah ]h"]hardware control functionah$]h&]uh1hhj&hhhhhKubh)}(hhh](h)}(hDevice ready functionh]hDevice ready function}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhhhKubh)}(hXIf the hardware interface has the ready busy pin of the NAND chip connected to a GPIO or other accessible I/O pin, this function is used to read back the state of the pin. The function has no arguments and should return 0, if the device is busy (R/B pin is low) and 1, if the device is ready (R/B pin is high). If the hardware interface does not give access to the ready busy pin, then the function must not be defined and the function pointer this->legacy.dev_ready is set to NULL.h]hXIf the hardware interface has the ready busy pin of the NAND chip connected to a GPIO or other accessible I/O pin, this function is used to read back the state of the pin. The function has no arguments and should return 0, if the device is busy (R/B pin is low) and 1, if the device is ready (R/B pin is high). If the hardware interface does not give access to the ready busy pin, then the function must not be defined and the function pointer this->legacy.dev_ready is set to NULL.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjUhhubeh}(h]device-ready-functionah ]h"]device ready functionah$]h&]uh1hhj&hhhhhKubh)}(hhh](h)}(h Init functionh]h Init function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhhhKubh)}(hXThe init function allocates memory and sets up all the board specific parameters and function pointers. When everything is set up nand_scan() is called. This function tries to detect and identify then chip. If a chip is found all the internal data fields are initialized accordingly. The structure(s) have to be zeroed out first and then filled with the necessary information about the device.h]hXThe init function allocates memory and sets up all the board specific parameters and function pointers. When everything is set up nand_scan() is called. This function tries to detect and identify then chip. If a chip is found all the internal data fields are initialized accordingly. The structure(s) have to be zeroed out first and then filled with the necessary information about the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj|hhubjs)}(hX]static int __init board_init (void) { struct nand_chip *this; int err = 0; /* Allocate memory for MTD device structure and private data */ this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL); if (!this) { printk ("Unable to allocate NAND MTD device structure.\n"); err = -ENOMEM; goto out; } board_mtd = nand_to_mtd(this); /* map physical address */ baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024); if (!baseaddr) { printk("Ioremap to access NAND chip failed\n"); err = -EIO; goto out_mtd; } /* Set address of NAND IO lines */ this->legacy.IO_ADDR_R = baseaddr; this->legacy.IO_ADDR_W = baseaddr; /* Reference hardware control function */ this->hwcontrol = board_hwcontrol; /* Set command delay time, see datasheet for correct value */ this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY; /* Assign the device ready function, if available */ this->legacy.dev_ready = board_dev_ready; this->eccmode = NAND_ECC_SOFT; /* Scan to find existence of the device */ if (nand_scan (this, 1)) { err = -ENXIO; goto out_ior; } add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS); goto out; out_ior: iounmap(baseaddr); out_mtd: kfree (this); out: return err; } module_init(board_init);h]hX]static int __init board_init (void) { struct nand_chip *this; int err = 0; /* Allocate memory for MTD device structure and private data */ this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL); if (!this) { printk ("Unable to allocate NAND MTD device structure.\n"); err = -ENOMEM; goto out; } board_mtd = nand_to_mtd(this); /* map physical address */ baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024); if (!baseaddr) { printk("Ioremap to access NAND chip failed\n"); err = -EIO; goto out_mtd; } /* Set address of NAND IO lines */ this->legacy.IO_ADDR_R = baseaddr; this->legacy.IO_ADDR_W = baseaddr; /* Reference hardware control function */ this->hwcontrol = board_hwcontrol; /* Set command delay time, see datasheet for correct value */ this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY; /* Assign the device ready function, if available */ this->legacy.dev_ready = board_dev_ready; this->eccmode = NAND_ECC_SOFT; /* Scan to find existence of the device */ if (nand_scan (this, 1)) { err = -ENXIO; goto out_ior; } add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS); goto out; out_ior: iounmap(baseaddr); out_mtd: kfree (this); out: return err; } module_init(board_init);}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhKhj|hhubeh}(h] init-functionah ]h"] init functionah$]h&]uh1hhj&hhhhhKubh)}(hhh](h)}(h Exit functionh]h Exit function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubh)}(hThe exit function is only necessary if the driver is compiled as a module. It releases all resources which are held by the chip driver and unregisters the partitions in the MTD layer.h]hThe exit function is only necessary if the driver is compiled as a module. It releases all resources which are held by the chip driver and unregisters the partitions in the MTD layer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubjs)}(hXs#ifdef MODULE static void __exit board_cleanup (void) { /* Unregister device */ WARN_ON(mtd_device_unregister(board_mtd)); /* Release resources */ nand_cleanup(mtd_to_nand(board_mtd)); /* unmap physical address */ iounmap(baseaddr); /* Free the MTD device structure */ kfree (mtd_to_nand(board_mtd)); } module_exit(board_cleanup); #endifh]hXs#ifdef MODULE static void __exit board_cleanup (void) { /* Unregister device */ WARN_ON(mtd_device_unregister(board_mtd)); /* Release resources */ nand_cleanup(mtd_to_nand(board_mtd)); /* unmap physical address */ iounmap(baseaddr); /* Free the MTD device structure */ kfree (mtd_to_nand(board_mtd)); } module_exit(board_cleanup); #endif}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMhjhhubeh}(h] exit-functionah ]h"] exit functionah$]h&]uh1hhj&hhhhhM ubeh}(h]basic-board-driverah ]h"]basic board driverah$]h&]uh1hhhhhhhhKbubh)}(hhh](h)}(hAdvanced board driver functionsh]hAdvanced board driver functions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM'ubh)}(hThis chapter describes the advanced functionality of the NAND driver. For a list of functions which can be overridden by the board driver see the documentation of the nand_chip structure.h]hThis chapter describes the advanced functionality of the NAND driver. For a list of functions which can be overridden by the board driver see the documentation of the nand_chip structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjhhubh)}(hhh](h)}(hMultiple chip controlh]hMultiple chip control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM.ubh)}(hXThe nand driver can control chip arrays. Therefore the board driver must provide an own select_chip function. This function must (de)select the requested chip. The function pointer in the nand_chip structure must be set before calling nand_scan(). The maxchip parameter of nand_scan() defines the maximum number of chips to scan for. Make sure that the select_chip function can handle the requested number of chips.h]hXThe nand driver can control chip arrays. Therefore the board driver must provide an own select_chip function. This function must (de)select the requested chip. The function pointer in the nand_chip structure must be set before calling nand_scan(). The maxchip parameter of nand_scan() defines the maximum number of chips to scan for. Make sure that the select_chip function can handle the requested number of chips.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj hhubh)}(hkThe nand driver concatenates the chips to one virtual chip and provides this virtual chip to the MTD layer.h]hkThe nand driver concatenates the chips to one virtual chip and provides this virtual chip to the MTD layer.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj hhubh)}(h*Note: The driver can only handle linear chip arrays of equally sized chips. There is no support for parallel arrays which extend the buswidth.*h]j)}(hj<h]hNote: The driver can only handle linear chip arrays of equally sized chips. There is no support for parallel arrays which extend the buswidth.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1hhhhM:hj hhubh)}(h*GPIO based example*h]j)}(hjSh]hGPIO based example}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1hhhhM>hj hhubjs)}(hstatic void board_select_chip (struct mtd_info *mtd, int chip) { /* Deselect all chips, set all nCE pins high */ GPIO(BOARD_NAND_NCE) |= 0xff; if (chip >= 0) GPIO(BOARD_NAND_NCE) &= ~ (1 << chip); }h]hstatic void board_select_chip (struct mtd_info *mtd, int chip) { /* Deselect all chips, set all nCE pins high */ GPIO(BOARD_NAND_NCE) |= 0xff; if (chip >= 0) GPIO(BOARD_NAND_NCE) &= ~ (1 << chip); }}hjhsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMBhj hhubh)}(ha*Address lines based example.* Its assumed that the nCE pins are connected to an address decoder.h](j)}(h*Address lines based example.*h]hAddress lines based example.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubhC Its assumed that the nCE pins are connected to an address decoder.}(hjvhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMKhj hhubjs)}(hX6static void board_select_chip (struct mtd_info *mtd, int chip) { struct nand_chip *this = mtd_to_nand(mtd); /* Deselect all chips */ this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK; this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK; switch (chip) { case 0: this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0; this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0; break; .... case n: this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn; this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn; break; } }h]hX6static void board_select_chip (struct mtd_info *mtd, int chip) { struct nand_chip *this = mtd_to_nand(mtd); /* Deselect all chips */ this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK; this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK; switch (chip) { case 0: this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0; this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0; break; .... case n: this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn; this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn; break; } }}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMPhj hhubeh}(h]multiple-chip-controlah ]h"]multiple chip controlah$]h&]uh1hhjhhhhhM.ubh)}(hhh](h)}(hHardware ECC supporth]hHardware ECC support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMfubh)}(hhh](h)}(hFunctions and constantsh]hFunctions and constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMiubh)}(h?The nand driver supports three different types of hardware ECC.h]h?The nand driver supports three different types of hardware ECC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjhhubj)}(hhh](j)}(hMNAND_ECC_HW3_256 Hardware ECC generator providing 3 bytes ECC per 256 byte. h](h)}(hNAND_ECC_HW3_256h]hNAND_ECC_HW3_256}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjubh)}(h:Hardware ECC generator providing 3 bytes ECC per 256 byte.h]h:Hardware ECC generator providing 3 bytes ECC per 256 byte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMNAND_ECC_HW3_512 Hardware ECC generator providing 3 bytes ECC per 512 byte. h](h)}(hNAND_ECC_HW3_512h]hNAND_ECC_HW3_512}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjubh)}(h:Hardware ECC generator providing 3 bytes ECC per 512 byte.h]h:Hardware ECC generator providing 3 bytes ECC per 512 byte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMNAND_ECC_HW6_512 Hardware ECC generator providing 6 bytes ECC per 512 byte. h](h)}(hNAND_ECC_HW6_512h]hNAND_ECC_HW6_512}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj'ubh)}(h:Hardware ECC generator providing 6 bytes ECC per 512 byte.h]h:Hardware ECC generator providing 6 bytes ECC per 512 byte.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhj'ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMNAND_ECC_HW8_512 Hardware ECC generator providing 8 bytes ECC per 512 byte. h](h)}(hNAND_ECC_HW8_512h]hNAND_ECC_HW8_512}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhjMubh)}(h:Hardware ECC generator providing 8 bytes ECC per 512 byte.h]h:Hardware ECC generator providing 8 bytes ECC per 512 byte.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjMubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhMmhjhhubh)}(hgIf your hardware generator has a different functionality add it at the appropriate place in nand_base.ch]hgIf your hardware generator has a different functionality add it at the appropriate place in nand_base.c}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjhhubh)}(h2The board driver must provide following functions:h]h2The board driver must provide following functions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(henable_hwecc This function is called before reading / writing to the chip. Reset or initialize the hardware generator in this function. The function is called with an argument which let you distinguish between read and write operations. h](h)}(h enable_hwecch]h enable_hwecc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hThis function is called before reading / writing to the chip. Reset or initialize the hardware generator in this function. The function is called with an argument which let you distinguish between read and write operations.h]hThis function is called before reading / writing to the chip. Reset or initialize the hardware generator in this function. The function is called with an argument which let you distinguish between read and write operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hcalculate_ecc This function is called after read / write from / to the chip. Transfer the ECC from the hardware to the buffer. If the option NAND_HWECC_SYNDROME is set then the function is only called on write. See below. h](h)}(h calculate_ecch]h calculate_ecc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hThis function is called after read / write from / to the chip. Transfer the ECC from the hardware to the buffer. If the option NAND_HWECC_SYNDROME is set then the function is only called on write. See below.h]hThis function is called after read / write from / to the chip. Transfer the ECC from the hardware to the buffer. If the option NAND_HWECC_SYNDROME is set then the function is only called on write. See below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXcorrect_data In case of an ECC error this function is called for error detection and correction. Return 1 respectively 2 in case the error can be corrected. If the error is not correctable return -1. If your hardware generator matches the default algorithm of the nand_ecc software generator then use the correction function provided by nand_ecc instead of implementing duplicated code. h](h)}(h correct_datah]h correct_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hXuIn case of an ECC error this function is called for error detection and correction. Return 1 respectively 2 in case the error can be corrected. If the error is not correctable return -1. If your hardware generator matches the default algorithm of the nand_ecc software generator then use the correction function provided by nand_ecc instead of implementing duplicated code.h]hXuIn case of an ECC error this function is called for error detection and correction. Return 1 respectively 2 in case the error can be corrected. If the error is not correctable return -1. If your hardware generator matches the default algorithm of the nand_ecc software generator then use the correction function provided by nand_ecc instead of implementing duplicated code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhMhjhhubeh}(h]functions-and-constantsah ]h"]functions and constantsah$]h&]uh1hhjhhhhhMiubh)}(hhh](h)}(h&Hardware ECC with syndrome calculationh]h&Hardware ECC with syndrome calculation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hMany hardware ECC implementations provide Reed-Solomon codes and calculate an error syndrome on read. The syndrome must be converted to a standard Reed-Solomon syndrome before calling the error correction code in the generic Reed-Solomon library.h]hMany hardware ECC implementations provide Reed-Solomon codes and calculate an error syndrome on read. The syndrome must be converted to a standard Reed-Solomon syndrome before calling the error correction code in the generic Reed-Solomon library.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXThe ECC bytes must be placed immediately after the data bytes in order to make the syndrome generator work. This is contrary to the usual layout used by software ECC. The separation of data and out of band area is not longer possible. The nand driver code handles this layout and the remaining free bytes in the oob area are managed by the autoplacement code. Provide a matching oob-layout in this case. See rts_from4.c and diskonchip.c for implementation reference. In those cases we must also use bad block tables on FLASH, because the ECC layout is interfering with the bad block marker positions. See bad block table support for details.h]hXThe ECC bytes must be placed immediately after the data bytes in order to make the syndrome generator work. This is contrary to the usual layout used by software ECC. The separation of data and out of band area is not longer possible. The nand driver code handles this layout and the remaining free bytes in the oob area are managed by the autoplacement code. Provide a matching oob-layout in this case. See rts_from4.c and diskonchip.c for implementation reference. In those cases we must also use bad block tables on FLASH, because the ECC layout is interfering with the bad block marker positions. See bad block table support for details.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]&hardware-ecc-with-syndrome-calculationah ]h"]&hardware ecc with syndrome calculationah$]h&]uh1hhjhhhhhMubeh}(h]hardware-ecc-supportah ]h"]hardware ecc supportah$]h&]uh1hhjhhhhhMfubh)}(hhh](h)}(hBad block table supporth]hBad block table support}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhhhMubh)}(hXqMost NAND chips mark the bad blocks at a defined position in the spare area. Those blocks must not be erased under any circumstances as the bad block information would be lost. It is possible to check the bad block mark each time when the blocks are accessed by reading the spare area of the first page in the block. This is time consuming so a bad block table is used.h]hXqMost NAND chips mark the bad blocks at a defined position in the spare area. Those blocks must not be erased under any circumstances as the bad block information would be lost. It is possible to check the bad block mark each time when the blocks are accessed by reading the spare area of the first page in the block. This is time consuming so a bad block table is used.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUhhubh)}(h;The nand driver supports various types of bad block tables.h]h;The nand driver supports various types of bad block tables.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUhhubj)}(hhh](j)}(hvPer device The bad block table contains all bad block information of the device which can consist of multiple chips. h](h)}(h Per deviceh]h Per device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hiThe bad block table contains all bad block information of the device which can consist of multiple chips.h]hiThe bad block table contains all bad block information of the device which can consist of multiple chips.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hnPer chip A bad block table is used per chip and contains the bad block information for this particular chip. h](h)}(hPer chiph]hPer chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hcA bad block table is used per chip and contains the bad block information for this particular chip.h]hcA bad block table is used per chip and contains the bad block information for this particular chip.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hFixed offset The bad block table is located at a fixed offset in the chip (device). This applies to various DiskOnChip devices. h](h)}(h Fixed offseth]h Fixed offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hrThe bad block table is located at a fixed offset in the chip (device). This applies to various DiskOnChip devices.h]hrThe bad block table is located at a fixed offset in the chip (device). This applies to various DiskOnChip devices.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hAutomatic placed The bad block table is automatically placed and detected either at the end or at the beginning of a chip (device) h](h)}(hAutomatic placedh]hAutomatic placed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hqThe bad block table is automatically placed and detected either at the end or at the beginning of a chip (device)h]hqThe bad block table is automatically placed and detected either at the end or at the beginning of a chip (device)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMirrored tables The bad block table is mirrored on the chip (device) to allow updates of the bad block table without data loss. h](h)}(hMirrored tablesh]hMirrored tables}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hoThe bad block table is mirrored on the chip (device) to allow updates of the bad block table without data loss.h]hoThe bad block table is mirrored on the chip (device) to allow updates of the bad block table without data loss.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhMhjUhhubh)}(hnand_scan() calls the function nand_default_bbt(). nand_default_bbt() selects appropriate default bad block table descriptors depending on the chip information which was retrieved by nand_scan().h]hnand_scan() calls the function nand_default_bbt(). nand_default_bbt() selects appropriate default bad block table descriptors depending on the chip information which was retrieved by nand_scan().}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUhhubh)}(hThe standard policy is scanning the device for bad blocks and build a ram based bad block table which allows faster access than always checking the bad block information on the flash chip itself.h]hThe standard policy is scanning the device for bad blocks and build a ram based bad block table which allows faster access than always checking the bad block information on the flash chip itself.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUhhubh)}(hhh](h)}(hFlash based tablesh]hFlash based tables}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhMubh)}(hXIt may be desired or necessary to keep a bad block table in FLASH. For AG-AND chips this is mandatory, as they have no factory marked bad blocks. They have factory marked good blocks. The marker pattern is erased when the block is erased to be reused. So in case of powerloss before writing the pattern back to the chip this block would be lost and added to the bad blocks. Therefore we scan the chip(s) when we detect them the first time for good blocks and store this information in a bad block table before erasing any of the blocks.h]hXIt may be desired or necessary to keep a bad block table in FLASH. For AG-AND chips this is mandatory, as they have no factory marked bad blocks. They have factory marked good blocks. The marker pattern is erased when the block is erased to be reused. So in case of powerloss before writing the pattern back to the chip this block would be lost and added to the bad blocks. Therefore we scan the chip(s) when we detect them the first time for good blocks and store this information in a bad block table before erasing any of the blocks.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjehhubh)}(hThe blocks in which the tables are stored are protected against accidental access by marking them bad in the memory bad block table. The bad block table management functions are allowed to circumvent this protection.h]hThe blocks in which the tables are stored are protected against accidental access by marking them bad in the memory bad block table. The bad block table management functions are allowed to circumvent this protection.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjehhubh)}(hXfThe simplest way to activate the FLASH based bad block table support is to set the option NAND_BBT_USE_FLASH in the bbt_option field of the nand chip structure before calling nand_scan(). For AG-AND chips is this done by default. This activates the default FLASH based bad block table functionality of the NAND driver. The default bad block table options areh]hXfThe simplest way to activate the FLASH based bad block table support is to set the option NAND_BBT_USE_FLASH in the bbt_option field of the nand chip structure before calling nand_scan(). For AG-AND chips is this done by default. This activates the default FLASH based bad block table functionality of the NAND driver. The default bad block table options are}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjehhubj)}(hhh](j)}(hStore bad block table per chip h]h)}(hStore bad block table per chiph]hStore bad block table per chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hUse 2 bits per block h]h)}(hUse 2 bits per blockh]hUse 2 bits per block}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h+Automatic placement at the end of the chip h]h)}(h*Automatic placement at the end of the chiph]h*Automatic placement at the end of the chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h)Use mirrored tables with version numbers h]h)}(h(Use mirrored tables with version numbersh]h(Use mirrored tables with version numbers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h(Reserve 4 blocks at the end of the chip h]h)}(h'Reserve 4 blocks at the end of the chiph]h'Reserve 4 blocks at the end of the chip}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhMhjehhubeh}(h]flash-based-tablesah ]h"]flash based tablesah$]h&]uh1hhjUhhhhhMubh)}(hhh](h)}(hUser defined tablesh]hUser defined tables}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhMubh)}(hXUser defined tables are created by filling out a nand_bbt_descr structure and storing the pointer in the nand_chip structure member bbt_td before calling nand_scan(). If a mirror table is necessary a second structure must be created and a pointer to this structure must be stored in bbt_md inside the nand_chip structure. If the bbt_md member is set to NULL then only the main table is used and no scan for the mirrored table is performed.h]hXUser defined tables are created by filling out a nand_bbt_descr structure and storing the pointer in the nand_chip structure member bbt_td before calling nand_scan(). If a mirror table is necessary a second structure must be created and a pointer to this structure must be stored in bbt_md inside the nand_chip structure. If the bbt_md member is set to NULL then only the main table is used and no scan for the mirrored table is performed.}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj) hhubh)}(hThe most important field in the nand_bbt_descr structure is the options field. The options define most of the table properties. Use the predefined constants from rawnand.h to define the options.h]hThe most important field in the nand_bbt_descr structure is the options field. The options define most of the table properties. Use the predefined constants from rawnand.h to define the options.}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj) hhubj)}(hhh](j)}(hFNumber of bits per block The supported number of bits is 1, 2, 4, 8. h](h)}(hNumber of bits per blockh]hNumber of bits per block}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjY ubh)}(h+The supported number of bits is 1, 2, 4, 8.h]h+The supported number of bits is 1, 2, 4, 8.}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjY ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hTable per chip Setting the constant NAND_BBT_PERCHIP selects that a bad block table is managed for each chip in a chip array. If this option is not set then a per device bad block table is used. h](h)}(hTable per chiph]hTable per chip}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hSetting the constant NAND_BBT_PERCHIP selects that a bad block table is managed for each chip in a chip array. If this option is not set then a per device bad block table is used.h]hSetting the constant NAND_BBT_PERCHIP selects that a bad block table is managed for each chip in a chip array. If this option is not set then a per device bad block table is used.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hXTable location is absolute Use the option constant NAND_BBT_ABSPAGE and define the absolute page number where the bad block table starts in the field pages. If you have selected bad block tables per chip and you have a multi chip array then the start page must be given for each chip in the chip array. Note: there is no scan for a table ident pattern performed, so the fields pattern, veroffs, offs, len can be left uninitialized h](h)}(hTable location is absoluteh]hTable location is absolute}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hXUse the option constant NAND_BBT_ABSPAGE and define the absolute page number where the bad block table starts in the field pages. If you have selected bad block tables per chip and you have a multi chip array then the start page must be given for each chip in the chip array. Note: there is no scan for a table ident pattern performed, so the fields pattern, veroffs, offs, len can be left uninitializedh]hXUse the option constant NAND_BBT_ABSPAGE and define the absolute page number where the bad block table starts in the field pages. If you have selected bad block tables per chip and you have a multi chip array then the start page must be given for each chip in the chip array. Note: there is no scan for a table ident pattern performed, so the fields pattern, veroffs, offs, len can be left uninitialized}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hXTable location is automatically detected The table can either be located in the first or the last good blocks of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block table at the end of the chip (device). The bad block tables are marked and identified by a pattern which is stored in the spare area of the first page in the block which holds the bad block table. Store a pointer to the pattern in the pattern field. Further the length of the pattern has to be stored in len and the offset in the spare area must be given in the offs member of the nand_bbt_descr structure. For mirrored bad block tables different patterns are mandatory. h](h)}(h(Table location is automatically detectedh]h(Table location is automatically detected}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hX_The table can either be located in the first or the last good blocks of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block table at the end of the chip (device). The bad block tables are marked and identified by a pattern which is stored in the spare area of the first page in the block which holds the bad block table. Store a pointer to the pattern in the pattern field. Further the length of the pattern has to be stored in len and the offset in the spare area must be given in the offs member of the nand_bbt_descr structure. For mirrored bad block tables different patterns are mandatory.h]hX_The table can either be located in the first or the last good blocks of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block table at the end of the chip (device). The bad block tables are marked and identified by a pattern which is stored in the spare area of the first page in the block which holds the bad block table. Store a pointer to the pattern in the pattern field. Further the length of the pattern has to be stored in len and the offset in the spare area must be given in the offs member of the nand_bbt_descr structure. For mirrored bad block tables different patterns are mandatory.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hTable creation Set the option NAND_BBT_CREATE to enable the table creation if no table can be found during the scan. Usually this is done only once if a new chip is found. h](h)}(hTable creationh]hTable creation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hj ubh)}(hSet the option NAND_BBT_CREATE to enable the table creation if no table can be found during the scan. Usually this is done only once if a new chip is found.h]hSet the option NAND_BBT_CREATE to enable the table creation if no table can be found during the scan. Usually this is done only once if a new chip is found.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hXTable write support Set the option NAND_BBT_WRITE to enable the table write support. This allows the update of the bad block table(s) in case a block has to be marked bad due to wear. The MTD interface function block_markbad is calling the update function of the bad block table. If the write support is enabled then the table is updated on FLASH. Note: Write support should only be enabled for mirrored tables with version control. h](h)}(hTable write supporth]hTable write support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubh)}(hXGSet the option NAND_BBT_WRITE to enable the table write support. This allows the update of the bad block table(s) in case a block has to be marked bad due to wear. The MTD interface function block_markbad is calling the update function of the bad block table. If the write support is enabled then the table is updated on FLASH.h]hXGSet the option NAND_BBT_WRITE to enable the table write support. This allows the update of the bad block table(s) in case a block has to be marked bad due to wear. The MTD interface function block_markbad is calling the update function of the bad block table. If the write support is enabled then the table is updated on FLASH.}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj ubh)}(hTNote: Write support should only be enabled for mirrored tables with version control.h]hTNote: Write support should only be enabled for mirrored tables with version control.}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hX Table version control Set the option NAND_BBT_VERSION to enable the table version control. It's highly recommended to enable this for mirrored tables with write support. It makes sure that the risk of losing the bad block table information is reduced to the loss of the information about the one worn out block which should be marked bad. The version is stored in 4 consecutive bytes in the spare area of the device. The position of the version number is defined by the member veroffs in the bad block table descriptor. h](h)}(hTable version controlh]hTable version control}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjK ubh)}(hXSet the option NAND_BBT_VERSION to enable the table version control. It's highly recommended to enable this for mirrored tables with write support. It makes sure that the risk of losing the bad block table information is reduced to the loss of the information about the one worn out block which should be marked bad. The version is stored in 4 consecutive bytes in the spare area of the device. The position of the version number is defined by the member veroffs in the bad block table descriptor.h]hXSet the option NAND_BBT_VERSION to enable the table version control. It’s highly recommended to enable this for mirrored tables with write support. It makes sure that the risk of losing the bad block table information is reduced to the loss of the information about the one worn out block which should be marked bad. The version is stored in 4 consecutive bytes in the spare area of the device. The position of the version number is defined by the member veroffs in the bad block table descriptor.}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjK ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hXSave block contents on write In case that the block which holds the bad block table does contain other useful information, set the option NAND_BBT_SAVECONTENT. When the bad block table is written then the whole block is read the bad block table is updated and the block is erased and everything is written back. If this option is not set only the bad block table is written and everything else in the block is ignored and erased. h](h)}(hSave block contents on writeh]hSave block contents on write}(hju hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjq ubh)}(hXIn case that the block which holds the bad block table does contain other useful information, set the option NAND_BBT_SAVECONTENT. When the bad block table is written then the whole block is read the bad block table is updated and the block is erased and everything is written back. If this option is not set only the bad block table is written and everything else in the block is ignored and erased.h]hXIn case that the block which holds the bad block table does contain other useful information, set the option NAND_BBT_SAVECONTENT. When the bad block table is written then the whole block is read the bad block table is updated and the block is erased and everything is written back. If this option is not set only the bad block table is written and everything else in the block is ignored and erased.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjq ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubj)}(hXNumber of reserved blocks For automatic placement some blocks must be reserved for bad block table storage. The number of reserved blocks is defined in the maxblocks member of the bad block table description structure. Reserving 4 blocks for mirrored tables should be a reasonable number. This also limits the number of blocks which are scanned for the bad block table ident pattern. h](h)}(hNumber of reserved blocksh]hNumber of reserved blocks}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj ubh)}(hXeFor automatic placement some blocks must be reserved for bad block table storage. The number of reserved blocks is defined in the maxblocks member of the bad block table description structure. Reserving 4 blocks for mirrored tables should be a reasonable number. This also limits the number of blocks which are scanned for the bad block table ident pattern.h]hXeFor automatic placement some blocks must be reserved for bad block table storage. The number of reserved blocks is defined in the maxblocks member of the bad block table description structure. Reserving 4 blocks for mirrored tables should be a reasonable number. This also limits the number of blocks which are scanned for the bad block table ident pattern.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj ubeh}(h]h ]h"]h$]h&]uh1jhjV hhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhM hj) hhubeh}(h]user-defined-tablesah ]h"]user defined tablesah$]h&]uh1hhjUhhhhhMubeh}(h]bad-block-table-supportah ]h"]bad block table supportah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hSpare area (auto)placementh]hSpare area (auto)placement}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMYubh)}(hfThe nand driver implements different possibilities for placement of filesystem data in the spare area,h]hfThe nand driver implements different possibilities for placement of filesystem data in the spare area,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj hhubj)}(hhh](j)}(hPlacement defined by fs driver h]h)}(hPlacement defined by fs driverh]hPlacement defined by fs driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hAutomatic placement h]h)}(hAutomatic placementh]hAutomatic placement}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhM^hj hhubh)}(hX The default placement function is automatic placement. The nand driver has built in default placement schemes for the various chiptypes. If due to hardware ECC functionality the default placement does not fit then the board driver can provide a own placement scheme.h]hX The default placement function is automatic placement. The nand driver has built in default placement schemes for the various chiptypes. If due to hardware ECC functionality the default placement does not fit then the board driver can provide a own placement scheme.}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj hhubh)}(hmFile system drivers can provide a own placement scheme which is used instead of the default placement scheme.h]hmFile system drivers can provide a own placement scheme which is used instead of the default placement scheme.}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj hhubh)}(h9Placement schemes are defined by a nand_oobinfo structureh]h9Placement schemes are defined by a nand_oobinfo structure}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj hhubjs)}(hestruct nand_oobinfo { int useecc; int eccbytes; int eccpos[24]; int oobfree[8][2]; };h]hestruct nand_oobinfo { int useecc; int eccbytes; int eccpos[24]; int oobfree[8][2]; };}hjU sbah}(h]h ]h"]h$]h&]jjuh1jrhhhMnhj hhubj)}(hhh](j)}(hXuuseecc The useecc member controls the ecc and placement function. The header file include/mtd/mtd-abi.h contains constants to select ecc and placement. MTD_NANDECC_OFF switches off the ecc complete. This is not recommended and available for testing and diagnosis only. MTD_NANDECC_PLACE selects caller defined placement, MTD_NANDECC_AUTOPLACE selects automatic placement. h](h)}(huseecch]huseecc}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjf ubh)}(hXlThe useecc member controls the ecc and placement function. The header file include/mtd/mtd-abi.h contains constants to select ecc and placement. MTD_NANDECC_OFF switches off the ecc complete. This is not recommended and available for testing and diagnosis only. MTD_NANDECC_PLACE selects caller defined placement, MTD_NANDECC_AUTOPLACE selects automatic placement.h]hXlThe useecc member controls the ecc and placement function. The header file include/mtd/mtd-abi.h contains constants to select ecc and placement. MTD_NANDECC_OFF switches off the ecc complete. This is not recommended and available for testing and diagnosis only. MTD_NANDECC_PLACE selects caller defined placement, MTD_NANDECC_AUTOPLACE selects automatic placement.}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjf ubeh}(h]h ]h"]h$]h&]uh1jhjc hhhhhNubj)}(hHeccbytes The eccbytes member defines the number of ecc bytes per page. h](h)}(heccbytesh]heccbytes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(h=The eccbytes member defines the number of ecc bytes per page.h]h=The eccbytes member defines the number of ecc bytes per page.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjc hhhhhNubj)}(hbeccpos The eccpos array holds the byte offsets in the spare area where the ecc codes are placed. h](h)}(heccposh]heccpos}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hYThe eccpos array holds the byte offsets in the spare area where the ecc codes are placed.h]hYThe eccpos array holds the byte offsets in the spare area where the ecc codes are placed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjc hhhhhNubj)}(hX6oobfree The oobfree array defines the areas in the spare area which can be used for automatic placement. The information is given in the format {offset, size}. offset defines the start of the usable area, size the length in bytes. More than one area can be defined. The list is terminated by an {0, 0} entry. h](h)}(hoobfreeh]hoobfree}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hX,The oobfree array defines the areas in the spare area which can be used for automatic placement. The information is given in the format {offset, size}. offset defines the start of the usable area, size the length in bytes. More than one area can be defined. The list is terminated by an {0, 0} entry.h]hX,The oobfree array defines the areas in the spare area which can be used for automatic placement. The information is given in the format {offset, size}. offset defines the start of the usable area, size the length in bytes. More than one area can be defined. The list is terminated by an {0, 0} entry.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjc hhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhMvhj hhubh)}(hhh](h)}(hPlacement defined by fs driverh]hPlacement defined by fs driver}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hXThe calling function provides a pointer to a nand_oobinfo structure which defines the ecc placement. For writes the caller must provide a spare area buffer along with the data buffer. The spare area buffer size is (number of pages) \* (size of spare area). For reads the buffer size is (number of pages) \* ((size of spare area) + (number of ecc steps per page) \* sizeof (int)). The driver stores the result of the ecc check for each tuple in the spare buffer. The storage sequence is::h]hXThe calling function provides a pointer to a nand_oobinfo structure which defines the ecc placement. For writes the caller must provide a spare area buffer along with the data buffer. The spare area buffer size is (number of pages) * (size of spare area). For reads the buffer size is (number of pages) * ((size of spare area) + (number of ecc steps per page) * sizeof (int)). The driver stores the result of the ecc check for each tuple in the spare buffer. The storage sequence is:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubjs)}(hk... ... ...h]hk... ... ...}hj# sbah}(h]h ]h"]h$]h&]jjuh1jrhhhMhj hhubh)}(h%This is a legacy mode used by YAFFS1.h]h%This is a legacy mode used by YAFFS1.}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hIf the spare area buffer is NULL then only the ECC placement is done according to the given scheme in the nand_oobinfo structure.h]hIf the spare area buffer is NULL then only the ECC placement is done according to the given scheme in the nand_oobinfo structure.}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]placement-defined-by-fs-driverah ]h"]placement defined by fs driverah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hAutomatic placementh]hAutomatic placement}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU hhhhhMubh)}(hX$Automatic placement uses the built in defaults to place the ecc bytes in the spare area. If filesystem data have to be stored / read into the spare area then the calling function must provide a buffer. The buffer size per page is determined by the oobfree array in the nand_oobinfo structure.h]hX$Automatic placement uses the built in defaults to place the ecc bytes in the spare area. If filesystem data have to be stored / read into the spare area then the calling function must provide a buffer. The buffer size per page is determined by the oobfree array in the nand_oobinfo structure.}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU hhubh)}(hmIf the spare area buffer is NULL then only the ECC placement is done according to the default builtin scheme.h]hmIf the spare area buffer is NULL then only the ECC placement is done according to the default builtin scheme.}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU hhubeh}(h]automatic-placementah ]h"]automatic placementah$]h&]uh1hhj hhhhhMubeh}(h]spare-area-auto-placementah ]h"]spare area (auto)placementah$]h&]uh1hhjhhhhhMYubh)}(hhh](h)}(h(Spare area autoplacement default schemesh]h(Spare area autoplacement default schemes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h256 byte pagesizeh]h256 byte pagesize}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK3uh1j hj ubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hOffseth]hOffset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hContenth]hContent}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hCommenth]hComment}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]uh1j hj ubhtbody)}(hhh](j )}(hhh](j )}(hhh]h)}(h0x00h]h0x00}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjC ubah}(h]h ]h"]h$]h&]uh1j hj@ ubj )}(hhh]h)}(h ECC byte 0h]h ECC byte 0}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZ ubah}(h]h ]h"]h$]h&]uh1j hj@ ubj )}(hhh]h)}(hError correction code byte 0h]hError correction code byte 0}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjq ubah}(h]h ]h"]h$]h&]uh1j hj@ ubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x01h]h0x01}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h ECC byte 1h]h ECC byte 1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hError correction code byte 1h]hError correction code byte 1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x02h]h0x02}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h ECC byte 2h]h ECC byte 2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hError correction code byte 2h]hError correction code byte 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x03h]h0x03}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1j hj*ubj )}(hhh]h)}(h Autoplace 0h]h Autoplace 0}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1j hj*ubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x04h]h0x04}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjmubah}(h]h ]h"]h$]h&]uh1j hjjubj )}(hhh]h)}(h Autoplace 1h]h Autoplace 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjjubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hjjubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x05h]h0x05}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hBad block markerh]hBad block marker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reservedh]hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x06h]h0x06}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h Autoplace 2h]h Autoplace 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hj= ubj )}(hhh](j )}(hhh]h)}(h0x07h]h0x07}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1j hj8ubj )}(hhh]h)}(h Autoplace 3h]h Autoplace 3}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1j hj8ubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hj8ubeh}(h]h ]h"]h$]h&]uh1j hj= ubeh}(h]h ]h"]h$]h&]uh1j; hj ubeh}(h]h ]h"]h$]h&]colsKuh1j hj ubah}(h]h ]h"]h$]h&]uh1j hj hhhhhNubeh}(h] byte-pagesizeah ]h"]256 byte pagesizeah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h512 byte pagesizeh]h512 byte pagesize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj )}(hhh]j )}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK.uh1j hjubj )}(hhh]j )}(hhh](j )}(hhh]h)}(hOffseth]hOffset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hContenth]hContent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hCommenth]hComment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hjubj< )}(hhh](j )}(hhh](j )}(hhh]h)}(h0x00h]h0x00}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1j hj"ubj )}(hhh]h)}(h ECC byte 0h]h ECC byte 0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1j hj"ubj )}(hhh]h)}(hDError correction code byte 0 of the lower 256 Byte data in this pageh]hDError correction code byte 0 of the lower 256 Byte data in this page}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjSubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x01h]h0x01}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1j hjpubj )}(hhh]h)}(h ECC byte 1h]h ECC byte 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjpubj )}(hhh]h)}(hHError correction code byte 1 of the lower 256 Bytes of data in this pageh]hHError correction code byte 1 of the lower 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjpubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x02h]h0x02}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 2h]h ECC byte 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 2 of the lower 256 Bytes of data in this pageh]hHError correction code byte 2 of the lower 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x03h]h0x03}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h ECC byte 3h]h ECC byte 3}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hHError correction code byte 0 of the upper 256 Bytes of data in this pageh]hHError correction code byte 0 of the upper 256 Bytes of data in this page}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x04h]h0x04}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]ubah}(h]h ]h"]h$]h&]uh1j hjZubj )}(hhh]h)}(hreservedh]hreserved}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjtubah}(h]h ]h"]h$]h&]uh1j hjZubj )}(hhh]h)}(hreservedh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjZubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x05h]h0x05}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hBad block markerh]hBad block marker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reservedh]hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x06h]h0x06}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 4h]h ECC byte 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 1 of the upper 256 Bytes of data in this pageh]hHError correction code byte 1 of the upper 256 Bytes of data in this page}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h0x07h]h0x07}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1j hjDubj )}(hhh]h)}(h ECC byte 5h]h ECC byte 5}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1j hjDubj )}(hhh]h)}(hHError correction code byte 2 of the upper 256 Bytes of data in this pageh]hHError correction code byte 2 of the upper 256 Bytes of data in this page}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjuubah}(h]h ]h"]h$]h&]uh1j hjDubeh}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh](j )}(hhh]h)}(h 0x08 - 0x0Fh]h 0x08 - 0x0F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hAutoplace 0 - 7h]hAutoplace 0 - 7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j; hjubeh}(h]h ]h"]h$]h&]colsKuh1j hjubah}(h]h ]h"]h$]h&]uh1j hjhhhhhNubeh}(h]id1ah ]h"]512 byte pagesizeah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h2048 byte pagesizeh]h2048 byte pagesize}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj )}(hhh]j )}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthK0uh1j hjubj )}(hhh]j )}(hhh](j )}(hhh]h)}(hOffseth]hOffset}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1j hj%ubj )}(hhh]h)}(hContenth]hContent}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?ubah}(h]h ]h"]h$]h&]uh1j hj%ubj )}(hhh]h)}(hCommenth]hComment}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1j hj"ubah}(h]h ]h"]h$]h&]uh1j hjubj< )}(hhh](j )}(hhh](j )}(hhh]h)}(h0x00h]h0x00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj|ubj )}(hhh]h)}(hBad block markerh]hBad block marker}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj|ubj )}(hhh]h)}(hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reservedh]hIf any bit in this byte is zero, then this block is bad. This applies only to the first page in a block. In the remaining pages this byte is reserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj|ubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x01h]h0x01}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hReservedh]hReserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h 0x02-0x27h]h 0x02-0x27}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hAutoplace 0 - 37h]hAutoplace 0 - 37}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x28h]h0x28}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1j hjXubj )}(hhh]h)}(h ECC byte 0h]h ECC byte 0}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjrubah}(h]h ]h"]h$]h&]uh1j hjXubj )}(hhh]h)}(hDError correction code byte 0 of the first 256 Byte data in this pageh]hDError correction code byte 0 of the first 256 Byte data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjXubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x29h]h0x29}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 1h]h ECC byte 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 1 of the first 256 Bytes of data in this pageh]hHError correction code byte 1 of the first 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Ah]h0x2A}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 2h]h ECC byte 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hEError correction code byte 2 of the first 256 Bytes data in this pageh]hEError correction code byte 2 of the first 256 Bytes data in this page}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Bh]h0x2B}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1j hjBubj )}(hhh]h)}(h ECC byte 3h]h ECC byte 3}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1j hjBubj )}(hhh]h)}(hIError correction code byte 0 of the second 256 Bytes of data in this pageh]hIError correction code byte 0 of the second 256 Bytes of data in this page}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1j hjBubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Ch]h0x2C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 4h]h ECC byte 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIError correction code byte 1 of the second 256 Bytes of data in this pageh]hIError correction code byte 1 of the second 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Dh]h0x2D}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 5h]h ECC byte 5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIError correction code byte 2 of the second 256 Bytes of data in this pageh]hIError correction code byte 2 of the second 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Eh]h0x2E}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1j hj,ubj )}(hhh]h)}(h ECC byte 6h]h ECC byte 6}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1j hj,ubj )}(hhh]h)}(hHError correction code byte 0 of the third 256 Bytes of data in this pageh]hHError correction code byte 0 of the third 256 Bytes of data in this page}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]ubah}(h]h ]h"]h$]h&]uh1j hj,ubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x2Fh]h0x2F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}ubah}(h]h ]h"]h$]h&]uh1j hjzubj )}(hhh]h)}(h ECC byte 7h]h ECC byte 7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjzubj )}(hhh]h)}(hHError correction code byte 1 of the third 256 Bytes of data in this pageh]hHError correction code byte 1 of the third 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjzubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x30h]h0x30}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 8h]h ECC byte 8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 2 of the third 256 Bytes of data in this pageh]hHError correction code byte 2 of the third 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x31h]h0x31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 9h]h ECC byte 9}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIError correction code byte 0 of the fourth 256 Bytes of data in this pageh]hIError correction code byte 0 of the fourth 256 Bytes of data in this page}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x32h]h0x32}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjgubah}(h]h ]h"]h$]h&]uh1j hjdubj )}(hhh]h)}(h ECC byte 10h]h ECC byte 10}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj~ubah}(h]h ]h"]h$]h&]uh1j hjdubj )}(hhh]h)}(hIError correction code byte 1 of the fourth 256 Bytes of data in this pageh]hIError correction code byte 1 of the fourth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjdubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x33h]h0x33}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 11h]h ECC byte 11}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIError correction code byte 2 of the fourth 256 Bytes of data in this pageh]hIError correction code byte 2 of the fourth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x34h]h0x34}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 12h]h ECC byte 12}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 0 of the fifth 256 Bytes of data in this pageh]hHError correction code byte 0 of the fifth 256 Bytes of data in this page}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x35h]h0x35}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjQubah}(h]h ]h"]h$]h&]uh1j hjNubj )}(hhh]h)}(h ECC byte 13h]h ECC byte 13}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1j hjNubj )}(hhh]h)}(hHError correction code byte 1 of the fifth 256 Bytes of data in this pageh]hHError correction code byte 1 of the fifth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjNubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x36h]h0x36}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 14h]h ECC byte 14}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 2 of the fifth 256 Bytes of data in this pageh]hHError correction code byte 2 of the fifth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x37h]h0x37}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 15h]h ECC byte 15}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 0 of the sixth 256 Bytes of data in this pageh]hHError correction code byte 0 of the sixth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x38h]h0x38}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1j hj8ubj )}(hhh]h)}(h ECC byte 16h]h ECC byte 16}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1j hj8ubj )}(hhh]h)}(hHError correction code byte 1 of the sixth 256 Bytes of data in this pageh]hHError correction code byte 1 of the sixth 256 Bytes of data in this page}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1j hj8ubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x39h]h0x39}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 17h]h ECC byte 17}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hHError correction code byte 2 of the sixth 256 Bytes of data in this pageh]hHError correction code byte 2 of the sixth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Ah]h0x3A}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 18h]h ECC byte 18}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hJError correction code byte 0 of the seventh 256 Bytes of data in this pageh]hJError correction code byte 0 of the seventh 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Bh]h0x3B}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1j hj"ubj )}(hhh]h)}(h ECC byte 19h]h ECC byte 19}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1j hj"ubj )}(hhh]h)}(hJError correction code byte 1 of the seventh 256 Bytes of data in this pageh]hJError correction code byte 1 of the seventh 256 Bytes of data in this page}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjSubah}(h]h ]h"]h$]h&]uh1j hj"ubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Ch]h0x3C}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1j hjpubj )}(hhh]h)}(h ECC byte 20h]h ECC byte 20}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjpubj )}(hhh]h)}(hJError correction code byte 2 of the seventh 256 Bytes of data in this pageh]hJError correction code byte 2 of the seventh 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjpubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Dh]h0x3D}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(h ECC byte 21h]h ECC byte 21}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubj )}(hhh]h)}(hIError correction code byte 0 of the eighth 256 Bytes of data in this pageh]hIError correction code byte 0 of the eighth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Eh]h0x3E}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(h ECC byte 22h]h ECC byte 22}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j hj ubj )}(hhh]h)}(hIError correction code byte 1 of the eighth 256 Bytes of data in this pageh]hIError correction code byte 1 of the eighth 256 Bytes of data in this page}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hjyubj )}(hhh](j )}(hhh]h)}(h0x3Fh]h0x3F}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]ubah}(h]h ]h"]h$]h&]uh1j hjZubj )}(hhh]h)}(h ECC byte 23h]h ECC byte 23}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjtubah}(h]h ]h"]h$]h&]uh1j hjZubj )}(hhh]h)}(hIError correction code byte 2 of the eighth 256 Bytes of data in this pageh]hIError correction code byte 2 of the eighth 256 Bytes of data in this page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjZubeh}(h]h ]h"]h$]h&]uh1j hjyubeh}(h]h ]h"]h$]h&]uh1j; hjubeh}(h]h ]h"]h$]h&]colsKuh1j hjubah}(h]h ]h"]h$]h&]uh1j hjhhhhhNubeh}(h]id2ah ]h"]2048 byte pagesizeah$]h&]uh1hhj hhhhhMubeh}(h](spare-area-autoplacement-default-schemesah ]h"](spare area autoplacement default schemesah$]h&]uh1hhjhhhhhMubeh}(h]advanced-board-driver-functionsah ]h"]advanced board driver functionsah$]h&]uh1hhhhhhhhM'ubh)}(hhh](h)}(hFilesystem supporth]hFilesystem support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM"ubh)}(hXThe NAND driver provides all necessary functions for a filesystem via the MTD interface.h]hXThe NAND driver provides all necessary functions for a filesystem via the MTD interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubh)}(hXTFilesystems must be aware of the NAND peculiarities and restrictions. One major restrictions of NAND Flash is, that you cannot write as often as you want to a page. The consecutive writes to a page, before erasing it again, are restricted to 1-3 writes, depending on the manufacturers specifications. This applies similar to the spare area.h]hXTFilesystems must be aware of the NAND peculiarities and restrictions. One major restrictions of NAND Flash is, that you cannot write as often as you want to a page. The consecutive writes to a page, before erasing it again, are restricted to 1-3 writes, depending on the manufacturers specifications. This applies similar to the spare area.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjhhubh)}(hTherefore NAND aware filesystems must either write in page size chunks or hold a writebuffer to collect smaller writes until they sum up to pagesize. Available NAND aware filesystems: JFFS2, YAFFS.h]hTherefore NAND aware filesystems must either write in page size chunks or hold a writebuffer to collect smaller writes until they sum up to pagesize. Available NAND aware filesystems: JFFS2, YAFFS.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjhhubh)}(hThe spare area usage to store filesystem data is controlled by the spare area placement functionality which is described in one of the earlier chapters.h]hThe spare area usage to store filesystem data is controlled by the spare area placement functionality which is described in one of the earlier chapters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjhhubeh}(h]filesystem-supportah ]h"]filesystem supportah$]h&]uh1hhhhhhhhM"ubh)}(hhh](h)}(hToolsh]hTools}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhM6ubh)}(hHThe MTD project provides a couple of helpful tools to handle NAND Flash.h]hHThe MTD project provides a couple of helpful tools to handle NAND Flash.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj$hhubj)}(hhh](j)}(h=flasherase, flasheraseall: Erase and format FLASH partitions h]h)}(hhjvubah}(h]h ]h"]h$]h&]uh1jhjChhhhhNubeh}(h]h ]h"]h$]h&]jLjMuh1jhhhM:hj$hhubh)}(hThese tools are aware of the NAND restrictions. Please use those tools instead of complaining about errors which are caused by non NAND aware access methods.h]hThese tools are aware of the NAND restrictions. Please use those tools instead of complaining about errors which are caused by non NAND aware access methods.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hj$hhubeh}(h]toolsah ]h"]toolsah$]h&]uh1hhhhhhhhM6ubh)}(hhh](h)}(h Constantsh]h Constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMEubh)}(hTThis chapter describes the constants which might be relevant for a driver developer.h]hTThis chapter describes the constants which might be relevant for a driver developer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjhhubh)}(hhh](h)}(hChip option constantsh]hChip option constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMKubh)}(hhh](h)}(hConstants for chip id tableh]hConstants for chip id table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMNubh)}(hfThese constants are defined in rawnand.h. They are OR-ed together to describe the chip functionality::h]heThese constants are defined in rawnand.h. They are OR-ed together to describe the chip functionality:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjhhubjs)}(hXW/* Buswitdh is 16 bit */ #define NAND_BUSWIDTH_16 0x00000002 /* Device supports partial programming without padding */ #define NAND_NO_PADDING 0x00000004 /* Chip has cache program function */ #define NAND_CACHEPRG 0x00000008 /* Chip has copy back function */ #define NAND_COPYBACK 0x00000010 /* AND Chip which has 4 banks and a confusing page / block * assignment. See Renesas datasheet for further information */ #define NAND_IS_AND 0x00000020 /* Chip has a array of 4 pages which can be read without * additional ready /busy waits */ #define NAND_4PAGE_ARRAY 0x00000040h]hXW/* Buswitdh is 16 bit */ #define NAND_BUSWIDTH_16 0x00000002 /* Device supports partial programming without padding */ #define NAND_NO_PADDING 0x00000004 /* Chip has cache program function */ #define NAND_CACHEPRG 0x00000008 /* Chip has copy back function */ #define NAND_COPYBACK 0x00000010 /* AND Chip which has 4 banks and a confusing page / block * assignment. See Renesas datasheet for further information */ #define NAND_IS_AND 0x00000020 /* Chip has a array of 4 pages which can be read without * additional ready /busy waits */ #define NAND_4PAGE_ARRAY 0x00000040}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMShjhhubeh}(h]constants-for-chip-id-tableah ]h"]constants for chip id tableah$]h&]uh1hhjhhhhhMNubh)}(hhh](h)}(hConstants for runtime optionsh]hConstants for runtime options}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMdubh)}(haThese constants are defined in rawnand.h. They are OR-ed together to describe the functionality::h]h`These constants are defined in rawnand.h. They are OR-ed together to describe the functionality:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjhhubjs)}(hX/* The hw ecc generator provides a syndrome instead a ecc value on read * This can only work if we have the ecc bytes directly behind the * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ #define NAND_HWECC_SYNDROME 0x00020000h]hX/* The hw ecc generator provides a syndrome instead a ecc value on read * This can only work if we have the ecc bytes directly behind the * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ #define NAND_HWECC_SYNDROME 0x00020000}hj.sbah}(h]h ]h"]h$]h&]jjuh1jrhhhMihjhhubeh}(h]constants-for-runtime-optionsah ]h"]constants for runtime optionsah$]h&]uh1hhjhhhhhMdubeh}(h]chip-option-constantsah ]h"]chip option constantsah$]h&]uh1hhjhhhhhMKubh)}(hhh](h)}(hECC selection constantsh]hECC selection constants}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhMpubh)}(h1Use these constants to select the ECC algorithm::h]h0Use these constants to select the ECC algorithm:}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjLhhubjs)}(hX/* No ECC. Usage is not recommended ! */ #define NAND_ECC_NONE 0 /* Software ECC 3 byte ECC per 256 Byte data */ #define NAND_ECC_SOFT 1 /* Hardware ECC 3 byte ECC per 256 Byte data */ #define NAND_ECC_HW3_256 2 /* Hardware ECC 3 byte ECC per 512 Byte data */ #define NAND_ECC_HW3_512 3 /* Hardware ECC 6 byte ECC per 512 Byte data */ #define NAND_ECC_HW6_512 4 /* Hardware ECC 8 byte ECC per 512 Byte data */ #define NAND_ECC_HW8_512 6h]hX/* No ECC. Usage is not recommended ! */ #define NAND_ECC_NONE 0 /* Software ECC 3 byte ECC per 256 Byte data */ #define NAND_ECC_SOFT 1 /* Hardware ECC 3 byte ECC per 256 Byte data */ #define NAND_ECC_HW3_256 2 /* Hardware ECC 3 byte ECC per 512 Byte data */ #define NAND_ECC_HW3_512 3 /* Hardware ECC 6 byte ECC per 512 Byte data */ #define NAND_ECC_HW6_512 4 /* Hardware ECC 8 byte ECC per 512 Byte data */ #define NAND_ECC_HW8_512 6}hjksbah}(h]h ]h"]h$]h&]jjuh1jrhhhMthjLhhubeh}(h]ecc-selection-constantsah ]h"]ecc selection constantsah$]h&]uh1hhjhhhhhMpubh)}(hhh](h)}(h"Hardware control related constantsh]h"Hardware control related constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h|These constants describe the requested hardware access function when the boardspecific hardware control function is called::h]h{These constants describe the requested hardware access function when the boardspecific hardware control function is called:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubjs)}(hX/* Select the chip by setting nCE to low */ #define NAND_CTL_SETNCE 1 /* Deselect the chip by setting nCE to high */ #define NAND_CTL_CLRNCE 2 /* Select the command latch by setting CLE to high */ #define NAND_CTL_SETCLE 3 /* Deselect the command latch by setting CLE to low */ #define NAND_CTL_CLRCLE 4 /* Select the address latch by setting ALE to high */ #define NAND_CTL_SETALE 5 /* Deselect the address latch by setting ALE to low */ #define NAND_CTL_CLRALE 6 /* Set write protection by setting WP to high. Not used! */ #define NAND_CTL_SETWP 7 /* Clear write protection by setting WP to low. Not used! */ #define NAND_CTL_CLRWP 8h]hX/* Select the chip by setting nCE to low */ #define NAND_CTL_SETNCE 1 /* Deselect the chip by setting nCE to high */ #define NAND_CTL_CLRNCE 2 /* Select the command latch by setting CLE to high */ #define NAND_CTL_SETCLE 3 /* Deselect the command latch by setting CLE to low */ #define NAND_CTL_CLRCLE 4 /* Select the address latch by setting ALE to high */ #define NAND_CTL_SETALE 5 /* Deselect the address latch by setting ALE to low */ #define NAND_CTL_CLRALE 6 /* Set write protection by setting WP to high. Not used! */ #define NAND_CTL_SETWP 7 /* Clear write protection by setting WP to low. Not used! */ #define NAND_CTL_CLRWP 8}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMhjhhubeh}(h]"hardware-control-related-constantsah ]h"]"hardware control related constantsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h!Bad block table related constantsh]h!Bad block table related constants}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hKThese constants describe the options used for bad block table descriptors::h]hJThese constants describe the options used for bad block table descriptors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubjs)}(hX/* Options for the bad block table descriptors */ /* The number of bits used per block in the bbt on the device */ #define NAND_BBT_NRBITS_MSK 0x0000000F #define NAND_BBT_1BIT 0x00000001 #define NAND_BBT_2BIT 0x00000002 #define NAND_BBT_4BIT 0x00000004 #define NAND_BBT_8BIT 0x00000008 /* The bad block table is in the last good block of the device */ #define NAND_BBT_LASTBLOCK 0x00000010 /* The bbt is at the given page, else we must scan for the bbt */ #define NAND_BBT_ABSPAGE 0x00000020 /* bbt is stored per chip on multichip devices */ #define NAND_BBT_PERCHIP 0x00000080 /* bbt has a version counter at offset veroffs */ #define NAND_BBT_VERSION 0x00000100 /* Create a bbt if none axists */ #define NAND_BBT_CREATE 0x00000200 /* Write bbt if necessary */ #define NAND_BBT_WRITE 0x00001000 /* Read and write back block contents when writing bbt */ #define NAND_BBT_SAVECONTENT 0x00002000h]hX/* Options for the bad block table descriptors */ /* The number of bits used per block in the bbt on the device */ #define NAND_BBT_NRBITS_MSK 0x0000000F #define NAND_BBT_1BIT 0x00000001 #define NAND_BBT_2BIT 0x00000002 #define NAND_BBT_4BIT 0x00000004 #define NAND_BBT_8BIT 0x00000008 /* The bad block table is in the last good block of the device */ #define NAND_BBT_LASTBLOCK 0x00000010 /* The bbt is at the given page, else we must scan for the bbt */ #define NAND_BBT_ABSPAGE 0x00000020 /* bbt is stored per chip on multichip devices */ #define NAND_BBT_PERCHIP 0x00000080 /* bbt has a version counter at offset veroffs */ #define NAND_BBT_VERSION 0x00000100 /* Create a bbt if none axists */ #define NAND_BBT_CREATE 0x00000200 /* Write bbt if necessary */ #define NAND_BBT_WRITE 0x00001000 /* Read and write back block contents when writing bbt */ #define NAND_BBT_SAVECONTENT 0x00002000}hjsbah}(h]h ]h"]h$]h&]jjuh1jrhhhMhjhhubeh}(h]!bad-block-table-related-constantsah ]h"]!bad block table related constantsah$]h&]uh1hhjhhhhhMubeh}(h] constantsah ]h"] constantsah$]h&]uh1hhhhhhhhMEubh)}(hhh](h)}(h Structuresh]h Structures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX&This chapter contains the autogenerated documentation of the structures which are used in the NAND driver and might be relevant for a driver developer. Each struct member has a short description which is marked with an [XXX] identifier. See the chapter "Documentation hints" for an explanation.h]hX*This chapter contains the autogenerated documentation of the structures which are used in the NAND driver and might be relevant for a driver developer. Each struct member has a short description which is marked with an [XXX] identifier. See the chapter “Documentation hints” for an explanation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlenand_parameters (C struct)c.nand_parametershNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(hnand_parametersh]hdesc_signature_line)}(hstruct nand_parametersh](hdesc_sig_keyword)}(hstructh]hstruct}(hj6hhhNhNubah}(h]h ]kah"]h$]h&]uh1j4hj0hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKubhdesc_sig_space)}(h h]h }(hjHhhhNhNubah}(h]h ]wah"]h$]h&]uh1jFhj0hhhjEhKubh desc_name)}(hnand_parametersh]h desc_sig_name)}(hj,h]hnand_parameters}(hj_hhhNhNubah}(h]h ]nah"]h$]h&]uh1j]hjYubah}(h]h ](sig-namedescnameeh"]h$]h&]jjuh1jWhj0hhhjEhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1j.sphinx_line_type declaratorhj*hhhjEhKubah}(h]j!ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j(hjEhKhj%hhubh desc_content)}(hhh]h)}(h/NAND generic parameters from the parameter pageh]h/NAND generic parameters from the parameter page}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhj%hhhjEhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j#hhhjhNhNubh container)}(hX **Definition**:: struct nand_parameters { const char *model; bool supports_set_get_features; bool supports_read_cache; unsigned long set_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; unsigned long get_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; struct onfi_params *onfi; }; **Members** ``model`` Model name ``supports_set_get_features`` The NAND chip supports setting/getting features ``supports_read_cache`` The NAND chip supports read cache operations ``set_feature_list`` Bitmap of features that can be set ``get_feature_list`` Bitmap of features that can be get ``onfi`` ONFI specific parametersh](h block_quote)}(hXS**Definition**:: struct nand_parameters { const char *model; bool supports_set_get_features; bool supports_read_cache; unsigned long set_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; unsigned long get_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; struct onfi_params *onfi; }; h](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubjs)}(hX0struct nand_parameters { const char *model; bool supports_set_get_features; bool supports_read_cache; unsigned long set_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; unsigned long get_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; struct onfi_params *onfi; };h]hX0struct nand_parameters { const char *model; bool supports_set_get_features; bool supports_read_cache; unsigned long set_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; unsigned long get_feature_list[BITS_TO_LONGS( ONFI_FEATURE_NUMBER)]; struct onfi_params *onfi; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubhdefinition_list)}(hhh](hdefinition_list_item)}(h``model`` Model name h](hterm)}(h ``model``h]hliteral)}(hjh]hmodel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubh definition)}(hhh]h)}(h Model nameh]h Model name}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hKhj2ubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhj/hKhj ubj)}(hN``supports_set_get_features`` The NAND chip supports setting/getting features h](j)}(h``supports_set_get_features``h]j)}(hjUh]hsupports_set_get_features}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjOubj1)}(hhh]h)}(h/The NAND chip supports setting/getting featuresh]h/The NAND chip supports setting/getting features}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhKhjkubah}(h]h ]h"]h$]h&]uh1j0hjOubeh}(h]h ]h"]h$]h&]uh1jhjjhKhj ubj)}(hE``supports_read_cache`` The NAND chip supports read cache operations h](j)}(h``supports_read_cache``h]j)}(hjh]hsupports_read_cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubj1)}(hhh]h)}(h,The NAND chip supports read cache operationsh]h,The NAND chip supports read cache operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h8``set_feature_list`` Bitmap of features that can be set h](j)}(h``set_feature_list``h]j)}(hjh]hset_feature_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubj1)}(hhh]h)}(h"Bitmap of features that can be seth]h"Bitmap of features that can be set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h8``get_feature_list`` Bitmap of features that can be get h](j)}(h``get_feature_list``h]j)}(hj h]hget_feature_list}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjubj1)}(hhh]h)}(h"Bitmap of features that can be geth]h"Bitmap of features that can be get}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h!``onfi`` ONFI specific parametersh](j)}(h``onfi``h]j)}(hj9 h]honfi}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7 ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj3 ubj1)}(hhh]h)}(hONFI specific parametersh]hONFI specific parameters}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjO ubah}(h]h ]h"]h$]h&]uh1j0hj3 ubeh}(h]h ]h"]h$]h&]uh1jhjN hKhj ubeh}(h]h ]h"]h$]h&]uh1j hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_id (C struct) c.nand_idhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_idh]j/)}(hstruct nand_idh](j5)}(hj8h]hstruct}(hj hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKubjG)}(h h]h }(hj hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj hhhj hKubjX)}(hnand_idh]j^)}(hj h]hnand_id}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj hhhj hKubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj hhhj hKubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j(hj hKhj hhubj)}(hhh]h)}(hNAND id structureh]hNAND id structure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_id { u8 data[NAND_MAX_ID_LEN]; int len; }; **Members** ``data`` buffer containing the id bytes. ``len`` ID length.h](j)}(h]**Definition**:: struct nand_id { u8 data[NAND_MAX_ID_LEN]; int len; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj ubjs)}(hBstruct nand_id { u8 data[NAND_MAX_ID_LEN]; int len; };h]hBstruct nand_id { u8 data[NAND_MAX_ID_LEN]; int len; };}hj!sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj!hKhj ubh)}(h **Members**h]j)}(hj-!h]hMembers}(hj/!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+!ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj ubj )}(hhh](j)}(h)``data`` buffer containing the id bytes. h](j)}(h``data``h]j)}(hjL!h]hdata}(hjN!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ!ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjF!ubj1)}(hhh]h)}(hbuffer containing the id bytes.h]hbuffer containing the id bytes.}(hje!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja!hKhjb!ubah}(h]h ]h"]h$]h&]uh1j0hjF!ubeh}(h]h ]h"]h$]h&]uh1jhja!hKhjC!ubj)}(h``len`` ID length.h](j)}(h``len``h]j)}(hj!h]hlen}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj!ubj1)}(hhh]h)}(h ID length.h]h ID length.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj!ubah}(h]h ]h"]h$]h&]uh1j0hj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hKhjC!ubeh}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_ecc_step_info (C struct)c.nand_ecc_step_infohNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_ecc_step_infoh]j/)}(hstruct nand_ecc_step_infoh](j5)}(hj8h]hstruct}(hj!hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj!hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj!hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj!hhhj!hMubjX)}(hnand_ecc_step_infoh]j^)}(hj!h]hnand_ecc_step_info}(hj!hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj!ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj!hhhj!hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj!hhhj!hMubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1j(hj!hMhj!hhubj)}(hhh]h)}(h"ECC step information of ECC engineh]h"ECC step information of ECC engine}(hj!"hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj"hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hMubeh}(h]h ](jstructeh"]h$]h&]jjjj9"jj9"jjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths; }; **Members** ``stepsize`` data bytes per ECC step ``strengths`` array of supported strengths ``nstrengths`` number of supported strengthsh](j)}(h**Definition**:: struct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjI"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE"ubh:}(hjE"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjA"ubjs)}(hdstruct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths; };h]hdstruct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths; };}hjb"sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hjA"ubeh}(h]h ]h"]h$]h&]uh1jhja"hMhj="ubh)}(h **Members**h]j)}(hjy"h]hMembers}(hj{"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw"ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj="ubj )}(hhh](j)}(h%``stepsize`` data bytes per ECC step h](j)}(h ``stepsize``h]j)}(hj"h]hstepsize}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj"ubj1)}(hhh]h)}(hdata bytes per ECC steph]hdata bytes per ECC step}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj"ubah}(h]h ]h"]h$]h&]uh1j0hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMhj"ubj)}(h+``strengths`` array of supported strengths h](j)}(h ``strengths``h]j)}(hj"h]h strengths}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj"ubj1)}(hhh]h)}(harray of supported strengthsh]harray of supported strengths}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hMhj"ubah}(h]h ]h"]h$]h&]uh1j0hj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMhj"ubj)}(h,``nstrengths`` number of supported strengthsh](j)}(h``nstrengths``h]j)}(hj #h]h nstrengths}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj#ubj1)}(hhh]h)}(hnumber of supported strengthsh]hnumber of supported strengths}(hj##hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj #ubah}(h]h ]h"]h$]h&]uh1j0hj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhj"ubeh}(h]h ]h"]h$]h&]uh1j hj="ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_ecc_caps (C struct)c.nand_ecc_capshNtauh1jhjhhhNhNubj$)}(hhh](j))}(h nand_ecc_capsh]j/)}(hstruct nand_ecc_capsh](j5)}(hj8h]hstruct}(hjd#hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj`#hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM ubjG)}(h h]h }(hjr#hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj`#hhhjq#hM ubjX)}(h nand_ecc_capsh]j^)}(hj^#h]h nand_ecc_caps}(hj#hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj#ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj`#hhhjq#hM ubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj\#hhhjq#hM ubah}(h]jW#ah ](jjeh"]h$]h&]jj)jhuh1j(hjq#hM hjY#hhubj)}(hhh]h)}(hcapability of ECC engineh]hcapability of ECC engine}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj#hhubah}(h]h ]h"]h$]h&]uh1jhjY#hhhjq#hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj#jj#jjjuh1j#hhhjhNhNubj)}(hXt **Definition**:: struct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength); }; **Members** ``stepinfos`` array of ECC step information ``nstepinfos`` number of ECC step information ``calc_ecc_bytes`` driver's hook to calculate ECC bytes per steph](j)}(h**Definition**:: struct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength); }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubh:}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj#ubjs)}(hstruct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength); };h]hstruct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength); };}hj#sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMhj#ubh)}(h **Members**h]j)}(hj#h]hMembers}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj#ubj )}(hhh](j)}(h,``stepinfos`` array of ECC step information h](j)}(h ``stepinfos``h]j)}(hj$h]h stepinfos}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj$ubj1)}(hhh]h)}(harray of ECC step informationh]harray of ECC step information}(hj6$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2$hMhj3$ubah}(h]h ]h"]h$]h&]uh1j0hj$ubeh}(h]h ]h"]h$]h&]uh1jhj2$hMhj$ubj)}(h.``nstepinfos`` number of ECC step information h](j)}(h``nstepinfos``h]j)}(hjV$h]h nstepinfos}(hjX$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT$ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjP$ubj1)}(hhh]h)}(hnumber of ECC step informationh]hnumber of ECC step information}(hjo$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk$hMhjl$ubah}(h]h ]h"]h$]h&]uh1j0hjP$ubeh}(h]h ]h"]h$]h&]uh1jhjk$hMhj$ubj)}(h@``calc_ecc_bytes`` driver's hook to calculate ECC bytes per steph](j)}(h``calc_ecc_bytes``h]j)}(hj$h]hcalc_ecc_bytes}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj$ubj1)}(hhh]h)}(h-driver's hook to calculate ECC bytes per steph]h/driver’s hook to calculate ECC bytes per step}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj$ubah}(h]h ]h"]h$]h&]uh1j0hj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhj$ubeh}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_ecc_ctrl (C struct)c.nand_ecc_ctrlhNtauh1jhjhhhNhNubj$)}(hhh](j))}(h nand_ecc_ctrlh]j/)}(hstruct nand_ecc_ctrlh](j5)}(hj8h]hstruct}(hj$hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj$hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj$hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj$hhhj$hMubjX)}(h nand_ecc_ctrlh]j^)}(hj$h]h nand_ecc_ctrl}(hj %hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj%ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj$hhhj$hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj$hhhj$hMubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1j(hj$hMhj$hhubj)}(hhh]h)}(hControl structure for ECCh]hControl structure for ECC}(hj+%hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM)hj(%hhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj$hMubeh}(h]h ](jstructeh"]h$]h&]jjjjC%jjC%jjjuh1j#hhhjhNhNubj)}(hXo **Definition**:: struct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page); }; **Members** ``engine_type`` ECC engine type ``placement`` OOB bytes placement ``algo`` ECC algorithm ``steps`` number of ECC steps per page ``size`` data bytes per ECC step ``bytes`` ECC bytes per step ``total`` total number of ECC bytes per page ``strength`` max number of correctible bits per ECC step ``prepad`` padding information for syndrome based ECC generators ``postpad`` padding information for syndrome based ECC generators ``options`` ECC specific options (see NAND_ECC_XXX flags defined above) ``calc_buf`` buffer for calculated ECC, size is oobsize. ``code_buf`` buffer for ECC read from flash, size is oobsize. ``hwctl`` function to control hardware ECC generator. Must only be provided if an hardware ECC is available ``calculate`` function for ECC calculation or readback from ECC hardware ``correct`` function for ECC correction, matching to ECC generator (sw/hw). Should return a positive number representing the number of corrected bitflips, -EBADMSG if the number of bitflips exceed ECC strength, or any other error code if the error is not directly related to correction. If -EBADMSG is returned the input buffers should be left untouched. ``read_page_raw`` function to read a raw page without ECC. This function should hide the specific layout used by the ECC controller and always return contiguous in-band and out-of-band data even if they're not stored contiguously on the NAND chip (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data). ``write_page_raw`` function to write a raw page without ECC. This function should hide the specific layout used by the ECC controller and consider the passed data as contiguous in-band and out-of-band data. ECC controller is responsible for doing the appropriate transformations to adapt to its specific layout (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data). ``read_page`` function to read a page according to the ECC generator requirements; returns maximum number of bitflips corrected in any single ECC step, -EIO hw error ``read_subpage`` function to read parts of the page covered by ECC; returns same as read_page() ``write_subpage`` function to write parts of the page covered by ECC. ``write_page`` function to write a page according to the ECC generator requirements. ``write_oob_raw`` function to write chip OOB data without ECC ``read_oob_raw`` function to read chip OOB data without ECC ``read_oob`` function to read chip OOB data ``write_oob`` function to write chip OOB datah](j)}(hX**Definition**:: struct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page); }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjS%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO%ubh:}(hjO%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM-hjK%ubjs)}(hXstruct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page); };h]hXstruct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page); };}hjl%sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM/hjK%ubeh}(h]h ]h"]h$]h&]uh1jhjk%hM-hjG%ubh)}(h **Members**h]j)}(hj%h]hMembers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMLhjG%ubj )}(hhh](j)}(h ``engine_type`` ECC engine type h](j)}(h``engine_type``h]j)}(hj%h]h engine_type}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM+hj%ubj1)}(hhh]h)}(hECC engine typeh]hECC engine type}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hM+hj%ubah}(h]h ]h"]h$]h&]uh1j0hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hM+hj%ubj)}(h"``placement`` OOB bytes placement h](j)}(h ``placement``h]j)}(hj%h]h placement}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM,hj%ubj1)}(hhh]h)}(hOOB bytes placementh]hOOB bytes placement}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hM,hj%ubah}(h]h ]h"]h$]h&]uh1j0hj%ubeh}(h]h ]h"]h$]h&]uh1jhj%hM,hj%ubj)}(h``algo`` ECC algorithm h](j)}(h``algo``h]j)}(hj&h]halgo}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM-hj&ubj1)}(hhh]h)}(h ECC algorithmh]h ECC algorithm}(hj-&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)&hM-hj*&ubah}(h]h ]h"]h$]h&]uh1j0hj&ubeh}(h]h ]h"]h$]h&]uh1jhj)&hM-hj%ubj)}(h'``steps`` number of ECC steps per page h](j)}(h ``steps``h]j)}(hjM&h]hsteps}(hjO&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK&ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM.hjG&ubj1)}(hhh]h)}(hnumber of ECC steps per pageh]hnumber of ECC steps per page}(hjf&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb&hM.hjc&ubah}(h]h ]h"]h$]h&]uh1j0hjG&ubeh}(h]h ]h"]h$]h&]uh1jhjb&hM.hj%ubj)}(h!``size`` data bytes per ECC step h](j)}(h``size``h]j)}(hj&h]hsize}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM/hj&ubj1)}(hhh]h)}(hdata bytes per ECC steph]hdata bytes per ECC step}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM/hj&ubah}(h]h ]h"]h$]h&]uh1j0hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hM/hj%ubj)}(h``bytes`` ECC bytes per step h](j)}(h ``bytes``h]j)}(hj&h]hbytes}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM0hj&ubj1)}(hhh]h)}(hECC bytes per steph]hECC bytes per step}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hM0hj&ubah}(h]h ]h"]h$]h&]uh1j0hj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hM0hj%ubj)}(h-``total`` total number of ECC bytes per page h](j)}(h ``total``h]j)}(hj&h]htotal}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM2hj&ubj1)}(hhh]h)}(h"total number of ECC bytes per pageh]h"total number of ECC bytes per page}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 'hM2hj'ubah}(h]h ]h"]h$]h&]uh1j0hj&ubeh}(h]h ]h"]h$]h&]uh1jhj 'hM2hj%ubj)}(h9``strength`` max number of correctible bits per ECC step h](j)}(h ``strength``h]j)}(hj1'h]hstrength}(hj3'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/'ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM1hj+'ubj1)}(hhh]h)}(h+max number of correctible bits per ECC steph]h+max number of correctible bits per ECC step}(hjJ'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF'hM1hjG'ubah}(h]h ]h"]h$]h&]uh1j0hj+'ubeh}(h]h ]h"]h$]h&]uh1jhjF'hM1hj%ubj)}(hA``prepad`` padding information for syndrome based ECC generators h](j)}(h ``prepad``h]j)}(hjj'h]hprepad}(hjl'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh'ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM3hjd'ubj1)}(hhh]h)}(h5padding information for syndrome based ECC generatorsh]h5padding information for syndrome based ECC generators}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM3hj'ubah}(h]h ]h"]h$]h&]uh1j0hjd'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM3hj%ubj)}(hB``postpad`` padding information for syndrome based ECC generators h](j)}(h ``postpad``h]j)}(hj'h]hpostpad}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM4hj'ubj1)}(hhh]h)}(h5padding information for syndrome based ECC generatorsh]h5padding information for syndrome based ECC generators}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM4hj'ubah}(h]h ]h"]h$]h&]uh1j0hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM4hj%ubj)}(hH``options`` ECC specific options (see NAND_ECC_XXX flags defined above) h](j)}(h ``options``h]j)}(hj'h]hoptions}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM5hj'ubj1)}(hhh]h)}(h;ECC specific options (see NAND_ECC_XXX flags defined above)h]h;ECC specific options (see NAND_ECC_XXX flags defined above)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hM5hj'ubah}(h]h ]h"]h$]h&]uh1j0hj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM5hj%ubj)}(h9``calc_buf`` buffer for calculated ECC, size is oobsize. h](j)}(h ``calc_buf``h]j)}(hj(h]hcalc_buf}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM6hj(ubj1)}(hhh]h)}(h+buffer for calculated ECC, size is oobsize.h]h+buffer for calculated ECC, size is oobsize.}(hj.(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*(hM6hj+(ubah}(h]h ]h"]h$]h&]uh1j0hj(ubeh}(h]h ]h"]h$]h&]uh1jhj*(hM6hj%ubj)}(h>``code_buf`` buffer for ECC read from flash, size is oobsize. h](j)}(h ``code_buf``h]j)}(hjN(h]hcode_buf}(hjP(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL(ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM7hjH(ubj1)}(hhh]h)}(h0buffer for ECC read from flash, size is oobsize.h]h0buffer for ECC read from flash, size is oobsize.}(hjg(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc(hM7hjd(ubah}(h]h ]h"]h$]h&]uh1j0hjH(ubeh}(h]h ]h"]h$]h&]uh1jhjc(hM7hj%ubj)}(hl``hwctl`` function to control hardware ECC generator. Must only be provided if an hardware ECC is available h](j)}(h ``hwctl``h]j)}(hj(h]hhwctl}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM9hj(ubj1)}(hhh]h)}(hafunction to control hardware ECC generator. Must only be provided if an hardware ECC is availableh]hafunction to control hardware ECC generator. Must only be provided if an hardware ECC is available}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM8hj(ubah}(h]h ]h"]h$]h&]uh1j0hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hM9hj%ubj)}(hI``calculate`` function for ECC calculation or readback from ECC hardware h](j)}(h ``calculate``h]j)}(hj(h]h calculate}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM:hj(ubj1)}(hhh]h)}(h:function for ECC calculation or readback from ECC hardwareh]h:function for ECC calculation or readback from ECC hardware}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hM:hj(ubah}(h]h ]h"]h$]h&]uh1j0hj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hM:hj%ubj)}(hXc``correct`` function for ECC correction, matching to ECC generator (sw/hw). Should return a positive number representing the number of corrected bitflips, -EBADMSG if the number of bitflips exceed ECC strength, or any other error code if the error is not directly related to correction. If -EBADMSG is returned the input buffers should be left untouched. h](j)}(h ``correct``h]j)}(hj(h]hcorrect}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMAhj(ubj1)}(hhh]h)}(hXVfunction for ECC correction, matching to ECC generator (sw/hw). Should return a positive number representing the number of corrected bitflips, -EBADMSG if the number of bitflips exceed ECC strength, or any other error code if the error is not directly related to correction. If -EBADMSG is returned the input buffers should be left untouched.h]hXVfunction for ECC correction, matching to ECC generator (sw/hw). Should return a positive number representing the number of corrected bitflips, -EBADMSG if the number of bitflips exceed ECC strength, or any other error code if the error is not directly related to correction. If -EBADMSG is returned the input buffers should be left untouched.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM;hj)ubah}(h]h ]h"]h$]h&]uh1j0hj(ubeh}(h]h ]h"]h$]h&]uh1jhj)hMAhj%ubj)}(hXG``read_page_raw`` function to read a raw page without ECC. This function should hide the specific layout used by the ECC controller and always return contiguous in-band and out-of-band data even if they're not stored contiguously on the NAND chip (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data). h](j)}(h``read_page_raw``h]j)}(hj4)h]h read_page_raw}(hj6)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2)ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMHhj.)ubj1)}(hhh]h)}(hX4function to read a raw page without ECC. This function should hide the specific layout used by the ECC controller and always return contiguous in-band and out-of-band data even if they're not stored contiguously on the NAND chip (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data).h]hX6function to read a raw page without ECC. This function should hide the specific layout used by the ECC controller and always return contiguous in-band and out-of-band data even if they’re not stored contiguously on the NAND chip (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data).}(hjM)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMBhjJ)ubah}(h]h ]h"]h$]h&]uh1j0hj.)ubeh}(h]h ]h"]h$]h&]uh1jhjI)hMHhj%ubj)}(hX``write_page_raw`` function to write a raw page without ECC. This function should hide the specific layout used by the ECC controller and consider the passed data as contiguous in-band and out-of-band data. ECC controller is responsible for doing the appropriate transformations to adapt to its specific layout (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data). h](j)}(h``write_page_raw``h]j)}(hjn)h]hwrite_page_raw}(hjp)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl)ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMPhjh)ubj1)}(hhh]h)}(hXsfunction to write a raw page without ECC. This function should hide the specific layout used by the ECC controller and consider the passed data as contiguous in-band and out-of-band data. ECC controller is responsible for doing the appropriate transformations to adapt to its specific layout (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data).h]hXsfunction to write a raw page without ECC. This function should hide the specific layout used by the ECC controller and consider the passed data as contiguous in-band and out-of-band data. ECC controller is responsible for doing the appropriate transformations to adapt to its specific layout (e.g. NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and out-of-band data).}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMIhj)ubah}(h]h ]h"]h$]h&]uh1j0hjh)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMPhj%ubj)}(h``read_page`` function to read a page according to the ECC generator requirements; returns maximum number of bitflips corrected in any single ECC step, -EIO hw error h](j)}(h ``read_page``h]j)}(hj)h]h read_page}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMShj)ubj1)}(hhh]h)}(hfunction to read a page according to the ECC generator requirements; returns maximum number of bitflips corrected in any single ECC step, -EIO hw errorh]hfunction to read a page according to the ECC generator requirements; returns maximum number of bitflips corrected in any single ECC step, -EIO hw error}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMQhj)ubah}(h]h ]h"]h$]h&]uh1j0hj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMShj%ubj)}(h```read_subpage`` function to read parts of the page covered by ECC; returns same as read_page() h](j)}(h``read_subpage``h]j)}(hj)h]h read_subpage}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMUhj)ubj1)}(hhh]h)}(hNfunction to read parts of the page covered by ECC; returns same as read_page()h]hNfunction to read parts of the page covered by ECC; returns same as read_page()}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMThj)ubah}(h]h ]h"]h$]h&]uh1j0hj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMUhj%ubj)}(hF``write_subpage`` function to write parts of the page covered by ECC. h](j)}(h``write_subpage``h]j)}(hj*h]h write_subpage}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMVhj*ubj1)}(hhh]h)}(h3function to write parts of the page covered by ECC.h]h3function to write parts of the page covered by ECC.}(hj5*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1*hMVhj2*ubah}(h]h ]h"]h$]h&]uh1j0hj*ubeh}(h]h ]h"]h$]h&]uh1jhj1*hMVhj%ubj)}(hU``write_page`` function to write a page according to the ECC generator requirements. h](j)}(h``write_page``h]j)}(hjU*h]h write_page}(hjW*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS*ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMXhjO*ubj1)}(hhh]h)}(hEfunction to write a page according to the ECC generator requirements.h]hEfunction to write a page according to the ECC generator requirements.}(hjn*hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMWhjk*ubah}(h]h ]h"]h$]h&]uh1j0hjO*ubeh}(h]h ]h"]h$]h&]uh1jhjj*hMXhj%ubj)}(h>``write_oob_raw`` function to write chip OOB data without ECC h](j)}(h``write_oob_raw``h]j)}(hj*h]h write_oob_raw}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMYhj*ubj1)}(hhh]h)}(h+function to write chip OOB data without ECCh]h+function to write chip OOB data without ECC}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMYhj*ubah}(h]h ]h"]h$]h&]uh1j0hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMYhj%ubj)}(h<``read_oob_raw`` function to read chip OOB data without ECC h](j)}(h``read_oob_raw``h]j)}(hj*h]h read_oob_raw}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMZhj*ubj1)}(hhh]h)}(h*function to read chip OOB data without ECCh]h*function to read chip OOB data without ECC}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMZhj*ubah}(h]h ]h"]h$]h&]uh1j0hj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMZhj%ubj)}(h,``read_oob`` function to read chip OOB data h](j)}(h ``read_oob``h]j)}(hj+h]hread_oob}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hj*ubj1)}(hhh]h)}(hfunction to read chip OOB datah]hfunction to read chip OOB data}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hM[hj+ubah}(h]h ]h"]h$]h&]uh1j0hj*ubeh}(h]h ]h"]h$]h&]uh1jhj+hM[hj%ubj)}(h-``write_oob`` function to write chip OOB datah](j)}(h ``write_oob``h]j)}(hj:+h]h write_oob}(hj<+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8+ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hj4+ubj1)}(hhh]h)}(hfunction to write chip OOB datah]hfunction to write chip OOB data}(hjS+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM\hjP+ubah}(h]h ]h"]h$]h&]uh1j0hj4+ubeh}(h]h ]h"]h$]h&]uh1jhjO+hM[hj%ubeh}(h]h ]h"]h$]h&]uh1j hjG%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_sdr_timings (C struct)c.nand_sdr_timingshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_sdr_timingsh]j/)}(hstruct nand_sdr_timingsh](j5)}(hj8h]hstruct}(hj+hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj+hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMbubjG)}(h h]h }(hj+hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj+hhhj+hMbubjX)}(hnand_sdr_timingsh]j^)}(hj+h]hnand_sdr_timings}(hj+hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj+ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj+hhhj+hMbubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj+hhhj+hMbubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1j(hj+hMbhj+hhubj)}(hhh]h)}(hSDR NAND chip timingsh]hSDR NAND chip timings}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+hhubah}(h]h ]h"]h$]h&]uh1jhj+hhhj+hMbubeh}(h]h ](jstructeh"]h$]h&]jjjj+jj+jjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; }; **Members** ``tBERS_max`` Block erase time ``tCCS_min`` Change column setup time ``tPROG_max`` Page program time ``tR_max`` Page read time ``tALH_min`` ALE hold time ``tADL_min`` ALE to data loading time ``tALS_min`` ALE setup time ``tAR_min`` ALE to RE# delay ``tCEA_max`` CE# access time ``tCEH_min`` CE# high hold time ``tCH_min`` CE# hold time ``tCHZ_max`` CE# high to output hi-Z ``tCLH_min`` CLE hold time ``tCLR_min`` CLE to RE# delay ``tCLS_min`` CLE setup time ``tCOH_min`` CE# high to output hold ``tCS_min`` CE# setup time ``tDH_min`` Data hold time ``tDS_min`` Data setup time ``tFEAT_max`` Busy time for Set Features and Get Features ``tIR_min`` Output hi-Z to RE# low ``tITC_max`` Interface and Timing Mode Change time ``tRC_min`` RE# cycle time ``tREA_max`` RE# access time ``tREH_min`` RE# high hold time ``tRHOH_min`` RE# high to output hold ``tRHW_min`` RE# high to WE# low ``tRHZ_max`` RE# high to output hi-Z ``tRLOH_min`` RE# low to output hold ``tRP_min`` RE# pulse width ``tRR_min`` Ready to RE# low (data only) ``tRST_max`` Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#. ``tWB_max`` WE# high to SR[6] low ``tWC_min`` WE# cycle time ``tWH_min`` WE# high hold time ``tWHR_min`` WE# high to RE# low ``tWP_min`` WE# pulse width ``tWW_min`` WP# transition to WE# low **Description** This struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing Parameters) All these timings are expressed in picoseconds.h](j)}(hXl**Definition**:: struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh:}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubjs)}(hX struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; };h]hX struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; };}hj,sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhj+ubh)}(h **Members**h]j)}(hj.,h]hMembers}(hj0,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,,ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubj )}(hhh](j)}(h``tBERS_max`` Block erase time h](j)}(h ``tBERS_max``h]j)}(hjM,h]h tBERS_max}(hjO,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK,ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjG,ubj1)}(hhh]h)}(hBlock erase timeh]hBlock erase time}(hjf,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb,hMhjc,ubah}(h]h ]h"]h$]h&]uh1j0hjG,ubeh}(h]h ]h"]h$]h&]uh1jhjb,hMhjD,ubj)}(h&``tCCS_min`` Change column setup time h](j)}(h ``tCCS_min``h]j)}(hj,h]htCCS_min}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj,ubj1)}(hhh]h)}(hChange column setup timeh]hChange column setup time}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj,ubah}(h]h ]h"]h$]h&]uh1j0hj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjD,ubj)}(h ``tPROG_max`` Page program time h](j)}(h ``tPROG_max``h]j)}(hj,h]h tPROG_max}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj,ubj1)}(hhh]h)}(hPage program timeh]hPage program time}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hMhj,ubah}(h]h ]h"]h$]h&]uh1j0hj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjD,ubj)}(h``tR_max`` Page read time h](j)}(h ``tR_max``h]j)}(hj,h]htR_max}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj,ubj1)}(hhh]h)}(hPage read timeh]hPage read time}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj -hMhj-ubah}(h]h ]h"]h$]h&]uh1j0hj,ubeh}(h]h ]h"]h$]h&]uh1jhj -hMhjD,ubj)}(h``tALH_min`` ALE hold time h](j)}(h ``tALH_min``h]j)}(hj1-h]htALH_min}(hj3-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/-ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+-ubj1)}(hhh]h)}(h ALE hold timeh]h ALE hold time}(hjJ-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF-hMhjG-ubah}(h]h ]h"]h$]h&]uh1j0hj+-ubeh}(h]h ]h"]h$]h&]uh1jhjF-hMhjD,ubj)}(h&``tADL_min`` ALE to data loading time h](j)}(h ``tADL_min``h]j)}(hjj-h]htADL_min}(hjl-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh-ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjd-ubj1)}(hhh]h)}(hALE to data loading timeh]hALE to data loading time}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj-ubah}(h]h ]h"]h$]h&]uh1j0hjd-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjD,ubj)}(h``tALS_min`` ALE setup time h](j)}(h ``tALS_min``h]j)}(hj-h]htALS_min}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj-ubj1)}(hhh]h)}(hALE setup timeh]hALE setup time}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj-ubah}(h]h ]h"]h$]h&]uh1j0hj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjD,ubj)}(h``tAR_min`` ALE to RE# delay h](j)}(h ``tAR_min``h]j)}(hj-h]htAR_min}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj-ubj1)}(hhh]h)}(hALE to RE# delayh]hALE to RE# delay}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hMhj-ubah}(h]h ]h"]h$]h&]uh1j0hj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hMhjD,ubj)}(h``tCEA_max`` CE# access time h](j)}(h ``tCEA_max``h]j)}(hj.h]htCEA_max}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj.ubj1)}(hhh]h)}(hCE# access timeh]hCE# access time}(hj..hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*.hMhj+.ubah}(h]h ]h"]h$]h&]uh1j0hj.ubeh}(h]h ]h"]h$]h&]uh1jhj*.hMhjD,ubj)}(h ``tCEH_min`` CE# high hold time h](j)}(h ``tCEH_min``h]j)}(hjN.h]htCEH_min}(hjP.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL.ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjH.ubj1)}(hhh]h)}(hCE# high hold timeh]hCE# high hold time}(hjg.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc.hMhjd.ubah}(h]h ]h"]h$]h&]uh1j0hjH.ubeh}(h]h ]h"]h$]h&]uh1jhjc.hMhjD,ubj)}(h``tCH_min`` CE# hold time h](j)}(h ``tCH_min``h]j)}(hj.h]htCH_min}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj.ubj1)}(hhh]h)}(h CE# hold timeh]h CE# hold time}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1j0hj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMhjD,ubj)}(h%``tCHZ_max`` CE# high to output hi-Z h](j)}(h ``tCHZ_max``h]j)}(hj.h]htCHZ_max}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj.ubj1)}(hhh]h)}(hCE# high to output hi-Zh]hCE# high to output hi-Z}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hMhj.ubah}(h]h ]h"]h$]h&]uh1j0hj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMhjD,ubj)}(h``tCLH_min`` CLE hold time h](j)}(h ``tCLH_min``h]j)}(hj.h]htCLH_min}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj.ubj1)}(hhh]h)}(h CLE hold timeh]h CLE hold time}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1j0hj.ubeh}(h]h ]h"]h$]h&]uh1jhj/hMhjD,ubj)}(h``tCLR_min`` CLE to RE# delay h](j)}(h ``tCLR_min``h]j)}(hj2/h]htCLR_min}(hj4/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0/ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj,/ubj1)}(hhh]h)}(hCLE to RE# delayh]hCLE to RE# delay}(hjK/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjG/hMhjH/ubah}(h]h ]h"]h$]h&]uh1j0hj,/ubeh}(h]h ]h"]h$]h&]uh1jhjG/hMhjD,ubj)}(h``tCLS_min`` CLE setup time h](j)}(h ``tCLS_min``h]j)}(hjk/h]htCLS_min}(hjm/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji/ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhje/ubj1)}(hhh]h)}(hCLE setup timeh]hCLE setup time}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1j0hje/ubeh}(h]h ]h"]h$]h&]uh1jhj/hMhjD,ubj)}(h%``tCOH_min`` CE# high to output hold h](j)}(h ``tCOH_min``h]j)}(hj/h]htCOH_min}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj/ubj1)}(hhh]h)}(hCE# high to output holdh]hCE# high to output hold}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1j0hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hMhjD,ubj)}(h``tCS_min`` CE# setup time h](j)}(h ``tCS_min``h]j)}(hj/h]htCS_min}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj/ubj1)}(hhh]h)}(hCE# setup timeh]hCE# setup time}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hMhj/ubah}(h]h ]h"]h$]h&]uh1j0hj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hMhjD,ubj)}(h``tDH_min`` Data hold time h](j)}(h ``tDH_min``h]j)}(hj0h]htDH_min}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj0ubj1)}(hhh]h)}(hData hold timeh]hData hold time}(hj/0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+0hMhj,0ubah}(h]h ]h"]h$]h&]uh1j0hj0ubeh}(h]h ]h"]h$]h&]uh1jhj+0hMhjD,ubj)}(h``tDS_min`` Data setup time h](j)}(h ``tDS_min``h]j)}(hjO0h]htDS_min}(hjQ0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM0ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjI0ubj1)}(hhh]h)}(hData setup timeh]hData setup time}(hjh0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd0hMhje0ubah}(h]h ]h"]h$]h&]uh1j0hjI0ubeh}(h]h ]h"]h$]h&]uh1jhjd0hMhjD,ubj)}(h:``tFEAT_max`` Busy time for Set Features and Get Features h](j)}(h ``tFEAT_max``h]j)}(hj0h]h tFEAT_max}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj0ubj1)}(hhh]h)}(h+Busy time for Set Features and Get Featuresh]h+Busy time for Set Features and Get Features}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1j0hj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhjD,ubj)}(h#``tIR_min`` Output hi-Z to RE# low h](j)}(h ``tIR_min``h]j)}(hj0h]htIR_min}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj0ubj1)}(hhh]h)}(hOutput hi-Z to RE# lowh]hOutput hi-Z to RE# low}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hMhj0ubah}(h]h ]h"]h$]h&]uh1j0hj0ubeh}(h]h ]h"]h$]h&]uh1jhj0hMhjD,ubj)}(h3``tITC_max`` Interface and Timing Mode Change time h](j)}(h ``tITC_max``h]j)}(hj0h]htITC_max}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj0ubj1)}(hhh]h)}(h%Interface and Timing Mode Change timeh]h%Interface and Timing Mode Change time}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j0hj0ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjD,ubj)}(h``tRC_min`` RE# cycle time h](j)}(h ``tRC_min``h]j)}(hj31h]htRC_min}(hj51hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj11ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj-1ubj1)}(hhh]h)}(hRE# cycle timeh]hRE# cycle time}(hjL1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH1hMhjI1ubah}(h]h ]h"]h$]h&]uh1j0hj-1ubeh}(h]h ]h"]h$]h&]uh1jhjH1hMhjD,ubj)}(h``tREA_max`` RE# access time h](j)}(h ``tREA_max``h]j)}(hjl1h]htREA_max}(hjn1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj1ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjf1ubj1)}(hhh]h)}(hRE# access timeh]hRE# access time}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j0hjf1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjD,ubj)}(h ``tREH_min`` RE# high hold time h](j)}(h ``tREH_min``h]j)}(hj1h]htREH_min}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj1ubj1)}(hhh]h)}(hRE# high hold timeh]hRE# high hold time}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j0hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjD,ubj)}(h&``tRHOH_min`` RE# high to output hold h](j)}(h ``tRHOH_min``h]j)}(hj1h]h tRHOH_min}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj1ubj1)}(hhh]h)}(hRE# high to output holdh]hRE# high to output hold}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hMhj1ubah}(h]h ]h"]h$]h&]uh1j0hj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjD,ubj)}(h!``tRHW_min`` RE# high to WE# low h](j)}(h ``tRHW_min``h]j)}(hj2h]htRHW_min}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2ubj1)}(hhh]h)}(hRE# high to WE# lowh]hRE# high to WE# low}(hj02hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,2hMhj-2ubah}(h]h ]h"]h$]h&]uh1j0hj2ubeh}(h]h ]h"]h$]h&]uh1jhj,2hMhjD,ubj)}(h%``tRHZ_max`` RE# high to output hi-Z h](j)}(h ``tRHZ_max``h]j)}(hjP2h]htRHZ_max}(hjR2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN2ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjJ2ubj1)}(hhh]h)}(hRE# high to output hi-Zh]hRE# high to output hi-Z}(hji2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje2hMhjf2ubah}(h]h ]h"]h$]h&]uh1j0hjJ2ubeh}(h]h ]h"]h$]h&]uh1jhje2hMhjD,ubj)}(h%``tRLOH_min`` RE# low to output hold h](j)}(h ``tRLOH_min``h]j)}(hj2h]h tRLOH_min}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2ubj1)}(hhh]h)}(hRE# low to output holdh]hRE# low to output hold}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj2ubah}(h]h ]h"]h$]h&]uh1j0hj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMhjD,ubj)}(h``tRP_min`` RE# pulse width h](j)}(h ``tRP_min``h]j)}(hj2h]htRP_min}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2ubj1)}(hhh]h)}(hRE# pulse widthh]hRE# pulse width}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hMhj2ubah}(h]h ]h"]h$]h&]uh1j0hj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMhjD,ubj)}(h)``tRR_min`` Ready to RE# low (data only) h](j)}(h ``tRR_min``h]j)}(hj2h]htRR_min}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2ubj1)}(hhh]h)}(hReady to RE# low (data only)h]hReady to RE# low (data only)}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1j0hj2ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhjD,ubj)}(hc``tRST_max`` Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#. h](j)}(h ``tRST_max``h]j)}(hj43h]htRST_max}(hj63hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj23ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj.3ubj1)}(hhh]h)}(hUDevice reset time, measured from the falling edge of R/B# to the rising edge of R/B#.h]hUDevice reset time, measured from the falling edge of R/B# to the rising edge of R/B#.}(hjM3hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjJ3ubah}(h]h ]h"]h$]h&]uh1j0hj.3ubeh}(h]h ]h"]h$]h&]uh1jhjI3hMhjD,ubj)}(h"``tWB_max`` WE# high to SR[6] low h](j)}(h ``tWB_max``h]j)}(hjn3h]htWB_max}(hjp3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl3ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjh3ubj1)}(hhh]h)}(hWE# high to SR[6] lowh]hWE# high to SR[6] low}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1j0hjh3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhjD,ubj)}(h``tWC_min`` WE# cycle time h](j)}(h ``tWC_min``h]j)}(hj3h]htWC_min}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj3ubj1)}(hhh]h)}(hWE# cycle timeh]hWE# cycle time}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1j0hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhjD,ubj)}(h``tWH_min`` WE# high hold time h](j)}(h ``tWH_min``h]j)}(hj3h]htWH_min}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj3ubj1)}(hhh]h)}(hWE# high hold timeh]hWE# high hold time}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hMhj3ubah}(h]h ]h"]h$]h&]uh1j0hj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhjD,ubj)}(h!``tWHR_min`` WE# high to RE# low h](j)}(h ``tWHR_min``h]j)}(hj4h]htWHR_min}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj4ubj1)}(hhh]h)}(hWE# high to RE# lowh]hWE# high to RE# low}(hj24hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.4hMhj/4ubah}(h]h ]h"]h$]h&]uh1j0hj4ubeh}(h]h ]h"]h$]h&]uh1jhj.4hMhjD,ubj)}(h``tWP_min`` WE# pulse width h](j)}(h ``tWP_min``h]j)}(hjR4h]htWP_min}(hjT4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjP4ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjL4ubj1)}(hhh]h)}(hWE# pulse widthh]hWE# pulse width}(hjk4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg4hMhjh4ubah}(h]h ]h"]h$]h&]uh1j0hjL4ubeh}(h]h ]h"]h$]h&]uh1jhjg4hMhjD,ubj)}(h'``tWW_min`` WP# transition to WE# low h](j)}(h ``tWW_min``h]j)}(hj4h]htWW_min}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj4ubj1)}(hhh]h)}(hWP# transition to WE# lowh]hWP# transition to WE# low}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj4ubah}(h]h ]h"]h$]h&]uh1j0hj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhjD,ubeh}(h]h ]h"]h$]h&]uh1j hj+ubh)}(h**Description**h]j)}(hj4h]h Description}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubh)}(hX#This struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing Parameters)h](hThis struct defines the timing requirements of a SDR NAND chip. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: }(hj4hhhNhNubh reference)}(hHhttps://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdfh]hHhttps://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf}(hj4hhhNhNubah}(h]h ]h"]h$]h&]refurij4uh1j4hj4ubh! (chapter 4.15 Timing Parameters)}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubh)}(h/All these timings are expressed in picoseconds.h]h/All these timings are expressed in picoseconds.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_nvddr_timings (C struct)c.nand_nvddr_timingshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_nvddr_timingsh]j/)}(hstruct nand_nvddr_timingsh](j5)}(hj8h]hstruct}(hj05hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj,5hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj>5hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj,5hhhj=5hMubjX)}(hnand_nvddr_timingsh]j^)}(hj*5h]hnand_nvddr_timings}(hjP5hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjL5ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj,5hhhj=5hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj(5hhhj=5hMubah}(h]j#5ah ](jjeh"]h$]h&]jj)jhuh1j(hj=5hMhj%5hhubj)}(hhh]h)}(hNV-DDR NAND chip timingsh]hNV-DDR NAND chip timings}(hjr5hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjo5hhubah}(h]h ]h"]h$]h&]uh1jhj%5hhhj=5hMubeh}(h]h ](jstructeh"]h$]h&]jjjj5jj5jjjuh1j#hhhjhNhNubj)}(hX[ **Definition**:: struct nand_nvddr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tAC_min; u32 tAC_max; u32 tADL_min; u32 tCAD_min; u32 tCAH_min; u32 tCALH_min; u32 tCALS_min; u32 tCAS_min; u32 tCEH_min; u32 tCH_min; u32 tCK_min; u32 tCS_min; u32 tDH_min; u32 tDQSCK_min; u32 tDQSCK_max; u32 tDQSD_min; u32 tDQSD_max; u32 tDQSHZ_max; u32 tDQSQ_max; u32 tDS_min; u32 tDSC_min; u32 tFEAT_max; u32 tITC_max; u32 tQHS_max; u32 tRHW_min; u32 tRR_min; u32 tRST_max; u32 tWB_max; u32 tWHR_min; u32 tWRCK_min; u32 tWW_min; }; **Members** ``tBERS_max`` Block erase time ``tCCS_min`` Change column setup time ``tPROG_max`` Page program time ``tR_max`` Page read time ``tAC_min`` Access window of DQ[7:0] from CLK ``tAC_max`` Access window of DQ[7:0] from CLK ``tADL_min`` ALE to data loading time ``tCAD_min`` Command, Address, Data delay ``tCAH_min`` Command/Address DQ hold time ``tCALH_min`` W/R_n, CLE and ALE hold time ``tCALS_min`` W/R_n, CLE and ALE setup time ``tCAS_min`` Command/address DQ setup time ``tCEH_min`` CE# high hold time ``tCH_min`` CE# hold time ``tCK_min`` Average clock cycle time ``tCS_min`` CE# setup time ``tDH_min`` Data hold time ``tDQSCK_min`` Start of the access window of DQS from CLK ``tDQSCK_max`` End of the access window of DQS from CLK ``tDQSD_min`` Min W/R_n low to DQS/DQ driven by device ``tDQSD_max`` Max W/R_n low to DQS/DQ driven by device ``tDQSHZ_max`` W/R_n high to DQS/DQ tri-state by device ``tDQSQ_max`` DQS-DQ skew, DQS to last DQ valid, per access ``tDS_min`` Data setup time ``tDSC_min`` DQS cycle time ``tFEAT_max`` Busy time for Set Features and Get Features ``tITC_max`` Interface and Timing Mode Change time ``tQHS_max`` Data hold skew factor ``tRHW_min`` Data output cycle to command, address, or data input cycle ``tRR_min`` Ready to RE# low (data only) ``tRST_max`` Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#. ``tWB_max`` WE# high to SR[6] low ``tWHR_min`` WE# high to RE# low ``tWRCK_min`` W/R_n low to data output cycle ``tWW_min`` WP# transition to WE# low **Description** This struct defines the timing requirements of a NV-DDR NAND data interface. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf (chapter 4.18.2 NV-DDR) All these timings are expressed in picoseconds.h](j)}(hX:**Definition**:: struct nand_nvddr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tAC_min; u32 tAC_max; u32 tADL_min; u32 tCAD_min; u32 tCAH_min; u32 tCALH_min; u32 tCALS_min; u32 tCAS_min; u32 tCEH_min; u32 tCH_min; u32 tCK_min; u32 tCS_min; u32 tDH_min; u32 tDQSCK_min; u32 tDQSCK_max; u32 tDQSD_min; u32 tDQSD_max; u32 tDQSHZ_max; u32 tDQSQ_max; u32 tDS_min; u32 tDSC_min; u32 tFEAT_max; u32 tITC_max; u32 tQHS_max; u32 tRHW_min; u32 tRR_min; u32 tRST_max; u32 tWB_max; u32 tWHR_min; u32 tWRCK_min; u32 tWW_min; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh:}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubjs)}(hXstruct nand_nvddr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tAC_min; u32 tAC_max; u32 tADL_min; u32 tCAD_min; u32 tCAH_min; u32 tCALH_min; u32 tCALS_min; u32 tCAS_min; u32 tCEH_min; u32 tCH_min; u32 tCK_min; u32 tCS_min; u32 tDH_min; u32 tDQSCK_min; u32 tDQSCK_max; u32 tDQSD_min; u32 tDQSD_max; u32 tDQSHZ_max; u32 tDQSQ_max; u32 tDS_min; u32 tDSC_min; u32 tFEAT_max; u32 tITC_max; u32 tQHS_max; u32 tRHW_min; u32 tRR_min; u32 tRST_max; u32 tWB_max; u32 tWHR_min; u32 tWRCK_min; u32 tWW_min; };h]hXstruct nand_nvddr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tAC_min; u32 tAC_max; u32 tADL_min; u32 tCAD_min; u32 tCAH_min; u32 tCALH_min; u32 tCALS_min; u32 tCAS_min; u32 tCEH_min; u32 tCH_min; u32 tCK_min; u32 tCS_min; u32 tDH_min; u32 tDQSCK_min; u32 tDQSCK_max; u32 tDQSD_min; u32 tDQSD_max; u32 tDQSHZ_max; u32 tDQSQ_max; u32 tDS_min; u32 tDSC_min; u32 tFEAT_max; u32 tITC_max; u32 tQHS_max; u32 tRHW_min; u32 tRR_min; u32 tRST_max; u32 tWB_max; u32 tWHR_min; u32 tWRCK_min; u32 tWW_min; };}hj5sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMhj5ubh)}(h **Members**h]j)}(hj5h]hMembers}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj5ubj )}(hhh](j)}(h``tBERS_max`` Block erase time h](j)}(h ``tBERS_max``h]j)}(hj5h]h tBERS_max}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubj1)}(hhh]h)}(hBlock erase timeh]hBlock erase time}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1j0hj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMhj5ubj)}(h&``tCCS_min`` Change column setup time h](j)}(h ``tCCS_min``h]j)}(hj"6h]htCCS_min}(hj$6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 6ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6ubj1)}(hhh]h)}(hChange column setup timeh]hChange column setup time}(hj;6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj76hMhj86ubah}(h]h ]h"]h$]h&]uh1j0hj6ubeh}(h]h ]h"]h$]h&]uh1jhj76hMhj5ubj)}(h ``tPROG_max`` Page program time h](j)}(h ``tPROG_max``h]j)}(hj[6h]h tPROG_max}(hj]6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY6ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjU6ubj1)}(hhh]h)}(hPage program timeh]hPage program time}(hjt6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp6hMhjq6ubah}(h]h ]h"]h$]h&]uh1j0hjU6ubeh}(h]h ]h"]h$]h&]uh1jhjp6hMhj5ubj)}(h``tR_max`` Page read time h](j)}(h ``tR_max``h]j)}(hj6h]htR_max}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6ubj1)}(hhh]h)}(hPage read timeh]hPage read time}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j0hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj5ubj)}(h.``tAC_min`` Access window of DQ[7:0] from CLK h](j)}(h ``tAC_min``h]j)}(hj6h]htAC_min}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6ubj1)}(hhh]h)}(h!Access window of DQ[7:0] from CLKh]h!Access window of DQ[7:0] from CLK}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1j0hj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj5ubj)}(h.``tAC_max`` Access window of DQ[7:0] from CLK h](j)}(h ``tAC_max``h]j)}(hj7h]htAC_max}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj7ubj1)}(hhh]h)}(h!Access window of DQ[7:0] from CLKh]h!Access window of DQ[7:0] from CLK}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1j0hj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj5ubj)}(h&``tADL_min`` ALE to data loading time h](j)}(h ``tADL_min``h]j)}(hj?7h]htADL_min}(hjA7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=7ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj97ubj1)}(hhh]h)}(hALE to data loading timeh]hALE to data loading time}(hjX7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT7hMhjU7ubah}(h]h ]h"]h$]h&]uh1j0hj97ubeh}(h]h ]h"]h$]h&]uh1jhjT7hMhj5ubj)}(h*``tCAD_min`` Command, Address, Data delay h](j)}(h ``tCAD_min``h]j)}(hjx7h]htCAD_min}(hjz7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv7ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjr7ubj1)}(hhh]h)}(hCommand, Address, Data delayh]hCommand, Address, Data delay}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1j0hjr7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj5ubj)}(h*``tCAH_min`` Command/Address DQ hold time h](j)}(h ``tCAH_min``h]j)}(hj7h]htCAH_min}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj7ubj1)}(hhh]h)}(hCommand/Address DQ hold timeh]hCommand/Address DQ hold time}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1j0hj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj5ubj)}(h+``tCALH_min`` W/R_n, CLE and ALE hold time h](j)}(h ``tCALH_min``h]j)}(hj7h]h tCALH_min}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj7ubj1)}(hhh]h)}(hW/R_n, CLE and ALE hold timeh]hW/R_n, CLE and ALE hold time}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1j0hj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj5ubj)}(h,``tCALS_min`` W/R_n, CLE and ALE setup time h](j)}(h ``tCALS_min``h]j)}(hj#8h]h tCALS_min}(hj%8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!8ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj8ubj1)}(hhh]h)}(hW/R_n, CLE and ALE setup timeh]hW/R_n, CLE and ALE setup time}(hj<8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj88hMhj98ubah}(h]h ]h"]h$]h&]uh1j0hj8ubeh}(h]h ]h"]h$]h&]uh1jhj88hMhj5ubj)}(h+``tCAS_min`` Command/address DQ setup time h](j)}(h ``tCAS_min``h]j)}(hj\8h]htCAS_min}(hj^8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ8ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjV8ubj1)}(hhh]h)}(hCommand/address DQ setup timeh]hCommand/address DQ setup time}(hju8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq8hMhjr8ubah}(h]h ]h"]h$]h&]uh1j0hjV8ubeh}(h]h ]h"]h$]h&]uh1jhjq8hMhj5ubj)}(h ``tCEH_min`` CE# high hold time h](j)}(h ``tCEH_min``h]j)}(hj8h]htCEH_min}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj8ubj1)}(hhh]h)}(hCE# high hold timeh]hCE# high hold time}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1j0hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj5ubj)}(h``tCH_min`` CE# hold time h](j)}(h ``tCH_min``h]j)}(hj8h]htCH_min}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj8ubj1)}(hhh]h)}(h CE# hold timeh]h CE# hold time}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1j0hj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj5ubj)}(h%``tCK_min`` Average clock cycle time h](j)}(h ``tCK_min``h]j)}(hj9h]htCK_min}(hj 9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj9ubj1)}(hhh]h)}(hAverage clock cycle timeh]hAverage clock cycle time}(hj 9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1j0hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj5ubj)}(h``tCS_min`` CE# setup time h](j)}(h ``tCS_min``h]j)}(hj@9h]htCS_min}(hjB9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>9ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:9ubj1)}(hhh]h)}(hCE# setup timeh]hCE# setup time}(hjY9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjU9hMhjV9ubah}(h]h ]h"]h$]h&]uh1j0hj:9ubeh}(h]h ]h"]h$]h&]uh1jhjU9hMhj5ubj)}(h``tDH_min`` Data hold time h](j)}(h ``tDH_min``h]j)}(hjy9h]htDH_min}(hj{9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw9ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjs9ubj1)}(hhh]h)}(hData hold timeh]hData hold time}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1j0hjs9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj5ubj)}(h:``tDQSCK_min`` Start of the access window of DQS from CLK h](j)}(h``tDQSCK_min``h]j)}(hj9h]h tDQSCK_min}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj9ubj1)}(hhh]h)}(h*Start of the access window of DQS from CLKh]h*Start of the access window of DQS from CLK}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1j0hj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj5ubj)}(h8``tDQSCK_max`` End of the access window of DQS from CLK h](j)}(h``tDQSCK_max``h]j)}(hj9h]h tDQSCK_max}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj9ubj1)}(hhh]h)}(h(End of the access window of DQS from CLKh]h(End of the access window of DQS from CLK}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1j0hj9ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj5ubj)}(h7``tDQSD_min`` Min W/R_n low to DQS/DQ driven by device h](j)}(h ``tDQSD_min``h]j)}(hj$:h]h tDQSD_min}(hj&:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj":ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:ubj1)}(hhh]h)}(h(Min W/R_n low to DQS/DQ driven by deviceh]h(Min W/R_n low to DQS/DQ driven by device}(hj=:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9:hMhj::ubah}(h]h ]h"]h$]h&]uh1j0hj:ubeh}(h]h ]h"]h$]h&]uh1jhj9:hMhj5ubj)}(h7``tDQSD_max`` Max W/R_n low to DQS/DQ driven by device h](j)}(h ``tDQSD_max``h]j)}(hj]:h]h tDQSD_max}(hj_:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[:ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjW:ubj1)}(hhh]h)}(h(Max W/R_n low to DQS/DQ driven by deviceh]h(Max W/R_n low to DQS/DQ driven by device}(hjv:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjr:hMhjs:ubah}(h]h ]h"]h$]h&]uh1j0hjW:ubeh}(h]h ]h"]h$]h&]uh1jhjr:hMhj5ubj)}(h8``tDQSHZ_max`` W/R_n high to DQS/DQ tri-state by device h](j)}(h``tDQSHZ_max``h]j)}(hj:h]h tDQSHZ_max}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:ubj1)}(hhh]h)}(h(W/R_n high to DQS/DQ tri-state by deviceh]h(W/R_n high to DQS/DQ tri-state by device}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1j0hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj5ubj)}(h<``tDQSQ_max`` DQS-DQ skew, DQS to last DQ valid, per access h](j)}(h ``tDQSQ_max``h]j)}(hj:h]h tDQSQ_max}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:ubj1)}(hhh]h)}(h-DQS-DQ skew, DQS to last DQ valid, per accessh]h-DQS-DQ skew, DQS to last DQ valid, per access}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1j0hj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj5ubj)}(h``tDS_min`` Data setup time h](j)}(h ``tDS_min``h]j)}(hj;h]htDS_min}(hj ;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj;ubj1)}(hhh]h)}(hData setup timeh]hData setup time}(hj!;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1j0hj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj5ubj)}(h``tDSC_min`` DQS cycle time h](j)}(h ``tDSC_min``h]j)}(hjA;h]htDSC_min}(hjC;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?;ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj;;ubj1)}(hhh]h)}(hDQS cycle timeh]hDQS cycle time}(hjZ;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV;hMhjW;ubah}(h]h ]h"]h$]h&]uh1j0hj;;ubeh}(h]h ]h"]h$]h&]uh1jhjV;hMhj5ubj)}(h:``tFEAT_max`` Busy time for Set Features and Get Features h](j)}(h ``tFEAT_max``h]j)}(hjz;h]h tFEAT_max}(hj|;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx;ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjt;ubj1)}(hhh]h)}(h+Busy time for Set Features and Get Featuresh]h+Busy time for Set Features and Get Features}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1j0hjt;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj5ubj)}(h3``tITC_max`` Interface and Timing Mode Change time h](j)}(h ``tITC_max``h]j)}(hj;h]htITC_max}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj;ubj1)}(hhh]h)}(h%Interface and Timing Mode Change timeh]h%Interface and Timing Mode Change time}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1j0hj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj5ubj)}(h#``tQHS_max`` Data hold skew factor h](j)}(h ``tQHS_max``h]j)}(hj;h]htQHS_max}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj;ubj1)}(hhh]h)}(hData hold skew factorh]hData hold skew factor}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1j0hj;ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj5ubj)}(hH``tRHW_min`` Data output cycle to command, address, or data input cycle h](j)}(h ``tRHW_min``h]j)}(hj%<h]htRHW_min}(hj'<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#<ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj<ubj1)}(hhh]h)}(h:Data output cycle to command, address, or data input cycleh]h:Data output cycle to command, address, or data input cycle}(hj><hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:<hMhj;<ubah}(h]h ]h"]h$]h&]uh1j0hj<ubeh}(h]h ]h"]h$]h&]uh1jhj:<hMhj5ubj)}(h)``tRR_min`` Ready to RE# low (data only) h](j)}(h ``tRR_min``h]j)}(hj^<h]htRR_min}(hj`<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\<ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjX<ubj1)}(hhh]h)}(hReady to RE# low (data only)h]hReady to RE# low (data only)}(hjw<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjs<hMhjt<ubah}(h]h ]h"]h$]h&]uh1j0hjX<ubeh}(h]h ]h"]h$]h&]uh1jhjs<hMhj5ubj)}(hc``tRST_max`` Device reset time, measured from the falling edge of R/B# to the rising edge of R/B#. h](j)}(h ``tRST_max``h]j)}(hj<h]htRST_max}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj<ubj1)}(hhh]h)}(hUDevice reset time, measured from the falling edge of R/B# to the rising edge of R/B#.h]hUDevice reset time, measured from the falling edge of R/B# to the rising edge of R/B#.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj<ubah}(h]h ]h"]h$]h&]uh1j0hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM hj5ubj)}(h"``tWB_max`` WE# high to SR[6] low h](j)}(h ``tWB_max``h]j)}(hj<h]htWB_max}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj<ubj1)}(hhh]h)}(hWE# high to SR[6] lowh]hWE# high to SR[6] low}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM hj<ubah}(h]h ]h"]h$]h&]uh1j0hj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM hj5ubj)}(h!``tWHR_min`` WE# high to RE# low h](j)}(h ``tWHR_min``h]j)}(hj =h]htWHR_min}(hj =hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj=ubj1)}(hhh]h)}(hWE# high to RE# lowh]hWE# high to RE# low}(hj#=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hM hj =ubah}(h]h ]h"]h$]h&]uh1j0hj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hM hj5ubj)}(h-``tWRCK_min`` W/R_n low to data output cycle h](j)}(h ``tWRCK_min``h]j)}(hjC=h]h tWRCK_min}(hjE=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA=ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM hj==ubj1)}(hhh]h)}(hW/R_n low to data output cycleh]hW/R_n low to data output cycle}(hj\=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX=hM hjY=ubah}(h]h ]h"]h$]h&]uh1j0hj==ubeh}(h]h ]h"]h$]h&]uh1jhjX=hM hj5ubj)}(h'``tWW_min`` WP# transition to WE# low h](j)}(h ``tWW_min``h]j)}(hj|=h]htWW_min}(hj~=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz=ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjv=ubj1)}(hhh]h)}(hWP# transition to WE# lowh]hWP# transition to WE# low}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj=ubah}(h]h ]h"]h$]h&]uh1j0hjv=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj5ubeh}(h]h ]h"]h$]h&]uh1j hj5ubh)}(h**Description**h]j)}(hj=h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubh)}(hX'This struct defines the timing requirements of a NV-DDR NAND data interface. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf (chapter 4.18.2 NV-DDR)h](hThis struct defines the timing requirements of a NV-DDR NAND data interface. These information can be found in every NAND datasheets and the timings meaning are described in the ONFI specifications: }(hj=hhhNhNubj4)}(hHhttps://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdfh]hHhttps://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf}(hj=hhhNhNubah}(h]h ]h"]h$]h&]refurij=uh1j4hj=ubh (chapter 4.18.2 NV-DDR)}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubh)}(h/All these timings are expressed in picoseconds.h]h/All these timings are expressed in picoseconds.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_interface_type (C enum)c.nand_interface_typehNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_interface_typeh]j/)}(henum nand_interface_typeh](j5)}(henumh]henum}(hj>hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj>hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj.>hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj>hhhj->hMubjX)}(hnand_interface_typeh]j^)}(hj>h]hnand_interface_type}(hj@>hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj<>ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj>hhhj->hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj>hhhj->hMubah}(h]j>ah ](jjeh"]h$]h&]jj)jhuh1j(hj->hMhj>hhubj)}(hhh]h)}(hNAND interface typeh]hNAND interface type}(hjb>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMRhj_>hhubah}(h]h ]h"]h$]h&]uh1jhj>hhhj->hMubeh}(h]h ](jenumeh"]h$]h&]jjjjz>jjz>jjjuh1j#hhhjhNhNubj)}(hq**Constants** ``NAND_SDR_IFACE`` Single Data Rate interface ``NAND_NVDDR_IFACE`` Double Data Rate interfaceh](h)}(h **Constants**h]j)}(hj>h]h Constants}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMVhj~>ubj )}(hhh](j)}(h.``NAND_SDR_IFACE`` Single Data Rate interface h](j)}(h``NAND_SDR_IFACE``h]j)}(hj>h]hNAND_SDR_IFACE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMYhj>ubj1)}(hhh]h)}(hSingle Data Rate interfaceh]hSingle Data Rate interface}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hMYhj>ubah}(h]h ]h"]h$]h&]uh1j0hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMYhj>ubj)}(h/``NAND_NVDDR_IFACE`` Double Data Rate interfaceh](j)}(h``NAND_NVDDR_IFACE``h]j)}(hj>h]hNAND_NVDDR_IFACE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hj>ubj1)}(hhh]h)}(hDouble Data Rate interfaceh]hDouble Data Rate interface}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM\hj>ubah}(h]h ]h"]h$]h&]uh1j0hj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hM[hj>ubeh}(h]h ]h"]h$]h&]uh1j hj~>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j nand_interface_config (C struct)c.nand_interface_confighNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_interface_configh]j/)}(hstruct nand_interface_configh](j5)}(hj8h]hstruct}(hj6?hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj2?hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMaubjG)}(h h]h }(hjD?hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj2?hhhjC?hMaubjX)}(hnand_interface_configh]j^)}(hj0?h]hnand_interface_config}(hjV?hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjR?ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj2?hhhjC?hMaubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj.?hhhjC?hMaubah}(h]j)?ah ](jjeh"]h$]h&]jj)jhuh1j(hjC?hMahj+?hhubj)}(hhh]h)}(hNAND interface timingh]hNAND interface timing}(hjx?hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM\hju?hhubah}(h]h ]h"]h$]h&]uh1jhj+?hhhjC?hMaubeh}(h]h ](jstructeh"]h$]h&]jjjj?jj?jjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_interface_config { enum nand_interface_type type; struct nand_timings { unsigned int mode; union { struct nand_sdr_timings sdr; struct nand_nvddr_timings nvddr; }; } timings; }; **Members** ``type`` type of the timing ``timings`` The timing information ``timings.mode`` Timing mode as defined in the specification ``{unnamed_union}`` anonymous ``timings.sdr`` Use it when **type** is ``NAND_SDR_IFACE``. ``timings.nvddr`` Use it when **type** is ``NAND_NVDDR_IFACE``.h](j)}(hX>**Definition**:: struct nand_interface_config { enum nand_interface_type type; struct nand_timings { unsigned int mode; union { struct nand_sdr_timings sdr; struct nand_nvddr_timings nvddr; }; } timings; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM`hj?ubjs)}(hXstruct nand_interface_config { enum nand_interface_type type; struct nand_timings { unsigned int mode; union { struct nand_sdr_timings sdr; struct nand_nvddr_timings nvddr; }; } timings; };h]hXstruct nand_interface_config { enum nand_interface_type type; struct nand_timings { unsigned int mode; union { struct nand_sdr_timings sdr; struct nand_nvddr_timings nvddr; }; } timings; };}hj?sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMbhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hM`hj?ubh)}(h **Members**h]j)}(hj?h]hMembers}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMmhj?ubj )}(hhh](j)}(h``type`` type of the timing h](j)}(h``type``h]j)}(hj?h]htype}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM^hj?ubj1)}(hhh]h)}(htype of the timingh]htype of the timing}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hM^hj@ubah}(h]h ]h"]h$]h&]uh1j0hj?ubeh}(h]h ]h"]h$]h&]uh1jhj@hM^hj?ubj)}(h#``timings`` The timing information h](j)}(h ``timings``h]j)}(hj(@h]htimings}(hj*@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&@ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM_hj"@ubj1)}(hhh]h)}(hThe timing informationh]hThe timing information}(hjA@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=@hM_hj>@ubah}(h]h ]h"]h$]h&]uh1j0hj"@ubeh}(h]h ]h"]h$]h&]uh1jhj=@hM_hj?ubj)}(h=``timings.mode`` Timing mode as defined in the specification h](j)}(h``timings.mode``h]j)}(hja@h]h timings.mode}(hjc@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_@ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM`hj[@ubj1)}(hhh]h)}(h+Timing mode as defined in the specificationh]h+Timing mode as defined in the specification}(hjz@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv@hM`hjw@ubah}(h]h ]h"]h$]h&]uh1j0hj[@ubeh}(h]h ]h"]h$]h&]uh1jhjv@hM`hj?ubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj@h]h{unnamed_union}}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj@ubj1)}(hhh]h)}(h anonymoush]h anonymous}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hKhj@ubah}(h]h ]h"]h$]h&]uh1j0hj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hKhj?ubj)}(h<``timings.sdr`` Use it when **type** is ``NAND_SDR_IFACE``. h](j)}(h``timings.sdr``h]j)}(hj@h]h timings.sdr}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMahj@ubj1)}(hhh]h)}(h+Use it when **type** is ``NAND_SDR_IFACE``.h](h Use it when }(hj@hhhNhNubj)}(h**type**h]htype}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh is }(hj@hhhNhNubj)}(h``NAND_SDR_IFACE``h]hNAND_SDR_IFACE}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh.}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj@hMahj@ubah}(h]h ]h"]h$]h&]uh1j0hj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMahj?ubj)}(h?``timings.nvddr`` Use it when **type** is ``NAND_NVDDR_IFACE``.h](j)}(h``timings.nvddr``h]j)}(hj0Ah]h timings.nvddr}(hj2AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.Aubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMahj*Aubj1)}(hhh]h)}(h-Use it when **type** is ``NAND_NVDDR_IFACE``.h](h Use it when }(hjIAhhhNhNubj)}(h**type**h]htype}(hjQAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIAubh is }(hjIAhhhNhNubj)}(h``NAND_NVDDR_IFACE``h]hNAND_NVDDR_IFACE}(hjcAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIAubh.}(hjIAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMbhjFAubah}(h]h ]h"]h$]h&]uh1j0hj*Aubeh}(h]h ]h"]h$]h&]uh1jhjEAhMahj?ubeh}(h]h ]h"]h$]h&]uh1j hj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"nand_interface_is_sdr (C function)c.nand_interface_is_sdrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hEbool nand_interface_is_sdr (const struct nand_interface_config *conf)h]j/)}(hDbool nand_interface_is_sdr(const struct nand_interface_config *conf)h](hdesc_sig_keyword_type)}(hboolh]hbool}(hjAhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jAhjAhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMoubjG)}(h h]h }(hjAhhhNhNubah}(h]h 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]pah"]h$]h&]uh1jbBhjAubj^)}(hconfh]hconf}(hjsBhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjAubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjAubah}(h]h ]h"]h$]h&]jjuh1jAhjAhhhjAhMoubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjAhhhjAhMoubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1j(hjAhMohjAhhubj)}(hhh]h)}(hget the interface typeh]hget the interface type}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMohjBhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhjAhMoubeh}(h]h ](jfunctioneh"]h$]h&]jjjjBjjBjjjuh1j#hhhjhNhNubj)}(hQ**Parameters** ``const struct nand_interface_config *conf`` The data interfaceh](h)}(h**Parameters**h]j)}(hjBh]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMshjBubj )}(hhh]j)}(h?``const struct nand_interface_config *conf`` The data interfaceh](j)}(h,``const struct nand_interface_config *conf``h]j)}(hjBh]h(const struct nand_interface_config *conf}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMuhjBubj1)}(hhh]h)}(hThe data interfaceh]hThe data interface}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMphjBubah}(h]h ]h"]h$]h&]uh1j0hjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMuhjBubah}(h]h ]h"]h$]h&]uh1j hjBubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$nand_interface_is_nvddr (C function)c.nand_interface_is_nvddrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hGbool nand_interface_is_nvddr (const struct nand_interface_config *conf)h]j/)}(hFbool nand_interface_is_nvddr(const struct nand_interface_config *conf)h](jA)}(hjAh]hbool}(hj8ChhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj4Chhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMxubjG)}(h h]h }(hjFChhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj4ChhhjEChMxubjX)}(hnand_interface_is_nvddrh]j^)}(hnand_interface_is_nvddrh]hnand_interface_is_nvddr}(hjXChhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjTCubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj4ChhhjEChMxubjA)}(h*(const struct nand_interface_config *conf)h]jA)}(h(const struct nand_interface_config *confh](j5)}(hjAh]hconst}(hjtChhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjpCubjG)}(h h]h }(hjChhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjpCubj5)}(hj8h]hstruct}(hjChhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjpCubjG)}(h h]h }(hjChhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjpCubh)}(hhh]j^)}(hnand_interface_configh]hnand_interface_config}(hjChhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjCubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjCmodnameN classnameNjFBjIB)}jLB]jOB)}jBBjZCsbc.nand_interface_is_nvddrasbuh1hhjpCubjG)}(h h]h }(hjChhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjpCubjcB)}(hjfBh]h*}(hjChhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjpCubj^)}(hconfh]hconf}(hjChhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjpCubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjlCubah}(h]h ]h"]h$]h&]jjuh1jAhj4ChhhjEChMxubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj0ChhhjEChMxubah}(h]j+Cah ](jjeh"]h$]h&]jj)jhuh1j(hjEChMxhj-Chhubj)}(hhh]h)}(hget the interface typeh]hget the interface type}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMxhjDhhubah}(h]h ]h"]h$]h&]uh1jhj-ChhhjEChMxubeh}(h]h ](jfunctioneh"]h$]h&]jjjj*Djj*Djjjuh1j#hhhjhNhNubj)}(hQ**Parameters** ``const struct nand_interface_config *conf`` The data interfaceh](h)}(h**Parameters**h]j)}(hj4Dh]h Parameters}(hj6DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2Dubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM|hj.Dubj )}(hhh]j)}(h?``const struct nand_interface_config *conf`` The data interfaceh](j)}(h,``const struct nand_interface_config *conf``h]j)}(hjSDh]h(const struct nand_interface_config *conf}(hjUDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQDubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM~hjMDubj1)}(hhh]h)}(hThe data interfaceh]hThe data interface}(hjlDhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMyhjiDubah}(h]h ]h"]h$]h&]uh1j0hjMDubeh}(h]h ]h"]h$]h&]uh1jhjhDhM~hjJDubah}(h]h ]h"]h$]h&]uh1j hj.Dubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!nand_get_sdr_timings (C function)c.nand_get_sdr_timingshNtauh1jhjhhhNhNubj$)}(hhh](j))}(h_const struct nand_sdr_timings * nand_get_sdr_timings (const struct nand_interface_config *conf)h]j/)}(h]const struct nand_sdr_timings *nand_get_sdr_timings(const struct nand_interface_config *conf)h](j5)}(hjAh]hconst}(hjDhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjDhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjDhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjDhhhjDhMubj5)}(hj8h]hstruct}(hjDhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjDhhhjDhMubjG)}(h h]h }(hjDhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjDhhhjDhMubh)}(hhh]j^)}(hnand_sdr_timingsh]hnand_sdr_timings}(hjDhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjDubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjDmodnameN classnameNjFBjIB)}jLB]jOB)}jBBnand_get_sdr_timingssbc.nand_get_sdr_timingsasbuh1hhjDhhhjDhMubjG)}(h h]h }(hjEhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjDhhhjDhMubjcB)}(hjfBh]h*}(hjEhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjDhhhjDhMubjX)}(hnand_get_sdr_timingsh]j^)}(hjEh]hnand_get_sdr_timings}(hj'EhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj#Eubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjDhhhjDhMubjA)}(h*(const struct nand_interface_config *conf)h]jA)}(h(const struct nand_interface_config *confh](j5)}(hjAh]hconst}(hjBEhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj>EubjG)}(h h]h }(hjOEhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj>Eubj5)}(hj8h]hstruct}(hj]EhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj>EubjG)}(h h]h }(hjjEhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj>Eubh)}(hhh]j^)}(hnand_interface_configh]hnand_interface_config}(hj{EhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjxEubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetj}EmodnameN classnameNjFBjIB)}jLB]jEc.nand_get_sdr_timingsasbuh1hhj>EubjG)}(h h]h }(hjEhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj>EubjcB)}(hjfBh]h*}(hjEhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhj>Eubj^)}(hconfh]hconf}(hjEhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj>Eubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhj:Eubah}(h]h ]h"]h$]h&]jjuh1jAhjDhhhjDhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjDhhhjDhMubah}(h]jDah ](jjeh"]h$]h&]jj)jhuh1j(hjDhMhjDhhubj)}(hhh]h)}(h"get SDR timing from data interfaceh]h"get SDR timing from data interface}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjEhhubah}(h]h ]h"]h$]h&]uh1jhjDhhhjDhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjEjjEjjjuh1j#hhhjhNhNubj)}(hQ**Parameters** ``const struct nand_interface_config *conf`` The data interfaceh](h)}(h**Parameters**h]j)}(hjFh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjEubj )}(hhh]j)}(h?``const struct nand_interface_config *conf`` The data interfaceh](j)}(h,``const struct nand_interface_config *conf``h]j)}(hjFh]h(const struct nand_interface_config *conf}(hj!FhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjFubj1)}(hhh]h)}(hThe data interfaceh]hThe data interface}(hj8FhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5Fubah}(h]h ]h"]h$]h&]uh1j0hjFubeh}(h]h ]h"]h$]h&]uh1jhj4FhMhjFubah}(h]h ]h"]h$]h&]uh1j hjEubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#nand_get_nvddr_timings (C function)c.nand_get_nvddr_timingshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hcconst struct nand_nvddr_timings * nand_get_nvddr_timings (const struct nand_interface_config *conf)h]j/)}(haconst struct nand_nvddr_timings *nand_get_nvddr_timings(const struct nand_interface_config *conf)h](j5)}(hjAh]hconst}(hjyFhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjuFhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjFhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjuFhhhjFhMubj5)}(hj8h]hstruct}(hjFhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjuFhhhjFhMubjG)}(h h]h }(hjFhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjuFhhhjFhMubh)}(hhh]j^)}(hnand_nvddr_timingsh]hnand_nvddr_timings}(hjFhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjFubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjFmodnameN classnameNjFBjIB)}jLB]jOB)}jBBnand_get_nvddr_timingssbc.nand_get_nvddr_timingsasbuh1hhjuFhhhjFhMubjG)}(h h]h }(hjFhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjuFhhhjFhMubjcB)}(hjfBh]h*}(hjFhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjuFhhhjFhMubjX)}(hnand_get_nvddr_timingsh]j^)}(hjFh]hnand_get_nvddr_timings}(hjFhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjFubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjuFhhhjFhMubjA)}(h*(const struct nand_interface_config *conf)h]jA)}(h(const struct nand_interface_config *confh](j5)}(hjAh]hconst}(hjGhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj GubjG)}(h h]h }(hjGhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj Gubj5)}(hj8h]hstruct}(hj)GhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj GubjG)}(h h]h }(hj6GhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj Gubh)}(hhh]j^)}(hnand_interface_configh]hnand_interface_config}(hjGGhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjDGubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjIGmodnameN classnameNjFBjIB)}jLB]jFc.nand_get_nvddr_timingsasbuh1hhj GubjG)}(h h]h }(hjeGhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj GubjcB)}(hjfBh]h*}(hjsGhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhj Gubj^)}(hconfh]hconf}(hjGhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj Gubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjGubah}(h]h ]h"]h$]h&]jjuh1jAhjuFhhhjFhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjqFhhhjFhMubah}(h]jlFah ](jjeh"]h$]h&]jj)jhuh1j(hjFhMhjnFhhubj)}(hhh]h)}(h%get NV-DDR timing from data interfaceh]h%get NV-DDR timing from data interface}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjGhhubah}(h]h ]h"]h$]h&]uh1jhjnFhhhjFhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjGjjGjjjuh1j#hhhjhNhNubj)}(hQ**Parameters** ``const struct nand_interface_config *conf`` The data interfaceh](h)}(h**Parameters**h]j)}(hjGh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjGubj )}(hhh]j)}(h?``const struct nand_interface_config *conf`` The data interfaceh](j)}(h,``const struct nand_interface_config *conf``h]j)}(hjGh]h(const struct nand_interface_config *conf}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjGubj1)}(hhh]h)}(hThe data interfaceh]hThe data interface}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHubah}(h]h ]h"]h$]h&]uh1j0hjGubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjGubah}(h]h ]h"]h$]h&]uh1j hjGubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_cmd_instr (C struct)c.nand_op_cmd_instrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_cmd_instrh]j/)}(hstruct nand_op_cmd_instrh](j5)}(hj8h]hstruct}(hjEHhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjAHhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjSHhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjAHhhhjRHhMubjX)}(hnand_op_cmd_instrh]j^)}(hj?Hh]hnand_op_cmd_instr}(hjeHhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjaHubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjAHhhhjRHhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj=HhhhjRHhMubah}(h]j8Hah ](jjeh"]h$]h&]jj)jhuh1j(hjRHhMhj:Hhhubj)}(hhh]h)}(h#Definition of a command instructionh]h#Definition of a command instruction}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHhhubah}(h]h ]h"]h$]h&]uh1jhj:HhhhjRHhMubeh}(h]h ](jstructeh"]h$]h&]jjjjHjjHjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_op_cmd_instr { u8 opcode; }; **Members** ``opcode`` the command to issue in one cycleh](j)}(hG**Definition**:: struct nand_op_cmd_instr { u8 opcode; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh:}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHubjs)}(h.struct nand_op_cmd_instr { u8 opcode; };h]h.struct nand_op_cmd_instr { u8 opcode; };}hjHsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjHubh)}(h **Members**h]j)}(hjHh]hMembers}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHubj )}(hhh]j)}(h,``opcode`` the command to issue in one cycleh](j)}(h ``opcode``h]j)}(hjHh]hopcode}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHubj1)}(hhh]h)}(h!the command to issue in one cycleh]h!the command to issue in one cycle}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjIubah}(h]h ]h"]h$]h&]uh1j0hjHubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjHubah}(h]h ]h"]h$]h&]uh1j hjHubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_addr_instr (C struct)c.nand_op_addr_instrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_addr_instrh]j/)}(hstruct nand_op_addr_instrh](j5)}(hj8h]hstruct}(hjXIhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjTIhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjfIhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjTIhhhjeIhMubjX)}(hnand_op_addr_instrh]j^)}(hjRIh]hnand_op_addr_instr}(hjxIhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjtIubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjTIhhhjeIhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjPIhhhjeIhMubah}(h]jKIah ](jjeh"]h$]h&]jj)jhuh1j(hjeIhMhjMIhhubj)}(hhh]h)}(h$Definition of an address instructionh]h$Definition of an address instruction}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjIhhubah}(h]h ]h"]h$]h&]uh1jhjMIhhhjeIhMubeh}(h]h ](jstructeh"]h$]h&]jjjjIjjIjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_op_addr_instr { unsigned int naddrs; const u8 *addrs; }; **Members** ``naddrs`` length of the **addrs** array ``addrs`` array containing the address cycles to issueh](j)}(hk**Definition**:: struct nand_op_addr_instr { unsigned int naddrs; const u8 *addrs; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh:}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjIubjs)}(hPstruct nand_op_addr_instr { unsigned int naddrs; const u8 *addrs; };h]hPstruct nand_op_addr_instr { unsigned int naddrs; const u8 *addrs; };}hjIsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjIubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjIubh)}(h **Members**h]j)}(hjIh]hMembers}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjIubj )}(hhh](j)}(h)``naddrs`` length of the **addrs** array h](j)}(h ``naddrs``h]j)}(hjJh]hnaddrs}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj Jubj1)}(hhh]h)}(hlength of the **addrs** arrayh](hlength of the }(hj*JhhhNhNubj)}(h **addrs**h]haddrs}(hj2JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*Jubh array}(hj*JhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj&JhMhj'Jubah}(h]h ]h"]h$]h&]uh1j0hj Jubeh}(h]h ]h"]h$]h&]uh1jhj&JhMhjJubj)}(h6``addrs`` array containing the address cycles to issueh](j)}(h ``addrs``h]j)}(hj\Jh]haddrs}(hj^JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZJubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjVJubj1)}(hhh]h)}(h,array containing the address cycles to issueh]h,array containing the address cycles to issue}(hjuJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjrJubah}(h]h ]h"]h$]h&]uh1j0hjVJubeh}(h]h ]h"]h$]h&]uh1jhjqJhMhjJubeh}(h]h ]h"]h$]h&]uh1j hjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_data_instr (C struct)c.nand_op_data_instrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_data_instrh]j/)}(hstruct nand_op_data_instrh](j5)}(hj8h]hstruct}(hjJhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjJhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjJhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjJhhhjJhMubjX)}(hnand_op_data_instrh]j^)}(hjJh]hnand_op_data_instr}(hjJhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjJubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjJhhhjJhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjJhhhjJhMubah}(h]jJah ](jjeh"]h$]h&]jj)jhuh1j(hjJhMhjJhhubj)}(hhh]h)}(h Definition of a data instructionh]h Definition of a data instruction}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjJhhubah}(h]h ]h"]h$]h&]uh1jhjJhhhjJhMubeh}(h]h ](jstructeh"]h$]h&]jjjjKjjKjjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_op_data_instr { unsigned int len; union { void *in; const void *out; } buf; bool force_8bit; }; **Members** ``len`` number of data bytes to move ``buf`` buffer to fill ``buf.in`` buffer to fill when reading from the NAND chip ``buf.out`` buffer to read from when writing to the NAND chip ``force_8bit`` force 8-bit access **Description** Please note that "in" and "out" are inverted from the ONFI specification and are from the controller perspective, so a "in" is a read from the NAND chip while a "out" is a write to the NAND chip.h](j)}(h**Definition**:: struct nand_op_data_instr { unsigned int len; union { void *in; const void *out; } buf; bool force_8bit; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj KhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubh:}(hjKhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubjs)}(hstruct nand_op_data_instr { unsigned int len; union { void *in; const void *out; } buf; bool force_8bit; };h]hstruct nand_op_data_instr { unsigned int len; union { void *in; const void *out; } buf; bool force_8bit; };}hj9Ksbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubeh}(h]h ]h"]h$]h&]uh1jhj8KhMhjKubh)}(h **Members**h]j)}(hjPKh]hMembers}(hjRKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNKubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubj )}(hhh](j)}(h%``len`` number of data bytes to move h](j)}(h``len``h]j)}(hjoKh]hlen}(hjqKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmKubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjiKubj1)}(hhh]h)}(hnumber of data bytes to moveh]hnumber of data bytes to move}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjKubah}(h]h ]h"]h$]h&]uh1j0hjiKubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjfKubj)}(h``buf`` buffer to fill h](j)}(h``buf``h]j)}(hjKh]hbuf}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubj1)}(hhh]h)}(hbuffer to fillh]hbuffer to fill}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjKubah}(h]h ]h"]h$]h&]uh1j0hjKubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjfKubj)}(h:``buf.in`` buffer to fill when reading from the NAND chip h](j)}(h ``buf.in``h]j)}(hjKh]hbuf.in}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubj1)}(hhh]h)}(h.buffer to fill when reading from the NAND chiph]h.buffer to fill when reading from the NAND chip}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMhjKubah}(h]h ]h"]h$]h&]uh1j0hjKubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjfKubj)}(h>``buf.out`` buffer to read from when writing to the NAND chip h](j)}(h ``buf.out``h]j)}(hjLh]hbuf.out}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjLubj1)}(hhh]h)}(h1buffer to read from when writing to the NAND chiph]h1buffer to read from when writing to the NAND chip}(hj3LhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/LhMhj0Lubah}(h]h ]h"]h$]h&]uh1j0hjLubeh}(h]h ]h"]h$]h&]uh1jhj/LhMhjfKubj)}(h#``force_8bit`` force 8-bit access h](j)}(h``force_8bit``h]j)}(hjSLh]h force_8bit}(hjULhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQLubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjMLubj1)}(hhh]h)}(hforce 8-bit accessh]hforce 8-bit access}(hjlLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjiLubah}(h]h ]h"]h$]h&]uh1j0hjMLubeh}(h]h ]h"]h$]h&]uh1jhjhLhMhjfKubeh}(h]h ]h"]h$]h&]uh1j hjKubh)}(h**Description**h]j)}(hjLh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubh)}(hPlease note that "in" and "out" are inverted from the ONFI specification and are from the controller perspective, so a "in" is a read from the NAND chip while a "out" is a write to the NAND chip.h]hPlease note that “in” and “out” are inverted from the ONFI specification and are from the controller perspective, so a “in” is a read from the NAND chip while a “out” is a write to the NAND chip.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j nand_op_waitrdy_instr (C struct)c.nand_op_waitrdy_instrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_waitrdy_instrh]j/)}(hstruct nand_op_waitrdy_instrh](j5)}(hj8h]hstruct}(hjLhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjLhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjLhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjLhhhjLhMubjX)}(hnand_op_waitrdy_instrh]j^)}(hjLh]hnand_op_waitrdy_instr}(hjLhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjLubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjLhhhjLhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjLhhhjLhMubah}(h]jLah ](jjeh"]h$]h&]jj)jhuh1j(hjLhMhjLhhubj)}(hhh]h)}(h&Definition of a wait ready instructionh]h&Definition of a wait ready instruction}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjMhhubah}(h]h ]h"]h$]h&]uh1jhjLhhhjLhMubeh}(h]h ](jstructeh"]h$]h&]jjjj.Mjj.Mjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_op_waitrdy_instr { unsigned int timeout_ms; }; **Members** ``timeout_ms`` maximum delay while waiting for the ready/busy pin in msh](j)}(hY**Definition**:: struct nand_op_waitrdy_instr { unsigned int timeout_ms; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj>MhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:Mubh:}(hj:MhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6Mubjs)}(h@struct nand_op_waitrdy_instr { unsigned int timeout_ms; };h]h@struct nand_op_waitrdy_instr { unsigned int timeout_ms; };}hjWMsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6Mubeh}(h]h ]h"]h$]h&]uh1jhjVMhMhj2Mubh)}(h **Members**h]j)}(hjnMh]hMembers}(hjpMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlMubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2Mubj )}(hhh]j)}(hG``timeout_ms`` maximum delay while waiting for the ready/busy pin in msh](j)}(h``timeout_ms``h]j)}(hjMh]h timeout_ms}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjMubj1)}(hhh]h)}(h8maximum delay while waiting for the ready/busy pin in msh]h8maximum delay while waiting for the ready/busy pin in ms}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjMubah}(h]h ]h"]h$]h&]uh1j0hjMubeh}(h]h ]h"]h$]h&]uh1jhjMhMhjMubah}(h]h ]h"]h$]h&]uh1j hj2Mubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_instr_type (C enum)c.nand_op_instr_typehNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_instr_typeh]j/)}(henum nand_op_instr_typeh](j5)}(hj!>h]henum}(hjMhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjMhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjMhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjMhhhjMhMubjX)}(hnand_op_instr_typeh]j^)}(hjMh]hnand_op_instr_type}(hjNhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjNubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjMhhhjMhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjMhhhjMhMubah}(h]jMah ](jjeh"]h$]h&]jj)jhuh1j(hjMhMhjMhhubj)}(hhh]h)}(h#Definition of all instruction typesh]h#Definition of all instruction types}(hj)NhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj&Nhhubah}(h]h ]h"]h$]h&]uh1jhjMhhhjMhMubeh}(h]h ](jenumeh"]h$]h&]jjjjANjjANjjjuh1j#hhhjhNhNubj)}(hX**Constants** ``NAND_OP_CMD_INSTR`` command instruction ``NAND_OP_ADDR_INSTR`` address instruction ``NAND_OP_DATA_IN_INSTR`` data in instruction ``NAND_OP_DATA_OUT_INSTR`` data out instruction ``NAND_OP_WAITRDY_INSTR`` wait ready instructionh](h)}(h **Constants**h]j)}(hjKNh]h Constants}(hjMNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjINubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjENubj )}(hhh](j)}(h*``NAND_OP_CMD_INSTR`` command instruction h](j)}(h``NAND_OP_CMD_INSTR``h]j)}(hjjNh]hNAND_OP_CMD_INSTR}(hjlNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhNubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjdNubj1)}(hhh]h)}(hcommand instructionh]hcommand instruction}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubah}(h]h ]h"]h$]h&]uh1j0hjdNubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjaNubj)}(h+``NAND_OP_ADDR_INSTR`` address instruction h](j)}(h``NAND_OP_ADDR_INSTR``h]j)}(hjNh]hNAND_OP_ADDR_INSTR}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjNubj1)}(hhh]h)}(haddress instructionh]haddress instruction}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubah}(h]h ]h"]h$]h&]uh1j0hjNubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjaNubj)}(h.``NAND_OP_DATA_IN_INSTR`` data in instruction h](j)}(h``NAND_OP_DATA_IN_INSTR``h]j)}(hjNh]hNAND_OP_DATA_IN_INSTR}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjNubj1)}(hhh]h)}(hdata in instructionh]hdata in instruction}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhMhjNubah}(h]h ]h"]h$]h&]uh1j0hjNubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjaNubj)}(h0``NAND_OP_DATA_OUT_INSTR`` data out instruction h](j)}(h``NAND_OP_DATA_OUT_INSTR``h]j)}(hjOh]hNAND_OP_DATA_OUT_INSTR}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjOubj1)}(hhh]h)}(hdata out instructionh]hdata out instruction}(hj.OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*OhMhj+Oubah}(h]h ]h"]h$]h&]uh1j0hjOubeh}(h]h ]h"]h$]h&]uh1jhj*OhMhjaNubj)}(h0``NAND_OP_WAITRDY_INSTR`` wait ready instructionh](j)}(h``NAND_OP_WAITRDY_INSTR``h]j)}(hjNOh]hNAND_OP_WAITRDY_INSTR}(hjPOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLOubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjHOubj1)}(hhh]h)}(hwait ready instructionh]hwait ready instruction}(hjgOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjdOubah}(h]h ]h"]h$]h&]uh1j0hjHOubeh}(h]h ]h"]h$]h&]uh1jhjcOhMhjaNubeh}(h]h ]h"]h$]h&]uh1j hjENubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_instr (C struct)c.nand_op_instrhNtauh1jhjhhhNhNubj$)}(hhh](j))}(h nand_op_instrh]j/)}(hstruct nand_op_instrh](j5)}(hj8h]hstruct}(hjOhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjOhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjOhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjOhhhjOhMubjX)}(h nand_op_instrh]j^)}(hjOh]h nand_op_instr}(hjOhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjOubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjOhhhjOhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjOhhhjOhMubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1j(hjOhMhjOhhubj)}(hhh]h)}(hInstruction objecth]hInstruction object}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjOhhubah}(h]h ]h"]h$]h&]uh1jhjOhhhjOhMubeh}(h]h ](jstructeh"]h$]h&]jjjjPjjPjjjuh1j#hhhjhNhNubj)}(hX  **Definition**:: struct nand_op_instr { enum nand_op_instr_type type; union { struct nand_op_cmd_instr cmd; struct nand_op_addr_instr addr; struct nand_op_data_instr data; struct nand_op_waitrdy_instr waitrdy; } ctx; unsigned int delay_ns; }; **Members** ``type`` the instruction type ``ctx`` extra data associated to the instruction. You'll have to use the appropriate element depending on **type** ``ctx.cmd`` use it if **type** is ``NAND_OP_CMD_INSTR`` ``ctx.addr`` use it if **type** is ``NAND_OP_ADDR_INSTR`` ``ctx.data`` use it if **type** is ``NAND_OP_DATA_IN_INSTR`` or ``NAND_OP_DATA_OUT_INSTR`` ``ctx.waitrdy`` use it if **type** is ``NAND_OP_WAITRDY_INSTR`` ``delay_ns`` delay the controller should apply after the instruction has been issued on the bus. Most modern controllers have internal timings control logic, and in this case, the controller driver can ignore this field.h](j)}(hXP**Definition**:: struct nand_op_instr { enum nand_op_instr_type type; union { struct nand_op_cmd_instr cmd; struct nand_op_addr_instr addr; struct nand_op_data_instr data; struct nand_op_waitrdy_instr waitrdy; } ctx; unsigned int delay_ns; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubh:}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj Pubjs)}(hX)struct nand_op_instr { enum nand_op_instr_type type; union { struct nand_op_cmd_instr cmd; struct nand_op_addr_instr addr; struct nand_op_data_instr data; struct nand_op_waitrdy_instr waitrdy; } ctx; unsigned int delay_ns; };h]hX)struct nand_op_instr { enum nand_op_instr_type type; union { struct nand_op_cmd_instr cmd; struct nand_op_addr_instr addr; struct nand_op_data_instr data; struct nand_op_waitrdy_instr waitrdy; } ctx; unsigned int delay_ns; };}hj+Psbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj Pubeh}(h]h ]h"]h$]h&]uh1jhj*PhMhjPubh)}(h **Members**h]j)}(hjBPh]hMembers}(hjDPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@Pubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjPubj )}(hhh](j)}(h``type`` the instruction type h](j)}(h``type``h]j)}(hjaPh]htype}(hjcPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_Pubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj[Pubj1)}(hhh]h)}(hthe instruction typeh]hthe instruction type}(hjzPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvPhMhjwPubah}(h]h ]h"]h$]h&]uh1j0hj[Pubeh}(h]h ]h"]h$]h&]uh1jhjvPhMhjXPubj)}(hs``ctx`` extra data associated to the instruction. You'll have to use the appropriate element depending on **type** h](j)}(h``ctx``h]j)}(hjPh]hctx}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjPubj1)}(hhh]h)}(hjextra data associated to the instruction. You'll have to use the appropriate element depending on **type**h](hdextra data associated to the instruction. You’ll have to use the appropriate element depending on }(hjPhhhNhNubj)}(h**type**h]htype}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjPubah}(h]h ]h"]h$]h&]uh1j0hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjXPubj)}(h8``ctx.cmd`` use it if **type** is ``NAND_OP_CMD_INSTR`` h](j)}(h ``ctx.cmd``h]j)}(hjPh]hctx.cmd}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjPubj1)}(hhh]h)}(h+use it if **type** is ``NAND_OP_CMD_INSTR``h](h use it if }(hjPhhhNhNubj)}(h**type**h]htype}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubh is }(hjPhhhNhNubj)}(h``NAND_OP_CMD_INSTR``h]hNAND_OP_CMD_INSTR}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhjPhMhjPubah}(h]h ]h"]h$]h&]uh1j0hjPubeh}(h]h ]h"]h$]h&]uh1jhjPhMhjXPubj)}(h:``ctx.addr`` use it if **type** is ``NAND_OP_ADDR_INSTR`` h](j)}(h ``ctx.addr``h]j)}(hj;Qh]hctx.addr}(hj=QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9Qubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5Qubj1)}(hhh]h)}(h,use it if **type** is ``NAND_OP_ADDR_INSTR``h](h use it if }(hjTQhhhNhNubj)}(h**type**h]htype}(hj\QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTQubh is }(hjTQhhhNhNubj)}(h``NAND_OP_ADDR_INSTR``h]hNAND_OP_ADDR_INSTR}(hjnQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTQubeh}(h]h ]h"]h$]h&]uh1hhjPQhMhjQQubah}(h]h ]h"]h$]h&]uh1j0hj5Qubeh}(h]h ]h"]h$]h&]uh1jhjPQhMhjXPubj)}(h[``ctx.data`` use it if **type** is ``NAND_OP_DATA_IN_INSTR`` or ``NAND_OP_DATA_OUT_INSTR`` h](j)}(h ``ctx.data``h]j)}(hjQh]hctx.data}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjQubj1)}(hhh]h)}(hMuse it if **type** is ``NAND_OP_DATA_IN_INSTR`` or ``NAND_OP_DATA_OUT_INSTR``h](h use it if }(hjQhhhNhNubj)}(h**type**h]htype}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubh is }(hjQhhhNhNubj)}(h``NAND_OP_DATA_IN_INSTR``h]hNAND_OP_DATA_IN_INSTR}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubh or }(hjQhhhNhNubj)}(h``NAND_OP_DATA_OUT_INSTR``h]hNAND_OP_DATA_OUT_INSTR}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjQubah}(h]h ]h"]h$]h&]uh1j0hjQubeh}(h]h ]h"]h$]h&]uh1jhjQhMhjXPubj)}(h@``ctx.waitrdy`` use it if **type** is ``NAND_OP_WAITRDY_INSTR`` h](j)}(h``ctx.waitrdy``h]j)}(hjRh]h ctx.waitrdy}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjQubj1)}(hhh]h)}(h/use it if **type** is ``NAND_OP_WAITRDY_INSTR``h](h use it if }(hjRhhhNhNubj)}(h**type**h]htype}(hj!RhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh is }(hjRhhhNhNubj)}(h``NAND_OP_WAITRDY_INSTR``h]hNAND_OP_WAITRDY_INSTR}(hj3RhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1hhjRhMhjRubah}(h]h ]h"]h$]h&]uh1j0hjQubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjXPubj)}(h``delay_ns`` delay the controller should apply after the instruction has been issued on the bus. Most modern controllers have internal timings control logic, and in this case, the controller driver can ignore this field.h](j)}(h ``delay_ns``h]j)}(hjYRh]hdelay_ns}(hj[RhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWRubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjSRubj1)}(hhh]h)}(hdelay the controller should apply after the instruction has been issued on the bus. Most modern controllers have internal timings control logic, and in this case, the controller driver can ignore this field.h]hdelay the controller should apply after the instruction has been issued on the bus. Most modern controllers have internal timings control logic, and in this case, the controller driver can ignore this field.}(hjrRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoRubah}(h]h ]h"]h$]h&]uh1j0hjSRubeh}(h]h ]h"]h$]h&]uh1jhjnRhMhjXPubeh}(h]h ]h"]h$]h&]uh1j hjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_subop (C struct) c.nand_subophNtauh1jhjhhhNhNubj$)}(hhh](j))}(h nand_suboph]j/)}(hstruct nand_suboph](j5)}(hj8h]hstruct}(hjRhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjRhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjRhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjRhhhjRhMubjX)}(h nand_suboph]j^)}(hjRh]h nand_subop}(hjRhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjRubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjRhhhjRhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjRhhhjRhMubah}(h]jRah ](jjeh"]h$]h&]jj)jhuh1j(hjRhMhjRhhubj)}(hhh]h)}(ha sub operationh]ha sub operation}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMMhjRhhubah}(h]h ]h"]h$]h&]uh1jhjRhhhjRhMubeh}(h]h ](jstructeh"]h$]h&]jjjj Sjj Sjjjuh1j#hhhjhNhNubj)}(hXv **Definition**:: struct nand_subop { unsigned int cs; const struct nand_op_instr *instrs; unsigned int ninstrs; unsigned int first_instr_start_off; unsigned int last_instr_end_off; }; **Members** ``cs`` the CS line to select for this NAND sub-operation ``instrs`` array of instructions ``ninstrs`` length of the **instrs** array ``first_instr_start_off`` offset to start from for the first instruction of the sub-operation ``last_instr_end_off`` offset to end at (excluded) for the last instruction of the sub-operation **Description** Both **first_instr_start_off** and **last_instr_end_off** only apply to data or address instructions. When an operation cannot be handled as is by the NAND controller, it will be split by the parser into sub-operations which will be passed to the controller driver.h](j)}(h**Definition**:: struct nand_subop { unsigned int cs; const struct nand_op_instr *instrs; unsigned int ninstrs; unsigned int first_instr_start_off; unsigned int last_instr_end_off; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh:}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMQhjSubjs)}(hstruct nand_subop { unsigned int cs; const struct nand_op_instr *instrs; unsigned int ninstrs; unsigned int first_instr_start_off; unsigned int last_instr_end_off; };h]hstruct nand_subop { unsigned int cs; const struct nand_op_instr *instrs; unsigned int ninstrs; unsigned int first_instr_start_off; unsigned int last_instr_end_off; };}hj6Ssbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMShjSubeh}(h]h ]h"]h$]h&]uh1jhj5ShMQhjSubh)}(h **Members**h]j)}(hjMSh]hMembers}(hjOShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKSubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hjSubj )}(hhh](j)}(h9``cs`` the CS line to select for this NAND sub-operation h](j)}(h``cs``h]j)}(hjlSh]hcs}(hjnShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjSubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMOhjfSubj1)}(hhh]h)}(h1the CS line to select for this NAND sub-operationh]h1the CS line to select for this NAND sub-operation}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMOhjSubah}(h]h ]h"]h$]h&]uh1j0hjfSubeh}(h]h ]h"]h$]h&]uh1jhjShMOhjcSubj)}(h!``instrs`` array of instructions h](j)}(h ``instrs``h]j)}(hjSh]hinstrs}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMPhjSubj1)}(hhh]h)}(harray of instructionsh]harray of instructions}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShMPhjSubah}(h]h ]h"]h$]h&]uh1j0hjSubeh}(h]h ]h"]h$]h&]uh1jhjShMPhjcSubj)}(h+``ninstrs`` length of the **instrs** array h](j)}(h ``ninstrs``h]j)}(hjSh]hninstrs}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMQhjSubj1)}(hhh]h)}(hlength of the **instrs** arrayh](hlength of the }(hjShhhNhNubj)}(h **instrs**h]hinstrs}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh array}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjShMQhjSubah}(h]h ]h"]h$]h&]uh1j0hjSubeh}(h]h ]h"]h$]h&]uh1jhjShMQhjcSubj)}(h^``first_instr_start_off`` offset to start from for the first instruction of the sub-operation h](j)}(h``first_instr_start_off``h]j)}(hj)Th]hfirst_instr_start_off}(hj+ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'Tubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMShj#Tubj1)}(hhh]h)}(hCoffset to start from for the first instruction of the sub-operationh]hCoffset to start from for the first instruction of the sub-operation}(hjBThhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMRhj?Tubah}(h]h ]h"]h$]h&]uh1j0hj#Tubeh}(h]h ]h"]h$]h&]uh1jhj>ThMShjcSubj)}(hb``last_instr_end_off`` offset to end at (excluded) for the last instruction of the sub-operation h](j)}(h``last_instr_end_off``h]j)}(hjcTh]hlast_instr_end_off}(hjeThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaTubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMVhj]Tubj1)}(hhh]h)}(hIoffset to end at (excluded) for the last instruction of the sub-operationh]hIoffset to end at (excluded) for the last instruction of the sub-operation}(hj|ThhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMThjyTubah}(h]h ]h"]h$]h&]uh1j0hj]Tubeh}(h]h ]h"]h$]h&]uh1jhjxThMVhjcSubeh}(h]h ]h"]h$]h&]uh1j hjSubh)}(h**Description**h]j)}(hjTh]h Description}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMXhjSubh)}(heBoth **first_instr_start_off** and **last_instr_end_off** only apply to data or address instructions.h](hBoth }(hjThhhNhNubj)}(h**first_instr_start_off**h]hfirst_instr_start_off}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubh and }(hjThhhNhNubj)}(h**last_instr_end_off**h]hlast_instr_end_off}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubh, only apply to data or address instructions.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMUhjSubh)}(hWhen an operation cannot be handled as is by the NAND controller, it will be split by the parser into sub-operations which will be passed to the controller driver.h]hWhen an operation cannot be handled as is by the NAND controller, it will be split by the parser into sub-operations which will be passed to the controller driver.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMXhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*nand_op_parser_addr_constraints (C struct)!c.nand_op_parser_addr_constraintshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_parser_addr_constraintsh]j/)}(h&struct nand_op_parser_addr_constraintsh](j5)}(hj8h]hstruct}(hjUhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjUhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM_ubjG)}(h h]h }(hj%UhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjUhhhj$UhM_ubjX)}(hnand_op_parser_addr_constraintsh]j^)}(hjUh]hnand_op_parser_addr_constraints}(hj7UhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj3Uubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjUhhhj$UhM_ubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjUhhhj$UhM_ubah}(h]j Uah ](jjeh"]h$]h&]jj)jhuh1j(hj$UhM_hj Uhhubj)}(hhh]h)}(h$Constraints for address instructionsh]h$Constraints for address instructions}(hjYUhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMohjVUhhubah}(h]h ]h"]h$]h&]uh1jhj Uhhhj$UhM_ubeh}(h]h ](jstructeh"]h$]h&]jjjjqUjjqUjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_op_parser_addr_constraints { unsigned int maxcycles; }; **Members** ``maxcycles`` maximum number of address cycles the controller can issue in a single steph](j)}(hb**Definition**:: struct nand_op_parser_addr_constraints { unsigned int maxcycles; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}Uubh:}(hj}UhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMshjyUubjs)}(hIstruct nand_op_parser_addr_constraints { unsigned int maxcycles; };h]hIstruct nand_op_parser_addr_constraints { unsigned int maxcycles; };}hjUsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMuhjyUubeh}(h]h ]h"]h$]h&]uh1jhjUhMshjuUubh)}(h **Members**h]j)}(hjUh]hMembers}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMyhjuUubj )}(hhh]j)}(hX``maxcycles`` maximum number of address cycles the controller can issue in a single steph](j)}(h ``maxcycles``h]j)}(hjUh]h maxcycles}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMqhjUubj1)}(hhh]h)}(hJmaximum number of address cycles the controller can issue in a single steph]hJmaximum number of address cycles the controller can issue in a single step}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhMqhjUubah}(h]h ]h"]h$]h&]uh1j0hjUubeh}(h]h ]h"]h$]h&]uh1jhjUhMqhjUubah}(h]h ]h"]h$]h&]uh1j hjuUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*nand_op_parser_data_constraints (C struct)!c.nand_op_parser_data_constraintshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_parser_data_constraintsh]j/)}(h&struct nand_op_parser_data_constraintsh](j5)}(hj8h]hstruct}(hj)VhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj%Vhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMxubjG)}(h h]h }(hj7VhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj%Vhhhj6VhMxubjX)}(hnand_op_parser_data_constraintsh]j^)}(hj#Vh]hnand_op_parser_data_constraints}(hjIVhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjEVubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj%Vhhhj6VhMxubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj!Vhhhj6VhMxubah}(h]jVah ](jjeh"]h$]h&]jj)jhuh1j(hj6VhMxhjVhhubj)}(hhh]h)}(h!Constraints for data instructionsh]h!Constraints for data instructions}(hjkVhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMxhjhVhhubah}(h]h ]h"]h$]h&]uh1jhjVhhhj6VhMxubeh}(h]h ](jstructeh"]h$]h&]jjjjVjjVjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_op_parser_data_constraints { unsigned int maxlen; }; **Members** ``maxlen`` maximum data length that the controller can handle in a single steph](j)}(h_**Definition**:: struct nand_op_parser_data_constraints { unsigned int maxlen; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh:}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM|hjVubjs)}(hFstruct nand_op_parser_data_constraints { unsigned int maxlen; };h]hFstruct nand_op_parser_data_constraints { unsigned int maxlen; };}hjVsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM~hjVubeh}(h]h ]h"]h$]h&]uh1jhjVhM|hjVubh)}(h **Members**h]j)}(hjVh]hMembers}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjVubj )}(hhh]j)}(hN``maxlen`` maximum data length that the controller can handle in a single steph](j)}(h ``maxlen``h]j)}(hjVh]hmaxlen}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMyhjVubj1)}(hhh]h)}(hCmaximum data length that the controller can handle in a single steph]hCmaximum data length that the controller can handle in a single step}(hjVhhhNhNubah}(h]h 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Controller drivers should declare as many patterns as they support and pass this list of patterns (created with the help of the following macro) to the nand_op_parser_exec_op() helper.h](j)}(h**Definition**:: struct nand_op_parser_pattern { const struct nand_op_parser_pattern_elem *elems; unsigned int nelems; int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh:}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubjs)}(hstruct nand_op_parser_pattern { const struct nand_op_parser_pattern_elem *elems; unsigned int nelems; int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); };h]hstruct nand_op_parser_pattern { const struct nand_op_parser_pattern_elem *elems; unsigned int nelems; int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); };}hjYsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubeh}(h]h ]h"]h$]h&]uh1jhjYhMhjYubh)}(h **Members**h]j)}(hjYh]hMembers}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubj )}(hhh](j)}(h$``elems`` array of pattern elements h](j)}(h ``elems``h]j)}(hjYh]helems}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubj1)}(hhh]h)}(harray of pattern elementsh]harray of pattern elements}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhMhjZubah}(h]h ]h"]h$]h&]uh1j0hjYubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjYubj)}(h9``nelems`` number of pattern elements in **elems** array h](j)}(h ``nelems``h]j)}(hj%Zh]hnelems}(hj'ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#Zubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjZubj1)}(hhh]h)}(h-number of pattern elements in **elems** arrayh](hnumber of pattern elements in }(hj>ZhhhNhNubj)}(h **elems**h]helems}(hjFZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>Zubh array}(hj>ZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj:ZhMhj;Zubah}(h]h ]h"]h$]h&]uh1j0hjZubeh}(h]h ]h"]h$]h&]uh1jhj:ZhMhjYubj)}(h7``exec`` the function that will issue a sub-operation h](j)}(h``exec``h]j)}(hjpZh]hexec}(hjrZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnZubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjjZubj1)}(hhh]h)}(h,the function that will issue a sub-operationh]h,the function that will issue a sub-operation}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjZubah}(h]h ]h"]h$]h&]uh1j0hjjZubeh}(h]h ]h"]h$]h&]uh1jhjZhMhjYubeh}(h]h ]h"]h$]h&]uh1j hjYubh)}(h**Description**h]j)}(hjZh]h Description}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubh)}(hXA pattern is a list of elements, each element reprensenting one instruction with its constraints. The pattern itself is used by the core to match NAND chip operation with NAND controller operations. Once a match between a NAND controller operation pattern and a NAND chip operation (or a sub-set of a NAND operation) is found, the pattern ->exec() hook is called so that the controller driver can issue the operation on the bus.h]hXA pattern is a list of elements, each element reprensenting one instruction with its constraints. The pattern itself is used by the core to match NAND chip operation with NAND controller operations. Once a match between a NAND controller operation pattern and a NAND chip operation (or a sub-set of a NAND operation) is found, the pattern ->exec() hook is called so that the controller driver can issue the operation on the bus.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubh)}(hController drivers should declare as many patterns as they support and pass this list of patterns (created with the help of the following macro) to the nand_op_parser_exec_op() helper.h]hController drivers should declare as many patterns as they support and pass this list of patterns (created with the help of the following macro) to the nand_op_parser_exec_op() helper.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_op_parser (C struct)c.nand_op_parserhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_op_parserh]j/)}(hstruct nand_op_parserh](j5)}(hj8h]hstruct}(hj[hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjZhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj[hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjZhhhj [hMubjX)}(hnand_op_parserh]j^)}(hjZh]hnand_op_parser}(hj [hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj[ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjZhhhj [hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjZhhhj [hMubah}(h]jZah ](jjeh"]h$]h&]jj)jhuh1j(hj [hMhjZhhubj)}(hhh]h)}(h+NAND controller operation parser descriptorh]h+NAND controller operation parser descriptor}(hjB[hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj?[hhubah}(h]h ]h"]h$]h&]uh1jhjZhhhj [hMubeh}(h]h ](jstructeh"]h$]h&]jjjjZ[jjZ[jjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_op_parser { const struct nand_op_parser_pattern *patterns; unsigned int npatterns; }; **Members** ``patterns`` array of supported patterns ``npatterns`` length of the **patterns** array **Description** The parser descriptor is just an array of supported patterns which will be iterated by nand_op_parser_exec_op() everytime it tries to execute an NAND operation (or tries to determine if a specific operation is supported). It is worth mentioning that patterns will be tested in their declaration order, and the first match will be taken, so it's important to order patterns appropriately so that simple/inefficient patterns are placed at the end of the list. Usually, this is where you put single instruction patterns.h](j)}(h**Definition**:: struct nand_op_parser { const struct nand_op_parser_pattern *patterns; unsigned int npatterns; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf[ubh:}(hjf[hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjb[ubjs)}(hmstruct nand_op_parser { const struct nand_op_parser_pattern *patterns; unsigned int npatterns; };h]hmstruct nand_op_parser { const struct nand_op_parser_pattern *patterns; unsigned int npatterns; };}hj[sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjb[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMhj^[ubh)}(h **Members**h]j)}(hj[h]hMembers}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj^[ubj )}(hhh](j)}(h)``patterns`` array of supported patterns h](j)}(h ``patterns``h]j)}(hj[h]hpatterns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj[ubj1)}(hhh]h)}(harray of supported patternsh]harray of supported patterns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hMhj[ubah}(h]h ]h"]h$]h&]uh1j0hj[ubeh}(h]h ]h"]h$]h&]uh1jhj[hMhj[ubj)}(h0``npatterns`` length of the **patterns** array h](j)}(h ``npatterns``h]j)}(hj[h]h npatterns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj[ubj1)}(hhh]h)}(h length of the **patterns** arrayh](hlength of the }(hj \hhhNhNubj)}(h **patterns**h]hpatterns}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj \ubh array}(hj \hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubah}(h]h ]h"]h$]h&]uh1j0hj[ubeh}(h]h ]h"]h$]h&]uh1jhj\hMhj[ubeh}(h]h ]h"]h$]h&]uh1j hj^[ubh)}(h**Description**h]j)}(hj@\h]h Description}(hjB\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>\ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj^[ubh)}(hThe parser descriptor is just an array of supported patterns which will be iterated by nand_op_parser_exec_op() everytime it tries to execute an NAND operation (or tries to determine if a specific operation is supported).h]hThe parser descriptor is just an array of supported patterns which will be iterated by nand_op_parser_exec_op() everytime it tries to execute an NAND operation (or tries to determine if a specific operation is supported).}(hjV\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj^[ubh)}(hX'It is worth mentioning that patterns will be tested in their declaration order, and the first match will be taken, so it's important to order patterns appropriately so that simple/inefficient patterns are placed at the end of the list. Usually, this is where you put single instruction patterns.h]hX)It is worth mentioning that patterns will be tested in their declaration order, and the first match will be taken, so it’s important to order patterns appropriately so that simple/inefficient patterns are placed at the end of the list. Usually, this is where you put single instruction patterns.}(hje\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj^[ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_operation (C struct)c.nand_operationhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_operationh]j/)}(hstruct nand_operationh](j5)}(hj8h]hstruct}(hj\hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj\hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj\hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj\hhhj\hMubjX)}(hnand_operationh]j^)}(hj\h]hnand_operation}(hj\hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj\ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj\hhhj\hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj\hhhj\hMubah}(h]j\ah ](jjeh"]h$]h&]jj)jhuh1j(hj\hMhj\hhubj)}(hhh]h)}(hNAND operation descriptorh]hNAND operation descriptor}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\hhubah}(h]h ]h"]h$]h&]uh1jhj\hhhj\hMubeh}(h]h ](jstructeh"]h$]h&]jjjj\jj\jjjuh1j#hhhjhNhNubj)}(hX$ **Definition**:: struct nand_operation { unsigned int cs; bool deassert_wp; const struct nand_op_instr *instrs; unsigned int ninstrs; }; **Members** ``cs`` the CS line to select for this NAND operation ``deassert_wp`` set to true when the operation requires the WP pin to be de-asserted (ERASE, PROG, ...) ``instrs`` array of instructions to execute ``ninstrs`` length of the **instrs** array **Description** The actual operation structure that will be passed to chip->exec_op().h](j)}(h**Definition**:: struct nand_operation { unsigned int cs; bool deassert_wp; const struct nand_op_instr *instrs; unsigned int ninstrs; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh:}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubjs)}(hstruct nand_operation { unsigned int cs; bool deassert_wp; const struct nand_op_instr *instrs; unsigned int ninstrs; };h]hstruct nand_operation { unsigned int cs; bool deassert_wp; const struct nand_op_instr *instrs; unsigned int ninstrs; };}hj]sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubeh}(h]h ]h"]h$]h&]uh1jhj]hMhj\ubh)}(h **Members**h]j)}(hj.]h]hMembers}(hj0]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,]ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubj )}(hhh](j)}(h5``cs`` the CS line to select for this NAND operation h](j)}(h``cs``h]j)}(hjM]h]hcs}(hjO]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK]ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjG]ubj1)}(hhh]h)}(h-the CS line to select for this NAND operationh]h-the CS line to select for this NAND operation}(hjf]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb]hMhjc]ubah}(h]h ]h"]h$]h&]uh1j0hjG]ubeh}(h]h ]h"]h$]h&]uh1jhjb]hMhjD]ubj)}(hh``deassert_wp`` set to true when the operation requires the WP pin to be de-asserted (ERASE, PROG, ...) h](j)}(h``deassert_wp``h]j)}(hj]h]h deassert_wp}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj]ubj1)}(hhh]h)}(hWset to true when the operation requires the WP pin to be de-asserted (ERASE, PROG, ...)h]hWset to true when the operation requires the WP pin to be de-asserted (ERASE, PROG, ...)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj]ubah}(h]h ]h"]h$]h&]uh1j0hj]ubeh}(h]h ]h"]h$]h&]uh1jhj]hMhjD]ubj)}(h,``instrs`` array of instructions to execute h](j)}(h ``instrs``h]j)}(hj]h]hinstrs}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj]ubj1)}(hhh]h)}(h array of instructions to executeh]h array of instructions to execute}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hMhj]ubah}(h]h ]h"]h$]h&]uh1j0hj]ubeh}(h]h ]h"]h$]h&]uh1jhj]hMhjD]ubj)}(h,``ninstrs`` length of the **instrs** array h](j)}(h ``ninstrs``h]j)}(hj]h]hninstrs}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj]ubj1)}(hhh]h)}(hlength of the **instrs** arrayh](hlength of the }(hj^hhhNhNubj)}(h **instrs**h]hinstrs}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubh array}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj^ubah}(h]h ]h"]h$]h&]uh1j0hj]ubeh}(h]h ]h"]h$]h&]uh1jhj^hMhjD]ubeh}(h]h ]h"]h$]h&]uh1j hj\ubh)}(h**Description**h]j)}(hjG^h]h Description}(hjI^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE^ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubh)}(hFThe actual operation structure that will be passed to chip->exec_op().h]hFThe actual operation structure that will be passed to chip->exec_op().}(hj]^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_controller_ops (C struct)c.nand_controller_opshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_controller_opsh]j/)}(hstruct nand_controller_opsh](j5)}(hj8h]hstruct}(hj^hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj^hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj^hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj^hhhj^hMubjX)}(hnand_controller_opsh]j^)}(hj^h]hnand_controller_ops}(hj^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj^ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj^hhhj^hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj^hhhj^hMubah}(h]j^ah ](jjeh"]h$]h&]jj)jhuh1j(hj^hMhj^hhubj)}(hhh]h)}(hController operationsh]hController operations}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM4hj^hhubah}(h]h ]h"]h$]h&]uh1jhj^hhhj^hMubeh}(h]h ](jstructeh"]h$]h&]jjjj^jj^jjjuh1j#hhhjhNhNubj)}(hX  **Definition**:: struct nand_controller_ops { int (*attach_chip)(struct nand_chip *chip); void (*detach_chip)(struct nand_chip *chip); int (*exec_op)(struct nand_chip *chip, const struct nand_operation *op, bool check_only); int (*setup_interface)(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf); }; **Members** ``attach_chip`` this method is called after the NAND detection phase after flash ID and MTD fields such as erase size, page size and OOB size have been set up. ECC requirements are available if provided by the NAND chip or device tree. Typically used to choose the appropriate ECC configuration and allocate associated resources. This hook is optional. ``detach_chip`` free all resources allocated/claimed in nand_controller_ops->attach_chip(). This hook is optional. ``exec_op`` controller specific method to execute NAND operations. This method replaces chip->legacy.cmdfunc(), chip->legacy.{read,write}_{buf,byte,word}(), chip->legacy.dev_ready() and chip->legacy.waitfunc(). ``setup_interface`` setup the data interface and timing. If chipnr is set to ``NAND_DATA_IFACE_CHECK_ONLY`` this means the configuration should not be applied but only checked. This hook is optional.h](j)}(hXo**Definition**:: struct nand_controller_ops { int (*attach_chip)(struct nand_chip *chip); void (*detach_chip)(struct nand_chip *chip); int (*exec_op)(struct nand_chip *chip, const struct nand_operation *op, bool check_only); int (*setup_interface)(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf); }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubh:}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM8hj^ubjs)}(hXPstruct nand_controller_ops { int (*attach_chip)(struct nand_chip *chip); void (*detach_chip)(struct nand_chip *chip); int (*exec_op)(struct nand_chip *chip, const struct nand_operation *op, bool check_only); int (*setup_interface)(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf); };h]hXPstruct nand_controller_ops { int (*attach_chip)(struct nand_chip *chip); void (*detach_chip)(struct nand_chip *chip); int (*exec_op)(struct nand_chip *chip, const struct nand_operation *op, bool check_only); int (*setup_interface)(struct nand_chip *chip, int chipnr, const struct nand_interface_config *conf); };}hj_sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM:hj^ubeh}(h]h ]h"]h$]h&]uh1jhj_hM8hj^ubh)}(h **Members**h]j)}(hj&_h]hMembers}(hj(_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$_ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMAhj^ubj )}(hhh](j)}(hXa``attach_chip`` this method is called after the NAND detection phase after flash ID and MTD fields such as erase size, page size and OOB size have been set up. ECC requirements are available if provided by the NAND chip or device tree. Typically used to choose the appropriate ECC configuration and allocate associated resources. This hook is optional. h](j)}(h``attach_chip``h]j)}(hjE_h]h attach_chip}(hjG_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC_ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM=hj?_ubj1)}(hhh]h)}(hXPthis method is called after the NAND detection phase after flash ID and MTD fields such as erase size, page size and OOB size have been set up. ECC requirements are available if provided by the NAND chip or device tree. Typically used to choose the appropriate ECC configuration and allocate associated resources. This hook is optional.h]hXPthis method is called after the NAND detection phase after flash ID and MTD fields such as erase size, page size and OOB size have been set up. ECC requirements are available if provided by the NAND chip or device tree. Typically used to choose the appropriate ECC configuration and allocate associated resources. This hook is optional.}(hj^_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM7hj[_ubah}(h]h ]h"]h$]h&]uh1j0hj?_ubeh}(h]h ]h"]h$]h&]uh1jhjZ_hM=hj<_ubj)}(hs``detach_chip`` free all resources allocated/claimed in nand_controller_ops->attach_chip(). This hook is optional. h](j)}(h``detach_chip``h]j)}(hj_h]h detach_chip}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}_ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM@hjy_ubj1)}(hhh]h)}(hbfree all resources allocated/claimed in nand_controller_ops->attach_chip(). This hook is optional.h]hbfree all resources allocated/claimed in nand_controller_ops->attach_chip(). This hook is optional.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM>hj_ubah}(h]h ]h"]h$]h&]uh1j0hjy_ubeh}(h]h ]h"]h$]h&]uh1jhj_hM@hj<_ubj)}(h``exec_op`` controller specific method to execute NAND operations. This method replaces chip->legacy.cmdfunc(), chip->legacy.{read,write}_{buf,byte,word}(), chip->legacy.dev_ready() and chip->legacy.waitfunc(). h](j)}(h ``exec_op``h]j)}(hj_h]hexec_op}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMDhj_ubj1)}(hhh]h)}(hcontroller specific method to execute NAND operations. This method replaces chip->legacy.cmdfunc(), chip->legacy.{read,write}_{buf,byte,word}(), chip->legacy.dev_ready() and chip->legacy.waitfunc().h]hcontroller specific method to execute NAND operations. This method replaces chip->legacy.cmdfunc(), chip->legacy.{read,write}_{buf,byte,word}(), chip->legacy.dev_ready() and chip->legacy.waitfunc().}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMAhj_ubah}(h]h ]h"]h$]h&]uh1j0hj_ubeh}(h]h ]h"]h$]h&]uh1jhj_hMDhj<_ubj)}(h``setup_interface`` setup the data interface and timing. If chipnr is set to ``NAND_DATA_IFACE_CHECK_ONLY`` this means the configuration should not be applied but only checked. This hook is optional.h](j)}(h``setup_interface``h]j)}(hj_h]hsetup_interface}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMGhj_ubj1)}(hhh]h)}(hsetup the data interface and timing. If chipnr is set to ``NAND_DATA_IFACE_CHECK_ONLY`` this means the configuration should not be applied but only checked. This hook is optional.h](h9setup the data interface and timing. If chipnr is set to }(hj `hhhNhNubj)}(h``NAND_DATA_IFACE_CHECK_ONLY``h]hNAND_DATA_IFACE_CHECK_ONLY}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj `ubh\ this means the configuration should not be applied but only checked. This hook is optional.}(hj `hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMEhj `ubah}(h]h ]h"]h$]h&]uh1j0hj_ubeh}(h]h ]h"]h$]h&]uh1jhj`hMGhj<_ubeh}(h]h ]h"]h$]h&]uh1j hj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_controller (C struct)c.nand_controllerhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_controllerh]j/)}(hstruct nand_controllerh](j5)}(hj8h]hstruct}(hj_`hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hj[`hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMNubjG)}(h h]h }(hjm`hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj[`hhhjl`hMNubjX)}(hnand_controllerh]j^)}(hjY`h]hnand_controller}(hj`hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj{`ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj[`hhhjl`hMNubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjW`hhhjl`hMNubah}(h]jR`ah ](jjeh"]h$]h&]jj)jhuh1j(hjl`hMNhjT`hhubj)}(hhh]h)}(h,Structure used to describe a NAND controllerh]h,Structure used to describe a NAND controller}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMThj`hhubah}(h]h ]h"]h$]h&]uh1jhjT`hhhjl`hMNubeh}(h]h ](jstructeh"]h$]h&]jjjj`jj`jjjuh1j#hhhjhNhNubj)}(hXV **Definition**:: struct nand_controller { struct mutex lock; const struct nand_controller_ops *ops; struct { unsigned int data_only_read: 1; unsigned int cont_read: 1; } supported_op; bool controller_wp; }; **Members** ``lock`` lock used to serialize accesses to the NAND controller ``ops`` NAND controller operations. ``supported_op`` NAND controller known-to-be-supported operations, only writable by the core after initial checking. ``supported_op.data_only_read`` The controller supports reading more data from the bus without restarting an entire read operation nor changing the column. ``supported_op.cont_read`` The controller supports sequential cache reads. ``controller_wp`` the controller is in charge of handling the WP pin.h](j)}(hX**Definition**:: struct nand_controller { struct mutex lock; const struct nand_controller_ops *ops; struct { unsigned int data_only_read: 1; unsigned int cont_read: 1; } supported_op; bool controller_wp; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubh:}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMXhj`ubjs)}(hstruct nand_controller { struct mutex lock; const struct nand_controller_ops *ops; struct { unsigned int data_only_read: 1; unsigned int cont_read: 1; } supported_op; bool controller_wp; };h]hstruct nand_controller { struct mutex lock; const struct nand_controller_ops *ops; struct { unsigned int data_only_read: 1; unsigned int cont_read: 1; } supported_op; bool controller_wp; };}hj`sbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMZhj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMXhj`ubh)}(h **Members**h]j)}(hj`h]hMembers}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMdhj`ubj )}(hhh](j)}(h@``lock`` lock used to serialize accesses to the NAND controller h](j)}(h``lock``h]j)}(hjah]hlock}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMWhjaubj1)}(hhh]h)}(h6lock used to serialize accesses to the NAND controllerh]h6lock used to serialize accesses to the NAND controller}(hj1ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-ahMWhj.aubah}(h]h ]h"]h$]h&]uh1j0hjaubeh}(h]h ]h"]h$]h&]uh1jhj-ahMWhjaubj)}(h$``ops`` NAND controller operations. h](j)}(h``ops``h]j)}(hjQah]hops}(hjSahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOaubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMXhjKaubj1)}(hhh]h)}(hNAND controller operations.h]hNAND controller operations.}(hjjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfahMXhjgaubah}(h]h ]h"]h$]h&]uh1j0hjKaubeh}(h]h ]h"]h$]h&]uh1jhjfahMXhjaubj)}(hu``supported_op`` NAND controller known-to-be-supported operations, only writable by the core after initial checking. h](j)}(h``supported_op``h]j)}(hjah]h supported_op}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMZhjaubj1)}(hhh]h)}(hcNAND controller known-to-be-supported operations, only writable by the core after initial checking.h]hcNAND controller known-to-be-supported operations, only writable by the core after initial checking.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMYhjaubah}(h]h ]h"]h$]h&]uh1j0hjaubeh}(h]h ]h"]h$]h&]uh1jhjahMZhjaubj)}(h``supported_op.data_only_read`` The controller supports reading more data from the bus without restarting an entire read operation nor changing the column. h](j)}(h``supported_op.data_only_read``h]j)}(hjah]hsupported_op.data_only_read}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM]hjaubj1)}(hhh]h)}(h{The controller supports reading more data from the bus without restarting an entire read operation nor changing the column.h]h{The controller supports reading more data from the bus without restarting an entire read operation nor changing the column.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hjaubah}(h]h ]h"]h$]h&]uh1j0hjaubeh}(h]h ]h"]h$]h&]uh1jhjahM]hjaubj)}(hK``supported_op.cont_read`` The controller supports sequential cache reads. h](j)}(h``supported_op.cont_read``h]j)}(hjah]hsupported_op.cont_read}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM^hjaubj1)}(hhh]h)}(h/The controller supports sequential cache reads.h]h/The controller supports sequential cache reads.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhM^hjbubah}(h]h ]h"]h$]h&]uh1j0hjaubeh}(h]h ]h"]h$]h&]uh1jhjbhM^hjaubj)}(hE``controller_wp`` the controller is in charge of handling the WP pin.h](j)}(h``controller_wp``h]j)}(hj7bh]h controller_wp}(hj9bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5bubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM^hj1bubj1)}(hhh]h)}(h3the controller is in charge of handling the WP pin.h]h3the controller is in charge of handling the WP pin.}(hjPbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM_hjMbubah}(h]h ]h"]h$]h&]uh1j0hj1bubeh}(h]h ]h"]h$]h&]uh1jhjLbhM^hjaubeh}(h]h ]h"]h$]h&]uh1j hj`ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_legacy (C struct) c.nand_legacyhNtauh1jhjhhhNhNubj$)}(hhh](j))}(h nand_legacyh]j/)}(hstruct nand_legacyh](j5)}(hj8h]hstruct}(hjbhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjbhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMeubjG)}(h h]h }(hjbhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjbhhhjbhMeubjX)}(h nand_legacyh]j^)}(hjbh]h nand_legacy}(hjbhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjbubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjbhhhjbhMeubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjbhhhjbhMeubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1j(hjbhMehjbhhubj)}(hhh]h)}(hNAND chip legacy fields/hooksh]hNAND chip legacy fields/hooks}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMphjbhhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjbhMeubeh}(h]h ](jstructeh"]h$]h&]jjjjbjjbjjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_legacy { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; void (*select_chip)(struct nand_chip *chip, int cs); u8 (*read_byte)(struct nand_chip *chip); void (*write_byte)(struct nand_chip *chip, u8 byte); void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, int page_addr); int (*dev_ready)(struct nand_chip *chip); int (*waitfunc)(struct nand_chip *chip); int (*block_bad)(struct nand_chip *chip, loff_t ofs); int (*block_markbad)(struct nand_chip *chip, loff_t ofs); int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int (*get_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int chip_delay; struct nand_controller dummy_controller; }; **Members** ``IO_ADDR_R`` address to read the 8 I/O lines of the flash device ``IO_ADDR_W`` address to write the 8 I/O lines of the flash device ``select_chip`` select/deselect a specific target/die ``read_byte`` read one byte from the chip ``write_byte`` write a single byte to the chip on the low 8 I/O lines ``write_buf`` write data from the buffer to the chip ``read_buf`` read data from the chip into the buffer ``cmd_ctrl`` hardware specific function for controlling ALE/CLE/nCE. Also used to write command and address ``cmdfunc`` hardware specific function for writing commands to the chip. ``dev_ready`` hardware specific function for accessing device ready/busy line. If set to NULL no access to ready/busy is available and the ready/busy information is read from the chip status register. ``waitfunc`` hardware specific function for wait on ready. ``block_bad`` check if a block is bad, using OOB markers ``block_markbad`` mark a block bad ``set_features`` set the NAND chip features ``get_features`` get the NAND chip features ``chip_delay`` chip dependent delay for transferring data from array to read regs (tR). ``dummy_controller`` dummy controller implementation for drivers that can only control a single chip **Description** If you look at this structure you're already wrong. These fields/hooks are all deprecated.h](j)}(hX:**Definition**:: struct nand_legacy { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; void (*select_chip)(struct nand_chip *chip, int cs); u8 (*read_byte)(struct nand_chip *chip); void (*write_byte)(struct nand_chip *chip, u8 byte); void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, int page_addr); int (*dev_ready)(struct nand_chip *chip); int (*waitfunc)(struct nand_chip *chip); int (*block_bad)(struct nand_chip *chip, loff_t ofs); int (*block_markbad)(struct nand_chip *chip, loff_t ofs); int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int (*get_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int chip_delay; struct nand_controller dummy_controller; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubh:}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMthjbubjs)}(hXstruct nand_legacy { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; void (*select_chip)(struct nand_chip *chip, int cs); u8 (*read_byte)(struct nand_chip *chip); void (*write_byte)(struct nand_chip *chip, u8 byte); void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, int page_addr); int (*dev_ready)(struct nand_chip *chip); int (*waitfunc)(struct nand_chip *chip); int (*block_bad)(struct nand_chip *chip, loff_t ofs); int (*block_markbad)(struct nand_chip *chip, loff_t ofs); int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int (*get_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int chip_delay; struct nand_controller dummy_controller; };h]hXstruct nand_legacy { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; void (*select_chip)(struct nand_chip *chip, int cs); u8 (*read_byte)(struct nand_chip *chip); void (*write_byte)(struct nand_chip *chip, u8 byte); void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, int page_addr); int (*dev_ready)(struct nand_chip *chip); int (*waitfunc)(struct nand_chip *chip); int (*block_bad)(struct nand_chip *chip, loff_t ofs); int (*block_markbad)(struct nand_chip *chip, loff_t ofs); int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int (*get_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int chip_delay; struct nand_controller dummy_controller; };}hjcsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMvhjbubeh}(h]h ]h"]h$]h&]uh1jhjchMthjbubh)}(h **Members**h]j)}(hj+ch]hMembers}(hj-chhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)cubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjbubj )}(hhh](j)}(hB``IO_ADDR_R`` address to read the 8 I/O lines of the flash device h](j)}(h ``IO_ADDR_R``h]j)}(hjJch]h IO_ADDR_R}(hjLchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHcubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMrhjDcubj1)}(hhh]h)}(h3address to read the 8 I/O lines of the flash deviceh]h3address to read the 8 I/O lines of the flash device}(hjcchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_chMrhj`cubah}(h]h ]h"]h$]h&]uh1j0hjDcubeh}(h]h ]h"]h$]h&]uh1jhj_chMrhjAcubj)}(hC``IO_ADDR_W`` address to write the 8 I/O lines of the flash device h](j)}(h ``IO_ADDR_W``h]j)}(hjch]h IO_ADDR_W}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMshj}cubj1)}(hhh]h)}(h4address to write the 8 I/O lines of the flash deviceh]h4address to write the 8 I/O lines of the flash device}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMshjcubah}(h]h ]h"]h$]h&]uh1j0hj}cubeh}(h]h ]h"]h$]h&]uh1jhjchMshjAcubj)}(h6``select_chip`` select/deselect a specific target/die h](j)}(h``select_chip``h]j)}(hjch]h select_chip}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMthjcubj1)}(hhh]h)}(h%select/deselect a specific target/dieh]h%select/deselect a specific target/die}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMthjcubah}(h]h ]h"]h$]h&]uh1j0hjcubeh}(h]h ]h"]h$]h&]uh1jhjchMthjAcubj)}(h*``read_byte`` read one byte from the chip h](j)}(h ``read_byte``h]j)}(hjch]h read_byte}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMuhjcubj1)}(hhh]h)}(hread one byte from the chiph]hread one byte from the chip}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj dhMuhj dubah}(h]h ]h"]h$]h&]uh1j0hjcubeh}(h]h ]h"]h$]h&]uh1jhj dhMuhjAcubj)}(hF``write_byte`` write a single byte to the chip on the low 8 I/O lines h](j)}(h``write_byte``h]j)}(hj.dh]h write_byte}(hj0dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,dubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMvhj(dubj1)}(hhh]h)}(h6write a single byte to the chip on the low 8 I/O linesh]h6write a single byte to the chip on the low 8 I/O lines}(hjGdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjCdhMvhjDdubah}(h]h ]h"]h$]h&]uh1j0hj(dubeh}(h]h ]h"]h$]h&]uh1jhjCdhMvhjAcubj)}(h5``write_buf`` write data from the buffer to the chip h](j)}(h ``write_buf``h]j)}(hjgdh]h write_buf}(hjidhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjedubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMwhjadubj1)}(hhh]h)}(h&write data from the buffer to the chiph]h&write data from the buffer to the chip}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|dhMwhj}dubah}(h]h ]h"]h$]h&]uh1j0hjadubeh}(h]h ]h"]h$]h&]uh1jhj|dhMwhjAcubj)}(h5``read_buf`` read data from the chip into the buffer h](j)}(h ``read_buf``h]j)}(hjdh]hread_buf}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMxhjdubj1)}(hhh]h)}(h'read data from the chip into the bufferh]h'read data from the chip into the buffer}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhMxhjdubah}(h]h ]h"]h$]h&]uh1j0hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMxhjAcubj)}(hl``cmd_ctrl`` hardware specific function for controlling ALE/CLE/nCE. Also used to write command and address h](j)}(h ``cmd_ctrl``h]j)}(hjdh]hcmd_ctrl}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMzhjdubj1)}(hhh]h)}(h^hardware specific function for controlling ALE/CLE/nCE. Also used to write command and addressh]h^hardware specific function for controlling ALE/CLE/nCE. Also used to write command and address}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMyhjdubah}(h]h ]h"]h$]h&]uh1j0hjdubeh}(h]h ]h"]h$]h&]uh1jhjdhMzhjAcubj)}(hI``cmdfunc`` hardware specific function for writing commands to the chip. h](j)}(h ``cmdfunc``h]j)}(hjeh]hcmdfunc}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM{hj eubj1)}(hhh]h)}(hjubj)}(h8``priv`` Private information for the manufacturer driverh](j)}(h``priv``h]j)}(hjjh]hpriv}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~jubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjzjubj1)}(hhh]h)}(h/Private information for the manufacturer driverh]h/Private information for the manufacturer driver}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjjubah}(h]h ]h"]h$]h&]uh1j0hjzjubeh}(h]h ]h"]h$]h&]uh1jhjjhMhj>jubeh}(h]h ]h"]h$]h&]uh1j hjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_secure_region (C struct)c.nand_secure_regionhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_secure_regionh]j/)}(hstruct nand_secure_regionh](j5)}(hj8h]hstruct}(hjjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjjhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hjjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjjhhhjjhMubjX)}(hnand_secure_regionh]j^)}(hjjh]hnand_secure_region}(hjjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjjubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjjhhhjjhMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjjhhhjjhMubah}(h]jjah ](jjeh"]h$]h&]jj)jhuh1j(hjjhMhjjhhubj)}(hhh]h)}(hNAND secure region structureh]hNAND secure region structure}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjkhhubah}(h]h ]h"]h$]h&]uh1jhjjhhhjjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj4kjj4kjjjuh1j#hhhjhNhNubj)}(h **Definition**:: struct nand_secure_region { u64 offset; u64 size; }; **Members** ``offset`` Offset of the start of the secure region ``size`` Size of the secure regionh](j)}(h[**Definition**:: struct nand_secure_region { u64 offset; u64 size; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjDkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@kubh:}(hj@khhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj= 0 && cur_cs < nanddev_ntargets(). NAND Controller drivers should not modify this value, but they're allowed to read it. ``read_retries`` The number of read retry modes supported ``secure_regions`` Structure containing the secure regions info ``nr_secure_regions`` Number of secure regions ``cont_read`` Sequential page read internals ``cont_read.ongoing`` Whether a continuous read is ongoing or not ``cont_read.first_page`` Start of the continuous read operation ``cont_read.pause_page`` End of the current sequential cache read operation ``cont_read.last_page`` End of the continuous read operation ``controller`` The hardware controller structure which is shared among multiple independent devices ``ecc`` The ECC controller structure ``priv`` Chip private datah](j)}(hX**Definition**:: struct nand_chip { struct nand_device base; struct nand_id id; struct nand_parameters parameters; struct nand_manufacturer manufacturer; struct nand_chip_ops ops; struct nand_legacy legacy; unsigned int options; const struct nand_interface_config *current_interface_config; struct nand_interface_config *best_interface_config; unsigned int bbt_erase_shift; unsigned int bbt_options; unsigned int badblockpos; unsigned int badblockbits; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; u8 *bbt; unsigned int page_shift; unsigned int phys_erase_shift; unsigned int chip_shift; unsigned int pagemask; unsigned int subpagesize; u8 *data_buf; u8 *oob_poi; struct { unsigned int bitflips; int page; } pagecache; unsigned long buf_align; struct mutex lock; unsigned int suspended : 1; wait_queue_head_t resume_wq; int cur_cs; int read_retries; struct nand_secure_region *secure_regions; u8 nr_secure_regions; struct { bool ongoing; unsigned int first_page; unsigned int pause_page; unsigned int last_page; } cont_read; struct nand_controller *controller; struct nand_ecc_ctrl ecc; void *priv; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubh:}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjlubjs)}(hXstruct nand_chip { struct nand_device base; struct nand_id id; struct nand_parameters parameters; struct nand_manufacturer manufacturer; struct nand_chip_ops ops; struct nand_legacy legacy; unsigned int options; const struct nand_interface_config *current_interface_config; struct nand_interface_config *best_interface_config; unsigned int bbt_erase_shift; unsigned int bbt_options; unsigned int badblockpos; unsigned int badblockbits; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; u8 *bbt; unsigned int page_shift; unsigned int phys_erase_shift; unsigned int chip_shift; unsigned int pagemask; unsigned int subpagesize; u8 *data_buf; u8 *oob_poi; struct { unsigned int bitflips; int page; } pagecache; unsigned long buf_align; struct mutex lock; unsigned int suspended : 1; wait_queue_head_t resume_wq; int cur_cs; int read_retries; struct nand_secure_region *secure_regions; u8 nr_secure_regions; struct { bool ongoing; unsigned int first_page; unsigned int pause_page; unsigned int last_page; } cont_read; struct nand_controller *controller; struct nand_ecc_ctrl ecc; void *priv; };h]hXstruct nand_chip { struct nand_device base; struct nand_id id; struct nand_parameters parameters; struct nand_manufacturer manufacturer; struct nand_chip_ops ops; struct nand_legacy legacy; unsigned int options; const struct nand_interface_config *current_interface_config; struct nand_interface_config *best_interface_config; unsigned int bbt_erase_shift; unsigned int bbt_options; unsigned int badblockpos; unsigned int badblockbits; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; u8 *bbt; unsigned int page_shift; unsigned int phys_erase_shift; unsigned int chip_shift; unsigned int pagemask; unsigned int subpagesize; u8 *data_buf; u8 *oob_poi; struct { unsigned int bitflips; int page; } pagecache; unsigned long buf_align; struct mutex lock; unsigned int suspended : 1; wait_queue_head_t resume_wq; int cur_cs; int read_retries; struct nand_secure_region *secure_regions; u8 nr_secure_regions; struct { bool ongoing; unsigned int first_page; unsigned int pause_page; unsigned int last_page; } cont_read; struct nand_controller *controller; struct nand_ecc_ctrl ecc; void *priv; };}hjlsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMhjlubh)}(h **Members**h]j)}(hjlh]hMembers}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjlubj )}(hhh](j)}(h.``base`` Inherit from the generic NAND device h](j)}(h``base``h]j)}(hjlh]hbase}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjlubj1)}(hhh]h)}(h$Inherit from the generic NAND deviceh]h$Inherit from the generic NAND device}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhMhjlubah}(h]h ]h"]h$]h&]uh1j0hjlubeh}(h]h ]h"]h$]h&]uh1jhjlhMhjlubj)}(h``id`` Holds NAND ID h](j)}(h``id``h]j)}(hjmh]hid}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjmubj1)}(hhh]h)}(h Holds NAND IDh]h Holds NAND ID}(hj1mhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-mhMhj.mubah}(h]h ]h"]h$]h&]uh1j0hjmubeh}(h]h ]h"]h$]h&]uh1jhj-mhMhjlubj)}(hF``parameters`` Holds generic parameters under an easily readable form h](j)}(h``parameters``h]j)}(hjQmh]h parameters}(hjSmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjKmubj1)}(hhh]h)}(h6Holds generic parameters under an easily readable formh]h6Holds generic parameters under an easily readable form}(hjjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfmhMhjgmubah}(h]h ]h"]h$]h&]uh1j0hjKmubeh}(h]h ]h"]h$]h&]uh1jhjfmhMhjlubj)}(h*``manufacturer`` Manufacturer information h](j)}(h``manufacturer``h]j)}(hjmh]h manufacturer}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjmubj1)}(hhh]h)}(hManufacturer informationh]hManufacturer information}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjmubah}(h]h ]h"]h$]h&]uh1j0hjmubeh}(h]h ]h"]h$]h&]uh1jhjmhMhjlubj)}(h``ops`` NAND chip operations h](j)}(h``ops``h]j)}(hjmh]hops}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjmubj1)}(hhh]h)}(hNAND chip operationsh]hNAND chip operations}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhMhjmubah}(h]h ]h"]h$]h&]uh1j0hjmubeh}(h]h ]h"]h$]h&]uh1jhjmhMhjlubj)}(h``legacy`` All legacy fields/hooks. If you develop a new driver, don't even try to use any of these fields/hooks, and if you're modifying an existing driver that is using those fields/hooks, you should consider reworking the driver and avoid using them. h](j)}(h ``legacy``h]j)}(hjmh]hlegacy}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjmubj1)}(hhh]h)}(hAll legacy fields/hooks. If you develop a new driver, don't even try to use any of these fields/hooks, and if you're modifying an existing driver that is using those fields/hooks, you should consider reworking the driver and avoid using them.h]hAll legacy fields/hooks. If you develop a new driver, don’t even try to use any of these fields/hooks, and if you’re modifying an existing driver that is using those fields/hooks, you should consider reworking the driver and avoid using them.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjnubah}(h]h ]h"]h$]h&]uh1j0hjmubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjlubj)}(h``options`` Various chip options. They can partly be set to inform nand_scan about special functionality. See the defines for further explanation. h](j)}(h ``options``h]j)}(hj6nh]hoptions}(hj8nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4nubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj0nubj1)}(hhh]h)}(hVarious chip options. They can partly be set to inform nand_scan about special functionality. See the defines for further explanation.h]hVarious chip options. They can partly be set to inform nand_scan about special functionality. See the defines for further explanation.}(hjOnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjLnubah}(h]h ]h"]h$]h&]uh1j0hj0nubeh}(h]h ]h"]h$]h&]uh1jhjKnhMhjlubj)}(hM``current_interface_config`` The currently used NAND interface configuration h](j)}(h``current_interface_config``h]j)}(hjpnh]hcurrent_interface_config}(hjrnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnnubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjjnubj1)}(hhh]h)}(h/The currently used NAND interface configurationh]h/The currently used NAND interface configuration}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1j0hjjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjlubj)}(h``best_interface_config`` The best NAND interface configuration which fits both the NAND chip and NAND controller constraints. If unset, the default reset interface configuration must be used. h](j)}(h``best_interface_config``h]j)}(hjnh]hbest_interface_config}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjnubj1)}(hhh]h)}(hThe best NAND interface configuration which fits both the NAND chip and NAND controller constraints. If unset, the default reset interface configuration must be used.h]hThe best NAND interface configuration which fits both the NAND chip and NAND controller constraints. If unset, the default reset interface configuration must be used.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjnubah}(h]h ]h"]h$]h&]uh1j0hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjlubj)}(h:``bbt_erase_shift`` Number of address bits in a bbt entry h](j)}(h``bbt_erase_shift``h]j)}(hjnh]hbbt_erase_shift}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjnubj1)}(hhh]h)}(h%Number of address bits in a bbt entryh]h%Number of address bits in a bbt entry}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjnubah}(h]h ]h"]h$]h&]uh1j0hjnubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjlubj)}(h``bbt_options`` Bad block table specific options. All options used here must come from bbm.h. By default, these options will be copied to the appropriate nand_bbt_descr's. h](j)}(h``bbt_options``h]j)}(hjoh]h bbt_options}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoubj1)}(hhh]h)}(hBad block table specific options. All options used here must come from bbm.h. By default, these options will be copied to the appropriate nand_bbt_descr's.h]hBad block table specific options. All options used here must come from bbm.h. By default, these options will be copied to the appropriate nand_bbt_descr’s.}(hj5ohhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj2oubah}(h]h ]h"]h$]h&]uh1j0hjoubeh}(h]h ]h"]h$]h&]uh1jhj1ohMhjlubj)}(h:``badblockpos`` Bad block marker position in the oob area h](j)}(h``badblockpos``h]j)}(hjVoh]h badblockpos}(hjXohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjToubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjPoubj1)}(hhh]h)}(h)Bad block marker position in the oob areah]h)Bad block marker position in the oob area}(hjoohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkohMhjloubah}(h]h ]h"]h$]h&]uh1j0hjPoubeh}(h]h ]h"]h$]h&]uh1jhjkohMhjlubj)}(h``badblockbits`` Minimum number of set bits in a good block's bad block marker position; i.e., BBM = 11110111b is good when badblockbits = 7 h](j)}(h``badblockbits``h]j)}(hjoh]h badblockbits}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoubj1)}(hhh]h)}(h{Minimum number of set bits in a good block's bad block marker position; i.e., BBM = 11110111b is good when badblockbits = 7h]h}Minimum number of set bits in a good block’s bad block marker position; i.e., BBM = 11110111b is good when badblockbits = 7}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoubah}(h]h ]h"]h$]h&]uh1j0hjoubeh}(h]h ]h"]h$]h&]uh1jhjohMhjlubj)}(h7``bbt_td`` Bad block table descriptor for flash lookup h](j)}(h ``bbt_td``h]j)}(hjoh]hbbt_td}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoubj1)}(hhh]h)}(h+Bad block table descriptor for flash lookuph]h+Bad block table descriptor for flash lookup}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohMhjoubah}(h]h ]h"]h$]h&]uh1j0hjoubeh}(h]h ]h"]h$]h&]uh1jhjohMhjlubj)}(h-``bbt_md`` Bad block table mirror descriptor h](j)}(h ``bbt_md``h]j)}(hjph]hbbt_md}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjoubj1)}(hhh]h)}(h!Bad block table mirror descriptorh]h!Bad block table mirror descriptor}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjpubah}(h]h ]h"]h$]h&]uh1j0hjoubeh}(h]h ]h"]h$]h&]uh1jhjphMhjlubj)}(hL``badblock_pattern`` Bad block scan pattern used for initial bad block scan h](j)}(h``badblock_pattern``h]j)}(hj;ph]hbadblock_pattern}(hj=phhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9pubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj5pubj1)}(hhh]h)}(h6Bad block scan pattern used for initial bad block scanh]h6Bad block scan pattern used for initial bad block scan}(hjTphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPphMhjQpubah}(h]h ]h"]h$]h&]uh1j0hj5pubeh}(h]h ]h"]h$]h&]uh1jhjPphMhjlubj)}(h ``bbt`` Bad block table pointer h](j)}(h``bbt``h]j)}(hjtph]hbbt}(hjvphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrpubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjnpubj1)}(hhh]h)}(hBad block table pointerh]hBad block table pointer}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjpubah}(h]h ]h"]h$]h&]uh1j0hjnpubeh}(h]h ]h"]h$]h&]uh1jhjphMhjlubj)}(hF``page_shift`` Number of address bits in a page (column address bits) h](j)}(h``page_shift``h]j)}(hjph]h page_shift}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjpubj1)}(hhh]h)}(h6Number of address bits in a page (column address bits)h]h6Number of address bits in a page (column address bits)}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjpubah}(h]h ]h"]h$]h&]uh1j0hjpubeh}(h]h ]h"]h$]h&]uh1jhjphMhjlubj)}(hE``phys_erase_shift`` Number of address bits in a physical eraseblock h](j)}(h``phys_erase_shift``h]j)}(hjph]hphys_erase_shift}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjpubj1)}(hhh]h)}(h/Number of address bits in a physical eraseblockh]h/Number of address bits in a physical eraseblock}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphMhjpubah}(h]h ]h"]h$]h&]uh1j0hjpubeh}(h]h ]h"]h$]h&]uh1jhjphMhjlubj)}(h2``chip_shift`` Number of address bits in one chip h](j)}(h``chip_shift``h]j)}(hjqh]h chip_shift}(hj!qhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjqubj1)}(hhh]h)}(h"Number of address bits in one chiph]h"Number of address bits in one chip}(hj8qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4qhMhj5qubah}(h]h ]h"]h$]h&]uh1j0hjqubeh}(h]h ]h"]h$]h&]uh1jhj4qhMhjlubj)}(h=``pagemask`` Page number mask = number of (pages / chip) - 1 h](j)}(h ``pagemask``h]j)}(hjXqh]hpagemask}(hjZqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVqubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjRqubj1)}(hhh]h)}(h/Page number mask = number of (pages / chip) - 1h]h/Page number mask = number of (pages / chip) - 1}(hjqqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmqhMhjnqubah}(h]h ]h"]h$]h&]uh1j0hjRqubeh}(h]h ]h"]h$]h&]uh1jhjmqhMhjlubj)}(h&``subpagesize`` Holds the subpagesize h](j)}(h``subpagesize``h]j)}(hjqh]h subpagesize}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjqubj1)}(hhh]h)}(hHolds the subpagesizeh]hHolds the subpagesize}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjqubah}(h]h ]h"]h$]h&]uh1j0hjqubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjlubj)}(h<``data_buf`` Buffer for data, size is (page size + oobsize) h](j)}(h ``data_buf``h]j)}(hjqh]hdata_buf}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjqubj1)}(hhh]h)}(h.Buffer for data, size is (page size + oobsize)h]h.Buffer for data, size is (page size + oobsize)}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhMhjqubah}(h]h ]h"]h$]h&]uh1j0hjqubeh}(h]h ]h"]h$]h&]uh1jhjqhMhjlubj)}(h8``oob_poi`` pointer on the OOB area covered by data_buf h](j)}(h ``oob_poi``h]j)}(hjrh]hoob_poi}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjqubj1)}(hhh]h)}(h+pointer on the OOB area covered by data_bufh]h+pointer on the OOB area covered by data_buf}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j0hjqubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjlubj)}(h=``pagecache`` Structure containing page cache related fields h](j)}(h ``pagecache``h]j)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:rubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj6rubj1)}(hhh]h)}(h.Structure containing page cache related fieldsh]h.Structure containing page cache related fields}(hjUrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQrhMhjRrubah}(h]h ]h"]h$]h&]uh1j0hj6rubeh}(h]h ]h"]h$]h&]uh1jhjQrhMhjlubj)}(h=``pagecache.bitflips`` Number of bitflips of the cached page h](j)}(h``pagecache.bitflips``h]j)}(hjurh]hpagecache.bitflips}(hjwrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsrubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjorubj1)}(hhh]h)}(h%Number of bitflips of the cached pageh]h%Number of bitflips of the cached page}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j0hjorubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjlubj)}(h\``pagecache.page`` Page number currently in the cache. -1 means no page is currently cached h](j)}(h``pagecache.page``h]j)}(hjrh]hpagecache.page}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjrubj1)}(hhh]h)}(hHPage number currently in the cache. -1 means no page is currently cachedh]hHPage number currently in the cache. -1 means no page is currently cached}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjrubah}(h]h ]h"]h$]h&]uh1j0hjrubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjlubj)}(h>``buf_align`` Minimum buffer alignment required by a platform h](j)}(h ``buf_align``h]j)}(hjrh]h buf_align}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjrubj1)}(hhh]h)}(h/Minimum buffer alignment required by a platformh]h/Minimum buffer alignment required by a platform}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhMhjrubah}(h]h ]h"]h$]h&]uh1j0hjrubeh}(h]h ]h"]h$]h&]uh1jhjrhMhjlubj)}(ha``lock`` Lock protecting the suspended field. Also used to serialize accesses to the NAND device h](j)}(h``lock``h]j)}(hj!sh]hlock}(hj#shhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjsubj1)}(hhh]h)}(hWLock protecting the suspended field. Also used to serialize accesses to the NAND deviceh]hWLock protecting the suspended field. Also used to serialize accesses to the NAND device}(hj:shhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj7subah}(h]h ]h"]h$]h&]uh1j0hjsubeh}(h]h ]h"]h$]h&]uh1jhj6shMhjlubj)}(hE``suspended`` Set to 1 when the device is suspended, 0 when it's not h](j)}(h ``suspended``h]j)}(hj[sh]h suspended}(hj]shhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYsubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjUsubj1)}(hhh]h)}(h6Set to 1 when the device is suspended, 0 when it's noth]h8Set to 1 when the device is suspended, 0 when it’s not}(hjtshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjpshMhjqsubah}(h]h ]h"]h$]h&]uh1j0hjUsubeh}(h]h ]h"]h$]h&]uh1jhjpshMhjlubj)}(hD``resume_wq`` wait queue to sleep if rawnand is in suspended state. h](j)}(h ``resume_wq``h]j)}(hjsh]h resume_wq}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjsubj1)}(hhh]h)}(h5wait queue to sleep if rawnand is in suspended state.h]h5wait queue to sleep if rawnand is in suspended state.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMhjsubah}(h]h ]h"]h$]h&]uh1j0hjsubeh}(h]h ]h"]h$]h&]uh1jhjshMhjlubj)}(h``cur_cs`` Currently selected target. -1 means no target selected, otherwise we should always have cur_cs >= 0 && cur_cs < nanddev_ntargets(). NAND Controller drivers should not modify this value, but they're allowed to read it. h](j)}(h ``cur_cs``h]j)}(hjsh]hcur_cs}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjsubj1)}(hhh]h)}(hCurrently selected target. -1 means no target selected, otherwise we should always have cur_cs >= 0 && cur_cs < nanddev_ntargets(). NAND Controller drivers should not modify this value, but they're allowed to read it.h]hCurrently selected target. -1 means no target selected, otherwise we should always have cur_cs >= 0 && cur_cs < nanddev_ntargets(). NAND Controller drivers should not modify this value, but they’re allowed to read it.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjsubah}(h]h ]h"]h$]h&]uh1j0hjsubeh}(h]h ]h"]h$]h&]uh1jhjshMhjlubj)}(h:``read_retries`` The number of read retry modes supported h](j)}(h``read_retries``h]j)}(hjth]h read_retries}(hj thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjtubj1)}(hhh]h)}(h(The number of read retry modes supportedh]h(The number of read retry modes supported}(hj thhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjtubah}(h]h ]h"]h$]h&]uh1j0hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMhjlubj)}(h@``secure_regions`` Structure containing the secure regions info h](j)}(h``secure_regions``h]j)}(hj@th]hsecure_regions}(hjBthhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>tubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:tubj1)}(hhh]h)}(h,Structure containing the secure regions infoh]h,Structure containing the secure regions info}(hjYthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUthMhjVtubah}(h]h ]h"]h$]h&]uh1j0hj:tubeh}(h]h ]h"]h$]h&]uh1jhjUthMhjlubj)}(h/``nr_secure_regions`` Number of secure regions h](j)}(h``nr_secure_regions``h]j)}(hjyth]hnr_secure_regions}(hj{thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwtubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjstubj1)}(hhh]h)}(hNumber of secure regionsh]hNumber of secure regions}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjtubah}(h]h ]h"]h$]h&]uh1j0hjstubeh}(h]h ]h"]h$]h&]uh1jhjthMhjlubj)}(h-``cont_read`` Sequential page read internals h](j)}(h ``cont_read``h]j)}(hjth]h cont_read}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjtubj1)}(hhh]h)}(hSequential page read internalsh]hSequential page read internals}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthMhjtubah}(h]h ]h"]h$]h&]uh1j0hjtubeh}(h]h ]h"]h$]h&]uh1jhjthMhjlubj)}(hB``cont_read.ongoing`` Whether a continuous read is ongoing or not h](j)}(h``cont_read.ongoing``h]j)}(hjth]hcont_read.ongoing}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjtubj1)}(hhh]h)}(h+Whether a continuous read is ongoing or noth]h+Whether a continuous read is ongoing or not}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjuubah}(h]h ]h"]h$]h&]uh1j0hjtubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjlubj)}(h@``cont_read.first_page`` Start of the continuous read operation h](j)}(h``cont_read.first_page``h]j)}(hj$uh]hcont_read.first_page}(hj&uhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"uubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjuubj1)}(hhh]h)}(h&Start of the continuous read operationh]h&Start of the continuous read operation}(hj=uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9uhMhj:uubah}(h]h ]h"]h$]h&]uh1j0hjuubeh}(h]h ]h"]h$]h&]uh1jhj9uhMhjlubj)}(hL``cont_read.pause_page`` End of the current sequential cache read operation h](j)}(h``cont_read.pause_page``h]j)}(hj]uh]hcont_read.pause_page}(hj_uhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[uubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjWuubj1)}(hhh]h)}(h2End of the current sequential cache read operationh]h2End of the current sequential cache read operation}(hjvuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjruhMhjsuubah}(h]h ]h"]h$]h&]uh1j0hjWuubeh}(h]h ]h"]h$]h&]uh1jhjruhMhjlubj)}(h=``cont_read.last_page`` End of the continuous read operation h](j)}(h``cont_read.last_page``h]j)}(hjuh]hcont_read.last_page}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjuubj1)}(hhh]h)}(h$End of the continuous read operationh]h$End of the continuous read operation}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhMhjuubah}(h]h ]h"]h$]h&]uh1j0hjuubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjlubj)}(hd``controller`` The hardware controller structure which is shared among multiple independent devices h](j)}(h``controller``h]j)}(hjuh]h controller}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjuubj1)}(hhh]h)}(hTThe hardware controller structure which is shared among multiple independent devicesh]hTThe hardware controller structure which is shared among multiple independent devices}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjuubah}(h]h ]h"]h$]h&]uh1j0hjuubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjlubj)}(h%``ecc`` The ECC controller structure h](j)}(h``ecc``h]j)}(hj vh]hecc}(hj vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjvubj1)}(hhh]h)}(hThe ECC controller structureh]hThe ECC controller structure}(hj"vhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhMhjvubah}(h]h ]h"]h$]h&]uh1j0hjvubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjlubj)}(h``priv`` Chip private datah](j)}(h``priv``h]j)}(hjBvh]hpriv}(hjDvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@vubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjwhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj-wubh)}(hhh]j^)}(h nand_chiph]h nand_chip}(hjOwhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjLwubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjQwmodnameN classnameNjFBjIB)}jLB]jvc.nand_get_interface_configasbuh1hhj-wubjG)}(h h]h }(hjmwhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj-wubjcB)}(hjfBh]h*}(hj{whhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhj-wubj^)}(hchiph]hchip}(hjwhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj-wubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhj)wubah}(h]h ]h"]h$]h&]jjuh1jAhjvhhhjvhMoubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjvhhhjvhMoubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j(hjvhMohjvhhubj)}(hhh]h)}(h;Retrieve the current interface configuration of a NAND chiph]h;Retrieve the current interface configuration of a NAND chip}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMohjwhhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhMoubeh}(h]h ](jfunctioneh"]h$]h&]jjjjwjjwjjjuh1j#hhhjhNhNubj)}(h:**Parameters** ``struct nand_chip *chip`` The NAND chiph](h)}(h**Parameters**h]j)}(hjwh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMshjwubj )}(hhh]j)}(h(``struct nand_chip *chip`` The NAND chiph](j)}(h``struct nand_chip *chip``h]j)}(hjwh]hstruct nand_chip *chip}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMuhjwubj1)}(hhh]h)}(h The NAND chiph]h The NAND chip}(hj xhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMqhj xubah}(h]h ]h"]h$]h&]uh1j0hjwubeh}(h]h ]h"]h$]h&]uh1jhjxhMuhjwubah}(h]h ]h"]h$]h&]uh1j hjwubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_flash_dev (C struct)c.nand_flash_devhNtauh1jhjhhhNhNubj$)}(hhh](j))}(hnand_flash_devh]j/)}(hstruct nand_flash_devh](j5)}(hj8h]hstruct}(hjMxhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjIxhhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMvubjG)}(h h]h }(hj[xhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjIxhhhjZxhMvubjX)}(hnand_flash_devh]j^)}(hjGxh]hnand_flash_dev}(hjmxhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjixubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjIxhhhjZxhMvubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hjExhhhjZxhMvubah}(h]j@xah ](jjeh"]h$]h&]jj)jhuh1j(hjZxhMvhjBxhhubj)}(hhh]h)}(hNAND Flash Device ID Structureh]hNAND Flash Device ID Structure}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjxhhubah}(h]h ]h"]h$]h&]uh1jhjBxhhhjZxhMvubeh}(h]h ](jstructeh"]h$]h&]jjjjxjjxjjjuh1j#hhhjhNhNubj)}(hX **Definition**:: struct nand_flash_dev { char *name; union { struct { uint8_t mfr_id; uint8_t dev_id; }; uint8_t id[NAND_MAX_ID_LEN]; }; unsigned int pagesize; unsigned int chipsize; unsigned int erasesize; unsigned int options; uint16_t id_len; uint16_t oobsize; struct { uint16_t strength_ds; uint16_t step_ds; } ecc; }; **Members** ``name`` a human-readable name of the NAND chip ``{unnamed_union}`` anonymous ``{unnamed_struct}`` anonymous ``mfr_id`` manufacturer ID part of the full chip ID array (refers the same memory address as ``id[0]``) ``dev_id`` device ID part of the full chip ID array (refers the same memory address as ``id[1]``) ``id`` full device ID array ``pagesize`` size of the NAND page in bytes; if 0, then the real page size (as well as the eraseblock size) is determined from the extended NAND chip ID array) ``chipsize`` total chip size in MiB ``erasesize`` eraseblock size in bytes (determined from the extended ID if 0) ``options`` stores various chip bit options ``id_len`` The valid length of the **id**. ``oobsize`` OOB size ``ecc`` ECC correctability and step information from the datasheet. ``ecc.strength_ds`` The ECC correctability from the datasheet, same as the **ecc_strength_ds** in nand_chip{}. ``ecc.step_ds`` The ECC step required by the **ecc.strength_ds**, same as the **ecc_step_ds** in nand_chip{}, also from the datasheet. For example, the "4bit ECC for each 512Byte" can be set with NAND_ECC_INFO(4, 512).h](j)}(hX**Definition**:: struct nand_flash_dev { char *name; union { struct { uint8_t mfr_id; uint8_t dev_id; }; uint8_t id[NAND_MAX_ID_LEN]; }; unsigned int pagesize; unsigned int chipsize; unsigned int erasesize; unsigned int options; uint16_t id_len; uint16_t oobsize; struct { uint16_t strength_ds; uint16_t step_ds; } ecc; }; h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubh:}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjxubjs)}(hXstruct nand_flash_dev { char *name; union { struct { uint8_t mfr_id; uint8_t dev_id; }; uint8_t id[NAND_MAX_ID_LEN]; }; unsigned int pagesize; unsigned int chipsize; unsigned int erasesize; unsigned int options; uint16_t id_len; uint16_t oobsize; struct { uint16_t strength_ds; uint16_t step_ds; } ecc; };h]hXstruct nand_flash_dev { char *name; union { struct { uint8_t mfr_id; uint8_t dev_id; }; uint8_t id[NAND_MAX_ID_LEN]; }; unsigned int pagesize; unsigned int chipsize; unsigned int erasesize; unsigned int options; uint16_t id_len; uint16_t oobsize; struct { uint16_t strength_ds; uint16_t step_ds; } ecc; };}hjxsbah}(h]h ]h"]h$]h&]jjuh1jrh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjxubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjxubh)}(h **Members**h]j)}(hjxh]hMembers}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjxubj )}(hhh](j)}(h0``name`` a human-readable name of the NAND chip h](j)}(h``name``h]j)}(hjyh]hname}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjyubj1)}(hhh]h)}(h&a human-readable name of the NAND chiph]h&a human-readable name of the NAND chip}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhMhjyubah}(h]h ]h"]h$]h&]uh1j0hjyubeh}(h]h ]h"]h$]h&]uh1jhjyhMhjxubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hj?yh]h{unnamed_union}}(hjAyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=yubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhj9yubj1)}(hhh]h)}(h anonymoush]h anonymous}(hjXyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTyhKhjUyubah}(h]h ]h"]h$]h&]uh1j0hj9yubeh}(h]h ]h"]h$]h&]uh1jhjTyhKhjxubj)}(h``{unnamed_struct}`` anonymous h](j)}(h``{unnamed_struct}``h]j)}(hjxyh]h{unnamed_struct}}(hjzyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvyubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhKhjryubj1)}(hhh]h)}(h anonymoush]h anonymous}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhKhjyubah}(h]h ]h"]h$]h&]uh1j0hjryubeh}(h]h ]h"]h$]h&]uh1jhjyhKhjxubj)}(hh``mfr_id`` manufacturer ID part of the full chip ID array (refers the same memory address as ``id[0]``) h](j)}(h ``mfr_id``h]j)}(hjyh]hmfr_id}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjyubj1)}(hhh]h)}(h\manufacturer ID part of the full chip ID array (refers the same memory address as ``id[0]``)h](hRmanufacturer ID part of the full chip ID array (refers the same memory address as }(hjyhhhNhNubj)}(h ``id[0]``h]hid[0]}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubh)}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjyubah}(h]h ]h"]h$]h&]uh1j0hjyubeh}(h]h ]h"]h$]h&]uh1jhjyhMhjxubj)}(hb``dev_id`` device ID part of the full chip ID array (refers the same memory address as ``id[1]``) h](j)}(h ``dev_id``h]j)}(hjyh]hdev_id}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjyubj1)}(hhh]h)}(hVdevice ID part of the full chip ID array (refers the same memory address as ``id[1]``)h](hLdevice ID part of the full chip ID array (refers the same memory address as }(hjzhhhNhNubj)}(h ``id[1]``h]hid[1]}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubh)}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjzubah}(h]h ]h"]h$]h&]uh1j0hjyubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjxubj)}(h``id`` full device ID array h](j)}(h``id``h]j)}(hjIzh]hid}(hjKzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGzubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjCzubj1)}(hhh]h)}(hfull device ID arrayh]hfull device ID array}(hjbzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^zhMhj_zubah}(h]h ]h"]h$]h&]uh1j0hjCzubeh}(h]h ]h"]h$]h&]uh1jhj^zhMhjxubj)}(h``pagesize`` size of the NAND page in bytes; if 0, then the real page size (as well as the eraseblock size) is determined from the extended NAND chip ID array) h](j)}(h ``pagesize``h]j)}(hjzh]hpagesize}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj|zubj1)}(hhh]h)}(hsize of the NAND page in bytes; if 0, then the real page size (as well as the eraseblock size) is determined from the extended NAND chip ID array)h]hsize of the NAND page in bytes; if 0, then the real page size (as well as the eraseblock size) is determined from the extended NAND chip ID array)}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjzubah}(h]h ]h"]h$]h&]uh1j0hj|zubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjxubj)}(h$``chipsize`` total chip size in MiB h](j)}(h ``chipsize``h]j)}(hjzh]hchipsize}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjzubj1)}(hhh]h)}(htotal chip size in MiBh]htotal chip size in MiB}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhMhjzubah}(h]h ]h"]h$]h&]uh1j0hjzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjxubj)}(hN``erasesize`` eraseblock size in bytes (determined from the extended ID if 0) h](j)}(h ``erasesize``h]j)}(hjzh]h erasesize}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjzubj1)}(hhh]h)}(h?eraseblock size in bytes (determined from the extended ID if 0)h]h?eraseblock size in bytes (determined from the extended ID if 0)}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj {hMhj {ubah}(h]h ]h"]h$]h&]uh1j0hjzubeh}(h]h ]h"]h$]h&]uh1jhj {hMhjxubj)}(h,``options`` stores various chip bit options h](j)}(h ``options``h]j)}(hj.{h]hoptions}(hj0{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,{ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj({ubj1)}(hhh]h)}(hstores various chip bit optionsh]hstores various chip bit options}(hjG{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC{hMhjD{ubah}(h]h ]h"]h$]h&]uh1j0hj({ubeh}(h]h ]h"]h$]h&]uh1jhjC{hMhjxubj)}(h+``id_len`` The valid length of the **id**. h](j)}(h ``id_len``h]j)}(hjg{h]hid_len}(hji{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje{ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhja{ubj1)}(hhh]h)}(hThe valid length of the **id**.h](hThe valid length of the }(hj{hhhNhNubj)}(h**id**h]hid}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubh.}(hj{hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhj|{hMhj}{ubah}(h]h ]h"]h$]h&]uh1j0hja{ubeh}(h]h ]h"]h$]h&]uh1jhj|{hMhjxubj)}(h``oobsize`` OOB size h](j)}(h ``oobsize``h]j)}(hj{h]hoobsize}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj{ubj1)}(hhh]h)}(hOOB sizeh]hOOB size}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hMhj{ubah}(h]h ]h"]h$]h&]uh1j0hj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hMhjxubj)}(hD``ecc`` ECC correctability and step information from the datasheet. h](j)}(h``ecc``h]j)}(hj{h]hecc}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj{ubj1)}(hhh]h)}(h;ECC correctability and step information from the datasheet.h]h;ECC correctability and step information from the datasheet.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hMhj|ubah}(h]h ]h"]h$]h&]uh1j0hj{ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjxubj)}(ho``ecc.strength_ds`` The ECC correctability from the datasheet, same as the **ecc_strength_ds** in nand_chip{}. h](j)}(h``ecc.strength_ds``h]j)}(hj$|h]hecc.strength_ds}(hj&|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"|ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj|ubj1)}(hhh]h)}(hZThe ECC correctability from the datasheet, same as the **ecc_strength_ds** in nand_chip{}.h](h7The ECC correctability from the datasheet, same as the }(hj=|hhhNhNubj)}(h**ecc_strength_ds**h]hecc_strength_ds}(hjE|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=|ubh in nand_chip{}.}(hj=|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj:|ubah}(h]h ]h"]h$]h&]uh1j0hj|ubeh}(h]h ]h"]h$]h&]uh1jhj9|hMhjxubj)}(h``ecc.step_ds`` The ECC step required by the **ecc.strength_ds**, same as the **ecc_step_ds** in nand_chip{}, also from the datasheet. For example, the "4bit ECC for each 512Byte" can be set with NAND_ECC_INFO(4, 512).h](j)}(h``ecc.step_ds``h]j)}(hjp|h]h ecc.step_ds}(hjr|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn|ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhjj|ubj1)}(hhh]h)}(hThe ECC step required by the **ecc.strength_ds**, same as the **ecc_step_ds** in nand_chip{}, also from the datasheet. For example, the "4bit ECC for each 512Byte" can be set with NAND_ECC_INFO(4, 512).h](hThe ECC step required by the }(hj|hhhNhNubj)}(h**ecc.strength_ds**h]hecc.strength_ds}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh, same as the }(hj|hhhNhNubj)}(h**ecc_step_ds**h]h ecc_step_ds}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh in nand_chip{}, also from the datasheet. For example, the “4bit ECC for each 512Byte” can be set with NAND_ECC_INFO(4, 512).}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj|ubah}(h]h ]h"]h$]h&]uh1j0hjj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMhjxubeh}(h]h ]h"]h$]h&]uh1j hjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_opcode_8bits (C function)c.nand_opcode_8bitshNtauh1jhjhhhNhNubj$)}(hhh](j))}(h,int nand_opcode_8bits (unsigned int command)h]j/)}(h+int nand_opcode_8bits(unsigned int command)h](jA)}(hinth]hint}(hj|hhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj|hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMubjG)}(h h]h }(hj|hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj|hhhj|hMubjX)}(hnand_opcode_8bitsh]j^)}(hnand_opcode_8bitsh]hnand_opcode_8bits}(hj}hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj }ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj|hhhj|hMubjA)}(h(unsigned int command)h]jA)}(hunsigned int commandh](jA)}(hunsignedh]hunsigned}(hj+}hhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj'}ubjG)}(h h]h }(hj9}hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj'}ubjA)}(hinth]hint}(hjG}hhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj'}ubjG)}(h h]h }(hjU}hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj'}ubj^)}(hcommandh]hcommand}(hjc}hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj'}ubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhj#}ubah}(h]h ]h"]h$]h&]jjuh1jAhj|hhhj|hMubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj|hhhj|hMubah}(h]j|ah ](jjeh"]h$]h&]jj)jhuh1j(hj|hMhj|hhubj)}(hhh]h)}(hECheck if the opcode's address should be sent only on the lower 8 bitsh]hGCheck if the opcode’s address should be sent only on the lower 8 bits}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj}hhubah}(h]h ]h"]h$]h&]uh1jhj|hhhj|hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj}jj}jjjuh1j#hhhjhNhNubj)}(h:**Parameters** ``unsigned int command`` opcode to checkh](h)}(h**Parameters**h]j)}(hj}h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj}ubj )}(hhh]j)}(h(``unsigned int command`` opcode to checkh](j)}(h``unsigned int command``h]j)}(hj}h]hunsigned int command}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj}ubj1)}(hhh]h)}(hopcode to checkh]hopcode to check}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMhj}ubah}(h]h ]h"]h$]h&]uh1j0hj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hMhj}ubah}(h]h ]h"]h$]h&]uh1j hj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_get_data_buf (C function)c.nand_get_data_bufhNtauh1jhjhhhNhNubj$)}(hhh](j))}(h1void * nand_get_data_buf (struct nand_chip *chip)h]j/)}(h/void *nand_get_data_buf(struct nand_chip *chip)h](jA)}(hvoidh]hvoid}(hj(~hhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj$~hhh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMPubjG)}(h h]h }(hj7~hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj$~hhhj6~hMPubjcB)}(hjfBh]h*}(hjE~hhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhj$~hhhj6~hMPubjX)}(hnand_get_data_bufh]j^)}(hnand_get_data_bufh]hnand_get_data_buf}(hjV~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjR~ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj$~hhhj6~hMPubjA)}(h(struct nand_chip *chip)h]jA)}(hstruct nand_chip *chiph](j5)}(hj8h]hstruct}(hjr~hhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjn~ubjG)}(h h]h }(hj~hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjn~ubh)}(hhh]j^)}(h nand_chiph]h nand_chip}(hj~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj~ubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetj~modnameN classnameNjFBjIB)}jLB]jOB)}jBBjX~sbc.nand_get_data_bufasbuh1hhjn~ubjG)}(h h]h }(hj~hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjn~ubjcB)}(hjfBh]h*}(hj~hhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjn~ubj^)}(hchiph]hchip}(hj~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjn~ubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjj~ubah}(h]h ]h"]h$]h&]jjuh1jAhj$~hhhj6~hMPubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj ~hhhj6~hMPubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1j(hj6~hMPhj~hhubj)}(hhh]h)}(hGet the internal page bufferh]hGet the internal page buffer}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMPhj~hhubah}(h]h ]h"]h$]h&]uh1jhj~hhhj6~hMPubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j#hhhjhNhNubj)}(hX**Parameters** ``struct nand_chip *chip`` NAND chip object **Description** Returns the pre-allocated page buffer after invalidating the cache. This function should be used by drivers that do not want to allocate their own bounce buffer and still need such a buffer for specific operations (most commonly when reading OOB data only). Be careful to never call this function in the write/write_oob path, because the core may have placed the data to be written out in this buffer. **Return** pointer to the page cache bufferh](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMThjubj )}(hhh]j)}(h,``struct nand_chip *chip`` NAND chip object h](j)}(h``struct nand_chip *chip``h]j)}(hj6h]hstruct nand_chip *chip}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMQhj0ubj1)}(hhh]h)}(hNAND chip objecth]hNAND chip object}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhMQhjLubah}(h]h ]h"]h$]h&]uh1j0hj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMQhj-ubah}(h]h ]h"]h$]h&]uh1j hjubh)}(h**Description**h]j)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMShjubh)}(hXReturns the pre-allocated page buffer after invalidating the cache. This function should be used by drivers that do not want to allocate their own bounce buffer and still need such a buffer for specific operations (most commonly when reading OOB data only).h]hXReturns the pre-allocated page buffer after invalidating the cache. This function should be used by drivers that do not want to allocate their own bounce buffer and still need such a buffer for specific operations (most commonly when reading OOB data only).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMRhjubh)}(hBe careful to never call this function in the write/write_oob path, because the core may have placed the data to be written out in this buffer.h]hBe careful to never call this function in the write/write_oob path, because the core may have placed the data to be written out in this buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMWhjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhMZhjubh)}(h pointer to the page cache bufferh]h pointer to the page cache buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hh_/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:961: ./include/linux/mtd/rawnand.hhM[hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h] structuresah ]h"] structuresah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hPublic Functions Providedh]hPublic Functions Provided}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThis chapter contains the autogenerated documentation of the NAND kernel API functions which are exported. Each function has a short description which is marked with an [XXX] identifier. See the chapter "Documentation hints" for an explanation.h]hThis chapter contains the autogenerated documentation of the NAND kernel API functions which are exported. Each function has a short description which is marked with an [XXX] identifier. See the chapter “Documentation hints” for an explanation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_extract_bits (C function)c.nand_extract_bitshNtauh1jhjhhhNhNubj$)}(hhh](j))}(hovoid nand_extract_bits (u8 *dst, unsigned int dst_off, const u8 *src, unsigned int src_off, unsigned int nbits)h]j/)}(hnvoid nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src, unsigned int src_off, unsigned int nbits)h](jA)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjhhhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKxubjG)}(h h]h }(hj"hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjhhhj!hKxubjX)}(hnand_extract_bitsh]j^)}(hnand_extract_bitsh]hnand_extract_bits}(hj4hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj0ubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhjhhhj!hKxubjA)}(hX(u8 *dst, unsigned int dst_off, const u8 *src, unsigned int src_off, unsigned int nbits)h](jA)}(hu8 *dsth](h)}(hhh]j^)}(hu8h]hu8}(hjShhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjPubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjUmodnameN classnameNjFBjIB)}jLB]jOB)}jBBj6sbc.nand_extract_bitsasbuh1hhjLubjG)}(h h]h }(hjshhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjLubjcB)}(hjfBh]h*}(hjhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjLubj^)}(hdsth]hdst}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjLubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjHubjA)}(hunsigned int dst_offh](jA)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubjA)}(hinth]hint}(hjÀhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjрhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubj^)}(hdst_offh]hdst_off}(hj߀hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjHubjA)}(h const u8 *srch](j5)}(hjAh]hconst}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubh)}(hhh]j^)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetjmodnameN classnameNjFBjIB)}jLB]joc.nand_extract_bitsasbuh1hhjubjG)}(h h]h }(hj4hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubjcB)}(hjfBh]h*}(hjBhhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjubj^)}(hsrch]hsrc}(hjOhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjHubjA)}(hunsigned int src_offh](jA)}(hunsignedh]hunsigned}(hjhhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjdubjG)}(h h]h }(hjvhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjdubjA)}(hinth]hint}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjdubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjdubj^)}(hsrc_offh]hsrc_off}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjdubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjHubjA)}(hunsigned int nbitsh](jA)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjǁhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubjA)}(hinth]hint}(hjՁhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubj^)}(hnbitsh]hnbits}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjHubeh}(h]h ]h"]h$]h&]jjuh1jAhjhhhj!hKxubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj hhhj!hKxubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j(hj!hKxhjhhubj)}(hhh]h)}(h2Copy unaligned bits from one buffer to another oneh]h2Copy unaligned bits from one buffer to another one}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKxhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj!hKxubeh}(h]h ](jfunctioneh"]h$]h&]jjjj3jj3jjjuh1j#hhhjhNhNubj)}(hXv**Parameters** ``u8 *dst`` destination buffer ``unsigned int dst_off`` bit offset at which the writing starts ``const u8 *src`` source buffer ``unsigned int src_off`` bit offset at which the reading starts ``unsigned int nbits`` number of bits to copy from **src** to **dst** **Description** Copy bits from one memory region to another (overlap authorized).h](h)}(h**Parameters**h]j)}(hj=h]h Parameters}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chK|hj7ubj )}(hhh](j)}(h``u8 *dst`` destination buffer h](j)}(h ``u8 *dst``h]j)}(hj\h]hu8 *dst}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKyhjVubj1)}(hhh]h)}(hdestination bufferh]hdestination buffer}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhKyhjrubah}(h]h ]h"]h$]h&]uh1j0hjVubeh}(h]h ]h"]h$]h&]uh1jhjqhKyhjSubj)}(h@``unsigned int dst_off`` bit offset at which the writing starts h](j)}(h``unsigned int dst_off``h]j)}(hjh]hunsigned int dst_off}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKzhjubj1)}(hhh]h)}(h&bit offset at which the writing startsh]h&bit offset at which the writing starts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKzhjubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhjhKzhjSubj)}(h ``const u8 *src`` source buffer h](j)}(h``const u8 *src``h]j)}(hj΂h]h const u8 *src}(hjЂhhhNhNubah}(h]h ]h"]h$]h&]uh1jhĵubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chK{hjȂubj1)}(hhh]h)}(h source bufferh]h source buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK{hjubah}(h]h ]h"]h$]h&]uh1j0hjȂubeh}(h]h ]h"]h$]h&]uh1jhjhK{hjSubj)}(h@``unsigned int src_off`` bit offset at which the reading starts h](j)}(h``unsigned int src_off``h]j)}(hjh]hunsigned int src_off}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chK|hjubj1)}(hhh]h)}(h&bit offset at which the reading startsh]h&bit offset at which the reading starts}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK|hjubah}(h]h ]h"]h$]h&]uh1j0hjubeh}(h]h ]h"]h$]h&]uh1jhjhK|hjSubj)}(hF``unsigned int nbits`` number of bits to copy from **src** to **dst** h](j)}(h``unsigned int nbits``h]j)}(hj@h]hunsigned int nbits}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chK}hj:ubj1)}(hhh]h)}(h.number of bits to copy from **src** to **dst**h](hnumber of bits to copy from }(hjYhhhNhNubj)}(h**src**h]hsrc}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh to }(hjYhhhNhNubj)}(h**dst**h]hdst}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhjUhK}hjVubah}(h]h ]h"]h$]h&]uh1j0hj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhK}hjSubeh}(h]h ]h"]h$]h&]uh1j hj7ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhj7ubh)}(hACopy bits from one memory region to another (overlap authorized).h]hACopy bits from one memory region to another (overlap authorized).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chK~hj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jnand_select_target (C function)c.nand_select_targethNtauh1jhjhhhNhNubj$)}(hhh](j))}(hAvoid nand_select_target (struct nand_chip *chip, unsigned int cs)h]j/)}(h@void nand_select_target(struct nand_chip *chip, unsigned int cs)h](jA)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhj܃hhhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhj܃hhhjhKubjX)}(hnand_select_targeth]j^)}(hnand_select_targeth]hnand_select_target}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubah}(h]h ](jpjqeh"]h$]h&]jjuh1jWhj܃hhhjhKubjA)}(h)(struct nand_chip *chip, unsigned int cs)h](jA)}(hstruct nand_chip *chiph](j5)}(hj8h]hstruct}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1j4hjubjG)}(h h]h }(hj*hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubh)}(hhh]j^)}(h nand_chiph]h nand_chip}(hj;hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hj8ubah}(h]h ]h"]h$]h&] refdomainjreftypejBB reftargetj=modnameN classnameNjFBjIB)}jLB]jOB)}jBBjsbc.nand_select_targetasbuh1hhjubjG)}(h h]h }(hj[hhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubjcB)}(hjfBh]h*}(hjihhhNhNubah}(h]h ]joBah"]h$]h&]uh1jbBhjubj^)}(hchiph]hchip}(hjvhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjubjA)}(hunsigned int csh](jA)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubjA)}(hinth]hint}(hjhhhNhNubah}(h]h ]jAah"]h$]h&]uh1jAhjubjG)}(h h]h }(hjhhhNhNubah}(h]h ]jSah"]h$]h&]uh1jFhjubj^)}(hcsh]hcs}(hjDŽhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j]hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jAhjubeh}(h]h ]h"]h$]h&]jjuh1jAhj܃hhhjhKubeh}(h]h ]h"]h$]h&]jjj{uh1j.j|j}hj؃hhhjhKubah}(h]jӃah ](jjeh"]h$]h&]jj)jhuh1j(hjhKhjՃhhubj)}(hhh]h)}(h!Select a NAND target (A.K.A. die)h]h!Select a NAND target (A.K.A. die)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjՃhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j#hhhjhNhNubj)}(hX-**Parameters** ``struct nand_chip *chip`` NAND chip object ``unsigned int cs`` the CS line to select. Note that this CS id is always from the chip PoV, not the controller one **Description** Select a NAND target so that further operations executed on **chip** go to the selected NAND target.h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhj ubj )}(hhh](j)}(h,``struct nand_chip *chip`` NAND chip object h](j)}(h``struct nand_chip *chip``h]j)}(hj2h]hstruct nand_chip *chip}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhj,ubj1)}(hhh]h)}(hNAND chip objecth]hNAND chip object}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhKhjHubah}(h]h ]h"]h$]h&]uh1j0hj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhKhj)ubj)}(ht``unsigned int cs`` the CS line to select. Note that this CS id is always from the chip PoV, not the controller one h](j)}(h``unsigned int cs``h]j)}(hjkh]hunsigned int cs}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhjeubj1)}(hhh]h)}(h_the CS line to select. Note that this CS id is always from the chip PoV, not the controller oneh]h_the CS line to select. Note that this CS id is always from the chip PoV, not the controller one}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhjubah}(h]h ]h"]h$]h&]uh1j0hjeubeh}(h]h ]h"]h$]h&]uh1jhjhKhj)ubeh}(h]h ]h"]h$]h&]uh1j hj ubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/mtdnand:972: ./drivers/mtd/nand/raw/nand_base.chKhj ubh)}(hdSelect a NAND target so that further operations executed on **chip** go to the selected NAND target.h](h