€•“‘Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ1/translations/zh_CN/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/zh_TW/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/it_IT/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ja_JP/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/ko_KR/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/pt_BR/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ1/translations/sp_SP/driver-api/media/drivers/ipu6”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³ŒK/var/lib/git/docbuild/linux/Documentation/driver-api/media/drivers/ipu6.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒIntel IPU6 Driver”h]”hŒIntel IPU6 Driver”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hŒ)Author: Bingbu Cao ”h]”(hŒAuthor: Bingbu Cao <”…””}”(hhßh²hh³Nh´NubhŒ reference”“”)”}”(hŒbingbu.cao@intel.com”h]”hŒbingbu.cao@intel.com”…””}”(hhéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:bingbu.cao@intel.com”uh1hçhhßubhŒ>”…””}”(hhßh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒOverview”h]”hŒOverview”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K ubhÞ)”}”(hXOIntel IPU6 is the sixth generation of Intel Image Processing Unit used in some Intel Chipsets such as Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake and Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and Processing System (PSYS). IPU6 are visible on the PCI bus as a single device, it can be found by ``lspci``:”h]”(hXEIntel IPU6 is the sixth generation of Intel Image Processing Unit used in some Intel Chipsets such as Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake and Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and Processing System (PSYS). IPU6 are visible on the PCI bus as a single device, it can be found by ”…””}”(hjh²hh³Nh´NubhŒliteral”“”)”}”(hŒ ``lspci``”h]”hŒlspci”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒ:”…””}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjh²hubhÞ)”}”(hŒN``0000:00:05.0 Multimedia controller: Intel Corporation Device xxxx (rev xx)``”h]”j)”}”(hj8h]”hŒJ0000:00:05.0 Multimedia controller: Intel Corporation Device xxxx (rev xx)”…””}”(hj:h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj6ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjh²hubhÞ)”}”(hŒ_IPU6 has a 16 MB BAR in PCI configuration Space for MMIO registers which is visible for driver.”h]”hŒ_IPU6 has a 16 MB BAR in PCI configuration Space for MMIO registers which is visible for driver.”…””}”(hjMh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjh²hubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubhÉ)”}”(hhh]”(hÎ)”}”(hŒButtress”h]”hŒButtress”…””}”(hjfh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjch²hh³hÇh´KubhÞ)”}”(hŒ×The IPU6 is connecting to the system fabric with Buttress which is enabling host driver to control the IPU6, it also allows IPU6 access the system memory to store and load frame pixel streams and any other metadata.”h]”hŒ×The IPU6 is connecting to the system fabric with Buttress which is enabling host driver to control the IPU6, it also allows IPU6 access the system memory to store and load frame pixel streams and any other metadata.”…””}”(hjth²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjch²hubhÞ)”}”(hŒŒButtress mainly manages several system functionalities: power management, interrupt handling, firmware authentication and global timer sync.”h]”hŒŒButtress mainly manages several system functionalities: power management, interrupt handling, firmware authentication and global timer sync.”…””}”(hj‚h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjch²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒISYS and PSYS Power flow”h]”hŒISYS and PSYS Power flow”…””}”(hj“h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K"ubhÞ)”}”(hŒÝIPU6 driver initialize the ISYS and PSYS power up or down request by setting the Buttress frequency control register for ISYS and PSYS (``IPU6_BUTTRESS_REG_IS_FREQ_CTL`` and ``IPU6_BUTTRESS_REG_PS_FREQ_CTL``) in function:”h]”(hŒˆIPU6 driver initialize the ISYS and PSYS power up or down request by setting the Buttress frequency control register for ISYS and PSYS (”…””}”(hj¡h²hh³Nh´Nubj)”}”(hŒ!``IPU6_BUTTRESS_REG_IS_FREQ_CTL``”h]”hŒIPU6_BUTTRESS_REG_IS_FREQ_CTL”…””}”(hj©h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¡ubhŒ and ”…””}”(hj¡h²hh³Nh´Nubj)”}”(hŒ!``IPU6_BUTTRESS_REG_PS_FREQ_CTL``”h]”hŒIPU6_BUTTRESS_REG_PS_FREQ_CTL”…””}”(hj»h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¡ubhŒ) in function:”…””}”(hj¡h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K$hjh²hubhŒindex”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(Œsingle”Œ ipu6_buttress_power (C function)”Œc.ipu6_buttress_power”hNt”auh1jÓhjh²hh³Nh´NubhŒdesc”“”)”}”(hhh]”(hŒdesc_signature”“”)”}”(hŒint ipu6_buttress_power(...)”h]”hŒdesc_signature_line”“”)”}”(hŒint ipu6_buttress_power(...)”h]”(hŒdesc_sig_keyword_type”“”)”}”(hŒint”h]”hŒint”…””}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”Œkt”ah"]”h$]”h&]”uh1jõhjñh²hh³hÇh´K)ubhŒdesc_sig_space”“”)”}”(hŒ ”h]”hŒ ”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”Œw”ah"]”h$]”h&]”uh1jhjñh²hh³hÇh´K)ubhŒ desc_name”“”)”}”(hŒipu6_buttress_power”h]”hŒ desc_sig_name”“”)”}”(hŒipu6_buttress_power”h]”hŒipu6_buttress_power”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”Œn”ah"]”h$]”h&]”uh1jhjubah}”(h]”h ]”(Œsig-name”Œdescname”eh"]”h$]”h&]”hÅhÆuh1jhjñh²hh³hÇh´K)ubhŒdesc_parameterlist”“”)”}”(hŒ(...)”h]”hŒdesc_parameter”“”)”}”(hŒ...”h]”hŒdesc_sig_punctuation”“”)”}”(hŒ...”h]”hŒ...”…””}”(hjDh²hh³Nh´Nubah}”(h]”h ]”Œp”ah"]”h$]”h&]”uh1jBhj>ubah}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆhÅhÆuh1j<hj8ubah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j6hjñh²hh³hÇh´K)ubeh}”(h]”h ]”h"]”h$]”h&]”hÅhÆŒ add_permalink”ˆuh1jïŒsphinx_line_type”Œ declarator”hjëh²hh³hÇh´K)ubah}”(h]”jâah ]”(Œsig”Œ sig-object”eh"]”h$]”h&]”Œ is_multiline”ˆŒ _toc_parts”)Œ _toc_name”huh1jéh³hÇh´K)hjæh²hubhŒ desc_content”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1jthjæh²hh³hÇh´K)ubeh}”(h]”h ]”(Œc”Œfunction”eh"]”h$]”h&]”Œdomain”j‚Œobjtype”jƒŒdesctype”jƒŒnoindex”‰Œ noindexentry”‰Œnocontentsentry”‰uh1jäh²hhjh³Nh´NubhÞ)”}”(hŒ°Buttress forwards the request to Punit, after Punit execute the power up flow, Buttress indicates driver that ISYS or PSYS is powered up by updating the power status registers.”h]”hŒ°Buttress forwards the request to Punit, after Punit execute the power up flow, Buttress indicates driver that ISYS or PSYS is powered up by updating the power status registers.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K+hjh²hubhŒnote”“”)”}”(hŒ‰ISYS power up needs take place prior to PSYS power up, ISYS power down needs take place after PSYS power down due to hardware limitation.”h]”hÞ)”}”(hŒ‰ISYS power up needs take place prior to PSYS power up, ISYS power down needs take place after PSYS power down due to hardware limitation.”h]”hŒ‰ISYS power up needs take place prior to PSYS power up, ISYS power down needs take place after PSYS power down due to hardware limitation.”…””}”(hj¡h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K/hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j›hjh²hh³hÇh´Nubeh}”(h]”Œisys-and-psys-power-flow”ah ]”h"]”Œisys and psys power flow”ah$]”h&]”uh1hÈhjch²hh³hÇh´K"ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Interrupt”h]”hŒ Interrupt”…””}”(hjÀh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj½h²hh³hÇh´K3ubhÞ)”}”(hX4IPU6 interrupt can be generated as MSI or INTA, interrupt will be triggered when ISYS, PSYS, Buttress event or error happen, driver can get the interrupt cause by reading the interrupt status register ``BUTTRESS_REG_ISR_STATUS``, driver clears the irq status and then calls specific ISYS or PSYS irq handler.”h]”(hŒÉIPU6 interrupt can be generated as MSI or INTA, interrupt will be triggered when ISYS, PSYS, Buttress event or error happen, driver can get the interrupt cause by reading the interrupt status register ”…””}”(hjÎh²hh³Nh´Nubj)”}”(hŒ``BUTTRESS_REG_ISR_STATUS``”h]”hŒBUTTRESS_REG_ISR_STATUS”…””}”(hjÖh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÎubhŒP, driver clears the irq status and then calls specific ISYS or PSYS irq handler.”…””}”(hjÎh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K5hj½h²hubjÔ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(jàŒipu6_buttress_isr (C function)”Œc.ipu6_buttress_isr”hNt”auh1jÓhj½h²hh³Nh´Nubjå)”}”(hhh]”(jê)”}”(hŒ+irqreturn_t ipu6_buttress_isr(int irq, ...)”h]”jð)”}”(hŒ+irqreturn_t ipu6_buttress_isr(int irq, ...)”h]”(h)”}”(hhh]”j)”}”(hŒ irqreturn_t”h]”hŒ irqreturn_t”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”j*ah"]”h$]”h&]”uh1jhjubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j‚Œreftype”Œ identifier”Œ reftarget”j Œmodname”NŒ classname”NŒ c:parent_key”Œsphinx.domains.c”Œ LookupKey”“”)”}”Œdata”]”j%Œ ASTIdentifier”“”)”}”j Œipu6_buttress_isr”sbŒc.ipu6_buttress_isr”†”asbuh1hhjh²hh³hÇh´K:ubj)”}”(hŒ ”h]”hŒ ”…””}”(hj3h²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jhjh²hh³hÇh´K:ubj)”}”(hŒipu6_buttress_isr”h]”j)”}”(hj0h]”hŒipu6_buttress_isr”…””}”(hjEh²hh³Nh´Nubah}”(h]”h ]”j*ah"]”h$]”h&]”uh1jhjAubah}”(h]”h ]”(j1j2eh"]”h$]”h&]”hÅhÆuh1jhjh²hh³hÇh´K:ubj7)”}”(hŒ(int irq, ...)”h]”(j=)”}”(hŒint irq”h]”(jö)”}”(hŒint”h]”hŒint”…””}”(hj`h²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jõhj\ubj)”}”(hŒ ”h]”hŒ ”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jhj\ubj)”}”(hŒirq”h]”hŒirq”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”j*ah"]”h$]”h&]”uh1jhj\ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆhÅhÆuh1j<hjXubj=)”}”(hŒ...”h]”jC)”}”(hjFh]”hŒ...”…””}”(hj•h²hh³Nh´Nubah}”(h]”h ]”jOah"]”h$]”h&]”uh1jBhj‘ubah}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆhÅhÆuh1j<hjXubeh}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j6hjh²hh³hÇh´K:ubeh}”(h]”h ]”h"]”h$]”h&]”hÅhÆjfˆuh1jïjgjhhjÿh²hh³hÇh´K:ubah}”(h]”júah ]”(jljmeh"]”h$]”h&]”jqˆjr)jshuh1jéh³hÇh´K:hjüh²hubju)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1jthjüh²hh³hÇh´K:ubeh}”(h]”h ]”(j‚Œfunction”eh"]”h$]”h&]”j‡j‚jˆjÇj‰jÇjŠ‰j‹‰jŒ‰uh1jäh²hhj½h³Nh´Nubeh}”(h]”Œ interrupt”ah ]”h"]”Œ interrupt”ah$]”h&]”uh1hÈhjch²hh³hÇh´K3ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ$Security and firmware authentication”h]”hŒ$Security and firmware authentication”…””}”(hjÖh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÓh²hh³hÇh´K=ubhÞ)”}”(hXnTo address the IPU6 firmware security concerns, the IPU6 firmware needs to undergo an authentication process before it is allowed to executed on the IPU6 internal processors. The IPU6 driver will work with Converged Security Engine (CSE) to complete authentication process. The CSE is responsible of authenticating the IPU6 firmware. The authenticated firmware binary is copied into an isolated memory region. Firmware authentication process is implemented by CSE following an IPC handshake with the IPU6 driver. There are some Buttress registers used by the CSE and the IPU6 driver to communicate with each other via IPC.”h]”hXnTo address the IPU6 firmware security concerns, the IPU6 firmware needs to undergo an authentication process before it is allowed to executed on the IPU6 internal processors. The IPU6 driver will work with Converged Security Engine (CSE) to complete authentication process. The CSE is responsible of authenticating the IPU6 firmware. The authenticated firmware binary is copied into an isolated memory region. Firmware authentication process is implemented by CSE following an IPC handshake with the IPU6 driver. There are some Buttress registers used by the CSE and the IPU6 driver to communicate with each other via IPC.”…””}”(hjäh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K?hjÓh²hubjÔ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(jàŒ'ipu6_buttress_authenticate (C function)”Œc.ipu6_buttress_authenticate”hNt”auh1jÓhjÓh²hh³Nh´Nubjå)”}”(hhh]”(jê)”}”(hŒ#int ipu6_buttress_authenticate(...)”h]”jð)”}”(hŒ#int ipu6_buttress_authenticate(...)”h]”(jö)”}”(hŒint”h]”hŒint”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jõhjh²hh³hÇh´KIubj)”}”(hŒ ”h]”hŒ ”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jhjh²hh³hÇh´KIubj)”}”(hŒipu6_buttress_authenticate”h]”j)”}”(hŒipu6_buttress_authenticate”h]”hŒipu6_buttress_authenticate”…””}”(hj+h²hh³Nh´Nubah}”(h]”h ]”j*ah"]”h$]”h&]”uh1jhj'ubah}”(h]”h ]”(j1j2eh"]”h$]”h&]”hÅhÆuh1jhjh²hh³hÇh´KIubj7)”}”(hŒ(...)”h]”j=)”}”(hŒ...”h]”jC)”}”(hjFh]”hŒ...”…””}”(hjGh²hh³Nh´Nubah}”(h]”h ]”jOah"]”h$]”h&]”uh1jBhjCubah}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆhÅhÆuh1j<hj?ubah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j6hjh²hh³hÇh´KIubeh}”(h]”h ]”h"]”h$]”h&]”hÅhÆjfˆuh1jïjgjhhjh²hh³hÇh´KIubah}”(h]”jþah ]”(jljmeh"]”h$]”h&]”jqˆjr)jshuh1jéh³hÇh´KIhjh²hubju)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1jthjh²hh³hÇh´KIubeh}”(h]”h ]”(j‚Œfunction”eh"]”h$]”h&]”j‡j‚jˆjyj‰jyjŠ‰j‹‰jŒ‰uh1jäh²hhjÓh³Nh´Nubeh}”(h]”Œ$security-and-firmware-authentication”ah ]”h"]”Œ$security and firmware authentication”ah$]”h&]”uh1hÈhjch²hh³hÇh´K=ubhÉ)”}”(hhh]”(hÎ)”}”(hŒGlobal timer sync”h]”hŒGlobal timer sync”…””}”(hjˆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj…h²hh³hÇh´KLubhÞ)”}”(hXŒThe IPU6 driver initiates a Hammock Harbor synchronization flow each time it starts camera operation. The IPU6 will synchronizes an internal counter in the Buttress with a copy of the SoC time, this counter maintains the up-to-date time until camera operation is stopped. The IPU6 driver can use this time counter to calibrate the timestamp based on the timestamp in response event from firmware.”h]”hXŒThe IPU6 driver initiates a Hammock Harbor synchronization flow each time it starts camera operation. The IPU6 will synchronizes an internal counter in the Buttress with a copy of the SoC time, this counter maintains the up-to-date time until camera operation is stopped. The IPU6 driver can use this time counter to calibrate the timestamp based on the timestamp in response event from firmware.”…””}”(hj–h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KNhj…h²hubjÔ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(jàŒ)ipu6_buttress_start_tsc_sync (C function)”Œc.ipu6_buttress_start_tsc_sync”hNt”auh1jÓhj…h²hh³Nh´Nubjå)”}”(hhh]”(jê)”}”(hŒ%int ipu6_buttress_start_tsc_sync(...)”h]”jð)”}”(hŒ%int ipu6_buttress_start_tsc_sync(...)”h]”(jö)”}”(hŒint”h]”hŒint”…””}”(hj½h²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jõhj¹h²hh³hÇh´KTubj)”}”(hŒ ”h]”hŒ ”…””}”(hjËh²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jhj¹h²hh³hÇh´KTubj)”}”(hŒipu6_buttress_start_tsc_sync”h]”j)”}”(hŒipu6_buttress_start_tsc_sync”h]”hŒipu6_buttress_start_tsc_sync”…””}”(hjÝh²hh³Nh´Nubah}”(h]”h ]”j*ah"]”h$]”h&]”uh1jhjÙubah}”(h]”h ]”(j1j2eh"]”h$]”h&]”hÅhÆuh1jhj¹h²hh³hÇh´KTubj7)”}”(hŒ(...)”h]”j=)”}”(hŒ...”h]”jC)”}”(hjFh]”hŒ...”…””}”(hjùh²hh³Nh´Nubah}”(h]”h ]”jOah"]”h$]”h&]”uh1jBhjõubah}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆhÅhÆuh1j<hjñubah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j6hj¹h²hh³hÇh´KTubeh}”(h]”h ]”h"]”h$]”h&]”hÅhÆjfˆuh1jïjgjhhjµh²hh³hÇh´KTubah}”(h]”j°ah ]”(jljmeh"]”h$]”h&]”jqˆjr)jshuh1jéh³hÇh´KThj²h²hubju)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1jthj²h²hh³hÇh´KTubeh}”(h]”h ]”(j‚Œfunction”eh"]”h$]”h&]”j‡j‚jˆj+j‰j+jŠ‰j‹‰jŒ‰uh1jäh²hhj…h³Nh´Nubeh}”(h]”Œglobal-timer-sync”ah ]”h"]”Œglobal timer sync”ah$]”h&]”uh1hÈhjch²hh³hÇh´KLubeh}”(h]”Œbuttress”ah ]”h"]”Œbuttress”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ DMA and MMU”h]”hŒ DMA and MMU”…””}”(hjBh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj?h²hh³hÇh´KWubhÞ)”}”(hXThe IPU6 has its own scalar processor where the firmware run at and an internal 32-bit virtual address space. The IPU6 has MMU address translation hardware to allow that scalar processors to access the internal memory and external system memory through IPU6 virtual address. The address translation is based on two levels of page lookup tables stored in system memory which are maintained by the IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU register and allows MMU to perform page table lookups.”h]”hXThe IPU6 has its own scalar processor where the firmware run at and an internal 32-bit virtual address space. The IPU6 has MMU address translation hardware to allow that scalar processors to access the internal memory and external system memory through IPU6 virtual address. The address translation is based on two levels of page lookup tables stored in system memory which are maintained by the IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU register and allows MMU to perform page table lookups.”…””}”(hjPh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KYhj?h²hubhÞ)”}”(hŒ¯The IPU6 driver exports its own DMA operations. The IPU6 driver will update the page table entries for each DMA operation and invalidate the MMU TLB after each unmap and free.”h]”hŒ¯The IPU6 driver exports its own DMA operations. The IPU6 driver will update the page table entries for each DMA operation and invalidate the MMU TLB after each unmap and free.”…””}”(hj^h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kahj?h²hubeh}”(h]”Œ dma-and-mmu”ah ]”h"]”Œ dma and mmu”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KWubhÉ)”}”(hhh]”(hÎ)”}”(hŒFirmware file format”h]”hŒFirmware file format”…””}”(hjwh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjth²hh³hÇh´KfubhÞ)”}”(hXÉThe IPU6 firmware is in Code Partition Directory (CPD) file format. The CPD firmware contains a CPD header, several CPD entries and components. The CPD component includes 3 entries - manifest, metadata and module data. Manifest and metadata are defined by CSE and used by CSE for authentication. Module data is specific to IPU6 which holds the binary data of firmware called package directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates the CPD firmware file and gets the package directory binary data of the IPU6 firmware, copies it to specific DMA buffer and sets its base address to Buttress ``FW_SOURCE_BASE`` register. Finally the CSE will do authentication for this firmware binary.”h]”(hX›The IPU6 firmware is in Code Partition Directory (CPD) file format. The CPD firmware contains a CPD header, several CPD entries and components. The CPD component includes 3 entries - manifest, metadata and module data. Manifest and metadata are defined by CSE and used by CSE for authentication. Module data is specific to IPU6 which holds the binary data of firmware called package directory. The IPU6 driver (”…””}”(hj…h²hh³Nh´Nubj)”}”(hŒ``ipu6-cpd.c``”h]”hŒ ipu6-cpd.c”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj…ubhŒÃ in particular) parses and validates the CPD firmware file and gets the package directory binary data of the IPU6 firmware, copies it to specific DMA buffer and sets its base address to Buttress ”…””}”(hj…h²hh³Nh´Nubj)”}”(hŒ``FW_SOURCE_BASE``”h]”hŒFW_SOURCE_BASE”…””}”(hjŸh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj…ubhŒK register. Finally the CSE will do authentication for this firmware binary.”…””}”(hj…h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhjth²hubeh}”(h]”Œfirmware-file-format”ah ]”h"]”Œfirmware file format”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KfubhÉ)”}”(hhh]”(hÎ)”}”(hŒSyscom interface”h]”hŒSyscom interface”…””}”(hjÂh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¿h²hh³hÇh´KuubhÞ)”}”(hX¸The IPU6 driver communicates with firmware via the Syscom ABI. Syscom is an inter-processor communication mechanism between the IPU scalar processors and the CPU. There are a number of resources shared between firmware and software. A system memory region where the message queues reside, firmware can access the memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues with a configurable number of tokens (messages). There are also common IPU6 MMIO registers where the queue read and write indices reside. Software and firmware function as producer and consumer of tokens in the queues and update the write and read indices separately when sending or receiving each message.”h]”hX¸The IPU6 driver communicates with firmware via the Syscom ABI. Syscom is an inter-processor communication mechanism between the IPU scalar processors and the CPU. There are a number of resources shared between firmware and software. A system memory region where the message queues reside, firmware can access the memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues with a configurable number of tokens (messages). There are also common IPU6 MMIO registers where the queue read and write indices reside. Software and firmware function as producer and consumer of tokens in the queues and update the write and read indices separately when sending or receiving each message.”…””}”(hjÐh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kwhj¿h²hubhÞ)”}”(hXThe IPU6 driver must prepare and configure the number of input and output queues, configure the count of tokens per queue and the size of per token before initiating and starting the communication with firmware. Firmware and software must use same configurations. The IPU6 Buttress has a number of firmware boot parameter registers which can be used to store the address of configuration and initialise the Syscom state, then driver can request firmware to start and run via setting the scalar processor control status register.”h]”hXThe IPU6 driver must prepare and configure the number of input and output queues, configure the count of tokens per queue and the size of per token before initiating and starting the communication with firmware. Firmware and software must use same configurations. The IPU6 Buttress has a number of firmware boot parameter registers which can be used to store the address of configuration and initialise the Syscom state, then driver can request firmware to start and run via setting the scalar processor control status register.”…””}”(hjÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj¿h²hubeh}”(h]”Œsyscom-interface”ah ]”h"]”Œsyscom interface”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KuubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Input System”h]”hŒ Input System”…””}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjôh²hh³hÇh´KŠubhÞ)”}”(hŒžIPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can capture image pixel data from camera sensors or other MIPI CSI-2 output devices.”h]”hŒžIPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can capture image pixel data from camera sensors or other MIPI CSI-2 output devices.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KŒhjôh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒ#D-PHYs and CSI-2 ports lane mapping”h]”hŒ#D-PHYs and CSI-2 ports lane mapping”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´KubhÞ)”}”(hXThe IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an adaptional layer between D-PHY and CSI-2 receiver controller which includes port configuration, PHY wrapper or private test interfaces for D-PHY. There are 3 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and ``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.”h]”(hX”The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an adaptional layer between D-PHY and CSI-2 receiver controller which includes port configuration, PHY wrapper or private test interfaces for D-PHY. There are 3 D-PHY drivers ”…””}”(hj$h²hh³Nh´Nubj)”}”(hŒ``ipu6-isys-mcd-phy.c``”h]”hŒipu6-isys-mcd-phy.c”…””}”(hj,h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj$ubhŒ, ”…””}”(hj$h²hh³Nh´Nubj)”}”(hŒ``ipu6-isys-jsl-phy.c``”h]”hŒipu6-isys-jsl-phy.c”…””}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj$ubhŒ and ”…””}”(hj$h²hh³Nh´Nubj)”}”(hŒ``ipu6-isys-dwc-phy.c``”h]”hŒipu6-isys-dwc-phy.c”…””}”(hjPh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj$ubhŒ$ program the above 3 D-PHYs in IPU6.”…””}”(hj$h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K’hjh²hubhÞ)”}”(hX´Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake, there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports, see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock lanes so IPU6 support maximum 6 CSI-2 ports.”h]”(hŒ³Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake, there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports, see the PPI mmapping in ”…””}”(hjhh²hh³Nh´Nubj)”}”(hŒ``ipu6-isys-mcd-phy.c``”h]”hŒipu6-isys-mcd-phy.c”…””}”(hjph²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhubhŒê for more information. On Jasper Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock lanes so IPU6 support maximum 6 CSI-2 ports.”…””}”(hjhh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kšhjh²hubjœ)”}”(hXÒEach pair of CSI-2 two ports is a single unit that can share the data lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1 will not be available as the 4 data lanes are shared by CSI-2 port 0 and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.”h]”hÞ)”}”(hXÒEach pair of CSI-2 two ports is a single unit that can share the data lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1 will not be available as the 4 data lanes are shared by CSI-2 port 0 and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.”h]”hXÒEach pair of CSI-2 two ports is a single unit that can share the data lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1 will not be available as the 4 data lanes are shared by CSI-2 port 0 and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.”…””}”(hjŒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K¡hjˆubah}”(h]”h ]”h"]”h$]”h&]”uh1j›hjh²hh³hÇh´Nubeh}”(h]”Œ#d-phys-and-csi-2-ports-lane-mapping”ah ]”h"]”Œ#d-phys and csi-2 ports lane mapping”ah$]”h&]”uh1hÈhjôh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒISYS firmware ABIs”h]”hŒISYS firmware ABIs”…””}”(hj«h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¨h²hh³hÇh´KªubhÞ)”}”(hXThe IPU6 firmware implements a series of ABIs for software access. In general, software firstly prepares the stream configuration ``struct ipu6_fw_isys_stream_cfg_data_abi`` and sends the configuration to firmware via sending ``STREAM_OPEN`` command. Stream configuration includes input pins and output pins, input pin ``struct ipu6_fw_isys_input_pin_info_abi`` defines the resolution and data type of input source, output pin ``struct ipu6_fw_isys_output_pin_info_abi`` defines the output resolution, stride and frame format, etc.”h]”(hŒ‚The IPU6 firmware implements a series of ABIs for software access. In general, software firstly prepares the stream configuration ”…””}”(hj¹h²hh³Nh´Nubj)”}”(hŒ+``struct ipu6_fw_isys_stream_cfg_data_abi``”h]”hŒ'struct ipu6_fw_isys_stream_cfg_data_abi”…””}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¹ubhŒ5 and sends the configuration to firmware via sending ”…””}”(hj¹h²hh³Nh´Nubj)”}”(hŒ``STREAM_OPEN``”h]”hŒ STREAM_OPEN”…””}”(hjÓh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¹ubhŒN command. Stream configuration includes input pins and output pins, input pin ”…””}”(hj¹h²hh³Nh´Nubj)”}”(hŒ*``struct ipu6_fw_isys_input_pin_info_abi``”h]”hŒ&struct ipu6_fw_isys_input_pin_info_abi”…””}”(hjåh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¹ubhŒB defines the resolution and data type of input source, output pin ”…””}”(hj¹h²hh³Nh´Nubj)”}”(hŒ+``struct ipu6_fw_isys_output_pin_info_abi``”h]”hŒ'struct ipu6_fw_isys_output_pin_info_abi”…””}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¹ubhŒ= defines the output resolution, stride and frame format, etc.”…””}”(hj¹h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K¬hj¨h²hubhÞ)”}”(hXõOnce the driver gets the interrupt from firmware that indicates stream open successfully, the driver will send the ``STREAM_START`` and ``STREAM_CAPTURE`` command to request firmware to start capturing image frames. ``STREAM_CAPTURE`` command queues the buffers to firmware with ``struct ipu6_fw_isys_frame_buff_set``, software then waits for the interrupt and response from firmware, ``PIN_DATA_READY`` means a buffer is ready on a specific output pin and then software can return the buffer to user.”h]”(hŒsOnce the driver gets the interrupt from firmware that indicates stream open successfully, the driver will send the ”…””}”(hjh²hh³Nh´Nubj)”}”(hŒ``STREAM_START``”h]”hŒ STREAM_START”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒ and ”…””}”(hjh²hh³Nh´Nubj)”}”(hŒ``STREAM_CAPTURE``”h]”hŒSTREAM_CAPTURE”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒ> command to request firmware to start capturing image frames. ”…””}”(hjh²hh³Nh´Nubj)”}”(hŒ``STREAM_CAPTURE``”h]”hŒSTREAM_CAPTURE”…””}”(hj;h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒ- command queues the buffers to firmware with ”…””}”(hjh²hh³Nh´Nubj)”}”(hŒ&``struct ipu6_fw_isys_frame_buff_set``”h]”hŒ"struct ipu6_fw_isys_frame_buff_set”…””}”(hjMh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒD, software then waits for the interrupt and response from firmware, ”…””}”(hjh²hh³Nh´Nubj)”}”(hŒ``PIN_DATA_READY``”h]”hŒPIN_DATA_READY”…””}”(hj_h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒb means a buffer is ready on a specific output pin and then software can return the buffer to user.”…””}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kµhj¨h²hubjœ)”}”(hŒ\See :ref:`Examples` about how to do capture by IPU6 ISYS driver.”h]”hÞ)”}”(hŒ\See :ref:`Examples` about how to do capture by IPU6 ISYS driver.”h]”(hŒSee ”…””}”(hj{h²hh³Nh´Nubh)”}”(hŒ+:ref:`Examples`”h]”hŒinline”“”)”}”(hj…h]”hŒExamples”…””}”(hj‰h²hh³Nh´Nubah}”(h]”h ]”(Œxref”Œstd”Œstd-ref”eh"]”h$]”h&]”uh1j‡hjƒubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”Œdriver-api/media/drivers/ipu6”Œ refdomain”j”Œreftype”Œref”Œ refexplicit”ˆŒrefwarn”ˆŒ reftarget”Œipu6_isys_capture_examples”uh1hh³hÇh´K½hj{ubhŒ- about how to do capture by IPU6 ISYS driver.”…””}”(hj{h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K½hjwubah}”(h]”h ]”h"]”h$]”h&]”uh1j›hj¨h²hh³hÇh´Nubeh}”(h]”Œisys-firmware-abis”ah ]”h"]”Œisys firmware abis”ah$]”h&]”uh1hÈhjôh²hh³hÇh´Kªubeh}”(h]”Œ input-system”ah ]”h"]”Œ input system”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KŠubeh}”(h]”Œintel-ipu6-driver”ah ]”h"]”Œintel ipu6 driver”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jóŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ 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autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.