sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget:/translations/zh_CN/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/zh_TW/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/it_IT/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/ja_JP/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/ko_KR/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget:/translations/sp_SP/driver-api/media/drivers/cx2341x-develmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhT/var/lib/git/docbuild/linux/Documentation/driver-api/media/drivers/cx2341x-devel.rsthKubhsection)}(hhh](htitle)}(hThe cx2341x driverh]hThe cx2341x driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMemory at cx2341x chipsh]hMemory at cx2341x chips}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hWThis section describes the cx2341x memory map and documents some of the register space.h]hWThis section describes the cx2341x memory map and documents some of the register space.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubhnote)}(h9the memory long words are little-endian ('intel format').h]h)}(hhh]h=the memory long words are little-endian (‘intel format’).}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubhwarning)}(hXThis information was figured out from searching through the memory and registers, this information may not be correct and is certainly not complete, and was not derived from anything more than searching through the memory space with commands like: .. code-block:: none ivtvctl -O min=0x02000000,max=0x020000ff So take this as is, I'm always searching for more stuff, it's a large register space :-).h](h)}(hThis information was figured out from searching through the memory and registers, this information may not be correct and is certainly not complete, and was not derived from anything more than searching through the memory space with commands like:h]hThis information was figured out from searching through the memory and registers, this information may not be correct and is certainly not complete, and was not derived from anything more than searching through the memory space with commands like:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh literal_block)}(h(ivtvctl -O min=0x02000000,max=0x020000ffh]h(ivtvctl -O min=0x02000000,max=0x020000ff}hjsbah}(h]h ]h"]h$]h&]hhforcelanguagenonehighlight_args}uh1jhhhKhjubh)}(hYSo take this as is, I'm always searching for more stuff, it's a large register space :-).h]h]So take this as is, I’m always searching for more stuff, it’s a large register space :-).}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhhhhhhhNubh)}(hhh](h)}(h Memory Maph]h Memory Map}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhKubh)}(hThe cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0 (Base Address Register 0). The addresses here are offsets relative to the address held in BAR0.h]hThe cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0 (Base Address Register 0). The addresses here are offsets relative to the address held in BAR0.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubj)}(hX0x00000000-0x00ffffff Encoder memory space 0x00000000-0x0003ffff Encode.rom ???-??? MPEG buffer(s) ???-??? Raw video capture buffer(s) ???-??? Raw audio capture buffer(s) ???-??? Display buffers (6 or 9) 0x01000000-0x01ffffff Decoder memory space 0x01000000-0x0103ffff Decode.rom ???-??? MPEG buffers(s) 0x0114b000-0x0115afff Audio.rom (deprecated?) 0x02000000-0x0200ffff Register Spaceh]hX0x00000000-0x00ffffff Encoder memory space 0x00000000-0x0003ffff Encode.rom ???-??? MPEG buffer(s) ???-??? Raw video capture buffer(s) ???-??? Raw audio capture buffer(s) ???-??? Display buffers (6 or 9) 0x01000000-0x01ffffff Decoder memory space 0x01000000-0x0103ffff Decode.rom ???-??? MPEG buffers(s) 0x0114b000-0x0115afff Audio.rom (deprecated?) 0x02000000-0x0200ffff Register Space}hj_sbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhK#hj@hhubeh}(h] memory-mapah ]h"] memory mapah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Registersh]h Registers}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhhhhhK4ubh)}(hxThe registers occupy the 64k space starting at the 0x02000000 offset from BAR0. All of these registers are 32 bits wide.h]hxThe registers occupy the 64k space starting at the 0x02000000 offset from BAR0. All of these registers are 32 bits wide.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjwhhubj)}(hXDMA Registers 0x000-0xff: 0x00 - Control: 0=reset/cancel, 1=read, 2=write, 4=stop 0x04 - DMA status: 1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error 0x08 - pci DMA pointer for read link list 0x0c - pci DMA pointer for write link list 0x10 - read/write DMA enable: 1=read enable, 2=write enable 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes 0x18 - ?? 0x1c - always 0x20 or 32, smaller values slow down DMA transactions 0x20 - always value of 0x780a010a 0x24-0x3c - usually just random values??? 0x40 - Interrupt status 0x44 - Write a bit here and shows up in Interrupt status 0x40 0x48 - Interrupt Mask 0x4C - always value of 0xfffdffff, if changed to 0xffffffff DMA write interrupts break. 0x50 - always 0xffffffff 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are 3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the interrupt masks???). 0x60-0x7C - random values 0x80 - first write linked list reg, for Encoder Memory addr 0x84 - first write linked list reg, for pci memory addr 0x88 - first write linked list reg, for length of buffer in memory addr (|0x80000000 or this for last link) 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here from linked list addr in reg 0x0c, firmware must push through or something. 0xe0 - first (and only) read linked list reg, for pci memory addr 0xe4 - first (and only) read linked list reg, for Decoder memory addr 0xe8 - first (and only) read linked list reg, for length of buffer 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.h]hXDMA Registers 0x000-0xff: 0x00 - Control: 0=reset/cancel, 1=read, 2=write, 4=stop 0x04 - DMA status: 1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error 0x08 - pci DMA pointer for read link list 0x0c - pci DMA pointer for write link list 0x10 - read/write DMA enable: 1=read enable, 2=write enable 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes 0x18 - ?? 0x1c - always 0x20 or 32, smaller values slow down DMA transactions 0x20 - always value of 0x780a010a 0x24-0x3c - usually just random values??? 0x40 - Interrupt status 0x44 - Write a bit here and shows up in Interrupt status 0x40 0x48 - Interrupt Mask 0x4C - always value of 0xfffdffff, if changed to 0xffffffff DMA write interrupts break. 0x50 - always 0xffffffff 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are 3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the interrupt masks???). 0x60-0x7C - random values 0x80 - first write linked list reg, for Encoder Memory addr 0x84 - first write linked list reg, for pci memory addr 0x88 - first write linked list reg, for length of buffer in memory addr (|0x80000000 or this for last link) 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here from linked list addr in reg 0x0c, firmware must push through or something. 0xe0 - first (and only) read linked list reg, for pci memory addr 0xe4 - first (and only) read linked list reg, for Decoder memory addr 0xe8 - first (and only) read linked list reg, for length of buffer 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.}hjsbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhK9hjwhhubh)}(h1Memory locations for Encoder Buffers 0x700-0x7ff:h]h1Memory locations for Encoder Buffers 0x700-0x7ff:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjwhhubh)}(hThese registers show offsets of memory locations pertaining to each buffer area used for encoding, have to shift them by <<1 first.h]hThese registers show offsets of memory locations pertaining to each buffer area used for encoding, have to shift them by <<1 first.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjwhhubh bullet_list)}(hhh](h list_item)}(h0x07F8: Encoder SDRAM refreshh]h)}(hjh]h0x07F8: Encoder SDRAM refresh}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h!0x07FC: Encoder SDRAM pre-charge h]h)}(h 0x07FC: Encoder SDRAM pre-chargeh]h 0x07FC: Encoder SDRAM pre-charge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKehjwhhubh)}(h1Memory locations for Decoder Buffers 0x800-0x8ff:h]h1Memory locations for Decoder Buffers 0x800-0x8ff:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjwhhubh)}(hThese registers show offsets of memory locations pertaining to each buffer area used for decoding, have to shift them by <<1 first.h]hThese registers show offsets of memory locations pertaining to each buffer area used for decoding, have to shift them by <<1 first.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjwhhubj)}(hhh](j)}(h0x08F8: Decoder SDRAM refreshh]h)}(hj!h]h0x08F8: Decoder SDRAM refresh}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h!0x08FC: Decoder SDRAM pre-charge h]h)}(h 0x08FC: Decoder SDRAM pre-chargeh]h 0x08FC: Decoder SDRAM pre-charge}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhj6ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKmhjwhhubh)}(hOther memory locations:h]hOther memory locations:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjwhhubj)}(hhh](j)}(h$0x2800: Video Display Module controlh]h)}(hjgh]h$0x2800: Video Display Module control}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjeubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h"0x2D00: AO (audio output?) controlh]h)}(hj~h]h"0x2D00: AO (audio output?) control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshj|ubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x2D24: Bytes Flushedh]h)}(hjh]h0x2D24: Bytes Flushed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h*0x7000: LSB I2C write clock bit (inverted)h]h)}(hjh]h*0x7000: LSB I2C write clock bit (inverted)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h)0x7004: LSB I2C write data bit (inverted)h]h)}(hjh]h)0x7004: LSB I2C write data bit (inverted)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x7008: LSB I2C read clock bith]h)}(hjh]h0x7008: LSB I2C read clock bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x700c: LSB I2C read data bith]h)}(hjh]h0x700c: LSB I2C read data bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x9008: GPIO get input stateh]h)}(hjh]h0x9008: GPIO get input state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x900c: GPIO set output stateh]h)}(hjh]h0x900c: GPIO set output state}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h=0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)h]h)}(hj6h]h=0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hj4ubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x9050: SPU controlh]h)}(hjMh]h0x9050: SPU control}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjKubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x9054: Reset HW blocksh]h)}(hjdh]h0x9054: Reset HW blocks}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjbubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0x9058: VPU controlh]h)}(hj{h]h0x9058: VPU control}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjyubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h 0xA018: Bit6: interrupt pending?h]h)}(hjh]h 0xA018: Bit6: interrupt pending?}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubj)}(h0xA064: APU command h]h)}(h0xA064: APU commandh]h0xA064: APU command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjbhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKrhjwhhubeh}(h] registersah ]h"] registersah$]h&]uh1hhhhhhhhK4ubh)}(hhh](h)}(hInterrupt Status Registerh]hInterrupt Status Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThe definition of the bits in the interrupt status register 0x0040, and the interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to execute.h]hThe definition of the bits in the interrupt status register 0x0040, and the interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to execute.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hbit 31 Encoder Start Captureh]h)}(hjh]hbit 31 Encoder Start Capture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 30 Encoder EOSh]h)}(hjh]hbit 30 Encoder EOS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 29 Encoder VBI captureh]h)}(hjh]hbit 29 Encoder VBI capture}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h-bit 28 Encoder Video Input Module reset eventh]h)}(hj6h]h-bit 28 Encoder Video Input Module reset event}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj4ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 27 Encoder DMA completeh]h)}(hjMh]hbit 27 Encoder DMA complete}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjKubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hMbit 24 Decoder audio mode change detection event (through event notification)h]h)}(hjdh]hMbit 24 Decoder audio mode change detection event (through event notification)}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjbubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 22 Decoder data requesth]h)}(hj{h]hbit 22 Decoder data request}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 20 Decoder DMA completeh]h)}(hjh]hbit 20 Decoder DMA complete}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hbit 19 Decoder VBI re-insertionh]h)}(hjh]hbit 19 Decoder VBI re-insertion}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h)bit 18 Decoder DMA err (linked-list bad) h]h)}(h(bit 18 Decoder DMA err (linked-list bad)h]h(bit 18 Decoder DMA err (linked-list bad)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubeh}(h]interrupt-status-registerah ]h"]interrupt status registerah$]h&]uh1hhhhhhhhKubeh}(h]memory-at-cx2341x-chipsah ]h"]memory at cx2341x chipsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hMissing documentationh]hMissing documentation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(hEncoder API post(?)h]h)}(hjh]hEncoder API post(?)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hDecoder API post(?)h]h)}(hjh]hDecoder API post(?)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hDecoder VTRACE event h]h)}(hDecoder VTRACE eventh]hDecoder VTRACE event}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj.ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubeh}(h]missing-documentationah ]h"]missing documentationah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hThe cx2341x firmware uploadh]hThe cx2341x firmware upload}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThhhhhKubh)}(hGThis document describes how to upload the cx2341x firmware to the card.h]hGThis document describes how to upload the cx2341x firmware to the card.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjThhubh)}(hhh](h)}(h How to findh]h How to find}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshhhhhKubh)}(hlSee the web pages of the various projects that uses this chip for information on how to obtain the firmware.h]hlSee the web pages of the various projects that uses this chip for information on how to obtain the firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjshhubh)}(hCThe firmware stored in a Windows driver can be detected as follows:h]hCThe firmware stored in a Windows driver can be detected as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjshhubj)}(hhh](j)}(h"Each firmware image is 256k bytes.h]h)}(hjh]h"Each firmware image is 256k bytes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5The 1st 32-bit word of the Encoder image is 0x0000da7h]h)}(hjh]h5The 1st 32-bit word of the Encoder image is 0x0000da7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5The 1st 32-bit word of the Decoder image is 0x00003a7h]h)}(hjh]h5The 1st 32-bit word of the Decoder image is 0x00003a7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h1The 2nd 32-bit word of both images is 0xaa55bb66 h]h)}(h0The 2nd 32-bit word of both images is 0xaa55bb66h]h0The 2nd 32-bit word of both images is 0xaa55bb66}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjshhubeh}(h] how-to-findah ]h"] how to findah$]h&]uh1hhjThhhhhKubh)}(hhh](h)}(h How to loadh]h How to load}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj)}(hhh](j)}(h_Issue the FWapi command to stop the encoder if it is running. Wait for the command to complete.h]h)}(h_Issue the FWapi command to stop the encoder if it is running. Wait for the command to complete.h]h_Issue the FWapi command to stop the encoder if it is running. Wait for the command to complete.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj"ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h_Issue the FWapi command to stop the decoder if it is running. Wait for the command to complete.h]h)}(h_Issue the FWapi command to stop the decoder if it is running. Wait for the command to complete.h]h_Issue the FWapi command to stop the decoder if it is running. Wait for the command to complete.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hEIssue the I2C command to the digitizer to stop emitting VSYNC events.h]h)}(hjTh]hEIssue the I2C command to the digitizer to stop emitting VSYNC events.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h7Issue the FWapi command to halt the encoder's firmware.h]h)}(hjkh]h9Issue the FWapi command to halt the encoder’s firmware.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjiubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hSleep for 10ms.h]h)}(hjh]hSleep for 10ms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h7Issue the FWapi command to halt the decoder's firmware.h]h)}(hjh]h9Issue the FWapi command to halt the decoder’s firmware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hSleep for 10ms.h]h)}(hjh]hSleep for 10ms.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hEWrite 0x00000000 to register 0x2800 to stop the Video Display Module.h]h)}(hjh]hEWrite 0x00000000 to register 0x2800 to stop the Video Display Module.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hCWrite 0x00000005 to register 0x2D00 to stop the AO (audio output?).h]h)}(hjh]hCWrite 0x00000005 to register 0x2D00 to stop the AO (audio output?).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h5Write 0x00000000 to register 0xA064 to ping? the APU.h]h)}(hjh]h5Write 0x00000000 to register 0xA064 to ping? the APU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h4Write 0xFFFFFFFE to register 0x9058 to stop the VPU.h]h)}(hj h]h4Write 0xFFFFFFFE to register 0x9058 to stop the VPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h;Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.h]h)}(hj#h]h;Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj!ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h4Write 0x00000001 to register 0x9050 to stop the SPU.h]h)}(hj:h]h4Write 0x00000001 to register 0x9050 to stop the SPU.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hSleep for 10ms.h]h)}(hjQh]hSleep for 10ms.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hKWrite 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.h]h)}(hjhh]hMWrite 0x0000001A to register 0x07FC to init the Encoder SDRAM’s pre-charge.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjfubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hOWrite 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.h]h)}(hjh]hQWrite 0x80000640 to register 0x07F8 to init the Encoder SDRAM’s refresh to 1us.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hKWrite 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.h]h)}(hjh]hMWrite 0x0000001A to register 0x08FC to init the Decoder SDRAM’s pre-charge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hOWrite 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.h]h)}(hjh]hQWrite 0x80000640 to register 0x08F8 to init the Decoder SDRAM’s refresh to 1us.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h'Sleep for 512ms. (600ms is recommended)h]h)}(hjh]h'Sleep for 512ms. (600ms is recommended)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hJTransfer the encoder's firmware image to offset 0 in Encoder memory space.h]h)}(hjh]hLTransfer the encoder’s firmware image to offset 0 in Encoder memory space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hJTransfer the decoder's firmware image to offset 0 in Decoder memory space.h]h)}(hjh]hLTransfer the decoder’s firmware image to offset 0 in Decoder memory space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hYUse a read-modify-write operation to Clear bit 0 of register 0x9050 to re-enable the SPU.h]h)}(hYUse a read-modify-write operation to Clear bit 0 of register 0x9050 to re-enable the SPU.h]hYUse a read-modify-write operation to Clear bit 0 of register 0x9050 to re-enable the SPU.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hSleep for 1 second.h]h)}(hj!h]hSleep for 1 second.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h`Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058 to re-enable the VPU.h]h)}(h`Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058 to re-enable the VPU.h]h`Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058 to re-enable the VPU.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hSleep for 1 second.h]h)}(hjPh]hSleep for 1 second.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h>Issue status API commands to both firmware images to verify. h]h)}(hubah}(h]h ]h"]h$]h&]uh1jhj;hhhhhNubj)}(h1=16bit RGB 5:6:5h]h)}(hjWh]h1=16bit RGB 5:6:5}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjUubah}(h]h ]h"]h$]h&]uh1jhj;hhhhhNubj)}(h2=16bit ARGB 1:5:5:5h]h)}(hjnh]h2=16bit ARGB 1:5:5:5}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hjlubah}(h]h ]h"]h$]h&]uh1jhj;hhhhhNubj)}(h3=16bit ARGB 1:4:4:4h]h)}(hjh]h3=16bit ARGB 1:4:4:4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hjubah}(h]h ]h"]h$]h&]uh1jhj;hhhhhNubj)}(h4=32bit ARGB 8:8:8:8 h]h)}(h4=32bit ARGB 8:8:8:8h]h4=32bit ARGB 8:8:8:8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjubah}(h]h ]h"]h$]h&]uh1jhj;hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM\hj*hhubeh}(h]param-0ah ]h"]h$]param[0]ah&]uh1hhj hhhhhMZj Kubeh}(h]cx2341x-osd-set-pixel-formatah ]h"]cx2341x_osd_set_pixel_formatah$]h&]uh1hhj hhhhhMPubh)}(hhh](h)}(hCX2341X_OSD_GET_STATEh]hCX2341X_OSD_GET_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMeubh)}(h Enum: 68/0x44h]h Enum: 68/0x44}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMjubh)}(hQuery OSD stateh]hQuery OSD state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjhhubeh}(h]id4ah ]h"]h$] descriptionah&]uh1hhjhhhhhMjj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMoubj)}(hhh](j)}(hBit 0 0=off, 1=onh]h)}(hj$h]hBit 0 0=off, 1=on}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj"ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hBits 1:2 alpha controlh]h)}(hj;h]hBits 1:2 alpha control}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhj9ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hBits 3:5 pixel format h]h)}(hBits 3:5 pixel formath]hBits 3:5 pixel format}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjPubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMqhjhhubeh}(h]id5ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMoj Kubeh}(h]cx2341x-osd-get-stateah ]h"]cx2341x_osd_get_stateah$]h&]uh1hhj hhhhhMeubh)}(hhh](h)}(hCX2341X_OSD_SET_STATEh]hCX2341X_OSD_SET_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhMxubh)}(h Enum: 69/0x45h]h Enum: 69/0x45}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj~hhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM}ubh)}(h OSD switchh]h OSD switch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id6ah ]h"]h$] descriptionah&]uh1hhj~hhhhhM}j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h 0=off, 1=onh]h 0=off, 1=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id7ah ]h"]h$]jah&]uh1hhj~hhhhhMj Kubeh}(h]cx2341x-osd-set-stateah ]h"]cx2341x_osd_set_stateah$]h&]uh1hhj hhhhhMxubh)}(hhh](h)}(hCX2341X_OSD_GET_OSD_COORDSh]hCX2341X_OSD_GET_OSD_COORDS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 70/0x46h]h Enum: 70/0x46}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h3Retrieve coordinates of OSD area blended with videoh]h3Retrieve coordinates of OSD area blended with video}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id8ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMubh)}(hOSD buffer addressh]hOSD buffer address}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8hhubeh}(h]id9ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hhhhhMubh)}(hStride in pixelsh]hStride in pixels}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_hhubeh}(h]id10ah ]h"]h$]jg ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[2]h]h Result[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hLines in OSD bufferh]hLines in OSD buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]result-2ah ]h"]h$] result[2]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[3]h]h Result[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hHorizontal offset in bufferh]hHorizontal offset in buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]result-3ah ]h"]h$] result[3]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[4]h]h Result[4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hVertical offset in bufferh]hVertical offset in buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]result-4ah ]h"]h$] result[4]ah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-osd-get-osd-coordsah ]h"]cx2341x_osd_get_osd_coordsah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_SET_OSD_COORDSh]hCX2341X_OSD_SET_OSD_COORDS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 71/0x47h]h Enum: 71/0x47}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhMubh)}(h:Assign the coordinates of the OSD area to blend with videoh]h:Assign the coordinates of the OSD area to blend with video}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!hhubeh}(h]id11ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhhhhhMubh)}(hbuffer addressh]hbuffer address}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHhhubeh}(h]id12ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohhhhhMubh)}(hbuffer stride in pixelsh]hbuffer stride in pixels}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjohhubeh}(h]param-1ah ]h"]h$]param[1]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hlines in bufferh]hlines in buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]param-2ah ]h"]h$]param[2]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hhorizontal offseth]hhorizontal offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]param-3ah ]h"]h$]param[3]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hvertical offseth]hvertical offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]param-4ah ]h"]h$]param[4]ah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-osd-set-osd-coordsah ]h"]cx2341x_osd_set_osd_coordsah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_GET_SCREEN_COORDSh]hCX2341X_OSD_GET_SCREEN_COORDS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 72/0x48h]h Enum: 72/0x48}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhMubh)}(h$Retrieve OSD screen area coordinatesh]h$Retrieve OSD screen area coordinates}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubeh}(h]id13ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhMubh)}(htop left horizontal offseth]htop left horizontal offset}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubeh}(h]id14ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(htop left vertical offseth]htop left vertical offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id15ah ]h"]h$] result[1]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[2]h]h Result[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hbottom right horizontal offseth]hbottom right horizontal offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id16ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[3]h]h Result[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hbottom right vertical offseth]hbottom right vertical offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id17ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-osd-get-screen-coordsah ]h"]cx2341x_osd_get_screen_coordsah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_SET_SCREEN_COORDSh]hCX2341X_OSD_SET_SCREEN_COORDS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 73/0x49h]h Enum: 73/0x49}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h=Assign the coordinates of the screen area to blend with videoh]h=Assign the coordinates of the screen area to blend with video}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id18ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(htop left horizontal offseth]htop left horizontal offset}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubeh}(h]id19ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhMubh)}(htop left vertical offseth]htop left vertical offset}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhhubeh}(h]id20ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hbottom left horizontal offseth]hbottom left horizontal offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]id21ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubh)}(hbottom left vertical offseth]hbottom left vertical offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id22ah ]h"]h$]jah&]uh1hhjhhhhhM j Kubeh}(h]cx2341x-osd-set-screen-coordsah ]h"]cx2341x_osd_set_screen_coordsah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_GET_GLOBAL_ALPHAh]hCX2341X_OSD_GET_GLOBAL_ALPHA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 74/0x4Ah]h Enum: 74/0x4A}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hRetrieve OSD global alphah]hRetrieve OSD global alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id23ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhMubh)}(hglobal alpha: 0=off, 1=onh]hglobal alpha: 0=off, 1=on}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(hhubeh}(h]id24ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhM"ubh)}(hbits 0:7 global alphah]hbits 0:7 global alpha}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjOhhubeh}(h]id25ah ]h"]h$] result[1]ah&]uh1hhjhhhhhM"j Kubeh}(h]cx2341x-osd-get-global-alphaah ]h"]cx2341x_osd_get_global_alphaah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_SET_GLOBAL_ALPHAh]hCX2341X_OSD_SET_GLOBAL_ALPHA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhM)ubh)}(h Enum: 75/0x4Bh]h Enum: 75/0x4B}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj~hhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM.ubh)}(hUpdate global alphah]hUpdate global alpha}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjhhubeh}(h]id26ah ]h"]h$] descriptionah&]uh1hhj~hhhhhM.j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM3ubh)}(hglobal alpha: 0=off, 1=onh]hglobal alpha: 0=off, 1=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjhhubeh}(h]id27ah ]h"]h$]param[0]ah&]uh1hhj~hhhhhM3j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM8ubh)}(hglobal alpha (8 bits)h]hglobal alpha (8 bits)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjhhubeh}(h]id28ah ]h"]h$]param[1]ah&]uh1hhj~hhhhhM8j Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM=ubh)}(hlocal alpha: 0=on, 1=offh]hlocal alpha: 0=on, 1=off}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hjhhubeh}(h]id29ah ]h"]h$]param[2]ah&]uh1hhj~hhhhhM=j Kubeh}(h]cx2341x-osd-set-global-alphaah ]h"]cx2341x_osd_set_global_alphaah$]h&]uh1hhj hhhhhM)ubh)}(hhh](h)}(hCX2341X_OSD_SET_BLEND_COORDSh]hCX2341X_OSD_SET_BLEND_COORDS}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMDubh)}(h Enum: 78/0x4Ch]h Enum: 78/0x4C}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjAhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhMIubh)}(h1Move start of blending area within display bufferh]h1Move start of blending area within display buffer}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhj`hhubeh}(h]id30ah ]h"]h$] descriptionah&]uh1hhjAhhhhhMIj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMNubh)}(hhorizontal offset in bufferh]hhorizontal offset in buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjhhubeh}(h]id31ah ]h"]h$]param[0]ah&]uh1hhjAhhhhhMNj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMSubh)}(hvertical offset in bufferh]hvertical offset in buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjhhubeh}(h]id32ah ]h"]h$]param[1]ah&]uh1hhjAhhhhhMSj Kubeh}(h]cx2341x-osd-set-blend-coordsah ]h"]cx2341x_osd_set_blend_coordsah$]h&]uh1hhj hhhhhMDubh)}(hhh](h)}(hCX2341X_OSD_GET_FLICKER_STATEh]hCX2341X_OSD_GET_FLICKER_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMZubh)}(h Enum: 79/0x4Fh]h Enum: 79/0x4F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM_ubh)}(h'Retrieve flicker reduction module stateh]h'Retrieve flicker reduction module state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjhhubeh}(h]id33ah ]h"]h$] descriptionah&]uh1hhjhhhhhM_j Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMdubh)}(hflicker state: 0=off, 1=onh]hflicker state: 0=off, 1=on}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhj#hhubeh}(h]id34ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMdj Kubeh}(h]cx2341x-osd-get-flicker-stateah ]h"]cx2341x_osd_get_flicker_stateah$]h&]uh1hhj hhhhhMZubh)}(hhh](h)}(hCX2341X_OSD_SET_FLICKER_STATEh]hCX2341X_OSD_SET_FLICKER_STATE}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhhhhhMkubh)}(h Enum: 80/0x50h]h Enum: 80/0x50}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjRhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhhhhhMpubh)}(h"Set flicker reduction module stateh]h"Set flicker reduction module state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjqhhubeh}(h]id35ah ]h"]h$] descriptionah&]uh1hhjRhhhhhMpj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMuubh)}(hState: 0=off, 1=onh]hState: 0=off, 1=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjhhubeh}(h]id36ah ]h"]h$]param[0]ah&]uh1hhjRhhhhhMuj Kubeh}(h]cx2341x-osd-set-flicker-stateah ]h"]cx2341x_osd_set_flicker_stateah$]h&]uh1hhj hhhhhMkubh)}(hhh](h)}(hCX2341X_OSD_BLT_COPYh]hCX2341X_OSD_BLT_COPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM|ubh)}(h Enum: 82/0x52h]h Enum: 82/0x52}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hBLT copyh]hBLT copy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id37ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubj)}(hX'0000' zero '0001' ~destination AND ~source '0010' ~destination AND source '0011' ~destination '0100' destination AND ~source '0101' ~source '0110' destination XOR source '0111' ~destination OR ~source '1000' ~destination AND ~source '1001' destination XNOR source '1010' source '1011' ~destination OR source '1100' destination '1101' destination OR ~source '1110' destination OR source '1111' oneh]hX'0000' zero '0001' ~destination AND ~source '0010' ~destination AND source '0011' ~destination '0100' destination AND ~source '0101' ~source '0110' destination XOR source '0111' ~destination OR ~source '1000' ~destination AND ~source '1001' destination XNOR source '1010' source '1011' ~destination OR source '1100' destination '1101' destination OR ~source '1110' destination OR source '1111' one}hjsbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhMhj hhubeh}(h]id38ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubh)}(hResulting alpha blendingh]hResulting alpha blending}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubj)}(hhh](j)}(h'01' source_alphah]h)}(hjZh]h‘01’ source_alpha}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjUhhhhhNubj)}(h'10' destination_alphah]h)}(hjqh]h‘10’ destination_alpha}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubah}(h]h ]h"]h$]h&]uh1jhjUhhhhhNubj)}(h['11' source_alpha*destination_alpha+1 (zero if both source and destination alpha are zero) h]h)}(hZ'11' source_alpha*destination_alpha+1 (zero if both source and destination alpha are zero)h]h^‘11’ source_alpha*destination_alpha+1 (zero if both source and destination alpha are zero)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjUhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj6hhubeh}(h]id39ah ]h"]h$]param[1]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hX'00' output_pixel = source_pixel '01' if source_alpha=0: output_pixel = destination_pixel if 256 > source_alpha > 1: output_pixel = ((source_alpha + 1)*source_pixel + (255 - source_alpha)*destination_pixel)/256 '10' if destination_alpha=0: output_pixel = source_pixel if 255 > destination_alpha > 0: output_pixel = ((255 - destination_alpha)*source_pixel + (destination_alpha + 1)*destination_pixel)/256 '11' if source_alpha=0: source_temp = 0 if source_alpha=255: source_temp = source_pixel*256 if 255 > source_alpha > 0: source_temp = source_pixel*(source_alpha + 1) if destination_alpha=0: destination_temp = 0 if destination_alpha=255: destination_temp = destination_pixel*256 if 255 > destination_alpha > 0: destination_temp = destination_pixel*(destination_alpha + 1) output_pixel = (source_temp + destination_temp)/256h]hX'00' output_pixel = source_pixel '01' if source_alpha=0: output_pixel = destination_pixel if 256 > source_alpha > 1: output_pixel = ((source_alpha + 1)*source_pixel + (255 - source_alpha)*destination_pixel)/256 '10' if destination_alpha=0: output_pixel = source_pixel if 255 > destination_alpha > 0: output_pixel = ((255 - destination_alpha)*source_pixel + (destination_alpha + 1)*destination_pixel)/256 '11' if source_alpha=0: source_temp = 0 if source_alpha=255: source_temp = source_pixel*256 if 255 > source_alpha > 0: source_temp = source_pixel*(source_alpha + 1) if destination_alpha=0: destination_temp = 0 if destination_alpha=255: destination_temp = destination_pixel*256 if 255 > destination_alpha > 0: destination_temp = destination_pixel*(destination_alpha + 1) output_pixel = (source_temp + destination_temp)/256}hjsbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhMhjhhubeh}(h]id40ah ]h"]h$]param[2]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hwidthh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id41ah ]h"]h$]param[3]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hheighth]hheight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id42ah ]h"]h$]j ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMubh)}(hdestination pixel maskh]hdestination pixel mask}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubeh}(h]param-5ah ]h"]h$]param[5]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[6]h]hParam[6]}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhhhMubh)}(h#destination rectangle start addressh]h#destination rectangle start address}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIhhubeh}(h]param-6ah ]h"]h$]param[6]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[7]h]hParam[7]}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhMubh)}(hdestination stride in dwordsh]hdestination stride in dwords}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjphhubeh}(h]param-7ah ]h"]h$]param[7]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[8]h]hParam[8]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hsource stride in dwordsh]hsource stride in dwords}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]param-8ah ]h"]h$]param[8]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[9]h]hParam[9]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hsource rectangle start addressh]hsource rectangle start address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]param-9ah ]h"]h$]param[9]ah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-osd-blt-copyah ]h"]cx2341x_osd_blt_copyah$]h&]uh1hhj hhhhhM|ubh)}(hhh](h)}(hCX2341X_OSD_BLT_FILLh]hCX2341X_OSD_BLT_FILL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 83/0x53h]h Enum: 83/0x53}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hBLT fill colorh]hBLT fill color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]id43ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubh)}(hSame as Param[0] on API 0x52h]hSame as Param[0] on API 0x52}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubeh}(h]id44ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhMubh)}(hSame as Param[1] on API 0x52h]hSame as Param[1] on API 0x52}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZhhubeh}(h]id45ah ]h"]h$]param[1]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hSame as Param[2] on API 0x52h]hSame as Param[2] on API 0x52}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id46ah ]h"]h$]param[2]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hwidthh]hwidth}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id47ah ]h"]h$]param[3]ah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubh)}(hheighth]hheight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]id48ah ]h"]h$]param[4]ah&]uh1hhjhhhhhM j Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hdestination pixel maskh]hdestination pixel mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id49ah ]h"]h$]jGah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[6]h]hParam[6]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h#destination rectangle start addressh]h#destination rectangle start address}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id50ah ]h"]h$]jnah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[7]h]hParam[7]}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhMubh)}(hdestination stride in dwordsh]hdestination stride in dwords}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBhhubeh}(h]id51ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[8]h]hParam[8]}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhMubh)}(hcolor fill valueh]hcolor fill value}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjhhhubeh}(h]id52ah ]h"]h$]jah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-osd-blt-fillah ]h"]cx2341x_osd_blt_fillah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hCX2341X_OSD_BLT_TEXTh]hCX2341X_OSD_BLT_TEXT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM&ubh)}(h Enum: 84/0x54h]h Enum: 84/0x54}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM+ubh)}(hBLT for 8 bit alpha text sourceh]hBLT for 8 bit alpha text source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjhhubeh}(h]id53ah ]h"]h$] descriptionah&]uh1hhjhhhhhM+j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM0ubh)}(hSame as Param[0] on API 0x52h]hSame as Param[0] on API 0x52}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjhhubeh}(h]id54ah ]h"]h$]param[0]ah&]uh1hhjhhhhhM0j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM5ubh)}(hSame as Param[1] on API 0x52h]hSame as Param[1] on API 0x52}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjhhubeh}(h]id55ah ]h"]h$]param[1]ah&]uh1hhjhhhhhM5j Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhM:ubh)}(hSame as Param[2] on API 0x52h]hSame as Param[2] on API 0x52}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj*hhubeh}(h]id56ah ]h"]h$]param[2]ah&]uh1hhjhhhhhM:j Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhM?ubh)}(hwidthh]hwidth}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjQhhubeh}(h]id57ah ]h"]h$]param[3]ah&]uh1hhjhhhhhM?j Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhhhhhMDubh)}(hheighth]hheight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjxhhubeh}(h]id58ah ]h"]h$]param[4]ah&]uh1hhjhhhhhMDj Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMIubh)}(hdestination pixel maskh]hdestination pixel mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjhhubeh}(h]id59ah ]h"]h$]param[5]ah&]uh1hhjhhhhhMIj Kubh)}(hhh](h)}(hParam[6]h]hParam[6]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMNubh)}(h#destination rectangle start addressh]h#destination rectangle start address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjhhubeh}(h]id60ah ]h"]h$]param[6]ah&]uh1hhjhhhhhMNj Kubh)}(hhh](h)}(hParam[7]h]hParam[7]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMSubh)}(hdestination stride in dwordsh]hdestination stride in dwords}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjhhubeh}(h]id61ah ]h"]h$]param[7]ah&]uh1hhjhhhhhMSj Kubh)}(hhh](h)}(hParam[8]h]hParam[8]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMXubh)}(hsource stride in dwordsh]hsource stride in dwords}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjhhubeh}(h]id62ah ]h"]h$]param[8]ah&]uh1hhjhhhhhMXj Kubh)}(hhh](h)}(hParam[9]h]hParam[9]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhM]ubh)}(hsource rectangle start addressh]hsource rectangle start address}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hj;hhubeh}(h]id63ah ]h"]h$]jah&]uh1hhjhhhhhM]j Kubh)}(hhh](h)}(h Param[10]h]h Param[10]}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahhhhhMbubh)}(hcolor fill valueh]hcolor fill value}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjahhubeh}(h]param-10ah ]h"]h$] param[10]ah&]uh1hhjhhhhhMbj Kubeh}(h]cx2341x-osd-blt-textah ]h"]cx2341x_osd_blt_textah$]h&]uh1hhj hhhhhM&ubh)}(hhh](h)}(h"CX2341X_OSD_SET_FRAMEBUFFER_WINDOWh]h"CX2341X_OSD_SET_FRAMEBUFFER_WINDOW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMiubh)}(h Enum: 86/0x56h]h Enum: 86/0x56}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMnubh)}(hwPositions the main output window on the screen. The coordinates must be such that the entire window fits on the screen.h]hwPositions the main output window on the screen. The coordinates must be such that the entire window fits on the screen.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphjhhubeh}(h]id64ah ]h"]h$] descriptionah&]uh1hhjhhhhhMnj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMtubh)}(h window widthh]h window width}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjhhubeh}(h]id65ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMtj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMyubh)}(h window heighth]h window height}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjhhubeh}(h]id66ah ]h"]h$]param[1]ah&]uh1hhjhhhhhMyj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhM~ubh)}(h(top left window corner horizontal offseth]h(top left window corner horizontal offset}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubeh}(h]id67ah ]h"]h$]param[2]ah&]uh1hhjhhhhhM~j Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhhhhhMubh)}(h&top left window corner vertical offseth]h&top left window corner vertical offset}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKhhubeh}(h]id68ah ]h"]h$]param[3]ah&]uh1hhjhhhhhMj Kubeh}(h]"cx2341x-osd-set-framebuffer-windowah ]h"]"cx2341x_osd_set_framebuffer_windowah$]h&]uh1hhj hhhhhMiubh)}(hhh](h)}(hCX2341X_OSD_SET_CHROMA_KEYh]hCX2341X_OSD_SET_CHROMA_KEY}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhhhhhMubh)}(h Enum: 96/0x60h]h Enum: 96/0x60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjzhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hChroma key switch and colorh]hChroma key switch and color}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id69ah ]h"]h$] descriptionah&]uh1hhjzhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hstate: 0=off, 1=onh]hstate: 0=off, 1=on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id70ah ]h"]h$]param[0]ah&]uh1hhjzhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hcolorh]hcolor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id71ah ]h"]h$]param[1]ah&]uh1hhjzhhhhhMj Kubeh}(h]cx2341x-osd-set-chroma-keyah ]h"]cx2341x_osd_set_chroma_keyah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h#CX2341X_OSD_GET_ALPHA_CONTENT_INDEXh]h#CX2341X_OSD_GET_ALPHA_CONTENT_INDEX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 97/0x61h]h Enum: 97/0x61}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMubh)}(hRetrieve alpha content indexh]hRetrieve alpha content index}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubeh}(h]id72ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hhhhhMubh)}(halpha content index, Range 0:15h]halpha content index, Range 0:15}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\hhubeh}(h]id73ah ]h"]h$] result[0]ah&]uh1hhjhhhhhMj Kubeh}(h]#cx2341x-osd-get-alpha-content-indexah ]h"]#cx2341x_osd_get_alpha_content_indexah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h#CX2341X_OSD_SET_ALPHA_CONTENT_INDEXh]h#CX2341X_OSD_SET_ALPHA_CONTENT_INDEX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(h Enum: 98/0x62h]h Enum: 98/0x62}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hAssign alpha content indexh]hAssign alpha content index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id74ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(halpha content index, range 0:15h]halpha content index, range 0:15}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id75ah ]h"]h$]param[0]ah&]uh1hhjhhhhhMj Kubeh}(h]#cx2341x-osd-set-alpha-content-indexah ]h"]#cx2341x_osd_set_alpha_content_indexah$]h&]uh1hhj hhhhhMubeh}(h]osd-firmware-api-descriptionah ]h"]osd firmware api descriptionah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h Encoder firmware API descriptionh]h Encoder firmware API description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_PING_FWh]hCX2341X_ENC_PING_FW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hEnum: 128/0x80h]hEnum: 128/0x80}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(h Descriptionh]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMubh)}(hADoes nothing. Can be used to check if the firmware is responding.h]hADoes nothing. Can be used to check if the firmware is responding.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8hhubeh}(h]id76ah ]h"]h$] descriptionah&]uh1hhjhhhhhMj Kubeh}(h]cx2341x-enc-ping-fwah ]h"]cx2341x_enc_ping_fwah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_START_CAPTUREh]hCX2341X_ENC_START_CAPTURE}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghhhhhMubh)}(hEnum: 129/0x81h]hEnum: 129/0x81}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjghhubh)}(hhh](h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hCommences the capture of video, audio and/or VBI data. All encoding parameters must be initialized prior to this API call. Captures frames continuously or until a predefined number of frames have been captured.h]hCommences the capture of video, audio and/or VBI data. All encoding parameters must be initialized prior to this API call. Captures frames continuously or until a predefined number of frames have been captured.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]id77ah ]h"]h$] descriptionah&]uh1hhjghhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hCapture stream type:h]hCapture stream type:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(h.- 0=MPEG - 1=Raw - 2=Raw passthrough - 3=VBI h]j)}(hhh](j)}(h0=MPEGh]h)}(hjh]h0=MPEG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1=Rawh]h)}(hjh]h1=Raw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h2=Raw passthroughh]h)}(hj h]h2=Raw passthrough}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h3=VBI h]h)}(h3=VBIh]h3=VBI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubeh}(h]id78ah ]h"]h$]param[0]ah&]uh1hhjghhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjD hhhhhMubh)}(hBitmask:h]hBitmask:}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjD hhubj)}(h- Bit 0 when set, captures YUV - Bit 1 when set, captures PCM audio - Bit 2 when set, captures VBI (same as param[0]=3) - Bit 3 when set, the capture destination is the decoder (same as param[0]=2) - Bit 4 when set, the capture destination is the host h]j)}(hhh](j)}(hBit 0 when set, captures YUVh]h)}(hjl h]hBit 0 when set, captures YUV}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjj ubah}(h]h ]h"]h$]h&]uh1jhjg ubj)}(h"Bit 1 when set, captures PCM audioh]h)}(hj h]h"Bit 1 when set, captures PCM audio}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjg ubj)}(h1Bit 2 when set, captures VBI (same as param[0]=3)h]h)}(hj h]h1Bit 2 when set, captures VBI (same as param[0]=3)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjg ubj)}(hKBit 3 when set, the capture destination is the decoder (same as param[0]=2)h]h)}(hKBit 3 when set, the capture destination is the decoder (same as param[0]=2)h]hKBit 3 when set, the capture destination is the decoder (same as param[0]=2)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjg ubj)}(h4Bit 4 when set, the capture destination is the host h]h)}(h3Bit 4 when set, the capture destination is the hosth]h3Bit 4 when set, the capture destination is the host}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjg ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjc ubah}(h]h ]h"]h$]h&]uh1jhhhMhjD hhubh)}(h7this parameter is only meaningful for RAW capture type.h]h)}(hj h]h7this parameter is only meaningful for RAW capture type.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhjD hhhhhNubeh}(h]id79ah ]h"]h$]param[1]ah&]uh1hhjghhhhhMj Kubeh}(h]cx2341x-enc-start-captureah ]h"]cx2341x_enc_start_captureah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_STOP_CAPTUREh]hCX2341X_ENC_STOP_CAPTURE}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhMubh)}(hEnum: 130/0x82h]hEnum: 130/0x82}(hj#!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj4!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1!hhhhhMubh)}(hEnds a capture in progressh]hEnds a capture in progress}(hjB!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1!hhubeh}(h]id80ah ]h"]h$] descriptionah&]uh1hhj!hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj[!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX!hhhhhMubj)}(hhh](j)}(h$0=stop at end of GOP (generates IRQ)h]h)}(hjn!h]h$0=stop at end of GOP (generates IRQ)}(hjp!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjl!ubah}(h]h ]h"]h$]h&]uh1jhji!hhhhhNubj)}(h1=stop immediate (no IRQ) h]h)}(h1=stop immediate (no IRQ)h]h1=stop immediate (no IRQ)}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhji!hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjX!hhubeh}(h]id81ah ]h"]h$]param[0]ah&]uh1hhj!hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhMubh)}(h-Stream type to stop, see param[0] of API 0x81h]h-Stream type to stop, see param[0] of API 0x81}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj!hhubeh}(h]id82ah ]h"]h$]param[1]ah&]uh1hhj!hhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhM ubh)}(h!Subtype, see param[1] of API 0x81h]h!Subtype, see param[1] of API 0x81}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!hhubeh}(h]id83ah ]h"]h$]param[2]ah&]uh1hhj!hhhhhM j Kubeh}(h]cx2341x-enc-stop-captureah ]h"]cx2341x_enc_stop_captureah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_AUDIO_IDh]hCX2341X_ENC_SET_AUDIO_ID}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhhhMubh)}(hEnum: 137/0x89h]hEnum: 137/0x89}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj!"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhMubh)}(h;Assigns the transport stream ID of the encoded audio streamh]h;Assigns the transport stream ID of the encoded audio stream}(hj/"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubeh}(h]id84ah ]h"]h$] descriptionah&]uh1hhj!hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjH"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE"hhhhhMubh)}(hAudio Stream IDh]hAudio Stream ID}(hjV"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjE"hhubeh}(h]id85ah ]h"]h$]param[0]ah&]uh1hhj!hhhhhMj Kubeh}(h]cx2341x-enc-set-audio-idah ]h"]cx2341x_enc_set_audio_idah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_VIDEO_IDh]hCX2341X_ENC_SET_VIDEO_ID}(hjw"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt"hhhhhM$ubh)}(hEnum: 139/0x8Bh]hEnum: 139/0x8B}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjt"hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM)ubh)}(hSet video transport stream IDh]hSet video transport stream ID}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj"hhubeh}(h]id86ah ]h"]h$] descriptionah&]uh1hhjt"hhhhhM)j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM.ubh)}(hVideo stream IDh]hVideo stream ID}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj"hhubeh}(h]id87ah ]h"]h$]param[0]ah&]uh1hhjt"hhhhhM.j Kubeh}(h]cx2341x-enc-set-video-idah ]h"]cx2341x_enc_set_video_idah$]h&]uh1hhjhhhhhM$ubh)}(hhh](h)}(hCX2341X_ENC_SET_PCR_IDh]hCX2341X_ENC_SET_PCR_ID}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM5ubh)}(hEnum: 141/0x8Dh]hEnum: 141/0x8D}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj"hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhM:ubh)}(h/Assigns the transport stream ID for PCR packetsh]h/Assigns the transport stream ID for PCR packets}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj#hhubeh}(h]id88ah ]h"]h$] descriptionah&]uh1hhj"hhhhhM:j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj2#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/#hhhhhM?ubh)}(h PCR Stream IDh]h PCR Stream ID}(hj@#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj/#hhubeh}(h]id89ah ]h"]h$]param[0]ah&]uh1hhj"hhhhhM?j Kubeh}(h]cx2341x-enc-set-pcr-idah ]h"]cx2341x_enc_set_pcr_idah$]h&]uh1hhjhhhhhM5ubh)}(hhh](h)}(hCX2341X_ENC_SET_FRAME_RATEh]hCX2341X_ENC_SET_FRAME_RATE}(hja#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^#hhhhhMFubh)}(hEnum: 143/0x8Fh]hEnum: 143/0x8F}(hjo#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj^#hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}#hhhhhMKubh)}(h?Set video frames per second. Change occurs at start of new GOP.h]h?Set video frames per second. Change occurs at start of new GOP.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj}#hhubeh}(h]id90ah ]h"]h$] descriptionah&]uh1hhj^#hhhhhMKj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMPubj)}(hhh](j)}(h0=30fpsh]h)}(hj#h]h0=30fps}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj#ubah}(h]h ]h"]h$]h&]uh1jhj#hhhhhNubj)}(h 1=25fps h]h)}(h1=25fpsh]h1=25fps}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj#ubah}(h]h ]h"]h$]h&]uh1jhj#hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMRhj#hhubeh}(h]id91ah ]h"]h$]param[0]ah&]uh1hhj^#hhhhhMPj Kubeh}(h]cx2341x-enc-set-frame-rateah ]h"]cx2341x_enc_set_frame_rateah$]h&]uh1hhjhhhhhMFubh)}(hhh](h)}(hCX2341X_ENC_SET_FRAME_SIZEh]hCX2341X_ENC_SET_FRAME_SIZE}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMXubh)}(hEnum: 145/0x91h]hEnum: 145/0x91}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhj#hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhM]ubh)}(h(Select video stream encoding resolution.h]h(Select video stream encoding resolution.}(hj-$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hj$hhubeh}(h]id92ah ]h"]h$] descriptionah&]uh1hhj#hhhhhM]j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjF$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC$hhhhhMbubh)}(hHeight in lines. Default 480h]hHeight in lines. Default 480}(hjT$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjC$hhubeh}(h]id93ah ]h"]h$]param[0]ah&]uh1hhj#hhhhhMbj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjm$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj$hhhhhMgubh)}(hWidth in pixels. Default 720h]hWidth in pixels. Default 720}(hj{$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjj$hhubeh}(h]id94ah ]h"]h$]param[1]ah&]uh1hhj#hhhhhMgj Kubeh}(h]cx2341x-enc-set-frame-sizeah ]h"]cx2341x_enc_set_frame_sizeah$]h&]uh1hhjhhhhhMXubh)}(hhh](h)}(hCX2341X_ENC_SET_BIT_RATEh]hCX2341X_ENC_SET_BIT_RATE}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhMnubh)}(hEnum: 149/0x95h]hEnum: 149/0x95}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphj$hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhMsubh)}(h$Assign average video stream bitrate.h]h$Assign average video stream bitrate.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj$hhubeh}(h]id95ah ]h"]h$] descriptionah&]uh1hhj$hhhhhMsj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhMxubh)}(h&0=variable bitrate, 1=constant bitrateh]h&0=variable bitrate, 1=constant bitrate}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj$hhubeh}(h]id96ah ]h"]h$]param[0]ah&]uh1hhj$hhhhhMxj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj %hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhM}ubh)}(hbitrate in bits per secondh]hbitrate in bits per second}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubeh}(h]id97ah ]h"]h$]param[1]ah&]uh1hhj$hhhhhM}j Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj0%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-%hhhhhMubh)}(h/peak bitrate in bits per second, divided by 400h]h/peak bitrate in bits per second, divided by 400}(hj>%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-%hhubeh}(h]id98ah ]h"]h$]param[2]ah&]uh1hhj$hhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjW%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT%hhhhhMubh)}(hCMux bitrate in bits per second, divided by 400. May be 0 (default).h]hCMux bitrate in bits per second, divided by 400. May be 0 (default).}(hje%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjT%hhubeh}(h]id99ah ]h"]h$]param[3]ah&]uh1hhj$hhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hj~%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{%hhhhhMubh)}(hRate Control VBR Paddingh]hRate Control VBR Padding}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{%hhubeh}(h]id100ah ]h"]h$]param[4]ah&]uh1hhj$hhhhhMj Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhMubh)}(hVBV Buffer used by encoderh]hVBV Buffer used by encoder}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hW#) Param\[3\] and Param\[4\] seem to be always 0 #) Param\[5\] doesn't seem to be used.h]henumerated_list)}(hhh](j)}(h-Param\[3\] and Param\[4\] seem to be always 0h]h)}(hj%h]h-Param[3] and Param[4] seem to be always 0}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(h#Param\[5\] doesn't seem to be used.h]h)}(hj%h]h%Param[5] doesn’t seem to be used.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1j%hj%ubah}(h]h ]h"]h$]h&]uh1hhj%hhhNhNubeh}(h]id101ah ]h"]h$]param[5]ah&]uh1hhj$hhhhhMj Kubeh}(h]cx2341x-enc-set-bit-rateah ]h"]cx2341x_enc_set_bit_rateah$]h&]uh1hhjhhhhhMnubh)}(hhh](h)}(hCX2341X_ENC_SET_GOP_PROPERTIESh]hCX2341X_ENC_SET_GOP_PROPERTIES}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(hEnum: 151/0x97h]hEnum: 151/0x97}(hj*&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj;&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8&hhhhhMubh)}(hSetup the GOP structureh]hSetup the GOP structure}(hjI&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8&hhubeh}(h]id102ah ]h"]h$] descriptionah&]uh1hhj&hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjb&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_&hhhhhMubh)}(hGOP size (maximum is 34)h]hGOP size (maximum is 34)}(hjp&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_&hhubeh}(h]id103ah ]h"]h$]param[0]ah&]uh1hhj&hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(h}Number of B frames between the I and P frame, plus 1. For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3h]h}Number of B frames between the I and P frame, plus 1. For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(h.GOP size must be a multiple of (B-frames + 1).h]h)}(hj&h]h.GOP size must be a multiple of (B-frames + 1).}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhNubeh}(h]id104ah ]h"]h$]param[1]ah&]uh1hhj&hhhhhMj Kubeh}(h]cx2341x-enc-set-gop-propertiesah ]h"]cx2341x_enc_set_gop_propertiesah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_ASPECT_RATIOh]hCX2341X_ENC_SET_ASPECT_RATIO}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(hEnum: 153/0x99h]hEnum: 153/0x99}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhMubh)}(heSets the encoding aspect ratio. Changes in the aspect ratio take effect at the start of the next GOP.h]heSets the encoding aspect ratio. Changes in the aspect ratio take effect at the start of the next GOP.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubeh}(h]id105ah ]h"]h$] descriptionah&]uh1hhj&hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubj)}(hhh](j)}(h'0000' forbiddenh]h)}(hj('h]h‘0000’ forbidden}(hj*'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&'ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubj)}(h'0001' 1:1 squareh]h)}(hj?'h]h‘0001’ 1:1 square}(hjA'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj='ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubj)}(h '0010' 4:3h]h)}(hjV'h]h‘0010’ 4:3}(hjX'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjT'ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubj)}(h '0011' 16:9h]h)}(hjm'h]h‘0011’ 16:9}(hjo'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjk'ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubj)}(h '0100' 2.21:1h]h)}(hj'h]h‘0100’ 2.21:1}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubj)}(h'0101' to '1111' reserved h]h)}(h'0101' to '1111' reservedh]h!‘0101’ to ‘1111’ reserved}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhj#'hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj'hhubeh}(h]id106ah ]h"]h$]param[0]ah&]uh1hhj&hhhhhMj Kubeh}(h]cx2341x-enc-set-aspect-ratioah ]h"]cx2341x_enc_set_aspect_ratioah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_DNR_FILTER_MODEh]hCX2341X_ENC_SET_DNR_FILTER_MODE}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubh)}(hEnum: 155/0x9Bh]hEnum: 155/0x9B}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubh)}(h-Assign Dynamic Noise Reduction operating modeh]h-Assign Dynamic Noise Reduction operating mode}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubeh}(h]id107ah ]h"]h$] descriptionah&]uh1hhj'hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj (hhhhhMubh)}(hZBit0: Spatial filter, set=auto, clear=manual Bit1: Temporal filter, set=auto, clear=manualh]hZBit0: Spatial filter, set=auto, clear=manual Bit1: Temporal filter, set=auto, clear=manual}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj (hhubeh}(h]id108ah ]h"]h$]param[0]ah&]uh1hhj'hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj7(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4(hhhhhMubh)}(hMedian filter:h]hMedian filter:}(hjE(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4(hhubj)}(hhh](j)}(h 0=Disabledh]h)}(hjX(h]h 0=Disabled}(hjZ(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjV(ubah}(h]h ]h"]h$]h&]uh1jhjS(hhhhhNubj)}(h 1=Horizontalh]h)}(hjo(h]h 1=Horizontal}(hjq(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjm(ubah}(h]h ]h"]h$]h&]uh1jhjS(hhhhhNubj)}(h 2=Verticalh]h)}(hj(h]h 2=Vertical}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhjS(hhhhhNubj)}(h 3=Horiz/Verth]h)}(hj(h]h 3=Horiz/Vert}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhjS(hhhhhNubj)}(h 4=Diagonal h]h)}(h 4=Diagonalh]h 4=Diagonal}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhjS(hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj4(hhubeh}(h]id109ah ]h"]h$]param[1]ah&]uh1hhj'hhhhhMj Kubeh}(h]cx2341x-enc-set-dnr-filter-modeah ]h"]cx2341x_enc_set_dnr_filter_modeah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h CX2341X_ENC_SET_DNR_FILTER_PROPSh]h CX2341X_ENC_SET_DNR_FILTER_PROPS}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhMubh)}(hEnum: 157/0x9Dh]hEnum: 157/0x9D}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhMubh)}(h|These Dynamic Noise Reduction filter values are only meaningful when the respective filter is set to "manual" (See API 0x9B)h]hThese Dynamic Noise Reduction filter values are only meaningful when the respective filter is set to “manual” (See API 0x9B)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(hhubeh}(h]id110ah ]h"]h$] descriptionah&]uh1hhj(hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj))hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&)hhhhhMubh)}(h%Spatial filter: default 0, range 0:15h]h%Spatial filter: default 0, range 0:15}(hj7)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&)hhubeh}(h]id111ah ]h"]h$]param[0]ah&]uh1hhj(hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjP)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM)hhhhhMubh)}(h&Temporal filter: default 0, range 0:31h]h&Temporal filter: default 0, range 0:31}(hj^)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjM)hhubeh}(h]id112ah ]h"]h$]param[1]ah&]uh1hhj(hhhhhMj Kubeh}(h] cx2341x-enc-set-dnr-filter-propsah ]h"] cx2341x_enc_set_dnr_filter_propsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_CORING_LEVELSh]hCX2341X_ENC_SET_CORING_LEVELS}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|)hhhhhMubh)}(hEnum: 159/0x9Fh]hEnum: 159/0x9F}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj|)hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMubh)}(h8Assign Dynamic Noise Reduction median filter properties.h]h8Assign Dynamic Noise Reduction median filter properties.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj)hhubeh}(h]id113ah ]h"]h$] descriptionah&]uh1hhj|)hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhM ubh)}(hUThreshold above which the luminance median filter is enabled. Default: 0, range 0:255h]hUThreshold above which the luminance median filter is enabled. Default: 0, range 0:255}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubeh}(h]id114ah ]h"]h$]param[0]ah&]uh1hhj|)hhhhhM j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMubh)}(hWThreshold below which the luminance median filter is enabled. Default: 255, range 0:255h]hWThreshold below which the luminance median filter is enabled. Default: 255, range 0:255}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubeh}(h]id115ah ]h"]h$]param[1]ah&]uh1hhj|)hhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhMubh)}(hWThreshold above which the chrominance median filter is enabled. Default: 0, range 0:255h]hWThreshold above which the chrominance median filter is enabled. Default: 0, range 0:255}(hj!*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubeh}(h]id116ah ]h"]h$]param[2]ah&]uh1hhj|)hhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hj:*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7*hhhhhMubh)}(hYThreshold below which the chrominance median filter is enabled. Default: 255, range 0:255h]hYThreshold below which the chrominance median filter is enabled. Default: 255, range 0:255}(hjH*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj7*hhubeh}(h]id117ah ]h"]h$]param[3]ah&]uh1hhj|)hhhhhMj Kubeh}(h]cx2341x-enc-set-coring-levelsah ]h"]cx2341x_enc_set_coring_levelsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h#CX2341X_ENC_SET_SPATIAL_FILTER_TYPEh]h#CX2341X_ENC_SET_SPATIAL_FILTER_TYPE}(hji*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf*hhhhhM'ubh)}(hEnum: 161/0xA1h]hEnum: 161/0xA1}(hjw*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjf*hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhM,ubh)}(h#Assign spatial prefilter parametersh]h#Assign spatial prefilter parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hj*hhubeh}(h]id118ah ]h"]h$] descriptionah&]uh1hhjf*hhhhhM,j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhM1ubh)}(hLuminance filterh]hLuminance filter}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hj*hhubj)}(hhh](j)}(h0=Offh]h)}(hj*h]h0=Off}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj*ubah}(h]h ]h"]h$]h&]uh1jhj*hhhhhNubj)}(h1=1D Horizontalh]h)}(hj*h]h1=1D Horizontal}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj*ubah}(h]h ]h"]h$]h&]uh1jhj*hhhhhNubj)}(h 2=1D Verticalh]h)}(hj*h]h 2=1D Vertical}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj*ubah}(h]h ]h"]h$]h&]uh1jhj*hhhhhNubj)}(h3=2D H/V Separable (default)h]h)}(hj+h]h3=2D H/V Separable (default)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj+ubah}(h]h ]h"]h$]h&]uh1jhj*hhhhhNubj)}(h4=2D Symmetric non-separable h]h)}(h4=2D Symmetric non-separableh]h4=2D Symmetric non-separable}(hj.+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj*+ubah}(h]h ]h"]h$]h&]uh1jhj*hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM5hj*hhubeh}(h]id119ah ]h"]h$]param[0]ah&]uh1hhjf*hhhhhM1j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjS+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP+hhhhhM<ubh)}(hChrominance filterh]hChrominance filter}(hja+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjP+hhubj)}(hhh](j)}(h0=Offh]h)}(hjt+h]h0=Off}(hjv+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjr+ubah}(h]h ]h"]h$]h&]uh1jhjo+hhhhhNubj)}(h1=1D Horizontal (default) h]h)}(h1=1D Horizontal (default)h]h1=1D Horizontal (default)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj+ubah}(h]h ]h"]h$]h&]uh1jhjo+hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM@hjP+hhubeh}(h]id120ah ]h"]h$]param[1]ah&]uh1hhjf*hhhhhM<j Kubeh}(h]#cx2341x-enc-set-spatial-filter-typeah ]h"]#cx2341x_enc_set_spatial_filter_typeah$]h&]uh1hhjhhhhhM'ubh)}(hhh](h)}(hCX2341X_ENC_SET_VBI_LINEh]hCX2341X_ENC_SET_VBI_LINE}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhMFubh)}(hEnum: 183/0xB7h]hEnum: 183/0xB7}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj+hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhMKubh)}(hSelects VBI line number.h]hSelects VBI line number.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj+hhubeh}(h]id121ah ]h"]h$] descriptionah&]uh1hhj+hhhhhMKj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhMPubj)}(hhh](j)}(hBits 0:4 line numberh]h)}(hj,h]hBits 0:4 line number}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj,ubah}(h]h ]h"]h$]h&]uh1jhj,hhhhhNubj)}(h1Bit 31 0=top_field, 1=bottom_fieldh]h)}(hj*,h]h1Bit 31 0=top_field, 1=bottom_field}(hj,,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj(,ubah}(h]h ]h"]h$]h&]uh1jhj,hhhhhNubj)}(h,Bits 0:31 all set specifies "all lines" h]h)}(h+Bits 0:31 all set specifies "all lines"h]h/Bits 0:31 all set specifies “all lines”}(hjC,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj?,ubah}(h]h ]h"]h$]h&]uh1jhj,hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMRhj+hhubeh}(h]id122ah ]h"]h$]param[0]ah&]uh1hhj+hhhhhMPj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjh,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje,hhhhhMWubh)}(h4VBI line information features: 0=disabled, 1=enabledh]h4VBI line information features: 0=disabled, 1=enabled}(hjv,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhje,hhubeh}(h]id123ah ]h"]h$]param[1]ah&]uh1hhj+hhhhhMWj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhM\ubh)}(hMSlicing: 0=None, 1=Closed Caption Almost certainly not implemented. Set to 0.h]hMSlicing: 0=None, 1=Closed Caption Almost certainly not implemented. Set to 0.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj,hhubeh}(h]id124ah ]h"]h$]param[2]ah&]uh1hhj+hhhhhM\j Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhMbubh)}(hKLuminance samples in this line. Almost certainly not implemented. Set to 0.h]hKLuminance samples in this line. Almost certainly not implemented. Set to 0.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhj,hhubeh}(h]id125ah ]h"]h$]param[3]ah&]uh1hhj+hhhhhMbj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhhhMhubh)}(hLChrominance samples in this line Almost certainly not implemented. Set to 0.h]hLChrominance samples in this line Almost certainly not implemented. Set to 0.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj,hhubeh}(h]id126ah ]h"]h$]param[4]ah&]uh1hhj+hhhhhMhj Kubeh}(h]cx2341x-enc-set-vbi-lineah ]h"]cx2341x_enc_set_vbi_lineah$]h&]uh1hhjhhhhhMFubh)}(hhh](h)}(hCX2341X_ENC_SET_STREAM_TYPEh]hCX2341X_ENC_SET_STREAM_TYPE}(hj -hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj -hhhhhMpubh)}(hEnum: 185/0xB9h]hEnum: 185/0xB9}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhj -hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj+-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(-hhhhhMuubh)}(hAssign stream typeh]hAssign stream type}(hj9-hhhNhNubah}(h]h ]h"]h$]h&]uh1^hhhhMwhj(-hhubh)}(h{Transport stream is not working in recent firmwares. And in older firmwares the timestamps in the TS seem to be unreliable.h]h)}(h{Transport stream is not working in recent firmwares. And in older firmwares the timestamps in the TS seem to be unreliable.h]h{Transport stream is not working in recent firmwares. And in older firmwares the timestamps in the TS seem to be unreliable.}(hjK-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjG-ubah}(h]h ]h"]h$]h&]uh1hhj(-hhhhhNubeh}(h]id127ah ]h"]h$] descriptionah&]uh1hhj -hhhhhMuj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg-hhhhhMubj)}(hhh](j)}(h0=Program streamh]h)}(hj}-h]h0=Program stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h1=Transport streamh]h)}(hj-h]h1=Transport stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h2=MPEG1 streamh]h)}(hj-h]h2=MPEG1 stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h3=PES A/V streamh]h)}(hj-h]h3=PES A/V stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h5=PES Video streamh]h)}(hj-h]h5=PES Video stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h7=PES Audio streamh]h)}(hj-h]h7=PES Audio stream}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h 10=DVD streamh]h)}(hj.h]h 10=DVD stream}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h 11=VCD streamh]h)}(hj.h]h 11=VCD stream}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h12=SVCD streamh]h)}(hj5.h]h12=SVCD stream}(hj7.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3.ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h13=DVD_S1 streamh]h)}(hjL.h]h13=DVD_S1 stream}(hjN.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJ.ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubj)}(h14=DVD_S2 stream h]h)}(h14=DVD_S2 streamh]h14=DVD_S2 stream}(hje.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhja.ubah}(h]h ]h"]h$]h&]uh1jhjx-hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjg-hhubeh}(h]id128ah ]h"]h$]param[0]ah&]uh1hhj -hhhhhMj Kubeh}(h]cx2341x-enc-set-stream-typeah ]h"]cx2341x_enc_set_stream_typeah$]h&]uh1hhjhhhhhMpubh)}(hhh](h)}(hCX2341X_ENC_SET_OUTPUT_PORTh]hCX2341X_ENC_SET_OUTPUT_PORT}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhMubh)}(hEnum: 187/0xBBh]hEnum: 187/0xBB}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhMubh)}(hAssign stream output port. Normally 0 when the data is copied through the PCI bus (DMA), and 1 when the data is streamed to another chip (pvrusb and cx88-blackbird).h]hAssign stream output port. Normally 0 when the data is copied through the PCI bus (DMA), and 1 when the data is streamed to another chip (pvrusb and cx88-blackbird).}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.hhubeh}(h]id129ah ]h"]h$] descriptionah&]uh1hhj.hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhMubj)}(hhh](j)}(h0=Memory (default)h]h)}(hj.h]h0=Memory (default)}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubj)}(h 1=Streamingh]h)}(hj/h]h 1=Streaming}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubj)}(h 2=Serial h]h)}(h2=Serialh]h2=Serial}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj.hhubeh}(h]id130ah ]h"]h$]param[0]ah&]uh1hhj.hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj@/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=/hhhhhMubh)}(hUnknown, but leaving this to 0 seems to work best. Indications are that this might have to do with USB support, although passing anything but 0 only breaks things.h]hUnknown, but leaving this to 0 seems to work best. Indications are that this might have to do with USB support, although passing anything but 0 only breaks things.}(hjN/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=/hhubeh}(h]id131ah ]h"]h$]param[1]ah&]uh1hhj.hhhhhMj Kubeh}(h]cx2341x-enc-set-output-portah ]h"]cx2341x_enc_set_output_portah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h CX2341X_ENC_SET_AUDIO_PROPERTIESh]h CX2341X_ENC_SET_AUDIO_PROPERTIES}(hjo/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl/hhhhhMubh)}(hEnum: 189/0xBDh]hEnum: 189/0xBD}(hj}/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjl/hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhMubh)}(hISet audio stream properties, may be called while encoding is in progress.h]hISet audio stream properties, may be called while encoding is in progress.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/hhubh)}(hXUAll bitfields are consistent with ISO11172 documentation except bits 2:3 which ISO docs define as: - '11' Layer I - '10' Layer II - '01' Layer III - '00' Undefined This discrepancy may indicate a possible error in the documentation. Testing indicated that only Layer II is actually working, and that the minimum bitrate should be 192 kbps.h](h)}(hbAll bitfields are consistent with ISO11172 documentation except bits 2:3 which ISO docs define as:h]hbAll bitfields are consistent with ISO11172 documentation except bits 2:3 which ISO docs define as:}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubj)}(hhh](j)}(h '11' Layer Ih]h)}(hj/h]h‘11’ Layer I}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(h '10' Layer IIh]h)}(hj/h]h‘10’ Layer II}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(h'01' Layer IIIh]h)}(hj/h]h‘01’ Layer III}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(h'00' Undefined h]h)}(h'00' Undefinedh]h‘00’ Undefined}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj/ubh)}(hThis discrepancy may indicate a possible error in the documentation. Testing indicated that only Layer II is actually working, and that the minimum bitrate should be 192 kbps.h]hThis discrepancy may indicate a possible error in the documentation. Testing indicated that only Layer II is actually working, and that the minimum bitrate should be 192 kbps.}(hj"0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/ubeh}(h]h ]h"]h$]h&]uh1hhj/hhhhhNubeh}(h]id132ah ]h"]h$] descriptionah&]uh1hhjl/hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjA0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>0hhhhhMubh)}(hBitmask:h]hBitmask:}(hjO0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>0hhubj)}(hX_ 0:1 '00' 44.1Khz '01' 48Khz '10' 32Khz '11' reserved 2:3 '01'=Layer I '10'=Layer II 4:7 Bitrate: Index | Layer I | Layer II ------+-------------+------------ '0000' | free format | free format '0001' | 32 kbit/s | 32 kbit/s '0010' | 64 kbit/s | 48 kbit/s '0011' | 96 kbit/s | 56 kbit/s '0100' | 128 kbit/s | 64 kbit/s '0101' | 160 kbit/s | 80 kbit/s '0110' | 192 kbit/s | 96 kbit/s '0111' | 224 kbit/s | 112 kbit/s '1000' | 256 kbit/s | 128 kbit/s '1001' | 288 kbit/s | 160 kbit/s '1010' | 320 kbit/s | 192 kbit/s '1011' | 352 kbit/s | 224 kbit/s '1100' | 384 kbit/s | 256 kbit/s '1101' | 416 kbit/s | 320 kbit/s '1110' | 448 kbit/s | 384 kbit/s .. note:: For Layer II, not all combinations of total bitrate and mode are allowed. See ISO11172-3 3-Annex B, Table 3-B.2 8:9 '00'=Stereo '01'=JointStereo '10'=Dual '11'=Mono .. note:: The cx23415 cannot decode Joint Stereo properly. 10:11 Mode Extension used in joint_stereo mode. In Layer I and II they indicate which subbands are in intensity_stereo. All other subbands are coded in stereo. '00' subbands 4-31 in intensity_stereo, bound==4 '01' subbands 8-31 in intensity_stereo, bound==8 '10' subbands 12-31 in intensity_stereo, bound==12 '11' subbands 16-31 in intensity_stereo, bound==16 12:13 Emphasis: '00' None '01' 50/15uS '10' reserved '11' CCITT J.17 14 CRC: '0' off '1' on 15 Copyright: '0' off '1' on 16 Generation: '0' copy '1' originalh]hX_ 0:1 '00' 44.1Khz '01' 48Khz '10' 32Khz '11' reserved 2:3 '01'=Layer I '10'=Layer II 4:7 Bitrate: Index | Layer I | Layer II ------+-------------+------------ '0000' | free format | free format '0001' | 32 kbit/s | 32 kbit/s '0010' | 64 kbit/s | 48 kbit/s '0011' | 96 kbit/s | 56 kbit/s '0100' | 128 kbit/s | 64 kbit/s '0101' | 160 kbit/s | 80 kbit/s '0110' | 192 kbit/s | 96 kbit/s '0111' | 224 kbit/s | 112 kbit/s '1000' | 256 kbit/s | 128 kbit/s '1001' | 288 kbit/s | 160 kbit/s '1010' | 320 kbit/s | 192 kbit/s '1011' | 352 kbit/s | 224 kbit/s '1100' | 384 kbit/s | 256 kbit/s '1101' | 416 kbit/s | 320 kbit/s '1110' | 448 kbit/s | 384 kbit/s .. note:: For Layer II, not all combinations of total bitrate and mode are allowed. See ISO11172-3 3-Annex B, Table 3-B.2 8:9 '00'=Stereo '01'=JointStereo '10'=Dual '11'=Mono .. note:: The cx23415 cannot decode Joint Stereo properly. 10:11 Mode Extension used in joint_stereo mode. In Layer I and II they indicate which subbands are in intensity_stereo. All other subbands are coded in stereo. '00' subbands 4-31 in intensity_stereo, bound==4 '01' subbands 8-31 in intensity_stereo, bound==8 '10' subbands 12-31 in intensity_stereo, bound==12 '11' subbands 16-31 in intensity_stereo, bound==16 12:13 Emphasis: '00' None '01' 50/15uS '10' reserved '11' CCITT J.17 14 CRC: '0' off '1' on 15 Copyright: '0' off '1' on 16 Generation: '0' copy '1' original}hj]0sbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhMhj>0hhubeh}(h]id133ah ]h"]h$]param[0]ah&]uh1hhjl/hhhhhMj Kubeh}(h] cx2341x-enc-set-audio-propertiesah ]h"] cx2341x_enc_set_audio_propertiesah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_HALT_FWh]hCX2341X_ENC_HALT_FW}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}0hhhhhMubh)}(hEnum: 195/0xC3h]hEnum: 195/0xC3}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}0hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhMubh)}(hbThe firmware is halted and no further API calls are serviced until the firmware is uploaded again.h]hbThe firmware is halted and no further API calls are serviced until the firmware is uploaded again.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubeh}(h]id134ah ]h"]h$] descriptionah&]uh1hhj}0hhhhhMj Kubeh}(h]cx2341x-enc-halt-fwah ]h"]cx2341x_enc_halt_fwah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_GET_VERSIONh]hCX2341X_ENC_GET_VERSION}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhMubh)}(hEnum: 196/0xC4h]hEnum: 196/0xC4}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj0hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhM$ubh)}(h,Returns the version of the encoder firmware.h]h,Returns the version of the encoder firmware.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hj0hhubeh}(h]id135ah ]h"]h$] descriptionah&]uh1hhj0hhhhhM$j Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhM)ubh)}(hIVersion bitmask: - Bits 0:15 build - Bits 16:23 minor - Bits 24:31 majorh]hIVersion bitmask: - Bits 0:15 build - Bits 16:23 minor - Bits 24:31 major}(hj"1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj1hhubeh}(h]id136ah ]h"]h$] result[0]ah&]uh1hhj0hhhhhM)j Kubeh}(h]cx2341x-enc-get-versionah ]h"]cx2341x_enc_get_versionah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_GOP_CLOSUREh]hCX2341X_ENC_SET_GOP_CLOSURE}(hjC1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@1hhhhhM3ubh)}(hEnum: 197/0xC5h]hEnum: 197/0xC5}(hjQ1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj@1hhubh)}(hhh](h)}(h Descriptionh]h Description}(hjb1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_1hhhhhM8ubh)}(h$Assigns the GOP open/close property.h]h$Assigns the GOP open/close property.}(hjp1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj_1hhubeh}(h]id137ah ]h"]h$] descriptionah&]uh1hhj@1hhhhhM8j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhM=ubj)}(hhh](j)}(h0=Openh]h)}(hj1h]h0=Open}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj1ubah}(h]h ]h"]h$]h&]uh1jhj1hhhhhNubj)}(h 1=Closed h]h)}(h1=Closedh]h1=Closed}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hj1ubah}(h]h ]h"]h$]h&]uh1jhj1hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM?hj1hhubeh}(h]id138ah ]h"]h$]param[0]ah&]uh1hhj@1hhhhhM=j Kubeh}(h]cx2341x-enc-set-gop-closureah ]h"]cx2341x_enc_set_gop_closureah$]h&]uh1hhjhhhhhM3ubh)}(hhh](h)}(hCX2341X_ENC_GET_SEQ_ENDh]hCX2341X_ENC_GET_SEQ_END}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhMEubh)}(hEnum: 198/0xC6h]hEnum: 198/0xC6}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhj1hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhMJubh)}(hObtains the sequence end code of the encoder's buffer. When a capture is started a number of interrupts are still generated, the last of which will have Result[0] set to 1 and Result[1] will contain the size of the buffer.h]hObtains the sequence end code of the encoder’s buffer. When a capture is started a number of interrupts are still generated, the last of which will have Result[0] set to 1 and Result[1] will contain the size of the buffer.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj1hhubeh}(h]id139ah ]h"]h$] descriptionah&]uh1hhj1hhhhhMJj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj(2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%2hhhhhMRubh)}(h(State of the transfer (1 if last buffer)h]h(State of the transfer (1 if last buffer)}(hj62hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj%2hhubeh}(h]id140ah ]h"]h$] result[0]ah&]uh1hhj1hhhhhMRj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjO2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL2hhhhhMWubh)}(hRIf Result[0] is 1, this contains the size of the last buffer, undefined otherwise.h]hRIf Result[0] is 1, this contains the size of the last buffer, undefined otherwise.}(hj]2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjL2hhubeh}(h]id141ah ]h"]h$] result[1]ah&]uh1hhj1hhhhhMWj Kubeh}(h]cx2341x-enc-get-seq-endah ]h"]cx2341x_enc_get_seq_endah$]h&]uh1hhjhhhhhMEubh)}(hhh](h)}(hCX2341X_ENC_SET_PGM_INDEX_INFOh]hCX2341X_ENC_SET_PGM_INDEX_INFO}(hj~2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{2hhhhhM_ubh)}(hEnum: 199/0xC7h]hEnum: 199/0xC7}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj{2hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhMdubh)}(hISets the Program Index Information. The information is stored as follows:h]hISets the Program Index Information. The information is stored as follows:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhj2hhubj)}(hXDstruct info { u32 length; // Length of this frame u32 offset_low; // Offset in the file of the u32 offset_high; // start of this frame u32 mask1; // Bits 0-2 are the type mask: // 1=I, 2=P, 4=B // 0=End of Program Index, other fields // are invalid. u32 pts; // The PTS of the frame u32 mask2; // Bit 0 is bit 32 of the pts. }; u32 table_ptr; struct info index[400];h]hXDstruct info { u32 length; // Length of this frame u32 offset_low; // Offset in the file of the u32 offset_high; // start of this frame u32 mask1; // Bits 0-2 are the type mask: // 1=I, 2=P, 4=B // 0=End of Program Index, other fields // are invalid. u32 pts; // The PTS of the frame u32 mask2; // Bit 0 is bit 32 of the pts. }; u32 table_ptr; struct info index[400];}hj2sbah}(h]h ]h"]h$]h&]hhj'j(cj*}uh1jhhhMihj2hhubh)}(h\The table_ptr is the encoder memory address in the table were *new* entries will be written.h](h>The table_ptr is the encoder memory address in the table were }(hj2hhhNhNubhemphasis)}(h*new*h]hnew}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j2hj2ubh entries will be written.}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMyhj2hhubh)}(h7This is a ringbuffer, so the table_ptr will wraparound.h]h)}(hj2h]h7This is a ringbuffer, so the table_ptr will wraparound.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hj2ubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhNubeh}(h]id142ah ]h"]h$] descriptionah&]uh1hhj{2hhhhhMdj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj 3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 3hhhhhMubh)}(hOPicture Mask: - 0=No index capture - 1=I frames - 3=I,P frames - 7=I,P,B framesh]hOPicture Mask: - 0=No index capture - 1=I frames - 3=I,P frames - 7=I,P,B frames}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj 3hhubh)}(h:(Seems to be ignored, it always indexes I, P and B frames)h]h:(Seems to be ignored, it always indexes I, P and B frames)}(hj)3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj 3hhubeh}(h]id143ah ]h"]h$]param[0]ah&]uh1hhj{2hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjB3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?3hhhhhMubh)}(hElements requested (up to 400)h]hElements requested (up to 400)}(hjP3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?3hhubeh}(h]id144ah ]h"]h$]param[1]ah&]uh1hhj{2hhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hji3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf3hhhhhMubh)}(h7Offset in the encoder memory of the start of the table.h]h7Offset in the encoder memory of the start of the table.}(hjw3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjf3hhubeh}(h]id145ah ]h"]h$] result[0]ah&]uh1hhj{2hhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubh)}(h8Number of allocated elements up to a maximum of Param[1]h]h8Number of allocated elements up to a maximum of Param[1]}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubeh}(h]id146ah ]h"]h$] result[1]ah&]uh1hhj{2hhhhhMj Kubeh}(h]cx2341x-enc-set-pgm-index-infoah ]h"]cx2341x_enc_set_pgm_index_infoah$]h&]uh1hhjhhhhhM_ubh)}(hhh](h)}(hCX2341X_ENC_SET_VBI_CONFIGh]hCX2341X_ENC_SET_VBI_CONFIG}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubh)}(hEnum: 200/0xC8h]hEnum: 200/0xC8}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubh)}(hConfigure VBI settingsh]hConfigure VBI settings}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubeh}(h]id147ah ]h"]h$] descriptionah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(hBitmap:h]hBitmap:}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubj)}(hX0 Mode '0' Sliced, '1' Raw 1:3 Insertion: '000' insert in extension & user data '001' insert in private packets '010' separate stream and user data '111' separate stream and private data 8:15 Stream ID (normally 0xBD)h]hX0 Mode '0' Sliced, '1' Raw 1:3 Insertion: '000' insert in extension & user data '001' insert in private packets '010' separate stream and user data '111' separate stream and private data 8:15 Stream ID (normally 0xBD)}hj!4sbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhMhj4hhubeh}(h]id148ah ]h"]h$]param[0]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj<4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj94hhhhhMubh)}(h5Frames per interrupt (max 8). Only valid in raw mode.h]h5Frames per interrupt (max 8). Only valid in raw mode.}(hjJ4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj94hhubeh}(h]id149ah ]h"]h$]param[1]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjc4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`4hhhhhMubh)}(h-Total raw VBI frames. Only valid in raw mode.h]h-Total raw VBI frames. Only valid in raw mode.}(hjq4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`4hhubeh}(h]id150ah ]h"]h$]param[2]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(h Start codesh]h Start codes}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubeh}(h]id151ah ]h"]h$]param[3]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(h Stop codesh]h Stop codes}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubeh}(h]id152ah ]h"]h$]param[4]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(hLines per frameh]hLines per frame}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubeh}(h]id153ah ]h"]h$]param[5]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(hParam[6]h]hParam[6]}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(h Byte per lineh]h Byte per line}(hj 5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubeh}(h]id154ah ]h"]h$]param[6]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj&5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#5hhhhhMubh)}(hBObserved frames per interrupt in raw mode only. Rage 1 to Param[1]h]hBObserved frames per interrupt in raw mode only. Rage 1 to Param[1]}(hj45hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#5hhubeh}(h]id155ah ]h"]h$] result[0]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjM5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ5hhhhhMubh)}(h:Observed number of frames in raw mode. Range 1 to Param[2]h]h:Observed number of frames in raw mode. Range 1 to Param[2]}(hj[5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJ5hhubeh}(h]id156ah ]h"]h$] result[1]ah&]uh1hhj3hhhhhMj Kubh)}(hhh](h)}(h Result[2]h]h Result[2]}(hjt5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq5hhhhhMubh)}(h&Memory offset to start or raw VBI datah]h&Memory offset to start or raw VBI data}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjq5hhubeh}(h]id157ah ]h"]h$] result[2]ah&]uh1hhj3hhhhhMj Kubeh}(h]cx2341x-enc-set-vbi-configah ]h"]cx2341x_enc_set_vbi_configah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_DMA_BLOCK_SIZEh]hCX2341X_ENC_SET_DMA_BLOCK_SIZE}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMubh)}(hEnum: 201/0xC9h]hEnum: 201/0xC9}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMubh)}(hSet DMA transfer block sizeh]hSet DMA transfer block size}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubeh}(h]id158ah ]h"]h$] descriptionah&]uh1hhj5hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMubh)}(hqDMA transfer block size in bytes or frames. When unit is bytes, supported block sizes are 2^7, 2^8 and 2^9 bytes.h]hqDMA transfer block size in bytes or frames. When unit is bytes, supported block sizes are 2^7, 2^8 and 2^9 bytes.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubeh}(h]id159ah ]h"]h$]param[0]ah&]uh1hhj5hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 6hhhhhMubh)}(hUnit: 0=bytes, 1=framesh]hUnit: 0=bytes, 1=frames}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj 6hhubeh}(h]id160ah ]h"]h$]param[1]ah&]uh1hhj5hhhhhMj Kubeh}(h]cx2341x-enc-set-dma-block-sizeah ]h"]cx2341x_enc_set_dma_block_sizeah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h#CX2341X_ENC_GET_PREV_DMA_INFO_MB_10h]h#CX2341X_ENC_GET_PREV_DMA_INFO_MB_10}(hj?6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<6hhhhhMubh)}(hEnum: 202/0xCAh]hEnum: 202/0xCA}(hjM6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<6hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj^6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[6hhhhhMubh)}(hsReturns information on the previous DMA transfer in conjunction with bit 27 of the interrupt mask. Uses mailbox 10.h]hsReturns information on the previous DMA transfer in conjunction with bit 27 of the interrupt mask. Uses mailbox 10.}(hjl6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[6hhubeh}(h]id161ah ]h"]h$] descriptionah&]uh1hhj<6hhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubh)}(hType of streamh]hType of stream}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubeh}(h]id162ah ]h"]h$] result[0]ah&]uh1hhj<6hhhhhMj Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhM ubh)}(hAddress Offseth]hAddress Offset}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6hhubeh}(h]id163ah ]h"]h$] result[1]ah&]uh1hhj<6hhhhhM j Kubh)}(hhh](h)}(h Result[2]h]h Result[2]}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubh)}(hMaximum size of transferh]hMaximum size of transfer}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubeh}(h]id164ah ]h"]h$] result[2]ah&]uh1hhj<6hhhhhMj Kubeh}(h]#cx2341x-enc-get-prev-dma-info-mb-10ah ]h"]#cx2341x_enc_get_prev_dma_info_mb_10ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h"CX2341X_ENC_GET_PREV_DMA_INFO_MB_9h]h"CX2341X_ENC_GET_PREV_DMA_INFO_MB_9}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubh)}(hEnum: 203/0xCBh]hEnum: 203/0xCB}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj!7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhMubh)}(hxReturns information on the previous DMA transfer in conjunction with bit 27 or 18 of the interrupt mask. Uses mailbox 9.h]hxReturns information on the previous DMA transfer in conjunction with bit 27 or 18 of the interrupt mask. Uses mailbox 9.}(hj/7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7hhubeh}(h]id165ah ]h"]h$] descriptionah&]uh1hhj6hhhhhMj Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hjH7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE7hhhhhM!ubh)}(hStatus bits: - 0 read completed - 1 write completed - 2 DMA read error - 3 DMA write error - 4 Scatter-Gather array errorh]hStatus bits: - 0 read completed - 1 write completed - 2 DMA read error - 3 DMA write error - 4 Scatter-Gather array error}(hjV7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjE7hhubeh}(h]id166ah ]h"]h$] result[0]ah&]uh1hhj6hhhhhM!j Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hjo7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl7hhhhhM+ubh)}(hDMA typeh]hDMA type}(hj}7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjl7hhubeh}(h]id167ah ]h"]h$] result[1]ah&]uh1hhj6hhhhhM+j Kubh)}(hhh](h)}(h Result[2]h]h Result[2]}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhM0ubh)}(h"Presentation Time Stamp bits 0..31h]h"Presentation Time Stamp bits 0..31}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj7hhubeh}(h]id168ah ]h"]h$] result[2]ah&]uh1hhj6hhhhhM0j Kubh)}(hhh](h)}(h Result[3]h]h Result[3]}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhM5ubh)}(hPresentation Time Stamp bit 32h]hPresentation Time Stamp bit 32}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj7hhubeh}(h]id169ah ]h"]h$] result[3]ah&]uh1hhj6hhhhhM5j Kubeh}(h]"cx2341x-enc-get-prev-dma-info-mb-9ah ]h"]"cx2341x_enc_get_prev_dma_info_mb_9ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SCHED_DMA_TO_HOSTh]hCX2341X_ENC_SCHED_DMA_TO_HOST}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhM<ubh)}(hEnum: 204/0xCCh]hEnum: 204/0xCC}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj7hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj 8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMAubh)}(hSetup DMA to host operationh]hSetup DMA to host operation}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj8hhubeh}(h]id170ah ]h"]h$] descriptionah&]uh1hhj7hhhhhMAj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj28hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/8hhhhhMFubh)}(hMemory address of link listh]hMemory address of link list}(hj@8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj/8hhubeh}(h]id171ah ]h"]h$]param[0]ah&]uh1hhj7hhhhhMFj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjY8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV8hhhhhMKubh)}(h)Length of link list (wtf: what units ???)h]h)Length of link list (wtf: what units ???)}(hjg8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjV8hhubeh}(h]id172ah ]h"]h$]param[1]ah&]uh1hhj7hhhhhMKj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}8hhhhhMPubh)}(hDMA type (0=MPEG)h]hDMA type (0=MPEG)}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj}8hhubeh}(h]id173ah ]h"]h$]param[2]ah&]uh1hhj7hhhhhMPj Kubeh}(h]cx2341x-enc-sched-dma-to-hostah ]h"]cx2341x_enc_sched_dma_to_hostah$]h&]uh1hhjhhhhhM<ubh)}(hhh](h)}(hCX2341X_ENC_INITIALIZE_INPUTh]hCX2341X_ENC_INITIALIZE_INPUT}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMWubh)}(hEnum: 205/0xCDh]hEnum: 205/0xCD}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhj8hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhM\ubh)}(hInitializes the video inputh]hInitializes the video input}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj8hhubeh}(h]id174ah ]h"]h$] descriptionah&]uh1hhj8hhhhhM\j Kubeh}(h]cx2341x-enc-initialize-inputah ]h"]cx2341x_enc_initialize_inputah$]h&]uh1hhjhhhhhMWubh)}(hhh](h)}(hCX2341X_ENC_SET_FRAME_DROP_RATEh]hCX2341X_ENC_SET_FRAME_DROP_RATE}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMcubh)}(hEnum: 208/0xD0h]hEnum: 208/0xD0}(hj 9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj8hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMhubh)}(h9For each frame captured, skip specified number of frames.h]h9For each frame captured, skip specified number of frames.}(hj*9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj9hhubeh}(h]id175ah ]h"]h$] descriptionah&]uh1hhj8hhhhhMhj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjC9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@9hhhhhMmubh)}(hNumber of frames to skiph]hNumber of frames to skip}(hjQ9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj@9hhubeh}(h]id176ah ]h"]h$]param[0]ah&]uh1hhj8hhhhhMmj Kubeh}(h]cx2341x-enc-set-frame-drop-rateah ]h"]cx2341x_enc_set_frame_drop_rateah$]h&]uh1hhjhhhhhMcubh)}(hhh](h)}(hCX2341X_ENC_PAUSE_ENCODERh]hCX2341X_ENC_PAUSE_ENCODER}(hjr9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo9hhhhhMtubh)}(hEnum: 210/0xD2h]hEnum: 210/0xD2}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjo9hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMyubh)}(hJDuring a pause condition, all frames are dropped instead of being encoded.h]hJDuring a pause condition, all frames are dropped instead of being encoded.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj9hhubeh}(h]id177ah ]h"]h$] descriptionah&]uh1hhjo9hhhhhMyj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhM~ubj)}(hhh](j)}(h0=Pause encodingh]h)}(hj9h]h0=Pause encoding}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9hhhhhNubj)}(h1=Continue encoding h]h)}(h1=Continue encodingh]h1=Continue encoding}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj9hhubeh}(h]id178ah ]h"]h$]param[0]ah&]uh1hhjo9hhhhhM~j Kubeh}(h]cx2341x-enc-pause-encoderah ]h"]cx2341x_enc_pause_encoderah$]h&]uh1hhjhhhhhMtubh)}(hhh](h)}(hCX2341X_ENC_REFRESH_INPUTh]hCX2341X_ENC_REFRESH_INPUT}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhMubh)}(hEnum: 211/0xD3h]hEnum: 211/0xD3}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj0:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-:hhhhhMubh)}(hRefreshes the video inputh]hRefreshes the video input}(hj>:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-:hhubeh}(h]id179ah ]h"]h$] descriptionah&]uh1hhj:hhhhhMj Kubeh}(h]cx2341x-enc-refresh-inputah ]h"]cx2341x_enc_refresh_inputah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_COPYRIGHTh]hCX2341X_ENC_SET_COPYRIGHT}(hj_:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\:hhhhhMubh)}(hEnum: 212/0xD4h]hEnum: 212/0xD4}(hjm:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\:hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj~:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{:hhhhhMubh)}(hSets stream copyright propertyh]hSets stream copyright property}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{:hhubeh}(h]id180ah ]h"]h$] descriptionah&]uh1hhj\:hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhMubj)}(hhh](j)}(h0=Stream is not copyrightedh]h)}(hj:h]h0=Stream is not copyrighted}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:hhhhhNubj)}(h1=Stream is copyrighted h]h)}(h1=Stream is copyrightedh]h1=Stream is copyrighted}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj:hhubeh}(h]id181ah ]h"]h$]param[0]ah&]uh1hhj\:hhhhhMj Kubeh}(h]cx2341x-enc-set-copyrightah ]h"]cx2341x_enc_set_copyrightah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h"CX2341X_ENC_SET_EVENT_NOTIFICATIONh]h"CX2341X_ENC_SET_EVENT_NOTIFICATION}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhMubh)}(hEnum: 213/0xD5h]hEnum: 213/0xD5}(hj ;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(h_Setup firmware to notify the host about a particular event. Host must unmask the interrupt bit.h]h_Setup firmware to notify the host about a particular event. Host must unmask the interrupt bit.}(hj+;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;hhubeh}(h]id182ah ]h"]h$] descriptionah&]uh1hhj:hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjD;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA;hhhhhMubh)}(hEvent (0=refresh encoder input)h]hEvent (0=refresh encoder input)}(hjR;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjA;hhubeh}(h]id183ah ]h"]h$]param[0]ah&]uh1hhj:hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjk;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjh;hhhhhMubh)}(h!Notification 0=disabled 1=enabledh]h!Notification 0=disabled 1=enabled}(hjy;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjh;hhubeh}(h]id184ah ]h"]h$]param[1]ah&]uh1hhj:hhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(h Interrupt bith]h Interrupt bit}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;hhubeh}(h]id185ah ]h"]h$]param[2]ah&]uh1hhj:hhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(h(Mailbox slot, -1 if no mailbox required.h]h(Mailbox slot, -1 if no mailbox required.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;hhubeh}(h]id186ah ]h"]h$]param[3]ah&]uh1hhj:hhhhhMj Kubeh}(h]"cx2341x-enc-set-event-notificationah ]h"]"cx2341x_enc_set_event_notificationah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_NUM_VSYNC_LINESh]hCX2341X_ENC_SET_NUM_VSYNC_LINES}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMubh)}(hEnum: 214/0xD6h]hEnum: 214/0xD6}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubh)}(h_Depending on the analog video decoder used, this assigns the number of lines for field 1 and 2.h]h_Depending on the analog video decoder used, this assigns the number of lines for field 1 and 2.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubeh}(h]id187ah ]h"]h$] descriptionah&]uh1hhj;hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj.<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+<hhhhhMubh)}(hXField 1 number of lines: - 0x00EF for SAA7114 - 0x00F0 for SAA7115 - 0x0105 for Micronash]hXField 1 number of lines: - 0x00EF for SAA7114 - 0x00F0 for SAA7115 - 0x0105 for Micronas}(hj<<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+<hhubeh}(h]id188ah ]h"]h$]param[0]ah&]uh1hhj;hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjU<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR<hhhhhMubh)}(hXField 2 number of lines: - 0x00EF for SAA7114 - 0x00F0 for SAA7115 - 0x0106 for Micronash]hXField 2 number of lines: - 0x00EF for SAA7114 - 0x00F0 for SAA7115 - 0x0106 for Micronas}(hjc<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjR<hhubeh}(h]id189ah ]h"]h$]param[1]ah&]uh1hhj;hhhhhMj Kubeh}(h]cx2341x-enc-set-num-vsync-linesah ]h"]cx2341x_enc_set_num_vsync_linesah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_SET_PLACEHOLDERh]hCX2341X_ENC_SET_PLACEHOLDER}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubh)}(hEnum: 215/0xD7h]hEnum: 215/0xD7}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubh)}(hFProvides a mechanism of inserting custom user data in the MPEG stream.h]hFProvides a mechanism of inserting custom user data in the MPEG stream.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubeh}(h]id190ah ]h"]h$] descriptionah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubj)}(hhh](j)}(h0=extension & user datah]h)}(hj<h]h0=extension & user data}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<hhhhhNubj)}(h%1=private packet with stream ID 0xBD h]h)}(h$1=private packet with stream ID 0xBDh]h$1=private packet with stream ID 0xBD}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj<hhubeh}(h]id191ah ]h"]h$]param[0]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhMubh)}(hdRate at which to insert data, in units of frames (for private packet) or GOPs (for ext. & user data)h]hdRate at which to insert data, in units of frames (for private packet) or GOPs (for ext. & user data)}(hj)=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubeh}(h]id192ah ]h"]h$]param[1]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjB=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?=hhhhhMubh)}(h'Number of data DWORDs (below) to inserth]h'Number of data DWORDs (below) to insert}(hjP=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?=hhubeh}(h]id193ah ]h"]h$]param[2]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hji=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf=hhhhhMubh)}(h Custom data 0h]h Custom data 0}(hjw=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjf=hhubeh}(h]id194ah ]h"]h$]param[3]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[4]h]hParam[4]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhMubh)}(h Custom data 1h]h Custom data 1}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubeh}(h]id195ah ]h"]h$]param[4]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[5]h]hParam[5]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhMubh)}(h Custom data 2h]h Custom data 2}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=hhubeh}(h]id196ah ]h"]h$]param[5]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[6]h]hParam[6]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhM ubh)}(h Custom data 3h]h Custom data 3}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubeh}(h]id197ah ]h"]h$]param[6]ah&]uh1hhj<hhhhhM j Kubh)}(hhh](h)}(hParam[7]h]hParam[7]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhMubh)}(h Custom data 4h]h Custom data 4}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>hhubeh}(h]id198ah ]h"]h$]param[7]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[8]h]hParam[8]}(hj,>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)>hhhhhMubh)}(h Custom data 5h]h Custom data 5}(hj:>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)>hhubeh}(h]id199ah ]h"]h$]param[8]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(hParam[9]h]hParam[9]}(hjS>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjP>hhhhhMubh)}(h Custom data 6h]h Custom data 6}(hja>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjP>hhubeh}(h]id200ah ]h"]h$]param[9]ah&]uh1hhj<hhhhhMj Kubh)}(hhh](h)}(h Param[10]h]h Param[10]}(hjz>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw>hhhhhM!ubh)}(h Custom data 7h]h Custom data 7}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjw>hhubeh}(h]id201ah ]h"]h$]jah&]uh1hhj<hhhhhM!j Kubh)}(hhh](h)}(h Param[11]h]h Param[11]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhM&ubh)}(h Custom data 8h]h Custom data 8}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj>hhubeh}(h]param-11ah ]h"] param[11]ah$]h&]uh1hhj<hhhhhM&ubeh}(h]cx2341x-enc-set-placeholderah ]h"]cx2341x_enc_set_placeholderah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(hCX2341X_ENC_MUTE_VIDEOh]hCX2341X_ENC_MUTE_VIDEO}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhM-ubh)}(hEnum: 217/0xD9h]hEnum: 217/0xD9}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj>hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhM2ubh)}(h Video mutingh]h Video muting}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hj>hhubeh}(h]id202ah ]h"]h$] descriptionah&]uh1hhj>hhhhhM2j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhM7ubh)}(h Bit usage:h]h Bit usage:}(hj#?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj?hhubj)}(h 0 '0'=video not muted '1'=video muted, creates frames with the YUV color defined below 1:7 Unused 8:15 V chrominance information 16:23 U chrominance information 24:31 Y luminance informationh]h 0 '0'=video not muted '1'=video muted, creates frames with the YUV color defined below 1:7 Unused 8:15 V chrominance information 16:23 U chrominance information 24:31 Y luminance information}hj1?sbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhM;hj?hhubeh}(h]id203ah ]h"]h$]param[0]ah&]uh1hhj>hhhhhM7j Kubeh}(h]cx2341x-enc-mute-videoah ]h"]cx2341x_enc_mute_videoah$]h&]uh1hhjhhhhhM-ubh)}(hhh](h)}(hCX2341X_ENC_MUTE_AUDIOh]hCX2341X_ENC_MUTE_AUDIO}(hjT?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQ?hhhhhMGubh)}(hEnum: 218/0xDAh]hEnum: 218/0xDA}(hjb?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhjQ?hhubh)}(hhh](h)}(h Descriptionh]h Description}(hjs?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp?hhhhhMLubh)}(h Audio mutingh]h Audio muting}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjp?hhubeh}(h]id204ah ]h"]h$] descriptionah&]uh1hhjQ?hhhhhMLj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhMQubj)}(hhh](j)}(h0=audio not mutedh]h)}(hj?h]h0=audio not muted}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj?ubah}(h]h ]h"]h$]h&]uh1jhj?hhhhhNubj)}(h41=audio muted (produces silent mpeg audio stream) h]h)}(h11=audio muted (produces silent mpeg audio stream)h]h11=audio muted (produces silent mpeg audio stream)}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj?ubah}(h]h ]h"]h$]h&]uh1jhj?hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMShj?hhubeh}(h]id205ah ]h"]h$]param[0]ah&]uh1hhjQ?hhhhhMQj Kubeh}(h]cx2341x-enc-mute-audioah ]h"]cx2341x_enc_mute_audioah$]h&]uh1hhjhhhhhMGubh)}(hhh](h)}(hCX2341X_ENC_SET_VERT_CROP_LINEh]hCX2341X_ENC_SET_VERT_CROP_LINE}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhMYubh)}(hEnum: 219/0xDBh]hEnum: 219/0xDB}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj?hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhM^ubh)}(h)Something to do with 'Vertical Crop Line'h]h-Something to do with ‘Vertical Crop Line’}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hj@hhubeh}(h]id206ah ]h"]h$] descriptionah&]uh1hhj?hhhhhM^j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj9@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6@hhhhhMcubh)}(hDIf saa7114 and raw VBI capture and 60 Hz, then set to 10001. Else 0.h]hDIf saa7114 and raw VBI capture and 60 Hz, then set to 10001. Else 0.}(hjG@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj6@hhubeh}(h]id207ah ]h"]h$]param[0]ah&]uh1hhj?hhhhhMcj Kubeh}(h]cx2341x-enc-set-vert-crop-lineah ]h"]cx2341x_enc_set_vert_crop_lineah$]h&]uh1hhjhhhhhMYubh)}(hhh](h)}(hCX2341X_ENC_MISCh]hCX2341X_ENC_MISC}(hjh@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje@hhhhhMkubh)}(hEnum: 220/0xDCh]hEnum: 220/0xDC}(hjv@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhje@hhubh)}(hhh](h)}(h Descriptionh]h Description}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhMpubh)}(hMiscellaneous actions. Not known for 100% what it does. It's really a sort of ioctl call. The first parameter is a command number, the second the value.h]hMiscellaneous actions. Not known for 100% what it does. It’s really a sort of ioctl call. The first parameter is a command number, the second the value.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhj@hhubeh}(h]id208ah ]h"]h$] descriptionah&]uh1hhje@hhhhhMpj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhMwubh)}(hCommand number:h]hCommand number:}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj@hhubj)}(hX 1=set initial SCR value when starting encoding (works). 2=set quality mode (apparently some test setting). 3=setup advanced VIM protection handling. Always 1 for the cx23416 and 0 for cx23415. 4=generate DVD compatible PTS timestamps 5=USB flush mode 6=something to do with the quantization matrix 7=set navigation pack insertion for DVD: adds 0xbf (private stream 2) packets to the MPEG. The size of these packets is 2048 bytes (including the header of 6 bytes: 0x000001bf + length). The payload is zeroed and it is up to the application to fill them in. These packets are apparently inserted every four frames. 8=enable scene change detection (seems to be a failure) 9=set history parameters of the video input module 10=set input field order of VIM 11=set quantization matrix 12=reset audio interface after channel change or input switch (has no argument). Needed for the cx2584x, not needed for the mspx4xx, but it doesn't seem to do any harm calling it regardless. 13=set audio volume delay 14=set audio delayh]hX 1=set initial SCR value when starting encoding (works). 2=set quality mode (apparently some test setting). 3=setup advanced VIM protection handling. Always 1 for the cx23416 and 0 for cx23415. 4=generate DVD compatible PTS timestamps 5=USB flush mode 6=something to do with the quantization matrix 7=set navigation pack insertion for DVD: adds 0xbf (private stream 2) packets to the MPEG. The size of these packets is 2048 bytes (including the header of 6 bytes: 0x000001bf + length). The payload is zeroed and it is up to the application to fill them in. These packets are apparently inserted every four frames. 8=enable scene change detection (seems to be a failure) 9=set history parameters of the video input module 10=set input field order of VIM 11=set quantization matrix 12=reset audio interface after channel change or input switch (has no argument). Needed for the cx2584x, not needed for the mspx4xx, but it doesn't seem to do any harm calling it regardless. 13=set audio volume delay 14=set audio delay}hj@sbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhM{hj@hhubeh}(h]id209ah ]h"]h$]param[0]ah&]uh1hhje@hhhhhMwj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhMubh)}(hCommand value.h]hCommand value.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@hhubeh}(h]id210ah ]h"]h$]param[1]ah&]uh1hhje@hhhhhMj Kubeh}(h]cx2341x-enc-miscah ]h"]cx2341x_enc_miscah$]h&]uh1hhjhhhhhMkubeh}(h] encoder-firmware-api-descriptionah ]h"] encoder firmware api descriptionah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h Decoder firmware API descriptionh]h Decoder firmware API description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(h?this API is part of the decoder firmware, so it's cx23415 only.h]h)}(hj,Ah]hAthis API is part of the decoder firmware, so it’s cx23415 only.}(hj.AhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*Aubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhNubh)}(hhh](h)}(hCX2341X_DEC_PING_FWh]hCX2341X_DEC_PING_FW}(hjDAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAAhhhhhMubh)}(h Enum: 0/0x00h]h Enum: 0/0x00}(hjRAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAAhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjcAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`AhhhhhMubh)}(hRThis API call does nothing. It may be used to check if the firmware is responding.h]hRThis API call does nothing. It may be used to check if the firmware is responding.}(hjqAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`Ahhubeh}(h]id211ah ]h"]h$] descriptionah&]uh1hhjAAhhhhhMj Kubeh}(h]cx2341x-dec-ping-fwah ]h"]cx2341x_dec_ping_fwah$]h&]uh1hhjAhhhhhMubh)}(hhh](h)}(hCX2341X_DEC_START_PLAYBACKh]hCX2341X_DEC_START_PLAYBACK}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(h Enum: 1/0x01h]h Enum: 1/0x01}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(hBegin or resume playback.h]hBegin or resume playback.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubeh}(h]id212ah ]h"]h$] descriptionah&]uh1hhjAhhhhhMj Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(h30 based frame number in GOP to begin playback from.h]h30 based frame number in GOP to begin playback from.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubeh}(h]id213ah ]h"]h$]param[0]ah&]uh1hhjAhhhhhMj Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMubh)}(hSpecifies the number of muted audio frames to play before normal audio resumes. (This is not implemented in the firmware, leave at 0)h]hSpecifies the number of muted audio frames to play before normal audio resumes. (This is not implemented in the firmware, leave at 0)}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubeh}(h]id214ah ]h"]h$]param[1]ah&]uh1hhjAhhhhhMj Kubeh}(h]cx2341x-dec-start-playbackah ]h"]cx2341x_dec_start_playbackah$]h&]uh1hhjAhhhhhMubh)}(hhh](h)}(hCX2341X_DEC_STOP_PLAYBACKh]hCX2341X_DEC_STOP_PLAYBACK}(hj.BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+BhhhhhMubh)}(h Enum: 2/0x02h]h Enum: 2/0x02}(hj hj&LubjI)}(hhh]h)}(h70=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchangedh]h70=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged}(hj;LhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM> hj8Lubah}(h]h ]h"]h$]h&]uh1jIhj&Lubeh}(h]h ]h"]h$]h&]uh1jIhhhM> hj#Lubah}(h]h ]h"]h$]h&]uh1jIhjLhhhhhNubeh}(h]id259ah ]h"]h$]param[0]ah&]uh1hhjKhhhhhM; j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjfLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcLhhhhhMA ubjI)}(hhh]jI)}(hNStereo mode action: 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged h](jI)}(hStereo mode action:h]hStereo mode action:}(hj{LhhhNhNubah}(h]h ]h"]h$]h&]uh1jIhhhMF hjwLubjI)}(hhh]h)}(h70=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchangedh]h70=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMD hjLubah}(h]h ]h"]h$]h&]uh1jIhjwLubeh}(h]h ]h"]h$]h&]uh1jIhhhMF hjtLubah}(h]h ]h"]h$]h&]uh1jIhjcLhhhhhNubeh}(h]id260ah ]h"]h$]param[1]ah&]uh1hhjKhhhhhMA j Kubeh}(h]cx2341x-dec-set-audio-modeah ]h"]cx2341x_dec_set_audio_modeah$]h&]uh1hhjAhhhhhM1 ubh)}(hhh](h)}(h"CX2341X_DEC_SET_EVENT_NOTIFICATIONh]h"CX2341X_DEC_SET_EVENT_NOTIFICATION}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhMI ubh)}(h Enum: 23/0x17h]h Enum: 23/0x17}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMK hjLhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhMN ubh)}(hSSetup firmware to notify the host about a particular event. Counterpart to API 0xD5h]hSSetup firmware to notify the host about a particular event. Counterpart to API 0xD5}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMP hjLhhubeh}(h]id261ah ]h"]h$] descriptionah&]uh1hhjLhhhhhMN j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhMT ubjI)}(hhh]jI)}(hEvent: - 0=Audio mode change between mono, (joint) stereo and dual channel. - 3=Decoder started - 4=Unknown: goes off 10-15 times per second while decoding. - 5=Some sync event: goes off once per frame. h](jI)}(hEvent:h]hEvent:}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jIhhhMZ hjMubjI)}(hhh]j)}(hhh](j)}(hB0=Audio mode change between mono, (joint) stereo and dual channel.h]h)}(hj0Mh]hB0=Audio mode change between mono, (joint) stereo and dual channel.}(hj2MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMW hj.Mubah}(h]h ]h"]h$]h&]uh1jhj+Mubj)}(h3=Decoder startedh]h)}(hjGMh]h3=Decoder started}(hjIMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMX hjEMubah}(h]h ]h"]h$]h&]uh1jhj+Mubj)}(h:4=Unknown: goes off 10-15 times per second while decoding.h]h)}(hj^Mh]h:4=Unknown: goes off 10-15 times per second while decoding.}(hj`MhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY hj\Mubah}(h]h ]h"]h$]h&]uh1jhj+Mubj)}(h,5=Some sync event: goes off once per frame. h]h)}(h+5=Some sync event: goes off once per frame.h]h+5=Some sync event: goes off once per frame.}(hjwMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZ hjsMubah}(h]h ]h"]h$]h&]uh1jhj+Mubeh}(h]h ]h"]h$]h&]jjuh1jhhhMW hj(Mubah}(h]h ]h"]h$]h&]uh1jIhjMubeh}(h]h ]h"]h$]h&]uh1jIhhhMZ hjMubah}(h]h ]h"]h$]h&]uh1jIhjMhhhNhNubeh}(h]id262ah ]h"]h$]param[0]ah&]uh1hhjLhhhhhMT j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhM] ubh)}(h"Notification 0=disabled, 1=enabledh]h"Notification 0=disabled, 1=enabled}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_ hjMhhubeh}(h]id263ah ]h"]h$]param[1]ah&]uh1hhjLhhhhhM] j Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhMb ubh)}(h Interrupt bith]h Interrupt bit}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd hjMhhubeh}(h]id264ah ]h"]h$]param[2]ah&]uh1hhjLhhhhhMb j Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhMg ubh)}(h(Mailbox slot, -1 if no mailbox required.h]h(Mailbox slot, -1 if no mailbox required.}(hj NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMi hjMhhubeh}(h]id265ah ]h"]h$]param[3]ah&]uh1hhjLhhhhhMg j Kubeh}(h]"cx2341x-dec-set-event-notificationah ]h"]"cx2341x_dec_set_event_notificationah$]h&]uh1hhjAhhhhhMI ubh)}(hhh](h)}(hCX2341X_DEC_SET_DISPLAY_BUFFERSh]hCX2341X_DEC_SET_DISPLAY_BUFFERS}(hj+NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(NhhhhhMn ubh)}(h Enum: 24/0x18h]h Enum: 24/0x18}(hj9NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMp hj(Nhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjJNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGNhhhhhMs ubh)}(h^Number of display buffers. To decode all frames in reverse playback you must use nine buffers.h]h^Number of display buffers. To decode all frames in reverse playback you must use nine buffers.}(hjXNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMu hjGNhhubeh}(h]id266ah ]h"]h$] descriptionah&]uh1hhj(NhhhhhMs j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjqNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnNhhhhhMy ubh)}(h0=six buffers, 1=nine buffersh]h0=six buffers, 1=nine buffers}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{ hjnNhhubeh}(h]id267ah ]h"]h$]param[0]ah&]uh1hhj(NhhhhhMy j Kubeh}(h]cx2341x-dec-set-display-buffersah ]h"]cx2341x_dec_set_display_buffersah$]h&]uh1hhjAhhhhhMn ubh)}(hhh](h)}(hCX2341X_DEC_EXTRACT_VBIh]hCX2341X_DEC_EXTRACT_VBI}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhM ubh)}(h Enum: 25/0x19h]h Enum: 25/0x19}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjNhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhM ubh)}(hExtracts VBI datah]hExtracts VBI data}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjNhhubeh}(h]id268ah ]h"]h$] descriptionah&]uh1hhjNhhhhhM j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhM ubh)}(hD0=extract from extension & user data, 1=extract from private packetsh]hD0=extract from extension & user data, 1=extract from private packets}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjNhhubeh}(h]id269ah ]h"]h$]param[0]ah&]uh1hhjNhhhhhM j Kubh)}(hhh](h)}(h Result[0]h]h Result[0]}(hj OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj OhhhhhM ubh)}(hVBI table locationh]hVBI table location}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj Ohhubeh}(h]id270ah ]h"]h$] result[0]ah&]uh1hhjNhhhhhM j Kubh)}(hhh](h)}(h Result[1]h]h Result[1]}(hj4OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1OhhhhhM ubh)}(hVBI table sizeh]hVBI table size}(hjBOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj1Ohhubeh}(h]id271ah ]h"]h$] result[1]ah&]uh1hhjNhhhhhM j Kubeh}(h]cx2341x-dec-extract-vbiah ]h"]cx2341x_dec_extract_vbiah$]h&]uh1hhjAhhhhhM ubh)}(hhh](h)}(hCX2341X_DEC_SET_DECODER_SOURCEh]hCX2341X_DEC_SET_DECODER_SOURCE}(hjcOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`OhhhhhM ubh)}(h Enum: 26/0x1Ah]h Enum: 26/0x1A}(hjqOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`Ohhubh)}(hhh](h)}(h Descriptionh]h Description}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhM ubh)}(haSelects decoder source. Ensure that the parameters passed to this API match the encoder settings.h]haSelects decoder source. Ensure that the parameters passed to this API match the encoder settings.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjOhhubeh}(h]id272ah ]h"]h$] descriptionah&]uh1hhj`OhhhhhM j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhM ubh)}(h;Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from hosth]h;Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjOhhubeh}(h]id273ah ]h"]h$]param[0]ah&]uh1hhj`OhhhhhM j Kubh)}(hhh](h)}(hParam[1]h]hParam[1]}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhM ubh)}(hYUV picture widthh]hYUV picture width}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjOhhubeh}(h]id274ah ]h"]h$]param[1]ah&]uh1hhj`OhhhhhM j Kubh)}(hhh](h)}(hParam[2]h]hParam[2]}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhM ubh)}(hYUV picture heighth]hYUV picture height}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjOhhubeh}(h]id275ah ]h"]h$]param[2]ah&]uh1hhj`OhhhhhM j Kubh)}(hhh](h)}(hParam[3]h]hParam[3]}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhM ubh)}(h Bitmap: see Param[0] of API 0xBDh]h Bitmap: see Param[0] of API 0xBD}(hj,PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubeh}(h]id276ah ]h"]h$]param[3]ah&]uh1hhj`OhhhhhM j Kubeh}(h]cx2341x-dec-set-decoder-sourceah ]h"]cx2341x_dec_set_decoder_sourceah$]h&]uh1hhjAhhhhhM ubh)}(hhh](h)}(hCX2341X_DEC_SET_PREBUFFERINGh]hCX2341X_DEC_SET_PREBUFFERING}(hjMPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJPhhhhhM ubh)}(h Enum: 30/0x1Eh]h Enum: 30/0x1E}(hj[PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJPhhubh)}(hhh](h)}(h Descriptionh]h Description}(hjlPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjiPhhhhhM ubh)}(hjDecoder prebuffering, when enabled up to 128KB are buffered for streams <8mpbs or 640KB for streams >8mbpsh]hjDecoder prebuffering, when enabled up to 128KB are buffered for streams <8mpbs or 640KB for streams >8mbps}(hjzPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjiPhhubeh}(h]id277ah ]h"]h$] descriptionah&]uh1hhjJPhhhhhM j Kubh)}(hhh](h)}(hParam[0]h]hParam[0]}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhM ubh)}(h 0=off, 1=onh]h 0=off, 1=on}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubeh}(h]id278ah ]h"]h$]param[0]ah&]uh1hhjJPhhhhhM j Kubeh}(h]cx2341x-dec-set-prebufferingah ]h"]cx2341x_dec_set_prebufferingah$]h&]uh1hhjAhhhhhM ubeh}(h] decoder-firmware-api-descriptionah ]h"] decoder firmware api descriptionah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h7PVR350 Video decoder registers 0x02002800 -> 0x02002B00h]h7PVR350 Video decoder registers 0x02002800 -> 0x02002B00}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhM ubh)}(h.Author: Ian Armstrong h](hAuthor: Ian Armstrong <}(hjPhhhNhNubh reference)}(hian@iarmst.demon.co.ukh]hian@iarmst.demon.co.uk}(hjPhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:ian@iarmst.demon.co.ukuh1jPhjPubh>}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubh)}(h Version: v0.4h]h Version: v0.4}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubh)}(hDate: 12 March 2007h]hDate: 12 March 2007}(hj QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubh)}(hXThis list has been worked out through trial and error. There will be mistakes and omissions. Some registers have no obvious effect so it's hard to say what they do, while others interact with each other, or require a certain load sequence. Horizontal filter setup is one example, with six registers working in unison and requiring a certain load sequence to correctly configure. The indexed colour palette is much easier to set at just two registers, but again it requires a certain load sequence.h]hXThis list has been worked out through trial and error. There will be mistakes and omissions. Some registers have no obvious effect so it’s hard to say what they do, while others interact with each other, or require a certain load sequence. Horizontal filter setup is one example, with six registers working in unison and requiring a certain load sequence to correctly configure. The indexed colour palette is much easier to set at just two registers, but again it requires a certain load sequence.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubh)}(hX_Some registers are fussy about what they are set to. Load in a bad value & the decoder will fail. A firmware reload will often recover, but sometimes a reset is required. For registers containing size information, setting them to 0 is generally a bad idea. For other control registers i.e. 2878, you'll only find out what values are bad when it hangs.h]hXaSome registers are fussy about what they are set to. Load in a bad value & the decoder will fail. A firmware reload will often recover, but sometimes a reset is required. For registers containing size information, setting them to 0 is generally a bad idea. For other control registers i.e. 2878, you’ll only find out what values are bad when it hangs.}(hj&QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPhhubj)}(hXNW-------------------------------------------------------------------------------- 2800 bit 0 Decoder enable 0 = disable 1 = enable -------------------------------------------------------------------------------- 2804 bits 0:31 Decoder horizontal Y alias register 1 --------------- 2808 bits 0:31 Decoder horizontal Y alias register 2 --------------- 280C bits 0:31 Decoder horizontal Y alias register 3 --------------- 2810 bits 0:31 Decoder horizontal Y alias register 4 --------------- 2814 bits 0:31 Decoder horizontal Y alias register 5 --------------- 2818 bits 0:31 Decoder horizontal Y alias trigger These six registers control the horizontal aliasing filter for the Y plane. The first five registers must all be loaded before accessing the trigger (2818), as this register actually clocks the data through for the first five. To correctly program set the filter, this whole procedure must be done 16 times. The actual register contents are copied from a lookup-table in the firmware which contains 4 different filter settings. -------------------------------------------------------------------------------- 281C bits 0:31 Decoder horizontal UV alias register 1 --------------- 2820 bits 0:31 Decoder horizontal UV alias register 2 --------------- 2824 bits 0:31 Decoder horizontal UV alias register 3 --------------- 2828 bits 0:31 Decoder horizontal UV alias register 4 --------------- 282C bits 0:31 Decoder horizontal UV alias register 5 --------------- 2830 bits 0:31 Decoder horizontal UV alias trigger These six registers control the horizontal aliasing for the UV plane. Operation is the same as the Y filter, with 2830 being the trigger register. -------------------------------------------------------------------------------- 2834 bits 0:15 Decoder Y source width in pixels bits 16:31 Decoder Y destination width in pixels --------------- 2838 bits 0:15 Decoder UV source width in pixels bits 16:31 Decoder UV destination width in pixels NOTE: For both registers, the resulting image must be fully visible on screen. If the image exceeds the right edge both the source and destination size must be adjusted to reflect the visible portion. For the source width, you must take into account the scaling when calculating the new value. -------------------------------------------------------------------------------- 283C bits 0:31 Decoder Y horizontal scaling Normally = Reg 2854 >> 2 --------------- 2840 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00080514 --------------- 2844 bits 0:31 Decoder UV horizontal scaling Normally = Reg 2854 >> 2 --------------- 2848 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00100514 --------------- 284C bits 0:31 Decoder ?? unknown - Y plane Usually 0x00200020 --------------- 2850 bits 0:31 Decoder ?? unknown - UV plane Usually 0x00200020 --------------- 2854 bits 0:31 Decoder 'master' value for horizontal scaling --------------- 2858 bits 0:31 Decoder ?? unknown Usually 0 --------------- 285C bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1 --------------- 2860 bits 0:31 Decoder ?? unknown Usually 0 --------------- 2864 bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1 --------------- 2868 bits 0:31 Decoder ?? unknown Usually 0 Most of these registers either control horizontal scaling, or appear linked to it in some way. Register 2854 contains the 'master' value & the other registers can be calculated from that one. You must also remember to correctly set the divider in Reg 2874. To enlarge: Reg 2854 = (source_width * 0x00200000) / destination_width Reg 2874 = No divide To reduce from full size down to half size: Reg 2854 = (source_width/2 * 0x00200000) / destination width Reg 2874 = Divide by 2 To reduce from half size down to quarter size: Reg 2854 = (source_width/4 * 0x00200000) / destination width Reg 2874 = Divide by 4 The result is always rounded up. -------------------------------------------------------------------------------- 286C bits 0:15 Decoder horizontal Y buffer offset bits 15:31 Decoder horizontal UV buffer offset Offset into the video image buffer. If the offset is gradually incremented, the on screen image will move left & wrap around higher up on the right. -------------------------------------------------------------------------------- 2870 bits 0:15 Decoder horizontal Y output offset bits 16:31 Decoder horizontal UV output offset Offsets the actual video output. Controls output alignment of the Y & UV planes. The higher the value, the greater the shift to the left. Use reg 2890 to move the image right. -------------------------------------------------------------------------------- 2874 bits 0:1 Decoder horizontal Y output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bits 4:5 Decoder horizontal UV output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bit 8 Decoder ?? unknown 0 = Normal 1 = Affects video output levels bit 16 Decoder ?? unknown 0 = Normal 1 = Disable horizontal filter -------------------------------------------------------------------------------- 2878 bit 0 ?? unknown bit 1 osd on/off 0 = osd off 1 = osd on bit 2 Decoder + osd video timing 0 = NTSC 1 = PAL bits 3:4 ?? unknown bit 5 Decoder + osd Swaps upper & lower fields -------------------------------------------------------------------------------- 287C bits 0:10 Decoder & osd ?? unknown Moves entire screen horizontally. Starts at 0x005 with the screen shifted heavily to the right. Incrementing in steps of 0x004 will gradually shift the screen to the left. bits 11:31 ?? unknown Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL) -------------------------------------------------------------------------------- 2880 -------- ?? unknown 2884 -------- ?? unknown -------------------------------------------------------------------------------- 2888 bit 0 Decoder + osd ?? unknown 0 = Normal 1 = Misaligned fields (Correctable through 289C & 28A4) bit 4 ?? unknown bit 8 ?? unknown Warning: Bad values will require a firmware reload to recover. Known to be bad are 0x000,0x011,0x100,0x111 -------------------------------------------------------------------------------- 288C bits 0:15 osd ?? unknown Appears to affect the osd position stability. The higher the value the more unstable it becomes. Decoder output remains stable. bits 16:31 osd ?? unknown Same as bits 0:15 -------------------------------------------------------------------------------- 2890 bits 0:11 Decoder output horizontal offset. Horizontal offset moves the video image right. A small left shift is possible, but it's better to use reg 2870 for that due to its greater range. NOTE: Video corruption will occur if video window is shifted off the right edge. To avoid this read the notes for 2834 & 2838. -------------------------------------------------------------------------------- 2894 bits 0:23 Decoder output video surround colour. Contains the colour (in yuv) used to fill the screen when the video is running in a window. -------------------------------------------------------------------------------- 2898 bits 0:23 Decoder video window colour Contains the colour (in yuv) used to fill the video window when the video is turned off. bit 24 Decoder video output 0 = Video on 1 = Video off bit 28 Decoder plane order 0 = Y,UV 1 = UV,Y bit 29 Decoder second plane byte order 0 = Normal (UV) 1 = Swapped (VU) In normal usage, the first plane is Y & the second plane is UV. Though the order of the planes can be swapped, only the byte order of the second plane can be swapped. This isn't much use for the Y plane, but can be useful for the UV plane. -------------------------------------------------------------------------------- 289C bits 0:15 Decoder vertical field offset 1 bits 16:31 Decoder vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL) -------------------------------------------------------------------------------- 28A0 bits 0:15 Decoder & osd width in pixels bits 16:31 Decoder & osd height in pixels All output from the decoder & osd are disabled beyond this area. Decoder output will simply go black outside of this region. If the osd tries to exceed this area it will become corrupt. -------------------------------------------------------------------------------- 28A4 bits 0:11 osd left shift. Has a range of 0x770->0x7FF. With the exception of 0, any value outside of this range corrupts the osd. -------------------------------------------------------------------------------- 28A8 bits 0:15 osd vertical field offset 1 bits 16:31 osd vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL) -------------------------------------------------------------------------------- 28AC -------- ?? unknown | V 28BC -------- ?? unknown -------------------------------------------------------------------------------- 28C0 bit 0 Current output field 0 = first field 1 = second field bits 16:31 Current scanline The scanline counts from the top line of the first field through to the last line of the second field. -------------------------------------------------------------------------------- 28C4 -------- ?? unknown | V 28F8 -------- ?? unknown -------------------------------------------------------------------------------- 28FC bit 0 ?? unknown 0 = Normal 1 = Breaks decoder & osd output -------------------------------------------------------------------------------- 2900 bits 0:31 Decoder vertical Y alias register 1 --------------- 2904 bits 0:31 Decoder vertical Y alias register 2 --------------- 2908 bits 0:31 Decoder vertical Y alias trigger These three registers control the vertical aliasing filter for the Y plane. Operation is similar to the horizontal Y filter (2804). The only real difference is that there are only two registers to set before accessing the trigger register (2908). As for the horizontal filter, the values are taken from a lookup table in the firmware, and the procedure must be repeated 16 times to fully program the filter. -------------------------------------------------------------------------------- 290C bits 0:31 Decoder vertical UV alias register 1 --------------- 2910 bits 0:31 Decoder vertical UV alias register 2 --------------- 2914 bits 0:31 Decoder vertical UV alias trigger These three registers control the vertical aliasing filter for the UV plane. Operation is the same as the Y filter, with 2914 being the trigger. -------------------------------------------------------------------------------- 2918 bits 0:15 Decoder Y source height in pixels bits 16:31 Decoder Y destination height in pixels --------------- 291C bits 0:15 Decoder UV source height in pixels divided by 2 bits 16:31 Decoder UV destination height in pixels NOTE: For both registers, the resulting image must be fully visible on screen. If the image exceeds the bottom edge both the source and destination size must be adjusted to reflect the visible portion. For the source height, you must take into account the scaling when calculating the new value. -------------------------------------------------------------------------------- 2920 bits 0:31 Decoder Y vertical scaling Normally = Reg 2930 >> 2 --------------- 2924 bits 0:31 Decoder Y vertical scaling Normally = Reg 2920 + 0x514 --------------- 2928 bits 0:31 Decoder UV vertical scaling When enlarging = Reg 2930 >> 2 When reducing = Reg 2930 >> 3 --------------- 292C bits 0:31 Decoder UV vertical scaling Normally = Reg 2928 + 0x514 --------------- 2930 bits 0:31 Decoder 'master' value for vertical scaling --------------- 2934 bits 0:31 Decoder ?? unknown - Y vertical scaling --------------- 2938 bits 0:31 Decoder Y vertical scaling Normally = Reg 2930 --------------- 293C bits 0:31 Decoder ?? unknown - Y vertical scaling --------------- 2940 bits 0:31 Decoder UV vertical scaling When enlarging = Reg 2930 >> 1 When reducing = Reg 2930 --------------- 2944 bits 0:31 Decoder ?? unknown - UV vertical scaling --------------- 2948 bits 0:31 Decoder UV vertical scaling Normally = Reg 2940 --------------- 294C bits 0:31 Decoder ?? unknown - UV vertical scaling Most of these registers either control vertical scaling, or appear linked to it in some way. Register 2930 contains the 'master' value & all other registers can be calculated from that one. You must also remember to correctly set the divider in Reg 296C To enlarge: Reg 2930 = (source_height * 0x00200000) / destination_height Reg 296C = No divide To reduce from full size down to half size: Reg 2930 = (source_height/2 * 0x00200000) / destination height Reg 296C = Divide by 2 To reduce from half down to quarter. Reg 2930 = (source_height/4 * 0x00200000) / destination height Reg 296C = Divide by 4 -------------------------------------------------------------------------------- 2950 bits 0:15 Decoder Y line index into display buffer, first field bits 16:31 Decoder Y vertical line skip, first field -------------------------------------------------------------------------------- 2954 bits 0:15 Decoder Y line index into display buffer, second field bits 16:31 Decoder Y vertical line skip, second field -------------------------------------------------------------------------------- 2958 bits 0:15 Decoder UV line index into display buffer, first field bits 16:31 Decoder UV vertical line skip, first field -------------------------------------------------------------------------------- 295C bits 0:15 Decoder UV line index into display buffer, second field bits 16:31 Decoder UV vertical line skip, second field -------------------------------------------------------------------------------- 2960 bits 0:15 Decoder destination height minus 1 bits 16:31 Decoder destination height divided by 2 -------------------------------------------------------------------------------- 2964 bits 0:15 Decoder Y vertical offset, second field bits 16:31 Decoder Y vertical offset, first field These two registers shift the Y plane up. The higher the number, the greater the shift. -------------------------------------------------------------------------------- 2968 bits 0:15 Decoder UV vertical offset, second field bits 16:31 Decoder UV vertical offset, first field These two registers shift the UV plane up. The higher the number, the greater the shift. -------------------------------------------------------------------------------- 296C bits 0:1 Decoder vertical Y output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 4 bits 8:9 Decoder vertical UV output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 4 -------------------------------------------------------------------------------- 2970 bit 0 Decoder ?? unknown 0 = Normal 1 = Affect video output levels bit 16 Decoder ?? unknown 0 = Normal 1 = Disable vertical filter -------------------------------------------------------------------------------- 2974 -------- ?? unknown | V 29EF -------- ?? unknown -------------------------------------------------------------------------------- 2A00 bits 0:2 osd colour mode 000 = 8 bit indexed 001 = 16 bit (565) 010 = 15 bit (555) 011 = 12 bit (444) 100 = 32 bit (8888) bits 4:5 osd display bpp 01 = 8 bit 10 = 16 bit 11 = 32 bit bit 8 osd global alpha 0 = Off 1 = On bit 9 osd local alpha 0 = Off 1 = On bit 10 osd colour key 0 = Off 1 = On bit 11 osd ?? unknown Must be 1 bit 13 osd colour space 0 = ARGB 1 = AYVU bits 16:31 osd ?? unknown Must be 0x001B (some kind of buffer pointer ?) When the bits-per-pixel is set to 8, the colour mode is ignored and assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth is honoured, and when using a colour depth that requires fewer bytes than allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit index colour, there are 3 padding bytes per pixel. It's also possible to select 16bpp with a 32 bit colour mode. This results in the pixel width being doubled, but the color key will not work as expected in this mode. Colour key is as it suggests. You designate a colour which will become completely transparent. When using 565, 555 or 444 colour modes, the colour key is always 16 bits wide. The colour to key on is set in Reg 2A18. Local alpha works differently depending on the colour mode. For 32bpp & 8 bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused bit(s) act as a simple transparency switch, with 0 being solid & 1 being fully transparent. There is no local alpha support for 16bit 565. Global alpha is a 256 step transparency that applies to the entire osd, with 0 being transparent & 255 being solid. It's possible to combine colour key, local alpha & global alpha. -------------------------------------------------------------------------------- 2A04 bits 0:15 osd x coord for left edge bits 16:31 osd y coord for top edge --------------- 2A08 bits 0:15 osd x coord for right edge bits 16:31 osd y coord for bottom edge For both registers, (0,0) = top left corner of the display area. These registers do not control the osd size, only where it's positioned & how much is visible. The visible osd area cannot exceed the right edge of the display, otherwise the osd will become corrupt. See reg 2A10 for setting osd width. -------------------------------------------------------------------------------- 2A0C bits 0:31 osd buffer index An index into the osd buffer. Slowly incrementing this moves the osd left, wrapping around onto the right edge -------------------------------------------------------------------------------- 2A10 bits 0:11 osd buffer 32 bit word width Contains the width of the osd measured in 32 bit words. This means that all colour modes are restricted to a byte width which is divisible by 4. -------------------------------------------------------------------------------- 2A14 bits 0:15 osd height in pixels bits 16:32 osd line index into buffer osd will start displaying from this line. -------------------------------------------------------------------------------- 2A18 bits 0:31 osd colour key Contains the colour value which will be transparent. -------------------------------------------------------------------------------- 2A1C bits 0:7 osd global alpha Contains the global alpha value (equiv ivtvfbctl --alpha XX) -------------------------------------------------------------------------------- 2A20 -------- ?? unknown | V 2A2C -------- ?? unknown -------------------------------------------------------------------------------- 2A30 bits 0:7 osd colour to change in indexed palette --------------- 2A34 bits 0:31 osd colour for indexed palette To set the new palette, first load the index of the colour to change into 2A30, then load the new colour into 2A34. The full palette is 256 colours, so the index range is 0x00-0xFF -------------------------------------------------------------------------------- 2A38 -------- ?? unknown 2A3C -------- ?? unknown -------------------------------------------------------------------------------- 2A40 bits 0:31 osd ?? unknown Affects overall brightness, wrapping around to black -------------------------------------------------------------------------------- 2A44 bits 0:31 osd ?? unknown Green tint -------------------------------------------------------------------------------- 2A48 bits 0:31 osd ?? unknown Red tint -------------------------------------------------------------------------------- 2A4C bits 0:31 osd ?? unknown Affects overall brightness, wrapping around to black -------------------------------------------------------------------------------- 2A50 bits 0:31 osd ?? unknown Colour shift -------------------------------------------------------------------------------- 2A54 bits 0:31 osd ?? unknown Colour shift -------------------------------------------------------------------------------- 2A58 -------- ?? unknown | V 2AFC -------- ?? unknown -------------------------------------------------------------------------------- 2B00 bit 0 osd filter control 0 = filter off 1 = filter on bits 1:4 osd ?? unknown --------------------------------------------------------------------------------h]hXNW-------------------------------------------------------------------------------- 2800 bit 0 Decoder enable 0 = disable 1 = enable -------------------------------------------------------------------------------- 2804 bits 0:31 Decoder horizontal Y alias register 1 --------------- 2808 bits 0:31 Decoder horizontal Y alias register 2 --------------- 280C bits 0:31 Decoder horizontal Y alias register 3 --------------- 2810 bits 0:31 Decoder horizontal Y alias register 4 --------------- 2814 bits 0:31 Decoder horizontal Y alias register 5 --------------- 2818 bits 0:31 Decoder horizontal Y alias trigger These six registers control the horizontal aliasing filter for the Y plane. The first five registers must all be loaded before accessing the trigger (2818), as this register actually clocks the data through for the first five. To correctly program set the filter, this whole procedure must be done 16 times. The actual register contents are copied from a lookup-table in the firmware which contains 4 different filter settings. -------------------------------------------------------------------------------- 281C bits 0:31 Decoder horizontal UV alias register 1 --------------- 2820 bits 0:31 Decoder horizontal UV alias register 2 --------------- 2824 bits 0:31 Decoder horizontal UV alias register 3 --------------- 2828 bits 0:31 Decoder horizontal UV alias register 4 --------------- 282C bits 0:31 Decoder horizontal UV alias register 5 --------------- 2830 bits 0:31 Decoder horizontal UV alias trigger These six registers control the horizontal aliasing for the UV plane. Operation is the same as the Y filter, with 2830 being the trigger register. -------------------------------------------------------------------------------- 2834 bits 0:15 Decoder Y source width in pixels bits 16:31 Decoder Y destination width in pixels --------------- 2838 bits 0:15 Decoder UV source width in pixels bits 16:31 Decoder UV destination width in pixels NOTE: For both registers, the resulting image must be fully visible on screen. If the image exceeds the right edge both the source and destination size must be adjusted to reflect the visible portion. For the source width, you must take into account the scaling when calculating the new value. -------------------------------------------------------------------------------- 283C bits 0:31 Decoder Y horizontal scaling Normally = Reg 2854 >> 2 --------------- 2840 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00080514 --------------- 2844 bits 0:31 Decoder UV horizontal scaling Normally = Reg 2854 >> 2 --------------- 2848 bits 0:31 Decoder ?? unknown - horizontal scaling Usually 0x00100514 --------------- 284C bits 0:31 Decoder ?? unknown - Y plane Usually 0x00200020 --------------- 2850 bits 0:31 Decoder ?? unknown - UV plane Usually 0x00200020 --------------- 2854 bits 0:31 Decoder 'master' value for horizontal scaling --------------- 2858 bits 0:31 Decoder ?? unknown Usually 0 --------------- 285C bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1 --------------- 2860 bits 0:31 Decoder ?? unknown Usually 0 --------------- 2864 bits 0:31 Decoder ?? unknown Normally = Reg 2854 >> 1 --------------- 2868 bits 0:31 Decoder ?? unknown Usually 0 Most of these registers either control horizontal scaling, or appear linked to it in some way. Register 2854 contains the 'master' value & the other registers can be calculated from that one. You must also remember to correctly set the divider in Reg 2874. To enlarge: Reg 2854 = (source_width * 0x00200000) / destination_width Reg 2874 = No divide To reduce from full size down to half size: Reg 2854 = (source_width/2 * 0x00200000) / destination width Reg 2874 = Divide by 2 To reduce from half size down to quarter size: Reg 2854 = (source_width/4 * 0x00200000) / destination width Reg 2874 = Divide by 4 The result is always rounded up. -------------------------------------------------------------------------------- 286C bits 0:15 Decoder horizontal Y buffer offset bits 15:31 Decoder horizontal UV buffer offset Offset into the video image buffer. If the offset is gradually incremented, the on screen image will move left & wrap around higher up on the right. -------------------------------------------------------------------------------- 2870 bits 0:15 Decoder horizontal Y output offset bits 16:31 Decoder horizontal UV output offset Offsets the actual video output. Controls output alignment of the Y & UV planes. The higher the value, the greater the shift to the left. Use reg 2890 to move the image right. -------------------------------------------------------------------------------- 2874 bits 0:1 Decoder horizontal Y output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bits 4:5 Decoder horizontal UV output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 3 bit 8 Decoder ?? unknown 0 = Normal 1 = Affects video output levels bit 16 Decoder ?? unknown 0 = Normal 1 = Disable horizontal filter -------------------------------------------------------------------------------- 2878 bit 0 ?? unknown bit 1 osd on/off 0 = osd off 1 = osd on bit 2 Decoder + osd video timing 0 = NTSC 1 = PAL bits 3:4 ?? unknown bit 5 Decoder + osd Swaps upper & lower fields -------------------------------------------------------------------------------- 287C bits 0:10 Decoder & osd ?? unknown Moves entire screen horizontally. Starts at 0x005 with the screen shifted heavily to the right. Incrementing in steps of 0x004 will gradually shift the screen to the left. bits 11:31 ?? unknown Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL) -------------------------------------------------------------------------------- 2880 -------- ?? unknown 2884 -------- ?? unknown -------------------------------------------------------------------------------- 2888 bit 0 Decoder + osd ?? unknown 0 = Normal 1 = Misaligned fields (Correctable through 289C & 28A4) bit 4 ?? unknown bit 8 ?? unknown Warning: Bad values will require a firmware reload to recover. Known to be bad are 0x000,0x011,0x100,0x111 -------------------------------------------------------------------------------- 288C bits 0:15 osd ?? unknown Appears to affect the osd position stability. The higher the value the more unstable it becomes. Decoder output remains stable. bits 16:31 osd ?? unknown Same as bits 0:15 -------------------------------------------------------------------------------- 2890 bits 0:11 Decoder output horizontal offset. Horizontal offset moves the video image right. A small left shift is possible, but it's better to use reg 2870 for that due to its greater range. NOTE: Video corruption will occur if video window is shifted off the right edge. To avoid this read the notes for 2834 & 2838. -------------------------------------------------------------------------------- 2894 bits 0:23 Decoder output video surround colour. Contains the colour (in yuv) used to fill the screen when the video is running in a window. -------------------------------------------------------------------------------- 2898 bits 0:23 Decoder video window colour Contains the colour (in yuv) used to fill the video window when the video is turned off. bit 24 Decoder video output 0 = Video on 1 = Video off bit 28 Decoder plane order 0 = Y,UV 1 = UV,Y bit 29 Decoder second plane byte order 0 = Normal (UV) 1 = Swapped (VU) In normal usage, the first plane is Y & the second plane is UV. Though the order of the planes can be swapped, only the byte order of the second plane can be swapped. This isn't much use for the Y plane, but can be useful for the UV plane. -------------------------------------------------------------------------------- 289C bits 0:15 Decoder vertical field offset 1 bits 16:31 Decoder vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL) -------------------------------------------------------------------------------- 28A0 bits 0:15 Decoder & osd width in pixels bits 16:31 Decoder & osd height in pixels All output from the decoder & osd are disabled beyond this area. Decoder output will simply go black outside of this region. If the osd tries to exceed this area it will become corrupt. -------------------------------------------------------------------------------- 28A4 bits 0:11 osd left shift. Has a range of 0x770->0x7FF. With the exception of 0, any value outside of this range corrupts the osd. -------------------------------------------------------------------------------- 28A8 bits 0:15 osd vertical field offset 1 bits 16:31 osd vertical field offset 2 Controls field output vertical alignment. The higher the number, the lower the image on screen. Known starting values are 0x011E0017 (NTSC) & 0x01500017 (PAL) -------------------------------------------------------------------------------- 28AC -------- ?? unknown | V 28BC -------- ?? unknown -------------------------------------------------------------------------------- 28C0 bit 0 Current output field 0 = first field 1 = second field bits 16:31 Current scanline The scanline counts from the top line of the first field through to the last line of the second field. -------------------------------------------------------------------------------- 28C4 -------- ?? unknown | V 28F8 -------- ?? unknown -------------------------------------------------------------------------------- 28FC bit 0 ?? unknown 0 = Normal 1 = Breaks decoder & osd output -------------------------------------------------------------------------------- 2900 bits 0:31 Decoder vertical Y alias register 1 --------------- 2904 bits 0:31 Decoder vertical Y alias register 2 --------------- 2908 bits 0:31 Decoder vertical Y alias trigger These three registers control the vertical aliasing filter for the Y plane. Operation is similar to the horizontal Y filter (2804). The only real difference is that there are only two registers to set before accessing the trigger register (2908). As for the horizontal filter, the values are taken from a lookup table in the firmware, and the procedure must be repeated 16 times to fully program the filter. -------------------------------------------------------------------------------- 290C bits 0:31 Decoder vertical UV alias register 1 --------------- 2910 bits 0:31 Decoder vertical UV alias register 2 --------------- 2914 bits 0:31 Decoder vertical UV alias trigger These three registers control the vertical aliasing filter for the UV plane. Operation is the same as the Y filter, with 2914 being the trigger. -------------------------------------------------------------------------------- 2918 bits 0:15 Decoder Y source height in pixels bits 16:31 Decoder Y destination height in pixels --------------- 291C bits 0:15 Decoder UV source height in pixels divided by 2 bits 16:31 Decoder UV destination height in pixels NOTE: For both registers, the resulting image must be fully visible on screen. If the image exceeds the bottom edge both the source and destination size must be adjusted to reflect the visible portion. For the source height, you must take into account the scaling when calculating the new value. -------------------------------------------------------------------------------- 2920 bits 0:31 Decoder Y vertical scaling Normally = Reg 2930 >> 2 --------------- 2924 bits 0:31 Decoder Y vertical scaling Normally = Reg 2920 + 0x514 --------------- 2928 bits 0:31 Decoder UV vertical scaling When enlarging = Reg 2930 >> 2 When reducing = Reg 2930 >> 3 --------------- 292C bits 0:31 Decoder UV vertical scaling Normally = Reg 2928 + 0x514 --------------- 2930 bits 0:31 Decoder 'master' value for vertical scaling --------------- 2934 bits 0:31 Decoder ?? unknown - Y vertical scaling --------------- 2938 bits 0:31 Decoder Y vertical scaling Normally = Reg 2930 --------------- 293C bits 0:31 Decoder ?? unknown - Y vertical scaling --------------- 2940 bits 0:31 Decoder UV vertical scaling When enlarging = Reg 2930 >> 1 When reducing = Reg 2930 --------------- 2944 bits 0:31 Decoder ?? unknown - UV vertical scaling --------------- 2948 bits 0:31 Decoder UV vertical scaling Normally = Reg 2940 --------------- 294C bits 0:31 Decoder ?? unknown - UV vertical scaling Most of these registers either control vertical scaling, or appear linked to it in some way. Register 2930 contains the 'master' value & all other registers can be calculated from that one. You must also remember to correctly set the divider in Reg 296C To enlarge: Reg 2930 = (source_height * 0x00200000) / destination_height Reg 296C = No divide To reduce from full size down to half size: Reg 2930 = (source_height/2 * 0x00200000) / destination height Reg 296C = Divide by 2 To reduce from half down to quarter. Reg 2930 = (source_height/4 * 0x00200000) / destination height Reg 296C = Divide by 4 -------------------------------------------------------------------------------- 2950 bits 0:15 Decoder Y line index into display buffer, first field bits 16:31 Decoder Y vertical line skip, first field -------------------------------------------------------------------------------- 2954 bits 0:15 Decoder Y line index into display buffer, second field bits 16:31 Decoder Y vertical line skip, second field -------------------------------------------------------------------------------- 2958 bits 0:15 Decoder UV line index into display buffer, first field bits 16:31 Decoder UV vertical line skip, first field -------------------------------------------------------------------------------- 295C bits 0:15 Decoder UV line index into display buffer, second field bits 16:31 Decoder UV vertical line skip, second field -------------------------------------------------------------------------------- 2960 bits 0:15 Decoder destination height minus 1 bits 16:31 Decoder destination height divided by 2 -------------------------------------------------------------------------------- 2964 bits 0:15 Decoder Y vertical offset, second field bits 16:31 Decoder Y vertical offset, first field These two registers shift the Y plane up. The higher the number, the greater the shift. -------------------------------------------------------------------------------- 2968 bits 0:15 Decoder UV vertical offset, second field bits 16:31 Decoder UV vertical offset, first field These two registers shift the UV plane up. The higher the number, the greater the shift. -------------------------------------------------------------------------------- 296C bits 0:1 Decoder vertical Y output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 4 bits 8:9 Decoder vertical UV output size divider 00 = No divide 01 = Divide by 2 10 = Divide by 4 -------------------------------------------------------------------------------- 2970 bit 0 Decoder ?? unknown 0 = Normal 1 = Affect video output levels bit 16 Decoder ?? unknown 0 = Normal 1 = Disable vertical filter -------------------------------------------------------------------------------- 2974 -------- ?? unknown | V 29EF -------- ?? unknown -------------------------------------------------------------------------------- 2A00 bits 0:2 osd colour mode 000 = 8 bit indexed 001 = 16 bit (565) 010 = 15 bit (555) 011 = 12 bit (444) 100 = 32 bit (8888) bits 4:5 osd display bpp 01 = 8 bit 10 = 16 bit 11 = 32 bit bit 8 osd global alpha 0 = Off 1 = On bit 9 osd local alpha 0 = Off 1 = On bit 10 osd colour key 0 = Off 1 = On bit 11 osd ?? unknown Must be 1 bit 13 osd colour space 0 = ARGB 1 = AYVU bits 16:31 osd ?? unknown Must be 0x001B (some kind of buffer pointer ?) When the bits-per-pixel is set to 8, the colour mode is ignored and assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth is honoured, and when using a colour depth that requires fewer bytes than allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit index colour, there are 3 padding bytes per pixel. It's also possible to select 16bpp with a 32 bit colour mode. This results in the pixel width being doubled, but the color key will not work as expected in this mode. Colour key is as it suggests. You designate a colour which will become completely transparent. When using 565, 555 or 444 colour modes, the colour key is always 16 bits wide. The colour to key on is set in Reg 2A18. Local alpha works differently depending on the colour mode. For 32bpp & 8 bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused bit(s) act as a simple transparency switch, with 0 being solid & 1 being fully transparent. There is no local alpha support for 16bit 565. Global alpha is a 256 step transparency that applies to the entire osd, with 0 being transparent & 255 being solid. It's possible to combine colour key, local alpha & global alpha. -------------------------------------------------------------------------------- 2A04 bits 0:15 osd x coord for left edge bits 16:31 osd y coord for top edge --------------- 2A08 bits 0:15 osd x coord for right edge bits 16:31 osd y coord for bottom edge For both registers, (0,0) = top left corner of the display area. These registers do not control the osd size, only where it's positioned & how much is visible. The visible osd area cannot exceed the right edge of the display, otherwise the osd will become corrupt. See reg 2A10 for setting osd width. -------------------------------------------------------------------------------- 2A0C bits 0:31 osd buffer index An index into the osd buffer. Slowly incrementing this moves the osd left, wrapping around onto the right edge -------------------------------------------------------------------------------- 2A10 bits 0:11 osd buffer 32 bit word width Contains the width of the osd measured in 32 bit words. This means that all colour modes are restricted to a byte width which is divisible by 4. -------------------------------------------------------------------------------- 2A14 bits 0:15 osd height in pixels bits 16:32 osd line index into buffer osd will start displaying from this line. -------------------------------------------------------------------------------- 2A18 bits 0:31 osd colour key Contains the colour value which will be transparent. -------------------------------------------------------------------------------- 2A1C bits 0:7 osd global alpha Contains the global alpha value (equiv ivtvfbctl --alpha XX) -------------------------------------------------------------------------------- 2A20 -------- ?? unknown | V 2A2C -------- ?? unknown -------------------------------------------------------------------------------- 2A30 bits 0:7 osd colour to change in indexed palette --------------- 2A34 bits 0:31 osd colour for indexed palette To set the new palette, first load the index of the colour to change into 2A30, then load the new colour into 2A34. The full palette is 256 colours, so the index range is 0x00-0xFF -------------------------------------------------------------------------------- 2A38 -------- ?? unknown 2A3C -------- ?? unknown -------------------------------------------------------------------------------- 2A40 bits 0:31 osd ?? unknown Affects overall brightness, wrapping around to black -------------------------------------------------------------------------------- 2A44 bits 0:31 osd ?? unknown Green tint -------------------------------------------------------------------------------- 2A48 bits 0:31 osd ?? unknown Red tint -------------------------------------------------------------------------------- 2A4C bits 0:31 osd ?? unknown Affects overall brightness, wrapping around to black -------------------------------------------------------------------------------- 2A50 bits 0:31 osd ?? unknown Colour shift -------------------------------------------------------------------------------- 2A54 bits 0:31 osd ?? unknown Colour shift -------------------------------------------------------------------------------- 2A58 -------- ?? unknown | V 2AFC -------- ?? unknown -------------------------------------------------------------------------------- 2B00 bit 0 osd filter control 0 = filter off 1 = filter on bits 1:4 osd ?? unknown --------------------------------------------------------------------------------}hj4Qsbah}(h]h ]h"]h$]h&]hhj'j(nonej*}uh1jhhhM hjPhhubeh}(h]4pvr350-video-decoder-registers-0x02002800-0x02002b00ah ]h"]7pvr350 video decoder registers 0x02002800 -> 0x02002b00ah$]h&]uh1hhhhhhhhM ubh)}(hhh](h)}(hThe cx231xx DMA engineh]hThe cx231xx DMA engine}(hjOQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLQhhhhhMubh)}(hQThis page describes the structures and procedures used by the cx2341x DMA engine.h]hQThis page describes the structures and procedures used by the cx2341x DMA engine.}(hj]QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLQhhubh)}(hhh](h)}(h Introductionh]h Introduction}(hjnQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkQhhhhhM ubh)}(hXPThe cx2341x PCI interface is busmaster capable. This means it has a DMA engine to efficiently transfer large volumes of data between the card and main memory without requiring help from a CPU. Like most hardware, it must operate on contiguous physical memory. This is difficult to come by in large quantities on virtual memory machines.h]hXPThe cx2341x PCI interface is busmaster capable. This means it has a DMA engine to efficiently transfer large volumes of data between the card and main memory without requiring help from a CPU. Like most hardware, it must operate on contiguous physical memory. This is difficult to come by in large quantities on virtual memory machines.}(hj|QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjkQhhubh)}(hTherefore, it also supports a technique called "scatter-gather". The card can transfer multiple buffers in one operation. Instead of allocating one large contiguous buffer, the driver can allocate several smaller buffers.h]hTherefore, it also supports a technique called “scatter-gather”. The card can transfer multiple buffers in one operation. Instead of allocating one large contiguous buffer, the driver can allocate several smaller buffers.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkQhhubh)}(hX|In practice, I've seen the average transfer to be roughly 80K, but transfers above 128K were not uncommon, particularly at startup. The 128K figure is important, because that is the largest block that the kernel can normally allocate. Even still, 128K blocks are hard to come by, so the driver writer is urged to choose a smaller block size and learn the scatter-gather technique.h]hX~In practice, I’ve seen the average transfer to be roughly 80K, but transfers above 128K were not uncommon, particularly at startup. The 128K figure is important, because that is the largest block that the kernel can normally allocate. Even still, 128K blocks are hard to come by, so the driver writer is urged to choose a smaller block size and learn the scatter-gather technique.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkQhhubh)}(h5Mailbox #10 is reserved for DMA transfer information.h]h5Mailbox #10 is reserved for DMA transfer information.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkQhhubh)}(h?Note: the hardware expects little-endian data ('intel format').h]hCNote: the hardware expects little-endian data (‘intel format’).}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkQhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1hhjLQhhhhhM ubh)}(hhh](h)}(hFlowh]hFlow}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhM"ubh)}(hThis section describes, in general, the order of events when handling DMA transfers. Detailed information follows this section.h]hThis section describes, in general, the order of events when handling DMA transfers. Detailed information follows this section.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjQhhubj)}(hhh](j)}(h&The card raises the Encoder interrupt.h]h)}(hjQh]h&The card raises the Encoder interrupt.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjQubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(hEThe driver reads the transfer type, offset and size from Mailbox #10.h]h)}(hjRh]hEThe driver reads the transfer type, offset and size from Mailbox #10.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjRubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(h^The driver constructs the scatter-gather array from enough free dma buffers to cover the size.h]h)}(h^The driver constructs the scatter-gather array from enough free dma buffers to cover the size.h]h^The driver constructs the scatter-gather array from enough free dma buffers to cover the size.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjRubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(hIThe driver schedules the DMA transfer via the ScheduleDMAtoHost API call.h]h)}(hj4Rh]hIThe driver schedules the DMA transfer via the ScheduleDMAtoHost API call.}(hj6RhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj2Rubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(h+The card raises the DMA Complete interrupt.h]h)}(hjKRh]h+The card raises the DMA Complete interrupt.}(hjMRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjIRubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(h9The driver checks the DMA status register for any errors.h]h)}(hjbRh]h9The driver checks the DMA status register for any errors.}(hjdRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj`Rubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubj)}(h9The driver post-processes the newly transferred buffers. h]h)}(h8The driver post-processes the newly transferred buffers.h]h8The driver post-processes the newly transferred buffers.}(hj{RhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjwRubah}(h]h ]h"]h$]h&]uh1jhjQhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM'hjQhhubh)}(hNOTE! It is possible that the Encoder and DMA Complete interrupts get raised simultaneously. (End of the last, start of the next, etc.)h]hNOTE! It is possible that the Encoder and DMA Complete interrupts get raised simultaneously. (End of the last, start of the next, etc.)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjQhhubeh}(h]flowah ]h"]flowah$]h&]uh1hhjLQhhhhhM"ubh)}(hhh](h)}(h Mailbox #10h]h Mailbox #10}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhhhhhM4ubh)}(h@The Flags, Command, Return Value and Timeout fields are ignored.h]h@The Flags, Command, Return Value and Timeout fields are ignored.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hjRhhubj)}(hhh](j)}(hName: Mailbox #10h]h)}(hjRh]hName: Mailbox #10}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hjRubah}(h]h ]h"]h$]h&]uh1jhjRhhhhhNubj)}(hResults[0]: Type: 0: MPEG.h]h)}(hjRh]hResults[0]: Type: 0: MPEG.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjRubah}(h]h ]h"]h$]h&]uh1jhjRhhhhhNubj)}(hEResults[1]: Offset: The position relative to the card's memory space.h]h)}(hjRh]hGResults[1]: Offset: The position relative to the card’s memory space.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjRubah}(h]h ]h"]h$]h&]uh1jhjRhhhhhNubj)}(h9Results[2]: Size: The exact number of bytes to transfer. h]h)}(h8Results[2]: Size: The exact number of bytes to transfer.h]h8Results[2]: Size: The exact number of bytes to transfer.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjSubah}(h]h ]h"]h$]h&]uh1jhjRhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM8hjRhhubh)}(hMy speculation is that since the StartCapture API has a capture type of "RAW" available, that the type field will have other values that correspond to YUV and PCM data.h]hMy speculation is that since the StartCapture API has a capture type of “RAW” available, that the type field will have other values that correspond to YUV and PCM data.}(hj0ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjRhhubeh}(h] mailbox-10ah ]h"] mailbox #10ah$]h&]uh1hhjLQhhhhhM4ubh)}(hhh](h)}(hScatter-Gather Arrayh]hScatter-Gather Array}(hjIShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFShhhhhMBubh)}(hX#The scatter-gather array is a contiguously allocated block of memory that tells the card the source and destination of each data-block to transfer. Card "addresses" are derived from the offset supplied by Mailbox #10. Host addresses are the physical memory location of the target DMA buffer.h]hX'The scatter-gather array is a contiguously allocated block of memory that tells the card the source and destination of each data-block to transfer. Card “addresses” are derived from the offset supplied by Mailbox #10. Host addresses are the physical memory location of the target DMA buffer.}(hjWShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjFShhubh)}(hXEach S-G array element is a struct of three 32-bit words. The first word is the source address, the second is the destination address. Both take up the entire 32 bits. The lowest 18 bits of the third word is the transfer byte count. The high-bit of the third word is the "last" flag. The last-flag tells the card to raise the DMA_DONE interrupt. From hard personal experience, if you forget to set this bit, the card will still "work" but the stream will most likely get corrupted.h]hXEach S-G array element is a struct of three 32-bit words. The first word is the source address, the second is the destination address. Both take up the entire 32 bits. The lowest 18 bits of the third word is the transfer byte count. The high-bit of the third word is the “last” flag. The last-flag tells the card to raise the DMA_DONE interrupt. From hard personal experience, if you forget to set this bit, the card will still “work” but the stream will most likely get corrupted.}(hjeShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhjFShhubh)}(hThe transfer count must be a multiple of 256. Therefore, the driver will need to track how much data in the target buffer is valid and deal with it accordingly.h]hThe transfer count must be a multiple of 256. Therefore, the driver will need to track how much data in the target buffer is valid and deal with it accordingly.}(hjsShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjFShhubh)}(hArray Element:h]hArray Element:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjFShhubj)}(hhh](j)}(h32-bit Source Addressh]h)}(hjSh]h32-bit Source Address}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjSubah}(h]h ]h"]h$]h&]uh1jhjShhhhhNubj)}(h32-bit Destination Addressh]h)}(hjSh]h32-bit Destination Address}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjSubah}(h]h ]h"]h$]h&]uh1jhjShhhhhNubj)}(h+14-bit reserved (high bit is the last flag)h]h)}(hjSh]h+14-bit reserved (high bit is the last flag)}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjSubah}(h]h ]h"]h$]h&]uh1jhjShhhhhNubj)}(h18-bit byte count h]h)}(h18-bit byte counth]h18-bit byte count}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjSubah}(h]h ]h"]h$]h&]uh1jhjShhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMWhjFShhubeh}(h]scatter-gather-arrayah ]h"]scatter-gather arrayah$]h&]uh1hhjLQhhhhhMBubh)}(hhh](h)}(hDMA Transfer Statush]hDMA Transfer Status}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhM]ubh)}(h.Register 0x0004 holds the DMA Transfer Status:h]h.Register 0x0004 holds the DMA Transfer Status:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hjShhubj)}(hhh](j)}(hbit 0: read completedh]h)}(hj!Th]hbit 0: read completed}(hj#ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjTubah}(h]h ]h"]h$]h&]uh1jhjThhhhhNubj)}(hbit 1: write completedh]h)}(hj8Th]hbit 1: write completed}(hj:ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj6Tubah}(h]h ]h"]h$]h&]uh1jhjThhhhhNubj)}(hbit 2: DMA read errorh]h)}(hjOTh]hbit 2: DMA read error}(hjQThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjMTubah}(h]h ]h"]h$]h&]uh1jhjThhhhhNubj)}(hbit 3: DMA write errorh]h)}(hjfTh]hbit 3: DMA write error}(hjhThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjdTubah}(h]h ]h"]h$]h&]uh1jhjThhhhhNubj)}(h#bit 4: Scatter-Gather array errorh]h)}(hj}Th]h#bit 4: Scatter-Gather array error}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj{Tubah}(h]h ]h"]h$]h&]uh1jhjThhhhhNubeh}(h]h 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implicit target name: "param[6]".h]h/Duplicate implicit target name: “param[6]”.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmubah}(h]h ]h"]h$]h&]jDalevelKtypej`UsourcehlineM7 uh1jEUhjDhhhhhM7 ubjFU)}(hhh]h)}(h.Duplicate implicit target name: "description".h]h2Duplicate implicit target name: “description”.}(hj!mhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmubah}(h]h ]h"]h$]h&]j4EalevelKtypej`UsourcehlineMD uh1jEUhjEhhhhhMD ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[0]".h]h/Duplicate implicit target name: “param[0]”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;qubah}(h]h ]h"]h$]h&]jhNalevelKtypej`UsourcehlineMs uh1jEUhjGNhhhhhMs ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[0]".h]h/Duplicate implicit target name: “param[0]”.}(hjYqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVqubah}(h]h ]h"]h$]h&]jNalevelKtypej`UsourcehlineMy uh1jEUhjnNhhhhhMy ubjFU)}(hhh]h)}(h.Duplicate implicit target name: "description".h]h2Duplicate implicit target name: “description”.}(hjtqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqqubah}(h]h ]h"]h$]h&]jNalevelKtypej`UsourcehlineM uh1jEUhjNhhhhhM ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[0]".h]h/Duplicate implicit target name: “param[0]”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubah}(h]h ]h"]h$]h&]jOalevelKtypej`UsourcehlineM uh1jEUhjNhhhhhM ubjFU)}(hhh]h)}(h,Duplicate implicit target name: "result[0]".h]h0Duplicate implicit target name: “result[0]”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubah}(h]h ]h"]h$]h&]j+OalevelKtypej`UsourcehlineM uh1jEUhj OhhhhhM ubjFU)}(hhh]h)}(h,Duplicate implicit target name: "result[1]".h]h0Duplicate implicit target name: “result[1]”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubah}(h]h ]h"]h$]h&]jROalevelKtypej`UsourcehlineM uh1jEUhj1OhhhhhM ubjFU)}(hhh]h)}(h.Duplicate implicit target name: "description".h]h2Duplicate implicit target name: “description”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubah}(h]h ]h"]h$]h&]jOalevelKtypej`UsourcehlineM uh1jEUhjOhhhhhM ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[0]".h]h/Duplicate implicit target name: “param[0]”.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqubah}(h]h ]h"]h$]h&]jOalevelKtypej`UsourcehlineM uh1jEUhjOhhhhhM ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[1]".h]h/Duplicate implicit target name: “param[1]”.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrubah}(h]h ]h"]h$]h&]jOalevelKtypej`UsourcehlineM uh1jEUhjOhhhhhM ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[2]".h]h/Duplicate implicit target name: “param[2]”.}(hj1rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.rubah}(h]h ]h"]h$]h&]jPalevelKtypej`UsourcehlineM uh1jEUhjOhhhhhM ubjFU)}(hhh]h)}(h+Duplicate implicit target name: "param[3]".h]h/Duplicate implicit target name: “param[3]”.}(hjLrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIrubah}(h]h ]h"]h$]h&]j