€•l)      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ)/translations/zh_CN/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/zh_TW/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/it_IT/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/ja_JP/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/ko_KR/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/pt_BR/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/sp_SP/driver-api/fpga/intro”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒIntroduction”h]”hŒIntroduction”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒC/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/intro.rst”h´KubhŒ	paragraph”“”)”}”(hŒThe FPGA subsystem supports reprogramming FPGAs dynamically under
Linux.  Some of the core intentions of the FPGA subsystems are:”h]”hŒThe FPGA subsystem supports reprogramming FPGAs dynamically under
Linux.  Some of the core intentions of the FPGA subsystems are:”…””}”(hhÍh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ'The FPGA subsystem is vendor agnostic.
”h]”hÌ)”}”(hŒ&The FPGA subsystem is vendor agnostic.”h]”hŒ&The FPGA subsystem is vendor agnostic.”…””}”(hhæh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khhâubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhhÝh²hh³hÊh´Nubhá)”}”(hŒThe FPGA subsystem separates upper layers (userspace interfaces and
enumeration) from lower layers that know how to program a specific
FPGA.
”h]”hÌ)”}”(hŒŒThe FPGA subsystem separates upper layers (userspace interfaces and
enumeration) from lower layers that know how to program a specific
FPGA.”h]”hŒŒThe FPGA subsystem separates upper layers (userspace interfaces and
enumeration) from lower layers that know how to program a specific
FPGA.”…””}”(hhþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K	hhúubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhhÝh²hh³hÊh´Nubhá)”}”(hXE  Code should not be shared between upper and lower layers.  This
should go without saying.  If that seems necessary, there's probably
framework functionality that can be added that will benefit
other users.  Write the linux-fpga mailing list and maintainers and
seek out a solution that expands the framework for broad reuse.
”h]”hÌ)”}”(hXD  Code should not be shared between upper and lower layers.  This
should go without saying.  If that seems necessary, there's probably
framework functionality that can be added that will benefit
other users.  Write the linux-fpga mailing list and maintainers and
seek out a solution that expands the framework for broad reuse.”h]”hXF  Code should not be shared between upper and lower layers.  This
should go without saying.  If that seems necessary, thereâ€™s probably
framework functionality that can be added that will benefit
other users.  Write the linux-fpga mailing list and maintainers and
seek out a solution that expands the framework for broad reuse.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhhÝh²hh³hÊh´Nubhá)”}”(hŒCGenerally, when adding code, think of the future.  Plan for reuse.
”h]”hÌ)”}”(hŒBGenerally, when adding code, think of the future.  Plan for reuse.”h]”hŒBGenerally, when adding code, think of the future.  Plan for reuse.”…””}”(hj.  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khj*  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hàhhÝh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1hÛh³hÊh´Khh·h²hubhÌ)”}”(hŒ,The framework in the kernel is divided into:”h]”hŒ,The framework in the kernel is divided into:”…””}”(hjJ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒFPGA Manager”h]”hŒFPGA Manager”…””}”(hj[  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjX  h²hh³hÊh´KubhÌ)”}”(hX*  If you are adding a new FPGA or a new method of programming an FPGA,
this is the subsystem for you.  Low level FPGA manager drivers contain
the knowledge of how to program a specific device.  This subsystem
includes the framework in fpga-mgr.c and the low level drivers that
are registered with it.”h]”hX*  If you are adding a new FPGA or a new method of programming an FPGA,
this is the subsystem for you.  Low level FPGA manager drivers contain
the knowledge of how to program a specific device.  This subsystem
includes the framework in fpga-mgr.c and the low level drivers that
are registered with it.”…””}”(hji  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjX  h²hubeh}”(h]”Œfpga-manager”ah ]”h"]”Œfpga manager”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒFPGA Bridge”h]”hŒFPGA Bridge”…””}”(hj‚  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´K!ubhÌ)”}”(hX½  FPGA Bridges prevent spurious signals from going out of an FPGA or a
region of an FPGA during programming.  They are disabled before
programming begins and re-enabled afterwards.  An FPGA bridge may be
actual hard hardware that gates a bus to a CPU or a soft ("freeze")
bridge in FPGA fabric that surrounds a partial reconfiguration region
of an FPGA.  This subsystem includes fpga-bridge.c and the low level
drivers that are registered with it.”h]”hXÁ  FPGA Bridges prevent spurious signals from going out of an FPGA or a
region of an FPGA during programming.  They are disabled before
programming begins and re-enabled afterwards.  An FPGA bridge may be
actual hard hardware that gates a bus to a CPU or a soft (â€œfreezeâ€)
bridge in FPGA fabric that surrounds a partial reconfiguration region
of an FPGA.  This subsystem includes fpga-bridge.c and the low level
drivers that are registered with it.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K#hj  h²hubeh}”(h]”Œfpga-bridge”ah ]”h"]”Œfpga bridge”ah$]”h&]”uh1hµhh·h²hh³hÊh´K!ubh¶)”}”(hhh]”(h»)”}”(hŒFPGA Region”h]”hŒFPGA Region”…””}”(hj©  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj¦  h²hh³hÊh´K,ubhÌ)”}”(hŒYIf you are adding a new interface to the FPGA framework, add it on top
of an FPGA region.”h]”hŒYIf you are adding a new interface to the FPGA framework, add it on top
of an FPGA region.”…””}”(hj·  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K.hj¦  h²hubhÌ)”}”(hŒÊThe FPGA Region framework (fpga-region.c) associates managers and
bridges as reconfigurable regions.  A region may refer to the whole
FPGA in full reconfiguration or to a partial reconfiguration region.”h]”hŒÊThe FPGA Region framework (fpga-region.c) associates managers and
bridges as reconfigurable regions.  A region may refer to the whole
FPGA in full reconfiguration or to a partial reconfiguration region.”…””}”(hjÅ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K1hj¦  h²hubhÌ)”}”(hŒyThe Device Tree FPGA Region support (of-fpga-region.c) handles
reprogramming FPGAs when device tree overlays are applied.”h]”hŒyThe Device Tree FPGA Region support (of-fpga-region.c) handles
reprogramming FPGAs when device tree overlays are applied.”…””}”(hjÓ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K5hj¦  h²hubeh}”(h]”Œfpga-region”ah ]”h"]”Œfpga region”ah$]”h&]”uh1hµhh·h²hh³hÊh´K,ubeh}”(h]”Œintroduction”ah ]”h"]”Œintroduction”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jî  jë  j|  jy  j£  j   jæ  jã  uŒ	nametypes”}”(jî  ‰j|  ‰j£  ‰jæ  ‰uh}”(jë  h·jy  jX  j   j  jã  j¦  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.