€•Œsphinx.addnodes”Œdocument”“”)�”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)�”}”(hhh]”(hŒ pending_xref”“”)�”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…”�”}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ//translations/zh_CN/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)�”}”(hhh]”hŒChinese (Traditional)”…”�”}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/zh_TW/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒItalian”…”�”}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/it_IT/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒJapanese”…”�”}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/ja_JP/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒKorean”…”�”}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/ko_KR/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒPortuguese (Brazilian)”…”�”}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/pt_BR/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒSpanish”…”�”}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ//translations/sp_SP/driver-api/fpga/fpga-region”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)�”}”(hhh]”(hŒtitle”“”)�”}”(hŒ FPGA Region”h]”hŒ FPGA Region”…”�”}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒI/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region.rst”h´Kubh¶)�”}”(hhh]”(h»)�”}”(hŒOverview”h]”hŒOverview”…”�”}”(hhÎh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhËh²hh³hÊh´KubhŒ paragraph”“”)�”}”(hŒ§This document is meant to be a brief overview of the FPGA region API usage. A more conceptual look at regions can be found in the Device Tree binding document [#f1]_.”h]”(hŒ This document is meant to be a brief overview of the FPGA region API usage. A more conceptual look at regions can be found in the Device Tree binding document ”…”�”}”(hhÞh²hh³Nh´NubhŒfootnote_reference”“”)�”}”(hŒ[#f1]_”h]”hŒ1”…”�”}”(hhèh²hh³Nh´Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œauto”KŒrefid”Œf1”Œdocname”Œdriver-api/fpga/fpga-region”uh1hæhhÞŒresolved”KubhŒ.”…”�”}”(hhÞh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)�”}”(hŒùFor the purposes of this API document, let's just say that a region associates an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an FPGA or the whole FPGA. The API provides a way to register a region and to program a region.”h]”hŒûFor the purposes of this API document, let’s just say that a region associates an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an FPGA or the whole FPGA. The API provides a way to register a region and to program a region.”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K hhËh²hubhÝ)�”}”(hX\Currently the only layer above fpga-region.c in the kernel is the Device Tree support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions to program the FPGA and then DT to handle enumeration. The common region code is intended to be used by other schemes that have other ways of accomplishing enumeration after programming.”h]”(hŒvCurrently the only layer above fpga-region.c in the kernel is the Device Tree support (of-fpga-region.c) described in ”…”�”}”(hjh²hh³Nh´Nubhç)�”}”(hŒ[#f1]_”h]”hŒ1”…”�”}”(hjh²hh³Nh´Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”h÷Khøhùhúhûuh1hæhjhüKubhŒà. The DT support layer uses regions to program the FPGA and then DT to handle enumeration. The common region code is intended to be used by other schemes that have other ways of accomplishing enumeration after programming.”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)�”}”(hŒ:An fpga-region can be set up to know the following things:”h]”hŒ:An fpga-region can be set up to know the following things:”…”�”}”(hj6h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhŒ block_quote”“”)�”}”(hŒx* which FPGA manager to use to do the programming * which bridges to disable before programming and enable afterwards. ”h]”hŒ bullet_list”“”)�”}”(hhh]”(hŒ list_item”“”)�”}”(hŒ0which FPGA manager to use to do the programming ”h]”hÝ)�”}”(hŒ/which FPGA manager to use to do the programming”h]”hŒ/which FPGA manager to use to do the programming”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhjQubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjLubjP)�”}”(hŒCwhich bridges to disable before programming and enable afterwards. ”h]”hÝ)�”}”(hŒBwhich bridges to disable before programming and enable afterwards.”h]”hŒBwhich bridges to disable before programming and enable afterwards.”…”�”}”(hjmh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjiubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjLubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1jJh³hÊh´KhjFubah}”(h]”h ]”h"]”h$]”h&]”uh1jDh³hÊh´KhhËh²hubhÝ)�”}”(hŒcAdditional info needed to program the FPGA image is passed in the struct fpga_image_info including:”h]”hŒcAdditional info needed to program the FPGA image is passed in the struct fpga_image_info including:”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubjE)�”}”(hŒÉ* pointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file * flags indicating specifics such as whether the image is for partial reconfiguration. ”h]”jK)�”}”(hhh]”(jP)�”}”(hŒkpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file ”h]”hÝ)�”}”(hŒjpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file”h]”hŒjpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file”…”�”}”(hj¨h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khj¤ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhj¡ubjP)�”}”(hŒUflags indicating specifics such as whether the image is for partial reconfiguration. ”h]”hÝ)�”}”(hŒTflags indicating specifics such as whether the image is for partial reconfiguration.”h]”hŒTflags indicating specifics such as whether the image is for partial reconfiguration.”…”�”}”(hjÀh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K"hj¼ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhj¡ubeh}”(h]”h ]”h"]”h$]”h&]”j‡jˆuh1jJh³hÊh´Khj�ubah}”(h]”h ]”h"]”h$]”h&]”uh1jDh³hÊh´KhhËh²hubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)�”}”(hhh]”(h»)�”}”(hŒHow to add a new FPGA region”h]”hŒHow to add a new FPGA region”…”�”}”(hjëh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjèh²hh³hÊh´K&ubhÝ)�”}”(hŒ@An example of usage can be seen in the probe function of [#f2]_.”h]”(hŒ9An example of usage can be seen in the probe function of ”…”�”}”(hjùh²hh³Nh´Nubhç)�”}”(hŒ[#f2]_”h]”hŒ2”…”�”}”(hjh²hh³Nh´Nubah}”(h]”Œid3”ah ]”h"]”h$]”h&]”h÷KhøŒf2”húhûuh1hæhjùhüKubhŒ.”…”�”}”(hjùh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K(hjèh²hubhŒfootnote”“”)�”}”(hŒ+../devicetree/bindings/fpga/fpga-region.txt”h]”(hŒlabel”“”)�”}”(hhh]”hŒ1”…”�”}”(hj#h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j!hjh²hh³Nh´NubhÝ)�”}”(hjh]”hŒ+../devicetree/bindings/fpga/fpga-region.txt”…”�”}”(hj0h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K*hjubeh}”(h]”hùah ]”h"]”Œf1”ah$]”h&]”(hòj'eh÷Khúhûuh1jh³hÊh´K*hjèh²hubj)�”}”(hŒ$../../drivers/fpga/of-fpga-region.c ”h]”(j")�”}”(hhh]”hŒ2”…”�”}”(hjHh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j!hjDh²hh³Nh´NubhÝ)�”}”(hŒ#../../drivers/fpga/of-fpga-region.c”h]”hŒ#../../drivers/fpga/of-fpga-region.c”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K+hjDubeh}”(h]”jah ]”h"]”Œf2”ah$]”h&]”j ah÷Khúhûuh1jh³hÊh´K+hjèh²hubeh}”(h]”Œhow-to-add-a-new-fpga-region”ah ]”h"]”Œhow to add a new fpga region”ah$]”h&]”uh1hµhh·h²hh³hÊh´K&ubh¶)�”}”(hhh]”(h»)�”}”(hŒAPI to add a new FPGA region”h]”hŒAPI to add a new FPGA region”…”�”}”(hjuh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjrh²hh³hÊh´K.ubjK)�”}”(hhh]”(jP)�”}”(hŒ+struct fpga_region - The FPGA region struct”h]”hÝ)�”}”(hjˆh]”hŒ+struct fpga_region - The FPGA region struct”…”�”}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K0hj†ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjƒh²hh³hÊh´NubjP)�”}”(hŒOstruct fpga_region_info - Parameter structure for __fpga_region_register_full()”h]”hÝ)�”}”(hjŸh]”hŒOstruct fpga_region_info - Parameter structure for __fpga_region_register_full()”…”�”}”(hj¡h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K1hj�ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjƒh²hh³hÊh´NubjP)�”}”(hŒ“__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of options”h]”hÝ)�”}”(hŒ“__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of options”h]”hŒ“__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of options”…”�”}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K2hj´ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjƒh²hh³hÊh´NubjP)�”}”(hŒW__fpga_region_register() - Create and register an FPGA region using standard arguments”h]”hÝ)�”}”(hŒW__fpga_region_register() - Create and register an FPGA region using standard arguments”h]”hŒW__fpga_region_register() - Create and register an FPGA region using standard arguments”…”�”}”(hjÐh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K4hjÌubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjƒh²hh³hÊh´NubjP)�”}”(hŒ6fpga_region_unregister() - Unregister an FPGA region ”h]”hÝ)�”}”(hŒ5fpga_region_unregister() - Unregister an FPGA region”h]”hŒ5fpga_region_unregister() - Unregister an FPGA region”…”�”}”(hjèh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K6hjäubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjƒh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j‡jˆuh1jJh³hÊh´K0hjrh²hubhÝ)�”}”(hŒ–Helper macros ``fpga_region_register()`` and ``fpga_region_register_full()`` automatically set the module that registers the FPGA region as the owner.”h]”(hŒHelper macros ”…”�”}”(hjh²hh³Nh´NubhŒliteral”“”)�”}”(hŒ``fpga_region_register()``”h]”hŒfpga_region_register()”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjubhŒ and ”…”�”}”(hjh²hh³Nh´Nubj )�”}”(hŒ``fpga_region_register_full()``”h]”hŒfpga_region_register_full()”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjubhŒJ automatically set the module that registers the FPGA region as the owner.”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K8hjrh²hubhÝ)�”}”(hŒ¸The FPGA region's probe function will need to get a reference to the FPGA Manager it will be using to do the programming. This usually would happen during the region's probe function.”h]”hŒ¼The FPGA region’s probe function will need to get a reference to the FPGA Manager it will be using to do the programming. This usually would happen during the region’s probe function.”…”�”}”(hj6h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K;hjrh²hubjK)�”}”(hhh]”(jP)�”}”(hŒDfpga_mgr_get() - Get a reference to an FPGA manager, raise ref count”h]”hÝ)�”}”(hjIh]”hŒDfpga_mgr_get() - Get a reference to an FPGA manager, raise ref count”…”�”}”(hjKh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K?hjGubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjDh²hh³hÊh´NubjP)�”}”(hŒ^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.”h]”hÝ)�”}”(hŒ^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.”h]”hŒ^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.”…”�”}”(hjbh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K@hj^ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjDh²hh³hÊh´NubjP)�”}”(hŒ%fpga_mgr_put() - Put an FPGA manager ”h]”hÝ)�”}”(hŒ$fpga_mgr_put() - Put an FPGA manager”h]”hŒ$fpga_mgr_put() - Put an FPGA manager”…”�”}”(hjzh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KBhjvubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjDh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j‡jˆuh1jJh³hÊh´K?hjrh²hubhÝ)�”}”(hX¨The FPGA region will need to specify which bridges to control while programming the FPGA. The region driver can build a list of bridges during probe time (:c:expr:`fpga_region->bridge_list`) or it can have a function that creates the list of bridges to program just before programming (:c:expr:`fpga_region->get_bridges`). The FPGA bridge framework supplies the following APIs to handle building or tearing down that list.”h]”(hŒœThe FPGA region will need to specify which bridges to control while programming the FPGA. The region driver can build a list of bridges during probe time (”…”�”}”(hj”h²hh³Nh´NubhŒ desc_inline”“”)�”}”(hŒfpga_region->bridge_list”h]”(h)�”}”(hhh]”hŒ desc_sig_name”“”)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hj§h²hh³Nh´Nubah}”(h]”h ]”Œn”ah"]”h$]”h&]”uh1j¥hj¢ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”Œc”Œreftype”Œ identifier”Œ reftarget”j©Œmodname”NŒ classname”NŒ c:parent_key”Œsphinx.domains.c”Œ LookupKey”“”)�”}”Œdata”]”sbuh1hhjžubhŒdesc_sig_operator”“”)�”}”(hŒ->”h]”hŒ->”…”�”}”(hjÍh²hh³Nh´Nubah}”(h]”h ]”Œo”ah"]”h$]”h&]”uh1jËhjžubj¦)�”}”(hŒ bridge_list”h]”hŒ bridge_list”…”�”}”(hjÜh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjžubeh}”(h]”h ]”(Œc-expr”Œsig”Œ sig-inline”j½eh"]”h$]”h&]”uh1jœhj”ubhŒa) or it can have a function that creates the list of bridges to program just before programming (”…”�”}”(hj”h²hh³Nh´Nubj�)�”}”(hŒfpga_region->get_bridges”h]”(h)�”}”(hhh]”j¦)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hjþh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjûubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”sbuh1hhj÷ubjÌ)�”}”(hjÏh]”hŒ->”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”jØah"]”h$]”h&]”uh1jËhj÷ubj¦)�”}”(hŒ get_bridges”h]”hŒ get_bridges”…”�”}”(hj'h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj÷ubeh}”(h]”h ]”(jíjîjïj½eh"]”h$]”h&]”uh1jœhj”ubhŒg). The FPGA bridge framework supplies the following APIs to handle building or tearing down that list.”…”�”}”(hj”h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KDhjrh²hubjK)�”}”(hhh]”(jP)�”}”(hŒIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list”h]”hÝ)�”}”(hŒIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list”h]”hŒIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list”…”�”}”(hjLh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KKhjHubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjEh²hh³hÊh´NubjP)�”}”(hŒaof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device node”h]”hÝ)�”}”(hŒaof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device node”h]”hŒaof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device node”…”�”}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KMhj`ubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjEh²hh³hÊh´NubjP)�”}”(hŒ7fpga_bridges_put() - Given a list of bridges, put them ”h]”hÝ)�”}”(hŒ6fpga_bridges_put() - Given a list of bridges, put them”h]”hŒ6fpga_bridges_put() - Given a list of bridges, put them”…”�”}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KOhjxubah}”(h]”h ]”h"]”h$]”h&]”uh1jOhjEh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j‡jˆuh1jJh³hÊh´KKhjrh²hubhŒindex”“”)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(Œsingle”Œfpga_region (C struct)”Œ c.fpga_region”hNt”auh1j–hjrh²hh³Nh´NubhŒdesc”“”)�”}”(hhh]”(hŒdesc_signature”“”)�”}”(hŒ fpga_region”h]”hŒdesc_signature_line”“”)�”}”(hŒstruct fpga_region”h]”(hŒdesc_sig_keyword”“”)�”}”(hŒstruct”h]”hŒstruct”…”�”}”(hjºh²hh³Nh´Nubah}”(h]”h ]”Œk”ah"]”h$]”h&]”uh1j¸hj´h²hh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´KubhŒdesc_sig_space”“”)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÌh²hh³Nh´Nubah}”(h]”h ]”Œw”ah"]”h$]”h&]”uh1jÊhj´h²hh³jÉh´KubhŒ desc_name”“”)�”}”(hŒ fpga_region”h]”j¦)�”}”(hj°h]”hŒ fpga_region”…”�”}”(hjáh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÝubah}”(h]”h ]”(Œsig-name”Œdescname”eh"]”h$]”h&]”Œ xml:space”Œpreserve”uh1jÛhj´h²hh³jÉh´Kubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷Œ add_permalink”ˆuh1j²Œsphinx_line_type”Œ declarator”hj®h²hh³jÉh´Kubah}”(h]”j¥ah ]”(jîŒ sig-object”eh"]”h$]”h&]”Œ is_multiline”ˆŒ _toc_parts”)Œ _toc_name”huh1j¬h³jÉh´Khj©h²hubhŒ desc_content”“”)�”}”(hhh]”hÝ)�”}”(hŒFPGA Region structure”h]”hŒFPGA Region structure”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K hj h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj©h²hh³jÉh´Kubeh}”(h]”h ]”(j½Œstruct”eh"]”h$]”h&]”Œdomain”j½Œobjtype”j(Œdesctype”j(Œnoindex”‰Œ noindexentry”‰Œnocontentsentry”‰uh1j§h²hhjrh³Nh´NubhŒ container”“”)�”}”(hXó**Definition**:: struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); }; **Members** ``dev`` FPGA Region device ``mutex`` enforces exclusive reference to region ``bridge_list`` list of FPGA bridges specified in region ``mgr`` FPGA manager ``info`` FPGA image info ``compat_id`` FPGA region id for compatibility check. ``ops_owner`` module containing the get_bridges function ``priv`` private data ``get_bridges`` optional function to get bridges to a list”h]”(hÝ)�”}”(hŒ**Definition**::”h]”(hŒstrong”“”)�”}”(hŒ**Definition**”h]”hŒ Definition”…”�”}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj8ubhŒ:”…”�”}”(hj8h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K$hj4ubhŒ literal_block”“”)�”}”(hX0struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); };”h]”hX0struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); };”…”�”}”hjYsbah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1jWh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K&hj4ubhÝ)�”}”(hŒ **Members**”h]”j=)�”}”(hjjh]”hŒMembers”…”�”}”(hjlh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjhubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K2hj4ubhŒdefinition_list”“”)�”}”(hhh]”(hŒdefinition_list_item”“”)�”}”(hŒ``dev`` FPGA Region device ”h]”(hŒterm”“”)�”}”(hŒ``dev``”h]”j )�”}”(hj�h]”hŒdev”…”�”}”(hj‘h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj�ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K"hj‡ubhŒ definition”“”)�”}”(hhh]”hÝ)�”}”(hŒFPGA Region device”h]”hŒFPGA Region device”…”�”}”(hjªh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j¤h´K"hj§ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj‡ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j¤h´K"hj‚ubj†)�”}”(hŒ1``mutex`` enforces exclusive reference to region ”h]”(jŒ)�”}”(hŒ ``mutex``”h]”j )�”}”(hjÊh]”hŒmutex”…”�”}”(hjÌh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjÈubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K#hjÄubj¦)�”}”(hhh]”hÝ)�”}”(hŒ&enforces exclusive reference to region”h]”hŒ&enforces exclusive reference to region”…”�”}”(hjãh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jßh´K#hjàubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjÄubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jßh´K#hj‚ubj†)�”}”(hŒ9``bridge_list`` list of FPGA bridges specified in region ”h]”(jŒ)�”}”(hŒ``bridge_list``”h]”j )�”}”(hjh]”hŒ bridge_list”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K$hjýubj¦)�”}”(hhh]”hÝ)�”}”(hŒ(list of FPGA bridges specified in region”h]”hŒ(list of FPGA bridges specified in region”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jh´K$hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjýubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jh´K$hj‚ubj†)�”}”(hŒ``mgr`` FPGA manager ”h]”(jŒ)�”}”(hŒ``mgr``”h]”j )�”}”(hj<h]”hŒmgr”…”�”}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj:ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K%hj6ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ FPGA manager”h]”hŒ FPGA manager”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jQh´K%hjRubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj6ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jQh´K%hj‚ubj†)�”}”(hŒ``info`` FPGA image info ”h]”(jŒ)�”}”(hŒ``info``”h]”j )�”}”(hjuh]”hŒinfo”…”�”}”(hjwh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjsubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K&hjoubj¦)�”}”(hhh]”hÝ)�”}”(hŒFPGA image info”h]”hŒFPGA image info”…”�”}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jŠh´K&hj‹ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjoubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jŠh´K&hj‚ubj†)�”}”(hŒ6``compat_id`` FPGA region id for compatibility check. ”h]”(jŒ)�”}”(hŒ ``compat_id``”h]”j )�”}”(hj®h]”hŒ compat_id”…”�”}”(hj°h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj¬ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K'hj¨ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ'FPGA region id for compatibility check.”h]”hŒ'FPGA region id for compatibility check.”…”�”}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÃh´K'hjÄubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj¨ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jÃh´K'hj‚ubj†)�”}”(hŒ9``ops_owner`` module containing the get_bridges function ”h]”(jŒ)�”}”(hŒ ``ops_owner``”h]”j )�”}”(hjçh]”hŒ ops_owner”…”�”}”(hjéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjåubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K(hjáubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*module containing the get_bridges function”h]”hŒ*module containing the get_bridges function”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jüh´K(hjýubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjáubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jüh´K(hj‚ubj†)�”}”(hŒ``priv`` private data ”h]”(jŒ)�”}”(hŒ``priv``”h]”j )�”}”(hj h]”hŒpriv”…”�”}”(hj"h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K)hjubj¦)�”}”(hhh]”hÝ)�”}”(hŒ private data”h]”hŒ private data”…”�”}”(hj9h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j5h´K)hj6ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j5h´K)hj‚ubj†)�”}”(hŒ:``get_bridges`` optional function to get bridges to a list”h]”(jŒ)�”}”(hŒ``get_bridges``”h]”j )�”}”(hjYh]”hŒ get_bridges”…”�”}”(hj[h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjWubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K)hjSubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*optional function to get bridges to a list”h]”hŒ*optional function to get bridges to a list”…”�”}”(hjrh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.h”h´K*hjoubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjSubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jnh´K)hj‚ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hj4ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œfpga_region_info (C struct)”Œc.fpga_region_info”hNt”auh1j–hjrh²hh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒfpga_region_info”h]”j³)�”}”(hŒstruct fpga_region_info”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj´h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj°h²hh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´KubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÂh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj°h²hh³jÁh´KubjÜ)�”}”(hŒfpga_region_info”h]”j¦)�”}”(hj®h]”hŒfpga_region_info”…”�”}”(hjÔh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÐubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj°h²hh³jÁh´Kubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhj¬h²hh³jÁh´Kubah}”(h]”j¦ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jÁh´Khj©h²hubj )�”}”(hhh]”hÝ)�”}”(hŒ'collection of parameters an FPGA Region”h]”hŒ'collection of parameters an FPGA Region”…”�”}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´K hjóh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj©h²hh³jÁh´Kubeh}”(h]”h ]”(j½Œstruct”eh"]”h$]”h&]”j,j½j-jj.jj/‰j0‰j1‰uh1j§h²hhjrh³j¨h´Nubj3)�”}”(hXŠ**Definition**:: struct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); }; **Members** ``mgr`` fpga region manager ``compat_id`` FPGA region id for compatibility check. ``priv`` fpga region private data ``get_bridges`` optional function to get bridges to a list”h]”(hÝ)�”}”(hŒ**Definition**::”h]”(j=)�”}”(hŒ**Definition**”h]”hŒ Definition”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjubhŒ:”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´KhjubjX)�”}”(hŒ¤struct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); };”h]”hŒ¤struct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); };”…”�”}”hj3sbah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1jWh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´KhjubhÝ)�”}”(hŒ **Members**”h]”j=)�”}”(hjDh]”hŒMembers”…”�”}”(hjFh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjBubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khjubj�)�”}”(hhh]”(j†)�”}”(hŒ``mgr`` fpga region manager ”h]”(jŒ)�”}”(hŒ``mgr``”h]”j )�”}”(hjch]”hŒmgr”…”�”}”(hjeh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjaubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khj]ubj¦)�”}”(hhh]”hÝ)�”}”(hŒfpga region manager”h]”hŒfpga region manager”…”�”}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jxh´Khjyubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj]ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jxh´KhjZubj†)�”}”(hŒ6``compat_id`` FPGA region id for compatibility check. ”h]”(jŒ)�”}”(hŒ ``compat_id``”h]”j )�”}”(hjœh]”hŒ compat_id”…”�”}”(hjžh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjšubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khj–ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ'FPGA region id for compatibility check.”h]”hŒ'FPGA region id for compatibility check.”…”�”}”(hjµh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j±h´Khj²ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj–ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j±h´KhjZubj†)�”}”(hŒ"``priv`` fpga region private data ”h]”(jŒ)�”}”(hŒ``priv``”h]”j )�”}”(hjÕh]”hŒpriv”…”�”}”(hj×h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjÓubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´KhjÏubj¦)�”}”(hhh]”hÝ)�”}”(hŒfpga region private data”h]”hŒfpga region private data”…”�”}”(hjîh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jêh´Khjëubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjÏubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jêh´KhjZubj†)�”}”(hŒ:``get_bridges`` optional function to get bridges to a list”h]”(jŒ)�”}”(hŒ``get_bridges``”h]”j )�”}”(hj h]”hŒ get_bridges”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khj ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*optional function to get bridges to a list”h]”hŒ*optional function to get bridges to a list”…”�”}”(hj' h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khj$ ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j# h´KhjZubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hjubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³j¨h´NubhÝ)�”}”(hŒ**Description**”h]”j=)�”}”(hjQ h]”hŒ Description”…”�”}”(hjS h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjO ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khjrh²hubhÝ)�”}”(hŒïfpga_region_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.”h]”hŒïfpga_region_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.”…”�”}”(hjg h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.h”h´Khjrh²hubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œ(__fpga_region_register_full (C function)”Œc.__fpga_region_register_full”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒƒstruct fpga_region * __fpga_region_register_full (struct device *parent, const struct fpga_region_info *info, struct module *owner)”h]”j³)�”}”(hŒ�struct fpga_region *__fpga_region_register_full(struct device *parent, const struct fpga_region_info *info, struct module *owner)”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj‹ h²hh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K¸ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj‹ h²hh³jœ h´K¸ubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hj® h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj« ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j° Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jÄŒ ASTIdentifier”“”)�”}”j¿Œ__fpga_region_register_full”sbŒc.__fpga_region_register_full”†”asbuh1hhj‹ h²hh³jœ h´K¸ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÑ h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj‹ h²hh³jœ h´K¸ubhŒdesc_sig_punctuation”“”)�”}”(hjˆh]”hŒ*”…”�”}”(hjá h²hh³Nh´Nubah}”(h]”h ]”Œp”ah"]”h$]”h&]”uh1jß hj‹ h²hh³jœ h´K¸ubjÜ)�”}”(hŒ__fpga_region_register_full”h]”j¦)�”}”(hjÎ h]”hŒ__fpga_region_register_full”…”�”}”(hjó h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjï ubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj‹ h²hh³jœ h´K¸ubhŒdesc_parameterlist”“”)�”}”(hŒR(struct device *parent, const struct fpga_region_info *info, struct module *owner)”h]”(hŒdesc_parameter”“”)�”}”(hŒstruct device *parent”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj ubh)�”}”(hhh]”j¦)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hj0 h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj- ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j2 Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jÌ Œc.__fpga_region_register_full”†”asbuh1hhj ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjN h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj\ h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj ubj¦)�”}”(hŒparent”h]”hŒparent”…”�”}”(hji h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj ubj )�”}”(hŒ#const struct fpga_region_info *info”h]”(j¹)�”}”(hŒconst”h]”hŒconst”…”�”}”(hj‚ h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj~ ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj~ ubj¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjž h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj~ ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj« h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj~ ubh)�”}”(hhh]”j¦)�”}”(hŒfpga_region_info”h]”hŒfpga_region_info”…”�”}”(hj¼ h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj¹ ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j¾ Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jÌ Œc.__fpga_region_register_full”†”asbuh1hhj~ ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÚ h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj~ ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjè h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj~ ubj¦)�”}”(hŒinfo”h]”hŒinfo”…”�”}”(hjõ h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj~ ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj ubj )�”}”(hŒstruct module *owner”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj ubh)�”}”(hhh]”j¦)�”}”(hŒmodule”h]”hŒmodule”…”�”}”(hj, h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj) ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j. Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jÌ Œc.__fpga_region_register_full”†”asbuh1hhj ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjJ h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjX h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj ubj¦)�”}”(hŒowner”h]”hŒowner”…”�”}”(hje h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj ubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hj‹ h²hh³jœ h´K¸ubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhj‡ h²hh³jœ h´K¸ubah}”(h]”j‚ ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jœ h´K¸hj„ h²hubj )�”}”(hhh]”hÝ)�”}”(hŒ)create and register an FPGA Region device”h]”hŒ)create and register an FPGA Region device”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K¸hjŒ h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj„ h²hh³jœ h´K¸ubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-j§ j.j§ j/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hŒó**Parameters** ``struct device *parent`` device parent ``const struct fpga_region_info *info`` parameters for FPGA Region ``struct module *owner`` module containing the get_bridges function **Return** struct fpga_region or ERR_PTR()”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hj± h]”hŒ Parameters”…”�”}”(hj³ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj¯ ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K¼hj« ubj�)�”}”(hhh]”(j†)�”}”(hŒ(``struct device *parent`` device parent ”h]”(jŒ)�”}”(hŒ``struct device *parent``”h]”j )�”}”(hjÐ h]”hŒstruct device *parent”…”�”}”(hjÒ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjÎ ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K¹hjÊ ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ device parent”h]”hŒ device parent”…”�”}”(hjé h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jå h´K¹hjæ ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjÊ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jå h´K¹hjÇ ubj†)�”}”(hŒC``const struct fpga_region_info *info`` parameters for FPGA Region ”h]”(jŒ)�”}”(hŒ'``const struct fpga_region_info *info``”h]”j )�”}”(hj h]”hŒ#const struct fpga_region_info *info”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´Kºhj ubj¦)�”}”(hhh]”hÝ)�”}”(hŒparameters for FPGA Region”h]”hŒparameters for FPGA Region”…”�”}”(hj" h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j h´Kºhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j h´KºhjÇ ubj†)�”}”(hŒD``struct module *owner`` module containing the get_bridges function ”h]”(jŒ)�”}”(hŒ``struct module *owner``”h]”j )�”}”(hjB h]”hŒstruct module *owner”…”�”}”(hjD h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj@ ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K»hj< ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*module containing the get_bridges function”h]”hŒ*module containing the get_bridges function”…”�”}”(hj[ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jW h´K»hjX ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj< ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jW h´K»hjÇ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hj« ubhÝ)�”}”(hŒ **Return**”h]”j=)�”}”(hj} h]”hŒReturn”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj{ ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K½hj« ubhÝ)�”}”(hŒstruct fpga_region or ERR_PTR()”h]”hŒstruct fpga_region or ERR_PTR()”…”�”}”(hj“ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.c”h´K½hj« ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œ#__fpga_region_register (C function)”Œc.__fpga_region_register”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ�struct fpga_region * __fpga_region_register (struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region *), struct module *owner)”h]”j³)�”}”(hŒšstruct fpga_region *__fpga_region_register(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region*), struct module *owner)”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj¾ h²hh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´KúubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÐ h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj¾ h²hh³jÏ h´Kúubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hjá h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÞ ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jã Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿Œ__fpga_region_register”sbŒc.__fpga_region_register”†”asbuh1hhj¾ h²hh³jÏ h´KúubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj¾ h²hh³jÏ h´Kúubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj¾ h²hh³jÏ h´KúubjÜ)�”}”(hŒ__fpga_region_register”h]”j¦)�”}”(hjÿ h]”hŒ__fpga_region_register”…”�”}”(hj! h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj¾ h²hh³jÏ h´Kúubj )�”}”(hŒp(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region*), struct module *owner)”h]”(j )�”}”(hŒstruct device *parent”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj< h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj8 ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjI h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj8 ubh)�”}”(hhh]”j¦)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hjZ h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjW ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j\ Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jý Œc.__fpga_region_register”†”asbuh1hhj8 ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjx h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj8 ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj† h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj8 ubj¦)�”}”(hŒparent”h]”hŒparent”…”�”}”(hj“ h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj8 ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj4 ubj )�”}”(hŒstruct fpga_manager *mgr”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj¬ h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj¨ ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj¹ h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj¨ ubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjÊ h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÇ ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jÌ Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jý Œc.__fpga_region_register”†”asbuh1hhj¨ ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjè h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj¨ ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjö h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj¨ ubj¦)�”}”(hŒmgr”h]”hŒmgr”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj¨ ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj4 ubj )�”}”(hŒ'int (*get_bridges)(struct fpga_region*)”h]”(hŒdesc_sig_keyword_type”“”)�”}”(hŒint”h]”hŒint”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”Œkt”ah"]”h$]”h&]”uh1jhjubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj-h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjubjà )�”}”(hŒ(”h]”hŒ(”…”�”}”(hj;h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjIh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubj¦)�”}”(hŒ get_bridges”h]”hŒ get_bridges”…”�”}”(hjVh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjubjà )�”}”(hŒ)”h]”hŒ)”…”�”}”(hjdh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubjà )�”}”(hj=h]”hŒ(”…”�”}”(hjrh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubj¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjŒh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjšubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŸŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jý Œc.__fpga_region_register”†”asbuh1hhjubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj»h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubjà )�”}”(hjfh]”hŒ)”…”�”}”(hjÈh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj4 ubj )�”}”(hŒstruct module *owner”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjàh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjÜubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjíh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjÜubh)�”}”(hhh]”j¦)�”}”(hŒmodule”h]”hŒmodule”…”�”}”(hjþh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjûubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jý Œc.__fpga_region_register”†”asbuh1hhjÜubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjÜubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj*h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjÜubj¦)�”}”(hŒowner”h]”hŒowner”…”�”}”(hj7h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÜubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj4 ubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hj¾ h²hh³jÏ h´Kúubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhjº h²hh³jÏ h´Kúubah}”(h]”jµ ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jÏ h´Kúhj· h²hubj )�”}”(hhh]”hÝ)�”}”(hŒ)create and register an FPGA Region device”h]”hŒ)create and register an FPGA Region device”…”�”}”(hjah²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Kúhj^h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj· h²hh³jÏ h´Kúubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jyj.jyj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hX!**Parameters** ``struct device *parent`` device parent ``struct fpga_manager *mgr`` manager that programs this region ``int (*get_bridges)(struct fpga_region *)`` optional function to get bridges to a list ``struct module *owner`` module containing the get_bridges function **Description** This simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters. **Return** struct fpga_region or ERR_PTR()”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hjƒh]”hŒ Parameters”…”�”}”(hj…h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj�ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Kþhj}ubj�)�”}”(hhh]”(j†)�”}”(hŒ(``struct device *parent`` device parent ”h]”(jŒ)�”}”(hŒ``struct device *parent``”h]”j )�”}”(hj¢h]”hŒstruct device *parent”…”�”}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Kûhjœubj¦)�”}”(hhh]”hÝ)�”}”(hŒ device parent”h]”hŒ device parent”…”�”}”(hj»h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j·h´Kûhj¸ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjœubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j·h´Kûhj™ubj†)�”}”(hŒ?``struct fpga_manager *mgr`` manager that programs this region ”h]”(jŒ)�”}”(hŒ``struct fpga_manager *mgr``”h]”j )�”}”(hjÛh]”hŒstruct fpga_manager *mgr”…”�”}”(hjÝh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjÙubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´KühjÕubj¦)�”}”(hhh]”hÝ)�”}”(hŒ!manager that programs this region”h]”hŒ!manager that programs this region”…”�”}”(hjôh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jðh´Kühjñubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjÕubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jðh´Kühj™ubj†)�”}”(hŒX``int (*get_bridges)(struct fpga_region *)`` optional function to get bridges to a list ”h]”(jŒ)�”}”(hŒ,``int (*get_bridges)(struct fpga_region *)``”h]”j )�”}”(hjh]”hŒ(int (*get_bridges)(struct fpga_region *)”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Kýhjubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*optional function to get bridges to a list”h]”hŒ*optional function to get bridges to a list”…”�”}”(hj-h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j)h´Kýhj*ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j)h´Kýhj™ubj†)�”}”(hŒD``struct module *owner`` module containing the get_bridges function ”h]”(jŒ)�”}”(hŒ``struct module *owner``”h]”j )�”}”(hjMh]”hŒstruct module *owner”…”�”}”(hjOh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjKubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´KþhjGubj¦)�”}”(hhh]”hÝ)�”}”(hŒ*module containing the get_bridges function”h]”hŒ*module containing the get_bridges function”…”�”}”(hjfh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jbh´Kþhjcubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjGubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jbh´Kþhj™ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hj}ubhÝ)�”}”(hŒ**Description**”h]”j=)�”}”(hjˆh]”hŒ Description”…”�”}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj†ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Mhj}ubhÝ)�”}”(hŒÄThis simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters.”h]”hŒÄThis simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters.”…”�”}”(hjžh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Kÿhj}ubhÝ)�”}”(hŒ **Return**”h]”j=)�”}”(hj¯h]”hŒReturn”…”�”}”(hj±h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj­ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Mhj}ubhÝ)�”}”(hŒstruct fpga_region or ERR_PTR()”h]”hŒstruct fpga_region or ERR_PTR()”…”�”}”(hjÅh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.c”h´Mhj}ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œ#fpga_region_unregister (C function)”Œc.fpga_region_unregister”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ8void fpga_region_unregister (struct fpga_region *region)”h]”j³)�”}”(hŒ7void fpga_region_unregister(struct fpga_region *region)”h]”(j)�”}”(hŒvoid”h]”hŒvoid”…”�”}”(hjôh²hh³Nh´Nubah}”(h]”h ]”j)ah"]”h$]”h&]”uh1jhjðh²hh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´MubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjðh²hh³jh´MubjÜ)�”}”(hŒfpga_region_unregister”h]”j¦)�”}”(hŒfpga_region_unregister”h]”hŒfpga_region_unregister”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhjðh²hh³jh´Mubj )�”}”(hŒ(struct fpga_region *region)”h]”j )�”}”(hŒstruct fpga_region *region”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj1h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj-ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj>h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj-ubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_region”h]”hŒ fpga_region”…”�”}”(hjOh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjLubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jQŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿jsbŒc.fpga_region_unregister”†”asbuh1hhj-ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjoh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj-ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj}h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj-ubj¦)�”}”(hŒregion”h]”hŒregion”…”�”}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj-ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj)ubah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hjðh²hh³jh´Mubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhjìh²hh³jh´Mubah}”(h]”jçah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jh´Mhjéh²hubj )�”}”(hhh]”hÝ)�”}”(hŒunregister an FPGA region”h]”hŒunregister an FPGA region”…”�”}”(hj´h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´Mhj±h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjéh²hh³jh´Mubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jÌj.jÌj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hŒœ**Parameters** ``struct fpga_region *region`` FPGA region **Description** This function is intended for use in an FPGA region driver's remove function.”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hjÖh]”hŒ Parameters”…”�”}”(hjØh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjÔubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´MhjÐubj�)�”}”(hhh]”j†)�”}”(hŒ+``struct fpga_region *region`` FPGA region ”h]”(jŒ)�”}”(hŒ``struct fpga_region *region``”h]”j )�”}”(hjõh]”hŒstruct fpga_region *region”…”�”}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjóubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´Mhjïubj¦)�”}”(hhh]”hÝ)�”}”(hŒ FPGA region”h]”hŒ FPGA region”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j h´Mhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjïubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j h´Mhjìubah}”(h]”h ]”h"]”h$]”h&]”uh1j€hjÐubhÝ)�”}”(hŒ**Description**”h]”j=)�”}”(hj0h]”hŒ Description”…”�”}”(hj2h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj.ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´MhjÐubhÝ)�”}”(hŒMThis function is intended for use in an FPGA region driver's remove function.”h]”hŒOThis function is intended for use in an FPGA region driver’s remove function.”…”�”}”(hjFh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.c”h´MhjÐubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œfpga_mgr_get (C function)”Œc.fpga_mgr_get”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ7struct fpga_manager * fpga_mgr_get (struct device *dev)”h]”j³)�”}”(hŒ5struct fpga_manager *fpga_mgr_get(struct device *dev)”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjuh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjqh²hh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M­ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjƒh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjqh²hh³j‚h´M­ubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hj”h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj‘ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j–Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿Œ fpga_mgr_get”sbŒc.fpga_mgr_get”†”asbuh1hhjqh²hh³j‚h´M­ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjµh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjqh²hh³j‚h´M­ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjqh²hh³j‚h´M­ubjÜ)�”}”(hŒ fpga_mgr_get”h]”j¦)�”}”(hj²h]”hŒ fpga_mgr_get”…”�”}”(hjÔh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÐubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhjqh²hh³j‚h´M­ubj )�”}”(hŒ(struct device *dev)”h]”j )�”}”(hŒstruct device *dev”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjïh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjëubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjüh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjëubh)�”}”(hhh]”j¦)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”j°Œc.fpga_mgr_get”†”asbuh1hhjëubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj+h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjëubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj9h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjëubj¦)�”}”(hŒdev”h]”hŒdev”…”�”}”(hjFh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjëubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hjçubah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hjqh²hh³j‚h´M­ubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhjmh²hh³j‚h´M­ubah}”(h]”jhah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³j‚h´M­hjjh²hubj )�”}”(hhh]”hÝ)�”}”(hŒ/Given a device, get a reference to an fpga mgr.”h]”hŒ/Given a device, get a reference to an fpga mgr.”…”�”}”(hjph²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M­hjmh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjjh²hh³j‚h´M­ubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jˆj.jˆj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hŒ¦**Parameters** ``struct device *dev`` parent device that fpga mgr was registered with **Return** fpga manager struct or IS_ERR() condition containing error code.”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hj’h]”hŒ Parameters”…”�”}”(hj”h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj�ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M±hjŒubj�)�”}”(hhh]”j†)�”}”(hŒG``struct device *dev`` parent device that fpga mgr was registered with ”h]”(jŒ)�”}”(hŒ``struct device *dev``”h]”j )�”}”(hj±h]”hŒstruct device *dev”…”�”}”(hj³h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj¯ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M®hj«ubj¦)�”}”(hhh]”hÝ)�”}”(hŒ/parent device that fpga mgr was registered with”h]”hŒ/parent device that fpga mgr was registered with”…”�”}”(hjÊh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÆh´M®hjÇubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj«ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jÆh´M®hj¨ubah}”(h]”h ]”h"]”h$]”h&]”uh1j€hjŒubhÝ)�”}”(hŒ **Return**”h]”j=)�”}”(hjìh]”hŒReturn”…”�”}”(hjîh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjêubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M°hjŒubhÝ)�”}”(hŒ@fpga manager struct or IS_ERR() condition containing error code.”h]”hŒ@fpga manager struct or IS_ERR() condition containing error code.”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.c”h´M°hjŒubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œof_fpga_mgr_get (C function)”Œc.of_fpga_mgr_get”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ@struct fpga_manager * of_fpga_mgr_get (struct device_node *node)”h]”j³)�”}”(hŒ>struct fpga_manager *of_fpga_mgr_get(struct device_node *node)”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj1h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj-h²hh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÄubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj?h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj-h²hh³j>h´MÄubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjPh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjMubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jRŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿Œof_fpga_mgr_get”sbŒc.of_fpga_mgr_get”†”asbuh1hhj-h²hh³j>h´MÄubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjqh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj-h²hh³j>h´MÄubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj-h²hh³j>h´MÄubjÜ)�”}”(hŒof_fpga_mgr_get”h]”j¦)�”}”(hjnh]”hŒof_fpga_mgr_get”…”�”}”(hj�h²hh³•·}Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjŒubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj-h²hh³j>h´MÄubj )�”}”(hŒ(struct device_node *node)”h]”j )�”}”(hŒstruct device_node *node”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj«h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj§ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj§ubh)�”}”(hhh]”j¦)�”}”(hŒ device_node”h]”hŒ device_node”…”�”}”(hjÉh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjÆubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jËŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jlŒc.of_fpga_mgr_get”†”asbuh1hhj§ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjçh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj§ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjõh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj§ubj¦)�”}”(hŒnode”h]”hŒnode”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj§ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj£ubah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hj-h²hh³j>h´MÄubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhj)h²hh³j>h´MÄubah}”(h]”j$ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³j>h´MÄhj&h²hubj )�”}”(hhh]”hÝ)�”}”(hŒ4Given a device node, get a reference to an fpga mgr.”h]”hŒ4Given a device node, get a reference to an fpga mgr.”…”�”}”(hj,h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÄhj)h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj&h²hh³j>h´MÄubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jDj.jDj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hŒˆ**Parameters** ``struct device_node *node`` device node **Return** fpga manager struct or IS_ERR() condition containing error code.”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hjNh]”hŒ Parameters”…”�”}”(hjPh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjLubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÈhjHubj�)�”}”(hhh]”j†)�”}”(hŒ)``struct device_node *node`` device node ”h]”(jŒ)�”}”(hŒ``struct device_node *node``”h]”j )�”}”(hjmh]”hŒstruct device_node *node”…”�”}”(hjoh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjkubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÆhjgubj¦)�”}”(hhh]”hÝ)�”}”(hŒ device node”h]”hŒ device node”…”�”}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j‚h´MÆhjƒubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjgubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j‚h´MÆhjdubah}”(h]”h ]”h"]”h$]”h&]”uh1j€hjHubhÝ)�”}”(hŒ **Return**”h]”j=)�”}”(hj¨h]”hŒReturn”…”�”}”(hjªh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hj¦ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÈhjHubhÝ)�”}”(hŒ@fpga manager struct or IS_ERR() condition containing error code.”h]”hŒ@fpga manager struct or IS_ERR() condition containing error code.”…”�”}”(hj¾h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.c”h´MÈhjHubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œfpga_mgr_put (C function)”Œc.fpga_mgr_put”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ,void fpga_mgr_put (struct fpga_manager *mgr)”h]”j³)�”}”(hŒ+void fpga_mgr_put(struct fpga_manager *mgr)”h]”(j)�”}”(hŒvoid”h]”hŒvoid”…”�”}”(hjíh²hh³Nh´Nubah}”(h]”h ]”j)ah"]”h$]”h&]”uh1jhjéh²hh³Œd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.c”h´MÜubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjüh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjéh²hh³jûh´MÜubjÜ)�”}”(hŒ fpga_mgr_put”h]”j¦)�”}”(hŒ fpga_mgr_put”h]”hŒ fpga_mgr_put”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhjéh²hh³jûh´MÜubj )�”}”(hŒ(struct fpga_manager *mgr)”h]”j )�”}”(hŒstruct fpga_manager *mgr”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj*h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj&ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj7h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj&ubh)�”}”(hhh]”j¦)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjHh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjEubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jJŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿jsbŒc.fpga_mgr_put”†”asbuh1hhj&ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjhh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj&ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjvh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj&ubj¦)�”}”(hŒmgr”h]”hŒmgr”…”�”}”(hjƒh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj&ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj"ubah}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hjéh²hh³jûh´MÜubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhjåh²hh³jûh´MÜubah}”(h]”jàah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jûh´MÜhjâh²hubj )�”}”(hhh]”hÝ)�”}”(hŒ&release a reference to an fpga manager”h]”hŒ&release a reference to an fpga manager”…”�”}”(hj­h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.c”h´MÜhjªh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjâh²hh³jûh´MÜubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jÅj.jÅj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hŒE**Parameters** ``struct fpga_manager *mgr`` fpga manager structure”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hjÏh]”hŒ Parameters”…”�”}”(hjÑh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjÍubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.c”h´MàhjÉubj�)�”}”(hhh]”j†)�”}”(hŒ3``struct fpga_manager *mgr`` fpga manager structure”h]”(jŒ)�”}”(hŒ``struct fpga_manager *mgr``”h]”j )�”}”(hjîh]”hŒstruct fpga_manager *mgr”…”�”}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjìubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.c”h´Mâhjèubj¦)�”}”(hhh]”hÝ)�”}”(hŒfpga manager structure”h]”hŒfpga manager structure”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.c”h´MÝhjubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjèubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jh´Mâhjåubah}”(h]”h ]”h"]”h$]”h&]”uh1j€hjÉubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œ$fpga_bridge_get_to_list (C function)”Œc.fpga_bridge_get_to_list”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒmint fpga_bridge_get_to_list (struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)”h]”j³)�”}”(hŒlint fpga_bridge_get_to_list(struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)”h]”(j)�”}”(hŒint”h]”hŒint”…”�”}”(hjHh²hh³Nh´Nubah}”(h]”h ]”j)ah"]”h$]”h&]”uh1jhjDh²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´MubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjWh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjDh²hh³jVh´MubjÜ)�”}”(hŒfpga_bridge_get_to_list”h]”j¦)�”}”(hŒfpga_bridge_get_to_list”h]”hŒfpga_bridge_get_to_list”…”�”}”(hjih²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjeubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhjDh²hh³jVh´Mubj )�”}”(hŒQ(struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)”h]”(j )�”}”(hŒstruct device *dev”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj…h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj�ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj’h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj�ubh)�”}”(hhh]”j¦)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hj£h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j¥Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿jksbŒc.fpga_bridge_get_to_list”†”asbuh1hhj�ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj�ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjÑh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj�ubj¦)�”}”(hŒdev”h]”hŒdev”…”�”}”(hjÞh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj�ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj}ubj )�”}”(hŒstruct fpga_image_info *info”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjóubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjóubh)�”}”(hhh]”j¦)�”}”(hŒfpga_image_info”h]”hŒfpga_image_info”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”j¿Œc.fpga_bridge_get_to_list”†”asbuh1hhjóubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj3h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjóubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjAh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjóubj¦)�”}”(hŒinfo”h]”hŒinfo”…”�”}”(hjNh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjóubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj}ubj )�”}”(hŒstruct list_head *bridge_list”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjgh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjcubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjth²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjcubh)�”}”(hhh]”j¦)�”}”(hŒ list_head”h]”hŒ list_head”…”�”}”(hj…h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj‚ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j‡Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”j¿Œc.fpga_bridge_get_to_list”†”asbuh1hhjcubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj£h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjcubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj±h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjcubj¦)�”}”(hŒ bridge_list”h]”hŒ bridge_list”…”�”}”(hj¾h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjcubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hj}ubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hjDh²hh³jVh´Mubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhj@h²hh³jVh´Mubah}”(h]”j;ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jVh´Mhj=h²hubj )�”}”(hhh]”hÝ)�”}”(hŒ,given device, get a bridge, add it to a list”h]”hŒ,given device, get a bridge, add it to a list”…”�”}”(hjèh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´Mhjåh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj=h²hh³jVh´Mubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-jj.jj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hXQ**Parameters** ``struct device *dev`` FPGA bridge device ``struct fpga_image_info *info`` fpga image specific information ``struct list_head *bridge_list`` list of FPGA bridges **Description** Get an exclusive reference to the bridge and it to the list. **Return** 0 for success, error code from fpga_bridge_get() otherwise.”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hj h]”hŒ Parameters”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´Mhjubj�)�”}”(hhh]”(j†)�”}”(hŒ*``struct device *dev`` FPGA bridge device ”h]”(jŒ)�”}”(hŒ``struct device *dev``”h]”j )�”}”(hj)h]”hŒstruct device *dev”…”�”}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj'ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´Mhj#ubj¦)�”}”(hhh]”hÝ)�”}”(hŒFPGA bridge device”h]”hŒFPGA bridge device”…”�”}”(hjBh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j>h´Mhj?ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj#ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j>h´Mhj ubj†)�”}”(hŒA``struct fpga_image_info *info`` fpga image specific information ”h]”(jŒ)�”}”(hŒ ``struct fpga_image_info *info``”h]”j )�”}”(hjbh]”hŒstruct fpga_image_info *info”…”�”}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj`ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´Mhj\ubj¦)�”}”(hhh]”hÝ)�”}”(hŒfpga image specific information”h]”hŒfpga image specific information”…”�”}”(hj{h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jwh´Mhjxubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj\ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jwh´Mhj ubj†)�”}”(hŒ7``struct list_head *bridge_list`` list of FPGA bridges ”h]”(jŒ)�”}”(hŒ!``struct list_head *bridge_list``”h]”j )�”}”(hj›h]”hŒstruct list_head *bridge_list”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj™ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´Mhj•ubj¦)�”}”(hhh]”hÝ)�”}”(hŒlist of FPGA bridges”h]”hŒlist of FPGA bridges”…”�”}”(hj´h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j°h´Mhj±ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj•ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j°h´Mhj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hjubhÝ)�”}”(hŒ**Description**”h]”j=)�”}”(hjÖh]”hŒ Description”…”�”}”(hjØh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjÔubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.c”h´M hjubhÝ)�”}”(hŒh²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´KåubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjQh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj>h²hh³jPh´KåubjÜ)�”}”(hŒof_fpga_bridge_get_to_list”h]”j¦)�”}”(hŒof_fpga_bridge_get_to_list”h]”hŒof_fpga_bridge_get_to_list”…”�”}”(hjch²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj_ubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj>h²hh³jPh´Kåubj )�”}”(hŒU(struct device_node *np, struct fpga_image_info *info, struct list_head *bridge_list)”h]”(j )�”}”(hŒstruct device_node *np”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj{ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjŒh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj{ubh)�”}”(hhh]”j¦)�”}”(hŒ device_node”h]”hŒ device_node”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjšubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŸŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿jesbŒc.of_fpga_bridge_get_to_list”†”asbuh1hhj{ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj½h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj{ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjËh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj{ubj¦)�”}”(hŒnp”h]”hŒnp”…”�”}”(hjØh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj{ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hjwubj )�”}”(hŒstruct fpga_image_info *info”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjñh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjíubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjþh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjíubh)�”}”(hhh]”j¦)�”}”(hŒfpga_image_info”h]”hŒfpga_image_info”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”jŒmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”j¹Œc.of_fpga_bridge_get_to_list”†”asbuh1hhjíubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj-h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjíubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj;h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjíubj¦)�”}”(hŒinfo”h]”hŒinfo”…”�”}”(hjHh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjíubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hjwubj )�”}”(hŒstruct list_head *bridge_list”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjah²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hj]ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjnh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj]ubh)�”}”(hhh]”j¦)�”}”(hŒ list_head”h]”hŒ list_head”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj|ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j�Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”j¹Œc.of_fpga_bridge_get_to_list”†”asbuh1hhj]ubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj]ubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hj«h²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hj]ubj¦)�”}”(hŒ bridge_list”h]”hŒ bridge_list”…”�”}”(hj¸h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj]ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjöj÷uh1j hjwubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷uh1j hj>h²hh³jPh´Kåubeh}”(h]”h ]”h"]”h$]”h&]”jöj÷jþˆuh1j²jÿjhj:h²hh³jPh´Kåubah}”(h]”j5ah ]”(jîjeh"]”h$]”h&]”jˆj )j huh1j¬h³jPh´Kåhj7h²hubj )�”}”(hhh]”hÝ)�”}”(hŒget a bridge, add it to a list”h]”hŒget a bridge, add it to a list”…”�”}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´Kåhjßh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj7h²hh³jPh´Kåubeh}”(h]”h ]”(j½Œfunction”eh"]”h$]”h&]”j,j½j-júj.júj/‰j0‰j1‰uh1j§h²hhjrh³Nh´Nubj3)�”}”(hXd**Parameters** ``struct device_node *np`` node pointer of an FPGA bridge ``struct fpga_image_info *info`` fpga image specific information ``struct list_head *bridge_list`` list of FPGA bridges **Description** Get an exclusive reference to the bridge and it to the list. **Return** 0 for success, error code from of_fpga_bridge_get() otherwise.”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j=)�”}”(hjh]”hŒ Parameters”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´Kéhjþubj�)�”}”(hhh]”(j†)�”}”(hŒ:``struct device_node *np`` node pointer of an FPGA bridge ”h]”(jŒ)�”}”(hŒ``struct device_node *np``”h]”j )�”}”(hj#h]”hŒstruct device_node *np”…”�”}”(hj%h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj!ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´Kçhjubj¦)�”}”(hhh]”hÝ)�”}”(hŒnode pointer of an FPGA bridge”h]”hŒnode pointer of an FPGA bridge”…”�”}”(hj<h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j8h´Kçhj9ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³j8h´Kçhjubj†)�”}”(hŒA``struct fpga_image_info *info`` fpga image specific information ”h]”(jŒ)�”}”(hŒ ``struct fpga_image_info *info``”h]”j )�”}”(hj\h]”hŒstruct fpga_image_info *info”…”�”}”(hj^h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hjZubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´KèhjVubj¦)�”}”(hhh]”hÝ)�”}”(hŒfpga image specific information”h]”hŒfpga image specific information”…”�”}”(hjuh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jqh´Kèhjrubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hjVubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jqh´Kèhjubj†)�”}”(hŒ7``struct list_head *bridge_list`` list of FPGA bridges ”h]”(jŒ)�”}”(hŒ!``struct list_head *bridge_list``”h]”j )�”}”(hj•h]”hŒstruct list_head *bridge_list”…”�”}”(hj—h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj“ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹h³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´Kéhj�ubj¦)�”}”(hhh]”hÝ)�”}”(hŒlist of FPGA bridges”h]”hŒlist of FPGA bridges”…”�”}”(hj®h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jªh´Kéhj«ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¥hj�ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j…h³jªh´Kéhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1j€hjþubhÝ)�”}”(hŒ**Description**”h]”j=)�”}”(hjÐh]”hŒ Description”…”�”}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j<hjÎubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´KëhjþubhÝ)�”}”(hŒ0 for success, error code from of_fpga_bridge_get() otherwise.”h]”hŒ>0 for success, error code from of_fpga_bridge_get() otherwise.”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.c”h´Kíhjþubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1j2hjrh²hh³Nh´Nubj—)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j£Œfpga_bridges_put (C function)”Œc.fpga_bridges_put”hNt”auh1j–hjrh²hh³Nh´Nubj¨)�”}”(hhh]”(j­)�”}”(hŒ5void fpga_bridges_put (struct list_head *bridge_list)”h]”j³)�”}”(hŒ4void fpga_bridges_put(struct list_head *bridge_list)”h]”(j)�”}”(hŒvoid”h]”hŒvoid”…”�”}”(hj<h²hh³Nh´Nubah}”(h]”h ]”j)ah"]”h$]”h&]”uh1jhj8h²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.c”h´KÎubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjKh²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhj8h²hh³jJh´KÎubjÜ)�”}”(hŒfpga_bridges_put”h]”j¦)�”}”(hŒfpga_bridges_put”h]”hŒfpga_bridges_put”…”�”}”(hj]h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjYubah}”(h]”h ]”(jñjòeh"]”h$]”h&]”jöj÷uh1jÛhj8h²hh³jJh´KÎubj )�”}”(hŒ(struct list_head *bridge_list)”h]”j )�”}”(hŒstruct list_head *bridge_list”h]”(j¹)�”}”(hj¼h]”hŒstruct”…”�”}”(hjyh²hh³Nh´Nubah}”(h]”h ]”jÅah"]”h$]”h&]”uh1j¸hjuubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj†h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjuubh)�”}”(hhh]”j¦)�”}”(hŒ list_head”h]”hŒ list_head”…”�”}”(hj—h²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hj”ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”j½Œreftype”j¿Œ reftarget”j™Œmodname”NŒ classname”NjÃjÆ)�”}”jÉ]”jË )�”}”j¿j_sbŒc.fpga_bridges_put”†”asbuh1hhjuubjË)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj·h²hh³Nh´Nubah}”(h]”h ]”j×ah"]”h$]”h&]”uh1jÊhjuubjà )�”}”(hjˆh]”hŒ*”…”�”}”(hjÅh²hh³Nh´Nubah}”(h]”h ]”jë ah"]”h$]”h&]”uh1jß hjuubj¦)�”}”(hŒ bridge_list”h]”hŒ bridge_list”…”�”}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”j²ah"]”h$]”h&]”uh1j¥hjuubeh}”(h]”h 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