sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget//translations/zh_CN/driver-api/fpga/fpga-regionmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/zh_TW/driver-api/fpga/fpga-regionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/it_IT/driver-api/fpga/fpga-regionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ja_JP/driver-api/fpga/fpga-regionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ko_KR/driver-api/fpga/fpga-regionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/sp_SP/driver-api/fpga/fpga-regionmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h FPGA Regionh]h FPGA Region}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhI/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region.rsthKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThis document is meant to be a brief overview of the FPGA region API usage. A more conceptual look at regions can be found in the Device Tree binding document [#f1]_.h](hThis document is meant to be a brief overview of the FPGA region API usage. A more conceptual look at regions can be found in the Device Tree binding document }(hhhhhNhNubhfootnote_reference)}(h[#f1]_h]h1}(hhhhhNhNubah}(h]id1ah ]h"]h$]h&]autoKrefidf1docnamedriver-api/fpga/fpga-regionuh1hhhʌresolvedKubh.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hFor the purposes of this API document, let's just say that a region associates an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an FPGA or the whole FPGA. The API provides a way to register a region and to program a region.h]hFor the purposes of this API document, let’s just say that a region associates an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an FPGA or the whole FPGA. The API provides a way to register a region and to program a region.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hX\Currently the only layer above fpga-region.c in the kernel is the Device Tree support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions to program the FPGA and then DT to handle enumeration. The common region code is intended to be used by other schemes that have other ways of accomplishing enumeration after programming.h](hvCurrently the only layer above fpga-region.c in the kernel is the Device Tree support (of-fpga-region.c) described in }(hjhhhNhNubh)}(h[#f1]_h]h1}(hj hhhNhNubah}(h]id2ah ]h"]h$]h&]hKhhhhuh1hhjhKubh. The DT support layer uses regions to program the FPGA and then DT to handle enumeration. The common region code is intended to be used by other schemes that have other ways of accomplishing enumeration after programming.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h:An fpga-region can be set up to know the following things:h]h:An fpga-region can be set up to know the following things:}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hx* which FPGA manager to use to do the programming * which bridges to disable before programming and enable afterwards. h]h bullet_list)}(hhh](h list_item)}(h0which FPGA manager to use to do the programming h]h)}(h/which FPGA manager to use to do the programmingh]h/which FPGA manager to use to do the programming}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj=ubah}(h]h ]h"]h$]h&]uh1j;hj8ubj<)}(hCwhich bridges to disable before programming and enable afterwards. h]h)}(hBwhich bridges to disable before programming and enable afterwards.h]hBwhich bridges to disable before programming and enable afterwards.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjUubah}(h]h ]h"]h$]h&]uh1j;hj8ubeh}(h]h ]h"]h$]h&]bullet*uh1j6hhhKhj2ubah}(h]h ]h"]h$]h&]uh1j0hhhKhhhhubh)}(hcAdditional info needed to program the FPGA image is passed in the struct fpga_image_info including:h]hcAdditional info needed to program the FPGA image is passed in the struct fpga_image_info including:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubj1)}(h* pointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file * flags indicating specifics such as whether the image is for partial reconfiguration. h]j7)}(hhh](j<)}(hkpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file h]h)}(hjpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware fileh]hjpointers to the image as either a scatter-gather buffer, a contiguous buffer, or the name of firmware file}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j;hjubj<)}(hUflags indicating specifics such as whether the image is for partial reconfiguration. h]h)}(hTflags indicating specifics such as whether the image is for partial reconfiguration.h]hTflags indicating specifics such as whether the image is for partial reconfiguration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j;hjubeh}(h]h ]h"]h$]h&]jsjtuh1j6hhhKhjubah}(h]h ]h"]h$]h&]uh1j0hhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hHow to add a new FPGA regionh]hHow to add a new FPGA region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK&ubh)}(h@An example of usage can be seen in the probe function of [#f2]_.h](h9An example of usage can be seen in the probe function of }(hjhhhNhNubh)}(h[#f2]_h]h2}(hjhhhNhNubah}(h]id3ah ]h"]h$]h&]hKhf2hhuh1hhjhKubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK(hjhhubhfootnote)}(h+../devicetree/bindings/fpga/fpga-region.txth](hlabel)}(hhh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j hj hhhNhNubh)}(hj h]h+../devicetree/bindings/fpga/fpga-region.txt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj ubeh}(h]hah ]h"]f1ah$]h&](hjehKhhuh1jhhhK*hjhhubj)}(h$../../drivers/fpga/of-fpga-region.c h](j)}(hhh]h2}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj0hhhNhNubh)}(h#../../drivers/fpga/of-fpga-region.ch]h#../../drivers/fpga/of-fpga-region.c}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hj0ubeh}(h]jah ]h"]f2ah$]h&]jahKhhuh1jhhhK+hjhhubeh}(h]how-to-add-a-new-fpga-regionah ]h"]how to add a new fpga regionah$]h&]uh1hhhhhhhhK&ubh)}(hhh](h)}(hAPI to add a new FPGA regionh]hAPI to add a new FPGA region}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhK.ubj7)}(hhh](j<)}(h+struct fpga_region - The FPGA region structh]h)}(hjth]h+struct fpga_region - The FPGA region struct}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjrubah}(h]h ]h"]h$]h&]uh1j;hjohhhhhNubj<)}(hOstruct fpga_region_info - Parameter structure for __fpga_region_register_full()h]h)}(hjh]hOstruct fpga_region_info - Parameter structure for __fpga_region_register_full()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1j;hjohhhhhNubj<)}(h__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of optionsh]h)}(h__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of optionsh]h__fpga_region_register_full() - Create and register an FPGA region using the fpga_region_info structure to provide the full flexibility of options}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1j;hjohhhhhNubj<)}(hW__fpga_region_register() - Create and register an FPGA region using standard argumentsh]h)}(hW__fpga_region_register() - Create and register an FPGA region using standard argumentsh]hW__fpga_region_register() - Create and register an FPGA region using standard arguments}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1j;hjohhhhhNubj<)}(h6fpga_region_unregister() - Unregister an FPGA region h]h)}(h5fpga_region_unregister() - Unregister an FPGA regionh]h5fpga_region_unregister() - Unregister an FPGA region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1j;hjohhhhhNubeh}(h]h ]h"]h$]h&]jsjtuh1j6hhhK0hj^hhubh)}(hHelper macros ``fpga_region_register()`` and ``fpga_region_register_full()`` automatically set the module that registers the FPGA region as the owner.h](hHelper macros }(hjhhhNhNubhliteral)}(h``fpga_region_register()``h]hfpga_region_register()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h``fpga_region_register_full()``h]hfpga_region_register_full()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhJ automatically set the module that registers the FPGA region as the owner.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK8hj^hhubh)}(hThe FPGA region's probe function will need to get a reference to the FPGA Manager it will be using to do the programming. This usually would happen during the region's probe function.h]hThe FPGA region’s probe function will need to get a reference to the FPGA Manager it will be using to do the programming. This usually would happen during the region’s probe function.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hj^hhubj7)}(hhh](j<)}(hDfpga_mgr_get() - Get a reference to an FPGA manager, raise ref counth]h)}(hj5h]hDfpga_mgr_get() - Get a reference to an FPGA manager, raise ref count}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hj3ubah}(h]h ]h"]h$]h&]uh1j;hj0hhhhhNubj<)}(h^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.h]h)}(h^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.h]h^of_fpga_mgr_get() - Get a reference to an FPGA manager, raise ref count, given a device node.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjJubah}(h]h ]h"]h$]h&]uh1j;hj0hhhhhNubj<)}(h%fpga_mgr_put() - Put an FPGA manager h]h)}(h$fpga_mgr_put() - Put an FPGA managerh]h$fpga_mgr_put() - Put an FPGA manager}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjbubah}(h]h ]h"]h$]h&]uh1j;hj0hhhhhNubeh}(h]h ]h"]h$]h&]jsjtuh1j6hhhK?hj^hhubh)}(hXThe FPGA region will need to specify which bridges to control while programming the FPGA. The region driver can build a list of bridges during probe time (:c:expr:`fpga_region->bridge_list`) or it can have a function that creates the list of bridges to program just before programming (:c:expr:`fpga_region->get_bridges`). The FPGA bridge framework supplies the following APIs to handle building or tearing down that list.h](hThe FPGA region will need to specify which bridges to control while programming the FPGA. The region driver can build a list of bridges during probe time (}(hjhhhNhNubh desc_inline)}(hfpga_region->bridge_listh](h)}(hhh]h desc_sig_name)}(h fpga_regionh]h fpga_region}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]sbuh1hhjubhdesc_sig_operator)}(h->h]h->}(hjhhhNhNubah}(h]h ]oah"]h$]h&]uh1jhjubj)}(h bridge_listh]h bridge_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ](c-exprsig sig-inlinejeh"]h$]h&]uh1jhjubha) or it can have a function that creates the list of bridges to program just before programming (}(hjhhhNhNubj)}(hfpga_region->get_bridgesh](h)}(hhh]j)}(h fpga_regionh]h fpga_region}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]sbuh1hhjubj)}(hjh]h->}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h get_bridgesh]h get_bridges}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ](jjjjeh"]h$]h&]uh1jhjubhg). The FPGA bridge framework supplies the following APIs to handle building or tearing down that list.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKDhj^hhubj7)}(hhh](j<)}(hIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a listh]h)}(hIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a listh]hIfpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhj4ubah}(h]h ]h"]h$]h&]uh1j;hj1hhhhhNubj<)}(haof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device nodeh]h)}(haof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device nodeh]haof_fpga_bridge_get_to_list() - Get a ref of an FPGA bridge, add it to a list, given a device node}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjLubah}(h]h ]h"]h$]h&]uh1j;hj1hhhhhNubj<)}(h7fpga_bridges_put() - Given a list of bridges, put them h]h)}(h6fpga_bridges_put() - Given a list of bridges, put themh]h6fpga_bridges_put() - Given a list of bridges, put them}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjdubah}(h]h ]h"]h$]h&]uh1j;hj1hhhhhNubeh}(h]h ]h"]h$]h&]jsjtuh1j6hhhKKhj^hhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlefpga_region (C struct) c.fpga_regionhNtauh1jhj^hhhNhNubhdesc)}(hhh](hdesc_signature)}(h fpga_regionh]hdesc_signature_line)}(hstruct fpga_regionh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(h fpga_regionh]j)}(hjh]h fpga_region}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]jah ](j sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(hFPGA Region structureh]hFPGA Region structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhj^hNhNubh container)}(hX**Definition**:: struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); }; **Members** ``dev`` FPGA Region device ``mutex`` enforces exclusive reference to region ``bridge_list`` list of FPGA bridges specified in region ``mgr`` FPGA manager ``info`` FPGA image info ``compat_id`` FPGA region id for compatibility check. ``ops_owner`` module containing the get_bridges function ``priv`` private data ``get_bridges`` optional function to get bridges to a listh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj$ubh:}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK$hj ubh literal_block)}(hX0struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); };h]hX0struct fpga_region { struct device dev; struct mutex mutex; struct list_head bridge_list; struct fpga_manager *mgr; struct fpga_image_info *info; struct fpga_compat_id *compat_id; struct module *ops_owner; void *priv; int (*get_bridges)(struct fpga_region *region); };}hjEsbah}(h]h ]h"]h$]h&]jjuh1jChl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK&hj ubh)}(h **Members**h]j))}(hjVh]hMembers}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjTubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK2hj ubhdefinition_list)}(hhh](hdefinition_list_item)}(h``dev`` FPGA Region device h](hterm)}(h``dev``h]j)}(hj{h]hdev}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK"hjsubh definition)}(hhh]h)}(hFPGA Region deviceh]hFPGA Region device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK"hjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jqhjhK"hjnubjr)}(h1``mutex`` enforces exclusive reference to region h](jx)}(h ``mutex``h]j)}(hjh]hmutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK#hjubj)}(hhh]h)}(h&enforces exclusive reference to regionh]h&enforces exclusive reference to region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhK#hjnubjr)}(h9``bridge_list`` list of FPGA bridges specified in region h](jx)}(h``bridge_list``h]j)}(hjh]h bridge_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK$hjubj)}(hhh]h)}(h(list of FPGA bridges specified in regionh]h(list of FPGA bridges specified in region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhK$hjnubjr)}(h``mgr`` FPGA manager h](jx)}(h``mgr``h]j)}(hj(h]hmgr}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK%hj"ubj)}(hhh]h)}(h FPGA managerh]h FPGA manager}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hK%hj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jqhj=hK%hjnubjr)}(h``info`` FPGA image info h](jx)}(h``info``h]j)}(hjah]hinfo}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK&hj[ubj)}(hhh]h)}(hFPGA image infoh]hFPGA image info}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhK&hjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jqhjvhK&hjnubjr)}(h6``compat_id`` FPGA region id for compatibility check. h](jx)}(h ``compat_id``h]j)}(hjh]h compat_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK'hjubj)}(hhh]h)}(h'FPGA region id for compatibility check.h]h'FPGA region id for compatibility check.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK'hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhK'hjnubjr)}(h9``ops_owner`` module containing the get_bridges function h](jx)}(h ``ops_owner``h]j)}(hjh]h ops_owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK(hjubj)}(hhh]h)}(h*module containing the get_bridges functionh]h*module containing the get_bridges function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhK(hjnubjr)}(h``priv`` private data h](jx)}(h``priv``h]j)}(hj h]hpriv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK)hjubj)}(hhh]h)}(h private datah]h private data}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK)hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhj!hK)hjnubjr)}(h:``get_bridges`` optional function to get bridges to a listh](jx)}(h``get_bridges``h]j)}(hjEh]h get_bridges}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK)hj?ubj)}(hhh]h)}(h*optional function to get bridges to a listh]h*optional function to get bridges to a list}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:81: ./include/linux/fpga/fpga-region.hhK*hj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jqhjZhK)hjnubeh}(h]h ]h"]h$]h&]uh1jlhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_region_info (C struct)c.fpga_region_infohNtauh1jhj^hhhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhNubj)}(hhh](j)}(hfpga_region_infoh]j)}(hstruct fpga_region_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hfpga_region_infoh]j)}(hjh]hfpga_region_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h'collection of parameters an FPGA Regionh]h'collection of parameters an FPGA Region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhK hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1jhhhj^hjhNubj)}(hX**Definition**:: struct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); }; **Members** ``mgr`` fpga region manager ``compat_id`` FPGA region id for compatibility check. ``priv`` fpga region private data ``get_bridges`` optional function to get bridges to a listh](h)}(h**Definition**::h](j))}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubjD)}(hstruct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); };h]hstruct fpga_region_info { struct fpga_manager *mgr; struct fpga_compat_id *compat_id; void *priv; int (*get_bridges)(struct fpga_region *region); };}hjsbah}(h]h ]h"]h$]h&]jjuh1jChl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubh)}(h **Members**h]j))}(hj0h]hMembers}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj.ubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubjm)}(hhh](jr)}(h``mgr`` fpga region manager h](jx)}(h``mgr``h]j)}(hjOh]hmgr}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjIubj)}(hhh]h)}(hfpga region managerh]hfpga region manager}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhKhjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jqhjdhKhjFubjr)}(h6``compat_id`` FPGA region id for compatibility check. h](jx)}(h ``compat_id``h]j)}(hjh]h compat_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubj)}(hhh]h)}(h'FPGA region id for compatibility check.h]h'FPGA region id for compatibility check.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhKhjFubjr)}(h"``priv`` fpga region private data h](jx)}(h``priv``h]j)}(hjh]hpriv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubj)}(hhh]h)}(hfpga region private datah]hfpga region private data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhKhjFubjr)}(h:``get_bridges`` optional function to get bridges to a listh](jx)}(h``get_bridges``h]j)}(hjh]h get_bridges}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhjubj)}(hhh]h)}(h*optional function to get bridges to a listh]h*optional function to get bridges to a list}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhj hKhjFubeh}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhjhNubh)}(h**Description**h]j))}(hj= h]h Description}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj; ubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhj^hhubh)}(hfpga_region_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.h]hfpga_region_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:84: ./include/linux/fpga/fpga-region.hhKhj^hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(__fpga_region_register_full (C function)c.__fpga_region_register_fullhNtauh1jhj^hhhNhNubj)}(hhh](j)}(hstruct fpga_region * __fpga_region_register_full (struct device *parent, const struct fpga_region_info *info, struct module *owner)h]j)}(hstruct fpga_region *__fpga_region_register_full(struct device *parent, const struct fpga_region_info *info, struct module *owner)h](j)}(hjh]hstruct}(hj{ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw hhhj hKubh)}(hhh]j)}(h fpga_regionh]h fpga_region}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j ASTIdentifier)}j__fpga_region_register_fullsbc.__fpga_region_register_fullasbuh1hhjw hhhj hKubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw hhhj hKubhdesc_sig_punctuation)}(hjth]h*}(hj hhhNhNubah}(h]h ]pah"]h$]h&]uh1j hjw hhhj hKubj)}(h__fpga_region_register_fullh]j)}(hj h]h__fpga_region_register_full}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjw hhhj hKubhdesc_parameterlist)}(hR(struct device *parent, const struct fpga_region_info *info, struct module *owner)h](hdesc_parameter)}(hstruct device *parenth](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hdeviceh]hdevice}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j c.__fpga_region_register_fullasbuh1hhj ubj)}(h h]h }(hj: hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj )}(hjth]h*}(hjH hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubj)}(hparenth]hparent}(hjU hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubj )}(h#const struct fpga_region_info *infoh](j)}(hconsth]hconst}(hjn hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(h h]h }(hj| hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubh)}(hhh]j)}(hfpga_region_infoh]hfpga_region_info}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j c.__fpga_region_register_fullasbuh1hhjj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubj )}(hjth]h*}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjj ubj)}(hinfoh]hinfo}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjj ubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubj )}(hstruct module *ownerh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(hmoduleh]hmodule}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j c.__fpga_region_register_fullasbuh1hhj ubj)}(h h]h }(hj6 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj )}(hjth]h*}(hjD hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubj)}(hownerh]howner}(hjQ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubeh}(h]h ]h"]h$]h&]jjuh1j hjw hhhj hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjs hhhj hKubah}(h]jn ah ](jjeh"]h$]h&]jj)jhuh1jhj hKhjp hhubj)}(hhh]h)}(h)create and register an FPGA Region deviceh]h)create and register an FPGA Region device}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhjx hhubah}(h]h ]h"]h$]h&]uh1jhjp hhhj hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jhhhj^hNhNubj)}(h**Parameters** ``struct device *parent`` device parent ``const struct fpga_region_info *info`` parameters for FPGA Region ``struct module *owner`` module containing the get_bridges function **Return** struct fpga_region or ERR_PTR()h](h)}(h**Parameters**h]j))}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj ubjm)}(hhh](jr)}(h(``struct device *parent`` device parent h](jx)}(h``struct device *parent``h]j)}(hj h]hstruct device *parent}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj ubj)}(hhh]h)}(h device parenth]h device parent}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jqhj hKhj ubjr)}(hC``const struct fpga_region_info *info`` parameters for FPGA Region h](jx)}(h'``const struct fpga_region_info *info``h]j)}(hj h]h#const struct fpga_region_info *info}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj ubj)}(hhh]h)}(hparameters for FPGA Regionh]hparameters for FPGA Region}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jqhj hKhj ubjr)}(hD``struct module *owner`` module containing the get_bridges function h](jx)}(h``struct module *owner``h]j)}(hj. h]hstruct module *owner}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj, ubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj( ubj)}(hhh]h)}(h*module containing the get_bridges functionh]h*module containing the get_bridges function}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC hKhjD ubah}(h]h ]h"]h$]h&]uh1jhj( ubeh}(h]h ]h"]h$]h&]uh1jqhjC hKhj ubeh}(h]h ]h"]h$]h&]uh1jlhj ubh)}(h **Return**h]j))}(hji h]hReturn}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjg ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj ubh)}(hstruct fpga_region or ERR_PTR()h]hstruct fpga_region or ERR_PTR()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:87: ./drivers/fpga/fpga-region.chKhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#__fpga_region_register (C function)c.__fpga_region_registerhNtauh1jhj^hhhNhNubj)}(hhh](j)}(hstruct fpga_region * __fpga_region_register (struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region *), struct module *owner)h]j)}(hstruct fpga_region *__fpga_region_register(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region*), struct module *owner)h](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubh)}(hhh]j)}(h fpga_regionh]h fpga_region}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j )}j__fpga_region_registersbc.__fpga_region_registerasbuh1hhj hhhj hMubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMubj )}(hjth]h*}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj hhhj hMubj)}(h__fpga_region_registerh]j)}(hj h]h__fpga_region_register}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj hhhj hMubj )}(hp(struct device *parent, struct fpga_manager *mgr, int (*get_bridges)(struct fpga_region*), struct module *owner)h](j )}(hstruct device *parenth](j)}(hjh]hstruct}(hj( hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubj)}(h h]h }(hj5 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubh)}(hhh]j)}(hdeviceh]hdevice}(hjF hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjC ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjH modnameN classnameNjj)}j]j c.__fpga_region_registerasbuh1hhj$ ubj)}(h h]h }(hjd hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubj )}(hjth]h*}(hjr hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj$ ubj)}(hparenth]hparent}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ ubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubj )}(hstruct fpga_manager *mgrh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j c.__fpga_region_registerasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj )}(hjth]h*}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubj)}(hmgrh]hmgr}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubj )}(h'int (*get_bridges)(struct fpga_region*)h](hdesc_sig_keyword_type)}(hinth]hint}(hj hhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(h(h]h(}(hj'hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hjth]h*}(hj5hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(h get_bridgesh]h get_bridges}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(h)h]h)}(hjPhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj)h]h(}(hj^hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hjh]hstruct}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h fpga_regionh]h fpga_region}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j c.__fpga_region_registerasbuh1hhjubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hjRh]h)}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubj )}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j c.__fpga_region_registerasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hownerh]howner}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj ubeh}(h]h ]h"]h$]h&]jjuh1j hj hhhj hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj hMubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1jhj hMhj hhubj)}(hhh]h)}(h)create and register an FPGA Region deviceh]h)create and register an FPGA Region device}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhjJhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjejjejjjuh1jhhhj^hNhNubj)}(hX!**Parameters** ``struct device *parent`` device parent ``struct fpga_manager *mgr`` manager that programs this region ``int (*get_bridges)(struct fpga_region *)`` optional function to get bridges to a list ``struct module *owner`` module containing the get_bridges function **Description** This simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters. **Return** struct fpga_region or ERR_PTR()h](h)}(h**Parameters**h]j))}(hjoh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjmubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhjiubjm)}(hhh](jr)}(h(``struct device *parent`` device parent h](jx)}(h``struct device *parent``h]j)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhjubj)}(hhh]h)}(h device parenth]h device parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhKhjubjr)}(h?``struct fpga_manager *mgr`` manager that programs this region h](jx)}(h``struct fpga_manager *mgr``h]j)}(hjh]hstruct fpga_manager *mgr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhjubj)}(hhh]h)}(h!manager that programs this regionh]h!manager that programs this region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhKhjubjr)}(hX``int (*get_bridges)(struct fpga_region *)`` optional function to get bridges to a list h](jx)}(h,``int (*get_bridges)(struct fpga_region *)``h]j)}(hjh]h(int (*get_bridges)(struct fpga_region *)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhjubj)}(hhh]h)}(h*optional function to get bridges to a listh]h*optional function to get bridges to a list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhKhjubjr)}(hD``struct module *owner`` module containing the get_bridges function h](jx)}(h``struct module *owner``h]j)}(hj9h]hstruct module *owner}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chKhj3ubj)}(hhh]h)}(h*module containing the get_bridges functionh]h*module containing the get_bridges function}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhKhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jqhjNhKhjubeh}(h]h ]h"]h$]h&]uh1jlhjiubh)}(h**Description**h]j))}(hjth]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjrubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chMhjiubh)}(hThis simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters.h]hThis simple version of the register function should be sufficient for most users. The fpga_region_register_full() function is available for users that need to pass additional, optional parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chMhjiubh)}(h **Return**h]j))}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chMhjiubh)}(hstruct fpga_region or ERR_PTR()h]hstruct fpga_region or ERR_PTR()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:90: ./drivers/fpga/fpga-region.chMhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#fpga_region_unregister (C function)c.fpga_region_unregisterhNtauh1jhj^hhhNhNubj)}(hhh](j)}(h8void fpga_region_unregister (struct fpga_region *region)h]j)}(h7void fpga_region_unregister(struct fpga_region *region)h](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hfpga_region_unregisterh]j)}(hfpga_region_unregisterh]hfpga_region_unregister}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubj )}(h(struct fpga_region *region)h]j )}(hstruct fpga_region *regionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h fpga_regionh]h fpga_region}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=modnameN classnameNjj)}j]j )}jjsbc.fpga_region_unregisterasbuh1hhjubj)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hjihhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hregionh]hregion}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjubah}(h]h ]h"]h$]h&]jjuh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(hunregister an FPGA regionh]hunregister an FPGA region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj^hNhNubj)}(h**Parameters** ``struct fpga_region *region`` FPGA region **Description** This function is intended for use in an FPGA region driver's remove function.h](h)}(h**Parameters**h]j))}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMhjubjm)}(hhh]jr)}(h+``struct fpga_region *region`` FPGA region h](jx)}(h``struct fpga_region *region``h]j)}(hjh]hstruct fpga_region *region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMhjubj)}(hhh]h)}(h FPGA regionh]h FPGA region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhMhjubah}(h]h ]h"]h$]h&]uh1jlhjubh)}(h**Description**h]j))}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMhjubh)}(hMThis function is intended for use in an FPGA region driver's remove function.h]hOThis function is intended for use in an FPGA region driver’s remove function.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:93: ./drivers/fpga/fpga-region.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_mgr_get (C function)c.fpga_mgr_gethNtauh1jhj^hhhNhNubj)}(hhh](j)}(h7struct fpga_manager * fpga_mgr_get (struct device *dev)h]j)}(h5struct fpga_manager *fpga_mgr_get(struct device *dev)h](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhjnhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j )}j fpga_mgr_getsbc.fpga_mgr_getasbuh1hhj]hhhjnhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhjnhMubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj]hhhjnhMubj)}(h fpga_mgr_geth]j)}(hjh]h fpga_mgr_get}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhj]hhhjnhMubj )}(h(struct device *dev)h]j )}(hstruct device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.fpga_mgr_getasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hj%hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hdevh]hdev}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjubah}(h]h ]h"]h$]h&]jjuh1j hj]hhhjnhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjYhhhjnhMubah}(h]jTah ](jjeh"]h$]h&]jj)jhuh1jhjnhMhjVhhubj)}(hhh]h)}(h/Given a device, get a reference to an fpga mgr.h]h/Given a device, get a reference to an fpga mgr.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMhjYhhubah}(h]h ]h"]h$]h&]uh1jhjVhhhjnhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjtjjtjjjuh1jhhhj^hNhNubj)}(h**Parameters** ``struct device *dev`` parent device that fpga mgr was registered with **Return** fpga manager struct or IS_ERR() condition containing error code.h](h)}(h**Parameters**h]j))}(hj~h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj|ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMhjxubjm)}(hhh]jr)}(hG``struct device *dev`` parent device that fpga mgr was registered with h](jx)}(h``struct device *dev``h]j)}(hjh]hstruct device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(h/parent device that fpga mgr was registered withh]h/parent device that fpga mgr was registered with}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhMhjubah}(h]h ]h"]h$]h&]uh1jlhjxubh)}(h **Return**h]j))}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMhjxubh)}(h@fpga manager struct or IS_ERR() condition containing error code.h]h@fpga manager struct or IS_ERR() condition containing error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:96: ./drivers/fpga/fpga-mgr.chMhjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jof_fpga_mgr_get (C function)c.of_fpga_mgr_gethNtauh1jhj^hhhNhNubj)}(hhh](j)}(h@struct fpga_manager * of_fpga_mgr_get (struct device_node *node)h]j)}(h>struct fpga_manager *of_fpga_mgr_get(struct device_node *node)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj*hMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj>modnameN classnameNjj)}j]j )}jof_fpga_mgr_getsbc.of_fpga_mgr_getasbuh1hhjhhhj*hMubj)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhj*hMubj )}(hjth]h*}(hjkhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhj*hMubj)}(hof_fpga_mgr_geth]j)}(hjZh]hof_fpga_mgr_get}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhj*hMubj )}(h(struct device_node *node)h]j )}(hstruct device_node *node|h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h device_nodeh]h device_node}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jXc.of_fpga_mgr_getasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hnodeh]hnode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjubah}(h]h ]h"]h$]h&]jjuh1j hjhhhj*hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhj*hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj*hMhjhhubj)}(hhh]h)}(h4Given a device node, get a reference to an fpga mgr.h]h4Given a device node, get a reference to an fpga mgr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj*hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj0jj0jjjuh1jhhhj^hNhNubj)}(h**Parameters** ``struct device_node *node`` device node **Return** fpga manager struct or IS_ERR() condition containing error code.h](h)}(h**Parameters**h]j))}(hj:h]h Parameters}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hj8ubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMhj4ubjm)}(hhh]jr)}(h)``struct device_node *node`` device node h](jx)}(h``struct device_node *node``h]j)}(hjYh]hstruct device_node *node}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jwhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMhjSubj)}(hhh]h)}(h device nodeh]h device node}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhMhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jqhjnhMhjPubah}(h]h ]h"]h$]h&]uh1jlhj4ubh)}(h **Return**h]j))}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMhj4ubh)}(h@fpga manager struct or IS_ERR() condition containing error code.h]h@fpga manager struct or IS_ERR() condition containing error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhc/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:99: ./drivers/fpga/fpga-mgr.chMhj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_mgr_put (C function)c.fpga_mgr_puthNtauh1jhj^hhhNhNubj)}(hhh](j)}(h,void fpga_mgr_put (struct fpga_manager *mgr)h]j)}(h+void fpga_mgr_put(struct fpga_manager *mgr)h](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(h fpga_mgr_puth]j)}(h fpga_mgr_puth]h fpga_mgr_put}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMubj )}(h(struct fpga_manager *mgr)h]j )}(hstruct fpga_manager *mgrh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j )}jjsbc.fpga_mgr_putasbuh1hhjubj)}(h h]h }(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hjbhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hmgrh]hmgr}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjubah}(h]h ]h"]h$]h&]jjuh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h&release a reference to an fpga managerh]h&release a reference to an fpga manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj^hNhNubj)}(hE**Parameters** ``struct fpga_manager *mgr`` fpga manager structureh](h)}(h**Parameters**h]j))}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.chMhjubjm)}(hhh]jr)}(h3``struct fpga_manager *mgr`` fpga manager structureh](jx)}(h``struct fpga_manager *mgr``h]j)}(hjh]hstruct fpga_manager *mgr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(hfpga manager structureh]hfpga manager structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:102: ./drivers/fpga/fpga-mgr.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhMhjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$fpga_bridge_get_to_list (C function)c.fpga_bridge_get_to_listhNtauh1jhj^hhhNhNubj)}(hhh](j)}(hmint fpga_bridge_get_to_list (struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)h]j)}(hlint fpga_bridge_get_to_list(struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)h](j )}(hinth]hint}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chM ubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhhjBhM ubj)}(hfpga_bridge_get_to_listh]j)}(hfpga_bridge_get_to_listh]hfpga_bridge_get_to_list}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubah}(h]h ](jjeh"]h$]h&]jjuh1jhj0hhhjBhM ubj )}(hQ(struct device *dev, struct fpga_image_info *info, struct list_head *bridge_list)h](j )}(hstruct device *devh](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j )}jjWsbc.fpga_bridge_get_to_listasbuh1hhjmubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjmubj)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjiubj )}(hstruct fpga_image_info *infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hfpga_image_infoh]hfpga_image_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.fpga_bridge_get_to_listasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj )}(hjth]h*}(hj-hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj)}(hinfoh]hinfo}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjiubj )}(hstruct list_head *bridge_listh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubj)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubh)}(hhh]j)}(h list_headh]h list_head}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]jc.fpga_bridge_get_to_listasbuh1hhjOubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjOubj)}(h bridge_listh]h bridge_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]noemphjjuh1j hjiubeh}(h]h ]h"]h$]h&]jjuh1j hj0hhhjBhM ubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj,hhhjBhM ubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1jhjBhM hj)hhubj)}(hhh]h)}(h,given device, get a bridge, add it to a listh]h,given device, get a bridge, add it to a list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj)hhhjBhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj^hNhNubj)}(hXQ**Parameters** ``struct device *dev`` FPGA bridge device ``struct fpga_image_info *info`` fpga image specific information ``struct list_head *bridge_list`` list of FPGA bridges **Description** Get an exclusive reference to the bridge and it to the list. **Return** 0 for success, error code from fpga_bridge_get() otherwise.h](h)}(h**Parameters**h]j))}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chMhjubjm)}(hhh](jr)}(h*``struct device *dev`` FPGA bridge device h](jx)}(h``struct device *dev``h]j)}(hjh]hstruct device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chMhjubj)}(hhh]h)}(hFPGA bridge deviceh]hFPGA bridge device}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhj*hMhj ubjr)}(hA``struct fpga_image_info *info`` fpga image specific information h](jx)}(h ``struct fpga_image_info *info``h]j)}(hjNh]hstruct fpga_image_info *info}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jwhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chMhjHubj)}(hhh]h)}(hfpga image specific informationh]hfpga image specific information}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchMhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jqhjchMhj ubjr)}(h7``struct list_head *bridge_list`` list of FPGA bridges h](jx)}(h!``struct list_head *bridge_list``h]j)}(hjh]hstruct list_head *bridge_list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jwhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chMhjubj)}(hhh]h)}(hlist of FPGA bridgesh]hlist of FPGA bridges}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jqhjhMhj ubeh}(h]h ]h"]h$]h&]uh1jlhjubh)}(h**Description**h]j))}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:105: ./drivers/fpga/fpga-bridge.chM hjubh)}(h0 for success, error code from of_fpga_bridge_get() otherwise.h]h>0 for success, error code from of_fpga_bridge_get() otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:108: ./drivers/fpga/fpga-bridge.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj^hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_bridges_put (C function)c.fpga_bridges_puthNtauh1jhj^hhhNhNubj)}(hhh](j)}(h5void fpga_bridges_put (struct list_head *bridge_list)h]j)}(h4void fpga_bridges_put(struct list_head *bridge_list)h](j )}(hvoidh]hvoid}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.chKubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$hhhj6hKubj)}(hfpga_bridges_puth]j)}(hfpga_bridges_puth]hfpga_bridges_put}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]jjuh1jhj$hhhj6hKubj )}(h(struct list_head *bridge_list)h]j )}(hstruct list_head *bridge_listh](j)}(hjh]hstruct}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubh)}(hhh]j)}(h list_headh]h list_head}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j )}jjKsbc.fpga_bridges_putasbuh1hhjaubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj )}(hjth]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjaubj)}(h bridge_listh]h bridge_list}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphjjuh1j hj]ubah}(h]h ]h"]h$]h&]jjuh1j hj$hhhj6hKubeh}(h]h ]h"]h$]h&]jjjuh1jjjhj hhhj6hKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhj6hKhjhhubj)}(hhh]h)}(h put bridgesh]h put bridges}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj6hKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jhhhj^hNhNubj)}(h**Parameters** ``struct list_head *bridge_list`` list of FPGA bridges **Description** For each bridge in the list, put the bridge and remove it from the list. If list is empty, do nothing.h](h)}(h**Parameters**h]j))}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.chKhjubjm)}(hhh]jr)}(h7``struct list_head *bridge_list`` list of FPGA bridges h](jx)}(h!``struct list_head *bridge_list``h]j)}(hj)h]hstruct list_head *bridge_list}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jwhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.chKhj#ubj)}(hhh]h)}(hlist of FPGA bridgesh]hlist of FPGA bridges}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj?ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jqhj>hKhj ubah}(h]h ]h"]h$]h&]uh1jlhjubh)}(h**Description**h]j))}(hjdh]h Description}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j(hjbubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-region:111: ./drivers/fpga/fpga-bridge.chKhjubh)}(hfFor each bridge in the list, put the bridge and remove it from the list. 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