Wsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget4/translations/zh_CN/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/zh_TW/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/it_IT/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/ja_JP/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/ko_KR/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget4/translations/sp_SP/driver-api/fpga/fpga-programmingmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h"In-kernel API for FPGA Programmingh]h"In-kernel API for FPGA Programming}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhN/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming.rsthKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe in-kernel API for FPGA programming is a combination of APIs from FPGA manager, bridge, and regions. The actual function used to trigger FPGA programming is fpga_region_program_fpga().h]hThe in-kernel API for FPGA programming is a combination of APIs from FPGA manager, bridge, and regions. The actual function used to trigger FPGA programming is fpga_region_program_fpga().}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hafpga_region_program_fpga() uses functionality supplied by the FPGA manager and bridges. It will:h]hafpga_region_program_fpga() uses functionality supplied by the FPGA manager and bridges. It will:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh block_quote)}(hX* lock the region's mutex * lock the mutex of the region's FPGA manager * build a list of FPGA bridges if a method has been specified to do so * disable the bridges * program the FPGA using info passed in :c:expr:`fpga_region->info`. * re-enable the bridges * release the locks h]h bullet_list)}(hhh](h list_item)}(hlock the region's mutexh]h)}(hhh]hlock the region’s mutex}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h+lock the mutex of the region's FPGA managerh]h)}(hj h]h-lock the mutex of the region’s FPGA manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hDbuild a list of FPGA bridges if a method has been specified to do soh]h)}(hj#h]hDbuild a list of FPGA bridges if a method has been specified to do so}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj!ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hdisable the bridgesh]h)}(hj:h]hdisable the bridges}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hBprogram the FPGA using info passed in :c:expr:`fpga_region->info`.h]h)}(hjQh](h&program the FPGA using info passed in }(hjShhhNhNubh desc_inline)}(hfpga_region->infoh](h)}(hhh]h desc_sig_name)}(h fpga_regionh]h fpga_region}(hjehhhNhNubah}(h]h ]nah"]h$]h&]uh1jchj`ubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjgmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]sbuh1hhj\ubhdesc_sig_operator)}(h->h]h->}(hjhhhNhNubah}(h]h ]oah"]h$]h&]uh1jhj\ubjd)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchj\ubeh}(h]h ](c-exprsig sig-inlinej{eh"]h$]h&]uh1jZhjSubh.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hre-enable the bridgesh]h)}(hjh]hre-enable the bridges}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hrelease the locks h]h)}(hrelease the locksh]hrelease the locks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe struct fpga_image_info specifies what FPGA image to program. It is allocated/freed by fpga_image_info_alloc() and freed with fpga_image_info_free()h]hThe struct fpga_image_info specifies what FPGA image to program. It is allocated/freed by fpga_image_info_alloc() and freed with fpga_image_info_free()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h%How to program an FPGA using a regionh]h%How to program an FPGA using a region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX0When the FPGA region driver probed, it was given a pointer to an FPGA manager driver so it knows which manager to use. The region also either has a list of bridges to control during programming or it has a pointer to a function that will generate that list. Here's some sample code of what to do next::h]hX1When the FPGA region driver probed, it was given a pointer to an FPGA manager driver so it knows which manager to use. The region also either has a list of bridges to control during programming or it has a pointer to a function that will generate that list. Here’s some sample code of what to do next:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh literal_block)}(hXs#include #include struct fpga_image_info *info; int ret; /* * First, alloc the struct with information about the FPGA image to * program. */ info = fpga_image_info_alloc(dev); if (!info) return -ENOMEM; /* Set flags as needed, such as: */ info->flags = FPGA_MGR_PARTIAL_RECONFIG; /* * Indicate where the FPGA image is. This is pseudo-code; you're * going to use one of these three. */ if (image is in a scatter gather table) { info->sgt = [your scatter gather table] } else if (image is in a buffer) { info->buf = [your image buffer] info->count = [image buffer size] } else if (image is in a firmware file) { info->firmware_name = devm_kstrdup(dev, firmware_name, GFP_KERNEL); } /* Add info to region and do the programming */ region->info = info; ret = fpga_region_program_fpga(region); /* Deallocate the image info if you're done with it */ region->info = NULL; fpga_image_info_free(info); if (ret) return ret; /* Now enumerate whatever hardware has appeared in the FPGA. */h]hXs#include #include struct fpga_image_info *info; int ret; /* * First, alloc the struct with information about the FPGA image to * program. */ info = fpga_image_info_alloc(dev); if (!info) return -ENOMEM; /* Set flags as needed, such as: */ info->flags = FPGA_MGR_PARTIAL_RECONFIG; /* * Indicate where the FPGA image is. This is pseudo-code; you're * going to use one of these three. */ if (image is in a scatter gather table) { info->sgt = [your scatter gather table] } else if (image is in a buffer) { info->buf = [your image buffer] info->count = [image buffer size] } else if (image is in a firmware file) { info->firmware_name = devm_kstrdup(dev, firmware_name, GFP_KERNEL); } /* Add info to region and do the programming */ region->info = info; ret = fpga_region_program_fpga(region); /* Deallocate the image info if you're done with it */ region->info = NULL; fpga_image_info_free(info); if (ret) return ret; /* Now enumerate whatever hardware has appeared in the FPGA. */}hj5sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1j3hhhK"hjhhubeh}(h]%how-to-program-an-fpga-using-a-regionah ]h"]%how to program an fpga using a regionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hAPI for programming an FPGAh]hAPI for programming an FPGA}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhKUubh)}(hhh](h)}(h-fpga_region_program_fpga() - Program an FPGAh]h)}(hjch]h-fpga_region_program_fpga() - Program an FPGA}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjaubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h9fpga_image_info() - Specifies what FPGA image to programh]h)}(hjzh]h9fpga_image_info() - Specifies what FPGA image to program}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhjxubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h=fpga_image_info_alloc() - Allocate an FPGA image info structh]h)}(hjh]h=fpga_image_info_alloc() - Allocate an FPGA image info struct}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubh)}(h9fpga_image_info_free() - Free an FPGA image info struct h]h)}(h8fpga_image_info_free() - Free an FPGA image info structh]h8fpga_image_info_free() - Free an FPGA image info struct}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjubah}(h]h ]h"]h$]h&]uh1hhj^hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKWhjMhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single%fpga_region_program_fpga (C function)c.fpga_region_program_fpgahNtauh1jhjMhhhNhNubhdesc)}(hhh](hdesc_signature)}(h9int fpga_region_program_fpga (struct fpga_region *region)h]hdesc_signature_line)}(h8int fpga_region_program_fpga(struct fpga_region *region)h](hdesc_sig_keyword_type)}(hinth]hint}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKaubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKaubh desc_name)}(hfpga_region_program_fpgah]jd)}(hfpga_region_program_fpgah]hfpga_region_program_fpga}(hjhhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchj ubah}(h]h ](sig-namedescnameeh"]h$]h&]jCjDuh1j hjhhhjhKaubhdesc_parameterlist)}(h(struct fpga_region *region)h]hdesc_parameter)}(hstruct fpga_region *regionh](hdesc_sig_keyword)}(hstructh]hstruct}(hj3hhhNhNubah}(h]h ]kah"]h$]h&]uh1j1hj-ubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubh)}(hhh]jd)}(h fpga_regionh]h fpga_region}(hjShhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchjPubah}(h]h ]h"]h$]h&] refdomainj{reftypej} reftargetjUmodnameN classnameNjj)}j]j ASTIdentifier)}j}jsbc.fpga_region_program_fpgaasbuh1hhj-ubj)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubhdesc_sig_punctuation)}(hjh]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj-ubjd)}(hregionh]hregion}(hjhhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchj-ubeh}(h]h ]h"]h$]h&]noemphjCjDuh1j+hj'ubah}(h]h ]h"]h$]h&]jCjDuh1j%hjhhhjhKaubeh}(h]h ]h"]h$]h&]jCjD add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKaubah}(h]jah ](j sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKahjhhubh desc_content)}(hhh]h)}(h program FPGAh]h program FPGA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKThjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKaubeh}(h]h ](j{functioneh"]h$]h&]domainj{objtypejdesctypejnoindex noindexentrynocontentsentryuh1jhhhjMhNhNubh container)}(hX**Parameters** ``struct fpga_region *region`` FPGA region **Description** Program an FPGA using fpga image info (region->info). If the region has a get_bridges function, the exclusive reference for the bridges will be held if programming succeeds. This is intended to prevent reprogramming the region until the caller considers it safe to do so. The caller will need to call fpga_bridges_put() before attempting to reprogram the region. **Return** 0 for success or negative error code.h](h)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKXhjubhdefinition_list)}(hhh]hdefinition_list_item)}(h+``struct fpga_region *region`` FPGA region h](hterm)}(h``struct fpga_region *region``h]hliteral)}(hjh]hstruct fpga_region *region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKVhjubh definition)}(hhh]h)}(h FPGA regionh]h FPGA region}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hKVhj1ubah}(h]h ]h"]h$]h&]uh1j/hjubeh}(h]h ]h"]h$]h&]uh1j hj.hKVhj ubah}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjVh]h Description}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKXhjubh)}(hXkProgram an FPGA using fpga image info (region->info). If the region has a get_bridges function, the exclusive reference for the bridges will be held if programming succeeds. This is intended to prevent reprogramming the region until the caller considers it safe to do so. The caller will need to call fpga_bridges_put() before attempting to reprogram the region.h]hXkProgram an FPGA using fpga image info (region->info). If the region has a get_bridges function, the exclusive reference for the bridges will be held if programming succeeds. This is intended to prevent reprogramming the region until the caller considers it safe to do so. The caller will need to call fpga_bridges_put() before attempting to reprogram the region.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chKXhjubh)}(h **Return**h]j)}(hj}h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chK_hjubh)}(h%0 for success or negative error code.h]h%0 for success or negative error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhk/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:92: ./drivers/fpga/fpga-region.chK_hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjMhhhNhNubh)}(hFPGA Manager flagsh]hFPGA Manager flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjMhhubh)}(hJFlags used in the :c:type:`fpga_image_info->flags ` fieldh](hFlags used in the }(hjhhhNhNubh)}(h2:c:type:`fpga_image_info->flags `h]j)}(hjh]hfpga_image_info->flags}(hjhhhNhNubah}(h]h ](xrefj{c-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc driver-api/fpga/fpga-programming refdomainj{reftypetype refexplicitrefwarnjj)}j]sb reftargetfpga_image_infouh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhK=hjubh field}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhK=hjMhhubh)}(hF``FPGA_MGR_PARTIAL_RECONFIG``: do partial reconfiguration if supportedh](j)}(h``FPGA_MGR_PARTIAL_RECONFIG``h]hFPGA_MGR_PARTIAL_RECONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh): do partial reconfiguration if supported}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhK?hjMhhubh)}(hM``FPGA_MGR_EXTERNAL_CONFIG``: FPGA has been configured prior to Linux bootingh](j)}(h``FPGA_MGR_EXTERNAL_CONFIG``h]hFPGA_MGR_EXTERNAL_CONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh1: FPGA has been configured prior to Linux booting}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhKAhjMhhubh)}(hB``FPGA_MGR_ENCRYPTED_BITSTREAM``: indicates bitstream is encryptedh](j)}(h ``FPGA_MGR_ENCRYPTED_BITSTREAM``h]hFPGA_MGR_ENCRYPTED_BITSTREAM}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubh": indicates bitstream is encrypted}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhKChjMhhubh)}(hF``FPGA_MGR_BITSTREAM_LSB_FIRST``: SPI bitstream bit order is LSB firsth](j)}(h ``FPGA_MGR_BITSTREAM_LSB_FIRST``h]hFPGA_MGR_BITSTREAM_LSB_FIRST}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubh&: SPI bitstream bit order is LSB first}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhKEhjMhhubh)}(h?``FPGA_MGR_COMPRESSED_BITSTREAM``: FPGA bitstream is compressedh](j)}(h!``FPGA_MGR_COMPRESSED_BITSTREAM``h]hFPGA_MGR_COMPRESSED_BITSTREAM}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubh: FPGA bitstream is compressed}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhn/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:97: ./include/linux/fpga/fpga-mgr.hhKGhjMhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_image_info (C struct)c.fpga_image_infohNtauh1jhjMhhhNhNubj)}(hhh](j)}(hfpga_image_infoh]j)}(hstruct fpga_image_infoh](j2)}(hj5h]hstruct}(hjhhhNhNubah}(h]h ]j>ah"]h$]h&]uh1j1hjhhho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj )}(hfpga_image_infoh]jd)}(hjh]hfpga_image_info}(hjhhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchjubah}(h]h ](j j!eh"]h$]h&]jCjDuh1j hjhhhjhKubeh}(h]h ]h"]h$]h&]jCjDjuh1jjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h%information specific to an FPGA imageh]h%information specific to an FPGA image}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKRhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](j{structeh"]h$]h&]jj{jjjjjjjuh1jhhhjMhNhNubj)}(hX**Definition**:: struct fpga_image_info { u32 flags; u32 enable_timeout_us; u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; struct sg_table *sgt; const char *buf; size_t count; size_t header_size; size_t data_size; int region_id; struct device *dev; #ifdef CONFIG_OF; struct device_node *overlay; #endif; }; **Members** ``flags`` boolean flags as defined above ``enable_timeout_us`` maximum time to enable traffic through bridge (uSec) ``disable_timeout_us`` maximum time to disable traffic through bridge (uSec) ``config_complete_timeout_us`` maximum time for FPGA to switch to operating status in the write_complete op. ``firmware_name`` name of FPGA image firmware file ``sgt`` scatter/gather table containing FPGA image ``buf`` contiguous buffer containing FPGA image ``count`` size of buf ``header_size`` size of image header. ``data_size`` size of image data to be sent to the device. If not specified, whole image will be used. Header may be skipped in either case. ``region_id`` id of target region ``dev`` device that owns this ``overlay`` Device Tree overlayh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKVhjubj4)}(hXsstruct fpga_image_info { u32 flags; u32 enable_timeout_us; u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; struct sg_table *sgt; const char *buf; size_t count; size_t header_size; size_t data_size; int region_id; struct device *dev; #ifdef CONFIG_OF; struct device_node *overlay; #endif; };h]hXsstruct fpga_image_info { u32 flags; u32 enable_timeout_us; u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; struct sg_table *sgt; const char *buf; size_t count; size_t header_size; size_t data_size; int region_id; struct device *dev; #ifdef CONFIG_OF; struct device_node *overlay; #endif; };}hjsbah}(h]h ]h"]h$]h&]jCjDuh1j3ho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKXhjubh)}(h **Members**h]j)}(hj)h]hMembers}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKjhjubj )}(hhh](j)}(h)``flags`` boolean flags as defined above h](j)}(h ``flags``h]j)}(hjHh]hflags}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKThjBubj0)}(hhh]h)}(hboolean flags as defined aboveh]hboolean flags as defined above}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hKThj^ubah}(h]h ]h"]h$]h&]uh1j/hjBubeh}(h]h ]h"]h$]h&]uh1j hj]hKThj?ubj)}(hK``enable_timeout_us`` maximum time to enable traffic through bridge (uSec) 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]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKYhj'ubj0)}(hhh]h)}(h name of FPGA image firmware fileh]h name of FPGA image firmware file}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhKYhjCubah}(h]h ]h"]h$]h&]uh1j/hj'ubeh}(h]h ]h"]h$]h&]uh1j hjBhKYhj?ubj)}(h3``sgt`` scatter/gather table containing FPGA image h](j)}(h``sgt``h]j)}(hjfh]hsgt}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKZhj`ubj0)}(hhh]h)}(h*scatter/gather table containing FPGA imageh]h*scatter/gather table containing FPGA image}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hKZhj|ubah}(h]h ]h"]h$]h&]uh1j/hj`ubeh}(h]h ]h"]h$]h&]uh1j hj{hKZhj?ubj)}(h0``buf`` contiguous buffer containing FPGA image h](j)}(h``buf``h]j)}(hjh]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK[hjubj0)}(hhh]h)}(h'contiguous buffer containing FPGA imageh]h'contiguous buffer containing FPGA image}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK[hjubah}(h]h ]h"]h$]h&]uh1j/hjubeh}(h]h ]h"]h$]h&]uh1j hjhK[hj?ubj)}(h``count`` size of buf h](j)}(h ``count``h]j)}(hjh]hcount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK\hjubj0)}(hhh]h)}(h size of bufh]h size of buf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK\hjubah}(h]h ]h"]h$]h&]uh1j/hjubeh}(h]h ]h"]h$]h&]uh1j hjhK\hj?ubj)}(h&``header_size`` size of image header. h](j)}(h``header_size``h]j)}(hjh]h header_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK]hj ubj0)}(hhh]h)}(hsize of image header.h]hsize of image header.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hK]hj'ubah}(h]h ]h"]h$]h&]uh1j/hj ubeh}(h]h ]h"]h$]h&]uh1j hj&hK]hj?ubj)}(h``data_size`` size of image data to be sent to the device. If not specified, whole image will be used. Header may be skipped in either case. h](j)}(h ``data_size``h]j)}(hjJh]h data_size}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK_hjDubj0)}(hhh]h)}(h~size of image data to be sent to the device. If not specified, whole image will be used. Header may be skipped in either case.h]h~size of image data to be sent to the device. If not specified, whole image will be used. Header may be skipped in either case.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK^hj`ubah}(h]h ]h"]h$]h&]uh1j/hjDubeh}(h]h ]h"]h$]h&]uh1j hj_hK_hj?ubj)}(h"``region_id`` id of target region h](j)}(h ``region_id``h]j)}(hjh]h region_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhK`hj~ubj0)}(hhh]h)}(hid of target regionh]hid of target region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK`hjubah}(h]h ]h"]h$]h&]uh1j/hj~ubeh}(h]h ]h"]h$]h&]uh1j hjhK`hj?ubj)}(h``dev`` device that owns this h](j)}(h``dev``h]j)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jho/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:100: ./include/linux/fpga/fpga-mgr.hhKahjubj0)}(hhh]h)}(hdevice that owns thish]hdevice that owns this}(hjhhhNhNubah}(h]h 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reftargetj modnameN classnameNjj)}j]j c.fpga_image_info_allocasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjd)}(hdevh]hdev}(hj! hhhNhNubah}(h]h ]jpah"]h$]h&]uh1jchj ubeh}(h]h ]h"]h$]h&]noemphjCjDuh1j+hj ubah}(h]h ]h"]h$]h&]jCjDuh1j%hjL hhhj] hKmubeh}(h]h ]h"]h$]h&]jCjDjuh1jjjhjH hhhj] hKmubah}(h]jC ah ](jjeh"]h$]h&]jj)jhuh1jhj] hKmhjE hhubj)}(hhh]h)}(h"Allocate an FPGA image info structh]h"Allocate an FPGA image info struct}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1hhi/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-programming:103: ./drivers/fpga/fpga-mgr.chKhhjH hhubah}(h]h ]h"]h$]h&]uh1jhjE hhhj] hKmubeh}(h]h ](j{functioneh"]h$]h&]jj{jjc jjc jjjuh1jhhhjMhNhNubj)}(hb**Parameters** ``struct device *dev`` owning device **Return** struct fpga_image_info or NULLh](h)}(h**Parameters**h]j)}(hjm h]h Parameters}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk ubah}(h]h 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