sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget,/translations/zh_CN/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/zh_TW/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/it_IT/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ja_JP/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ko_KR/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/sp_SP/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h FPGA Managerh]h FPGA Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhF/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr.rsthKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXuThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it's just binary data. The FPGA manager core won't parse it.h]hXyThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it’s just binary data. The FPGA manager core won’t parse it.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.h]hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.h]hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h How to support a new FPGA deviceh]h How to support a new FPGA device}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hTo add another FPGA manager, write a driver that implements a set of ops. The probe function calls ``fpga_mgr_register()`` or ``fpga_mgr_register_full()``, such as::h](hdTo add another FPGA manager, write a driver that implements a set of ops. The probe function calls }(hj hhhNhNubhliteral)}(h``fpga_mgr_register()``h]hfpga_mgr_register()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh or }(hj hhhNhNubj)}(h``fpga_mgr_register_full()``h]hfpga_mgr_register_full()}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh , such as:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh literal_block)}(hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }h]hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }}hjCsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jAhhhKhhhhubh)}(hXrAlternatively, the probe function could call one of the resource managed register functions, ``devm_fpga_mgr_register()`` or ``devm_fpga_mgr_register_full()``. When these functions are used, the parameter syntax is the same, but the call to ``fpga_mgr_unregister()`` should be removed. In the above example, the ``socfpga_fpga_remove()`` function would not be required.h](h]Alternatively, the probe function could call one of the resource managed register functions, }(hjShhhNhNubj)}(h``devm_fpga_mgr_register()``h]hdevm_fpga_mgr_register()}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh or }(hjShhhNhNubj)}(h!``devm_fpga_mgr_register_full()``h]hdevm_fpga_mgr_register_full()}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubhT. When these functions are used, the parameter syntax is the same, but the call to }(hjShhhNhNubj)}(h``fpga_mgr_unregister()``h]hfpga_mgr_unregister()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh. should be removed. In the above example, the }(hjShhhNhNubj)}(h``socfpga_fpga_remove()``h]hsocfpga_fpga_remove()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh function would not be required.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKHhhhhubh)}(hThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.h]hThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhhhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe programming sequence is:: 1. .parse_header (optional, may be called once or multiple times) 2. .write_init 3. .write or .write_sg (may be called once or multiple times) 4. .write_complete h](hterm)}(hThe programming sequence is::h]hThe programming sequence is::}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKWhjubh definition)}(hhh]henumerated_list)}(hhh](h list_item)}(h>.parse_header (optional, may be called once or multiple times)h]h)}(hjh]h>.parse_header (optional, may be called once or multiple times)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h .write_inith]h)}(hjh]h .write_init}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h:.write or .write_sg (may be called once or multiple times)h]h)}(hjh]h:.write or .write_sg (may be called once or multiple times)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h.write_complete h]h)}(h.write_completeh]h.write_complete}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhhhhhNhNubh)}(hXThe .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.h]hXThe .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhhhhubh)}(hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.h]hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghhhhubh)}(hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.h]hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhhhhubh)}(hThe .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.h]hThe .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhhhhubh)}(hpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.h]hpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthhhhubh)}(hThe ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn't result in a change in state.h]hThe ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn’t result in a change in state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhhhhubeh}(h] how-to-support-a-new-fpga-deviceah ]h"] how to support a new fpga deviceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h.API for implementing a new FPGA Manager driverh]h.API for implementing a new FPGA Manager driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK|ubh bullet_list)}(hhh](j)}(h@``fpga_mgr_states`` - Values for :c:expr:`fpga_manager->state`.h]h)}(hjh](j)}(h``fpga_mgr_states``h]hfpga_mgr_states}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Values for }(hjhhhNhNubh desc_inline)}(hfpga_manager->stateh](h)}(hhh]h desc_sig_name)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]sbuh1hhjubhdesc_sig_operator)}(h->h]h->}(hjhhhNhNubah}(h]h ]oah"]h$]h&]uh1jhjubj)}(hstateh]hstate}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ](c-exprsig sig-inlinejeh"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h.struct fpga_manager - the FPGA manager structh]h)}(hjLh]h.struct fpga_manager - the FPGA manager struct}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjJubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hubj)}(hhh]h)}(hfirmware request failedh]hfirmware request failed}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhK(hjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhK(hjubj)}(h8``FPGA_MGR_STATE_PARSE_HEADER`` parse FPGA image header h](j)}(h``FPGA_MGR_STATE_PARSE_HEADER``h]j)}(hj}h]hFPGA_MGR_STATE_PARSE_HEADER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK+hjwubj)}(hhh]h)}(hparse FPGA image headerh]hparse FPGA image header}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK+hjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhK+hjubj)}(hD``FPGA_MGR_STATE_PARSE_HEADER_ERR`` Error during PARSE_HEADER stage h](j)}(h#``FPGA_MGR_STATE_PARSE_HEADER_ERR``h]j)}(hjh]hFPGA_MGR_STATE_PARSE_HEADER_ERR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK.hjubj)}(hhh]h)}(hError during PARSE_HEADER stageh]hError during PARSE_HEADER stage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK.hjubj)}(h=``FPGA_MGR_STATE_WRITE_INIT`` preparing FPGA for programming h](j)}(h``FPGA_MGR_STATE_WRITE_INIT``h]j)}(hjh]hFPGA_MGR_STATE_WRITE_INIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK1hjubj)}(hhh]h)}(hpreparing FPGA for programmingh]hpreparing FPGA for programming}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK1hjubj)}(h@``FPGA_MGR_STATE_WRITE_INIT_ERR`` Error during WRITE_INIT stage h](j)}(h!``FPGA_MGR_STATE_WRITE_INIT_ERR``h]j)}(hj(h]hFPGA_MGR_STATE_WRITE_INIT_ERR}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK4hj"ubj)}(hhh]h)}(hError during WRITE_INIT stageh]hError during WRITE_INIT stage}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hK4hj>ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hK4hjubj)}(h/``FPGA_MGR_STATE_WRITE`` writing image to FPGA h](j)}(h``FPGA_MGR_STATE_WRITE``h]j)}(hjah]hFPGA_MGR_STATE_WRITE}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK7hj[ubj)}(hhh]h)}(hwriting image to FPGAh]hwriting image to FPGA}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvhK7hjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhK7hjubj)}(h6``FPGA_MGR_STATE_WRITE_ERR`` Error while writing FPGA h](j)}(h``FPGA_MGR_STATE_WRITE_ERR``h]j)}(hjh]hFPGA_MGR_STATE_WRITE_ERR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK:hjubj)}(hhh]h)}(hError while writing FPGAh]hError while writing FPGA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK:hjubj)}(h?``FPGA_MGR_STATE_WRITE_COMPLETE`` Doing post programming steps h](j)}(h!``FPGA_MGR_STATE_WRITE_COMPLETE``h]j)}(hjh]hFPGA_MGR_STATE_WRITE_COMPLETE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK=hjubj)}(hhh]h)}(hDoing post programming stepsh]hDoing post programming steps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK=hjubj)}(hB``FPGA_MGR_STATE_WRITE_COMPLETE_ERR`` Error during WRITE_COMPLETE h](j)}(h%``FPGA_MGR_STATE_WRITE_COMPLETE_ERR``h]j)}(hj h]h!FPGA_MGR_STATE_WRITE_COMPLETE_ERR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK@hjubj)}(hhh]h)}(hError during WRITE_COMPLETEh]hError during WRITE_COMPLETE}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hK@hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj!hK@hjubj)}(h=``FPGA_MGR_STATE_OPERATING`` FPGA is programmed and operatingh](j)}(h``FPGA_MGR_STATE_OPERATING``h]j)}(hjEh]hFPGA_MGR_STATE_OPERATING}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhKBhj?ubj)}(hhh]h)}(h FPGA is programmed and operatingh]h FPGA is programmed and operating}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhKChj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhKBhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jqfpga_manager (C struct)c.fpga_managerhNtauh1jdhjhhhNhNubjv)}(hhh](j{)}(h fpga_managerh]j)}(hstruct fpga_managerh](j)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(h fpga_managerh]j)}(hjh]h fpga_manager}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhjhhhjhKubah}(h]jah ](j5jeh"]h$]h&]jj)jhuh1jzhjhKhjhhubj)}(hhh]h)}(hfpga manager structureh]hfpga manager structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1juhhhjhNhNubj)}(hX**Definition**:: struct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; }; **Members** ``name`` name of low level fpga manager ``dev`` fpga manager device ``ref_mutex`` only allows one reference to fpga manager ``state`` state of fpga manager ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to struct of fpga manager ops ``mops_owner`` module containing the mops ``priv`` low level driver private dateh](h)}(h**Definition**::h](j )}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjubjB)}(hstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };h]hstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };}hj sbah}(h]h ]h"]h$]h&]jQjRuh1jAhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjubh)}(h **Members**h]j )}(hj0 h]hMembers}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj. ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh](j)}(h(``name`` name of low level fpga manager h](j)}(h``name``h]j)}(hjO h]hname}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjI ubj)}(hhh]h)}(hname of low level fpga managerh]hname of low level fpga manager}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjd hKhje ubah}(h]h ]h"]h$]h&]uh1jhjI ubeh}(h]h ]h"]h$]h&]uh1jhjd hKhjF ubj)}(h``dev`` fpga manager device h](j)}(h``dev``h]j)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hfpga manager deviceh]hfpga manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubj)}(h8``ref_mutex`` only allows one reference to fpga manager h](j)}(h ``ref_mutex``h]j)}(hj h]h ref_mutex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h)only allows one reference to fpga managerh]h)only allows one reference to fpga manager}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubj)}(h ``state`` state of fpga manager h](j)}(h ``state``h]j)}(hj h]hstate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hstate of fpga managerh]hstate of fpga manager}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubj)}(h7``compat_id`` FPGA manager id for compatibility check. h](j)}(h ``compat_id``h]j)}(hj3 h]h compat_id}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1 ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj- ubj)}(hhh]h)}(h(FPGA manager id for compatibility check.h]h(FPGA manager id for compatibility check.}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjH hKhjI ubah}(h]h ]h"]h$]h&]uh1jhj- ubeh}(h]h ]h"]h$]h&]uh1jhjH hKhjF ubj)}(h/``mops`` pointer to struct of fpga manager ops h](j)}(h``mops``h]j)}(hjl h]hmops}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjf ubj)}(hhh]h)}(h%pointer to struct of fpga manager opsh]h%pointer to struct of fpga manager ops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjf ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubj)}(h*``mops_owner`` module containing the mops h](j)}(h``mops_owner``h]j)}(hj h]h mops_owner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hmodule containing the mopsh]hmodule containing the mops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubj)}(h&``priv`` low level driver private dateh](j)}(h``priv``h]j)}(hj h]hpriv}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hlow level driver private dateh]hlow level driver private date}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjF ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jqfpga_manager_ops (C struct)c.fpga_manager_opshNtauh1jdhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhNubjv)}(hhh](j{)}(hfpga_manager_opsh]j)}(hstruct fpga_manager_opsh](j)}(hjh]hstruct}(hj9 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5 hhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjG hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5 hhhjF hKubj)}(hfpga_manager_opsh]j)}(hj3 h]hfpga_manager_ops}(hjY hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU ubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhj5 hhhjF hKubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhj1 hhhjF hKubah}(h]j+ ah ](j5jeh"]h$]h&]jj)jhuh1jzhjF hKhj. hhubj)}(hhh]h)}(h&ops for low level fpga manager driversh]h&ops for low level fpga manager drivers}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjx hhubah}(h]h ]h"]h$]h&]uh1jhj. hhhjF hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1juhhhjhj- hNubj)}(hX**Definition**:: struct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; **Members** ``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. ``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. ``state`` returns an enum value of the FPGA's state ``status`` returns status of the FPGA, including reconfiguration error code ``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. ``write_init`` prepare the FPGA to receive configuration data ``write`` write count bytes of configuration data to the FPGA ``write_sg`` write the scatter list of configuration data to the FPGA ``write_complete`` set FPGA to operating state after writing is done ``fpga_remove`` optional: Set FPGA into a specific state during driver remove ``groups`` optional attribute groups.h](h)}(h**Definition**::h](j )}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubjB)}(hXstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };h]hXstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr,struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };}hj sbah}(h]h ]h"]h$]h&]jQjRuh1jAhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubh)}(h **Members**h]j )}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh](j)}(hh``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. h](j)}(h``initial_header_size``h]j)}(hj h]hinitial_header_size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hOminimum number of bytes that should be passed into parse_header and write_init.h]hOminimum number of bytes that should be passed into parse_header and write_init.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. h](j)}(h``skip_header``h]j)}(hj" h]h skip_header}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hbool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.h]hbool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj8 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj7 hKhj ubj)}(h4``state`` returns an enum value of the FPGA's state h](j)}(h ``state``h]j)}(hj\ h]hstate}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjV ubj)}(hhh]h)}(h)returns an enum value of the FPGA's stateh]h+returns an enum value of the FPGA’s state}(hju hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjq hKhjr ubah}(h]h ]h"]h$]h&]uh1jhjV ubeh}(h]h ]h"]h$]h&]uh1jhjq hKhj ubj)}(hL``status`` returns status of the FPGA, including reconfiguration error code h](j)}(h ``status``h]j)}(hj h]hstatus}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h@returns status of the FPGA, including reconfiguration error codeh]h@returns status of the FPGA, including reconfiguration error code}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. h](j)}(h``parse_header``h]j)}(hj h]h parse_header}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hparse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.h]hparse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h>``write_init`` prepare the FPGA to receive configuration data h](j)}(h``write_init``h]j)}(hj h]h write_init}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h.prepare the FPGA to receive configuration datah]h.prepare the FPGA to receive configuration data}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h>``write`` write count bytes of configuration data to the FPGA h](j)}(h ``write``h]j)}(hjA h]hwrite}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj? ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj; ubj)}(hhh]h)}(h3write count bytes of configuration data to the FPGAh]h3write count bytes of configuration data to the FPGA}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjV hKhjW ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jhjV hKhj ubj)}(hF``write_sg`` write the scatter list of configuration data to the FPGA h](j)}(h ``write_sg``h]j)}(hjz h]hwrite_sg}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjt ubj)}(hhh]h)}(h8write the scatter list of configuration data to the FPGAh]h8write the scatter list of configuration data to the FPGA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjt ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hE``write_complete`` set FPGA to operating state after writing is done h](j)}(h``write_complete``h]j)}(hj h]hwrite_complete}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h1set FPGA to operating state after writing is doneh]h1set FPGA to operating state after writing is done}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hN``fpga_remove`` optional: Set FPGA into a specific state during driver remove h](j)}(h``fpga_remove``h]j)}(hj h]h fpga_remove}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h=optional: Set FPGA into a specific state during driver removeh]h=optional: Set FPGA into a specific state during driver remove}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h%``groups`` optional attribute groups.h](j)}(h ``groups``h]j)}(hj%h]hgroups}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(hoptional attribute groups.h]hoptional attribute groups.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj:hKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhj- hNubh)}(h**Description**h]j )}(hjhh]h Description}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjhhubh)}(hfpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.h]hfpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjhhubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jqfpga_manager_info (C struct)c.fpga_manager_infohNtauh1jdhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhNubjv)}(hhh](j{)}(hfpga_manager_infoh]j)}(hstruct fpga_manager_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hfpga_manager_infoh]j)}(hjh]hfpga_manager_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhjhhhjhKubah}(h]jah ](j5jeh"]h$]h&]jj)jhuh1jzhjhKhjhhubj)}(hhh]h)}(h,collection of parameters for an FPGA Managerh]h,collection of parameters for an FPGA Manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1juhhhjhjhNubj)}(hXp**Definition**:: struct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; }; **Members** ``name`` fpga manager name ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to structure of fpga manager ops ``priv`` fpga manager private datah](h)}(h**Definition**::h](j )}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubjB)}(hstruct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };h]hstruct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };}hj&sbah}(h]h ]h"]h$]h&]jQjRuh1jAhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubh)}(h **Members**h]j )}(hj7h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh](j)}(h``name`` fpga manager name h](j)}(h``name``h]j)}(hjVh]hname}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjPubj)}(hhh]h)}(hfpga manager nameh]hfpga manager name}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhKhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjkhKhjMubj)}(h7``compat_id`` FPGA manager id for compatibility check. h](j)}(h ``compat_id``h]j)}(hjh]h compat_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(h(FPGA manager id for compatibility check.h]h(FPGA manager id for compatibility check.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjMubj)}(h2``mops`` pointer to structure of fpga manager ops h](j)}(h``mops``h]j)}(hjh]hmops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(h(pointer to structure of fpga manager opsh]h(pointer to structure of fpga manager ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjMubj)}(h"``priv`` fpga manager private datah](j)}(h``priv``h]j)}(hjh]hpriv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(hfpga manager private datah]hfpga manager private data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjMubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjhNubh)}(h**Description**h]j )}(hjDh]h Description}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubh)}(hfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.h]hfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jq%__fpga_mgr_register_full (C function)c.__fpga_mgr_register_fullhNtauh1jdhjhhhNhNubjv)}(hhh](j{)}(hstruct fpga_manager * __fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)Ch]j)}(hstruct fpga_manager *__fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhjhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]j  ASTIdentifier)}j__fpga_mgr_register_fullsbc.__fpga_mgr_register_fullasbuh1hhj~hhhjhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~hhhjhMubhdesc_sig_punctuation)}(hj h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj~hhhjhMubj)}(h__fpga_mgr_register_fullh]j)}(hjh]h__fpga_mgr_register_full}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhj~hhhjhMubhdesc_parameterlist)}(hS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](hdesc_parameter)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%modnameN classnameNj j )}j]jc.__fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(h$const struct fpga_manager_info *infoh](j)}(hconsth]hconst}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubh)}(hhh]j)}(hfpga_manager_infoh]hfpga_manager_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]jc.__fpga_mgr_register_fullasbuh1hhjqubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj!modnameN classnameNj j )}j]jc.__fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubeh}(h]h ]h"]h$]h&]jQjRuh1jhj~hhhjhMubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhjzhhhjhMubah}(h]juah ](j5jeh"]h$]h&]jj)jhuh1jzhjhMhjwhhubj)}(hhh]h)}(h*create and register an FPGA Manager deviceh]h*create and register an FPGA Manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1juhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const struct fpga_manager_info *info`` parameters for fpga manager ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended. **Return** pointer to struct fpga_manager pointer or ERR_PTR()h](h)}(h**Parameters**h]j )}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hE``const struct fpga_manager_info *info`` parameters for fpga manager h](j)}(h(``const struct fpga_manager_info *info``h]j)}(hjh]h$const struct fpga_manager_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubj)}(hhh]h)}(hparameters for fpga managerh]hparameters for fpga manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j)}(hj5h]hstruct module *owner}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hj/ubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhM hjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j )}(hjph]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubh)}(hThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.h]hThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubh)}(h **Return**h]j )}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjubh)}(h3pointer to struct fpga_manager pointer or ERR_PTR()h]h3pointer to struct fpga_manager pointer or ERR_PTR()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jq __fpga_mgr_register (C function)c.__fpga_mgr_registerhNtauh1jdhjhhhNhNubjv)}(hhh](j{)}(hstruct fpga_manager * __fpga_mgr_register (struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h]j)}(hstruct fpga_manager *__fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMiubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMiubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]j)}j__fpga_mgr_registersbc.__fpga_mgr_registerasbuh1hhjhhhjhMiubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMiubj)}(hj h]h*}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMiubj)}(h__fpga_mgr_registerh]j)}(hjh]h__fpga_mgr_register}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhjhhhjhMiubj)}(hp(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubh)}(hhh]j)}(hdeviceh]hdevice}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNj j )}j]jc.__fpga_mgr_registerasbuh1hhjRubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hparenth]hparent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjNubj)}(hconst char *nameh](j)}(hjwh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_keyword_type)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hnameh]hname}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjNubj)}(h#const struct fpga_manager_ops *mopsh](j)}(hjwh]hconst}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubh)}(hhh]j)}(hfpga_manager_opsh]hfpga_manager_ops}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNj j )}j]jc.__fpga_mgr_registerasbuh1hhj"ubj)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubj)}(hmopsh]hmops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjNubj)}(h void *privh](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjNubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]jc.__fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjNubeh}(h]h ]h"]h$]h&]jQjRuh1jhjhhhjhMiubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhjhhhjhMiubah}(h]jah ](j5jeh"]h$]h&]jj)jhuh1jzhjhMihjhhubj)}(hhh]h)}(h*create and register an FPGA Manager deviceh]h*create and register an FPGA Manager device}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMZhjqhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMiubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1juhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const char *name`` fpga manager name ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ``void *priv`` fpga manager private data ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters. **Return** pointer to struct fpga_manager pointer or ERR_PTR()h](h)}(h**Parameters**h]j )}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM^hjubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM[hjubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM[hjubj)}(h'``const char *name`` fpga manager name h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM\hjubj)}(hhh]h)}(hfpga manager nameh]hfpga manager name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM\hjubj)}(hQ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops h](j)}(h'``const struct fpga_manager_ops *mops``h]j)}(hj'h]h#const struct fpga_manager_ops *mops}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM]hj!ubj)}(hhh]h)}(h(pointer to structure of fpga manager opsh]h(pointer to structure of fpga manager ops}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hM]hj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj<hM]hjubj)}(h)``void *priv`` fpga manager private data h](j)}(h``void *priv``h]j)}(hj`h]h void *priv}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM^hjZubj)}(hhh]h)}(hfpga manager private datah]hfpga manager private data}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhM^hjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjuhM^hjubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM_hjubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM_hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j )}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMahjubh)}(hXFThe caller of this function is responsible for calling fpga_mgr_unregister(). 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The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMahjubh)}(h **Return**h]j )}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMghjubh)}(h3pointer to struct fpga_manager pointer or ERR_PTR()h]h3pointer to struct fpga_manager pointer or ERR_PTR()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMghjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jq*__devm_fpga_mgr_register_full (C function)c.__devm_fpga_mgr_register_fullhNtauh1jdhjhhhNhNubjv)}(hhh](j{)}(hstruct fpga_manager * __devm_fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)h]j)}(hstruct fpga_manager *__devm_fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hjh]hstruct}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhjMhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNj j )}j]j)}j__devm_fpga_mgr_register_fullsbc.__devm_fpga_mgr_register_fullasbuh1hhj<hhhjMhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhjMhMubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<hhhjMhMubj)}(h__devm_fpga_mgr_register_fullh]j)}(hj}h]h__devm_fpga_mgr_register_full}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhj<hhhjMhMubj)}(hS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]j{c.__devm_fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(h$const struct fpga_manager_info *infoh](j)}(hjwh]hconst}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubh)}(hhh]j)}(hfpga_manager_infoh]hfpga_manager_info}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjemodnameN classnameNj j )}j]j{c.__devm_fpga_mgr_register_fullasbuh1hhj&ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]j{c.__devm_fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubeh}(h]h ]h"]h$]h&]jQjRuh1jhj<hhhjMhMubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhj8hhhjMhMubah}(h]j3ah ](j5jeh"]h$]h&]jj)jhuh1jzhjMhMhj5hhubj)}(hhh]h)}(h/resource managed variant of fpga_mgr_register()h]h/resource managed variant of fpga_mgr_register()}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhj3hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhjMhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjNjjNjjjuh1juhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const struct fpga_manager_info *info`` parameters for fpga manager ``struct module *owner`` owner module containing the ops **Return** fpga manager pointer on success, negative error code otherwise. **Description** This is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.h](h)}(h**Parameters**h]j )}(hjXh]h Parameters}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjRubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev 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*owner``h]j)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjnubeh}(h]h ]h"]h$]h&]uh1jhjRubh)}(h **Return**h]j )}(hj$h]hReturn}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjRubh)}(h?fpga manager pointer on success, negative error code otherwise.h]h?fpga manager pointer on success, negative error code otherwise.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjRubh)}(h**Description**h]j )}(hjKh]h Description}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjRubh)}(hThis is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.h]hThis is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubje)}(hhh]h}(h]h ]h"]h$]h&]entries](jq%__devm_fpga_mgr_register (C function)c.__devm_fpga_mgr_registerhNtauh1jdhjhhhNhNubjv)}(hhh](j{)}(hstruct fpga_manager * __devm_fpga_mgr_register (struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h]j)}(hstruct fpga_manager *__devm_fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]j)}j__devm_fpga_mgr_registersbc.__devm_fpga_mgr_registerasbuh1hhjhhhjhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(h__devm_fpga_mgr_registerh]j)}(hjh]h__devm_fpga_mgr_register}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jQjRuh1jhjhhhjhMubj)}(hp(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj*modnameN classnameNj j )}j]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(hconst char *nameh](j)}(hjwh]hconst}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubj)}(hnameh]hname}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(h#const struct fpga_manager_ops *mopsh](j)}(hjwh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hfpga_manager_opsh]hfpga_manager_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hmopsh]hmops}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(h void *privh](j)}(hvoidh]hvoid}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(hj h]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNj j )}j]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjQjRuh1jhjubeh}(h]h ]h"]h$]h&]jQjRuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]jQjRjuh1jjjhjhhhjhMubah}(h]jah ](j5jeh"]h$]h&]jj)jhuh1jzhjhMhjhhubj)}(hhh]h)}(h/resource managed variant of fpga_mgr_register()h]h/resource managed variant of fpga_mgr_register()}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhj"hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj=jj=jjjuh1juhhhjhNhNubj)}(hX%**Parameters** ``struct device *parent`` fpga manager device from pdev ``const char *name`` fpga manager name ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ``void 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