sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget,/translations/zh_CN/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/zh_TW/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/it_IT/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ja_JP/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/ko_KR/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/pt_BR/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget,/translations/sp_SP/driver-api/fpga/fpga-mgrmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h FPGA Managerh]h FPGA Manager}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhF/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr.rsthKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXuThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it's just binary data. The FPGA manager core won't parse it.h]hXyThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it’s just binary data. The FPGA manager core won’t parse it.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.h]hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.h]hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h How to support a new FPGA deviceh]h How to support a new FPGA device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hTo add another FPGA manager, write a driver that implements a set of ops. The probe function calls ``fpga_mgr_register()`` or ``fpga_mgr_register_full()``, such as::h](hdTo add another FPGA manager, write a driver that implements a set of ops. The probe function calls }(hj!hhhNhNubhliteral)}(h``fpga_mgr_register()``h]hfpga_mgr_register()}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubh or }(hj!hhhNhNubj*)}(h``fpga_mgr_register_full()``h]hfpga_mgr_register_full()}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubh , such as:}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh literal_block)}(hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }h]hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }}hjWsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jUhhhKhjhhubh)}(hXrAlternatively, the probe function could call one of the resource managed register functions, ``devm_fpga_mgr_register()`` or ``devm_fpga_mgr_register_full()``. When these functions are used, the parameter syntax is the same, but the call to ``fpga_mgr_unregister()`` should be removed. In the above example, the ``socfpga_fpga_remove()`` function would not be required.h](h]Alternatively, the probe function could call one of the resource managed register functions, }(hjghhhNhNubj*)}(h``devm_fpga_mgr_register()``h]hdevm_fpga_mgr_register()}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgubh or }(hjghhhNhNubj*)}(h!``devm_fpga_mgr_register_full()``h]hdevm_fpga_mgr_register_full()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgubhT. When these functions are used, the parameter syntax is the same, but the call to }(hjghhhNhNubj*)}(h``fpga_mgr_unregister()``h]hfpga_mgr_unregister()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgubh. should be removed. In the above example, the }(hjghhhNhNubj*)}(h``socfpga_fpga_remove()``h]hsocfpga_fpga_remove()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjgubh function would not be required.}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubh)}(hThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.h]hThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe programming sequence is:: 1. .parse_header (optional, may be called once or multiple times) 2. .write_init 3. .write or .write_sg (may be called once or multiple times) 4. .write_complete h](hterm)}(hThe programming sequence is::h]hThe programming sequence is::}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKWhjubh definition)}(hhh]henumerated_list)}(hhh](h list_item)}(h>.parse_header (optional, may be called once or multiple times)h]h)}(hjh]h>.parse_header (optional, may be called once or multiple times)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h .write_inith]h)}(hj h]h .write_init}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h:.write or .write_sg (may be called once or multiple times)h]h)}(hj"h]h:.write or .write_sg (may be called once or multiple times)}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKVhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h.write_complete h]h)}(h.write_completeh]h.write_complete}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubh)}(hXThe .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.h]hXThe .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjhhubh)}(hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.h]hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjhhubh)}(hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.h]hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjhhubh)}(hThe .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.h]hThe .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjhhubh)}(hpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.h]hpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjhhubh)}(hThe ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn't result in a change in state.h]hThe ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn’t result in a change in state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjhhubeh}(h] how-to-support-a-new-fpga-deviceah ]h"] how to support a new fpga deviceah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h.API for implementing a new FPGA Manager driverh]h.API for implementing a new FPGA Manager driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK|ubh bullet_list)}(hhh](j)}(h@``fpga_mgr_states`` - Values for :c:expr:`fpga_manager->state`.h]h)}(hjh](j*)}(h``fpga_mgr_states``h]hfpga_mgr_states}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubh - Values for }(hjhhhNhNubh desc_inline)}(hfpga_manager->stateh](h)}(hhh]h desc_sig_name)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]sbuh1hhjubhdesc_sig_operator)}(h->h]h->}(hj(hhhNhNubah}(h]h ]oah"]h$]h&]uh1j&hjubj)}(hstateh]hstate}(hj7hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ](c-exprsig sig-inlinejeh"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h.struct fpga_manager - the FPGA manager structh]h)}(hj`h]h.struct fpga_manager - the FPGA manager struct}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj^ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj:ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK4hj6ubj)}(hhh]h)}(hError during WRITE_INIT stageh]hError during WRITE_INIT stage}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhK4hjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhjQhK4hj2ubj)}(h/``FPGA_MGR_STATE_WRITE`` writing image to FPGA h](j)}(h``FPGA_MGR_STATE_WRITE``h]j*)}(hjuh]hFPGA_MGR_STATE_WRITE}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjsubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK7hjoubj)}(hhh]h)}(hwriting image to FPGAh]hwriting image to FPGA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK7hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjhK7hj2ubj)}(h6``FPGA_MGR_STATE_WRITE_ERR`` Error while writing FPGA h](j)}(h``FPGA_MGR_STATE_WRITE_ERR``h]j*)}(hjh]hFPGA_MGR_STATE_WRITE_ERR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK:hjubj)}(hhh]h)}(hError while writing FPGAh]hError while writing FPGA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK:hj2ubj)}(h?``FPGA_MGR_STATE_WRITE_COMPLETE`` Doing post programming steps h](j)}(h!``FPGA_MGR_STATE_WRITE_COMPLETE``h]j*)}(hjh]hFPGA_MGR_STATE_WRITE_COMPLETE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK=hjubj)}(hhh]h)}(hDoing post programming stepsh]hDoing post programming steps}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK=hj2ubj)}(hB``FPGA_MGR_STATE_WRITE_COMPLETE_ERR`` Error during WRITE_COMPLETE h](j)}(h%``FPGA_MGR_STATE_WRITE_COMPLETE_ERR``h]j*)}(hj h]h!FPGA_MGR_STATE_WRITE_COMPLETE_ERR}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhK@hjubj)}(hhh]h)}(hError during WRITE_COMPLETEh]hError during WRITE_COMPLETE}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hK@hj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hK@hj2ubj)}(h=``FPGA_MGR_STATE_OPERATING`` FPGA is programmed and operatingh](j)}(h``FPGA_MGR_STATE_OPERATING``h]j*)}(hjYh]hFPGA_MGR_STATE_OPERATING}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjWubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhKBhjSubj)}(hhh]h)}(h FPGA is programmed and operatingh]h FPGA is programmed and operating}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.hhKChjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjnhKBhj2ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_manager (C struct)c.fpga_managerhNtauh1jxhjhhhNhNubj)}(hhh](j)}(h fpga_managerh]j)}(hstruct fpga_managerh](j)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(h fpga_managerh]j)}(hjh]h fpga_manager}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhjhKubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(hfpga manager structureh]hfpga manager structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j jj j jj jjjuh1jhhhjhNhNubj)}(hX**Definition**:: struct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; }; **Members** ``name`` name of low level fpga manager ``dev`` fpga manager device ``ref_mutex`` only allows one reference to fpga manager ``state`` state of fpga manager ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to struct of fpga manager ops ``mops_owner`` module containing the mops ``priv`` low level driver private dateh](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubjV)}(hstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };h]hstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };}hj3 sbah}(h]h ]h"]h$]h&]jejfuh1jUhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubh)}(h **Members**h]j)}(hjD h]hMembers}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh](j)}(h(``name`` name of low level fpga manager h](j)}(h``name``h]j*)}(hjc h]hname}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hja ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj] ubj)}(hhh]h)}(hname of low level fpga managerh]hname of low level fpga manager}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx hKhjy ubah}(h]h ]h"]h$]h&]uh1jhj] ubeh}(h]h ]h"]h$]h&]uh1jhjx hKhjZ ubj)}(h``dev`` fpga manager device h](j)}(h``dev``h]j*)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hfpga manager deviceh]hfpga manager device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjZ ubj)}(h8``ref_mutex`` only allows one reference to fpga manager h](j)}(h ``ref_mutex``h]j*)}(hj h]h ref_mutex}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h)only allows one reference to fpga managerh]h)only allows one reference to fpga manager}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjZ ubj)}(h ``state`` state of fpga manager h](j)}(h ``state``h]j*)}(hj h]hstate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hstate of fpga managerh]hstate of fpga manager}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj# hKhj$ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj# hKhjZ ubj)}(h7``compat_id`` FPGA manager id for compatibility check. h](j)}(h ``compat_id``h]j*)}(hjG h]h compat_id}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjE ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjA ubj)}(hhh]h)}(h(FPGA manager id for compatibility check.h]h(FPGA manager id for compatibility check.}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ hKhj] ubah}(h]h ]h"]h$]h&]uh1jhjA ubeh}(h]h ]h"]h$]h&]uh1jhj\ hKhjZ ubj)}(h/``mops`` pointer to struct of fpga manager ops h](j)}(h``mops``h]j*)}(hj h]hmops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj~ ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhjz ubj)}(hhh]h)}(h%pointer to struct of fpga manager opsh]h%pointer to struct of fpga manager ops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjz ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjZ ubj)}(h*``mops_owner`` module containing the mops h](j)}(h``mops_owner``h]j*)}(hj h]h mops_owner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hmodule containing the mopsh]hmodule containing the mops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjZ ubj)}(h&``priv`` low level driver private dateh](j)}(h``priv``h]j*)}(hj h]hpriv}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hlow level driver private dateh]hlow level driver private date}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhjZ ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_manager_ops (C struct)c.fpga_manager_opshNtauh1jxhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhNubj)}(hhh](j)}(hfpga_manager_opsh]j)}(hstruct fpga_manager_opsh](j)}(hjh]hstruct}(hjM hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI hhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hj[ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI hhhjZ hKubj)}(hfpga_manager_opsh]j)}(hjG h]hfpga_manager_ops}(hjm hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhji ubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjI hhhjZ hKubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjE hhhjZ hKubah}(h]j? ah ](jIjeh"]h$]h&]jj)jhuh1jhjZ hKhjB hhubj)}(hhh]h)}(h&ops for low level fpga manager driversh]h&ops for low level fpga manager drivers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj hhubah}(h]h ]h"]h$]h&]uh1jhjB hhhjZ hKubeh}(h]h ](jstructeh"]h$]h&]j jj j jj jjjuh1jhhhjhjA hNubj)}(hX**Definition**:: struct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; **Members** ``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. ``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. ``state`` returns an enum value of the FPGA's state ``status`` returns status of the FPGA, including reconfiguration error code ``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. ``write_init`` prepare the FPGA to receive configuration data ``write`` write count bytes of configuration data to the FPGA ``write_sg`` write the scatter list of configuration data to the FPGA ``write_complete`` set FPGA to operating state after writing is done ``fpga_remove`` optional: Set FPGA into a specific state during driver remove ``groups`` optional attribute groups.h](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubjV)}(hXstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };h]hXstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };}hj sbah}(h]h ]h"]h$]h&]jejfuh1jUhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubh)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh](j)}(hh``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. h](j)}(h``initial_header_size``h]j*)}(hj h]hinitial_header_size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hOminimum number of bytes that should be passed into parse_header and write_init.h]hOminimum number of bytes that should be passed into parse_header and write_init.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. h](j)}(h``skip_header``h]j*)}(hj6 h]h skip_header}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj4 ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj0 ubj)}(hhh]h)}(hbool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.h]hbool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjL ubah}(h]h ]h"]h$]h&]uh1jhj0 ubeh}(h]h ]h"]h$]h&]uh1jhjK hKhj ubj)}(h4``state`` returns an enum value of the FPGA's state h](j)}(h ``state``h]j*)}(hjp h]hstate}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjn ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjj ubj)}(hhh]h)}(h)returns an enum value of the FPGA's stateh]h+returns an enum value of the FPGA’s state}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hL``status`` returns status of the FPGA, including reconfiguration error code h](j)}(h ``status``h]j*)}(hj h]hstatus}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h@returns status of the FPGA, including reconfiguration error codeh]h@returns status of the FPGA, including reconfiguration error code}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. h](j)}(h``parse_header``h]j*)}(hj h]h parse_header}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(hparse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.h]hparse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(h>``write_init`` prepare the FPGA to receive configuration data h](j)}(h``write_init``h]j*)}(hj h]h write_init}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h.prepare the FPGA to receive configuration datah]h.prepare the FPGA to receive configuration data}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1 hKhj2 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj1 hKhj ubj)}(h>``write`` write count bytes of configuration data to the FPGA h](j)}(h ``write``h]j*)}(hjU h]hwrite}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjS ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjO ubj)}(hhh]h)}(h3write count bytes of configuration data to the FPGAh]h3write count bytes of configuration data to the FPGA}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj hKhjk ubah}(h]h ]h"]h$]h&]uh1jhjO ubeh}(h]h ]h"]h$]h&]uh1jhjj hKhj ubj)}(hF``write_sg`` write the scatter list of configuration data to the FPGA h](j)}(h ``write_sg``h]j*)}(hj h]hwrite_sg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h8write the scatter list of configuration data to the FPGAh]h8write the scatter list of configuration data to the FPGA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hE``write_complete`` set FPGA to operating state after writing is done h](j)}(h``write_complete``h]j*)}(hj h]hwrite_complete}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h1set FPGA to operating state after writing is doneh]h1set FPGA to operating state after writing is done}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hKhj ubj)}(hN``fpga_remove`` optional: Set FPGA into a specific state during driver remove h](j)}(h``fpga_remove``h]j*)}(hjh]h fpga_remove}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj ubj)}(hhh]h)}(h=optional: Set FPGA into a specific state during driver removeh]h=optional: Set FPGA into a specific state during driver remove}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjhKhj ubj)}(h%``groups`` optional attribute groups.h](j)}(h ``groups``h]j*)}(hj9h]hgroups}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj7ubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhj3ubj)}(hhh]h)}(hoptional attribute groups.h]hoptional attribute groups.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjA hNubh)}(h**Description**h]j)}(hj|h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjhhubh)}(hfpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.h]hfpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.hhKhjhhubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](jfpga_manager_info (C struct)c.fpga_manager_infohNtauh1jxhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhNubj)}(hhh](j)}(hfpga_manager_infoh]j)}(hstruct fpga_manager_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hfpga_manager_infoh]j)}(hjh]hfpga_manager_info}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhjhKubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhjhKhjhhubj)}(hhh]h)}(h,collection of parameters for an FPGA Managerh]h,collection of parameters for an FPGA Manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]j jj jjjjjjuh1jhhhjhjhNubj)}(hXp**Definition**:: struct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; }; **Members** ``name`` fpga manager name ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to structure of fpga manager ops ``priv`` fpga manager private datah](h)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubjV)}(hstruct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };h]hstruct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };}hj:sbah}(h]h ]h"]h$]h&]jejfuh1jUhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubh)}(h **Members**h]j)}(hjKh]hMembers}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh](j)}(h``name`` fpga manager name h](j)}(h``name``h]j*)}(hjjh]hname}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjhubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjdubj)}(hhh]h)}(hfpga manager nameh]hfpga manager name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhKhjaubj)}(h7``compat_id`` FPGA manager id for compatibility check. h](j)}(h ``compat_id``h]j*)}(hjh]h compat_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(h(FPGA manager id for compatibility check.h]h(FPGA manager id for compatibility check.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjaubj)}(h2``mops`` pointer to structure of fpga manager ops h](j)}(h``mops``h]j*)}(hjh]hmops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(h(pointer to structure of fpga manager opsh]h(pointer to structure of fpga manager ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjaubj)}(h"``priv`` fpga manager private datah](j)}(h``priv``h]j*)}(hjh]hpriv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjubj)}(hhh]h)}(hfpga manager private datah]hfpga manager private data}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hKhjaubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhjhNubh)}(h**Description**h]j)}(hjXh]h Description}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubh)}(hfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.h]hfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.hhKhjhhubjy)}(hhh]h}(h]h ]h"]h$]h&]entriesf](j%__fpga_mgr_register_full (C function)c.__fpga_mgr_register_fullhNtauh1jxhjhhhNhNubj)}(hhh](j)}(hstruct fpga_manager * __fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)h]j)}(hstruct fpga_manager *__fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]j ASTIdentifier)}j__fpga_mgr_register_fullsbc.__fpga_mgr_register_fullasbuh1hhjhhhjhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubhdesc_sig_punctuation)}(hj!h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjhhhjhMubj)}(h__fpga_mgr_register_fullh]j)}(hjh]h__fpga_mgr_register_full}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjhhhjhMubhdesc_parameterlist)}(hS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](hdesc_parameter)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hj7hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj9modnameN classnameNjj!)}j$]jc.__fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hjphhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(h$const struct fpga_manager_info *infoh](j)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hfpga_manager_infoh]hfpga_manager_info}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]jc.__fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hj3hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj5modnameN classnameNjj!)}j$]jc.__fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjlhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubeh}(h]h ]h"]h$]h&]jejfuh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhjhMubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h*create and register an FPGA Manager deviceh]h*create and register an FPGA Manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const struct fpga_manager_info *info`` parameters for fpga manager ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended. **Return** pointer to struct fpga_manager pointer or ERR_PTR()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j*)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hE``const struct fpga_manager_info *info`` parameters for fpga manager h](j)}(h(``const struct fpga_manager_info *info``h]j*)}(hjh]h$const struct fpga_manager_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hj ubj)}(hhh]h)}(hparameters for fpga managerh]hparameters for fpga manager}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hM hj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj%hM hjubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j*)}(hjIh]hstruct module *owner}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjGubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjCubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hM hj_ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhj^hM hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubh)}(hThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.h]hThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chM hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjubh)}(h3pointer to struct fpga_manager pointer or ERR_PTR()h]h3pointer to struct fpga_manager pointer or ERR_PTR()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](j __fpga_mgr_register (C function)c.__fpga_mgr_registerhNtauh1jxhjhhhNhNubj)}(hhh](j)}(hstruct fpga_manager * __fpga_mgr_register (struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h]j)}(hstruct fpga_manager *__fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMZubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMZubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]j)}j__fpga_mgr_registersbc.__fpga_mgr_registerasbuh1hhjhhhjhMZubj)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMZubj)}(hj!h]h*}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMZubj)}(h__fpga_mgr_registerh]j)}(hj-h]h__fpga_mgr_register}(hjOhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjKubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjhhhjhMZubj)}(hp(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]j+c.__fpga_mgr_registerasbuh1hhjfubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj)}(hparenth]hparent}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjbubj)}(hconst char *nameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_keyword_type)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hnameh]hname}(hj!hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjbubj)}(h#const struct fpga_manager_ops *mopsh](j)}(hjh]hconst}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hjh]hstruct}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubh)}(hhh]j)}(hfpga_manager_opsh]hfpga_manager_ops}(hjshhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj!)}j$]j+c.__fpga_mgr_registerasbuh1hhj6ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubj)}(hmopsh]hmops}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjbubj)}(h void *privh](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjbubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hj%hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj'modnameN classnameNjj!)}j$]j+c.__fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hj^hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjbubeh}(h]h ]h"]h$]h&]jejfuh1j hjhhhjhMZubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhjhMZubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhjhMZhjhhubj)}(hhh]h)}(h*create and register an FPGA Manager deviceh]h*create and register an FPGA Manager device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMZhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMZubeh}(h]h ](jfunctioneh"]h$]h&]j jj jjjjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const char *name`` fpga manager name ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ``void *priv`` fpga manager private data ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters. **Return** pointer to struct fpga_manager pointer or ERR_PTR()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM^hjubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j*)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM[hjubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM[hjubj)}(h'``const char *name`` fpga manager name h](j)}(h``const char *name``h]j*)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM\hjubj)}(hhh]h)}(hfpga manager nameh]hfpga manager name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM\hjubj)}(hQ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops h](j)}(h'``const struct fpga_manager_ops *mops``h]j*)}(hj;h]h#const struct fpga_manager_ops *mops}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj9ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM]hj5ubj)}(hhh]h)}(h(pointer to structure of fpga manager opsh]h(pointer to structure of fpga manager ops}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhM]hjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhjPhM]hjubj)}(h)``void *priv`` fpga manager private data h](j)}(h``void *priv``h]j*)}(hjth]h void *priv}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjrubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM^hjnubj)}(hhh]h)}(hfpga manager private datah]hfpga manager private data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM^hjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhM^hjubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j*)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM_hjubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhM_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM_hjubeh}(h]h ]h"]h$]h&]uh1jhjubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMahjubh)}(hXFThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters.h]hXFThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chM`hjubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMfhjubh)}(h3pointer to struct fpga_manager pointer or ERR_PTR()h]h3pointer to struct fpga_manager pointer or ERR_PTR()}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.chMghjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](j*__devm_fpga_mgr_register_full (C function)c.__devm_fpga_mgr_register_fullhNtauh1jxhjhhhNhNubj)}(hhh](j)}(hstruct fpga_manager * __devm_fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)h]j)}(hstruct fpga_manager *__devm_fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjahMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjshhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj!)}j$]j)}j__devm_fpga_mgr_register_fullsbc.__devm_fpga_mgr_register_fullasbuh1hhjPhhhjahMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjahMubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPhhhjahMubj)}(h__devm_fpga_mgr_register_fullh]j)}(hjh]h__devm_fpga_mgr_register_full}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjPhhhjahMubj)}(hS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hj%hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(h$const struct fpga_manager_info *infoh](j)}(hjh]hconst}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(h h]h }(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hjh]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubh)}(hhh]j)}(hfpga_manager_infoh]hfpga_manager_info}(hjwhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjymodnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_register_fullasbuh1hhj:ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_register_fullasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubeh}(h]h ]h"]h$]h&]jejfuh1j hjPhhhjahMubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjLhhhjahMubah}(h]jGah ](jIjeh"]h$]h&]jj)jhuh1jhjahMhjIhhubj)}(hhh]h)}(h/resource managed variant of fpga_mgr_register()h]h/resource managed variant of fpga_mgr_register()}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjGhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjahMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jbjjbjjjuh1jhhhjhNhNubj)}(hX**Parameters** ``struct device *parent`` fpga manager device from pdev ``const struct fpga_manager_info *info`` parameters for fpga manager ``struct module *owner`` owner module containing the ops **Return** fpga manager pointer on success, negative error code otherwise. **Description** This is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.h](h)}(h**Parameters**h]j)}(hjlh]h Parameters}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjfubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j*)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``const struct fpga_manager_info *info`` parameters for fpga manager h](j)}(h(``const struct fpga_manager_info *info``h]j*)}(hjh]h$const struct fpga_manager_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(hparameters for fpga managerh]hparameters for fpga manager}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j*)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjfubh)}(h **Return**h]j)}(hj8h]hReturn}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjfubh)}(h?fpga manager pointer on success, negative error code otherwise.h]h?fpga manager pointer on success, negative error code otherwise.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjfubh)}(h**Description**h]j)}(hj_h]h Description}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjfubh)}(hThis is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.h]hThis is the devres variant of fpga_mgr_register_full() for which the unregister function will be called automatically when the managing device is detached.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.chMhjfubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](j%__devm_fpga_mgr_register (C function)c.__devm_fpga_mgr_registerhNtauh1jxhjhhhNhNubj)}(hhh](j)}(hstruct fpga_manager * __devm_fpga_mgr_register (struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h]j)}(hstruct fpga_manager *__devm_fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]j)}j__devm_fpga_mgr_registersbc.__devm_fpga_mgr_registerasbuh1hhjhhhjhMubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMubj)}(h__devm_fpga_mgr_registerh]j)}(hjh]h__devm_fpga_mgr_register}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]jejfuh1jhjhhhjhMubj)}(hp(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)h](j)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hj<hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj>modnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hparenth]hparent}(hjuhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(hconst char *nameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hnameh]hname}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(h#const struct fpga_manager_ops *mopsh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hfpga_manager_opsh]hfpga_manager_ops}(hj$hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&modnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hmopsh]hmops}(hj]hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(h void *privh](j)}(hvoidh]hvoid}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj!)}j$]jc.__devm_fpga_mgr_registerasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hj!h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhjubeh}(h]h ]h"]h$]h&]jejfuh1j hjhhhjhMubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhjhMubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhjhMhjhhubj)}(hhh]h)}(h/resource managed variant of fpga_mgr_register()h]h/resource managed variant of fpga_mgr_register()}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhj6hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]j jj jQjjQjjjuh1jhhhjhNhNubj)}(hX%**Parameters** ``struct device *parent`` fpga manager device from pdev ``const char *name`` fpga manager name ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ``void *priv`` fpga manager private data ``struct module *owner`` owner module containing the ops **Return** fpga manager pointer on success, negative error code otherwise. **Description** This is the devres variant of fpga_mgr_register() for which the unregister function will be called automatically when the managing device is detached.h](h)}(h**Parameters**h]j)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjUubj)}(hhh](j)}(h8``struct device *parent`` fpga manager device from pdev h](j)}(h``struct device *parent``h]j*)}(hjzh]hstruct device *parent}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjxubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjtubj)}(hhh]h)}(hfpga manager device from pdevh]hfpga manager device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhMhjqubj)}(h'``const char *name`` fpga manager name h](j)}(h``const char *name``h]j*)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(hfpga manager nameh]hfpga manager name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjqubj)}(hQ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops h](j)}(h'``const struct fpga_manager_ops *mops``h]j*)}(hjh]h#const struct fpga_manager_ops *mops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(h(pointer to structure of fpga manager opsh]h(pointer to structure of fpga manager ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjqubj)}(h)``void *priv`` fpga manager private data h](j)}(h``void *priv``h]j*)}(hj%h]h void *priv}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj#ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjubj)}(hhh]h)}(hfpga manager private datah]hfpga manager private data}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hMhj;ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj:hMhjqubj)}(h9``struct module *owner`` owner module containing the ops h](j)}(h``struct module *owner``h]j*)}(hj^h]hstruct module *owner}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj\ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjXubj)}(hhh]h)}(howner module containing the opsh]howner module containing the ops}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshMhjtubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jhjshMhjqubeh}(h]h ]h"]h$]h&]uh1jhjUubh)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjUubh)}(h?fpga manager pointer on success, negative error code otherwise.h]h?fpga manager pointer on success, negative error code otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjUubh)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjUubh)}(hThis is the devres variant of fpga_mgr_register() for which the unregister function will be called automatically when the managing device is detached.h]hThis is the devres variant of fpga_mgr_register() for which the unregister function will be called automatically when the managing device is detached.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:164: ./drivers/fpga/fpga-mgr.chMhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubjy)}(hhh]h}(h]h ]h"]h$]h&]entries](j fpga_mgr_unregister (C function)c.fpga_mgr_unregisterhNtauh1jxhjhhhNhNubj)}(hhh](j)}(h3void fpga_mgr_unregister (struct fpga_manager *mgr)h]j)}(h2void fpga_mgr_unregister(struct fpga_manager *mgr)h](j)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chMxubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhj hMxubj)}(hfpga_mgr_unregisterh]j)}(hfpga_mgr_unregisterh]hfpga_mgr_unregister}(hj& hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj" ubah}(h]h ](jjeh"]h$]h&]jejfuh1jhj hhhj hMxubj)}(h(struct fpga_manager *mgr)h]j)}(hstruct fpga_manager *mgrh](j)}(hjh]hstruct}(hjB hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> ubj)}(h h]h }(hjO hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> ubh)}(hhh]j)}(h fpga_managerh]h fpga_manager}(hj` hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj] ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjb modnameN classnameNjj!)}j$]j)}jj( sbc.fpga_mgr_unregisterasbuh1hhj> ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> ubj)}(hj!h]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> ubj)}(hmgrh]hmgr}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1jhj> ubeh}(h]h ]h"]h$]h&]noemphjejfuh1jhj: ubah}(h]h ]h"]h$]h&]jejfuh1j hj hhhj hMxubeh}(h]h ]h"]h$]h&]jejfjuh1jjjhjhhhj hMxubah}(h]jah ](jIjeh"]h$]h&]jj)jhuh1jhj hMxhjhhubj)}(hhh]h)}(hunregister an FPGA managerh]hunregister an FPGA manager}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chMxhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMxubeh}(h]h ](jfunctioneh"]h$]h&]j jj j jj jjjuh1jhhhjhNhNubj)}(h**Parameters** ``struct fpga_manager *mgr`` fpga manager struct **Description** This function is intended for use in an FPGA manager driver's remove function.h](h)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chM|hj ubj)}(hhh]j)}(h1``struct fpga_manager *mgr`` fpga manager struct h](j)}(h``struct fpga_manager *mgr``h]j*)}(hj!h]hstruct fpga_manager *mgr}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j)hj!ubah}(h]h ]h"]h$]h&]uh1jha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chMyhj!ubj)}(hhh]h)}(hfpga manager structh]hfpga manager struct}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hMyhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMyhj ubah}(h]h ]h"]h$]h&]uh1jhj ubh)}(h**Description**h]j)}(hjA!h]h Description}(hjC!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?!ubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chM{hj ubh)}(hNThis function is intended for use in an FPGA manager driver's remove function.h]hPThis function is intended for use in an FPGA manager driver’s remove function.}(hjW!hhhNhNubah}(h]h ]h"]h$]h&]uh1hha/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:167: ./drivers/fpga/fpga-mgr.chMzhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h].api-for-implementing-a-new-fpga-manager-driverah ]h"].api for implementing a new fpga manager driverah$]h&]uh1hhhhhhhhK|ubeh}(h] fpga-managerah ]h"] fpga managerah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj!error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehʌ _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jz!jw!j j jjjr!jo!u nametypes}(jz!j jjr!uh}(jw!hj hjjjo!jjjjjj? jE jjjjjjjGjLjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]hsystem_message)}(hhh]h)}(h`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.h]hdBlank line missing before literal block (after the “::”)? Interpreted as a definition list item.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]h ]h"]h$]h&]levelKtypeINFOlineKXsourcehuh1j"hjubatransform_messages] transformerN include_log] decorationNhhub.