€•Œsphinx.addnodes”Œdocument”“”)�”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)�”}”(hhh]”(hŒ pending_xref”“”)�”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…”�”}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ,/translations/zh_CN/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)�”}”(hhh]”hŒChinese (Traditional)”…”�”}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/zh_TW/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒItalian”…”�”}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/it_IT/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒJapanese”…”�”}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/ja_JP/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒKorean”…”�”}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/ko_KR/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒPortuguese (Brazilian)”…”�”}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/pt_BR/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒSpanish”…”�”}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ,/translations/sp_SP/driver-api/fpga/fpga-mgr”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)�”}”(hhh]”(hŒtitle”“”)�”}”(hŒ FPGA Manager”h]”hŒ FPGA Manager”…”�”}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒF/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr.rst”h´Kubh¶)�”}”(hhh]”(h»)�”}”(hŒOverview”h]”hŒOverview”…”�”}”(hhÎh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhËh²hh³hÊh´KubhŒ paragraph”“”)�”}”(hXuThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it's just binary data. The FPGA manager core won't parse it.”h]”hXyThe FPGA manager core exports a set of functions for programming an FPGA with an image. The API is manufacturer agnostic. All manufacturer specifics are hidden away in a low level driver which registers a set of ops with the core. The FPGA image data itself is very manufacturer specific, but for our purposes it’s just binary data. The FPGA manager core won’t parse it.”…”�”}”(hhÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)�”}”(hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.”h]”hXThe FPGA image to be programmed can be in a scatter gather list, a single contiguous buffer, or a firmware file. Because allocating contiguous kernel memory for the buffer should be avoided, users are encouraged to use a scatter gather list instead if possible.”…”�”}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K hhËh²hubhÝ)�”}”(hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.”h]”hXThe particulars for programming the image are presented in a structure (struct fpga_image_info). This struct contains parameters such as pointers to the FPGA image as well as image-specific particulars such as whether the image was built for full or partial reconfiguration.”…”�”}”(hhúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)�”}”(hhh]”(h»)�”}”(hŒ How to support a new FPGA device”h]”hŒ How to support a new FPGA device”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjh²hh³hÊh´KubhÝ)�”}”(hŒ¦To add another FPGA manager, write a driver that implements a set of ops. The probe function calls ``fpga_mgr_register()`` or ``fpga_mgr_register_full()``, such as::”h]”(hŒdTo add another FPGA manager, write a driver that implements a set of ops. The probe function calls ”…”�”}”(hj!h²hh³Nh´NubhŒliteral”“”)�”}”(hŒ``fpga_mgr_register()``”h]”hŒfpga_mgr_register()”…”�”}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj!ubhŒ or ”…”�”}”(hj!h²hh³Nh´Nubj*)�”}”(hŒ``fpga_mgr_register_full()``”h]”hŒfpga_mgr_register_full()”…”�”}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj!ubhŒ , such as:”…”�”}”(hj!h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjh²hubhŒ literal_block”“”)�”}”(hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }”h]”hX[static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, .write = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, .state = socfpga_fpga_ops_state, }; static int socfpga_fpga_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; /* * do ioremaps, get interrupts, etc. and save * them in priv */ mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", &socfpga_fpga_ops, priv); if (IS_ERR(mgr)) return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) { struct fpga_manager *mgr = platform_get_drvdata(pdev); fpga_mgr_unregister(mgr); return 0; }”…”�”}”hjWsbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1jUh³hÊh´Khjh²hubhÝ)�”}”(hXrAlternatively, the probe function could call one of the resource managed register functions, ``devm_fpga_mgr_register()`` or ``devm_fpga_mgr_register_full()``. When these functions are used, the parameter syntax is the same, but the call to ``fpga_mgr_unregister()`` should be removed. In the above example, the ``socfpga_fpga_remove()`` function would not be required.”h]”(hŒ]Alternatively, the probe function could call one of the resource managed register functions, ”…”�”}”(hjgh²hh³Nh´Nubj*)�”}”(hŒ``devm_fpga_mgr_register()``”h]”hŒdevm_fpga_mgr_register()”…”�”}”(hjoh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjgubhŒ or ”…”�”}”(hjgh²hh³Nh´Nubj*)�”}”(hŒ!``devm_fpga_mgr_register_full()``”h]”hŒdevm_fpga_mgr_register_full()”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjgubhŒT. When these functions are used, the parameter syntax is the same, but the call to ”…”�”}”(hjgh²hh³Nh´Nubj*)�”}”(hŒ``fpga_mgr_unregister()``”h]”hŒfpga_mgr_unregister()”…”�”}”(hj“h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjgubhŒ. should be removed. In the above example, the ”…”�”}”(hjgh²hh³Nh´Nubj*)�”}”(hŒ``socfpga_fpga_remove()``”h]”hŒsocfpga_fpga_remove()”…”�”}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjgubhŒ function would not be required.”…”�”}”(hjgh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KHhjh²hubhÝ)�”}”(hŒÆThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.”h]”hŒÆThe ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for success or negative error codes otherwise.”…”�”}”(hj½h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KOhjh²hubhŒdefinition_list”“”)�”}”(hhh]”hŒdefinition_list_item”“”)�”}”(hŒÀThe programming sequence is:: 1. .parse_header (optional, may be called once or multiple times) 2. .write_init 3. .write or .write_sg (may be called once or multiple times) 4. .write_complete ”h]”(hŒterm”“”)�”}”(hŒThe programming sequence is::”h]”hŒThe programming sequence is::”…”�”}”(hjØh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³hÊh´KWhjÒubhŒ definition”“”)�”}”(hhh]”hŒenumerated_list”“”)�”}”(hhh]”(hŒ list_item”“”)�”}”(hŒ>.parse_header (optional, may be called once or multiple times)”h]”hÝ)�”}”(hjôh]”hŒ>.parse_header (optional, may be called once or multiple times)”…”�”}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KThjòubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjíubjñ)�”}”(hŒ .write_init”h]”hÝ)�”}”(hj h]”hŒ .write_init”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KUhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjíubjñ)�”}”(hŒ:.write or .write_sg (may be called once or multiple times)”h]”hÝ)�”}”(hj"h]”hŒ:.write or .write_sg (may be called once or multiple times)”…”�”}”(hj$h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KVhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjíubjñ)�”}”(hŒ.write_complete ”h]”hÝ)�”}”(hŒ.write_complete”h]”hŒ.write_complete”…”�”}”(hj;h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KWhj7ubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjíubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jëhjèubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÒubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³hÊh´KWhjÍubah}”(h]”h ]”h"]”h$]”h&]”uh1jËhjh²hh³Nh´NubhÝ)�”}”(hX¾The .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.”h]”hX¾The .parse_header function will set header_size and data_size to struct fpga_image_info. Before parse_header call, header_size is initialized with initial_header_size. If flag skip_header of fpga_manager_ops is true, .write function will get image buffer starting at header_size offset from the beginning. If data_size is set, .write function will get data_size bytes of the image buffer, otherwise .write will get data up to the end of image buffer. This will not affect .write_sg, .write_sg will still get whole image in sg_table form. If FPGA image is already mapped as a single contiguous buffer, whole buffer will be passed into .parse_header. If image is in scatter-gather form, core code will buffer up at least .initial_header_size before the first call of .parse_header, if it is not enough, .parse_header should set desired size into info->header_size and return -EAGAIN, then it will be called again with greater part of image buffer on the input.”…”�”}”(hjlh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KYhjh²hubhÝ)�”}”(hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.”h]”hXThe .write_init function will prepare the FPGA to receive the image data. The buffer passed into .write_init will be at least info->header_size bytes long; if the whole bitstream is not immediately available then the core code will buffer up at least this much before starting.”…”�”}”(hjzh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kghjh²hubhÝ)�”}”(hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.”h]”hXThe .write function writes a buffer to the FPGA. The buffer may be contain the whole FPGA image or may be a smaller chunk of an FPGA image. In the latter case, this function is called multiple times for successive chunks. This interface is suitable for drivers which use PIO.”…”�”}”(hjˆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Klhjh²hubhÝ)�”}”(hŒ“The .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.”h]”hŒ“The .write_sg version behaves the same as .write except the input is a sg_table scatter list. This interface is suitable for drivers which use DMA.”…”�”}”(hj–h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kqhjh²hubhÝ)�”}”(hŒpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.”h]”hŒpThe .write_complete function is called after all the image has been written to put the FPGA into operating mode.”…”�”}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kthjh²hubhÝ)�”}”(hŒ¨The ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn't result in a change in state.”h]”hŒªThe ops include a .state function which will determine the state the FPGA is in and return a code of type enum fpga_mgr_states. It doesn’t result in a change in state.”…”�”}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kwhjh²hubeh}”(h]”Œ how-to-support-a-new-fpga-device”ah ]”h"]”Œ how to support a new fpga device”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)�”}”(hhh]”(h»)�”}”(hŒ.API for implementing a new FPGA Manager driver”h]”hŒ.API for implementing a new FPGA Manager driver”…”�”}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÈh²hh³hÊh´K|ubhŒ bullet_list”“”)�”}”(hhh]”(jñ)�”}”(hŒ@``fpga_mgr_states`` - Values for :c:expr:`fpga_manager->state`.”h]”hÝ)�”}”(hjàh]”(j*)�”}”(hŒ``fpga_mgr_states``”h]”hŒfpga_mgr_states”…”�”}”(hjåh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjâubhŒ - Values for ”…”�”}”(hjâh²hh³Nh´NubhŒ desc_inline”“”)�”}”(hŒfpga_manager->state”h]”(h)�”}”(hhh]”hŒ desc_sig_name”“”)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”Œn”ah"]”h$]”h&]”uh1jhjýubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”Œc”Œreftype”Œ identifier”Œ reftarget”jŒmodname”NŒ classname”NŒ c:parent_key”Œsphinx.domains.c”Œ LookupKey”“”)�”}”Œdata”]”sbuh1hhjùubhŒdesc_sig_operator”“”)�”}”(hŒ->”h]”hŒ->”…”�”}”(hj(h²hh³Nh´Nubah}”(h]”h ]”Œo”ah"]”h$]”h&]”uh1j&hjùubj)�”}”(hŒstate”h]”hŒstate”…”�”}”(hj7h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjùubeh}”(h]”h ]”(Œc-expr”Œsig”Œ sig-inline”jeh"]”h$]”h&]”uh1j÷hjâubhŒ.”…”�”}”(hjâh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K~hjÞubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjÛh²hh³hÊh´Nubjñ)�”}”(hŒ.struct fpga_manager - the FPGA manager struct”h]”hÝ)�”}”(hj`h]”hŒ.struct fpga_manager - the FPGA manager struct”…”�”}”(hjbh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khj^ubah}”(h]”h ]”h"]”h$]”h&]”uh1jðhjÛh²hh³hÊh´Nubjñ)�”}”(hŒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj:ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´K4hj6ubjç)�”}”(hhh]”hÝ)�”}”(hŒError during WRITE_INIT stage”h]”hŒError during WRITE_INIT stage”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jQh´K4hjRubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj6ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jQh´K4hj2ubjÑ)�”}”(hŒ/``FPGA_MGR_STATE_WRITE`` writing image to FPGA ”h]”(j×)�”}”(hŒ``FPGA_MGR_STATE_WRITE``”h]”j*)�”}”(hjuh]”hŒFPGA_MGR_STATE_WRITE”…”�”}”(hjwh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjsubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´K7hjoubjç)�”}”(hhh]”hÝ)�”}”(hŒwriting image to FPGA”h]”hŒwriting image to FPGA”…”�”}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jŠh´K7hj‹ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjoubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jŠh´K7hj2ubjÑ)�”}”(hŒ6``FPGA_MGR_STATE_WRITE_ERR`` Error while writing FPGA ”h]”(j×)�”}”(hŒ``FPGA_MGR_STATE_WRITE_ERR``”h]”j*)�”}”(hj®h]”hŒFPGA_MGR_STATE_WRITE_ERR”…”�”}”(hj°h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj¬ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´K:hj¨ubjç)�”}”(hhh]”hÝ)�”}”(hŒError while writing FPGA”h]”hŒError while writing FPGA”…”�”}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÃh´K:hjÄubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj¨ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jÃh´K:hj2ubjÑ)�”}”(hŒ?``FPGA_MGR_STATE_WRITE_COMPLETE`` Doing post programming steps ”h]”(j×)�”}”(hŒ!``FPGA_MGR_STATE_WRITE_COMPLETE``”h]”j*)�”}”(hjçh]”hŒFPGA_MGR_STATE_WRITE_COMPLETE”…”�”}”(hjéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjåubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´K=hjáubjç)�”}”(hhh]”hÝ)�”}”(hŒDoing post programming steps”h]”hŒDoing post programming steps”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jüh´K=hjýubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjáubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jüh´K=hj2ubjÑ)�”}”(hŒB``FPGA_MGR_STATE_WRITE_COMPLETE_ERR`` Error during WRITE_COMPLETE ”h]”(j×)�”}”(hŒ%``FPGA_MGR_STATE_WRITE_COMPLETE_ERR``”h]”j*)�”}”(hj h]”hŒ!FPGA_MGR_STATE_WRITE_COMPLETE_ERR”…”�”}”(hj"h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´K@hjubjç)�”}”(hhh]”hÝ)�”}”(hŒError during WRITE_COMPLETE”h]”hŒError during WRITE_COMPLETE”…”�”}”(hj9h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j5h´K@hj6ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j5h´K@hj2ubjÑ)�”}”(hŒ=``FPGA_MGR_STATE_OPERATING`` FPGA is programmed and operating”h]”(j×)�”}”(hŒ``FPGA_MGR_STATE_OPERATING``”h]”j*)�”}”(hjYh]”hŒFPGA_MGR_STATE_OPERATING”…”�”}”(hj[h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjWubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´KBhjSubjç)�”}”(hhh]”hÝ)�”}”(hŒ FPGA is programmed and operating”h]”hŒ FPGA is programmed and operating”…”�”}”(hjrh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:143: ./include/linux/fpga/fpga-mgr.h”h´KChjoubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjSubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jnh´KBhj2ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhjubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³Nh´Nubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j…Œfpga_manager (C struct)”Œc.fpga_manager”hNt”auh1jxhjÈh²hh³Nh´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒ fpga_manager”h]”j•)�”}”(hŒstruct fpga_manager”h]”(j›)�”}”(hŒstruct”h]”hŒstruct”…”�”}”(hj³h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj¯h²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´Kubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÂh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj¯h²hh³jÁh´Kubj¾)�”}”(hŒ fpga_manager”h]”j)�”}”(hj­h]”hŒ fpga_manager”…”�”}”(hjÔh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjÐubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hj¯h²hh³jÁh´Kubeh}”(h]”h ]”h"]”h$]”h&]”jejfjÞˆuh1j”jßjàhj«h²hh³jÁh´Kubah}”(h]”j¦ah ]”(jIjäeh"]”h$]”h&]”jèˆjé)jêhuh1jŽh³jÁh´Khj¨h²hubjì)�”}”(hhh]”hÝ)�”}”(hŒfpga manager structure”h]”hŒfpga manager structure”…”�”}”(hjöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÅhjóh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jëhj¨h²hh³jÁh´Kubeh}”(h]”h ]”(jŒstruct”eh"]”h$]”h&]”j jj j jj j‰j‰j‰uh1j‰h²hhjÈh³Nh´Nubj)�”}”(hX�**Definition**:: struct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; }; **Members** ``name`` name of low level fpga manager ``dev`` fpga manager device ``ref_mutex`` only allows one reference to fpga manager ``state`` state of fpga manager ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to struct of fpga manager ops ``mops_owner`` module containing the mops ``priv`` low level driver private date”h]”(hÝ)�”}”(hŒ**Definition**::”h]”(j)�”}”(hŒ**Definition**”h]”hŒ Definition”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj ubhŒ:”…”�”}”(hj h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÉhj ubjV)�”}”(hŒÿstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };”h]”hŒÿstruct fpga_manager { const char *name; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; struct module *mops_owner; void *priv; };”…”�”}”hj3 sbah}”(h]”h ]”h"]”h$]”h&]”jejfuh1jUh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KËhj ubhÝ)�”}”(hŒ **Members**”h]”j)�”}”(hjD h]”hŒMembers”…”�”}”(hjF h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjB ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÖhj ubjÌ)�”}”(hhh]”(jÑ)�”}”(hŒ(``name`` name of low level fpga manager ”h]”(j×)�”}”(hŒ``name``”h]”j*)�”}”(hjc h]”hŒname”…”�”}”(hje h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hja ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÇhj] ubjç)�”}”(hhh]”hÝ)�”}”(hŒname of low level fpga manager”h]”hŒname of low level fpga manager”…”�”}”(hj| h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jx h´KÇhjy ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj] ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jx h´KÇhjZ ubjÑ)�”}”(hŒ``dev`` fpga manager device ”h]”(j×)�”}”(hŒ``dev``”h]”j*)�”}”(hjœ h]”hŒdev”…”�”}”(hjž h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjš ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÈhj– ubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager device”h]”hŒfpga manager device”…”�”}”(hjµ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j± h´KÈhj² ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj– ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j± h´KÈhjZ ubjÑ)�”}”(hŒ8``ref_mutex`` only allows one reference to fpga manager ”h]”(j×)�”}”(hŒ ``ref_mutex``”h]”j*)�”}”(hjÕ h]”hŒ ref_mutex”…”�”}”(hj× h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjÓ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÉhjÏ ubjç)�”}”(hhh]”hÝ)�”}”(hŒ)only allows one reference to fpga manager”h]”hŒ)only allows one reference to fpga manager”…”�”}”(hjî h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jê h´KÉhjë ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÏ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jê h´KÉhjZ ubjÑ)�”}”(hŒ ``state`` state of fpga manager ”h]”(j×)�”}”(hŒ ``state``”h]”j*)�”}”(hj h]”hŒstate”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÊhj ubjç)�”}”(hhh]”hÝ)�”}”(hŒstate of fpga manager”h]”hŒstate of fpga manager”…”�”}”(hj' h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j# h´KÊhj$ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j# h´KÊhjZ ubjÑ)�”}”(hŒ7``compat_id`` FPGA manager id for compatibility check. ”h]”(j×)�”}”(hŒ ``compat_id``”h]”j*)�”}”(hjG h]”hŒ compat_id”…”�”}”(hjI h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjE ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KËhjA ubjç)�”}”(hhh]”hÝ)�”}”(hŒ(FPGA manager id for compatibility check.”h]”hŒ(FPGA manager id for compatibility check.”…”�”}”(hj` h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j\ h´KËhj] ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjA ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j\ h´KËhjZ ubjÑ)�”}”(hŒ/``mops`` pointer to struct of fpga manager ops ”h]”(j×)�”}”(hŒ``mops``”h]”j*)�”}”(hj€ h]”hŒmops”…”�”}”(hj‚ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj~ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÌhjz ubjç)�”}”(hhh]”hÝ)�”}”(hŒ%pointer to struct of fpga manager ops”h]”hŒ%pointer to struct of fpga manager ops”…”�”}”(hj™ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j• h´KÌhj– ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjz ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j• h´KÌhjZ ubjÑ)�”}”(hŒ*``mops_owner`` module containing the mops ”h]”(j×)�”}”(hŒ``mops_owner``”h]”j*)�”}”(hj¹ h]”hŒ mops_owner”…”�”}”(hj» h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj· ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÍhj³ ubjç)�”}”(hhh]”hÝ)�”}”(hŒmodule containing the mops”h]”hŒmodule containing the mops”…”�”}”(hjÒ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÎ h´KÍhjÏ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj³ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jÎ h´KÍhjZ ubjÑ)�”}”(hŒ&``priv`` low level driver private date”h]”(j×)�”}”(hŒ``priv``”h]”j*)�”}”(hjò h]”hŒpriv”…”�”}”(hjô h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjð ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÍhjì ubjç)�”}”(hhh]”hÝ)�”}”(hŒlow level driver private date”h]”hŒlow level driver private date”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:146: ./include/linux/fpga/fpga-mgr.h”h´KÎhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjì ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j h´KÍhjZ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhj ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³Nh´Nubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j…Œfpga_manager_ops (C struct)”Œc.fpga_manager_ops”hNt”auh1jxhjÈh²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒfpga_manager_ops”h]”j•)�”}”(hŒstruct fpga_manager_ops”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjM h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjI h²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´Kubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj[ h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjI h²hh³jZ h´Kubj¾)�”}”(hŒfpga_manager_ops”h]”j)�”}”(hjG h]”hŒfpga_manager_ops”…”�”}”(hjm h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhji ubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hjI h²hh³jZ h´Kubeh}”(h]”h ]”h"]”h$]”h&]”jejfjÞˆuh1j”jßjàhjE h²hh³jZ h´Kubah}”(h]”j? ah ]”(jIjäeh"]”h$]”h&]”jèˆjé)jêhuh1jŽh³jZ h´KhjB h²hubjì)�”}”(hhh]”hÝ)�”}”(hŒ&ops for low level fpga manager drivers”h]”hŒ&ops for low level fpga manager drivers”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K”hjŒ h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jëhjB h²hh³jZ h´Kubeh}”(h]”h ]”(jŒstruct”eh"]”h$]”h&]”j jj j§ jj§ j‰j‰j‰uh1j‰h²hhjÈh³jA h´Nubj)�”}”(hXü**Definition**:: struct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; **Members** ``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. ``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. ``state`` returns an enum value of the FPGA's state ``status`` returns status of the FPGA, including reconfiguration error code ``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. ``write_init`` prepare the FPGA to receive configuration data ``write`` write count bytes of configuration data to the FPGA ``write_sg`` write the scatter list of configuration data to the FPGA ``write_complete`` set FPGA to operating state after writing is done ``fpga_remove`` optional: Set FPGA into a specific state during driver remove ``groups`` optional attribute groups.”h]”(hÝ)�”}”(hŒ**Definition**::”h]”(j)�”}”(hŒ**Definition**”h]”hŒ Definition”…”�”}”(hj³ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¯ ubhŒ:”…”�”}”(hj¯ h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K˜hj« ubjV)�”}”(hXÛstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };”h]”hXÛstruct fpga_manager_ops { size_t initial_header_size; bool skip_header; enum fpga_mgr_states (*state)(struct fpga_manager *mgr); u64 (*status)(struct fpga_manager *mgr); int (*parse_header)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write_init)(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t count); int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; };”…”�”}”hjÌ sbah}”(h]”h ]”h"]”h$]”h&]”jejfuh1jUh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´Kšhj« ubhÝ)�”}”(hŒ **Members**”h]”j)�”}”(hjÝ h]”hŒMembers”…”�”}”(hjß h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjÛ ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¨hj« ubjÌ)�”}”(hhh]”(jÑ)�”}”(hŒh``initial_header_size`` minimum number of bytes that should be passed into parse_header and write_init. ”h]”(j×)�”}”(hŒ``initial_header_size``”h]”j*)�”}”(hjü h]”hŒinitial_header_size”…”�”}”(hjþ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjú ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K—hjö ubjç)�”}”(hhh]”hÝ)�”}”(hŒOminimum number of bytes that should be passed into parse_header and write_init.”h]”hŒOminimum number of bytes that should be passed into parse_header and write_init.”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K–hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjö ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j h´K—hjó ubjÑ)�”}”(hŒš``skip_header`` bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback. ”h]”(j×)�”}”(hŒ``skip_header``”h]”j*)�”}”(hj6 h]”hŒ skip_header”…”�”}”(hj8 h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj4 ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´Kšhj0 ubjç)�”}”(hhh]”hÝ)�”}”(hŒ‰bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.”h]”hŒ‰bool flag to tell fpga-mgr core whether it should skip info->header_size part at the beginning of the image when invoking write callback.”…”�”}”(hjO h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K˜hjL ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj0 ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jK h´Kšhjó ubjÑ)�”}”(hŒ4``state`` returns an enum value of the FPGA's state ”h]”(j×)�”}”(hŒ ``state``”h]”j*)�”}”(hjp h]”hŒstate”…”�”}”(hjr h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjn ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K›hjj ubjç)�”}”(hhh]”hÝ)�”}”(hŒ)returns an enum value of the FPGA's state”h]”hŒ+returns an enum value of the FPGA’s state”…”�”}”(hj‰ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j… h´K›hj† ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j… h´K›hjó ubjÑ)�”}”(hŒL``status`` returns status of the FPGA, including reconfiguration error code ”h]”(j×)�”}”(hŒ ``status``”h]”j*)�”}”(hj© h]”hŒstatus”…”�”}”(hj« h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj§ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´Kœhj£ ubjç)�”}”(hhh]”hÝ)�”}”(hŒ@returns status of the FPGA, including reconfiguration error code”h]”hŒ@returns status of the FPGA, including reconfiguration error code”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j¾ h´Kœhj¿ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj£ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j¾ h´Kœhjó ubjÑ)�”}”(hŒÀ``parse_header`` parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN. ”h]”(j×)�”}”(hŒ``parse_header``”h]”j*)�”}”(hjâ h]”hŒ parse_header”…”�”}”(hjä h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjà ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´KŸhjÜ ubjç)�”}”(hhh]”hÝ)�”}”(hŒ®parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.”h]”hŒ®parse FPGA image header to set info->header_size and info->data_size. In case the input buffer is not large enough, set required size to info->header_size and return -EAGAIN.”…”�”}”(hjû h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K�hjø ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÜ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j÷ h´KŸhjó ubjÑ)�”}”(hŒ>``write_init`` prepare the FPGA to receive configuration data ”h]”(j×)�”}”(hŒ``write_init``”h]”j*)�”}”(hj h]”hŒ write_init”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K hj ubjç)�”}”(hhh]”hÝ)�”}”(hŒ.prepare the FPGA to receive configuration data”h]”hŒ.prepare the FPGA to receive configuration data”…”�”}”(hj5 h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j1 h´K hj2 ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j1 h´K hjó ubjÑ)�”}”(hŒ>``write`` write count bytes of configuration data to the FPGA ”h]”(j×)�”}”(hŒ ``write``”h]”j*)�”}”(hjU h]”hŒwrite”…”�”}”(hjW h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjS ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¡hjO ubjç)�”}”(hhh]”hÝ)�”}”(hŒ3write count bytes of configuration data to the FPGA”h]”hŒ3write count bytes of configuration data to the FPGA”…”�”}”(hjn h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jj h´K¡hjk ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjO ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jj h´K¡hjó ubjÑ)�”}”(hŒF``write_sg`` write the scatter list of configuration data to the FPGA ”h]”(j×)�”}”(hŒ ``write_sg``”h]”j*)�”}”(hjŽ h]”hŒwrite_sg”…”�”}”(hj� h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjŒ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¢hjˆ ubjç)�”}”(hhh]”hÝ)�”}”(hŒ8write the scatter list of configuration data to the FPGA”h]”hŒ8write the scatter list of configuration data to the FPGA”…”�”}”(hj§ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j£ h´K¢hj¤ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjˆ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j£ h´K¢hjó ubjÑ)�”}”(hŒE``write_complete`` set FPGA to operating state after writing is done ”h]”(j×)�”}”(hŒ``write_complete``”h]”j*)�”}”(hjÇ h]”hŒwrite_complete”…”�”}”(hjÉ h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjÅ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K£hjÁ ubjç)�”}”(hhh]”hÝ)�”}”(hŒ1set FPGA to operating state after writing is done”h]”hŒ1set FPGA to operating state after writing is done”…”�”}”(hjà h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÜ h´K£hjÝ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÁ ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jÜ h´K£hjó ubjÑ)�”}”(hŒN``fpga_remove`` optional: Set FPGA into a specific state during driver remove ”h]”(j×)�”}”(hŒ``fpga_remove``”h]”j*)�”}”(hjh]”hŒ fpga_remove”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjþ ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¤hjú ubjç)�”}”(hhh]”hÝ)�”}”(hŒ=optional: Set FPGA into a specific state during driver remove”h]”hŒ=optional: Set FPGA into a specific state during driver remove”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jh´K¤hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjú ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jh´K¤hjó ubjÑ)�”}”(hŒ%``groups`` optional attribute groups.”h]”(j×)�”}”(hŒ ``groups``”h]”j*)�”}”(hj9h]”hŒgroups”…”�”}”(hj;h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj7ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¤hj3ubjç)�”}”(hhh]”hÝ)�”}”(hŒoptional attribute groups.”h]”hŒoptional attribute groups.”…”�”}”(hjRh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¥hjOubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj3ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jNh´K¤hjó ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhj« ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³jA h´NubhÝ)�”}”(hŒ**Description**”h]”j)�”}”(hj|h]”hŒ Description”…”�”}”(hj~h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjzubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¨hjÈh²hubhÝ)�”}”(hŒ´fpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.”h]”hŒ´fpga_manager_ops are the low level functions implemented by a specific fpga manager driver. The optional ones are tested for NULL before being called, so leaving them out is fine.”…”�”}”(hj’h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:149: ./include/linux/fpga/fpga-mgr.h”h´K¥hjÈh²hubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j…Œfpga_manager_info (C struct)”Œc.fpga_manager_info”hNt”auh1jxhjÈh²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒfpga_manager_info”h]”j•)�”}”(hŒstruct fpga_manager_info”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hj»h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj·h²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´Kubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÉh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj·h²hh³jÈh´Kubj¾)�”}”(hŒfpga_manager_info”h]”j)�”}”(hjµh]”hŒfpga_manager_info”…”�”}”(hjÛh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj×ubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hj·h²hh³jÈh´Kubeh}”(h]”h ]”h"]”h$]”h&]”jejfjÞˆuh1j”jßjàhj³h²hh³jÈh´Kubah}”(h]”j­ah ]”(jIjäeh"]”h$]”h&]”jèˆjé)jêhuh1jŽh³jÈh´Khj°h²hubjì)�”}”(hhh]”hÝ)�”}”(hŒ,collection of parameters for an FPGA Manager”h]”hŒ,collection of parameters for an FPGA Manager”…”�”}”(hjýh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K�hjúh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jëhj°h²hh³jÈh´Kubeh}”(h]”h ]”(jŒstruct”eh"]”h$]”h&]”j jj jjjj‰j‰j‰uh1j‰h²hhjÈh³j¯h´Nubj)�”}”(hXp**Definition**:: struct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; }; **Members** ``name`` fpga manager name ``compat_id`` FPGA manager id for compatibility check. ``mops`` pointer to structure of fpga manager ops ``priv`` fpga manager private data”h]”(hÝ)�”}”(hŒ**Definition**::”h]”(j)�”}”(hŒ**Definition**”h]”hŒ Definition”…”�”}”(hj!h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjubhŒ:”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K…hjubjV)�”}”(hŒ’struct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };”h]”hŒ’struct fpga_manager_info { const char *name; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; };”…”�”}”hj:sbah}”(h]”h ]”h"]”h$]”h&]”jejfuh1jUh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K‡hjubhÝ)�”}”(hŒ **Members**”h]”j)�”}”(hjKh]”hŒMembers”…”�”}”(hjMh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjIubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´KŽhjubjÌ)�”}”(hhh]”(jÑ)�”}”(hŒ``name`` fpga manager name ”h]”(j×)�”}”(hŒ``name``”h]”j*)�”}”(hjjh]”hŒname”…”�”}”(hjlh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjhubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´Kƒhjdubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager name”h]”hŒfpga manager name”…”�”}”(hjƒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jh´Kƒhj€ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjdubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jh´KƒhjaubjÑ)�”}”(hŒ7``compat_id`` FPGA manager id for compatibility check. ”h]”(j×)�”}”(hŒ ``compat_id``”h]”j*)�”}”(hj£h]”hŒ compat_id”…”�”}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj¡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K„hj�ubjç)�”}”(hhh]”hÝ)�”}”(hŒ(FPGA manager id for compatibility check.”h]”hŒ(FPGA manager id for compatibility check.”…”�”}”(hj¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j¸h´K„hj¹ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj�ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j¸h´K„hjaubjÑ)�”}”(hŒ2``mops`` pointer to structure of fpga manager ops ”h]”(j×)�”}”(hŒ``mops``”h]”j*)�”}”(hjÜh]”hŒmops”…”�”}”(hjÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjÚubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K…hjÖubjç)�”}”(hhh]”hÝ)�”}”(hŒ(pointer to structure of fpga manager ops”h]”hŒ(pointer to structure of fpga manager ops”…”�”}”(hjõh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jñh´K…hjòubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÖubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jñh´K…hjaubjÑ)�”}”(hŒ"``priv`` fpga manager private data”h]”(j×)�”}”(hŒ``priv``”h]”j*)�”}”(hjh]”hŒpriv”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K…hjubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager private data”h]”hŒfpga manager private data”…”�”}”(hj.h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K†hj+ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j*h´K…hjaubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhjubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³j¯h´NubhÝ)�”}”(hŒ**Description**”h]”j)�”}”(hjXh]”hŒ Description”…”�”}”(hjZh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjVubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K‰hjÈh²hubhÝ)�”}”(hŒðfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.”h]”hŒðfpga_manager_info contains parameters for the register_full function. These are separated into an info structure because they some are optional others could be added to in the future. The info structure facilitates maintaining a stable API.”…”�”}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:152: ./include/linux/fpga/fpga-mgr.h”h´K†hjÈh²hubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”•fÍ]”(j…Œ%__fpga_mgr_register_full (C function)”Œc.__fpga_mgr_register_full”hNt”auh1jxhjÈh²hh³Nh´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒ‚struct fpga_manager * __fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”j•)�”}”(hŒ€struct fpga_manager *__fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hj–h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj’h²hh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´Mubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj’h²hh³j£h´Mubh)�”}”(hhh]”j)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjµh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj²ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”j·Œmodname”NŒ classname”Njj!)�”}”j$]”jŒ ASTIdentifier”“”)�”}”jŒ__fpga_mgr_register_full”sbŒc.__fpga_mgr_register_full”†”asbuh1hhj’h²hh³j£h´Mubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjØh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj’h²hh³j£h´MubhŒdesc_sig_punctuation”“”)�”}”(hj!h]”hŒ*”…”�”}”(hjèh²hh³Nh´Nubah}”(h]”h ]”Œp”ah"]”h$]”h&]”uh1jæhj’h²hh³j£h´Mubj¾)�”}”(hŒ__fpga_mgr_register_full”h]”j)�”}”(hjÕh]”hŒ__fpga_mgr_register_full”…”�”}”(hjúh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjöubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hj’h²hh³j£h´MubhŒdesc_parameterlist”“”)�”}”(hŒS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”(hŒdesc_parameter”“”)�”}”(hŒstruct device *parent”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj&h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubh)�”}”(hhh]”j)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hj7h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj4ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”j9Œmodname”NŒ classname”Njj!)�”}”j$]”jÓŒc.__fpga_mgr_register_full”†”asbuh1hhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjch²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjubj)�”}”(hŒparent”h]”hŒparent”…”�”}”(hjph²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjubj)�”}”(hŒ$const struct fpga_manager_info *info”h]”(j›)�”}”(hŒconst”h]”hŒconst”…”�”}”(hj‰h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj…ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj—h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj…ubj›)�”}”(hjµh]”hŒstruct”…”�”}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj…ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj²h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj…ubh)�”}”(hhh]”j)�”}”(hŒfpga_manager_info”h]”hŒfpga_manager_info”…”�”}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjÀubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”jÅŒmodname”NŒ classname”Njj!)�”}”j$]”jÓŒc.__fpga_mgr_register_full”†”asbuh1hhj…ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjáh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj…ubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjïh²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhj…ubj)�”}”(hŒinfo”h]”hŒinfo”…”�”}”(hjüh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj…ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjubj)�”}”(hŒstruct module *owner”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj"h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubh)�”}”(hhh]”j)�”}”(hŒmodule”h]”hŒmodule”…”�”}”(hj3h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj0ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”j5Œmodname”NŒ classname”Njj!)�”}”j$]”jÓŒc.__fpga_mgr_register_full”†”asbuh1hhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjQh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubjç)�”}”(hj!h]”hŒ*”…”�”}”(hj_h²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjubj)�”}”(hŒowner”h]”hŒowner”…”�”}”(hjlh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”jejfuh1j hj’h²hh³j£h´Mubeh}”(h]”h ]”h"]”h$]”h&]”jejfjÞˆuh1j”jßjàhjŽh²hh³j£h´Mubah}”(h]”j‰ah ]”(jIjäeh"]”h$]”h&]”jèˆjé)jêhuh1jŽh³j£h´Mhj‹h²hubjì)�”}”(hhh]”hÝ)�”}”(hŒ*create and register an FPGA Manager device”h]”hŒ*create and register an FPGA Manager device”…”�”}”(hj–h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´Mhj“h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jëhj‹h²hh³j£h´Mubeh}”(h]”h ]”(jŒfunction”eh"]”h$]”h&]”j jj j®jj®j‰j‰j‰uh1j‰h²hhjÈh³Nh´Nubj)�”}”(hXª**Parameters** ``struct device *parent`` fpga manager device from pdev ``const struct fpga_manager_info *info`` parameters for fpga manager ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended. **Return** pointer to struct fpga_manager pointer or ERR_PTR()”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j)�”}”(hj¸h]”hŒ Parameters”…”�”}”(hjºh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¶ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hj²ubjÌ)�”}”(hhh]”(jÑ)�”}”(hŒ8``struct device *parent`` fpga manager device from pdev ”h]”(j×)�”}”(hŒ``struct device *parent``”h]”j*)�”}”(hj×h]”hŒstruct device *parent”…”�”}”(hjÙh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjÕubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hjÑubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager device from pdev”h]”hŒfpga manager device from pdev”…”�”}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jìh´M hjíubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÑubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jìh´M hjÎubjÑ)�”}”(hŒE``const struct fpga_manager_info *info`` parameters for fpga manager ”h]”(j×)�”}”(hŒ(``const struct fpga_manager_info *info``”h]”j*)�”}”(hjh]”hŒ$const struct fpga_manager_info *info”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hj ubjç)�”}”(hhh]”hÝ)�”}”(hŒparameters for fpga manager”h]”hŒparameters for fpga manager”…”�”}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j%h´M hj&ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j%h´M hjÎubjÑ)�”}”(hŒ9``struct module *owner`` owner module containing the ops ”h]”(j×)�”}”(hŒ``struct module *owner``”h]”j*)�”}”(hjIh]”hŒstruct module *owner”…”�”}”(hjKh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjGubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hjCubjç)�”}”(hhh]”hÝ)�”}”(hŒowner module containing the ops”h]”hŒowner module containing the ops”…”�”}”(hjbh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j^h´M hj_ubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjCubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j^h´M hjÎubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhj²ubhÝ)�”}”(hŒ**Description**”h]”j)�”}”(hj„h]”hŒ Description”…”�”}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj‚ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hj²ubhÝ)�”}”(hŒ‰The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.”h]”hŒ‰The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register_full() instead is recommended.”…”�”}”(hjšh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´M hj²ubhÝ)�”}”(hŒ **Return**”h]”j)�”}”(hj«h]”hŒReturn”…”�”}”(hj­h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj©ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´Mhj²ubhÝ)�”}”(hŒ3pointer to struct fpga_manager pointer or ERR_PTR()”h]”hŒ3pointer to struct fpga_manager pointer or ERR_PTR()”…”�”}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:155: ./drivers/fpga/fpga-mgr.c”h´Mhj²ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³Nh´Nubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j…Œ __fpga_mgr_register (C function)”Œc.__fpga_mgr_register”hNt”auh1jxhjÈh²hh³Nh´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒšstruct fpga_manager * __fpga_mgr_register (struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)”h]”j•)�”}”(hŒ˜struct fpga_manager *__fpga_mgr_register(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjðh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjìh²hh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´MZubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjþh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjìh²hh³jýh´MZubh)�”}”(hhh]”j)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”jŒmodname”NŒ classname”Njj!)�”}”j$]”jÒ)�”}”jŒ__fpga_mgr_register”sbŒc.__fpga_mgr_register”†”asbuh1hhjìh²hh³jýh´MZubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj0h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjìh²hh³jýh´MZubjç)�”}”(hj!h]”hŒ*”…”�”}”(hj>h²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjìh²hh³jýh´MZubj¾)�”}”(hŒ__fpga_mgr_register”h]”j)�”}”(hj-h]”hŒ__fpga_mgr_register”…”�”}”(hjOh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjKubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hjìh²hh³jýh´MZubj)�”}”(hŒp(struct device *parent, const char *name, const struct fpga_manager_ops *mops, void *priv, struct module *owner)”h]”(j)�”}”(hŒstruct device *parent”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjjh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjfubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjwh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjfubh)�”}”(hhh]”j)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hjˆh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj…ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”jŠŒmodname”NŒ classname”Njj!)�”}”j$]”j+Œc.__fpga_mgr_register”†”asbuh1hhjfubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj¦h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjfubjç)�”}”(hj!h]”hŒ*”…”�”}”(hj´h²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjfubj)�”}”(hŒparent”h]”hŒparent”…”�”}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjfubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjbubj)�”}”(hŒconst char *name”h]”(j›)�”}”(hj‹h]”hŒconst”…”�”}”(hjÚh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjÖubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjçh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjÖubhŒdesc_sig_keyword_type”“”)�”}”(hŒchar”h]”hŒchar”…”�”}”(hj÷h²hh³Nh´Nubah}”(h]”h ]”Œkt”ah"]”h$]”h&]”uh1jõhjÖubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjÖubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjÖubj)�”}”(hŒname”h]”hŒname”…”�”}”(hj!h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjÖubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjbubj)�”}”(hŒ#const struct fpga_manager_ops *mops”h]”(j›)�”}”(hj‹h]”hŒconst”…”�”}”(hj:h²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj6ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjGh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj6ubj›)�”}”(hjµh]”hŒstruct”…”�”}”(hjUh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhj6ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjbh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj6ubh)�”}”(hhh]”j)�”}”(hŒfpga_manager_ops”h]”hŒfpga_manager_ops”…”�”}”(hjsh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjpubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”juŒmodname”NŒ classname”Njj!)�”}”j$]”j+Œc.__fpga_mgr_register”†”asbuh1hhj6ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj‘h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hj6ubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjŸh²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhj6ubj)�”}”(hŒmops”h]”hŒmops”…”�”}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj6ubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjbubj)�”}”(hŒ void *priv”h]”(jö)�”}”(hŒvoid”h]”hŒvoid”…”�”}”(hjÅh²hh³Nh´Nubah}”(h]”h ]”jah"]”h$]”h&]”uh1jõhjÁubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÓh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjÁubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjáh²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjÁubj)�”}”(hŒpriv”h]”hŒpriv”…”�”}”(hjîh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjÁubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjbubj)�”}”(hŒstruct module *owner”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubh)�”}”(hhh]”j)�”}”(hŒmodule”h]”hŒmodule”…”�”}”(hj%h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj"ubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”j'Œmodname”NŒ classname”Njj!)�”}”j$]”j+Œc.__fpga_mgr_register”†”asbuh1hhjubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjCh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjubjç)�”}”(hj!h]”hŒ*”…”�”}”(hjQh²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjubj)�”}”(hŒowner”h]”hŒowner”…”�”}”(hj^h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjubeh}”(h]”h ]”h"]”h$]”h&]”Œnoemph”ˆjejfuh1jhjbubeh}”(h]”h ]”h"]”h$]”h&]”jejfuh1j hjìh²hh³jýh´MZubeh}”(h]”h ]”h"]”h$]”h&]”jejfjÞˆuh1j”jßjàhjèh²hh³jýh´MZubah}”(h]”jãah ]”(jIjäeh"]”h$]”h&]”jèˆjé)jêhuh1jŽh³jýh´MZhjåh²hubjì)�”}”(hhh]”hÝ)�”}”(hŒ*create and register an FPGA Manager device”h]”hŒ*create and register an FPGA Manager device”…”�”}”(hjˆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´MZhj…h²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jëhjåh²hh³jýh´MZubeh}”(h]”h ]”(jŒfunction”eh"]”h$]”h&]”j jj j jj j‰j‰j‰uh1j‰h²hhjÈh³Nh´Nubj)�”}”(hXÉ**Parameters** ``struct device *parent`` fpga manager device from pdev ``const char *name`` fpga manager name ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ``void *priv`` fpga manager private data ``struct module *owner`` owner module containing the ops **Description** The caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters. **Return** pointer to struct fpga_manager pointer or ERR_PTR()”h]”(hÝ)�”}”(hŒ**Parameters**”h]”j)�”}”(hjªh]”hŒ Parameters”…”�”}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj¨ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M^hj¤ubjÌ)�”}”(hhh]”(jÑ)�”}”(hŒ8``struct device *parent`` fpga manager device from pdev ”h]”(j×)�”}”(hŒ``struct device *parent``”h]”j*)�”}”(hjÉh]”hŒstruct device *parent”…”�”}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjÇubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M[hjÃubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager device from pdev”h]”hŒfpga manager device from pdev”…”�”}”(hjâh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÞh´M[hjßubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjÃubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jÞh´M[hjÀubjÑ)�”}”(hŒ'``const char *name`` fpga manager name ”h]”(j×)�”}”(hŒ``const char *name``”h]”j*)�”}”(hjh]”hŒconst char *name”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M\hjüubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager name”h]”hŒfpga manager name”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jh´M\hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjüubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jh´M\hjÀubjÑ)�”}”(hŒQ``const struct fpga_manager_ops *mops`` pointer to structure of fpga manager ops ”h]”(j×)�”}”(hŒ'``const struct fpga_manager_ops *mops``”h]”j*)�”}”(hj;h]”hŒ#const struct fpga_manager_ops *mops”…”�”}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj9ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M]hj5ubjç)�”}”(hhh]”hÝ)�”}”(hŒ(pointer to structure of fpga manager ops”h]”hŒ(pointer to structure of fpga manager ops”…”�”}”(hjTh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jPh´M]hjQubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj5ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jPh´M]hjÀubjÑ)�”}”(hŒ)``void *priv`` fpga manager private data ”h]”(j×)�”}”(hŒ``void *priv``”h]”j*)�”}”(hjth]”hŒ void *priv”…”�”}”(hjvh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hjrubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M^hjnubjç)�”}”(hhh]”hÝ)�”}”(hŒfpga manager private data”h]”hŒfpga manager private data”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³j‰h´M^hjŠubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhjnubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³j‰h´M^hjÀubjÑ)�”}”(hŒ9``struct module *owner`` owner module containing the ops ”h]”(j×)�”}”(hŒ``struct module *owner``”h]”j*)�”}”(hj­h]”hŒstruct module *owner”…”�”}”(hj¯h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj«ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M_hj§ubjç)�”}”(hhh]”hÝ)�”}”(hŒowner module containing the ops”h]”hŒowner module containing the ops”…”�”}”(hjÆh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³jÂh´M_hjÃubah}”(h]”h ]”h"]”h$]”h&]”uh1jæhj§ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÐh³jÂh´M_hjÀubeh}”(h]”h ]”h"]”h$]”h&]”uh1jËhj¤ubhÝ)�”}”(hŒ**Description**”h]”j)�”}”(hjèh]”hŒ Description”…”�”}”(hjêh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjæubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´Mahj¤ubhÝ)�”}”(hXFThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters.”h]”hXFThe caller of this function is responsible for calling fpga_mgr_unregister(). Using devm_fpga_mgr_register() instead is recommended. This simple version of the register function should be sufficient for most users. The fpga_mgr_register_full() function is available for users that need to pass additional, optional parameters.”…”�”}”(hjþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´M`hj¤ubhÝ)�”}”(hŒ **Return**”h]”j)�”}”(hjh]”hŒReturn”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´Mfhj¤ubhÝ)�”}”(hŒ3pointer to struct fpga_manager pointer or ERR_PTR()”h]”hŒ3pointer to struct fpga_manager pointer or ERR_PTR()”…”�”}”(hj%h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:158: ./drivers/fpga/fpga-mgr.c”h´Mghj¤ubeh}”(h]”h ]”Œ kernelindent”ah"]”h$]”h&]”uh1jhjÈh²hh³Nh´Nubjy)�”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œentries”]”(j…Œ*__devm_fpga_mgr_register_full (C function)”Œc.__devm_fpga_mgr_register_full”hNt”auh1jxhjÈh²hh³Nh´NubjŠ)�”}”(hhh]”(j�)�”}”(hŒ‡struct fpga_manager * __devm_fpga_mgr_register_full (struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”j•)�”}”(hŒ…struct fpga_manager *__devm_fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjTh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjPh²hh³Œa/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-mgr:161: ./drivers/fpga/fpga-mgr.c”h´M“ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjbh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjPh²hh³jah´M“ubh)�”}”(hhh]”j)�”}”(hŒ fpga_manager”h]”hŒ fpga_manager”…”�”}”(hjsh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjpubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”juŒmodname”NŒ classname”Njj!)�”}”j$]”jÒ)�”}”jŒ__devm_fpga_mgr_register_full”sbŒc.__devm_fpga_mgr_register_full”†”asbuh1hhjPh²hh³jah´M“ubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj”h²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjPh²hh³jah´M“ubjç)�”}”(hj!h]”hŒ*”…”�”}”(hj¢h²hh³Nh´Nubah}”(h]”h ]”jòah"]”h$]”h&]”uh1jæhjPh²hh³jah´M“ubj¾)�”}”(hŒ__devm_fpga_mgr_register_full”h]”j)�”}”(hj‘h]”hŒ__devm_fpga_mgr_register_full”…”�”}”(hj³h²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhj¯ubah}”(h]”h ]”(jÓjÔeh"]”h$]”h&]”jejfuh1j½hjPh²hh³jah´M“ubj)�”}”(hŒS(struct device *parent, const struct fpga_manager_info *info, struct module *owner)”h]”(j)�”}”(hŒstruct device *parent”h]”(j›)�”}”(hjµh]”hŒstruct”…”�”}”(hjÎh²hh³Nh´Nubah}”(h]”h ]”j§ah"]”h$]”h&]”uh1jšhjÊubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hjÛh²hh³Nh´Nubah}”(h]”h ]”j¹ah"]”h$]”h&]”uh1j¬hjÊubh)�”}”(hhh]”j)�”}”(hŒdevice”h]”hŒdevice”…”�”}”(hjìh²hh³Nh´Nubah}”(h]”h ]”j ah"]”h$]”h&]”uh1jhjéubah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”jŒreftype”jŒ reftarget”jîŒmodname”NŒ classname”Njj!)�”}”j$]”j�Œc.__devm_fpga_mgr_register_full”†”asbuh1hhjÊubj­)�”}”(hŒ ”h]”hŒ ”…”�”}”(hj h²hh³Nh´Nubah}”(h]”h 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