sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget//translations/zh_CN/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/zh_TW/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/it_IT/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ja_JP/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ko_KR/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/sp_SP/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h FPGA Bridgeh]h FPGA Bridge}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhI/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge.rsthKubh)}(hhh](h)}(h"API to implement a new FPGA bridgeh]h"API to implement a new FPGA bridge}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh bullet_list)}(hhh](h list_item)}(h.struct fpga_bridge - The FPGA Bridge structureh]h paragraph)}(hhh]h.struct fpga_bridge - The FPGA Bridge structure}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h4struct fpga_bridge_ops - Low level Bridge driver opsh]h)}(hhh]h4struct fpga_bridge_ops - Low level Bridge driver ops}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h7__fpga_bridge_register() - Create and register a bridgeh]h)}(hjh]h7__fpga_bridge_register() - Create and register a bridge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h/fpga_bridge_unregister() - Unregister a bridge h]h)}(h.fpga_bridge_unregister() - Unregister a bridgeh]h.fpga_bridge_unregister() - Unregister a bridge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhhhubh)}(hvThe helper macro ``fpga_bridge_register()`` automatically sets the module that registers the FPGA bridge as the owner.h](hThe helper macro }(hj6hhhNhNubhliteral)}(h``fpga_bridge_register()``h]hfpga_bridge_register()}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj6ubhK automatically sets the module that registers the FPGA bridge as the owner.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlefpga_bridge (C struct) c.fpga_bridgehNtauh1jXhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(h fpga_bridgeh]hdesc_signature_line)}(hstruct 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container)}(hX**Definition**:: struct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; }; **Members** ``name`` name of low level FPGA bridge ``dev`` FPGA bridge device ``mutex`` enforces exclusive reference to bridge ``br_ops`` pointer to struct of FPGA bridge ops ``br_ops_owner`` module containing the br_ops ``info`` fpga image specific information ``node`` FPGA bridge list node ``priv`` low level driver private dateh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK/hjubh literal_block)}(hstruct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; };h]hstruct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; };}hj sbah}(h]h ]h"]h$]h&]jjuh1jhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK1hjubh)}(h **Members**h]j)}(hj1h]hMembers}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhKhjTubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK-hjNubh definition)}(hhh]h)}(hname of low level FPGA bridgeh]hname of low level FPGA bridge}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhK-hjnubah}(h]h ]h"]h$]h&]uh1jlhjNubeh}(h]h ]h"]h$]h&]uh1jLhjkhK-hjIubjM)}(h``dev`` FPGA bridge device h](jS)}(h``dev``h]j?)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK.hjubjm)}(hhh]h)}(hFPGA bridge deviceh]hFPGA bridge device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK.hjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ]h"]h$]h&]uh1jLhjhK.hjIubjM)}(h1``mutex`` enforces exclusive reference to bridge h](jS)}(h ``mutex``h]j?)}(hjh]hmutex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK/hjubjm)}(hhh]h)}(h&enforces exclusive reference to bridgeh]h&enforces exclusive reference to bridge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK/hjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ]h"]h$]h&]uh1jLhjhK/hjIubjM)}(h0``br_ops`` pointer to struct of FPGA bridge ops h](jS)}(h ``br_ops``h]j?)}(hjh]hbr_ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h 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]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubj)}(hstruct fpga_bridge_ops { int (*enable_show)(struct fpga_bridge *bridge); int (*enable_set)(struct fpga_bridge *bridge, bool enable); void (*fpga_bridge_remove)(struct fpga_bridge *bridge); const struct attribute_group **groups; };h]hstruct fpga_bridge_ops { int (*enable_show)(struct fpga_bridge *bridge); int (*enable_set)(struct fpga_bridge *bridge, bool enable); void (*fpga_bridge_remove)(struct fpga_bridge *bridge); const struct attribute_group **groups; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubh)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubjH)}(hhh](jM)}(h1``enable_show`` returns the FPGA bridge's status h](jS)}(h``enable_show``h]j?)}(hjh]h enable_show}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubjm)}(hhh]h)}(h returns the FPGA bridge's statush]h"returns the FPGA bridge’s status}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhKhjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ]h"]h$]h&]uh1jLhjhKhjubjM)}(h9``enable_set`` set an FPGA bridge as enabled or disabled h](jS)}(h``enable_set``h]j?)}(hj)h]h enable_set}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj'ubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhj#ubjm)}(hhh]h)}(h)set an FPGA bridge as enabled or disabledh]h)set an FPGA bridge as enabled or disabled}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hKhj?ubah}(h]h ]h"]h$]h&]uh1jlhj#ubeh}(h]h ]h"]h$]h&]uh1jLhj>hKhjubjM)}(hK``fpga_bridge_remove`` set FPGA into a specific state during driver remove h](jS)}(h``fpga_bridge_remove``h]j?)}(hjbh]hfpga_bridge_remove}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj`ubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhj\ubjm)}(hhh]h)}(h3set FPGA into a specific state during driver removeh]h3set FPGA into a specific state during driver remove}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhKhjxubah}(h]h ]h"]h$]h&]uh1jlhj\ubeh}(h]h ]h"]h$]h&]uh1jLhjwhKhjubjM)}(h%``groups`` optional attribute groups.h](jS)}(h ``groups``h]j?)}(hjh]hgroups}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h ]h"]h$]h&]uh1jRhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubjm)}(hhh]h)}(hoptional attribute groups.h]hoptional attribute groups.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:18: ./include/linux/fpga/fpga-bridge.hhKhjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h 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ASTIdentifier)}j*__fpga_bridge_registersbc.__fpga_bridge_registerasbuh1hhjhhhjhMKubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMKubhdesc_sig_punctuation)}(hj5h]h*}(hjMhhhNhNubah}(h]h ]pah"]h$]h&]uh1jKhjhhhjhMKubj)}(h__fpga_bridge_registerh]j)}(hj:h]h__fpga_bridge_register}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMKubhdesc_parameterlist)}(hq(struct device *parent, const char *name, const struct fpga_bridge_ops *br_ops, void *priv, struct module *owner)h](hdesc_parameter)}(hstruct device *parenth](j{)}(hj~h]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej* reftargetjmodnameN classnameNj.j1)}j4]j8c.__fpga_bridge_registerasbuh1hhjzubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubjL)}(hj5h]h*}(hjhhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhjzubj)}(hparenth]hparent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjtubjy)}(hconst char *nameh](j{)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_keyword_type)}(hcharh]hchar}(hj hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjL)}(hj5h]h*}(hj)hhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhjubj)}(hnameh]hname}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjtubjy)}(h$const struct fpga_bridge_ops *br_opsh](j{)}(hjh]hconst}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjKubj)}(h h]h }(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubj{)}(hj~h]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjKubj)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubh)}(hhh]j)}(hfpga_bridge_opsh]hfpga_bridge_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej* reftargetjmodnameN classnameNj.j1)}j4]j8c.__fpga_bridge_registerasbuh1hhjKubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubjL)}(hj5h]h*}(hjhhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhjKubj)}(hbr_opsh]hbr_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjtubjy)}(h void *privh](j )}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1j hjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjL)}(hj5h]h*}(hjhhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhjubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjtubjy)}(hstruct module *ownerh](j{)}(hj~h]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhjubj)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hmoduleh]hmodule}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&] refdomainjreftypej* reftargetj<modnameN classnameNj.j1)}j4]j8c.__fpga_bridge_registerasbuh1hhjubj)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjL)}(hj5h]h*}(hjfhhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhjubj)}(hownerh]howner}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjtubeh}(h]h ]h"]h$]h&]jjuh1jrhjhhhjhMKubeh}(h]h ]h"]h$]h&]jjjuh1jtjjhjhhhjhMKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jnhjhMKhjhhubj)}(hhh]h)}(h)create and register an FPGA Bridge deviceh]h)create and register an FPGA Bridge device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMBhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1jihhhhhNhNubj)}(hXd**Parameters** ``struct device *parent`` FPGA bridge device from pdev ``const char *name`` FPGA bridge name ``const struct fpga_bridge_ops *br_ops`` pointer to structure of fpga bridge ops ``void *priv`` FPGA bridge private data ``struct module *owner`` owner module containing the br_ops **Return** struct fpga_bridge pointer or ERR_PTR()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMFhjubjH)}(hhh](jM)}(h7``struct device *parent`` FPGA bridge device from pdev h](jS)}(h``struct device *parent``h]j?)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j>hjubah}(h]h ]h"]h$]h&]uh1jRhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMChjubjm)}(hhh]h)}(hFPGA bridge device from pdevh]hFPGA bridge device from pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhMChjubah}(h]h ]h"]h$]h&]uh1jlhjubeh}(h]h ]h"]h$]h&]uh1jLhjhMChjubjM)}(h&``const char *name`` FPGA bridge name h](jS)}(h``const char *name``h]j?)}(hj h]hconst char *name}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj ubah}(h]h ]h"]h$]h&]uh1jRhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMDhj ubjm)}(hhh]h)}(hFPGA bridge nameh]hFPGA bridge name}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj, hMDhj- ubah}(h]h ]h"]h$]h&]uh1jlhj ubeh}(h]h ]h"]h$]h&]uh1jLhj, hMDhjubjM)}(hQ``const struct fpga_bridge_ops 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module *owner`` owner module containing the br_ops h](jS)}(h``struct module *owner``h]j?)}(hj h]hstruct module *owner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j>hj ubah}(h]h ]h"]h$]h&]uh1jRhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMGhj ubjm)}(hhh]h)}(h"owner module containing the br_opsh]h"owner module containing the br_ops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMGhj ubah}(h]h ]h"]h$]h&]uh1jlhj ubeh}(h]h ]h"]h$]h&]uh1jLhj hMGhjubeh}(h]h ]h"]h$]h&]uh1jGhjubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMIhjubh)}(h'struct fpga_bridge pointer or ERR_PTR()h]h'struct fpga_bridge pointer or ERR_PTR()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMIhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhhhhhNhNubjY)}(hhh]h}(h]h ]h"]h$]h&]entries](je#fpga_bridge_unregister (C function)c.fpga_bridge_unregisterhNtauh1jXhhhhhNhNubjj)}(hhh](jo)}(h8void fpga_bridge_unregister (struct fpga_bridge *bridge)h]ju)}(h7void fpga_bridge_unregister(struct fpga_bridge *bridge)h](j )}(hvoidh]hvoid}(hjB hhhNhNubah}(h]h ]jah"]h$]h&]uh1j hj> hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:24: ./drivers/fpga/fpga-bridge.chMubj)}(h h]h }(hjQ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj> hhhjP hMubj)}(hfpga_bridge_unregisterh]j)}(hfpga_bridge_unregisterh]hfpga_bridge_unregister}(hjc hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ ubah}(h]h ](jjeh"]h$]h&]jjuh1jhj> hhhjP hMubjs)}(h(struct fpga_bridge *bridge)h]jy)}(hstruct fpga_bridge *bridgeh](j{)}(hj~h]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jzhj{ ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubh)}(hhh]j)}(h fpga_bridgeh]h fpga_bridge}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej* reftargetj modnameN classnameNj.j1)}j4]j7)}j*je sbc.fpga_bridge_unregisterasbuh1hhj{ ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubjL)}(hj5h]h*}(hj hhhNhNubah}(h]h ]jWah"]h$]h&]uh1jKhj{ ubj)}(hbridgeh]hbridge}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ ubeh}(h]h ]h"]h$]h&]noemphjjuh1jxhjw ubah}(h]h ]h"]h$]h&]jjuh1jrhj> hhhjP hMubeh}(h]h ]h"]h$]h&]jjjuh1jtjjhj: hhhjP hMubah}(h]j5 ah ](jjeh"]h$]h&]jj)jhuh1jnhjP hMhj7 hhubj)}(hhh]h)}(hunregister an FPGA bridgeh]hunregister an FPGA bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:24: ./drivers/fpga/fpga-bridge.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhj7 hhhjP hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1jihhhhhNhNubj)}(h**Parameters** ``struct fpga_bridge *bridge`` FPGA bridge struct **Description** This function is intended for use in an FPGA bridge driver's remove function.h](h)}(h**Parameters**h]j)}(hj$ h]h Parameters}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj" ubah}(h]h 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