sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget//translations/zh_CN/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/zh_TW/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/it_IT/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ja_JP/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ko_KR/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/pt_BR/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/sp_SP/driver-api/fpga/fpga-bridgemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h FPGA Bridgeh]h FPGA Bridge}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhI/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge.rsthKubh)}(hhh](h)}(h"API to implement a new FPGA bridgeh]h"API to implement a new FPGA bridge}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh bullet_list)}(hhh](h list_item)}(h.struct fpga_bridge - The FPGA Bridge structureh]h paragraph)}(hhh]h.struct fpga_bridge - The FPGA Bridge structure}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h4struct fpga_bridge_ops - Low level Bridge driver opsh]h)}(hhh]h4struct fpga_bridge_ops - Low level Bridge driver ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h7__fpga_bridge_register() - Create and register a bridgeh]h)}(hjh]h7__fpga_bridge_register() - Create and register a bridge}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h/fpga_bridge_unregister() - Unregister a bridge h]h)}(h.fpga_bridge_unregister() - Unregister a bridgeh]h.fpga_bridge_unregister() - Unregister a bridge}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj*ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhKhhhhubh)}(hvThe helper macro ``fpga_bridge_register()`` automatically sets the module that registers the FPGA bridge as the owner.h](hThe helper macro }(hjJhhhNhNubhliteral)}(h``fpga_bridge_register()``h]hfpga_bridge_register()}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjJubhK automatically sets the module that registers the FPGA bridge as the owner.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlefpga_bridge (C struct) c.fpga_bridgehNtauh1jlhhhhhNhNubhdesc)}(hhh](hdesc_signature)}(h fpga_bridgeh]hdesc_signature_line)}(hstruct fpga_bridgeh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(h fpga_bridgeh]h desc_sig_name)}(hjh]h fpga_bridge}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&] xml:spacepreserveuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhjhKubah}(h]j{ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhjhKhjhhubh desc_content)}(hhh]h)}(hFPGA bridge structureh]hFPGA bridge structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK+hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j}hhhhhNhNubh container)}(hX**Definition**:: struct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; }; **Members** ``name`` name of low level FPGA bridge ``dev`` FPGA bridge device ``mutex`` enforces exclusive reference to bridge ``br_ops`` pointer to struct of FPGA bridge ops ``br_ops_owner`` module containing the br_ops ``info`` fpga image specific information ``node`` FPGA bridge list node ``priv`` low level driver private dateh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK/hjubh literal_block)}(hstruct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; };h]hstruct fpga_bridge { const char *name; struct device dev; struct mutex mutex; const struct fpga_bridge_ops *br_ops; struct module *br_ops_owner; struct fpga_image_info *info; struct list_head node; void *priv; };}hj4sbah}(h]h ]h"]h$]h&]jjuh1j2hl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK1hjubh)}(h **Members**h]j)}(hjEh]hMembers}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1hhl/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:15: ./include/linux/fpga/fpga-bridge.hhK__fpga_bridge_registersbc.__fpga_bridge_registerasbuh1hhjhhhjhMBubj)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhMBubhdesc_sig_punctuation)}(hjIh]h*}(hjahhhNhNubah}(h]h ]pah"]h$]h&]uh1j_hjhhhjhMBubj)}(h__fpga_bridge_registerh]j)}(hjNh]h__fpga_bridge_register}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ](jjeh"]h$]h&]jjuh1jhjhhhjhMBubhdesc_parameterlist)}(hq(struct device *parent, const char *name, const struct fpga_bridge_ops *br_ops, void *priv, struct module *owner)h](hdesc_parameter)}(hstruct device *parenth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubh)}(hhh]j)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej> reftargetjmodnameN classnameNjBjE)}jH]jLc.__fpga_bridge_registerasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj`)}(hjIh]h*}(hjhhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hjubj)}(hparenth]hparent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hconst char *nameh](j)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubhdesc_sig_keyword_type)}(hcharh]hchar}(hj hhhNhNubah}(h]h ]ktah"]h$]h&]uh1jhjubj)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj`)}(hjIh]h*}(hj=hhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hjubj)}(hnameh]hname}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h$const struct fpga_bridge_ops *br_opsh](j)}(hjh]hconst}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubh)}(hhh]j)}(hfpga_bridge_opsh]hfpga_bridge_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjreftypej> reftargetjmodnameN classnameNjBjE)}jH]jLc.__fpga_bridge_registerasbuh1hhj_ubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj`)}(hjIh]h*}(hjhhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hj_ubj)}(hbr_opsh]hbr_ops}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(h void *privh](j)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j+ah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj`)}(hjIh]h*}(hj hhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hjubj)}(hprivh]hpriv}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubh)}(hhh]j)}(hmoduleh]hmodule}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&] refdomainjreftypej> reftargetjPmodnameN classnameNjBjE)}jH]jLc.__fpga_bridge_registerasbuh1hhj,ubj)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj`)}(hjIh]h*}(hjzhhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hj,ubj)}(hownerh]howner}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhhhjhMBubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjhhhjhMBubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1jhjhMBhjhhubj)}(hhh]h)}(h)create and register an FPGA Bridge deviceh]h)create and register an FPGA Bridge device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMBhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMBubeh}(h]h ](jfunctioneh"]h$]h&]jjjjj jj j j uh1j}hhhhhNhNubj)}(hXd**Parameters** ``struct device *parent`` FPGA bridge device from pdev ``const char *name`` FPGA bridge name ``const struct fpga_bridge_ops *br_ops`` pointer to structure of fpga bridge ops ``void *priv`` FPGA bridge private data ``struct module *owner`` owner module containing the br_ops **Return** struct fpga_bridge pointer or ERR_PTR()h](h)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMFhjubj\)}(hhh](ja)}(h7``struct device *parent`` FPGA bridge device from pdev h](jg)}(h``struct device *parent``h]jS)}(hjh]hstruct device *parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjubah}(h]h ]h"]h$]h&]uh1jfhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMChjubj)}(hhh]h)}(hFPGA bridge device from pdevh]hFPGA bridge device from pdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMChj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j`hj hMChjubja)}(h&``const char *name`` FPGA bridge name h](jg)}(h``const char *name``h]jS)}(hj+ h]hconst char *name}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj) ubah}(h]h ]h"]h$]h&]uh1jfhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMDhj% ubj)}(hhh]h)}(hFPGA bridge nameh]hFPGA bridge name}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ hMDhjA ubah}(h]h ]h"]h$]h&]uh1jhj% ubeh}(h]h ]h"]h$]h&]uh1j`hj@ hMDhjubja)}(hQ``const struct fpga_bridge_ops *br_ops`` pointer to structure of fpga bridge ops h](jg)}(h(``const struct fpga_bridge_ops *br_ops``h]jS)}(hjd h]h$const struct fpga_bridge_ops *br_ops}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhjb ubah}(h]h ]h"]h$]h&]uh1jfhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMEhj^ ubj)}(hhh]h)}(h'pointer to structure of fpga bridge opsh]h'pointer to structure of fpga bridge ops}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjy hMEhjz ubah}(h]h ]h"]h$]h&]uh1jhj^ ubeh}(h]h ]h"]h$]h&]uh1j`hjy hMEhjubja)}(h(``void *priv`` FPGA bridge private data h](jg)}(h``void *priv``h]jS)}(hj h]h void *priv}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jfhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMFhj ubj)}(hhh]h)}(hFPGA bridge private datah]hFPGA bridge private data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMFhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j`hj hMFhjubja)}(h<``struct module *owner`` owner module containing the br_ops h](jg)}(h``struct module *owner``h]jS)}(hj h]hstruct module *owner}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jRhj ubah}(h]h ]h"]h$]h&]uh1jfhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMGhj ubj)}(hhh]h)}(h"owner module containing the br_opsh]h"owner module containing the br_ops}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hMGhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j`hj hMGhjubeh}(h]h ]h"]h$]h&]uh1j[hjubh)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMIhjubh)}(h'struct fpga_bridge pointer or ERR_PTR()h]h'struct fpga_bridge pointer or ERR_PTR()}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:21: ./drivers/fpga/fpga-bridge.chMIhjubeh}(h]h ] kernelindentah"]h$]h&]uh1j hhhhhNhNubjm)}(hhh]h}(h]h ]h"]h$]h&]entries](jy#fpga_bridge_unregister (C function)c.fpga_bridge_unregisterhNtauh1jlhhhhhNhNubj~)}(hhh](j)}(h8void fpga_bridge_unregister (struct fpga_bridge *bridge)h]j)}(h7void fpga_bridge_unregister(struct fpga_bridge *bridge)h](j)}(hvoidh]hvoid}(hjV hhhNhNubah}(h]h ]j+ah"]h$]h&]uh1jhjR hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:24: ./drivers/fpga/fpga-bridge.chMubj)}(h h]h }(hje hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR hhhjd hMubj)}(hfpga_bridge_unregisterh]j)}(hfpga_bridge_unregisterh]hfpga_bridge_unregister}(hjw hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs ubah}(h]h ](jjeh"]h$]h&]jjuh1jhjR hhhjd hMubj)}(h(struct fpga_bridge *bridge)h]j)}(hstruct fpga_bridge *bridgeh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubh)}(hhh]j)}(h fpga_bridgeh]h fpga_bridge}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjreftypej> reftargetj modnameN classnameNjBjE)}jH]jK)}j>jy sbc.fpga_bridge_unregisterasbuh1hhj ubj)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj`)}(hjIh]h*}(hj hhhNhNubah}(h]h ]jkah"]h$]h&]uh1j_hj ubj)}(hbridgeh]hbridge}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphjjuh1jhj ubah}(h]h ]h"]h$]h&]jjuh1jhjR hhhjd hMubeh}(h]h ]h"]h$]h&]jjjuh1jjjhjN hhhjd hMubah}(h]jI ah ](jjeh"]h$]h&]jj)jhuh1jhjd hMhjK hhubj)}(hhh]h)}(hunregister an FPGA bridgeh]hunregister an FPGA bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:24: ./drivers/fpga/fpga-bridge.chMhj hhubah}(h]h ]h"]h$]h&]uh1jhjK hhhjd hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj. j j. j j j uh1j}hhhhhNhNubj)}(h**Parameters** ``struct fpga_bridge *bridge`` FPGA bridge struct **Description** This function is intended for use in an FPGA bridge driver's remove function.h](h)}(h**Parameters**h]j)}(hj8 h]h Parameters}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6 ubah}(h]h ]h"]h$]h&]uh1hhf/var/lib/git/docbuild/linux/Documentation/driver-api/fpga/fpga-bridge:24: ./drivers/fpga/fpga-bridge.chMhj2 ubj\)}(hhh]ja)}(h2``struct fpga_bridge *bridge`` FPGA bridge struct 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