sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/driver-api/dpllmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/driver-api/dpll.rsthKubhsection)}(hhh](htitle)}(hThe Linux kernel dpll subsystemh]hThe Linux kernel dpll subsystem}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDPLLh]hDPLL}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hPLL - Phase Locked Loop is an electronic circuit which syntonizes clock signal of a device with an external clock signal. Effectively enabling device to run on the same clock signal beat as provided on a PLL input.h]hPLL - Phase Locked Loop is an electronic circuit which syntonizes clock signal of a device with an external clock signal. Effectively enabling device to run on the same clock signal beat as provided on a PLL input.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hDPLL - Digital Phase Locked Loop is an integrated circuit which in addition to plain PLL behavior incorporates a digital phase detector and may have digital divider in the loop. As a result, the frequency on DPLL's input and output may be configurable.h]hDPLL - Digital Phase Locked Loop is an integrated circuit which in addition to plain PLL behavior incorporates a digital phase detector and may have digital divider in the loop. As a result, the frequency on DPLL’s input and output may be configurable.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]dpllah ]h"]dpllah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Subsystemh]h Subsystem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXIThe main purpose of dpll subsystem is to provide general interface to configure devices that use any kind of Digital PLL and could use different sources of input signal to synchronize to, as well as different types of outputs. The main interface is NETLINK_GENERIC based protocol with an event monitoring multicast group defined.h]hXIThe main purpose of dpll subsystem is to provide general interface to configure devices that use any kind of Digital PLL and could use different sources of input signal to synchronize to, as well as different types of outputs. The main interface is NETLINK_GENERIC based protocol with an event monitoring multicast group defined.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] subsystemah ]h"] subsystemah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Device objecth]h Device object}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhKubh)}(hXSingle dpll device object means single Digital PLL circuit and bunch of connected pins. It reports the supported modes of operation and current status to the user in response to the `do` request of netlink command ``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem with `dump` netlink request of the same command. Changing the configuration of dpll device is done with `do` request of netlink ``DPLL_CMD_DEVICE_SET`` command. A device handle is ``DPLL_A_ID``, it shall be provided to get or set configuration of particular device in the system. It can be obtained with a ``DPLL_CMD_DEVICE_GET`` `dump` request or a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide attributes that result in single device match.h](hSingle dpll device object means single Digital PLL circuit and bunch of connected pins. It reports the supported modes of operation and current status to the user in response to the }(hj8hhhNhNubhtitle_reference)}(h`do`h]hdo}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj8ubh request of netlink command }(hj8hhhNhNubhliteral)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj8ubh4 and list of dplls registered in the subsystem with }(hj8hhhNhNubjA)}(h`dump`h]hdump}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj8ubh] netlink request of the same command. Changing the configuration of dpll device is done with }(hj8hhhNhNubjA)}(h`do`h]hdo}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj8ubh request of netlink }(hj8hhhNhNubjU)}(h``DPLL_CMD_DEVICE_SET``h]hDPLL_CMD_DEVICE_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj8ubh command. A device handle is }(hj8hhhNhNubjU)}(h ``DPLL_A_ID``h]h DPLL_A_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj8ubhq, it shall be provided to get or set configuration of particular device in the system. It can be obtained with a }(hj8hhhNhNubjU)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj8ubh }(hj8hhhNhNubjA)}(h`dump`h]hdump}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj8ubh request or a }(hj8hhhNhNubjU)}(h``DPLL_CMD_DEVICE_ID_GET``h]hDPLL_CMD_DEVICE_ID_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj8ubh }hj8sbjA)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hj8ubhS request, where the one must provide attributes that result in single device match.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hj'hhubeh}(h] device-objectah ]h"] device objectah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Pin objecth]h Pin object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK/ubh)}(hXyA pin is amorphic object which represents either input or output, it could be internal component of the device, as well as externally connected. The number of pins per dpll vary, but usually multiple pins shall be provided for a single dpll device. Pin's properties, capabilities and status is provided to the user in response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. It is also possible to list all the pins that were registered in the system with `dump` request of ``DPLL_CMD_PIN_GET`` command. Configuration of a pin can be changed by `do` request of netlink ``DPLL_CMD_PIN_SET`` command. Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set configuration of particular pin in the system. It can be obtained with ``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` request, where user provides attributes that result in single pin match.h](hXLA pin is amorphic object which represents either input or output, it could be internal component of the device, as well as externally connected. The number of pins per dpll vary, but usually multiple pins shall be provided for a single dpll device. Pin’s properties, capabilities and status is provided to the user in response to }(hjhhhNhNubjA)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh request of netlink }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh[ command. It is also possible to list all the pins that were registered in the system with }(hjhhhNhNubjA)}(h`dump`h]hdump}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh request of }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh3 command. Configuration of a pin can be changed by }(hjhhhNhNubjA)}(h`do`h]hdo}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh request of netlink }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_SET``h]hDPLL_CMD_PIN_SET}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh command. Pin handle is a }(hjhhhNhNubjU)}(h``DPLL_A_PIN_ID``h]h DPLL_A_PIN_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhl, it shall be provided to get or set configuration of particular pin in the system. It can be obtained with }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh }(hjhhhNhNubjA)}(h`dump`h]hdump}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh request or }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_ID_GET``h]hDPLL_CMD_PIN_ID_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh }hjsbjA)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubhI request, where user provides attributes that result in single pin match.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjhhubeh}(h] pin-objectah ]h"] pin objectah$]h&]uh1hhhhhhhhK/ubh)}(hhh](h)}(h Pin selectionh]h Pin selection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hIn general, selected pin (the one which signal is driving the dpll device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll device.h](h`In general, selected pin (the one which signal is driving the dpll device) can be obtained from }(hjhhhNhNubjU)}(h``DPLL_A_PIN_STATE``h]hDPLL_A_PIN_STATE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh) attribute, and only one pin shall be in }(hjhhhNhNubjU)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh state for any dpll device.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hX<Pin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (``DPLL_A_MODE`` attribute). The consequence is that there are differences for each mode in terms of available pin states, as well as for the states the user can request for a dpll device.h](hPin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (}(hj6hhhNhNubjU)}(h``DPLL_A_MODE``h]h DPLL_A_MODE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj6ubh attribute). The consequence is that there are differences for each mode in terms of available pin states, as well as for the states the user can request for a dpll device.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubh)}(hbIn manual mode (``DPLL_MODE_MANUAL``) the user can request or receive one of following pin states:h](hIn manual mode (}(hjVhhhNhNubjU)}(h``DPLL_MODE_MANUAL``h]hDPLL_MODE_MANUAL}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjVubh>) the user can request or receive one of following pin states:}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKOhjhhubh bullet_list)}(hhh](h list_item)}(hC``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll deviceh]h)}(hjh](jU)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh' - the pin is used to drive dpll device}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKRhj}ubah}(h]h ]h"]h$]h&]uh1j{hjxhhhhhNubj|)}(hK``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll device h]h)}(hJ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll deviceh](jU)}(h``DPLL_PIN_STATE_DISCONNECTED``h]hDPLL_PIN_STATE_DISCONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh+ - the pin is not used to drive dpll device}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKShjubah}(h]h ]h"]h$]h&]uh1j{hjxhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jvhhhKRhjhhubh)}(hhIn automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or receive one of following pin states:h](hIn automatic mode (}(hjhhhNhNubjU)}(h``DPLL_MODE_AUTOMATIC``h]hDPLL_MODE_AUTOMATIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh>) the user can request or receive one of following pin states:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKVhjhhubjw)}(hhh](j|)}(hl``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithmh]h)}(hl``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithmh](jU)}(h``DPLL_PIN_STATE_SELECTABLE``h]hDPLL_PIN_STATE_SELECTABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhO - the pin shall be considered as valid input for automatic selection algorithm}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1j{hjhhhhhNubj|)}(hu``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithm h]h)}(ht``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithmh](jU)}(h``DPLL_PIN_STATE_DISCONNECTED``h]hDPLL_PIN_STATE_DISCONNECTED}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhU - the pin shall be not considered as a valid input for automatic selection algorithm}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK[hjubah}(h]h ]h"]h$]h&]uh1j{hjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jvhhhKYhjhhubh)}(hIn automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection algorithm locks a dpll device with one of the inputs.h](hIn automatic mode (}(hjEhhhNhNubjU)}(h``DPLL_MODE_AUTOMATIC``h]hDPLL_MODE_AUTOMATIC}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjEubh&) the user can only receive pin state }(hjEhhhNhNubjU)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjEubhO once automatic selection algorithm locks a dpll device with one of the inputs.}(hjEhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubeh}(h] pin-selectionah ]h"] pin selectionah$]h&]uh1hhhhhhhhKBubh)}(hhh](h)}(h Shared pinsh]h Shared pins}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKcubh)}(hoA single pin object can be attached to multiple dpll devices. Then there are two groups of configuration knobs:h]hoA single pin object can be attached to multiple dpll devices. Then there are two groups of configuration knobs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehjhhubhenumerated_list)}(hhh](j|)}(hpSet on a pin - the configuration affects all dpll devices pin is registered to (i.e., ``DPLL_A_PIN_FREQUENCY``),h]h)}(hpSet on a pin - the configuration affects all dpll devices pin is registered to (i.e., ``DPLL_A_PIN_FREQUENCY``),h](hVSet on a pin - the configuration affects all dpll devices pin is registered to (i.e., }(hjhhhNhNubjU)}(h``DPLL_A_PIN_FREQUENCY``h]hDPLL_A_PIN_FREQUENCY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh),}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1j{hjhhhhhNubj|)}(hSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, ``DPLL_A_PIN_DIRECTION``). h]h)}(hSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, ``DPLL_A_PIN_DIRECTION``).h](hUSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PRIO``h]hDPLL_A_PIN_PRIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh, }(hjhhhNhNubjU)}(h``DPLL_A_PIN_STATE``h]hDPLL_A_PIN_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh, }(hjhhhNhNubjU)}(h``DPLL_A_PIN_DIRECTION``h]hDPLL_A_PIN_DIRECTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1j{hjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jhjhhhhhKhubeh}(h] shared-pinsah ]h"] shared pinsah$]h&]uh1hhhhhhhhKcubh)}(hhh](h)}(h MUX-type pinsh]h MUX-type pins}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhKoubh)}(hXCA pin can be MUX-type, it aggregates child pins and serves as a pin multiplexer. One or more pins are registered with MUX-type instead of being directly registered to a dpll device. Pins registered with a MUX-type pin provide user with additional nested attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered with. If a pin was registered with multiple parent pins, they behave like a multiple output multiplexer. In this case output of a ``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested attributes with current state related to each parent, like::h](hXA pin can be MUX-type, it aggregates child pins and serves as a pin multiplexer. One or more pins are registered with MUX-type instead of being directly registered to a dpll device. Pins registered with a MUX-type pin provide user with additional nested attribute }(hj?hhhNhNubjU)}(h``DPLL_A_PIN_PARENT_PIN``h]hDPLL_A_PIN_PARENT_PIN}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj?ubh for each parent they were registered with. If a pin was registered with multiple parent pins, they behave like a multiple output multiplexer. In this case output of a }(hj?hhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj?ubhe would contain multiple pin-parent nested attributes with current state related to each parent, like:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKqhj.hhubh literal_block)}(h'pin': [{{ 'clock-id': 282574471561216, 'module-name': 'ice', 'capabilities': 4, 'id': 13, 'parent-pin': [ {'parent-id': 2, 'state': 'connected'}, {'parent-id': 3, 'state': 'disconnected'} ], 'type': 'synce-eth-port' }}]h]h'pin': [{{ 'clock-id': 282574471561216, 'module-name': 'ice', 'capabilities': 4, 'id': 13, 'parent-pin': [ {'parent-id': 2, 'state': 'connected'}, {'parent-id': 3, 'state': 'disconnected'} ], 'type': 'synce-eth-port' }}]}hjssbah}(h]h ]h"]h$]h&]hhuh1jqhhhK|hj.hhubh)}(hXOnly one child pin can provide its signal to the parent MUX-type pin at a time, the selection is done by requesting change of a child pin state on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested attribute. Example of netlink `set state on parent pin` message format:h](hOnly one child pin can provide its signal to the parent MUX-type pin at a time, the selection is done by requesting change of a child pin state on desired parent, with the use of }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PARENT``h]hDPLL_A_PIN_PARENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh& nested attribute. Example of netlink }(hjhhhNhNubjA)}(h`set state on parent pin`h]hset state on parent pin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh message format:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj.hhubh block_quote)}(hX========================== ============================================= ``DPLL_A_PIN_ID`` child pin id ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration related to parent pin ``DPLL_A_PIN_PARENT_ID`` parent pin id ``DPLL_A_PIN_STATE`` requested pin state on parent ========================== ============================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h``DPLL_A_PIN_ID``h]jU)}(hjh]h DPLL_A_PIN_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h child pin idh]h child pin id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_PIN``h]jU)}(hj*h]hDPLL_A_PIN_PARENT_PIN}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj(ubah}(h]h ]h"]h$]h&]uh1hhhhKhj%ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]h)}(hCnested attribute for requesting configuration related to parent pinh]hCnested attribute for requesting configuration related to parent pin}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjEubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]jU)}(hjjh]hDPLL_A_PIN_PARENT_ID}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjhubah}(h]h ]h"]h$]h&]uh1hhhhKhjeubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(hhh]h)}(h parent pin idh]h parent pin id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_STATE``h]jU)}(hjh]hDPLL_A_PIN_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hrequested pin state on parenth]hrequested pin state on parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhKhj.hhubeh}(h] mux-type-pinsah ]h"] mux-type pinsah$]h&]uh1hhhhhhhhKoubh)}(hhh](h)}(h Pin priorityh]h Pin priority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXSome devices might offer a capability of automatic pin selection mode (enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). Usually, automatic selection is performed on the hardware level, which means only pins directly connected to the dpll can be used for automatic input pin selection. In automatic selection mode, the user cannot manually select a input pin for the device, instead the user shall provide all directly connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would pick a highest priority valid signal and use it to control the DPLL device. Example of netlink `set priority on parent pin` message format:h](hRSome devices might offer a capability of automatic pin selection mode (enum value }(hjhhhNhNubjU)}(h``DPLL_MODE_AUTOMATIC``h]hDPLL_MODE_AUTOMATIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh of }(hjhhhNhNubjU)}(h``DPLL_A_MODE``h]h DPLL_A_MODE}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhXV attribute). Usually, automatic selection is performed on the hardware level, which means only pins directly connected to the dpll can be used for automatic input pin selection. In automatic selection mode, the user cannot manually select a input pin for the device, instead the user shall provide all directly connected pins with a priority }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PRIO``h]hDPLL_A_PIN_PRIO}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhr, the device would pick a highest priority valid signal and use it to control the DPLL device. Example of netlink }(hjhhhNhNubjA)}(h`set priority on parent pin`h]hset priority on parent pin}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j@hjubh message format:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX============================ ============================================= ``DPLL_A_PIN_ID`` configured pin id ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration related to parent dpll device ``DPLL_A_PIN_PARENT_ID`` parent dpll device id ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll ============================ ============================================= h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjqubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jhjqubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ID``h]jU)}(hjh]h DPLL_A_PIN_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hconfigured pin idh]hconfigured pin id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_DEVICE``h]jU)}(hjh]hDPLL_A_PIN_PARENT_DEVICE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKnested attribute for requesting configuration related to parent dpll deviceh]hKnested attribute for requesting configuration related to parent dpll device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]jU)}(hjh]hDPLL_A_PIN_PARENT_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hparent dpll device idh]hparent dpll device id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj.ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PRIO``h]jU)}(hjSh]hDPLL_A_PIN_PRIO}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjQubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1jhjKubj)}(hhh]h)}(h!requested pin prio on parent dpllh]h!requested pin prio on parent dpll}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]colsKuh1jhjnubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubh)}(hChild pin of MUX-type pin is not capable of automatic input pin selection, in order to configure active input of a MUX-type pin, the user needs to request desired pin state of the child pin on the parent pin, as described in the ``MUX-type pins`` chapter.h](hChild pin of MUX-type pin is not capable of automatic input pin selection, in order to configure active input of a MUX-type pin, the user needs to request desired pin state of the child pin on the parent pin, as described in the }(hjhhhNhNubjU)}(h``MUX-type pins``h]h MUX-type pins}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh chapter.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] pin-priorityah ]h"] pin priorityah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h'Phase offset measurement and adjustmenth]h'Phase offset measurement and adjustment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hDevice may provide ability to measure a phase difference between signals on a pin and its parent dpll device. If pin-dpll phase offset measurement is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` attribute for each parent dpll device.h](hDevice may provide ability to measure a phase difference between signals on a pin and its parent dpll device. If pin-dpll phase offset measurement is supported, it shall be provided with }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PHASE_OFFSET``h]hDPLL_A_PIN_PHASE_OFFSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh' attribute for each parent dpll device.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXDevice may also provide ability to adjust a signal phase on a pin. If pin phase adjustment is supported, minimal and maximal values that pin handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attributes. Configured phase adjust value is provided with ``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.h](hDevice may also provide ability to adjust a signal phase on a pin. If pin phase adjustment is supported, minimal and maximal values that pin handle shall be provide to the user on }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh respond with }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PHASE_ADJUST_MIN``h]hDPLL_A_PIN_PHASE_ADJUST_MIN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh and }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PHASE_ADJUST_MAX``h]hDPLL_A_PIN_PHASE_ADJUST_MAX}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh< attributes. Configured phase adjust value is provided with }(hjhhhNhNubjU)}(h``DPLL_A_PIN_PHASE_ADJUST``h]hDPLL_A_PIN_PHASE_ADJUST}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubhT attribute of a pin, and value change can be requested with the same attribute with }(hjhhhNhNubjU)}(h``DPLL_CMD_PIN_SET``h]hDPLL_CMD_PIN_SET}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX2=============================== ====================================== ``DPLL_A_PIN_ID`` configured pin id ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase adjustment on parent dpll device ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration on given parent dpll device ``DPLL_A_PIN_PARENT_ID`` parent dpll device id ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference between a pin and parent dpll device =============================== ====================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjl ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK&uh1jhjl ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ID``h]jU)}(hj h]h DPLL_A_PIN_ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hconfigured pin idh]hconfigured pin id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MIN``h]jU)}(hj h]hDPLL_A_PIN_PHASE_ADJUST_MIN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h&attr minimum value of phase adjustmenth]h&attr minimum value of phase adjustment}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MAX``h]jU)}(hj h]hDPLL_A_PIN_PHASE_ADJUST_MAX}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h&attr maximum value of phase adjustmenth]h&attr maximum value of phase adjustment}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj) ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST``h]jU)}(hjN h]hDPLL_A_PIN_PHASE_ADJUST}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjL ubah}(h]h ]h"]h$]h&]uh1hhhhKhjI ubah}(h]h ]h"]h$]h&]uh1jhjF ubj)}(hhh]h)}(h?attr configured value of phase adjustment on parent dpll deviceh]h?attr configured value of phase adjustment on parent dpll device}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhji ubah}(h]h ]h"]h$]h&]uh1jhjF ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_DEVICE``h]jU)}(hj h]hDPLL_A_PIN_PARENT_DEVICE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInested attribute for requesting configuration on given parent dpll deviceh]hInested attribute for requesting configuration on given parent dpll device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]jU)}(hj h]hDPLL_A_PIN_PARENT_ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hparent dpll device idh]hparent dpll device id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_OFFSET``h]jU)}(hj h]hDPLL_A_PIN_PHASE_OFFSET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hCattr measured phase difference between a pin and parent dpll deviceh]hCattr measured phase difference between a pin and parent dpll device}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj) ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjl ubeh}(h]h ]h"]h$]h&]colsKuh1jhji ubah}(h]h ]h"]h$]h&]uh1jhje ubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubh)}(hX#All phase related values are provided in pico seconds, which represents time difference between signals phase. The negative value means that phase of signal on pin is earlier in time than dpll's signal. Positive value means that phase of signal on pin is later in time than signal of a dpll.h]hX%All phase related values are provided in pico seconds, which represents time difference between signals phase. The negative value means that phase of signal on pin is earlier in time than dpll’s signal. Positive value means that phase of signal on pin is later in time than signal of a dpll.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hPhase adjust (also min and max) values are integers, but measured phase offset values are fractional with 3-digit decimal places and shell be divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and modulo divided to get fractional part.h](hPhase adjust (also min and max) values are integers, but measured phase offset values are fractional with 3-digit decimal places and shell be divided with }(hjm hhhNhNubjU)}(h!``DPLL_PIN_PHASE_OFFSET_DIVIDER``h]hDPLL_PIN_PHASE_OFFSET_DIVIDER}(hju hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjm ubh? to get integer part and modulo divided to get fractional part.}(hjm hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]'phase-offset-measurement-and-adjustmentah ]h"]'phase offset measurement and adjustmentah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Embedded SYNCh]h Embedded SYNC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXDevice may provide ability to use Embedded SYNC feature. It allows to embed additional SYNC signal into the base frequency of a pin - a one special pulse of base frequency signal every time SYNC signal pulse happens. The user can configure the frequency of Embedded SYNC. The Embedded SYNC capability is always related to a given base frequency and HW capabilities. The user is provided a range of Embedded SYNC frequencies supported, depending on current base frequency configured for the pin.h]hXDevice may provide ability to use Embedded SYNC feature. It allows to embed additional SYNC signal into the base frequency of a pin - a one special pulse of base frequency signal every time SYNC signal pulse happens. The user can configure the frequency of Embedded SYNC. The Embedded SYNC capability is always related to a given base frequency and HW capabilities. The user is provided a range of Embedded SYNC frequencies supported, depending on current base frequency configured for the pin.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hX>========================================= ================================= ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC frequency ranges ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC ========================================= ================================= h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK)uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ESYNC_FREQUENCY``h]jU)}(hj h]hDPLL_A_PIN_ESYNC_FREQUENCY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hcurrent Embedded SYNC frequencyh]hcurrent Embedded SYNC frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h(``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED``h]jU)}(hj h]h$DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h-nest available Embedded SYNC frequency rangesh]h-nest available Embedded SYNC frequency ranges}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj8 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_FREQUENCY_MIN``h]jU)}(hj] h]hDPLL_A_PIN_FREQUENCY_MIN}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj[ ubah}(h]h ]h"]h$]h&]uh1hhhhKhjX ubah}(h]h ]h"]h$]h&]uh1jhjU ubj)}(hhh]h)}(hattr minimum value of frequencyh]hattr minimum value of frequency}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjx ubah}(h]h ]h"]h$]h&]uh1jhjU ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_FREQUENCY_MAX``h]jU)}(hj h]hDPLL_A_PIN_FREQUENCY_MAX}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hattr maximum value of frequencyh]hattr maximum value of frequency}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ESYNC_PULSE``h]jU)}(hj h]hDPLL_A_PIN_ESYNC_PULSE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hpulse type of Embedded SYNCh]hpulse type of Embedded SYNC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubeh}(h] embedded-syncah ]h"] embedded syncah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hConfiguration commands grouph]hConfiguration commands group}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6 hhhhhKubh)}(hXAConfiguration commands are used to get information about registered dpll devices (and pins), as well as set configuration of device or pins. As dpll devices must be abstracted and reflect real hardware, there is no way to add new dpll device via netlink from user space and each device should be registered by its driver.h]hXAConfiguration commands are used to get information about registered dpll devices (and pins), as well as set configuration of device or pins. As dpll devices must be abstracted and reflect real hardware, there is no way to add new dpll device via netlink from user space and each device should be registered by its driver.}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubh)}(hAll netlink commands require ``GENL_ADMIN_PERM``. This is to prevent any spamming/DoS from unauthorized userspace applications.h](hAll netlink commands require }(hjU hhhNhNubjU)}(h``GENL_ADMIN_PERM``h]hGENL_ADMIN_PERM}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjU ubhO. This is to prevent any spamming/DoS from unauthorized userspace applications.}(hjU hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubeh}(h]configuration-commands-groupah ]h"]configuration commands groupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h1List of netlink commands with possible attributesh]h1List of netlink commands with possible attributes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj} hhhhhKubh)}(hConstants identifying command types for dpll device uses a ``DPLL_CMD_`` prefix and suffix according to command purpose. The dpll device related attributes use a ``DPLL_A_`` prefix and suffix according to attribute purpose.h](h;Constants identifying command types for dpll device uses a }(hj hhhNhNubjU)}(h ``DPLL_CMD_``h]h DPLL_CMD_}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubhZ prefix and suffix according to command purpose. The dpll device related attributes use a }(hj hhhNhNubjU)}(h ``DPLL_A_``h]hDPLL_A_}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubh2 prefix and suffix according to attribute purpose.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj} hhubj)}(hX==================================== ================================= ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID ``DPLL_A_MODULE_NAME`` attr module name of registerer ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard ``DPLL_A_TYPE`` attr type of dpll device ==================================== ================================= ==================================== ================================= ``DPLL_CMD_DEVICE_GET`` command to get device info or dump list of available devices ``DPLL_A_ID`` attr unique dpll device ID ``DPLL_A_MODULE_NAME`` attr module name of registerer ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard ``DPLL_A_MODE`` attr selection mode ``DPLL_A_MODE_SUPPORTED`` attr available selection modes ``DPLL_A_LOCK_STATUS`` attr dpll device lock status ``DPLL_A_TEMP`` attr device temperature info ``DPLL_A_TYPE`` attr type of dpll device ==================================== ================================= ==================================== ================================= ``DPLL_CMD_DEVICE_SET`` command to set dpll device config ``DPLL_A_ID`` attr internal dpll device index ``DPLL_A_MODE`` attr selection mode to configure ==================================== ================================= h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_ID_GET``h]jU)}(hj h]hDPLL_CMD_DEVICE_ID_GET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hcommand to get device IDh]hcommand to get device ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_MODULE_NAME``h]jU)}(hj)h]hDPLL_A_MODULE_NAME}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj'ubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hattr module name of registererh]hattr module name of registerer}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_CLOCK_ID``h]jU)}(hjih]hDPLL_A_CLOCK_ID}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjgubah}(h]h ]h"]h$]h&]uh1hhhhMhjdubah}(h]h ]h"]h$]h&]uh1jhjaubj)}(hhh]h)}(hKattr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standardh]hKattr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_TYPE``h]jU)}(hjh]h DPLL_A_TYPE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr type of dpll deviceh]hattr type of dpll device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_GET``h]jU)}(hjh]hDPLL_CMD_DEVICE_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h+attr pin panel label provided by registererh]h+attr pin panel label provided by registerer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PACKAGE_LABEL``h]jU)}(hj%h]hDPLL_A_PIN_PACKAGE_LABEL}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj#ubah}(h]h ]h"]h$]h&]uh1hhhhM@hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h-attr pin package label provided by registererh]h-attr pin package label provided by registerer}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hj@ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_TYPE``h]jU)}(hjeh]hDPLL_A_PIN_TYPE}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jThjcubah}(h]h ]h"]h$]h&]uh1hhhhMBhj`ubah}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh]h)}(hattr type of a pinh]hattr type of a pin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhjubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_FREQUENCY``h]jU)}(hjh]hDPLL_A_PIN_FREQUENCY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr current frequency of a pinh]hattr current frequency of a pin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h"``DPLL_A_PIN_FREQUENCY_SUPPORTED``h]jU)}(hjh]hDPLL_A_PIN_FREQUENCY_SUPPORTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h*nested attr provides supported frequenciesh]h*nested attr provides supported frequencies}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h ``DPLL_A_PIN_ANY_FREQUENCY_MIN``h]jU)}(hj%h]hDPLL_A_PIN_ANY_FREQUENCY_MIN}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj#ubah}(h]h ]h"]h$]h&]uh1hhhhMFhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr minimum value of frequencyh]hattr minimum value of frequency}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj@ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h ``DPLL_A_PIN_ANY_FREQUENCY_MAX``h]jU)}(hjeh]hDPLL_A_PIN_ANY_FREQUENCY_MAX}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jThjcubah}(h]h ]h"]h$]h&]uh1hhhhMGhj`ubah}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh]h)}(hattr maximum value of frequencyh]hattr maximum value of frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MIN``h]jU)}(hjh]hDPLL_A_PIN_PHASE_ADJUST_MIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhMHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&attr minimum value of phase adjustmenth]h&attr minimum value of phase adjustment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MAX``h]jU)}(hjh]hDPLL_A_PIN_PHASE_ADJUST_MAX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&attr maximum value of phase adjustmenth]h&attr maximum value of phase adjustment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST``h]jU)}(hj%h]hDPLL_A_PIN_PHASE_ADJUST}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj#ubah}(h]h ]h"]h$]h&]uh1hhhhMLhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h:attr configured value of phase adjustment on parent deviceh]h:attr configured value of phase adjustment on parent device}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj@ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_DEVICE``h]jU)}(hjeh]hDPLL_A_PIN_PARENT_DEVICE}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jThjcubah}(h]h ]h"]h$]h&]uh1hhhhMNhj`ubah}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh]h)}(hhjO#ubj )}(hhh]h)}(h5dpll device lock status was changed without any errorh]h5dpll device lock status was changed without any error}(hjn#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhK=hjk#ubah}(h]h ]h"]h$]h&]uh1j hjO#ubeh}(h]h ]h"]h$]h&]uh1j hjj#hK>hjL#ubj )}(h``DPLL_LOCK_STATUS_ERROR_UNDEFINED`` dpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type. h](j )}(h$``DPLL_LOCK_STATUS_ERROR_UNDEFINED``h]jU)}(hj#h]h DPLL_LOCK_STATUS_ERROR_UNDEFINED}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj#ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKChj#ubj )}(hhh]h)}(hdpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type.h]hdpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKAhj#ubah}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ]h"]h$]h&]uh1j hj#hKChjL#ubj )}(h``DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN`` dpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. h](j )}(h%``DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN``h]jU)}(hj#h]h!DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj#ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKIhj#ubj )}(hhh]h)}(hdpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h]hdpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKFhj#ubah}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ]h"]h$]h&]uh1j hj#hKIhjL#ubj )}(hX``DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH`` the FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h](j )}(h?``DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH``h]jU)}(hj$h]h;DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj$ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKNhj#ubj )}(hhh]h)}(hthe FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h]hthe FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKLhj$ubah}(h]h ]h"]h$]h&]uh1j hj#ubeh}(h]h ]h"]h$]h&]uh1j hj$hKNhjL#ubeh}(h]h ]h"]h$]h&]uh1j hj0#ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_type (C enum) c.dpll_typehNtauh1jhjhhhNhNubj)}(hhh](j)}(h dpll_typeh]j )}(henum dpll_typeh](j )}(hj h]henum}(hj]$hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjY$hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKUubj )}(h h]h }(hjk$hhhNhNubah}(h]h ]j& ah"]h$]h&]uh1j hjY$hhhjj$hKUubj+ )}(h dpll_typeh]j1 )}(hjW$h]h dpll_type}(hj}$hhhNhNubah}(h]h ]j< ah"]h$]h&]uh1j0 hjy$ubah}(h]h ](jC jD eh"]h$]h&]hhuh1j* hjY$hhhjj$hKUubeh}(h]h ]h"]h$]h&]hhjN uh1j jO jP hjU$hhhjj$hKUubah}(h]jP$ah ](jT jU eh"]h$]h&]jY jZ )j[ huh1jhjj$hKUhjR$hhubj] )}(hhh]h)}(h4type of dpll, valid values for DPLL_A_TYPE attributeh]h4type of dpll, valid values for DPLL_A_TYPE attribute}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKlhj$hhubah}(h]h ]h"]h$]h&]uh1j\ hjR$hhhjj$hKUubeh}(h]h ](jy enumeh"]h$]h&]j~ jy j j$j j$j j j uh1jhhhjhNhNubj )}(h**Constants** ``DPLL_TYPE_PPS`` dpll produces Pulse-Per-Second signal ``DPLL_TYPE_EEC`` dpll drives the Ethernet Equipment Clockh](h)}(h **Constants**h]j )}(hj$h]h Constants}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj$ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKphj$ubj )}(hhh](j )}(h8``DPLL_TYPE_PPS`` dpll produces Pulse-Per-Second signal h](j )}(h``DPLL_TYPE_PPS``h]jU)}(hj$h]h DPLL_TYPE_PPS}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj$ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKshj$ubj )}(hhh]h)}(h%dpll produces Pulse-Per-Second signalh]h%dpll produces Pulse-Per-Second signal}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hKshj$ubah}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ]h"]h$]h&]uh1j hj$hKshj$ubj )}(h:``DPLL_TYPE_EEC`` dpll drives the Ethernet Equipment Clockh](j )}(h``DPLL_TYPE_EEC``h]jU)}(hj%h]h DPLL_TYPE_EEC}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj%ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKuhj%ubj )}(hhh]h)}(h(dpll drives the Ethernet Equipment Clockh]h(dpll drives the Ethernet Equipment Clock}(hj2%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKvhj/%ubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1j hj.%hKuhj$ubeh}(h]h ]h"]h$]h&]uh1j hj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_pin_type (C enum)c.dpll_pin_typehNtauh1jhjhhhNhNubj)}(hhh](j)}(h dpll_pin_typeh]j )}(henum dpll_pin_typeh](j )}(hj h]henum}(hjs%hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjo%hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhK|ubj )}(h h]h }(hj%hhhNhNubah}(h]h ]j& ah"]h$]h&]uh1j hjo%hhhj%hK|ubj+ )}(h dpll_pin_typeh]j1 )}(hjm%h]h dpll_pin_type}(hj%hhhNhNubah}(h]h ]j< ah"]h$]h&]uh1j0 hj%ubah}(h]h ](jC jD eh"]h$]h&]hhuh1j* hjo%hhhj%hK|ubeh}(h]h ]h"]h$]h&]hhjN uh1j jO jP hjk%hhhj%hK|ubah}(h]jf%ah ](jT jU eh"]h$]h&]jY jZ )j[ huh1jhj%hK|hjh%hhubj] )}(hhh]h)}(hKdefines possible types of a pin, valid values for DPLL_A_PIN_TYPE attributeh]hKdefines possible types of a pin, valid values for DPLL_A_PIN_TYPE attribute}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKzhj%hhubah}(h]h ]h"]h$]h&]uh1j\ hjh%hhhj%hK|ubeh}(h]h ](jy enumeh"]h$]h&]j~ jy j j%j j%j j j uh1jhhhjhNhNubj )}(hX0**Constants** ``DPLL_PIN_TYPE_MUX`` aggregates another layer of selectable pins ``DPLL_PIN_TYPE_EXT`` external input ``DPLL_PIN_TYPE_SYNCE_ETH_PORT`` ethernet port PHY's recovered clock ``DPLL_PIN_TYPE_INT_OSCILLATOR`` device internal oscillator ``DPLL_PIN_TYPE_GNSS`` GNSS recovered clockh](h)}(h **Constants**h]j )}(hj%h]h Constants}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj%ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhK~hj%ubj )}(hhh](j )}(hB``DPLL_PIN_TYPE_MUX`` aggregates another layer of selectable pins h](j )}(h``DPLL_PIN_TYPE_MUX``h]jU)}(hj%h]hDPLL_PIN_TYPE_MUX}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj%ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj%ubj )}(hhh]h)}(h+aggregates another layer of selectable pinsh]h+aggregates another layer of selectable pins}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj &hKhj &ubah}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ]h"]h$]h&]uh1j hj &hKhj%ubj )}(h%``DPLL_PIN_TYPE_EXT`` external input h](j )}(h``DPLL_PIN_TYPE_EXT``h]jU)}(hj/&h]hDPLL_PIN_TYPE_EXT}(hj1&hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj-&ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj)&ubj )}(hhh]h)}(hexternal inputh]hexternal input}(hjH&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjD&hKhjE&ubah}(h]h ]h"]h$]h&]uh1j hj)&ubeh}(h]h ]h"]h$]h&]uh1j hjD&hKhj%ubj )}(hE``DPLL_PIN_TYPE_SYNCE_ETH_PORT`` ethernet port PHY's recovered clock h](j )}(h ``DPLL_PIN_TYPE_SYNCE_ETH_PORT``h]jU)}(hjh&h]hDPLL_PIN_TYPE_SYNCE_ETH_PORT}(hjj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjf&ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhjb&ubj )}(hhh]h)}(h#ethernet port PHY's recovered clockh]h%ethernet port PHY’s recovered clock}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}&hKhj~&ubah}(h]h ]h"]h$]h&]uh1j hjb&ubeh}(h]h ]h"]h$]h&]uh1j hj}&hKhj%ubj )}(h<``DPLL_PIN_TYPE_INT_OSCILLATOR`` device internal oscillator h](j )}(h ``DPLL_PIN_TYPE_INT_OSCILLATOR``h]jU)}(hj&h]hDPLL_PIN_TYPE_INT_OSCILLATOR}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj&ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj&ubj )}(hhh]h)}(hdevice internal oscillatorh]hdevice internal oscillator}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hKhj&ubah}(h]h ]h"]h$]h&]uh1j hj&ubeh}(h]h ]h"]h$]h&]uh1j hj&hKhj%ubj )}(h+``DPLL_PIN_TYPE_GNSS`` GNSS recovered clockh](j )}(h``DPLL_PIN_TYPE_GNSS``h]jU)}(hj&h]hDPLL_PIN_TYPE_GNSS}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj&ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj&ubj )}(hhh]h)}(hGNSS recovered clockh]hGNSS recovered clock}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj&ubah}(h]h ]h"]h$]h&]uh1j hj&ubeh}(h]h ]h"]h$]h&]uh1j hj&hKhj%ubeh}(h]h ]h"]h$]h&]uh1j hj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_pin_direction (C enum)c.dpll_pin_directionhNtauh1jhjhhhNhNubj)}(hhh](j)}(hdpll_pin_directionh]j )}(henum dpll_pin_directionh](j )}(hj h]henum}(hj4'hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj0'hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKubj )}(h h]h }(hjB'hhhNhNubah}(h]h ]j& ah"]h$]h&]uh1j hj0'hhhjA'hKubj+ )}(hdpll_pin_directionh]j1 )}(hj.'h]hdpll_pin_direction}(hjT'hhhNhNubah}(h]h ]j< ah"]h$]h&]uh1j0 hjP'ubah}(h]h ](jC jD eh"]h$]h&]hhuh1j* hj0'hhhjA'hKubeh}(h]h ]h"]h$]h&]hhjN uh1j jO jP hj,'hhhjA'hKubah}(h]j''ah ](jT jU eh"]h$]h&]jY jZ )j[ huh1jhjA'hKhj)'hhubj] )}(hhh]h)}(hTdefines possible direction of a pin, valid values for DPLL_A_PIN_DIRECTION attributeh]hTdefines possible direction of a pin, valid values for DPLL_A_PIN_DIRECTION attribute}(hjv'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhjs'hhubah}(h]h ]h"]h$]h&]uh1j\ hj)'hhhjA'hKubeh}(h]h ](jy enumeh"]h$]h&]j~ jy j j'j j'j j j uh1jhhhjhNhNubj )}(h**Constants** ``DPLL_PIN_DIRECTION_INPUT`` pin used as a input of a signal ``DPLL_PIN_DIRECTION_OUTPUT`` pin used to output the signalh](h)}(h **Constants**h]j )}(hj'h]h Constants}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj'ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj'ubj )}(hhh](j )}(h=``DPLL_PIN_DIRECTION_INPUT`` pin used as a input of a signal h](j )}(h``DPLL_PIN_DIRECTION_INPUT``h]jU)}(hj'h]hDPLL_PIN_DIRECTION_INPUT}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj'ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj'ubj )}(hhh]h)}(hpin used as a input of a signalh]hpin used as a input of a signal}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hKhj'ubah}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ]h"]h$]h&]uh1j hj'hKhj'ubj )}(h;``DPLL_PIN_DIRECTION_OUTPUT`` pin used to output the signalh](j )}(h``DPLL_PIN_DIRECTION_OUTPUT``h]jU)}(hj'h]hDPLL_PIN_DIRECTION_OUTPUT}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj'ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj'ubj )}(hhh]h)}(hpin used to output the signalh]hpin used to output the signal}(hj (hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj(ubah}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ]h"]h$]h&]uh1j hj(hKhj'ubeh}(h]h ]h"]h$]h&]uh1j hj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_pin_state (C enum)c.dpll_pin_statehNtauh1jhjhhhNhNubj)}(hhh](j)}(hdpll_pin_stateh]j )}(henum dpll_pin_stateh](j )}(hj h]henum}(hjJ(hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjF(hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKubj )}(h h]h }(hjX(hhhNhNubah}(h]h ]j& ah"]h$]h&]uh1j hjF(hhhjW(hKubj+ )}(hdpll_pin_stateh]j1 )}(hjD(h]hdpll_pin_state}(hjj(hhhNhNubah}(h]h ]j< ah"]h$]h&]uh1j0 hjf(ubah}(h]h ](jC jD eh"]h$]h&]hhuh1j* hjF(hhhjW(hKubeh}(h]h ]h"]h$]h&]hhjN uh1j jO jP hjB(hhhjW(hKubah}(h]j=(ah ](jT jU eh"]h$]h&]jY jZ )j[ huh1jhjW(hKhj?(hhubj] )}(hhh]h)}(hMdefines possible states of a pin, valid values for DPLL_A_PIN_STATE attributeh]hMdefines possible states of a pin, valid values for DPLL_A_PIN_STATE attribute}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj(hhubah}(h]h ]h"]h$]h&]uh1j\ hj?(hhhjW(hKubeh}(h]h ](jy enumeh"]h$]h&]j~ jy j j(j j(j j j uh1jhhhjhNhNubj )}(hX**Constants** ``DPLL_PIN_STATE_CONNECTED`` pin connected, active input of phase locked loop ``DPLL_PIN_STATE_DISCONNECTED`` pin disconnected, not considered as a valid input ``DPLL_PIN_STATE_SELECTABLE`` pin enabled for automatic input selectionh](h)}(h **Constants**L{h]j )}(hj(h]h Constants}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj(ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj(ubj )}(hhh](j )}(hN``DPLL_PIN_STATE_CONNECTED`` pin connected, active input of phase locked loop h](j )}(h``DPLL_PIN_STATE_CONNECTED``h]jU)}(hj(h]hDPLL_PIN_STATE_CONNECTED}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj(ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj(ubj )}(hhh]h)}(h0pin connected, active input of phase locked looph]h0pin connected, active input of phase locked loop}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hKhj(ubah}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ]h"]h$]h&]uh1j hj(hKhj(ubj )}(hR``DPLL_PIN_STATE_DISCONNECTED`` pin disconnected, not considered as a valid input h](j )}(h``DPLL_PIN_STATE_DISCONNECTED``h]jU)}(hj)h]hDPLL_PIN_STATE_DISCONNECTED}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj)ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj)ubj )}(hhh]h)}(h1pin disconnected, not considered as a valid inputh]h1pin disconnected, not considered as a valid input}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj)ubah}(h]h ]h"]h$]h&]uh1j hj)ubeh}(h]h ]h"]h$]h&]uh1j hj)hKhj(ubj )}(hG``DPLL_PIN_STATE_SELECTABLE`` pin enabled for automatic input selectionh](j )}(h``DPLL_PIN_STATE_SELECTABLE``h]jU)}(hj@)h]hDPLL_PIN_STATE_SELECTABLE}(hjB)hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj>)ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj:)ubj )}(hhh]h)}(h)pin enabled for automatic input selectionh]h)pin enabled for automatic input selection}(hjY)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhjV)ubah}(h]h ]h"]h$]h&]uh1j hj:)ubeh}(h]h ]h"]h$]h&]uh1j hjU)hKhj(ubeh}(h]h ]h"]h$]h&]uh1j hj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdpll_pin_capabilities (C enum)c.dpll_pin_capabilitieshNtauh1jhjhhhNhNubj)}(hhh](j)}(hdpll_pin_capabilitiesh]j )}(henum dpll_pin_capabilitiesh](j )}(hj h]henum}(hj)hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj)hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKubj )}(h h]h }(hj)hhhNhNubah}(h]h ]j& ah"]h$]h&]uh1j hj)hhhj)hKubj+ )}(hdpll_pin_capabilitiesh]j1 )}(hj)h]hdpll_pin_capabilities}(hj)hhhNhNubah}(h]h ]j< ah"]h$]h&]uh1j0 hj)ubah}(h]h ](jC jD eh"]h$]h&]hhuh1j* hj)hhhj)hKubeh}(h]h ]h"]h$]h&]hhjN uh1j jO jP hj)hhhj)hKubah}(h]j)ah ](jT jU eh"]h$]h&]jY jZ )j[ huh1jhj)hKhj)hhubj] )}(hhh]h)}(hXdefines possible capabilities of a pin, valid flags on DPLL_A_PIN_CAPABILITIES attributeh]hXdefines possible capabilities of a pin, valid flags on DPLL_A_PIN_CAPABILITIES attribute}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj)hhubah}(h]h ]h"]h$]h&]uh1j\ hj)hhhj)hKubeh}(h]h ](jy enumeh"]h$]h&]j~ jy j j)j j)j j j uh1jhhhjhNhNubj )}(h**Constants** ``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE`` pin direction can be changed ``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE`` pin priority can be changed ``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE`` pin state can be changedh](h)}(h **Constants**h]j )}(hj)h]h Constants}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j hj)ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj)ubj )}(hhh](j )}(hL``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE`` pin direction can be changed h](j )}(h.``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE``h]jU)}(hj*h]h*DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj*ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj*ubj )}(hhh]h)}(hpin direction can be changedh]hpin direction can be changed}(hj6*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2*hKhj3*ubah}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ]h"]h$]h&]uh1j hj2*hKhj*ubj )}(hJ``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE`` pin priority can be changed h](j )}(h-``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE``h]jU)}(hjV*h]h)DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE}(hjX*hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjT*ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhjP*ubj )}(hhh]h)}(hpin priority can be changedh]hpin priority can be changed}(hjo*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjk*hKhjl*ubah}(h]h ]h"]h$]h&]uh1j hjP*ubeh}(h]h ]h"]h$]h&]uh1j hjk*hKhj*ubj )}(hC``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE`` pin state can be changedh](j )}(h*``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE``h]jU)}(hj*h]h&DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj*ubah}(h]h ]h"]h$]h&]uh1j hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj*ubj )}(hhh]h)}(hpin state can be changedh]hpin state can be changed}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:411: ./include/uapi/linux/dpll.hhKhj*ubah}(h]h ]h"]h$]h&]uh1j hj*ubeh}(h]h ]h"]h$]h&]uh1j hj*hKhj*ubeh}(h]h ]h"]h$]h&]uh1j hj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1j hjhhhNhNubeh}(h]configuration-pre-defined-enumsah ]h"]configuration pre-defined enumsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h Notificationsh]h Notifications}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhMubh)}(hdpll device can provide notifications regarding status changes of the device, i.e. lock status changes, input/output changes or other alarms. There is one multicast group that is used to notify user-space apps via netlink socket: ``DPLL_MCGRP_MONITOR``h](hdpll device can provide notifications regarding status changes of the device, i.e. lock status changes, input/output changes or other alarms. There is one multicast group that is used to notify user-space apps via netlink socket: }(hj*hhhNhNubjU)}(h``DPLL_MCGRP_MONITOR``h]hDPLL_MCGRP_MONITOR}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj*ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubh)}(hNotifications messages:h]hNotifications messages:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubj)}(hX============================== ===================================== ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed ============================== ===================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj+ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK%uh1jhj+ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_CREATE_NTF``h]jU)}(hj<+h]hDPLL_CMD_DEVICE_CREATE_NTF}(hj>+hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj:+ubah}(h]h ]h"]h$]h&]uh1hhhhMhj7+ubah}(h]h ]h"]h$]h&]uh1jhj4+ubj)}(hhh]h)}(hdpll device was createdh]hdpll device was created}(hjZ+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjW+ubah}(h]h ]h"]h$]h&]uh1jhj4+ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_DELETE_NTF``h]jU)}(hj|+h]hDPLL_CMD_DEVICE_DELETE_NTF}(hj~+hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjz+ubah}(h]h ]h"]h$]h&]uh1hhhhMhjw+ubah}(h]h ]h"]h$]h&]uh1jhjt+ubj)}(hhh]h)}(hdpll device was deletedh]hdpll device was deleted}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhjt+ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_CHANGE_NTF``h]jU)}(hj+h]hDPLL_CMD_DEVICE_CHANGE_NTF}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh]h)}(hdpll device has changedh]hdpll device has changed}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_CREATE_NTF``h]jU)}(hj+h]hDPLL_CMD_PIN_CREATE_NTF}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh]h)}(hdpll pin was createdh]hdpll pin was created}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_DELETE_NTF``h]jU)}(hj<,h]hDPLL_CMD_PIN_DELETE_NTF}(hj>,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj:,ubah}(h]h ]h"]h$]h&]uh1hhhhMhj7,ubah}(h]h ]h"]h$]h&]uh1jhj4,ubj)}(hhh]h)}(hdpll pin was deletedh]hdpll pin was deleted}(hjZ,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjW,ubah}(h]h ]h"]h$]h&]uh1jhj4,ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_CHANGE_NTF``h]jU)}(hj|,h]hDPLL_CMD_PIN_CHANGE_NTF}(hj~,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjz,ubah}(h]h ]h"]h$]h&]uh1hhhhMhjw,ubah}(h]h ]h"]h$]h&]uh1jhjt,ubj)}(hhh]h)}(hdpll pin has changedh]hdpll pin has changed}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjt,ubeh}(h]h ]h"]h$]h&]uh1jhj1+ubeh}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]colsKuh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhhhMhj*hhubh)}(hEvents format is the same as for the corresponding get command. Format of ``DPLL_CMD_DEVICE_`` events is the same as response of ``DPLL_CMD_DEVICE_GET``. Format of ``DPLL_CMD_PIN_`` events is same as response of ``DPLL_CMD_PIN_GET``.h](hJEvents format is the same as for the corresponding get command. Format of }(hj,hhhNhNubjU)}(h``DPLL_CMD_DEVICE_``h]hDPLL_CMD_DEVICE_}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj,ubh# events is the same as response of }(hj,hhhNhNubjU)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj,ubh . Format of }(hj,hhhNhNubjU)}(h``DPLL_CMD_PIN_``h]h DPLL_CMD_PIN_}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj,ubh events is same as response of }(hj,hhhNhNubjU)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj -hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj,ubh.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubeh}(h] notificationsah ]h"] notificationsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hDevice driver implementationh]hDevice driver implementation}(hj.-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+-hhhhhMubh)}(hXfDevice is allocated by dpll_device_get() call. Second call with the same arguments will not create new object but provides pointer to previously created device for given arguments, it also increases refcount of that object. Device is deallocated by dpll_device_put() call, which first decreases the refcount, once refcount is cleared the object is destroyed.h]hXfDevice is allocated by dpll_device_get() call. Second call with the same arguments will not create new object but provides pointer to previously created device for given arguments, it also increases refcount of that object. Device is deallocated by dpll_device_put() call, which first decreases the refcount, once refcount is cleared the object is destroyed.}(hj<-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubh)}(hXDevice should implement set of operations and register device via dpll_device_register() at which point it becomes available to the users. Multiple driver instances can obtain reference to it with dpll_device_get(), as well as register dpll device with their own ops and priv.h]hXDevice should implement set of operations and register device via dpll_device_register() at which point it becomes available to the users. Multiple driver instances can obtain reference to it with dpll_device_get(), as well as register dpll device with their own ops and priv.}(hjJ-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubh)}(hX The pins are allocated separately with dpll_pin_get(), it works similarly to dpll_device_get(). Function first creates object and then for each call with the same arguments only the object refcount increases. Also dpll_pin_put() works similarly to dpll_device_put().h]hX The pins are allocated separately with dpll_pin_get(), it works similarly to dpll_device_get(). Function first creates object and then for each call with the same arguments only the object refcount increases. Also dpll_pin_put() works similarly to dpll_device_put().}(hjX-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubh)}(hA pin can be registered with parent dpll device or parent pin, depending on hardware needs. Each registration requires registerer to provide set of pin callbacks, and private data pointer for calling them:h]hA pin can be registered with parent dpll device or parent pin, depending on hardware needs. Each registration requires registerer to provide set of pin callbacks, and private data pointer for calling them:}(hjf-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjw)}(hhh](j|)}(h6dpll_pin_register() - register pin with a dpll device,h]h)}(hjy-h]h6dpll_pin_register() - register pin with a dpll device,}(hj{-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjw-ubah}(h]h ]h"]h$]h&]uh1j{hjt-hhhhhNubj|)}(hEdpll_pin_on_pin_register() - register pin with another MUX type pin. h]h)}(hDdpll_pin_on_pin_register() - register pin with another MUX type pin.h]hDdpll_pin_on_pin_register() - register pin with another MUX type pin.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1j{hjt-hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jvhhhMhj+-hhubh)}(hXNotifications of adding or removing dpll devices are created within subsystem itself. Notifications about registering/deregistering pins are also invoked by the subsystem. Notifications about status changes either of dpll device or a pin are invoked in two ways:h]hXNotifications of adding or removing dpll devices are created within subsystem itself. Notifications about registering/deregistering pins are also invoked by the subsystem. Notifications about status changes either of dpll device or a pin are invoked in two ways:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjw)}(hhh](j|)}(hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,h]h)}(hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,h]hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1j{hj-hhhhhNubj|)}(hrequested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change. h]h)}(h~requested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change.h]h~requested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1j{hj-hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jvhhhMhj+-hhubh)}(hThe device driver using dpll interface is not required to implement all the callback operation. Nevertheless, there are few required to be implemented. Required dpll device level callback operations:h]hThe device driver using dpll interface is not required to implement all the callback operation. Nevertheless, there are few required to be implemented. Required dpll device level callback operations:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjw)}(hhh](j|)}(h``.mode_get``,h]h)}(hj.h](jU)}(h ``.mode_get``h]h .mode_get}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj.ubh,}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1j{hj.hhhhhNubj|)}(h``.lock_status_get``. h]h)}(h``.lock_status_get``.h](jU)}(h``.lock_status_get``h]h.lock_status_get}(hj1.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj-.ubh.}(hj-.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj).ubah}(h]h ]h"]h$]h&]uh1j{hj.hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jvhhhMhj+-hhubh)}(h'Required pin level callback operations:h]h'Required pin level callback operations:}(hjU.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjw)}(hhh](j|)}(h:``.state_on_dpll_get`` (pins registered with dpll device),h]h)}(hjh.h](jU)}(h``.state_on_dpll_get``h]h.state_on_dpll_get}(hjm.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjj.ubh$ (pins registered with dpll device),}(hjj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjf.ubah}(h]h ]h"]h$]h&]uh1j{hjc.hhhhhNubj|)}(h8``.state_on_pin_get`` (pins registered with parent pin),h]h)}(hj.h](jU)}(h``.state_on_pin_get``h]h.state_on_pin_get}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj.ubh# (pins registered with parent pin),}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1j{hjc.hhhhhNubj|)}(h``.direction_get``. h]h)}(h``.direction_get``.h](jU)}(h``.direction_get``h]h.direction_get}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj.ubh.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1j{hjc.hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jvhhhMhj+-hhubh)}(h~Every other operation handler is checked for existence and ``-EOPNOTSUPP`` is returned in case of absence of specific handler.h](h;Every other operation handler is checked for existence and }(hj.hhhNhNubjU)}(h``-EOPNOTSUPP``h]h -EOPNOTSUPP}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj.ubh4 is returned in case of absence of specific handler.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubh)}(hdThe simplest implementation is in the OCP TimeCard driver. The ops structures are defined like this:h]hdThe simplest implementation is in the OCP TimeCard driver. The ops structures are defined like this:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjr)}(hXstatic const struct dpll_device_ops dpll_ops = { .lock_status_get = ptp_ocp_dpll_lock_status_get, .mode_get = ptp_ocp_dpll_mode_get, .mode_supported = ptp_ocp_dpll_mode_supported, }; static const struct dpll_pin_ops dpll_pins_ops = { .frequency_get = ptp_ocp_dpll_frequency_get, .frequency_set = ptp_ocp_dpll_frequency_set, .direction_get = ptp_ocp_dpll_direction_get, .direction_set = ptp_ocp_dpll_direction_set, .state_on_dpll_get = ptp_ocp_dpll_state_get, };h]hXstatic const struct dpll_device_ops dpll_ops = { .lock_status_get = ptp_ocp_dpll_lock_status_get, .mode_get = ptp_ocp_dpll_mode_get, .mode_supported = ptp_ocp_dpll_mode_supported, }; static const struct dpll_pin_ops dpll_pins_ops = { .frequency_get = ptp_ocp_dpll_frequency_get, .frequency_set = ptp_ocp_dpll_frequency_set, .direction_get = ptp_ocp_dpll_direction_get, .direction_set = ptp_ocp_dpll_direction_set, .state_on_dpll_get = ptp_ocp_dpll_state_get, };}hj /sbah}(h]h ]h"]h$]h&]hhforcelanguagejy highlight_args}uh1jqhhhMhj+-hhubh)}(h3The registration part is then looks like this part:h]h3The registration part is then looks like this part:}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+-hhubjr)}(hX clkid = pci_get_dsn(pdev); bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); if (IS_ERR(bp->dpll)) { err = PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); goto out; } err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); if (err) goto out; for (i = 0; i < OCP_SMA_NUM; i++) { bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); if (IS_ERR(bp->sma[i].dpll_pin)) { err = PTR_ERR(bp->dpll); goto out_dpll; } err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { dpll_pin_put(bp->sma[i].dpll_pin); goto out_dpll; } }h]hX clkid = pci_get_dsn(pdev); bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); if (IS_ERR(bp->dpll)) { err = PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); goto out; } err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); if (err) goto out; for (i = 0; i < OCP_SMA_NUM; i++) { bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); if (IS_ERR(bp->sma[i].dpll_pin)) { err = PTR_ERR(bp->dpll); goto out_dpll; } err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { dpll_pin_put(bp->sma[i].dpll_pin); goto out_dpll; } }}hj*/sbah}(h]h ]h"]h$]h&]hhj/j/jy j/}uh1jqhhhMhj+-hhubh)}(hJIn the error path we have to rewind every allocation in the reverse order:h]hJIn the error path we have to rewind every allocation in the reverse order:}(hj9/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj+-hhubjr)}(hwhile (i) { --i; dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); dpll_pin_put(bp->sma[i].dpll_pin); } dpll_device_put(bp->dpll);h]hwhile (i) { --i; dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); dpll_pin_put(bp->sma[i].dpll_pin); } dpll_device_put(bp->dpll);}hjG/sbah}(h]h ]h"]h$]h&]hhj/j/jy j/}uh1jqhhhM$hj+-hhubh)}(hPMore complex example can be found in Intel's ICE driver or nVidia's mlx5 driver.h]hTMore complex example can be found in Intel’s ICE driver or nVidia’s mlx5 driver.}(hjV/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj+-hhubeh}(h]device-driver-implementationah ]h"]device driver implementationah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hSyncE enablementh]hSyncE enablement}(hjo/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjl/hhhhhM0ubh)}(hXFor SyncE enablement it is required to allow control over dpll device for a software application which monitors and configures the inputs of dpll device in response to current state of a dpll device and its inputs. In such scenario, dpll device input signal shall be also configurable to drive dpll with signal recovered from the PHY netdevice. This is done by exposing a pin to the netdevice - attaching pin to the netdevice itself with ``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in nested attribute ``IFLA_DPLL_PIN``.h](hXFor SyncE enablement it is required to allow control over dpll device for a software application which monitors and configures the inputs of dpll device in response to current state of a dpll device and its inputs. In such scenario, dpll device input signal shall be also configurable to drive dpll with signal recovered from the PHY netdevice. This is done by exposing a pin to the netdevice - attaching pin to the netdevice itself with }(hj}/hhhNhNubjU)}(hJ``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``h]hFdpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj}/ubh. Exposed pin id handle }(hj}/hhhNhNubjU)}(h``DPLL_A_PIN_ID``h]h DPLL_A_PIN_ID}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj}/ubhP is then identifiable by the user as it is attached to rtnetlink respond to get }(hj}/hhhNhNubjU)}(h``RTM_NEWLINK``h]h RTM_NEWLINK}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj}/ubh command in nested attribute }(hj}/hhhNhNubjU)}(h``IFLA_DPLL_PIN``h]h IFLA_DPLL_PIN}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj}/ubh.}(hj}/hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM1hjl/hhubeh}(h]synce-enablementah ]h"]synce enablementah$]h&]uh1hhhhhhhhM0ubeh}(h]the-linux-kernel-dpll-subsystemah ]h"]the linux kernel dpll subsystemah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj0error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j/j/hhj$j!jjjjj|jyj+j(jjjjj j j3 j0 jz jw j+j(jjjjj*j*j(-j%-ji/jf/j/j/u nametypes}(j/hj$jjj|j+jjj j3 jz j+jjj*j(-ji/j/uh}(j/hhhj!jjj'jjjyjj(jjj.jjj jj0 j jw j6 j(j} jj.jjj*jjjj;!j@!j"j"jP$jU$jf%jk%j''j,'j=(jB(j)j)j%-j*jf/j+-j/jl/u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.