sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/driver-api/dpllmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/pt_BR/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/driver-api/dpllmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/driver-api/dpll.rsthKubhsection)}(hhh](htitle)}(hThe Linux kernel dpll subsystemh]hThe Linux kernel dpll subsystem}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDPLLh]hDPLL}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hPLL - Phase Locked Loop is an electronic circuit which syntonizes clock signal of a device with an external clock signal. Effectively enabling device to run on the same clock signal beat as provided on a PLL input.h]hPLL - Phase Locked Loop is an electronic circuit which syntonizes clock signal of a device with an external clock signal. Effectively enabling device to run on the same clock signal beat as provided on a PLL input.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hDPLL - Digital Phase Locked Loop is an integrated circuit which in addition to plain PLL behavior incorporates a digital phase detector and may have digital divider in the loop. As a result, the frequency on DPLL's input and output may be configurable.h]hDPLL - Digital Phase Locked Loop is an integrated circuit which in addition to plain PLL behavior incorporates a digital phase detector and may have digital divider in the loop. As a result, the frequency on DPLL’s input and output may be configurable.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]dpllah ]h"]dpllah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Subsystemh]h Subsystem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXIThe main purpose of dpll subsystem is to provide general interface to configure devices that use any kind of Digital PLL and could use different sources of input signal to synchronize to, as well as different types of outputs. The main interface is NETLINK_GENERIC based protocol with an event monitoring multicast group defined.h]hXIThe main purpose of dpll subsystem is to provide general interface to configure devices that use any kind of Digital PLL and could use different sources of input signal to synchronize to, as well as different types of outputs. The main interface is NETLINK_GENERIC based protocol with an event monitoring multicast group defined.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] subsystemah ]h"] subsystemah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Device objecth]h Device object}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhKubh)}(hXSingle dpll device object means single Digital PLL circuit and bunch of connected pins. It reports the supported modes of operation and current status to the user in response to the `do` request of netlink command ``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem with `dump` netlink request of the same command. Changing the configuration of dpll device is done with `do` request of netlink ``DPLL_CMD_DEVICE_SET`` command. A device handle is ``DPLL_A_ID``, it shall be provided to get or set configuration of particular device in the system. It can be obtained with a ``DPLL_CMD_DEVICE_GET`` `dump` request or a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide attributes that result in single device match.h](hSingle dpll device object means single Digital PLL circuit and bunch of connected pins. It reports the supported modes of operation and current status to the user in response to the }(hjLhhhNhNubhtitle_reference)}(h`do`h]hdo}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjLubh request of netlink command }(hjLhhhNhNubhliteral)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjLubh4 and list of dplls registered in the subsystem with }(hjLhhhNhNubjU)}(h`dump`h]hdump}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjLubh] netlink request of the same command. Changing the configuration of dpll device is done with }(hjLhhhNhNubjU)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjLubh request of netlink }(hjLhhhNhNubji)}(h``DPLL_CMD_DEVICE_SET``h]hDPLL_CMD_DEVICE_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjLubh command. A device handle is }(hjLhhhNhNubji)}(h ``DPLL_A_ID``h]h DPLL_A_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjLubhq, it shall be provided to get or set configuration of particular device in the system. It can be obtained with a }(hjLhhhNhNubji)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjLubh }(hjLhhhNhNubjU)}(h`dump`h]hdump}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjLubh request or a }(hjLhhhNhNubji)}(h``DPLL_CMD_DEVICE_ID_GET``h]hDPLL_CMD_DEVICE_ID_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjLubh }hjLsbjU)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThjLubhS request, where the one must provide attributes that result in single device match.}(hjLhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hj;hhubeh}(h] device-objectah ]h"] device objectah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Pin objecth]h Pin object}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK/ubh)}(hXyA pin is amorphic object which represents either input or output, it could be internal component of the device, as well as externally connected. The number of pins per dpll vary, but usually multiple pins shall be provided for a single dpll device. Pin's properties, capabilities and status is provided to the user in response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. It is also possible to list all the pins that were registered in the system with `dump` request of ``DPLL_CMD_PIN_GET`` command. Configuration of a pin can be changed by `do` request of netlink ``DPLL_CMD_PIN_SET`` command. Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set configuration of particular pin in the system. It can be obtained with ``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` request, where user provides attributes that result in single pin match.h](hXLA pin is amorphic object which represents either input or output, it could be internal component of the device, as well as externally connected. The number of pins per dpll vary, but usually multiple pins shall be provided for a single dpll device. Pin’s properties, capabilities and status is provided to the user in response to }(hj+hhhNhNubjU)}(h`do`h]hdo}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubh request of netlink }(hj+hhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubh[ command. It is also possible to list all the pins that were registered in the system with }(hj+hhhNhNubjU)}(h`dump`h]hdump}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubh request of }(hj+hhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubh3 command. Configuration of a pin can be changed by }(hj+hhhNhNubjU)}(h`do`h]hdo}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubh request of netlink }(hj+hhhNhNubji)}(h``DPLL_CMD_PIN_SET``h]hDPLL_CMD_PIN_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubh command. Pin handle is a }(hj+hhhNhNubji)}(h``DPLL_A_PIN_ID``h]h DPLL_A_PIN_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubhl, it shall be provided to get or set configuration of particular pin in the system. It can be obtained with }(hj+hhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubh }(hj+hhhNhNubjU)}(h`dump`h]hdump}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubh request or }(hj+hhhNhNubji)}(h``DPLL_CMD_PIN_ID_GET``h]hDPLL_CMD_PIN_ID_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj+ubh }hj+sbjU)}(h`do`h]hdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jThj+ubhI request, where user provides attributes that result in single pin match.}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjhhubeh}(h] pin-objectah ]h"] pin objectah$]h&]uh1hhhhhhhhK/ubh)}(hhh](h)}(h Pin selectionh]h Pin selection}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKBubh)}(hPin state (``DPLL_A_PIN_STATE``) reflects the administrative intent set by the user. Pin operational state (``DPLL_A_PIN_OPERSTATE``) reflects what the hardware is actually doing with the pin.h](h Pin state (}(hjhhhNhNubji)}(h``DPLL_A_PIN_STATE``h]hDPLL_A_PIN_STATE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhM) reflects the administrative intent set by the user. Pin operational state (}(hjhhhNhNubji)}(h``DPLL_A_PIN_OPERSTATE``h]hDPLL_A_PIN_OPERSTATE}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh<) reflects what the hardware is actually doing with the pin.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKDhjhhubh)}(hX!Pin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (``DPLL_A_MODE`` attribute). The consequence is that there are differences for each mode in terms of available pin states the user can request for a dpll device.h](hPin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (}(hjJhhhNhNubji)}(h``DPLL_A_MODE``h]h DPLL_A_MODE}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjJubh attribute). The consequence is that there are differences for each mode in terms of available pin states the user can request for a dpll device.}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubh)}(hWIn manual mode (``DPLL_MODE_MANUAL``) the user can request one of following pin states:h](hIn manual mode (}(hjjhhhNhNubji)}(h``DPLL_MODE_MANUAL``h]hDPLL_MODE_MANUAL}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjjubh3) the user can request one of following pin states:}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh bullet_list)}(hhh](h list_item)}(hG``DPLL_PIN_STATE_CONNECTED`` - the pin is selected to drive dpll deviceh]h)}(hG``DPLL_PIN_STATE_CONNECTED`` - the pin is selected to drive dpll deviceh](ji)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh+ - the pin is selected to drive dpll device}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hO``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not selected to drive dpll device h]h)}(hN``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not selected to drive dpll deviceh](ji)}(h``DPLL_PIN_STATE_DISCONNECTED``h]hDPLL_PIN_STATE_DISCONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh/ - the pin is not selected to drive dpll device}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKShjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKQhjhhubh)}(h]In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request one of following pin states:h](hIn automatic mode (}(hjhhhNhNubji)}(h``DPLL_MODE_AUTOMATIC``h]hDPLL_MODE_AUTOMATIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh3) the user can request one of following pin states:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKVhjhhubj)}(hhh](j)}(hl``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithmh]h)}(hl``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithmh](ji)}(h``DPLL_PIN_STATE_SELECTABLE``h]hDPLL_PIN_STATE_SELECTABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubhO - the pin shall be considered as valid input for automatic selection algorithm}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hu``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithm h]h)}(ht``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithmh](ji)}(h``DPLL_PIN_STATE_DISCONNECTED``h]hDPLL_PIN_STATE_DISCONNECTED}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj2ubhU - the pin shall be not considered as a valid input for automatic selection algorithm}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK[hj.ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKYhjhhubh)}(hXlPins that have the ``DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE`` capability can additionally be set to ``DPLL_PIN_STATE_CONNECTED`` in automatic mode, overriding the active input selection. This is useful for automatic-only DPLL devices where mode cannot be switched to manual. When such a pin is disconnected, the device returns to automatic input selection.h](hPins that have the }(hjZhhhNhNubji)}(h2``DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE``h]h.DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjZubh' capability can additionally be set to }(hjZhhhNhNubji)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjZubh in automatic mode, overriding the active input selection. This is useful for automatic-only DPLL devices where mode cannot be switched to manual. When such a pin is disconnected, the device returns to automatic input selection.}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubh)}(hThe actual hardware status of a pin is reported via the operational state (``DPLL_A_PIN_OPERSTATE``) attribute nested under the parent device:h](hKThe actual hardware status of a pin is reported via the operational state (}(hjhhhNhNubji)}(h``DPLL_A_PIN_OPERSTATE``h]hDPLL_A_PIN_OPERSTATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh+) attribute nested under the parent device:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKehjhhubj)}(hhh](j)}(hN``DPLL_PIN_OPERSTATE_ACTIVE`` - pin is qualified and actively used by the DPLLh]h)}(hN``DPLL_PIN_OPERSTATE_ACTIVE`` - pin is qualified and actively used by the DPLLh](ji)}(h``DPLL_PIN_OPERSTATE_ACTIVE``h]hDPLL_PIN_OPERSTATE_ACTIVE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh1 - pin is qualified and actively used by the DPLL}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hS``DPLL_PIN_OPERSTATE_STANDBY`` - pin is qualified but not actively used by the DPLLh]h)}(hS``DPLL_PIN_OPERSTATE_STANDBY`` - pin is qualified but not actively used by the DPLLh](ji)}(h``DPLL_PIN_OPERSTATE_STANDBY``h]hDPLL_PIN_OPERSTATE_STANDBY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh5 - pin is qualified but not actively used by the DPLL}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hC``DPLL_PIN_OPERSTATE_NO_SIGNAL`` - pin does not have a valid signalh]h)}(hjh](ji)}(h ``DPLL_PIN_OPERSTATE_NO_SIGNAL``h]hDPLL_PIN_OPERSTATE_NO_SIGNAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh# - pin does not have a valid signal}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hL``DPLL_PIN_OPERSTATE_QUAL_FAILED`` - pin signal failed qualification checks h]h)}(hK``DPLL_PIN_OPERSTATE_QUAL_FAILED`` - pin signal failed qualification checksh](ji)}(h"``DPLL_PIN_OPERSTATE_QUAL_FAILED``h]hDPLL_PIN_OPERSTATE_QUAL_FAILED}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj$ubh) - pin signal failed qualification checks}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKnhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKihjhhubeh}(h] pin-selectionah ]h"] pin selectionah$]h&]uh1hhhhhhhhKBubh)}(hhh](h)}(h Shared pinsh]h Shared pins}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThhhhhKrubh)}(hoA single pin object can be attached to multiple dpll devices. Then there are two groups of configuration knobs:h]hoA single pin object can be attached to multiple dpll devices. Then there are two groups of configuration knobs:}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjThhubhenumerated_list)}(hhh](j)}(hSet on a pin - the configuration is a property of the pin itself and applies to all dpll devices the pin is registered with (i.e., ``DPLL_A_PIN_FREQUENCY``),h]h)}(hSet on a pin - the configuration is a property of the pin itself and applies to all dpll devices the pin is registered with (i.e., ``DPLL_A_PIN_FREQUENCY``),h](hSet on a pin - the configuration is a property of the pin itself and applies to all dpll devices the pin is registered with (i.e., }(hj|hhhNhNubji)}(h``DPLL_A_PIN_FREQUENCY``h]hDPLL_A_PIN_FREQUENCY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj|ubh),}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjxubah}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubj)}(hSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, ``DPLL_A_PIN_DIRECTION``). h]h)}(hSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, ``DPLL_A_PIN_DIRECTION``).h](hUSet on a pin-dpll tuple - the configuration affects only selected dpll device (i.e., }(hjhhhNhNubji)}(h``DPLL_A_PIN_PRIO``h]hDPLL_A_PIN_PRIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh, }(hjhhhNhNubji)}(h``DPLL_A_PIN_STATE``h]hDPLL_A_PIN_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh, }(hjhhhNhNubji)}(h``DPLL_A_PIN_DIRECTION``h]hDPLL_A_PIN_DIRECTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKzhjubah}(h]h ]h"]h$]h&]uh1jhjuhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jshjThhhhhKwubeh}(h] shared-pinsah ]h"] shared pinsah$]h&]uh1hhhhhhhhKrubh)}(hhh](h)}(h MUX-type pinsh]h MUX-type pins}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXCA pin can be MUX-type, it aggregates child pins and serves as a pin multiplexer. One or more pins are registered with MUX-type instead of being directly registered to a dpll device. Pins registered with a MUX-type pin provide user with additional nested attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered with. If a pin was registered with multiple parent pins, they behave like a multiple output multiplexer. In this case output of a ``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested attributes with current state related to each parent, like::h](hXA pin can be MUX-type, it aggregates child pins and serves as a pin multiplexer. One or more pins are registered with MUX-type instead of being directly registered to a dpll device. Pins registered with a MUX-type pin provide user with additional nested attribute }(hjhhhNhNubji)}(h``DPLL_A_PIN_PARENT_PIN``h]hDPLL_A_PIN_PARENT_PIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh for each parent they were registered with. If a pin was registered with multiple parent pins, they behave like a multiple output multiplexer. In this case output of a }(hjhhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhe would contain multiple pin-parent nested attributes with current state related to each parent, like:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh literal_block)}(h'pin': [{{ 'clock-id': 282574471561216, 'module-name': 'ice', 'capabilities': 4, 'id': 13, 'parent-pin': [ {'parent-id': 2, 'state': 'connected'}, {'parent-id': 3, 'state': 'disconnected'} ], 'type': 'synce-eth-port' }}]h]h'pin': [{{ 'clock-id': 282574471561216, 'module-name': 'ice', 'capabilities': 4, 'id': 13, 'parent-pin': [ {'parent-id': 2, 'state': 'connected'}, {'parent-id': 3, 'state': 'disconnected'} ], 'type': 'synce-eth-port' }}]}hjHsbah}(h]h ]h"]h$]h&]hhuh1jFhhhKhjhhubh)}(hXOnly one child pin can provide its signal to the parent MUX-type pin at a time, the selection is done by requesting change of a child pin state on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested attribute. Example of netlink `set state on parent pin` message format:h](hOnly one child pin can provide its signal to the parent MUX-type pin at a time, the selection is done by requesting change of a child pin state on desired parent, with the use of }(hjVhhhNhNubji)}(h``DPLL_A_PIN_PARENT``h]hDPLL_A_PIN_PARENT}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjVubh& nested attribute. Example of netlink }(hjVhhhNhNubjU)}(h`set state on parent pin`h]hset state on parent pin}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jThjVubh message format:}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh block_quote)}(hX========================== ============================================= ``DPLL_A_PIN_ID`` child pin id ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration related to parent pin ``DPLL_A_PIN_PARENT_ID`` parent pin id ``DPLL_A_PIN_STATE`` requested pin state on parent ========================== ============================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h``DPLL_A_PIN_ID``h]ji)}(hjh]h DPLL_A_PIN_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h child pin idh]h child pin id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_PIN``h]ji)}(hjh]hDPLL_A_PIN_PARENT_PIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCnested attribute for requesting configuration related to parent pinh]hCnested attribute for requesting configuration related to parent pin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]ji)}(hj?h]hDPLL_A_PIN_PARENT_ID}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj=ubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(h parent pin idh]h parent pin id}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_STATE``h]ji)}(hjh]hDPLL_A_PIN_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj}ubah}(h]h ]h"]h$]h&]uh1hhhhKhjzubah}(h]h ]h"]h$]h&]uh1jhjwubj)}(hhh]h)}(hrequested pin state on parenth]hrequested pin state on parent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h] mux-type-pinsah ]h"] mux-type pinsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Pin priorityh]h Pin priority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXSome devices might offer a capability of automatic pin selection mode (enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). Usually, automatic selection is performed on the hardware level, which means only pins directly connected to the dpll can be used for automatic input pin selection. In automatic selection mode, the user cannot manually select a input pin for the device, instead the user shall provide all directly connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would pick a highest priority valid signal and use it to control the DPLL device. Example of netlink `set priority on parent pin` message format:h](hRSome devices might offer a capability of automatic pin selection mode (enum value }(hjhhhNhNubji)}(h``DPLL_MODE_AUTOMATIC``h]hDPLL_MODE_AUTOMATIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh of }(hjhhhNhNubji)}(h``DPLL_A_MODE``h]h DPLL_A_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhXV attribute). Usually, automatic selection is performed on the hardware level, which means only pins directly connected to the dpll can be used for automatic input pin selection. In automatic selection mode, the user cannot manually select a input pin for the device, instead the user shall provide all directly connected pins with a priority }(hjhhhNhNubji)}(h``DPLL_A_PIN_PRIO``h]hDPLL_A_PIN_PRIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhr, the device would pick a highest priority valid signal and use it to control the DPLL device. Example of netlink }(hjhhhNhNubjU)}(h`set priority on parent pin`h]hset priority on parent pin}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jThjubh message format:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX============================ ============================================= ``DPLL_A_PIN_ID`` configured pin id ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration related to parent dpll device ``DPLL_A_PIN_PARENT_ID`` parent dpll device id ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll ============================ ============================================= h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjFubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jhjFubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ID``h]ji)}(hjhh]h DPLL_A_PIN_ID}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjfubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(hhh]h)}(hconfigured pin idh]hconfigured pin id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_DEVICE``h]ji)}(hjh]hDPLL_A_PIN_PARENT_DEVICE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKnested attribute for requesting configuration related to parent dpll deviceh]hKnested attribute for requesting configuration related to parent dpll device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]ji)}(hjh]hDPLL_A_PIN_PARENT_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hparent dpll device idh]hparent dpll device id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PRIO``h]ji)}(hj( h]hDPLL_A_PIN_PRIO}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj& ubah}(h]h ]h"]h$]h&]uh1hhhhKhj# ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h!requested pin prio on parent dpllh]h!requested pin prio on parent dpll}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjC ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]colsKuh1jhjCubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubh)}(hChild pin of MUX-type pin is not capable of automatic input pin selection, in order to configure active input of a MUX-type pin, the user needs to request desired pin state of the child pin on the parent pin, as described in the ``MUX-type pins`` chapter.h](hChild pin of MUX-type pin is not capable of automatic input pin selection, in order to configure active input of a MUX-type pin, the user needs to request desired pin state of the child pin on the parent pin, as described in the }(hjy hhhNhNubji)}(h``MUX-type pins``h]h MUX-type pins}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjy ubh chapter.}(hjy hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] pin-priorityah ]h"] pin priorityah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h'Phase offset measurement and adjustmenth]h'Phase offset measurement and adjustment}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXDevice may provide ability to measure a phase difference between signals on a pin and its parent dpll device. If pin-dpll phase offset measurement is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` attribute for each parent dpll device. The reported phase offset may be computed as the average of prior values and the current measurement, using the following formula:h](hDevice may provide ability to measure a phase difference between signals on a pin and its parent dpll device. If pin-dpll phase offset measurement is supported, it shall be provided with }(hj hhhNhNubji)}(h``DPLL_A_PIN_PHASE_OFFSET``h]hDPLL_A_PIN_PHASE_OFFSET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh attribute for each parent dpll device. The reported phase offset may be computed as the average of prior values and the current measurement, using the following formula:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh math_block)}(hFcurr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N} h]hFcurr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N} }hj sbah}(h]h ]h"]h$]h&]docnamedriver-api/dpllnumberNlabelNnowraphhuh1j hhhKhj hhubh)}(hXvwhere `curr_avg` is the current reported phase offset, `prev_avg` is the previously reported value, `new_val` is the current measurement, and `N` is the averaging factor. Configured averaging factor value is provided with ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command.h](hwhere }(hj hhhNhNubjU)}(h `curr_avg`h]hcurr_avg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubh' is the current reported phase offset, }(hj hhhNhNubjU)}(h `prev_avg`h]hprev_avg}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubh# is the previously reported value, }(hj hhhNhNubjU)}(h `new_val`h]hnew_val}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubh! is the current measurement, and }(hj hhhNhNubjU)}(h`N`h]hN}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jThj ubhM is the averaging factor. Configured averaging factor value is provided with }(hj hhhNhNubji)}(h"``DPLL_A_PHASE_OFFSET_AVG_FACTOR``h]hDPLL_A_PHASE_OFFSET_AVG_FACTOR}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubhV attribute of a device and value change can be requested with the same attribute with }(hj hhhNhNubji)}(h``DPLL_CMD_DEVICE_SET``h]hDPLL_CMD_DEVICE_SET}(hjI hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh command.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hX================================== ====================================== ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset averaging factor ================================== ====================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhjh ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK&uh1jhjh ubj)}(hhh]j)}(hhh](j)}(hhh]h)}(h"``DPLL_A_PHASE_OFFSET_AVG_FACTOR``h]ji)}(hj h]hDPLL_A_PHASE_OFFSET_AVG_FACTOR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h6attr configured value of phase offset averaging factorh]h6attr configured value of phase offset averaging factor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjh ubeh}(h]h ]h"]h$]h&]colsKuh1jhje ubah}(h]h ]h"]h$]h&]uh1jhja ubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubh)}(hXDevice may also provide ability to adjust a signal phase on a pin. If pin phase adjustment is supported, minimal and maximal values and granularity that pin handle shall be provided to the user on ``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``, ``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attributes. Configured phase adjust value is provided with ``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.h](hDevice may also provide ability to adjust a signal phase on a pin. If pin phase adjustment is supported, minimal and maximal values and granularity that pin handle shall be provided to the user on }(hj hhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh respond with }(hj hhhNhNubji)}(h``DPLL_A_PIN_PHASE_ADJUST_MIN``h]hDPLL_A_PIN_PHASE_ADJUST_MIN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh, }(hj hhhNhNubji)}(h``DPLL_A_PIN_PHASE_ADJUST_MAX``h]hDPLL_A_PIN_PHASE_ADJUST_MAX}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh and }(hj hhhNhNubji)}(h ``DPLL_A_PIN_PHASE_ADJUST_GRAN``h]hDPLL_A_PIN_PHASE_ADJUST_GRAN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh< attributes. Configured phase adjust value is provided with }(hj hhhNhNubji)}(h``DPLL_A_PIN_PHASE_ADJUST``h]hDPLL_A_PIN_PHASE_ADJUST}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubhT attribute of a pin, and value change can be requested with the same attribute with }(hj hhhNhNubji)}(h``DPLL_CMD_PIN_SET``h]hDPLL_CMD_PIN_SET}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh command.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(hX================================ ========================================== ``DPLL_A_PIN_ID`` configured pin id ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase adjustment on parent dpll device ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration on given parent dpll device ``DPLL_A_PIN_PARENT_ID`` parent dpll device id ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference between a pin and parent dpll device ================================ ========================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhj\ ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jhj\ ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ID``h]ji)}(hj~ h]h DPLL_A_PIN_ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj| ubah}(h]h ]h"]h$]h&]uh1hhhhKhjy ubah}(h]h ]h"]h$]h&]uh1jhjv ubj)}(hhh]h)}(hconfigured pin idh]hconfigured pin id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjv ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h ``DPLL_A_PIN_PHASE_ADJUST_GRAN``h]ji)}(hj h]hDPLL_A_PIN_PHASE_ADJUST_GRAN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h*attr granularity of phase adjustment valueh]h*attr granularity of phase adjustment value}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MIN``h]ji)}(hj h]hDPLL_A_PIN_PHASE_ADJUST_MIN}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h&attr minimum value of phase adjustmenth]h&attr minimum value of phase adjustment}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST_MAX``h]ji)}(hj> h]hDPLL_A_PIN_PHASE_ADJUST_MAX}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj< ubah}(h]h ]h"]h$]h&]uh1hhhhKhj9 ubah}(h]h ]h"]h$]h&]uh1jhj6 ubj)}(hhh]h)}(h&attr maximum value of phase adjustmenth]h&attr maximum value of phase adjustment}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjY ubah}(h]h ]h"]h$]h&]uh1jhj6 ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_ADJUST``h]ji)}(hj~ h]hDPLL_A_PIN_PHASE_ADJUST}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj| ubah}(h]h ]h"]h$]h&]uh1hhhhKhjy ubah}(h]h ]h"]h$]h&]uh1jhjv ubj)}(hhh]h)}(h?attr configured value of phase adjustment on parent dpll deviceh]h?attr configured value of phase adjustment on parent dpll device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjv ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_DEVICE``h]ji)}(hj h]hDPLL_A_PIN_PARENT_DEVICE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInested attribute for requesting configuration on given parent dpll deviceh]hInested attribute for requesting configuration on given parent dpll device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PARENT_ID``h]ji)}(hj h]hDPLL_A_PIN_PARENT_ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hparent dpll device idh]hparent dpll device id}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_PHASE_OFFSET``h]ji)}(hj> h]hDPLL_A_PIN_PHASE_OFFSET}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj< ubah}(h]h ]h"]h$]h&]uh1hhhhKhj9 ubah}(h]h ]h"]h$]h&]uh1jhj6 ubj)}(hhh]h)}(hCattr measured phase difference between a pin and parent dpll deviceh]hCattr measured phase difference between a pin and parent dpll device}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjY ubah}(h]h ]h"]h$]h&]uh1jhj6 ubeh}(h]h ]h"]h$]h&]uh1jhjs ubeh}(h]h ]h"]h$]h&]uh1jhj\ ubeh}(h]h ]h"]h$]h&]colsKuh1jhjY ubah}(h]h ]h"]h$]h&]uh1jhjU ubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubh)}(hX#All phase related values are provided in pico seconds, which represents time difference between signals phase. The negative value means that phase of signal on pin is earlier in time than dpll's signal. Positive value means that phase of signal on pin is later in time than signal of a dpll.h]hX%All phase related values are provided in pico seconds, which represents time difference between signals phase. The negative value means that phase of signal on pin is earlier in time than dpll’s signal. Positive value means that phase of signal on pin is later in time than signal of a dpll.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hPhase adjust (also min and max) values are integers, but measured phase offset values are fractional with 3-digit decimal places and shell be divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and modulo divided to get fractional part.h](hPhase adjust (also min and max) values are integers, but measured phase offset values are fractional with 3-digit decimal places and shell be divided with }(hj hhhNhNubji)}(h!``DPLL_PIN_PHASE_OFFSET_DIVIDER``h]hDPLL_PIN_PHASE_OFFSET_DIVIDER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh? to get integer part and modulo divided to get fractional part.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]'phase-offset-measurement-and-adjustmentah ]h"]'phase offset measurement and adjustmentah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hPhase offset monitorh]hPhase offset monitor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hXPhase offset measurement is typically performed against the current active source. However, some DPLL (Digital Phase-Locked Loop) devices may offer the capability to monitor phase offsets across all available inputs. The attribute and current feature state shall be included in the response message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. In such cases, users can also control the feature using the ``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` values for the attribute. Once enabled the phase offset measurements for the input shall be returned in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute.h](hX2Phase offset measurement is typically performed against the current active source. However, some DPLL (Digital Phase-Locked Loop) devices may offer the capability to monitor phase offsets across all available inputs. The attribute and current feature state shall be included in the response message of the }(hj hhhNhNubji)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubha command for supported DPLL devices. In such cases, users can also control the feature using the }(hj hhhNhNubji)}(h``DPLL_CMD_DEVICE_SET``h]hDPLL_CMD_DEVICE_SET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh command by setting the }(hj hhhNhNubji)}(h``enum dpll_feature_state``h]henum dpll_feature_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubhm values for the attribute. Once enabled the phase offset measurements for the input shall be returned in the }(hj hhhNhNubji)}(h``DPLL_A_PIN_PHASE_OFFSET``h]hDPLL_A_PIN_PHASE_OFFSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ubh attribute.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(h=============================== ======================== ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature =============================== ======================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj3ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj3ubj)}(hhh]j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PHASE_OFFSET_MONITOR``h]ji)}(hjUh]hDPLL_A_PHASE_OFFSET_MONITOR}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjSubah}(h]h ]h"]h$]h&]uh1hhhhM hjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(hattr state of a featureh]hattr state of a feature}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjpubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]colsKuh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhhhM hj hhubeh}(h]phase-offset-monitorah ]h"]phase offset monitorah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hFractional frequency offseth]hFractional frequency offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe fractional frequency offset (FFO) is reported through two attributes that carry the same measurement at different precisions:h]hThe fractional frequency offset (FFO) is reported through two attributes that carry the same measurement at different precisions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(hE``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET`` in PPM (parts per million)h]h)}(hjh](ji)}(h*``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET``h]h&DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh in PPM (parts per million)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hK``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT`` in PPT (parts per trillion) h]h)}(hJ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT`` in PPT (parts per trillion)h](ji)}(h.``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT``h]h*DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh in PPT (parts per trillion)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjhhubh)}(hwBoth attributes appear at the top level of a pin and inside each ``pin-parent-device`` nest. Two FFO types are defined:h](hABoth attributes appear at the top level of a pin and inside each }(hj!hhhNhNubji)}(h``pin-parent-device``h]hpin-parent-device}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj!ubh! nest. Two FFO types are defined:}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(hE``DPLL_FFO_PORT_RXTX_RATE`` - RX vs TX symbol rate offset (top-level)h]h)}(hjFh](ji)}(h``DPLL_FFO_PORT_RXTX_RATE``h]hDPLL_FFO_PORT_RXTX_RATE}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjHubh* - RX vs TX symbol rate offset (top-level)}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhjAhhhhhNubj)}(hA``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent) h]h)}(h@``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent)h](ji)}(h``DPLL_FFO_PIN_DEVICE``h]hDPLL_FFO_PIN_DEVICE}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjmubh) - pin vs parent DPLL offset (per-parent)}(hjmhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjAhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjhhubh)}(hXThe driver declares which types it supports via the ``supported_ffo`` bitmask in ``struct dpll_pin_ops``. The core only calls the ``ffo_get`` callback for types the driver has opted into. The requested type is passed to the driver in the ``struct dpll_ffo_param``.h](h4The driver declares which types it supports via the }(hjhhhNhNubji)}(h``supported_ffo``h]h supported_ffo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh bitmask in }(hjhhhNhNubji)}(h``struct dpll_pin_ops``h]hstruct dpll_pin_ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh. The core only calls the }(hjhhhNhNubji)}(h ``ffo_get``h]hffo_get}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubha callback for types the driver has opted into. The requested type is passed to the driver in the }(hjhhhNhNubji)}(h``struct dpll_ffo_param``h]hstruct dpll_ffo_param}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]fractional-frequency-offsetah ]h"]fractional frequency offsetah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hFrequency monitorh]hFrequency monitor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM"ubh)}(hXSome DPLL devices may offer the capability to measure the actual frequency of all available input pins. The attribute and current feature state shall be included in the response message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. In such cases, users can also control the feature using the ``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` values for the attribute. Once enabled the measured input frequency for each input pin shall be returned in the ``DPLL_A_PIN_MEASURED_FREQUENCY`` attribute. The value is in millihertz (mHz), using ``DPLL_PIN_MEASURED_FREQUENCY_DIVIDER`` as the divider.h](hSome DPLL devices may offer the capability to measure the actual frequency of all available input pins. The attribute and current feature state shall be included in the response message of the }(hjhhhNhNubji)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubha command for supported DPLL devices. In such cases, users can also control the feature using the }(hjhhhNhNubji)}(h``DPLL_CMD_DEVICE_SET``h]hDPLL_CMD_DEVICE_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh command by setting the }(hjhhhNhNubji)}(h``enum dpll_feature_state``h]henum dpll_feature_state}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhq values for the attribute. Once enabled the measured input frequency for each input pin shall be returned in the }(hjhhhNhNubji)}(h!``DPLL_A_PIN_MEASURED_FREQUENCY``h]hDPLL_A_PIN_MEASURED_FREQUENCY}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh4 attribute. The value is in millihertz (mHz), using }(hjhhhNhNubji)}(h'``DPLL_PIN_MEASURED_FREQUENCY_DIVIDER``h]h#DPLL_PIN_MEASURED_FREQUENCY_DIVIDER}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh as the divider.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubj)}(h=============================== ======================== ``DPLL_A_FREQUENCY_MONITOR`` attr state of a feature =============================== ======================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjsubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjsubj)}(hhh]j)}(hhh](j)}(hhh]h)}(h``DPLL_A_FREQUENCY_MONITOR``h]ji)}(hjh]hDPLL_A_FREQUENCY_MONITOR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr state of a featureh]hattr state of a feature}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]colsKuh1jhjpubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhhhM/hjhhubeh}(h]frequency-monitorah ]h"]frequency monitorah$]h&]uh1hhhhhhhhM"ubh)}(hhh](h)}(h Embedded SYNCh]h Embedded SYNC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM4ubh)}(hXDevice may provide ability to use Embedded SYNC feature. It allows to embed additional SYNC signal into the base frequency of a pin - a one special pulse of base frequency signal every time SYNC signal pulse happens. The user can configure the frequency of Embedded SYNC. The Embedded SYNC capability is always related to a given base frequency and HW capabilities. The user is provided a range of Embedded SYNC frequencies supported, depending on current base frequency configured for the pin.h]hXDevice may provide ability to use Embedded SYNC feature. It allows to embed additional SYNC signal into the base frequency of a pin - a one special pulse of base frequency signal every time SYNC signal pulse happens. The user can configure the frequency of Embedded SYNC. The Embedded SYNC capability is always related to a given base frequency and HW capabilities. The user is provided a range of Embedded SYNC frequencies supported, depending on current base frequency configured for the pin.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hjhhubj)}(hX>========================================= ================================= ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC frequency ranges ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC ========================================= ================================= h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK)uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ESYNC_FREQUENCY``h]ji)}(hj6h]hDPLL_A_PIN_ESYNC_FREQUENCY}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj4ubah}(h]h ]h"]h$]h&]uh1hhhhM@hj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh]h)}(hcurrent Embedded SYNC frequencyh]hcurrent Embedded SYNC frequency}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjQubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh](j)}(hhh]h)}(h(``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED``h]ji)}(hjvh]h$DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjtubah}(h]h ]h"]h$]h&]uh1hhhhMAhjqubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]h)}(h-nest available Embedded SYNC frequency rangesh]h-nest available Embedded SYNC frequency ranges}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_FREQUENCY_MIN``h]ji)}(hjh]hDPLL_A_PIN_FREQUENCY_MIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr minimum value of frequencyh]hattr minimum value of frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_FREQUENCY_MAX``h]ji)}(hjh]hDPLL_A_PIN_FREQUENCY_MAX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr maximum value of frequencyh]hattr maximum value of frequency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ESYNC_PULSE``h]ji)}(hj6h]hDPLL_A_PIN_ESYNC_PULSE}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj4ubah}(h]h ]h"]h$]h&]uh1hhhhMEhj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh]h)}(hpulse type of Embedded SYNCh]hpulse type of Embedded SYNC}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjQubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]Vh&]uh1jhhhM?hjhhubeh}(h] embedded-syncah ]h"] embedded syncah$]h&]uh1hhhhhhhhM4ubh)}(hhh](h)}(hReference SYNCh]hReference SYNC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMIubh)}(hXThe device may support the Reference SYNC feature, which allows the combination of two inputs into a input pair. In this configuration, clock signals from both inputs are used to synchronize the DPLL device. The higher frequency signal is utilized for the loop bandwidth of the DPLL, while the lower frequency signal is used to syntonize the output signal of the DPLL device. This feature enables the provision of a high-quality loop bandwidth signal from an external source.h]hXThe device may support the Reference SYNC feature, which allows the combination of two inputs into a input pair. In this configuration, clock signals from both inputs are used to synchronize the DPLL device. The higher frequency signal is utilized for the loop bandwidth of the DPLL, while the lower frequency signal is used to syntonize the output signal of the DPLL device. This feature enables the provision of a high-quality loop bandwidth signal from an external source.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjhhubh)}(hXTA capable input provides a list of inputs that can be bound with to create Reference SYNC. To control this feature, the user must request a desired state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or ``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be bound to only one other pin at any given time.h](hA capable input provides a list of inputs that can be bound with to create Reference SYNC. To control this feature, the user must request a desired state for a target pin: use }(hjhhhNhNubji)}(h``DPLL_PIN_STATE_CONNECTED``h]hDPLL_PIN_STATE_CONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh to enable or }(hjhhhNhNubji)}(h``DPLL_PIN_STATE_DISCONNECTED``h]hDPLL_PIN_STATE_DISCONNECTED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubh[ to disable the feature. An input pin can be bound to only one other pin at any given time.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMShjhhubj)}(hX============================== ========================================== ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or requesting configuration of the Reference SYNC feature ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature ``DPLL_A_PIN_STATE`` state of Reference SYNC connection ============================== ========================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_REFERENCE_SYNC``h]ji)}(hj h]hDPLL_A_PIN_REFERENCE_SYNC}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h]nested attribute for providing info or requesting configuration of the Reference SYNC featureh]h]nested attribute for providing info or requesting configuration of the Reference SYNC feature}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_ID``h]ji)}(hjIh]h DPLL_A_PIN_ID}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjGubah}(h]h ]h"]h$]h&]uh1hhhhM]hjDubah}(h]h ]h"]h$]h&]uh1jhjAubj)}(hhh]h)}(h(target pin id for Reference SYNC featureh]h(target pin id for Reference SYNC feature}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjdubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_PIN_STATE``h]ji)}(hjh]hDPLL_A_PIN_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhM^hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h"state of Reference SYNC connectionh]h"state of Reference SYNC connection}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhMYhjhhubeh}(h]reference-syncah ]h"]reference syncah$]h&]uh1hhhhhhhhMIubh)}(hhh](h)}(hConfiguration commands grouph]hConfiguration commands group}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMbubh)}(hXAConfiguration commands are used to get information about registered dpll devices (and pins), as well as set configuration of device or pins. As dpll devices must be abstracted and reflect real hardware, there is no way to add new dpll device via netlink from user space and each device should be registered by its driver.h]hXAConfiguration commands are used to get information about registered dpll devices (and pins), as well as set configuration of device or pins. As dpll devices must be abstracted and reflect real hardware, there is no way to add new dpll device via netlink from user space and each device should be registered by its driver.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjhhubh)}(hAll netlink commands require ``GENL_ADMIN_PERM``. This is to prevent any spamming/DoS from unauthorized userspace applications.h](hAll netlink commands require }(hjhhhNhNubji)}(h``GENL_ADMIN_PERM``h]hGENL_ADMIN_PERM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubhO. This is to prevent any spamming/DoS from unauthorized userspace applications.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMjhjhhubeh}(h]configuration-commands-groupah ]h"]configuration commands groupah$]h&]uh1hhhhhhhhMbubh)}(hhh](h)}(h1List of netlink commands with possible attributesh]h1List of netlink commands with possible attributes}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMnubh)}(hConstants identifying command types for dpll device uses a ``DPLL_CMD_`` prefix and suffix according to command purpose. The dpll device related attributes use a ``DPLL_A_`` prefix and suffix according to attribute purpose.h](h;Constants identifying command types for dpll device uses a }(hj:hhhNhNubji)}(h ``DPLL_CMD_``h]h DPLL_CMD_}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj:ubhZ prefix and suffix according to command purpose. The dpll device related attributes use a }(hj:hhhNhNubji)}(h ``DPLL_A_``h]hDPLL_A_}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj:ubh2 prefix and suffix according to attribute purpose.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMphj)hhubj)}(hX==================================== ================================= ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID ``DPLL_A_MODULE_NAME`` attr module name of registerer ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard ``DPLL_A_TYPE`` attr type of dpll device ==================================== ================================= ==================================== ================================= ``DPLL_CMD_DEVICE_GET`` command to get device info or dump list of available devices ``DPLL_A_ID`` attr unique dpll device ID ``DPLL_A_MODULE_NAME`` attr module name of registerer ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard ``DPLL_A_MODE`` attr selection mode ``DPLL_A_MODE_SUPPORTED`` attr available selection modes ``DPLL_A_LOCK_STATUS`` attr dpll device lock status ``DPLL_A_TEMP`` attr device temperature info ``DPLL_A_TYPE`` attr type of dpll device ==================================== ================================= ==================================== ================================= ``DPLL_CMD_DEVICE_SET`` command to set dpll device config ``DPLL_A_ID`` attr internal dpll device index ``DPLL_A_MODE`` attr selection mode to configure ==================================== ================================= h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjsubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhjsubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_ID_GET``h]ji)}(hjh]hDPLL_CMD_DEVICE_ID_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMvhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hcommand to get device IDh]hcommand to get device ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_MODULE_NAME``h]ji)}(hjh]hDPLL_A_MODULE_NAME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMwhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hattr module name of registererh]hattr module name of registerer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_CLOCK_ID``h]ji)}(hjh]hDPLL_A_CLOCK_ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMxhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hKattr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standardh]hKattr Unique Clock Identifier (EUI-64), as defined by the IEEE 1588 standard}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj0ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h``DPLL_A_TYPE``h]ji)}(hjUh]h DPLL_A_TYPE}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjSubah}(h]h ]h"]h$]h&]uh1hhhhM{hjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(hattr type of dpll deviceh]hattr type of dpll device}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjpubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]colsKuh1jhjpubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_GET``h]ji)}(hjh]hDPLL_CMD_DEVICE_GET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hhj*ubah}(h]h ]h"]h$]h&]uh1j'hj{*ubeh}(h]h ]h"]h$]h&]uh1j'hj*hK?hjx*ubj')}(h``DPLL_LOCK_STATUS_ERROR_UNDEFINED`` dpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type. h](j')}(h$``DPLL_LOCK_STATUS_ERROR_UNDEFINED``h]ji)}(hj*h]h DPLL_LOCK_STATUS_ERROR_UNDEFINED}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj*ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKDhj*ubj')}(hhh]h)}(hdpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type.h]hdpll device lock status was changed due to undefined error. Driver fills this value up in case it is not able to obtain suitable exact error type.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKBhj*ubah}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1j'hj*hKDhjx*ubj')}(h``DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN`` dpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. h](j')}(h%``DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN``h]ji)}(hj*h]h!DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj*ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKJhj*ubj')}(hhh]h)}(hdpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h]hdpll device lock status was changed because of associated media got down. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKGhj +ubah}(h]h ]h"]h$]h&]uh1j'hj*ubeh}(h]h ]h"]h$]h&]uh1j'hj +hKJhjx*ubj')}(hX``DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH`` the FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h](j')}(h?``DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH``h]ji)}(hj/+h]h;DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH}(hj1+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj-+ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKOhj)+ubj')}(hhh]h)}(hthe FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.h]hthe FFO (Fractional Frequency Offset) between the RX and TX symbol rate on the media got too high. This may happen for example if dpll device was previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.}(hjH+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKMhjE+ubah}(h]h ]h"]h$]h&]uh1j'hj)+ubeh}(h]h ]h"]h$]h&]uh1j'hjD+hKOhjx*ubeh}(h]h ]h"]h$]h&]uh1j'hj\*ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_type (C enum) c.dpll_typehNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(h dpll_typeh]j.')}(henum dpll_typeh](j4')}(hj7'h]henum}(hj+hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj+hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKUubjF')}(h h]h }(hj+hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj+hhhj+hKUubjW')}(h dpll_typeh]j]')}(hj+h]h dpll_type}(hj+hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hj+ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj+hhhj+hKUubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj+hhhj+hKUubah}(h]j|+ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hj+hKUhj~+hhubj')}(hhh]h)}(h4type of dpll, valid values for DPLL_A_TYPE attributeh]h4type of dpll, valid values for DPLL_A_TYPE attribute}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKmhj+hhubah}(h]h ]h"]h$]h&]uh1j'hj~+hhhj+hKUubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j+j'j+j'j'j'uh1j"'hhhj'hNhNubj')}(h**Constants** ``DPLL_TYPE_PPS`` dpll produces Pulse-Per-Second signal ``DPLL_TYPE_EEC`` dpll drives the Ethernet Equipment Clock ``DPLL_TYPE_GENERIC`` generic dpll type for devices outside PPS/EEC classesh](h)}(h **Constants**h]j')}(hj+h]h Constants}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj+ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKqhj+ubj')}(hhh](j')}(h8``DPLL_TYPE_PPS`` dpll produces Pulse-Per-Second signal h](j')}(h``DPLL_TYPE_PPS``h]ji)}(hj ,h]h DPLL_TYPE_PPS}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj ,ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKthj,ubj')}(hhh]h)}(h%dpll produces Pulse-Per-Second signalh]h%dpll produces Pulse-Per-Second signal}(hj%,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!,hKthj",ubah}(h]h ]h"]h$]h&]uh1j'hj,ubeh}(h]h ]h"]h$]h&]uh1j'hj!,hKthj,ubj')}(h;``DPLL_TYPE_EEC`` dpll drives the Ethernet Equipment Clock h](j')}(h``DPLL_TYPE_EEC``h]ji)}(hjE,h]h DPLL_TYPE_EEC}(hjG,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjC,ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKwhj?,ubj')}(hhh]h)}(h(dpll drives the Ethernet Equipment Clockh]h(dpll drives the Ethernet Equipment Clock}(hj^,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ,hKwhj[,ubah}(h]h ]h"]h$]h&]uh1j'hj?,ubeh}(h]h ]h"]h$]h&]uh1j'hjZ,hKwhj,ubj')}(hK``DPLL_TYPE_GENERIC`` generic dpll type for devices outside PPS/EEC classesh](j')}(h``DPLL_TYPE_GENERIC``h]ji)}(hj~,h]hDPLL_TYPE_GENERIC}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj|,ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKyhjx,ubj')}(hhh]h)}(h5generic dpll type for devices outside PPS/EEC classesh]h5generic dpll type for devices outside PPS/EEC classes}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKzhj,ubah}(h]h ]h"]h$]h&]uh1j'hjx,ubeh}(h]h ]h"]h$]h&]uh1j'hj,hKyhj,ubeh}(h]h ]h"]h$]h&]uh1j'hj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_pin_type (C enum)c.dpll_pin_typehNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(h dpll_pin_typeh]j.')}(henum dpll_pin_typeh](j4')}(hj7'h]henum}(hj,hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj,hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hj,hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj,hhhj,hKubjW')}(h dpll_pin_typeh]j]')}(hj,h]h dpll_pin_type}(hj,hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hj,ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj,hhhj,hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj,hhhj,hKubah}(h]j,ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hj,hKhj,hhubj')}(hhh]h)}(hKdefines possible types of a pin, valid values for DPLL_A_PIN_TYPE attributeh]hKdefines possible types of a pin, valid values for DPLL_A_PIN_TYPE attribute}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhK}hj-hhubah}(h]h ]h"]h$]h&]uh1j'hj,hhhj,hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j2-j'j2-j'j'j'uh1j"'hhhj'hNhNubj')}(hX **Constants** ``DPLL_PIN_TYPE_MUX`` aggregates another layer of selectable pins ``DPLL_PIN_TYPE_EXT`` external input ``DPLL_PIN_TYPE_SYNCE_ETH_PORT`` ethernet port PHY's recovered clock ``DPLL_PIN_TYPE_INT_OSCILLATOR`` device internal oscillator ``DPLL_PIN_TYPE_GNSS`` GNSS recovered clock ``DPLL_PIN_TYPE_INT_NCO`` Device internal numerically controlled oscillator. When connected as a DPLL input, the DPLL enters NCO mode where the output frequency is adjusted by the host via the PTP clock interface.h](h)}(h **Constants**h]j')}(hj<-h]h Constants}(hj>-hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj:-ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj6-ubj')}(hhh](j')}(hB``DPLL_PIN_TYPE_MUX`` aggregates another layer of selectable pins h](j')}(h``DPLL_PIN_TYPE_MUX``h]ji)}(hj[-h]hDPLL_PIN_TYPE_MUX}(hj]-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjY-ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjU-ubj')}(hhh]h)}(h+aggregates another layer of selectable pinsh]h+aggregates another layer of selectable pins}(hjt-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjp-hKhjq-ubah}(h]h ]h"]h$]h&]uh1j'hjU-ubeh}(h]h ]h"]h$]h&]uh1j'hjp-hKhjR-ubj')}(h%``DPLL_PIN_TYPE_EXT`` external input h](j')}(h``DPLL_PIN_TYPE_EXT``h]ji)}(hj-h]hDPLL_PIN_TYPE_EXT}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj-ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj-ubj')}(hhh]h)}(hexternal inputh]hexternal input}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKhj-ubah}(h]h ]h"]h$]h&]uh1j'hj-ubeh}(h]h ]h"]h$]h&]uh1j'hj-hKhjR-ubj')}(hE``DPLL_PIN_TYPE_SYNCE_ETH_PORT`` ethernet port PHY's recovered clock h](j')}(h ``DPLL_PIN_TYPE_SYNCE_ETH_PORT``h]ji)}(hj-h]hDPLL_PIN_TYPE_SYNCE_ETH_PORT}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj-ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj-ubj')}(hhh]h)}(h#ethernet port PHY's recovered clockh]h%ethernet port PHY’s recovered clock}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hKhj-ubah}(h]h ]h"]h$]h&]uh1j'hj-ubeh}(h]h ]h"]h$]h&]uh1j'hj-hKhjR-ubj')}(h<``DPLL_PIN_TYPE_INT_OSCILLATOR`` device internal oscillator h](j')}(h ``DPLL_PIN_TYPE_INT_OSCILLATOR``h]ji)}(hj.h]hDPLL_PIN_TYPE_INT_OSCILLATOR}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj.ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj.ubj')}(hhh]h)}(hdevice internal oscillatorh]hdevice internal oscillator}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hKhj.ubah}(h]h ]h"]h$]h&]uh1j'hj.ubeh}(h]h ]h"]h$]h&]uh1j'hj.hKhjR-ubj')}(h,``DPLL_PIN_TYPE_GNSS`` GNSS recovered clock h](j')}(h``DPLL_PIN_TYPE_GNSS``h]ji)}(hj?.h]hDPLL_PIN_TYPE_GNSS}(hjA.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj=.ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj9.ubj')}(hhh]h)}(hGNSS recovered clockh]hGNSS recovered clock}(hjX.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT.hKhjU.ubah}(h]h ]h"]h$]h&]uh1j'hj9.ubeh}(h]h ]h"]h$]h&]uh1j'hjT.hKhjR-ubj')}(h``DPLL_PIN_TYPE_INT_NCO`` Device internal numerically controlled oscillator. When connected as a DPLL input, the DPLL enters NCO mode where the output frequency is adjusted by the host via the PTP clock interface.h](j')}(h``DPLL_PIN_TYPE_INT_NCO``h]ji)}(hjx.h]hDPLL_PIN_TYPE_INT_NCO}(hjz.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjv.ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjr.ubj')}(hhh]h)}(hDevice internal numerically controlled oscillator. When connected as a DPLL input, the DPLL enters NCO mode where the output frequency is adjusted by the host via the PTP clock interface.h]hDevice internal numerically controlled oscillator. When connected as a DPLL input, the DPLL enters NCO mode where the output frequency is adjusted by the host via the PTP clock interface.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj.ubah}(h]h ]h"]h$]h&]uh1j'hjr.ubeh}(h]h ]h"]h$]h&]uh1j'hj.hKhjR-ubeh}(h]h ]h"]h$]h&]uh1j'hj6-ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_pin_direction (C enum)c.dpll_pin_directionhNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(hdpll_pin_directionh]j.')}(henum dpll_pin_directionh](j4')}(hj7'h]henum}(hj.hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj.hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hj.hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj.hhhj.hKubjW')}(hdpll_pin_directionh]j]')}(hj.h]hdpll_pin_direction}(hj.hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hj.ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj.hhhj.hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj.hhhj.hKubah}(h]j.ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hj.hKhj.hhubj')}(hhh]h)}(hTdefines possible direction of a pin, valid values for DPLL_A_PIN_DIRECTION attributeh]hTdefines possible direction of a pin, valid values for DPLL_A_PIN_DIRECTION attribute}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj/hhubah}(h]h ]h"]h$]h&]uh1j'hj.hhhj.hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j,/j'j,/j'j'j'uh1j"'hhhj'hNhNubj')}(h**Constants** ``DPLL_PIN_DIRECTION_INPUT`` pin used as a input of a signal ``DPLL_PIN_DIRECTION_OUTPUT`` pin used to output the signalh](h)}(h **Constants**h]j')}(hj6/h]h Constants}(hj8/hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj4/ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj0/ubj')}(hhh](j')}(h=``DPLL_PIN_DIRECTION_INPUT`` pin used as a input of a signal h](j')}(h``DPLL_PIN_DIRECTION_INPUT``h]ji)}(hjU/h]hDPLL_PIN_DIRECTION_INPUT}(hjW/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjS/ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjO/ubj')}(hhh]h)}(hpin used as a input of a signalh]hpin used as a input of a signal}(hjn/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjj/hKhjk/ubah}(h]h ]h"]h$]h&]uh1j'hjO/ubeh}(h]h ]h"]h$]h&]uh1j'hjj/hKhjL/ubj')}(h;``DPLL_PIN_DIRECTION_OUTPUT`` pin used to output the signalh](j')}(h``DPLL_PIN_DIRECTION_OUTPUT``h]ji)}(hj/h]hDPLL_PIN_DIRECTION_OUTPUT}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj/ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj/ubj')}(hhh]h)}(hpin used to output the signalh]hpin used to output the signal}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj/ubah}(h]h ]h"]h$]h&]uh1j'hj/ubeh}(h]h ]h"]h$]h&]uh1j'hj/hKhjL/ubeh}(h]h ]h"]h$]h&]uh1j'hj0/ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_pin_state (C enum)c.dpll_pin_statehNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(hdpll_pin_stateh]j.')}(henum dpll_pin_stateh](j4')}(hj7'h]henum}(hj/hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj/hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hj/hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj/hhhj/hKubjW')}(hdpll_pin_stateh]j]')}(hj/h]hdpll_pin_state}(hj0hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hj0ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj/hhhj/hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj/hhhj/hKubah}(h]j/ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hj/hKhj/hhubj')}(hhh]h)}(hMdefines possible states of a pin, valid values for DPLL_A_PIN_STATE attributeh]hMdefines possible states of a pin, valid values for DPLL_A_PIN_STATE attribute}(hj*0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj'0hhubah}(h]h ]h"]h$]h&]uh1j'hj/hhhj/hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'jB0j'jB0j'j'j'uh1j"'hhhj'hNhNubj')}(hX**Constants** ``DPLL_PIN_STATE_CONNECTED`` pin connected, active input of phase locked loop ``DPLL_PIN_STATE_DISCONNECTED`` pin disconnected, not considered as a valid input ``DPLL_PIN_STATE_SELECTABLE`` pin enabled for automatic input selectionh](h)}(h **Constants**h]j')}(hjL0h]h Constants}(hjN0hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hjJ0ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjF0ubj')}(hhh](j')}(hN``DPLL_PIN_STATE_CONNECTED`` pin connected, active input of phase locked loop h](j')}(h``DPLL_PIN_STATE_CONNECTED``h]ji)}(hjk0h]hDPLL_PIN_STATE_CONNECTED}(hjm0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhji0ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhje0ubj')}(hhh]h)}(h0pin connected, active input of phase locked looph]h0pin connected, active input of phase locked loop}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hKhj0ubah}(h]h ]h"]h$]h&]uh1j'hje0ubeh}(h]h ]h"]h$]h&]uh1j'hj0hKhjb0ubj')}(hR``DPLL_PIN_STATE_DISCONNECTED`` pin disconnected, not considered as a valid input h](j')}(h``DPLL_PIN_STATE_DISCONNECTED``h]ji)}(hj0h]hDPLL_PIN_STATE_DISCONNECTED}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj0ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj0ubj')}(hhh]h)}(h1pin disconnected, not considered as a valid inputh]h1pin disconnected, not considered as a valid input}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj0ubah}(h]h ]h"]h$]h&]uh1j'hj0ubeh}(h]h ]h"]h$]h&]uh1j'hj0hKhjb0ubj')}(hG``DPLL_PIN_STATE_SELECTABLE`` pin enabled for automatic input selectionh](j')}(h``DPLL_PIN_STATE_SELECTABLE``h]ji)}(hj0h]hDPLL_PIN_STATE_SELECTABLE}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj0ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj0ubj')}(hhh]h)}(h)pin enabled for automatic input selectionh]h)pin enabled for automatic input selection}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj0ubah}(h]h ]h"]h$]h&]uh1j'hj0ubeh}(h]h ]h"]h$]h&]uh1j'hj0hKhjb0ubeh}(h]h ]h"]h$]h&]uh1j'hjF0ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_pin_operstate (C enum)c.dpll_pin_operstatehNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(hdpll_pin_operstateh]j.')}(henum dpll_pin_operstateh](j4')}(hj7'h]henum}(hj81hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj41hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hjF1hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj41hhhjE1hKubjW')}(hdpll_pin_operstateh]j]')}(hj21h]hdpll_pin_operstate}(hjX1hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hjT1ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj41hhhjE1hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj01hhhjE1hKubah}(h]j+1ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hjE1hKhj-1hhubj')}(hhh]h)}(hdefines possible operational states of a pin with respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE attributeh]hdefines possible operational states of a pin with respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE attribute}(hjz1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjw1hhubah}(h]h ]h"]h$]h&]uh1j'hj-1hhhjE1hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j1j'j1j'j'j'uh1j"'hhhj'hNhNubj')}(hXc**Constants** ``DPLL_PIN_OPERSTATE_ACTIVE`` pin is qualified and actively used by the DPLL ``DPLL_PIN_OPERSTATE_STANDBY`` pin is qualified but not actively used by the DPLL ``DPLL_PIN_OPERSTATE_NO_SIGNAL`` pin does not have a valid signal ``DPLL_PIN_OPERSTATE_QUAL_FAILED`` pin signal failed qualification (e.g. frequency or phase monitor)h](h)}(h **Constants**h]j')}(hj1h]h Constants}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj1ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj1ubj')}(hhh](j')}(hM``DPLL_PIN_OPERSTATE_ACTIVE`` pin is qualified and actively used by the DPLL h](j')}(h``DPLL_PIN_OPERSTATE_ACTIVE``h]ji)}(hj1h]hDPLL_PIN_OPERSTATE_ACTIVE}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj1ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj1ubj')}(hhh]h)}(h.pin is qualified and actively used by the DPLLh]h.pin is qualified and actively used by the DPLL}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hKhj1ubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1j'hj1hKhj1ubj')}(hR``DPLL_PIN_OPERSTATE_STANDBY`` pin is qualified but not actively used by the DPLL h](j')}(h``DPLL_PIN_OPERSTATE_STANDBY``h]ji)}(hj1h]hDPLL_PIN_OPERSTATE_STANDBY}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj1ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj1ubj')}(hhh]h)}(h2pin is qualified but not actively used by the DPLLh]h2pin is qualified but not actively used by the DPLL}(hj 2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj 2ubah}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ]h"]h$]h&]uh1j'hj 2hKhj1ubj')}(hB``DPLL_PIN_OPERSTATE_NO_SIGNAL`` pin does not have a valid signal h](j')}(h ``DPLL_PIN_OPERSTATE_NO_SIGNAL``h]ji)}(hj.2h]hDPLL_PIN_OPERSTATE_NO_SIGNAL}(hj02hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj,2ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj(2ubj')}(hhh]h)}(h pin does not have a valid signalh]h pin does not have a valid signal}(hjG2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjC2hKhjD2ubah}(h]h ]h"]h$]h&]uh1j'hj(2ubeh}(h]h ]h"]h$]h&]uh1j'hjC2hKhj1ubj')}(hd``DPLL_PIN_OPERSTATE_QUAL_FAILED`` pin signal failed qualification (e.g. frequency or phase monitor)h](j')}(h"``DPLL_PIN_OPERSTATE_QUAL_FAILED``h]ji)}(hjg2h]hDPLL_PIN_OPERSTATE_QUAL_FAILED}(hji2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhje2ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhja2ubj')}(hhh]h)}(hApin signal failed qualification (e.g. frequency or phase monitor)h]hApin signal failed qualification (e.g. frequency or phase monitor)}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|2hKhj}2ubah}(h]h ]h"]h$]h&]uh1j'hja2ubeh}(h]h ]h"]h$]h&]uh1j'hj|2hKhj1ubeh}(h]h ]h"]h$]h&]uh1j'hj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_pin_capabilities (C enum)c.dpll_pin_capabilitieshNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(hdpll_pin_capabilitiesh]j.')}(henum dpll_pin_capabilitiesh](j4')}(hj7'h]henum}(hj2hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hj2hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hj2hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hj2hhhj2hKubjW')}(hdpll_pin_capabilitiesh]j]')}(hj2h]hdpll_pin_capabilities}(hj2hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hj2ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hj2hhhj2hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj2hhhj2hKubah}(h]j2ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hj2hKhj2hhubj')}(hhh]h)}(hXdefines possible capabilities of a pin, valid flags on DPLL_A_PIN_CAPABILITIES attributeh]hXdefines possible capabilities of a pin, valid flags on DPLL_A_PIN_CAPABILITIES attribute}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj2hhubah}(h]h ]h"]h$]h&]uh1j'hj2hhhj2hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j3j'j3j'j'j'uh1j"'hhhj'hNhNubj')}(hX**Constants** ``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE`` pin direction can be changed ``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE`` pin priority can be changed ``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE`` pin state can be changed ``DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE`` pin state can be set to connected regardless of current DPLL device mode, overriding the active input selection. Requires state-can-change to be set as well.h](h)}(h **Constants**h]j')}(hj$3h]h Constants}(hj&3hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj"3ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj3ubj')}(hhh](j')}(hL``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE`` pin direction can be changed h](j')}(h.``DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE``h]ji)}(hjC3h]h*DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE}(hjE3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjA3ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj=3ubj')}(hhh]h)}(hpin direction can be changedh]hpin direction can be changed}(hj\3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX3hKhjY3ubah}(h]h ]h"]h$]h&]uh1j'hj=3ubeh}(h]h ]h"]h$]h&]uh1j'hjX3hKhj:3ubj')}(hJ``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE`` pin priority can be changed h](j')}(h-``DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE``h]ji)}(hj|3h]h)DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE}(hj~3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjz3ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhjv3ubj')}(hhh]h)}(hpin priority can be changedh]hpin priority can be changed}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hKhj3ubah}(h]h ]h"]h$]h&]uh1j'hjv3ubeh}(h]h ]h"]h$]h&]uh1j'hj3hKhj:3ubj')}(hD``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE`` pin state can be changed h](j')}(h*``DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE``h]ji)}(hj3h]h&DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj3ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj3ubj')}(hhh]h)}(hpin state can be changedh]hpin state can be changed}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hKhj3ubah}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ]h"]h$]h&]uh1j'hj3hKhj:3ubj')}(h``DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE`` pin state can be set to connected regardless of current DPLL device mode, overriding the active input selection. Requires state-can-change to be set as well.h](j')}(h2``DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE``h]ji)}(hj3h]h.DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj3ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj3ubj')}(hhh]h)}(hpin state can be set to connected regardless of current DPLL device mode, overriding the active input selection. Requires state-can-change to be set as well.h]hpin state can be set to connected regardless of current DPLL device mode, overriding the active input selection. Requires state-can-change to be set as well.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj4ubah}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ]h"]h$]h&]uh1j'hj4hKhj:3ubeh}(h]h ]h"]h$]h&]uh1j'hj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubj')}(hhh]h}(h]h ]h"]h$]h&]entries](j'dpll_feature_state (C enum)c.dpll_feature_statehNtauh1j'hj'hhhNhNubj#')}(hhh](j(')}(hdpll_feature_stateh]j.')}(henum dpll_feature_stateh](j4')}(hj7'h]henum}(hjH4hhhNhNubah}(h]h ]j@'ah"]h$]h&]uh1j3'hjD4hhhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKubjF')}(h h]h }(hjV4hhhNhNubah}(h]h ]jR'ah"]h$]h&]uh1jE'hjD4hhhjU4hKubjW')}(hdpll_feature_stateh]j]')}(hjB4h]hdpll_feature_state}(hjh4hhhNhNubah}(h]h ]jh'ah"]h$]h&]uh1j\'hjd4ubah}(h]h ](jo'jp'eh"]h$]h&]hhuh1jV'hjD4hhhjU4hKubeh}(h]h ]h"]h$]h&]hhjz'uh1j-'j{'j|'hj@4hhhjU4hKubah}(h]j;4ah ](j'j'eh"]h$]h&]j'j')j'huh1j''hjU4hKhj=4hhubj')}(hhh]h)}(hAAllow control (enable/disable) and status checking over features.h]hAAllow control (enable/disable) and status checking over features.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj4hhubah}(h]h ]h"]h$]h&]uh1j'hj=4hhhjU4hKubeh}(h]h ](j'enumeh"]h$]h&]j'j'j'j4j'j4j'j'j'uh1j"'hhhj'hNhNubj')}(h**Constants** ``DPLL_FEATURE_STATE_DISABLE`` feature shall be disabled ``DPLL_FEATURE_STATE_ENABLE`` feature shall be enabledh](h)}(h **Constants**h]j')}(hj4h]h Constants}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j'hj4ubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj4ubj')}(hhh](j')}(h9``DPLL_FEATURE_STATE_DISABLE`` feature shall be disabled h](j')}(h``DPLL_FEATURE_STATE_DISABLE``h]ji)}(hj4h]hDPLL_FEATURE_STATE_DISABLE}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj4ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj4ubj')}(hhh]h)}(hfeature shall be disabledh]hfeature shall be disabled}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1j'hj4hKhj4ubj')}(h6``DPLL_FEATURE_STATE_ENABLE`` feature shall be enabledh](j')}(h``DPLL_FEATURE_STATE_ENABLE``h]ji)}(hj5h]hDPLL_FEATURE_STATE_ENABLE}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj5ubah}(h]h ]h"]h$]h&]uh1j'hZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj4ubj')}(hhh]h)}(hfeature shall be enabledh]hfeature shall be enabled}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhZ/var/lib/git/docbuild/linux/Documentation/driver-api/dpll:530: ./include/uapi/linux/dpll.hhKhj5ubah}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ]h"]h$]h&]uh1j'hj5hKhj4ubeh}(h]h ]h"]h$]h&]uh1j'hj4ubeh}(h]h ] kernelindentah"]h$]h&]uh1j'hj'hhhNhNubeh}(h]configuration-pre-defined-enumsah ]h"]configuration pre-defined enumsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(h Notificationsh]h Notifications}(hjP5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM5hhhhhMubh)}(hdpll device can provide notifications regarding status changes of the device, i.e. lock status changes, input/output changes or other alarms. There is one multicast group that is used to notify user-space apps via netlink socket: ``DPLL_MCGRP_MONITOR``h](hdpll device can provide notifications regarding status changes of the device, i.e. lock status changes, input/output changes or other alarms. There is one multicast group that is used to notify user-space apps via netlink socket: }(hj^5hhhNhNubji)}(h``DPLL_MCGRP_MONITOR``h]hDPLL_MCGRP_MONITOR}(hjf5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj^5ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjM5hhubh)}(hNotifications messages:h]hNotifications messages:}(hjz5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjM5hhubj)}(hX============================== ===================================== ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed ============================== ===================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj5ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK%uh1jhj5ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_CREATE_NTF``h]ji)}(hj5h]hDPLL_CMD_DEVICE_CREATE_NTF}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj5ubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(hdpll device was createdh]hdpll device was created}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_DELETE_NTF``h]ji)}(hj5h]hDPLL_CMD_DEVICE_DELETE_NTF}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj5ubah}(h]h ]h"]h$]h&]uh1hhhhM hj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(hdpll device was deletedh]hdpll device was deleted}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj 6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_DEVICE_CHANGE_NTF``h]ji)}(hj16h]hDPLL_CMD_DEVICE_CHANGE_NTF}(hj36hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj/6ubah}(h]h ]h"]h$]h&]uh1hhhhM!hj,6ubah}(h]h ]h"]h$]h&]uh1jhj)6ubj)}(hhh]h)}(hdpll device has changedh]hdpll device has changed}(hjO6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjL6ubah}(h]h ]h"]h$]h&]uh1jhj)6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_CREATE_NTF``h]ji)}(hjq6h]hDPLL_CMD_PIN_CREATE_NTF}(hjs6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjo6ubah}(h]h ]h"]h$]h&]uh1hhhhM"hjl6ubah}(h]h ]h"]h$]h&]uh1jhji6ubj)}(hhh]h)}(hdpll pin was createdh]hdpll pin was created}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj6ubah}(h]h ]h"]h$]h&]uh1jhji6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_DELETE_NTF``h]ji)}(hj6h]hDPLL_CMD_PIN_DELETE_NTF}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj6ubah}(h]h ]h"]h$]h&]uh1hhhhM#hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]h)}(hdpll pin was deletedh]hdpll pin was deleted}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh](j)}(hhh]h)}(h``DPLL_CMD_PIN_CHANGE_NTF``h]ji)}(hj6h]hDPLL_CMD_PIN_CHANGE_NTF}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj6ubah}(h]h ]h"]h$]h&]uh1hhhhM$hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]h)}(hdpll pin has changedh]hdpll pin has changed}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj 7ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]colsKuh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhhhMhjM5hhubh)}(hEvents format is the same as for the corresponding get command. Format of ``DPLL_CMD_DEVICE_`` events is the same as response of ``DPLL_CMD_DEVICE_GET``. Format of ``DPLL_CMD_PIN_`` events is same as response of ``DPLL_CMD_PIN_GET``.h](hJEvents format is the same as for the corresponding get command. Format of }(hjB7hhhNhNubji)}(h``DPLL_CMD_DEVICE_``h]hDPLL_CMD_DEVICE_}(hjJ7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjB7ubh# events is the same as response of }(hjB7hhhNhNubji)}(h``DPLL_CMD_DEVICE_GET``h]hDPLL_CMD_DEVICE_GET}(hj\7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjB7ubh . Format of }(hjB7hhhNhNubji)}(h``DPLL_CMD_PIN_``h]h DPLL_CMD_PIN_}(hjn7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjB7ubh events is same as response of }(hjB7hhhNhNubji)}(h``DPLL_CMD_PIN_GET``h]hDPLL_CMD_PIN_GET}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjB7ubh.}(hjB7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM'hjM5hhubeh}(h] notificationsah ]h"] notificationsah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hDevice driver implementationh]hDevice driver implementation}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhhhM.ubh)}(hXfDevice is allocated by dpll_device_get() call. Second call with the same arguments will not create new object but provides pointer to previously created device for given arguments, it also increases refcount of that object. Device is deallocated by dpll_device_put() call, which first decreases the refcount, once refcount is cleared the object is destroyed.h]hXfDevice is allocated by dpll_device_get() call. Second call with the same arguments will not create new object but provides pointer to previously created device for given arguments, it also increases refcount of that object. Device is deallocated by dpll_device_put() call, which first decreases the refcount, once refcount is cleared the object is destroyed.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj7hhubh)}(hXDevice should implement set of operations and register device via dpll_device_register() at which point it becomes available to the users. Multiple driver instances can obtain reference to it with dpll_device_get(), as well as register dpll device with their own ops and priv.h]hXDevice should implement set of operations and register device via dpll_device_register() at which point it becomes available to the users. Multiple driver instances can obtain reference to it with dpll_device_get(), as well as register dpll device with their own ops and priv.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj7hhubh)}(hX The pins are allocated separately with dpll_pin_get(), it works similarly to dpll_device_get(). Function first creates object and then for each call with the same arguments only the object refcount increases. Also dpll_pin_put() works similarly to dpll_device_put().h]hX The pins are allocated separately with dpll_pin_get(), it works similarly to dpll_device_get(). Function first creates object and then for each call with the same arguments only the object refcount increases. Also dpll_pin_put() works similarly to dpll_device_put().}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj7hhubh)}(hA pin can be registered with parent dpll device or parent pin, depending on hardware needs. Each registration requires registerer to provide set of pin callbacks, and private data pointer for calling them:h]hA pin can be registered with parent dpll device or parent pin, depending on hardware needs. Each registration requires registerer to provide set of pin callbacks, and private data pointer for calling them:}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj7hhubj)}(hhh](j)}(h6dpll_pin_register() - register pin with a dpll device,h]h)}(hj7h]h6dpll_pin_register() - register pin with a dpll device,}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhj7ubah}(h]h ]h"]h$]h&]uh1jhj7hhhhhNubj)}(hEdpll_pin_on_pin_register() - register pin with another MUX type pin. h]h)}(hDdpll_pin_on_pin_register() - register pin with another MUX type pin.h]hDdpll_pin_on_pin_register() - register pin with another MUX type pin.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj8ubah}(h]h ]h"]h$]h&]uh1jhj7hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMGhj7hhubh)}(hXNotifications of adding or removing dpll devices are created within subsystem itself. Notifications about registering/deregistering pins are also invoked by the subsystem. Notifications about status changes either of dpll device or a pin are invoked in two ways:h]hXNotifications of adding or removing dpll devices are created within subsystem itself. Notifications about registering/deregistering pins are also invoked by the subsystem. Notifications about status changes either of dpll device or a pin are invoked in two ways:}(hj!8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhj7hhubj)}(hhh](j)}(hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,h]h)}(hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,h]hhafter successful change was requested on dpll subsystem, the subsystem calls corresponding notification,}(hj68hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj28ubah}(h]h ]h"]h$]h&]uh1jhj/8hhhhhNubj)}(hrequested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change. h]h)}(h~requested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change.h]h~requested by device driver with dpll_device_change_ntf() or dpll_pin_change_ntf() when driver informs about the status change.}(hjN8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShjJ8ubah}(h]h ]h"]h$]h&]uh1jhj/8hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMQhj7hhubh)}(hThe device driver using dpll interface is not required to implement all the callback operation. Nevertheless, there are few required to be implemented. Required dpll device level callback operations:h]hThe device driver using dpll interface is not required to implement all the callback operation. Nevertheless, there are few required to be implemented. Required dpll device level callback operations:}(hjh8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj7hhubj)}(hhh](j)}(h``.mode_get``,h]h)}(hj{8h](ji)}(h ``.mode_get``h]h .mode_get}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj}8ubh,}(hj}8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM[hjy8ubah}(h]h ]h"]h$]h&]uh1jhjv8hhhhhNubj)}(h``.lock_status_get``. h]h)}(h``.lock_status_get``.h](ji)}(h``.lock_status_get``h]h.lock_status_get}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj8ubh.}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM\hj8ubah}(h]h ]h"]h$]h&]uh1jhjv8hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM[hj7hhubh)}(h'Required pin level callback operations:h]h'Required pin level callback operations:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj7hhubj)}(hhh](j)}(h:``.state_on_dpll_get`` (pins registered with dpll device),h]h)}(hj8h](ji)}(h``.state_on_dpll_get``h]h.state_on_dpll_get}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj8ubh$ (pins registered with dpll device),}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM`hj8ubah}(h]h ]h"]h$]h&]uh1jhj8hhhhhNubj)}(h8``.state_on_pin_get`` (pins registered with parent pin),h]h)}(hj9h](ji)}(h``.state_on_pin_get``h]h.state_on_pin_get}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj9ubh# (pins registered with parent pin),}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMahj9ubah}(h]h ]h"]h$]h&]uh1jhj8hhhhhNubj)}(h``.direction_get``. h]h)}(h``.direction_get``.h](ji)}(h``.direction_get``h]h.direction_get}(hj-9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj)9ubh.}(hj)9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMbhj%9ubah}(h]h ]h"]h$]h&]uh1jhj8hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM`hj7hhubh)}(h~Every other operation handler is checked for existence and ``-EOPNOTSUPP`` is returned in case of absence of specific handler.h](h;Every other operation handler is checked for existence and }(hjQ9hhhNhNubji)}(h``-EOPNOTSUPP``h]h -EOPNOTSUPP}(hjY9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhjQ9ubh4 is returned in case of absence of specific handler.}(hjQ9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMdhj7hhubh)}(hdThe simplest implementation is in the OCP TimeCard driver. The ops structures are defined like this:h]hdThe simplest implementation is in the OCP TimeCard driver. The ops structures are defined like this:}(hjq9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj7hhubjG)}(hXstatic const struct dpll_device_ops dpll_ops = { .lock_status_get = ptp_ocp_dpll_lock_status_get, .mode_get = ptp_ocp_dpll_mode_get, .mode_supported = ptp_ocp_dpll_mode_supported, }; static const struct dpll_pin_ops dpll_pins_ops = { .frequency_get = ptp_ocp_dpll_frequency_get, .frequency_set = ptp_ocp_dpll_frequency_set, .direction_get = ptp_ocp_dpll_direction_get, .direction_set = ptp_ocp_dpll_direction_set, .state_on_dpll_get = ptp_ocp_dpll_state_get, };h]hXstatic const struct dpll_device_ops dpll_ops = { .lock_status_get = ptp_ocp_dpll_lock_status_get, .mode_get = ptp_ocp_dpll_mode_get, .mode_supported = ptp_ocp_dpll_mode_supported, }; static const struct dpll_pin_ops dpll_pins_ops = { .frequency_get = ptp_ocp_dpll_frequency_get, .frequency_set = ptp_ocp_dpll_frequency_set, .direction_get = ptp_ocp_dpll_direction_get, .direction_set = ptp_ocp_dpll_direction_set, .state_on_dpll_get = ptp_ocp_dpll_state_get, };}hj9sbah}(h]h ]h"]h$]h&]hhƌforcelanguagej'highlight_args}uh1jFhhhMjhj7hhubh)}(h3The registration part is then looks like this part:h]h3The registration part is then looks like this part:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj7hhubjG)}(hX clkid = pci_get_dsn(pdev); bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); if (IS_ERR(bp->dpll)) { err = PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); goto out; } err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); if (err) goto out; for (i = 0; i < OCP_SMA_NUM; i++) { bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); if (IS_ERR(bp->sma[i].dpll_pin)) { err = PTR_ERR(bp->dpll); goto out_dpll; } err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { dpll_pin_put(bp->sma[i].dpll_pin); goto out_dpll; } }h]hX clkid = pci_get_dsn(pdev); bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); if (IS_ERR(bp->dpll)) { err = PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); goto out; } err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); if (err) goto out; for (i = 0; i < OCP_SMA_NUM; i++) { bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); if (IS_ERR(bp->sma[i].dpll_pin)) { err = PTR_ERR(bp->dpll); goto out_dpll; } err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { dpll_pin_put(bp->sma[i].dpll_pin); goto out_dpll; } }}hj9sbah}(h]h ]h"]h$]h&]hhj9j9j'j9}uh1jFhhhM|hj7hhubh)}(hJIn the error path we have to rewind every allocation in the reverse order:h]hJIn the error path we have to rewind every allocation in the reverse order:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7hhubjG)}(hwhile (i) { --i; dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); dpll_pin_put(bp->sma[i].dpll_pin); } dpll_device_put(bp->dpll);h]hwhile (i) { --i; dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); dpll_pin_put(bp->sma[i].dpll_pin); } dpll_device_put(bp->dpll);}hj9sbah}(h]h ]h"]h$]h&]hhj9j9j'j9}uh1jFhhhMhj7hhubh)}(hPMore complex example can be found in Intel's ICE driver or nVidia's mlx5 driver.h]hTMore complex example can be found in Intel’s ICE driver or nVidia’s mlx5 driver.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7hhubeh}(h]device-driver-implementationah ]h"]device driver implementationah$]h&]uh1hhhhhhhhM.ubh)}(hhh](h)}(hSyncE enablementh]hSyncE enablement}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMubh)}(hXFor SyncE enablement it is required to allow control over dpll device for a software application which monitors and configures the inputs of dpll device in response to current state of a dpll device and its inputs. In such scenario, dpll device input signal shall be also configurable to drive dpll with signal recovered from the PHY netdevice. This is done by exposing a pin to the netdevice - attaching pin to the netdevice itself with ``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in nested attribute ``IFLA_DPLL_PIN``.h](hXFor SyncE enablement it is required to allow control over dpll device for a software application which monitors and configures the inputs of dpll device in response to current state of a dpll device and its inputs. In such scenario, dpll device input signal shall be also configurable to drive dpll with signal recovered from the PHY netdevice. This is done by exposing a pin to the netdevice - attaching pin to the netdevice itself with }(hj9hhhNhNubji)}(hJ``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``h]hFdpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj9ubh. Exposed pin id handle }(hj9hhhNhNubji)}(h``DPLL_A_PIN_ID``h]h DPLL_A_PIN_ID}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj9ubhP is then identifiable by the user as it is attached to rtnetlink respond to get }(hj9hhhNhNubji)}(h``RTM_NEWLINK``h]h RTM_NEWLINK}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj9ubh command in nested attribute }(hj9hhhNhNubji)}(h``IFLA_DPLL_PIN``h]h IFLA_DPLL_PIN}(hj0:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhj9ubh.}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubeh}(h]synce-enablementah ]h"]synce enablementah$]h&]uh1hhhhhhhhMubeh}(h]the-linux-kernel-dpll-subsystemah ]h"]the linux kernel dpll subsystemah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjz:error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jU:jR:jjj8j5jjjjjQjNjjjjj j j j jjjjjjjjjjj&j#jW%jT%j%j%j&j&jJ5jG5j7j7j9j9jM:jJ:u nametypes}(jU:jj8jjjQjjj j jjjjjj&jW%j%j&jJ5j7j9jM:uh}(jR:hjhj5jjj;jjjNjjjTjjj jj j jj jjjjjjjjj#jjT%j)j%jZ%j&j%jG5j'j 'j)'jg(jl(j)j)j|+j+j,j,j.j.j/j/j+1j01j2j2j;4j@4j7jM5j9j7jJ:j9u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.