€• m      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ0/translations/zh_CN/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/zh_TW/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/it_IT/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ja_JP/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ko_KR/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/pt_BR/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/sp_SP/driver-api/dmaengine/pxa_dma”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒPXA/MMP - DMA Slave controller”h]”hŒPXA/MMP - DMA Slave controller”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒJ/var/lib/git/docbuild/linux/Documentation/driver-api/dmaengine/pxa_dma.rst”h´Kubh¶)”}”(hhh]”(h»)”}”(hŒConstraints”h]”hŒConstraints”…””}”(hhÎh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhËh²hh³hÊh´KubhŒ	paragraph”“”)”}”(hX4  a) Transfers hot queuing
A driver submitting a transfer and issuing it should be granted the transfer
is queued even on a running DMA channel.
This implies that the queuing doesn't wait for the previous transfer end,
and that the descriptor chaining is not only done in the irq/tasklet code
triggered by the end of the transfer.
A transfer which is submitted and issued on a phy doesn't wait for a phy to
stop and restart, but is submitted on a "running channel". The other
drivers, especially mmp_pdma waited for the phy to stop before relaunching
a new transfer.”h]”hX<  a) Transfers hot queuing
A driver submitting a transfer and issuing it should be granted the transfer
is queued even on a running DMA channel.
This implies that the queuing doesnâ€™t wait for the previous transfer end,
and that the descriptor chaining is not only done in the irq/tasklet code
triggered by the end of the transfer.
A transfer which is submitted and issued on a phy doesnâ€™t wait for a phy to
stop and restart, but is submitted on a â€œrunning channelâ€. The other
drivers, especially mmp_pdma waited for the phy to stop before relaunching
a new transfer.”…””}”(hhÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)”}”(hX<  b) All transfers having asked for confirmation should be signaled
Any issued transfer with DMA_PREP_INTERRUPT should trigger a callback call.
This implies that even if an irq/tasklet is triggered by end of tx1, but
at the time of irq/dma tx2 is already finished, tx1->complete() and
tx2->complete() should be called.”h]”hX<  b) All transfers having asked for confirmation should be signaled
Any issued transfer with DMA_PREP_INTERRUPT should trigger a callback call.
This implies that even if an irq/tasklet is triggered by end of tx1, but
at the time of irq/dma tx2 is already finished, tx1->complete() and
tx2->complete() should be called.”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)”}”(hXv  c) Channel running state
A driver should be able to query if a channel is running or not. For the
multimedia case, such as video capture, if a transfer is submitted and then
a check of the DMA channel reports a "stopped channel", the transfer should
not be issued until the next "start of frame interrupt", hence the need to
know if a channel is in running or stopped state.”h]”hX~  c) Channel running state
A driver should be able to query if a channel is running or not. For the
multimedia case, such as video capture, if a transfer is submitted and then
a check of the DMA channel reports a â€œstopped channelâ€, the transfer should
not be issued until the next â€œstart of frame interruptâ€, hence the need to
know if a channel is in running or stopped state.”…””}”(hhúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhhËh²hubhÝ)”}”(hXF  d) Bandwidth guarantee
The PXA architecture has 4 levels of DMAs priorities : high, normal, low.
The high priorities get twice as much bandwidth as the normal, which get twice
as much as the low priorities.
A driver should be able to request a priority, especially the real-time
ones such as pxa_camera with (big) throughputs.”h]”hXF  d) Bandwidth guarantee
The PXA architecture has 4 levels of DMAs priorities : high, normal, low.
The high priorities get twice as much bandwidth as the normal, which get twice
as much as the low priorities.
A driver should be able to request a priority, especially the real-time
ones such as pxa_camera with (big) throughputs.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K hhËh²hubeh}”(h]”Œconstraints”ah ]”h"]”Œconstraints”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒDesign”h]”hŒDesign”…””}”(hj!  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´K(ubhÝ)”}”(hŒÒa) Virtual channels
Same concept as in sa11x0 driver, ie. a driver was assigned a "virtual
channel" linked to the requester line, and the physical DMA channel is
assigned on the fly when the transfer is issued.”h]”hŒÖa) Virtual channels
Same concept as in sa11x0 driver, ie. a driver was assigned a â€œvirtual
channelâ€ linked to the requester line, and the physical DMA channel is
assigned on the fly when the transfer is issued.”…””}”(hj/  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K)hj  h²hubhŒenumerated_list”“”)”}”(hhh]”hŒ	list_item”“”)”}”(hŒ/Transfer anatomy for a scatter-gather transfer
”h]”hÝ)”}”(hŒ.Transfer anatomy for a scatter-gather transfer”h]”hŒ.Transfer anatomy for a scatter-gather transfer”…””}”(hjH  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K.hjD  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj?  h²hh³hÊh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œ
loweralpha”Œprefix”hŒsuffix”Œ)”Œstart”Kuh1j=  hj  h²hh³hÊh´K.ubhŒliteral_block”“”)”}”(hŒ×+------------+-----+---------------+----------------+-----------------+
| desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
+------------+-----+---------------+----------------+-----------------+”h]”hŒ×+------------+-----+---------------+----------------+-----------------+
| desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
+------------+-----+---------------+----------------+-----------------+”…””}”hjj  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jh  h³hÊh´K2hj  h²hubhÝ)”}”(hŒOThis structure is pointed by dma->sg_cpu.
The descriptors are used as follows :”h]”hŒOThis structure is pointed by dma->sg_cpu.
The descriptors are used as follows :”…””}”(hjz  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K6hj  h²hubhŒblock_quote”“”)”}”(hXê  - desc-sg[i]: i-th descriptor, transferring the i-th sg
  element to the video buffer scatter gather

- status updater
  Transfers a single u32 to a well known dma coherent memory to leave
  a trace that this transfer is done. The "well known" is unique per
  physical channel, meaning that a read of this value will tell which
  is the last finished transfer at that point in time.

- finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN

- linker: has ddadr= desc-sg[0] of next transfer, dcmd=0
”h]”hŒbullet_list”“”)”}”(hhh]”(jC  )”}”(hŒadesc-sg[i]: i-th descriptor, transferring the i-th sg
element to the video buffer scatter gather
”h]”hÝ)”}”(hŒ`desc-sg[i]: i-th descriptor, transferring the i-th sg
element to the video buffer scatter gather”h]”hŒ`desc-sg[i]: i-th descriptor, transferring the i-th sg
element to the video buffer scatter gather”…””}”(hj—  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K9hj“  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj  ubjC  )”}”(hX  status updater
Transfers a single u32 to a well known dma coherent memory to leave
a trace that this transfer is done. The "well known" is unique per
physical channel, meaning that a read of this value will tell which
is the last finished transfer at that point in time.
”h]”hÝ)”}”(hX  status updater
Transfers a single u32 to a well known dma coherent memory to leave
a trace that this transfer is done. The "well known" is unique per
physical channel, meaning that a read of this value will tell which
is the last finished transfer at that point in time.”h]”hX  status updater
Transfers a single u32 to a well known dma coherent memory to leave
a trace that this transfer is done. The â€œwell knownâ€ is unique per
physical channel, meaning that a read of this value will tell which
is the last finished transfer at that point in time.”…””}”(hj¯  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K<hj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj  ubjC  )”}”(hŒ.finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN
”h]”hÝ)”}”(hŒ-finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN”h]”hŒ-finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN”…””}”(hjÇ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KBhjÃ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj  ubjC  )”}”(hŒ7linker: has ddadr= desc-sg[0] of next transfer, dcmd=0
”h]”hÝ)”}”(hŒ6linker: has ddadr= desc-sg[0] of next transfer, dcmd=0”h]”hŒ6linker: has ddadr= desc-sg[0] of next transfer, dcmd=0”…””}”(hjß  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KDhjÛ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jŽ  h³hÊh´K9hjŠ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  h³hÊh´K9hj  h²hubhÝ)”}”(hŒ7c) Transfers hot-chaining
Suppose the running chain is:”h]”hŒ7c) Transfers hot-chaining
Suppose the running chain is:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KFhj  h²hubji  )”}”(hŒÏBuffer 1              Buffer 2
+---------+----+---+  +----+----+----+---+
| d0 | .. | dN | l |  | d0 | .. | dN | f |
+---------+----+-|-+  ^----+----+----+---+
                 |    |
                 +----+”h]”hŒÏBuffer 1              Buffer 2
+---------+----+---+  +----+----+----+---+
| d0 | .. | dN | l |  | d0 | .. | dN | f |
+---------+----+-|-+  ^----+----+----+---+
                 |    |
                 +----+”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”jx  jy  uh1jh  h³hÊh´KKhj  h²hubhÝ)”}”(hŒ?After a call to dmaengine_submit(b3), the chain will look like:”h]”hŒ?After a call to dmaengine_submit(b3), the chain will look like:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KRhj  h²hubji  )”}”(hX‚  Buffer 1              Buffer 2              Buffer 3
+---------+----+---+  +----+----+----+---+  +----+----+----+---+
| d0 | .. | dN | l |  | d0 | .. | dN | l |  | d0 | .. | dN | f |
+---------+----+-|-+  ^----+----+----+-|-+  ^----+----+----+---+
                 |    |                |    |
                 +----+                +----+
                                      new_link”h]”hX‚  Buffer 1              Buffer 2              Buffer 3
+---------+----+---+  +----+----+----+---+  +----+----+----+---+
| d0 | .. | dN | l |  | d0 | .. | dN | l |  | d0 | .. | dN | f |
+---------+----+-|-+  ^----+----+----+-|-+  ^----+----+----+---+
                 |    |                |    |
                 +----+                +----+
                                      new_link”…””}”hj+  sbah}”(h]”h ]”h"]”h$]”h&]”jx  jy  uh1jh  h³hÊh´KVhj  h²hubhÝ)”}”(hŒÐIf while new_link was created the DMA channel stopped, it is _not_
restarted. Hot-chaining doesn't break the assumption that
dma_async_issue_pending() is to be used to ensure the transfer is actually started.”h]”hŒÒIf while new_link was created the DMA channel stopped, it is _not_
restarted. Hot-chaining doesnâ€™t break the assumption that
dma_async_issue_pending() is to be used to ensure the transfer is actually started.”…””}”(hj9  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K^hj  h²hubhÝ)”}”(hŒOne exception to this rule :”h]”hŒOne exception to this rule :”…””}”(hjG  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kbhj  h²hubj  )”}”(hhh]”(jC  )”}”(hŒ?if Buffer1 and Buffer2 had all their addresses 8 bytes aligned
”h]”hÝ)”}”(hŒ>if Buffer1 and Buffer2 had all their addresses 8 bytes aligned”h]”hŒ>if Buffer1 and Buffer2 had all their addresses 8 bytes aligned”…””}”(hj\  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KdhjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjU  h²hh³hÊh´NubjC  )”}”(hŒ<and if Buffer3 has at least one address not 4 bytes aligned
”h]”hÝ)”}”(hŒ;and if Buffer3 has at least one address not 4 bytes aligned”h]”hŒ;and if Buffer3 has at least one address not 4 bytes aligned”…””}”(hjt  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kfhjp  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjU  h²hh³hÊh´NubjC  )”}”(hX  then hot-chaining cannot happen, as the channel must be stopped, the
"align bit" must be set, and the channel restarted As a consequence,
such a transfer tx_submit() will be queued on the submitted queue, and
this specific case if the DMA is already running in aligned mode.
”h]”hÝ)”}”(hX  then hot-chaining cannot happen, as the channel must be stopped, the
"align bit" must be set, and the channel restarted As a consequence,
such a transfer tx_submit() will be queued on the submitted queue, and
this specific case if the DMA is already running in aligned mode.”h]”hX  then hot-chaining cannot happen, as the channel must be stopped, the
â€œalign bitâ€ must be set, and the channel restarted As a consequence,
such a transfer tx_submit() will be queued on the submitted queue, and
this specific case if the DMA is already running in aligned mode.”…””}”(hjŒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khhjˆ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjU  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jù  jú  uh1jŽ  h³hÊh´Kdhj  h²hubhÝ)”}”(hX:  d) Transfers completion updater
Each time a transfer is completed on a channel, an interrupt might be
generated or not, up to the client's request. But in each case, the last
descriptor of a transfer, the "status updater", will write the latest
transfer being completed into the physical channel's completion mark.”h]”hXB  d) Transfers completion updater
Each time a transfer is completed on a channel, an interrupt might be
generated or not, up to the clientâ€™s request. But in each case, the last
descriptor of a transfer, the â€œstatus updaterâ€, will write the latest
transfer being completed into the physical channelâ€™s completion mark.”…””}”(hj¦  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kmhj  h²hubhÝ)”}”(hŒçThis will speed up residue calculation, for large transfers such as video
buffers which hold around 6k descriptors or more. This also allows without
any lock to find out what is the latest completed transfer in a running
DMA chain.”h]”hŒçThis will speed up residue calculation, for large transfers such as video
buffers which hold around 6k descriptors or more. This also allows without
any lock to find out what is the latest completed transfer in a running
DMA chain.”…””}”(hj´  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kshj  h²hubhÝ)”}”(hŒÂe) Transfers completion, irq and tasklet
When a transfer flagged as "DMA_PREP_INTERRUPT" is finished, the dma irq
is raised. Upon this interrupt, a tasklet is scheduled for the physical
channel.”h]”hŒÆe) Transfers completion, irq and tasklet
When a transfer flagged as â€œDMA_PREP_INTERRUPTâ€ is finished, the dma irq
is raised. Upon this interrupt, a tasklet is scheduled for the physical
channel.”…””}”(hjÂ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kxhj  h²hubhÝ)”}”(hŒ The tasklet is responsible for :”h]”hŒ The tasklet is responsible for :”…””}”(hjÐ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K}hj  h²hubj  )”}”(hhh]”(jC  )”}”(hŒ/reading the physical channel last updater mark
”h]”hÝ)”}”(hŒ.reading the physical channel last updater mark”h]”hŒ.reading the physical channel last updater mark”…””}”(hjå  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjá  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjÞ  h²hh³hÊh´NubjC  )”}”(hŒgcalling all the transfer callbacks of finished transfers, based on
that mark, and each transfer flags.
”h]”hÝ)”}”(hŒfcalling all the transfer callbacks of finished transfers, based on
that mark, and each transfer flags.”h]”hŒfcalling all the transfer callbacks of finished transfers, based on
that mark, and each transfer flags.”…””}”(hjý  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khjù  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjÞ  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jù  jú  uh1jŽ  h³hÊh´Khj  h²hubhÝ)”}”(hŒšIf a transfer is completed while this handling is done, a dma irq will
be raised, and the tasklet will be scheduled once again, having a new
updater mark.”h]”hŒšIf a transfer is completed while this handling is done, a dma irq will
be raised, and the tasklet will be scheduled once again, having a new
updater mark.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K„hj  h²hubhÝ)”}”(hŒ¶f) Residue
Residue granularity will be descriptor based. The issued but not completed
transfers will be scanned for all of their descriptors against the
currently running descriptor.”h]”hŒ¶f) Residue
Residue granularity will be descriptor based. The issued but not completed
transfers will be scanned for all of their descriptors against the
currently running descriptor.”…””}”(hj%  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Kˆhj  h²hubhÝ)”}”(hŒRg) Most complicated case of driver's tx queues
The most tricky situation is when :”h]”hŒTg) Most complicated case of driverâ€™s tx queues
The most tricky situation is when :”…””}”(hj3  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´Khj  h²hubj‰  )”}”(hXº  - there are not "acked" transfers (tx0)

- a driver submitted an aligned tx1, not chained

- a driver submitted an aligned tx2 => tx2 is cold chained to tx1

- a driver issued tx1+tx2 => channel is running in aligned mode

- a driver submitted an aligned tx3 => tx3 is hot-chained

- a driver submitted an unaligned tx4 => tx4 is put in submitted queue,
  not chained

- a driver issued tx4 => tx4 is put in issued queue, not chained

- a driver submitted an aligned tx5 => tx5 is put in submitted queue, not
  chained

- a driver submitted an aligned tx6 => tx6 is put in submitted queue,
  cold chained to tx5

This translates into (after tx4 is issued) :

- issued queue

::

     +-----+ +-----+ +-----+ +-----+
     | tx1 | | tx2 | | tx3 | | tx4 |
     +---|-+ ^---|-+ ^-----+ +-----+
         |   |   |   |
         +---+   +---+
       - submitted queue
     +-----+ +-----+
     | tx5 | | tx6 |
     +---|-+ ^-----+
         |   |
         +---+
”h]”(j  )”}”(hhh]”(jC  )”}”(hŒ&there are not "acked" transfers (tx0)
”h]”hÝ)”}”(hŒ%there are not "acked" transfers (tx0)”h]”hŒ)there are not â€œackedâ€ transfers (tx0)”…””}”(hjL  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhjH  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒ/a driver submitted an aligned tx1, not chained
”h]”hÝ)”}”(hŒ.a driver submitted an aligned tx1, not chained”h]”hŒ.a driver submitted an aligned tx1, not chained”…””}”(hjd  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K’hj`  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒ@a driver submitted an aligned tx2 => tx2 is cold chained to tx1
”h]”hÝ)”}”(hŒ?a driver submitted an aligned tx2 => tx2 is cold chained to tx1”h]”hŒ?a driver submitted an aligned tx2 => tx2 is cold chained to tx1”…””}”(hj|  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K”hjx  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒ>a driver issued tx1+tx2 => channel is running in aligned mode
”h]”hÝ)”}”(hŒ=a driver issued tx1+tx2 => channel is running in aligned mode”h]”hŒ=a driver issued tx1+tx2 => channel is running in aligned mode”…””}”(hj”  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K–hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒ8a driver submitted an aligned tx3 => tx3 is hot-chained
”h]”hÝ)”}”(hŒ7a driver submitted an aligned tx3 => tx3 is hot-chained”h]”hŒ7a driver submitted an aligned tx3 => tx3 is hot-chained”…””}”(hj¬  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K˜hj¨  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒRa driver submitted an unaligned tx4 => tx4 is put in submitted queue,
not chained
”h]”hÝ)”}”(hŒQa driver submitted an unaligned tx4 => tx4 is put in submitted queue,
not chained”h]”hŒQa driver submitted an unaligned tx4 => tx4 is put in submitted queue,
not chained”…””}”(hjÄ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KšhjÀ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒ?a driver issued tx4 => tx4 is put in issued queue, not chained
”h]”hÝ)”}”(hŒ>a driver issued tx4 => tx4 is put in issued queue, not chained”h]”hŒ>a driver issued tx4 => tx4 is put in issued queue, not chained”…””}”(hjÜ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KhjØ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒPa driver submitted an aligned tx5 => tx5 is put in submitted queue, not
chained
”h]”hÝ)”}”(hŒOa driver submitted an aligned tx5 => tx5 is put in submitted queue, not
chained”h]”hŒOa driver submitted an aligned tx5 => tx5 is put in submitted queue, not
chained”…””}”(hjô  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´KŸhjð  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubjC  )”}”(hŒXa driver submitted an aligned tx6 => tx6 is put in submitted queue,
cold chained to tx5
”h]”hÝ)”}”(hŒWa driver submitted an aligned tx6 => tx6 is put in submitted queue,
cold chained to tx5”h]”hŒWa driver submitted an aligned tx6 => tx6 is put in submitted queue,
cold chained to tx5”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K¢hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hjE  ubeh}”(h]”h ]”h"]”h$]”h&]”jù  jú  uh1jŽ  h³hÊh´KhjA  ubhÝ)”}”(hŒ,This translates into (after tx4 is issued) :”h]”hŒ,This translates into (after tx4 is issued) :”…””}”(hj&  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K¥hjA  ubj  )”}”(hhh]”jC  )”}”(hŒissued queue
”h]”hÝ)”}”(hŒissued queue”h]”hŒissued queue”…””}”(hj;  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K§hj7  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hj4  ubah}”(h]”h ]”h"]”h$]”h&]”jù  jú  uh1jŽ  h³hÊh´K§hjA  ubji  )”}”(hŒÛ+-----+ +-----+ +-----+ +-----+
| tx1 | | tx2 | | tx3 | | tx4 |
+---|-+ ^---|-+ ^-----+ +-----+
    |   |   |   |
    +---+   +---+
  - submitted queue
+-----+ +-----+
| tx5 | | tx6 |
+---|-+ ^-----+
    |   |
    +---+”h]”hŒÛ+-----+ +-----+ +-----+ +-----+
| tx1 | | tx2 | | tx3 | | tx4 |
+---|-+ ^---|-+ ^-----+ +-----+
    |   |   |   |
    +---+   +---+
  - submitted queue
+-----+ +-----+
| tx5 | | tx6 |
+---|-+ ^-----+
    |   |
    +---+”…””}”hjU  sbah}”(h]”h ]”h"]”h$]”h&]”jx  jy  uh1jh  h³hÊh´K«hjA  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jˆ  h³hÊh´Khj  h²hubj  )”}”(hhh]”(jC  )”}”(hŒcompleted queue : empty
”h]”hÝ)”}”(hŒcompleted queue : empty”h]”hŒcompleted queue : empty”…””}”(hjp  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K·hjl  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hji  h²hh³hÊh´NubjC  )”}”(hŒallocated queue : tx0
”h]”hÝ)”}”(hŒallocated queue : tx0”h]”hŒallocated queue : tx0”…””}”(hjˆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K¹hj„  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jB  hji  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jù  jú  uh1jŽ  h³hÊh´K·hj  h²hubhÝ)”}”(hŒxIt should be noted that after tx3 is completed, the channel is stopped, and
restarted in "unaligned mode" to handle tx4.”h]”hŒ|It should be noted that after tx3 is completed, the channel is stopped, and
restarted in â€œunaligned modeâ€ to handle tx4.”…””}”(hj¢  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K»hj  h²hubhÝ)”}”(hŒ/Author: Robert Jarzmik <robert.jarzmik@free.fr>”h]”(hŒAuthor: Robert Jarzmik <”…””}”(hj°  h²hh³Nh´NubhŒ	reference”“”)”}”(hŒrobert.jarzmik@free.fr”h]”hŒrobert.jarzmik@free.fr”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:robert.jarzmik@free.fr”uh1j¸  hj°  ubhŒ>”…””}”(hj°  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÜh³hÊh´K¾hj  h²hubeh}”(h]”Œdesign”ah ]”h"]”Œdesign”ah$]”h&]”uh1hµhh·h²hh³hÊh´K(ubeh}”(h]”Œpxa-mmp-dma-slave-controller”ah ]”h"]”Œpxa/mmp - dma slave controller”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(já  jÞ  j  j  jÙ  jÖ  uŒ	nametypes”}”(já  ‰j  ‰jÙ  ‰uh}”(jÞ  h·j  hËjÖ  j  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”hŒsystem_message”“”)”}”(hhh]”hÝ)”}”(hŒ:Enumerated list start value not ordinal-1: "b" (ordinal 2)”h]”hŒ>Enumerated list start value not ordinal-1: â€œbâ€ (ordinal 2)”…””}”(hjn  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÜhjk  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œsource”hÊŒline”Kuh1ji  hj  h²hh³hÊh´K.ubaŒtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.