Qsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget1/translations/zh_CN/driver-api/dmaengine/providermodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/zh_TW/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/it_IT/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ja_JP/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ko_KR/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/pt_BR/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/sp_SP/driver-api/dmaengine/providermodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h"DMAengine controller documentationh]h"DMAengine controller documentation}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhK/var/lib/git/docbuild/linux/Documentation/driver-api/dmaengine/provider.rsthKubh)}(hhh](h)}(hHardware Introductionh]hHardware Introduction}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hQMost of the Slave DMA controllers have the same general principles of operations.h]hQMost of the Slave DMA controllers have the same general principles of operations.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhThey have a given number of channels to use for the DMA transfers, and a given number of requests lines.h]hhThey have a given number of channels to use for the DMA transfers, and a given number of requests lines.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hRequests and channels are pretty much orthogonal. Channels can be used to serve several to any requests. To simplify, channels are the entities that will be doing the copy, and requests what endpoints are involved.h]hRequests and channels are pretty much orthogonal. Channels can be used to serve several to any requests. To simplify, channels are the entities that will be doing the copy, and requests what endpoints are involved.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe request lines actually correspond to physical lines going from the DMA-eligible devices to the controller itself. Whenever the device will want to start a transfer, it will assert a DMA request (DRQ) by asserting that request line.h]hThe request lines actually correspond to physical lines going from the DMA-eligible devices to the controller itself. Whenever the device will want to start a transfer, it will assert a DMA request (DRQ) by asserting that request line.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hA very simple DMA controller would only take into account a single parameter: the transfer size. At each clock cycle, it would transfer a byte of data from one buffer to another, until the transfer size has been reached.h]hA very simple DMA controller would only take into account a single parameter: the transfer size. At each clock cycle, it would transfer a byte of data from one buffer to another, until the transfer size has been reached.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXThat wouldn't work well in the real world, since slave devices might require a specific number of bits to be transferred in a single cycle. For example, we may want to transfer as much data as the physical bus allows to maximize performances when doing a simple memory copy operation, but our audio device could have a narrower FIFO that requires data to be written exactly 16 or 24 bits at a time. This is why most if not all of the DMA controllers can adjust this, using a parameter called the transfer width.h]hXThat wouldn’t work well in the real world, since slave devices might require a specific number of bits to be transferred in a single cycle. For example, we may want to transfer as much data as the physical bus allows to maximize performances when doing a simple memory copy operation, but our audio device could have a narrower FIFO that requires data to be written exactly 16 or 24 bits at a time. This is why most if not all of the DMA controllers can adjust this, using a parameter called the transfer width.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXMoreover, some DMA controllers, whenever the RAM is used as a source or destination, can group the reads or writes in memory into a buffer, so instead of having a lot of small memory accesses, which is not really efficient, you'll get several bigger transfers. This is done using a parameter called the burst size, that defines how many single reads/writes it's allowed to do without the controller splitting the transfer into smaller sub-transfers.h]hXMoreover, some DMA controllers, whenever the RAM is used as a source or destination, can group the reads or writes in memory into a buffer, so instead of having a lot of small memory accesses, which is not really efficient, you’ll get several bigger transfers. This is done using a parameter called the burst size, that defines how many single reads/writes it’s allowed to do without the controller splitting the transfer into smaller sub-transfers.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hhhhubh)}(hXOur theoretical DMA controller would then only be able to do transfers that involve a single contiguous block of data. However, some of the transfers we usually have are not, and want to copy data from non-contiguous buffers to a contiguous buffer, which is called scatter-gather.h]hXOur theoretical DMA controller would then only be able to do transfers that involve a single contiguous block of data. However, some of the transfers we usually have are not, and want to copy data from non-contiguous buffers to a contiguous buffer, which is called scatter-gather.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hhhhubh)}(hX:DMAEngine, at least for mem2dev transfers, require support for scatter-gather. So we're left with two cases here: either we have a quite simple DMA controller that doesn't support it, and we'll have to implement it in software, or we have a more advanced DMA controller, that implements in hardware scatter-gather.h]hX@DMAEngine, at least for mem2dev transfers, require support for scatter-gather. So we’re left with two cases here: either we have a quite simple DMA controller that doesn’t support it, and we’ll have to implement it in software, or we have a more advanced DMA controller, that implements in hardware scatter-gather.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hhhhubh)}(hThe latter are usually programmed using a collection of chunks to transfer, and whenever the transfer is started, the controller will go over that collection, doing whatever we programmed there.h]hThe latter are usually programmed using a collection of chunks to transfer, and whenever the transfer is started, the controller will go over that collection, doing whatever we programmed there.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hhhhubh)}(hX;This collection is usually either a table or a linked list. You will then push either the address of the table and its number of elements, or the first item of the list to one channel of the DMA controller, and whenever a DRQ will be asserted, it will go through the collection to know where to fetch the data from.h]hX;This collection is usually either a table or a linked list. You will then push either the address of the table and its number of elements, or the first item of the list to one channel of the DMA controller, and whenever a DRQ will be asserted, it will go through the collection to know where to fetch the data from.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hhhhubh)}(hXEither way, the format of this collection is completely dependent on your hardware. Each DMA controller will require a different structure, but all of them will require, for every chunk, at least the source and destination addresses, whether it should increment these addresses or not and the three parameters we saw earlier: the burst size, the transfer width and the transfer size.h]hXEither way, the format of this collection is completely dependent on your hardware. Each DMA controller will require a different structure, but all of them will require, for every chunk, at least the source and destination addresses, whether it should increment these addresses or not and the three parameters we saw earlier: the burst size, the transfer width and the transfer size.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhhhhubh)}(hThe one last thing is that usually, slave devices won't issue DRQ by default, and you have to enable this in your slave device driver first whenever you're willing to use DMA.h]hThe one last thing is that usually, slave devices won’t issue DRQ by default, and you have to enable this in your slave device driver first whenever you’re willing to use DMA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhhhhubh)}(hThese were just the general memory-to-memory (also called mem2mem) or memory-to-device (mem2dev) kind of transfers. Most devices often support other kind of transfers or memory operations that dmaengine support and will be detailed later in this document.h]hThese were just the general memory-to-memory (also called mem2mem) or memory-to-device (mem2dev) kind of transfers. Most devices often support other kind of transfers or memory operations that dmaengine support and will be detailed later in this document.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhhhhubeh}(h]hardware-introductionah ]h"]hardware introductionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDMA Support in Linuxh]hDMA Support in Linux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKUubh)}(hHistorically, DMA controller drivers have been implemented using the async TX API, to offload operations such as memory copy, XOR, cryptography, etc., basically any memory to memory operation.h]hHistorically, DMA controller drivers have been implemented using the async TX API, to offload operations such as memory copy, XOR, cryptography, etc., basically any memory to memory operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjhhubh)}(hX)Over time, the need for memory to device transfers arose, and dmaengine was extended. Nowadays, the async TX API is written as a layer on top of dmaengine, and acts as a client. Still, dmaengine accommodates that API in some cases, and made some design choices to ensure that it stayed compatible.h]hX)Over time, the need for memory to device transfers arose, and dmaengine was extended. Nowadays, the async TX API is written as a layer on top of dmaengine, and acts as a client. Still, dmaengine accommodates that API in some cases, and made some design choices to ensure that it stayed compatible.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjhhubh)}(hFor more information on the Async TX API, please look the relevant documentation file in Documentation/crypto/async-tx-api.rst.h]hFor more information on the Async TX API, please look the relevant documentation file in Documentation/crypto/async-tx-api.rst.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjhhubeh}(h]dma-support-in-linuxah ]h"]dma support in linuxah$]h&]uh1hhhhhhhhKUubh)}(hhh](h)}(hDMAEngine APIsh]hDMAEngine APIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKeubh)}(hhh](h)}(h$``struct dma_device`` Initializationh](hliteral)}(h``struct dma_device``h]hstruct dma_device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh Initialization}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhhhhhKhubh)}(hJust like any other kernel framework, the whole DMAEngine registration relies on the driver filling a structure and registering against the framework. In our case, that structure is dma_device.h]hJust like any other kernel framework, the whole DMAEngine registration relies on the driver filling a structure and registering against the framework. In our case, that structure is dma_device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjhhubh)}(hThe first thing you need to do in your driver is to allocate this structure. Any of the usual memory allocators will do, but you'll also need to initialize a few fields in there:h]hThe first thing you need to do in your driver is to allocate this structure. Any of the usual memory allocators will do, but you’ll also need to initialize a few fields in there:}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubh bullet_list)}(hhh](h list_item)}(hY``channels``: should be initialized as a list using the INIT_LIST_HEAD macro for example h]h)}(hX``channels``: should be initialized as a list using the INIT_LIST_HEAD macro for exampleh](j)}(h ``channels``h]hchannels}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubhL: should be initialized as a list using the INIT_LIST_HEAD macro for example}(hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKrhjBubah}(h]h ]h"]h$]h&]uh1j@hj=hhhhhNubjA)}(hU``src_addr_widths``: should contain a bitmask of the supported source transfer width h]h)}(hT``src_addr_widths``: should contain a bitmask of the supported source transfer widthh](j)}(h``src_addr_widths``h]hsrc_addr_widths}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubhA: should contain a bitmask of the supported source transfer width}(hjlhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKuhjhubah}(h]h ]h"]h$]h&]uh1j@hj=hhhhhNubjA)}(hZ``dst_addr_widths``: should contain a bitmask of the supported destination transfer width h]h)}(hY``dst_addr_widths``: should contain a bitmask of the supported destination transfer widthh](j)}(h``dst_addr_widths``h]hdst_addr_widths}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhF: should contain a bitmask of the supported destination transfer width}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1j@hj=hhhhhNubjA)}(hn``directions``: should contain a bitmask of the supported slave directions (i.e. excluding mem2mem transfers) h]h)}(hm``directions``: should contain a bitmask of the supported slave directions (i.e. excluding mem2mem transfers)h](j)}(h``directions``h]h directions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh_: should contain a bitmask of the supported slave directions (i.e. excluding mem2mem transfers)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1j@hj=hhhhhNubjA)}(hX``residue_granularity``: granularity of the transfer residue reported to dma_set_residue. This can be either: - Descriptor: your device doesn't support any kind of residue reporting. The framework will only know that a particular transaction descriptor is done. - Segment: your device is able to report which chunks have been transferred - Burst: your device is able to report which burst have been transferred h](h)}(hm``residue_granularity``: granularity of the transfer residue reported to dma_set_residue. This can be either:h](j)}(h``residue_granularity``h]hresidue_granularity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhV: granularity of the transfer residue reported to dma_set_residue. This can be either:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubj<)}(hhh](jA)}(hDescriptor: your device doesn't support any kind of residue reporting. The framework will only know that a particular transaction descriptor is done. h]h)}(hDescriptor: your device doesn't support any kind of residue reporting. The framework will only know that a particular transaction descriptor is done.h]hDescriptor: your device doesn’t support any kind of residue reporting. The framework will only know that a particular transaction descriptor is done.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hJSegment: your device is able to report which chunks have been transferred h]h)}(hISegment: your device is able to report which chunks have been transferredh]hISegment: your device is able to report which chunks have been transferred}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hGBurst: your device is able to report which burst have been transferred h]h)}(hFBurst: your device is able to report which burst have been transferredh]hFBurst: your device is able to report which burst have been transferred}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-ubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]bullet-uh1j;hhhKhjubeh}(h]h ]h"]h$]h&]uh1j@hj=hhhNhNubjA)}(hf``dev``: should hold the pointer to the ``struct device`` associated to your current driver instance. h]h)}(he``dev``: should hold the pointer to the ``struct device`` associated to your current driver instance.h](j)}(h``dev``h]hdev}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh!: should hold the pointer to the }(hjWhhhNhNubj)}(h``struct device``h]h struct device}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh, associated to your current driver instance.}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjSubah}(h]h ]h"]h$]h&]uh1j@hj=hhhhhNubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhKrhjhhubeh}(h] struct-dma-device-initializationah ]h"] struct dma_device initializationah$]h&]uh1hhjhhhhhKhubh)}(hhh](h)}(hSupported transaction typesh]hSupported transaction types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h\The next thing you need is to set which transaction types your device (and driver) supports.h]h\The next thing you need is to set which transaction types your device (and driver) supports.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hOur ``dma_device structure`` has a field called cap_mask that holds the various types of transaction supported, and you need to modify this mask using the dma_cap_set function, with various flags depending on transaction types you support as an argument.h](hOur }(hjhhhNhNubj)}(h``dma_device structure``h]hdma_device structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh has a field called cap_mask that holds the various types of transaction supported, and you need to modify this mask using the dma_cap_set function, with various flags depending on transaction types you support as an argument.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hiAll those capabilities are defined in the ``dma_transaction_type enum``, in ``include/linux/dmaengine.h``h](h*All those capabilities are defined in the }(hjhhhNhNubj)}(h``dma_transaction_type enum``h]hdma_transaction_type enum}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, in }(hjhhhNhNubj)}(h``include/linux/dmaengine.h``h]hinclude/linux/dmaengine.h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h#Currently, the types available are:h]h#Currently, the types available are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj<)}(hhh](jA)}(hX;DMA_MEMCPY - The device is able to do memory to memory copies - No matter what the overall size of the combined chunks for source and destination is, only as many bytes as the smallest of the two will be transmitted. That means the number and size of the scatter-gather buffers in both lists need not be the same, and that the operation functionally is equivalent to a ``strncpy`` where the ``count`` argument equals the smallest total size of the two scatter-gather list buffers. - It's usually used for copying pixel data between host memory and memory-mapped GPU device memory, such as found on modern PCI video graphics cards. The most immediate example is the OpenGL API function ``glReadPixels()``, which might require a verbatim copy of a huge framebuffer from local device memory onto host memory. h](h)}(h DMA_MEMCPYh]h DMA_MEMCPY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj<)}(hhh](jA)}(h1The device is able to do memory to memory copies h]h)}(h0The device is able to do memory to memory copiesh]h0The device is able to do memory to memory copies}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj,ubah}(h]h ]h"]h$]h&]uh1j@hj)ubjA)}(hXNo matter what the overall size of the combined chunks for source and destination is, only as many bytes as the smallest of the two will be transmitted. That means the number and size of the scatter-gather buffers in both lists need not be the same, and that the operation functionally is equivalent to a ``strncpy`` where the ``count`` argument equals the smallest total size of the two scatter-gather list buffers. h]h)}(hXNo matter what the overall size of the combined chunks for source and destination is, only as many bytes as the smallest of the two will be transmitted. That means the number and size of the scatter-gather buffers in both lists need not be the same, and that the operation functionally is equivalent to a ``strncpy`` where the ``count`` argument equals the smallest total size of the two scatter-gather list buffers.h](hX1No matter what the overall size of the combined chunks for source and destination is, only as many bytes as the smallest of the two will be transmitted. That means the number and size of the scatter-gather buffers in both lists need not be the same, and that the operation functionally is equivalent to a }(hjHhhhNhNubj)}(h ``strncpy``h]hstrncpy}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh where the }(hjHhhhNhNubj)}(h ``count``h]hcount}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubhP argument equals the smallest total size of the two scatter-gather list buffers.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDubah}(h]h ]h"]h$]h&]uh1j@hj)ubjA)}(hXCIt's usually used for copying pixel data between host memory and memory-mapped GPU device memory, such as found on modern PCI video graphics cards. The most immediate example is the OpenGL API function ``glReadPixels()``, which might require a verbatim copy of a huge framebuffer from local device memory onto host memory. h]h)}(hXBIt's usually used for copying pixel data between host memory and memory-mapped GPU device memory, such as found on modern PCI video graphics cards. The most immediate example is the OpenGL API function ``glReadPixels()``, which might require a verbatim copy of a huge framebuffer from local device memory onto host memory.h](hIt’s usually used for copying pixel data between host memory and memory-mapped GPU device memory, such as found on modern PCI video graphics cards. The most immediate example is the OpenGL API function }(hjhhhNhNubj)}(h``glReadPixels()``h]hglReadPixels()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhf, which might require a verbatim copy of a huge framebuffer from local device memory onto host memory.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hj)ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhKhjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hDMA_XOR - The device is able to perform XOR operations on memory areas - Used to accelerate XOR intensive tasks, such as RAID5 h](h)}(hDMA_XORh]hDMA_XOR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj<)}(hhh](jA)}(h=The device is able to perform XOR operations on memory areas h]h)}(hDMA_CYCLIC - The device can handle cyclic transfers. - A cyclic transfer is a transfer where the chunk collection will loop over itself, with the last item pointing to the first. - It's usually used for audio transfers, where you want to operate on a single ring buffer that you will fill with your audio data. h](h)}(h DMA_CYCLICh]h DMA_CYCLIC}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjGubj<)}(hhh](jA)}(h(The device can handle cyclic transfers. h]h)}(h'The device can handle cyclic transfers.h]h'The device can handle cyclic transfers.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\ubah}(h]h ]h"]h$]h&]uh1j@hjYubjA)}(h|A cyclic transfer is a transfer where the chunk collection will loop over itself, with the last item pointing to the first. h]h)}(h{A cyclic transfer is a transfer where the chunk collection will loop over itself, with the last item pointing to the first.h]h{A cyclic transfer is a transfer where the chunk collection will loop over itself, with the last item pointing to the first.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjtubah}(h]h ]h"]h$]h&]uh1j@hjYubjA)}(hIt's usually used for audio transfers, where you want to operate on a single ring buffer that you will fill with your audio data. h]h)}(hIt's usually used for audio transfers, where you want to operate on a single ring buffer that you will fill with your audio data.h]hIt’s usually used for audio transfers, where you want to operate on a single ring buffer that you will fill with your audio data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hjYubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhKhjGubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hXDMA_INTERLEAVE - The device supports interleaved transfer. - These transfers can transfer data from a non-contiguous buffer to a non-contiguous buffer, opposed to DMA_SLAVE that can transfer data from a non-contiguous data set to a continuous destination buffer. - It's usually used for 2d content transfers, in which case you want to transfer a portion of uncompressed data directly to the display to print it h](h)}(hDMA_INTERLEAVEh]hDMA_INTERLEAVE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj<)}(hhh](jA)}(h*The device supports interleaved transfer. h]h)}(h)The device supports interleaved transfer.h]h)The device supports interleaved transfer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hThese transfers can transfer data from a non-contiguous buffer to a non-contiguous buffer, opposed to DMA_SLAVE that can transfer data from a non-contiguous data set to a continuous destination buffer. h]h)}(hThese transfers can transfer data from a non-contiguous buffer to a non-contiguous buffer, opposed to DMA_SLAVE that can transfer data from a non-contiguous data set to a continuous destination buffer.h]hThese transfers can transfer data from a non-contiguous buffer to a non-contiguous buffer, opposed to DMA_SLAVE that can transfer data from a non-contiguous data set to a continuous destination buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hIt's usually used for 2d content transfers, in which case you want to transfer a portion of uncompressed data directly to the display to print it h]h)}(hIt's usually used for 2d content transfers, in which case you want to transfer a portion of uncompressed data directly to the display to print ith]hIt’s usually used for 2d content transfers, in which case you want to transfer a portion of uncompressed data directly to the display to print it}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhKhjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hXDMA_COMPLETION_NO_ORDER - The device does not support in order completion. - The driver should return DMA_OUT_OF_ORDER for device_tx_status if the device is setting this capability. - All cookie tracking and checking API should be treated as invalid if the device exports this capability. - At this point, this is incompatible with polling option for dmatest. - If this cap is set, the user is recommended to provide an unique identifier for each descriptor sent to the DMA device in order to properly track the completion. h](h)}(hDMA_COMPLETION_NO_ORDERh]hDMA_COMPLETION_NO_ORDER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj<)}(hhh](jA)}(h1The device does not support in order completion. h]h)}(h0The device does not support in order completion.h]h0The device does not support in order completion.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj.ubah}(h]h ]h"]h$]h&]uh1j@hj+ubjA)}(hiThe driver should return DMA_OUT_OF_ORDER for device_tx_status if the device is setting this capability. h]h)}(hhThe driver should return DMA_OUT_OF_ORDER for device_tx_status if the device is setting this capability.h]hhThe driver should return DMA_OUT_OF_ORDER for device_tx_status if the device is setting this capability.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjFubah}(h]h ]h"]h$]h&]uh1j@hj+ubjA)}(hiAll cookie tracking and checking API should be treated as invalid if the device exports this capability. h]h)}(hhAll cookie tracking and checking API should be treated as invalid if the device exports this capability.h]hhAll cookie tracking and checking API should be treated as invalid if the device exports this capability.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1j@hj+ubjA)}(hEAt this point, this is incompatible with polling option for dmatest. h]h)}(hDAt this point, this is incompatible with polling option for dmatest.h]hDAt this point, this is incompatible with polling option for dmatest.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjvubah}(h]h ]h"]h$]h&]uh1j@hj+ubjA)}(hIf this cap is set, the user is recommended to provide an unique identifier for each descriptor sent to the DMA device in order to properly track the completion. h]h)}(hIf this cap is set, the user is recommended to provide an unique identifier for each descriptor sent to the DMA device in order to properly track the completion.h]hIf this cap is set, the user is recommended to provide an unique identifier for each descriptor sent to the DMA device in order to properly track the completion.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hj+ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhM hjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hX'DMA_REPEAT - The device supports repeated transfers. A repeated transfer, indicated by the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that it gets automatically repeated when it ends, but can additionally be replaced by the client. - This feature is limited to interleaved transfers, this flag should thus not be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on the current needs of DMA clients, support for additional transfer types should be added in the future if and when the need arises. h](h)}(h DMA_REPEATh]h DMA_REPEAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj<)}(hhh](jA)}(hThe device supports repeated transfers. A repeated transfer, indicated by the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that it gets automatically repeated when it ends, but can additionally be replaced by the client. h]h)}(hThe device supports repeated transfers. A repeated transfer, indicated by the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that it gets automatically repeated when it ends, but can additionally be replaced by the client.h]hThe device supports repeated transfers. A repeated transfer, indicated by the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that it gets automatically repeated when it ends, but can additionally be replaced by the client.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hXThis feature is limited to interleaved transfers, this flag should thus not be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on the current needs of DMA clients, support for additional transfer types should be added in the future if and when the need arises. h]h)}(hXThis feature is limited to interleaved transfers, this flag should thus not be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on the current needs of DMA clients, support for additional transfer types should be added in the future if and when the need arises.h]hXThis feature is limited to interleaved transfers, this flag should thus not be set if the DMA_INTERLEAVE flag isn’t set. This limitation is based on the current needs of DMA clients, support for additional transfer types should be added in the future if and when the need arises.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMhjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hXmDMA_LOAD_EOT - The device supports replacing repeated transfers at end of transfer (EOT) by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set. - Support for replacing a currently running transfer at another point (such as end of burst instead of end of transfer) will be added in the future based on DMA clients needs, if and when the need arises. h](h)}(h DMA_LOAD_EOTh]h DMA_LOAD_EOT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj ubj<)}(hhh](jA)}(hThe device supports replacing repeated transfers at end of transfer (EOT) by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set. h]h)}(hThe device supports replacing repeated transfers at end of transfer (EOT) by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.h]hThe device supports replacing repeated transfers at end of transfer (EOT) by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hj ubah}(h]h ]h"]h$]h&]uh1j@hj ubjA)}(hSupport for replacing a currently running transfer at another point (such as end of burst instead of end of transfer) will be added in the future based on DMA clients needs, if and when the need arises. h]h)}(hSupport for replacing a currently running transfer at another point (such as end of burst instead of end of transfer) will be added in the future based on DMA clients needs, if and when the need arises.h]hSupport for replacing a currently running transfer at another point (such as end of burst instead of end of transfer) will be added in the future based on DMA clients needs, if and when the need arises.}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj0 ubah}(h]h ]h"]h$]h&]uh1j@hj ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhM%hj ubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhKhjhhubh)}(h_These various types will also affect how the source and destination addresses change over time.h]h_These various types will also affect how the source and destination addresses change over time.}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjhhubh)}(hAddresses pointing to RAM are typically incremented (or decremented) after each transfer. In case of a ring buffer, they may loop (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO) are typically fixed.h]hAddresses pointing to RAM are typically incremented (or decremented) after each transfer. In case of a ring buffer, they may loop (DMA_CYCLIC). Addresses pointing to a device’s register (e.g. a FIFO) are typically fixed.}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjhhubeh}(h]supported-transaction-typesah ]h"]supported transaction typesah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(hPer descriptor metadata supporth]hPer descriptor metadata support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~ hhhhhM5ubh)}(hXLSome data movement architecture (DMA controller and peripherals) uses metadata associated with a transaction. The DMA controller role is to transfer the payload and the metadata alongside. The metadata itself is not used by the DMA engine itself, but it contains parameters, keys, vectors, etc for peripheral or from the peripheral.h]hXLSome data movement architecture (DMA controller and peripherals) uses metadata associated with a transaction. The DMA controller role is to transfer the payload and the metadata alongside. The metadata itself is not used by the DMA engine itself, but it contains parameters, keys, vectors, etc for peripheral or from the peripheral.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj~ hhubh)}(hThe DMAengine framework provides a generic ways to facilitate the metadata for descriptors. Depending on the architecture the DMA driver can implement either or both of the methods and it is up to the client driver to choose which one to use.h]hThe DMAengine framework provides a generic ways to facilitate the metadata for descriptors. Depending on the architecture the DMA driver can implement either or both of the methods and it is up to the client driver to choose which one to use.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj~ hhubj<)}(hhh](jA)}(hXDESC_METADATA_CLIENT The metadata buffer is allocated/provided by the client driver and it is attached (via the dmaengine_desc_attach_metadata() helper to the descriptor. From the DMA driver the following is expected for this mode: - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM The data from the provided metadata buffer should be prepared for the DMA controller to be sent alongside of the payload data. Either by copying to a hardware descriptor, or highly coupled packet. - DMA_DEV_TO_MEM On transfer completion the DMA driver must copy the metadata to the client provided metadata buffer before notifying the client about the completion. After the transfer completion, DMA drivers must not touch the metadata buffer provided by the client. h](h)}(hDESC_METADATA_CLIENTh]hDESC_METADATA_CLIENT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj ubh)}(hThe metadata buffer is allocated/provided by the client driver and it is attached (via the dmaengine_desc_attach_metadata() helper to the descriptor.h]hThe metadata buffer is allocated/provided by the client driver and it is attached (via the dmaengine_desc_attach_metadata() helper to the descriptor.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj ubh)}(hubah}(h]h ]h"]h$]h&]uh1j@hj;ubjA)}(hqThis command should NOT perform synchronously, or on any currently queued transfers, but only on subsequent ones h]h)}(hpThis command should NOT perform synchronously, or on any currently queued transfers, but only on subsequent onesh]hpThis command should NOT perform synchronously, or on any currently queued transfers, but only on subsequent ones}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1j@hj;ubjA)}(hIn this case, the function will receive a ``dma_slave_config`` structure pointer as an argument, that will detail which configuration to use. h]h)}(hIn this case, the function will receive a ``dma_slave_config`` structure pointer as an argument, that will detail which configuration to use.h](h*In this case, the function will receive a }(hjrhhhNhNubj)}(h``dma_slave_config``h]hdma_slave_config}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubhO structure pointer as an argument, that will detail which configuration to use.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1j@hj;ubjA)}(hEven though that structure contains a direction field, this field is deprecated in favor of the direction argument given to the prep_* functions h]h)}(hEven though that structure contains a direction field, this field is deprecated in favor of the direction argument given to the prep_* functionsh]hEven though that structure contains a direction field, this field is deprecated in favor of the direction argument given to the prep_* functions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hj;ubjA)}(hThis call is mandatory for slave operations only. This should NOT be set or expected to be set for memcpy operations. If a driver support both, it should use this call for slave operations only and not for memcpy ones. h]h)}(hThis call is mandatory for slave operations only. This should NOT be set or expected to be set for memcpy operations. If a driver support both, it should use this call for slave operations only and not for memcpy ones.h]hThis call is mandatory for slave operations only. This should NOT be set or expected to be set for memcpy operations. If a driver support both, it should use this call for slave operations only and not for memcpy ones.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hj;ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMhj)ubeh}(h]h ]h"]h$]h&]uh1j@hj hhhNhNubjA)}(hdevice_pause - Pauses a transfer on the channel - This command should operate synchronously on the channel, pausing right away the work of the given channel h](h)}(h device_pauseh]h device_pause}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj<)}(hhh](jA)}(h!Pauses a transfer on the channel h]h)}(h Pauses a transfer on the channelh]h Pauses a transfer on the channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hkThis command should operate synchronously on the channel, pausing right away the work of the given channel h]h)}(hjThis command should operate synchronously on the channel, pausing right away the work of the given channelh]hjThis command should operate synchronously on the channel, pausing right away the work of the given channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMhjubeh}(h]h ]h"]h$]h&]uh1j@hj hhhNhNubjA)}(hdevice_resume - Resumes a transfer on the channel - This command should operate synchronously on the channel, resuming right away the work of the given channel h](h)}(h device_resumeh]h device_resume}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubj<)}(hhh](jA)}(h"Resumes a transfer on the channel h]h)}(h!Resumes a transfer on the channelh]h!Resumes a transfer on the channel}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1j@hj7ubjA)}(hlThis command should operate synchronously on the channel, resuming right away the work of the given channel h]h)}(hkThis command should operate synchronously on the channel, resuming right away the work of the given channelh]hkThis command should operate synchronously on the channel, resuming right away the work of the given channel}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1j@hj7ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMhj%ubeh}(h]h ]h"]h$]h&]uh1j@hj hhhNhNubjA)}(hXdevice_terminate_all - Aborts all the pending and ongoing transfers on the channel - For aborted transfers the complete callback should not be called - Can be called from atomic context or from within a complete callback of a descriptor. Must not sleep. Drivers must be able to handle this correctly. - Termination may be asynchronous. The driver does not have to wait until the currently active transfer has completely stopped. See device_synchronize. h](h)}(hdevice_terminate_allh]hdevice_terminate_all}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjvubj<)}(hhh](jA)}(hhjubah}(h]h ]h"]h$]h&]uh1j@hjhhhhhNubjA)}(hvThe descriptor should be prepared for reuse by invoking ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE. h]h)}(huThe descriptor should be prepared for reuse by invoking ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE.h](h8The descriptor should be prepared for reuse by invoking }(hjhhhNhNubj)}(h``dmaengine_desc_set_reuse()``h]hdmaengine_desc_set_reuse()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh which will set DMA_CTRL_REUSE.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMAhj ubah}(h]h ]h"]h$]h&]uh1j@hjhhhhhNubjA)}(hw``dmaengine_desc_set_reuse()`` will succeed only when channel support reusable descriptor as exhibited by capabilities h]h)}(hv``dmaengine_desc_set_reuse()`` will succeed only when channel support reusable descriptor as exhibited by capabilitiesh](j)}(h``dmaengine_desc_set_reuse()``h]hdmaengine_desc_set_reuse()}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubhX will succeed only when channel support reusable descriptor as exhibited by capabilities}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMDhj7ubah}(h]h ]h"]h$]h&]uh1j@hjhhhhhNubjA)}(hAs a consequence, if a device driver wants to skip the ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers, because the DMA'd data wasn't used, it can resubmit the transfer right after its completion. h]h)}(hAs a consequence, if a device driver wants to skip the ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers, because the DMA'd data wasn't used, it can resubmit the transfer right after its completion.h](h7As a consequence, if a device driver wants to skip the }(hjahhhNhNubj)}(h``dma_map_sg()``h]h dma_map_sg()}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubh and }(hjahhhNhNubj)}(h``dma_unmap_sg()``h]hdma_unmap_sg()}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubhy in between 2 transfers, because the DMA’d data wasn’t used, it can resubmit the transfer right after its completion.}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMGhj]ubah}(h]h ]h"]h$]h&]uh1j@hjhhhhhNubjA)}(hXDescriptor can be freed in few ways - Clearing DMA_CTRL_REUSE by invoking ``dmaengine_desc_clear_reuse()`` and submitting for last txn - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only when DMA_CTRL_REUSE is already set - Terminating the channel h](h)}(h#Descriptor can be freed in few waysh]h#Descriptor can be freed in few ways}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjubj<)}(hhh](jA)}(haClearing DMA_CTRL_REUSE by invoking ``dmaengine_desc_clear_reuse()`` and submitting for last txn h]h)}(h`Clearing DMA_CTRL_REUSE by invoking ``dmaengine_desc_clear_reuse()`` and submitting for last txnh](h$Clearing DMA_CTRL_REUSE by invoking }(hjhhhNhNubj)}(h ``dmaengine_desc_clear_reuse()``h]hdmaengine_desc_clear_reuse()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and submitting for last txn}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMNhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hhExplicitly invoking ``dmaengine_desc_free()``, this can succeed only when DMA_CTRL_REUSE is already set h]h)}(hgExplicitly invoking ``dmaengine_desc_free()``, this can succeed only when DMA_CTRL_REUSE is already seth](hExplicitly invoking }(hjhhhNhNubj)}(h``dmaengine_desc_free()``h]hdmaengine_desc_free()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:, this can succeed only when DMA_CTRL_REUSE is already set}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMQhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hTerminating the channel h]h)}(hTerminating the channelh]hTerminating the channel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMNhjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hX_DMA_PREP_CMD - If set, the client driver tells DMA controller that passed data in DMA API is command data. - Interpretation of command data is DMA controller specific. It can be used for issuing commands to other peripherals/register reads/register writes for which the descriptor should be in different format from normal data descriptors. h](h)}(h DMA_PREP_CMDh]h DMA_PREP_CMD}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj&ubj<)}(hhh](jA)}(h\If set, the client driver tells DMA controller that passed data in DMA API is command data. h]h)}(h[If set, the client driver tells DMA controller that passed data in DMA API is command data.h]h[If set, the client driver tells DMA controller that passed data in DMA API is command data.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhj;ubah}(h]h ]h"]h$]h&]uh1j@hj8ubjA)}(hInterpretation of command data is DMA controller specific. It can be used for issuing commands to other peripherals/register reads/register writes for which the descriptor should be in different format from normal data descriptors. h]h)}(hInterpretation of command data is DMA controller specific. It can be used for issuing commands to other peripherals/register reads/register writes for which the descriptor should be in different format from normal data descriptors.h]hInterpretation of command data is DMA controller specific. It can be used for issuing commands to other peripherals/register reads/register writes for which the descriptor should be in different format from normal data descriptors.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjSubah}(h]h ]h"]h$]h&]uh1j@hj8ubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMXhj&ubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hXDMA_PREP_REPEAT - If set, the transfer will be automatically repeated when it ends until a new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag. If the next transfer to be queued on the channel does not have the DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the client terminates all transfers. - This flag is only supported if the channel reports the DMA_REPEAT capability. h](h)}(hDMA_PREP_REPEATh]hDMA_PREP_REPEAT}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjwubj<)}(hhh](jA)}(hXEIf set, the transfer will be automatically repeated when it ends until a new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag. If the next transfer to be queued on the channel does not have the DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the client terminates all transfers. h]h)}(hXDIf set, the transfer will be automatically repeated when it ends until a new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag. If the next transfer to be queued on the channel does not have the DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the client terminates all transfers.h]hXDIf set, the transfer will be automatically repeated when it ends until a new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag. If the next transfer to be queued on the channel does not have the DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the client terminates all transfers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hNThis flag is only supported if the channel reports the DMA_REPEAT capability. h]h)}(hMThis flag is only supported if the channel reports the DMA_REPEAT capability.h]hMThis flag is only supported if the channel reports the DMA_REPEAT capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMbhjwubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubjA)}(hXDMA_PREP_LOAD_EOT - If set, the transfer will replace the transfer currently being executed at the end of the transfer. - This is the default behaviour for non-repeated transfers, specifying DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference. - When using repeated transfers, DMA clients will usually need to set the DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep repeating the last repeated transfer and ignore the new transfers being queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was stuck on the previous transfer. - This flag is only supported if the channel reports the DMA_LOAD_EOT capability. h](h)}(hDMA_PREP_LOAD_EOTh]hDMA_PREP_LOAD_EOT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjubj<)}(hhh](jA)}(hdIf set, the transfer will replace the transfer currently being executed at the end of the transfer. h]h)}(hcIf set, the transfer will replace the transfer currently being executed at the end of the transfer.h]hcIf set, the transfer will replace the transfer currently being executed at the end of the transfer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hThis is the default behaviour for non-repeated transfers, specifying DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference. h]h)}(hThis is the default behaviour for non-repeated transfers, specifying DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.h]hThis is the default behaviour for non-repeated transfers, specifying DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphjubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hXDWhen using repeated transfers, DMA clients will usually need to set the DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep repeating the last repeated transfer and ignore the new transfers being queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was stuck on the previous transfer. h]h)}(hXCWhen using repeated transfers, DMA clients will usually need to set the DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep repeating the last repeated transfer and ignore the new transfers being queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was stuck on the previous transfer.h]hXCWhen using repeated transfers, DMA clients will usually need to set the DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep repeating the last repeated transfer and ignore the new transfers being queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was stuck on the previous transfer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj ubah}(h]h ]h"]h$]h&]uh1j@hjubjA)}(hPThis flag is only supported if the channel reports the DMA_LOAD_EOT capability. h]h)}(hOThis flag is only supported if the channel reports the DMA_LOAD_EOT capability.h]hOThis flag is only supported if the channel reports the DMA_LOAD_EOT capability.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj%ubah}(h]h ]h"]h$]h&]uh1j@hjubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhMmhjubeh}(h]h ]h"]h$]h&]uh1j@hjhhhNhNubeh}(h]h ]h"]h$]h&]jKjLuh1j;hhhM>hjhhubeh}(h] misc-notesah ]h"] misc notesah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hGeneral Design Notesh]hGeneral Design Notes}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhhhhhM}ubh)}(hMost of the DMAEngine drivers you'll see are based on a similar design that handles the end of transfer interrupts in the handler, but defer most work to a tasklet, including the start of a new transfer whenever the previous transfer ended.h]hMost of the DMAEngine drivers you’ll see are based on a similar design that handles the end of transfer interrupts in the handler, but defer most work to a tasklet, including the start of a new transfer whenever the previous transfer ended.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubh)}(hXThis is a rather inefficient design though, because the inter-transfer latency will be not only the interrupt latency, but also the scheduling latency of the tasklet, which will leave the channel idle in between, which will slow down the global transfer rate.h]hXThis is a rather inefficient design though, because the inter-transfer latency will be not only the interrupt latency, but also the scheduling latency of the tasklet, which will leave the channel idle in between, which will slow down the global transfer rate.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubh)}(hYou should avoid this kind of practice, and instead of electing a new transfer in your tasklet, move that part to the interrupt handler in order to have a shorter idle window (that we can't really avoid anyway).h]hYou should avoid this kind of practice, and instead of electing a new transfer in your tasklet, move that part to the interrupt handler in order to have a shorter idle window (that we can’t really avoid anyway).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubeh}(h]general-design-notesah ]h"]general design notesah$]h&]uh1hhhhhhhhM}ubh)}(hhh](h)}(hGlossaryh]hGlossary}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj<)}(hhh](jA)}(hvBurst: A number of consecutive read or write operations that can be queued to buffers before being flushed to memory. h]h)}(huBurst: A number of consecutive read or write operations that can be queued to buffers before being flushed to memory.h]huBurst: A number of consecutive read or write operations that can be queued to buffers before being flushed to memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j@hjhhhhhNubjA)}(h)Chunk: A contiguous collection of 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