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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h/Compute Express Link Driver Theory of Operationh]h/Compute Express Link Driver Theory of Operation}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh paragraph)}(hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device's contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.h]hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device’s contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjIhhubjH)}(hhh](jM)}(h The CXL Bush]h The CXL Bus}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjlhhhhhKubj])}(hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.h]hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hXPlatform firmware enumerates a menu of interleave options at the "CXL root port" (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example platform firmware may say at a given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.h]hXPlatform firmware enumerates a menu of interleave options at the “CXL root port” (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example platform firmware may say at a given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hX-Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test' module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints::h]hX4Here is a sample listing of a CXL topology defined by ‘cxl_test’. The ‘cxl_test’ module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK&hjlhhubh literal_block)}(hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }h]hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK+hjlhhubj])}(hXIn that listing each "root", "port", and "endpoint" object correspond a kernel 'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to its descendants. So "root" claims non-PCIe enumerable platform decode ranges and decodes them to "ports", "ports" decode to "endpoints", and "endpoints" represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).h]hXIn that listing each “root”, “port”, and “endpoint” object correspond a kernel ‘struct cxl_port’ object. A ‘cxl_port’ is a device that can decode CXL.mem to its descendants. So “root” claims non-PCIe enumerable platform decode ranges and decodes them to “ports”, “ports” decode to “endpoints”, and “endpoints” represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hXContinuing the RAID analogy, disks have both topology metadata and on device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.h]hXContinuing the RAID analogy, disks have both topology metadata and on device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hThe port metadata and potential decode schemes that a give memory device may participate can be determined via a command like::h]h~The port metadata and potential decode schemes that a give memory device may participate can be determined via a command like:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj)}(hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }h]hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjlhhubj])}(hXF...which queries the CXL topology to ask "given CXL Memory Expander with a kernel device name of 'mem3' which platform level decode ranges may this device participate". A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resource it has. In this example mem3 can participate in one or more of a PMEM interleave that spans to Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.h]hXN...which queries the CXL topology to ask “given CXL Memory Expander with a kernel device name of ‘mem3’ which platform level decode ranges may this device participate”. A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resource it has. In this example mem3 can participate in one or more of a PMEM interleave that spans to Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following::h]hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhMhjlhhubj)}(hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]h]hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjlhhubj])}(hL...where the naming scheme for decoders is "decoder.".h]hP...where the naming scheme for decoders is “decoder.”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhM8hjlhhubeh}(h] the-cxl-busah ]h"] the cxl busah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(hDriver Infrastructureh]hDriver Infrastructure}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj/hhhhhM;ubj])}(hFThis section covers the driver infrastructure for a CXL memory device.h]hFThis section covers the driver infrastructure for a CXL memory device.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhM=hj/hhubjH)}(hhh](jM)}(hCXL Memory Deviceh]hCXL Memory Device}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjNhhhhhM@ubj])}(hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn't CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.h]hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn’t CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjNhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe driver has several responsibilities, mainly: - Create the memX device and register on the CXL bus. - Enumerate device's register interface and map them. - Registers nvdimm bridge device with cxl_core. - Registers a CXL mailbox with cxl_core. h](hterm)}(h0The driver has several responsibilities, mainly:h]h0The driver has several responsibilities, mainly:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK!hjuubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h3Create the memX device and register on the CXL bus.h]j])}(hjh]h3Create the memX device and register on the CXL bus.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h3Enumerate device's register interface and map them.h]j])}(hjh]h5Enumerate device’s register interface and map them.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h-Registers nvdimm bridge device with cxl_core.h]j])}(hjh]h-Registers nvdimm bridge device with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h(Registers a CXL mailbox with cxl_core. h]j])}(h&Registers a CXL mailbox with cxl_core.h]h&Registers a CXL mailbox with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jshjhK!hjpubah}(h]h ]h"]h$]h&]uh1jnhjNhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single$__cxl_pci_mbox_send_cmd (C function)c.__cxl_pci_mbox_send_cmdhNtauh1jhjNhhhNhNubhdesc)}(hhh](hdesc_signature)}(hYint __cxl_pci_mbox_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]hdesc_signature_line)}(hXint __cxl_pci_mbox_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_sig_keyword_type)}(hinth]hint}(hj5hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j3hj/hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKubhdesc_sig_space)}(h h]h }(hjGhhhNhNubah}(h]h ]wah"]h$]h&]uh1jEhj/hhhjDhKubh desc_name)}(h__cxl_pci_mbox_send_cmdh]h desc_sig_name)}(h__cxl_pci_mbox_send_cmdh]h__cxl_pci_mbox_send_cmd}(hj^hhhNhNubah}(h]h ]nah"]h$]h&]uh1j\hjXubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jVhj/hhhjDhKubhdesc_parameterlist)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_parameter)}(hstruct cxl_mailbox *cxl_mboxh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhj}ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}ubh)}(hhh]j])}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jj`sbc.__cxl_pci_mbox_send_cmdasbuh1hhj}ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}ubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj}ubj])}(hcxl_mboxh]hcxl_mbox}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjwubj|)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj"hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]jc.__cxl_pci_mbox_send_cmdasbuh1hhjubjF)}(h h]h }(hj@hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hmbox_cmdh]hmbox_cmd}(hj[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjwubeh}(h]h ]h"]h$]h&]hhuh1juhj/hhhjDhKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1j-sphinx_line_type declaratorhj)hhhjDhKubah}(h]j ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j'hjDhKhj$hhubh desc_content)}(hhh]j])}(hExecute a mailbox commandh]hExecute a mailbox command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj$hhhjDhKubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j"hhhjNhNhNubh container)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. **Context** Any context. Expects mbox_mutex to be held. **Return** -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded. **Description** This is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command. The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h](j])}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjo)}(hhh](jt)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](jz)}(h ``struct cxl_mailbox *cxl_mbox``h]hliteral)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj)}(hhh]j])}(hCXL mailbox contexth]hCXL mailbox context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hH``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. h](jz)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hj h]hstruct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj)}(hhh]j])}(h%Command to send to the memory device.h]h%Command to send to the memory device.}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj* hKhj+ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj* hKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Context**h]j)}(hjP h]hContext}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj])}(h+Any context. Expects mbox_mutex to be held.h]h+Any context. Expects mbox_mutex to be held.}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj])}(h **Return**h]j)}(hjw h]hReturn}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjo)}(hhh]jt)}(h-ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded. h](jz)}(hD-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.h]hD-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj)}(hhh]j])}(hNCaller should check the return code in **mbox_cmd** to make sure it succeeded.h](h'Caller should check the return code in }(hj hhhNhNubj)}(h **mbox_cmd**h]hmbox_cmd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh to make sure it succeeded.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hKhj ubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj])}(hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.h]hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj])}(hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h]hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.h]hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chK hjNhhubj])}(hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.h]hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chKhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_memdev (C struct) c.cxl_memdevhNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h cxl_memdevh]j.)}(hstruct cxl_memdevh](j)}(hjh]hstruct}(hjM hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKubjF)}(h h]h }(hj[ hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjI hhhjZ hKubjW)}(h cxl_memdevh]j])}(hjG h]h cxl_memdev}(hjm hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hji ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjI hhhjZ hKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjE hhhjZ hKubah}(h]j@ ah ](jjeh"]h$]h&]jj)jhuh1j'hjZ hKhjB hhubj)}(hhh]j])}(h2CXL bus object representing a Type-3 Memory Deviceh]h2CXL bus object representing a Type-3 Memory Device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK&hj hhubah}(h]h ]h"]h$]h&]uh1jhjB hhhjZ hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; u8 scrub_cycle; int scrub_region_id; void *err_rec_array; }; **Members** ``dev`` driver core device object ``cdev`` char dev core object for ioctl operations ``cxlds`` The device state backing this device ``detach_work`` active memdev lost a port in its ancestry ``cxl_nvb`` coordinate removal of **cxl_nvd** if present ``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem ``endpoint`` connection to the CXL port topology for this memory device ``id`` id number of this memdev instance. ``depth`` endpoint port depth ``scrub_cycle`` current scrub cycle set for this device ``scrub_region_id`` id number of a backed region (if any) for which current scrub cycle set ``err_rec_array`` List of xarrarys to store the memdev error records to check attributes for a memory repair operation are from current boot.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK*hj ubj)}(hXOstruct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; u8 scrub_cycle; int scrub_region_id; void *err_rec_array; };h]hXOstruct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; u8 scrub_cycle; int scrub_region_id; void *err_rec_array; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK,hj ubj])}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK;hj ubjo)}(hhh](jt)}(h"``dev`` driver core device object h](jz)}(h``dev``h]j)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK(hj ubj)}(hhh]j])}(hdriver core device objecth]hdriver core device object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK(hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK(hj ubjt)}(h3``cdev`` char dev core object for ioctl operations h](jz)}(h``cdev``h]j)}(hj5 h]hcdev}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3 ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK)hj/ ubj)}(hhh]j])}(h)char dev core object for ioctl operationsh]h)char dev core object for ioctl operations}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjJ hK)hjK ubah}(h]h ]h"]h$]h&]uh1jhj/ ubeh}(h]h ]h"]h$]h&]uh1jshjJ hK)hj ubjt)}(h/``cxlds`` The device state backing this device h](jz)}(h ``cxlds``h]j)}(hjn h]hcxlds}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK*hjh ubj)}(hhh]j])}(h$The device state backing this deviceh]h$The device state backing this device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK*hj ubah}(h]h ]h"]h$]h&]uh1jhjh ubeh}(h]h ]h"]h$]h&]uh1jshj hK*hj ubjt)}(h:``detach_work`` active memdev lost a port in its ancestry h](jz)}(h``detach_work``h]j)}(hj h]h detach_work}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK+hj ubj)}(hhh]j])}(h)active memdev lost a port in its ancestryh]h)active memdev lost a port in its ancestry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK+hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK+hj ubjt)}(h9``cxl_nvb`` coordinate removal of **cxl_nvd** if present h](jz)}(h ``cxl_nvb``h]j)}(hj h]hcxl_nvb}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK,hj ubj)}(hhh]j])}(h,coordinate removal of **cxl_nvd** if presenth](hcoordinate removal of }(hj hhhNhNubj)}(h **cxl_nvd**h]hcxl_nvd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh if present}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj hK,hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK,hj ubjt)}(hE``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem h](jz)}(h ``cxl_nvd``h]j)}(hj+ h]hcxl_nvd}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj) ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK-hj% ubj)}(hhh]j])}(h8optional bridge to an nvdimm if the device supports pmemh]h8optional bridge to an nvdimm if the device supports pmem}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj@ hK-hjA ubah}(h]h ]h"]h$]h&]uh1jhj% ubeh}(h]h ]h"]h$]h&]uh1jshj@ hK-hj ubjt)}(hH``endpoint`` connection to the CXL port topology for this memory device h](jz)}(h ``endpoint``h]j)}(hjd h]hendpoint}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK.hj^ ubj)}(hhh]j])}(h:connection to the CXL port topology for this memory deviceh]h:connection to the CXL port topology for this memory device}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjy hK.hjz ubah}(h]h ]h"]h$]h&]uh1jhj^ ubeh}(h]h ]h"]h$]h&]uh1jshjy hK.hj ubjt)}(h*``id`` id number of this memdev instance. h](jz)}(h``id``h]j)}(hj h]hid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK/hj ubj)}(hhh]j])}(h"id number of this memdev instance.h]h"id number of this memdev instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK/hj ubjt)}(h``depth`` endpoint port depth h](jz)}(h ``depth``h]j)}(hj h]hdepth}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK0hj ubj)}(hhh]j])}(hendpoint port depthh]hendpoint port depth}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK0hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK0hj ubjt)}(h8``scrub_cycle`` current scrub cycle set for this device h](jz)}(h``scrub_cycle``h]j)}(hj h]h scrub_cycle}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK1hj ubj)}(hhh]j])}(h'current scrub cycle set for this deviceh]h'current scrub cycle set for this device}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj$ hK1hj% ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj$ hK1hj ubjt)}(h\``scrub_region_id`` id number of a backed region (if any) for which current scrub cycle set h](jz)}(h``scrub_region_id``h]j)}(hjH h]hscrub_region_id}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjF ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK2hjB ubj)}(hhh]j])}(hGid number of a backed region (if any) for which current scrub cycle seth]hGid number of a backed region (if any) for which current scrub cycle set}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj] hK2hj^ ubah}(h]h ]h"]h$]h&]uh1jhjB ubeh}(h]h ]h"]h$]h&]uh1jshj] hK2hj ubjt)}(h``err_rec_array`` List of xarrarys to store the memdev error records to check attributes for a memory repair operation are from current boot.h](jz)}(h``err_rec_array``h]j)}(hj h]h err_rec_array}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK4hj{ ubj)}(hhh]j])}(h{List of xarrarys to store the memdev error records to check attributes for a memory repair operation are from current boot.h]h{List of xarrarys to store the memdev error records to check attributes for a memory repair operation are from current boot.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK3hj ubah}(h]h ]h"]h$]h&]uh1jhj{ ubeh}(h]h ]h"]h$]h&]uh1jshj hK4hj ubeh}(h]h ]h"]h$]h&]uh1jnhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_event_state (C struct)c.cxl_event_statehNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hcxl_event_stateh]j.)}(hstruct cxl_event_stateh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK;ubjF)}(h h]h }(hj hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj hhhj hK;ubjW)}(hcxl_event_stateh]j])}(hj h]hcxl_event_state}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj hhhj hK;ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj hhhj hK;ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j'hj hK;hj hhubj)}(hhh]j])}(hEvent log driver stateh]hEvent log driver state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj hK;ubeh}(h]h ](jstructeh"]h$]h&]jjjj5jj5jjjuh1j"hhhjNhNhNubj)}(h**Definition**:: struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; }; **Members** ``buf`` Buffer to receive event data ``log_lock`` Serialize event_buf and log useh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj9ubj)}(h]struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; };h]h]struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; };}hjZsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj9ubj])}(h **Members**h]j)}(hjkh]hMembers}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj9ubjo)}(hhh](jt)}(h%``buf`` Buffer to receive event data h](jz)}(h``buf``h]j)}(hjh]hbuf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(hBuffer to receive event datah]hBuffer to receive event data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h,``log_lock`` Serialize event_buf and log useh](jz)}(h ``log_lock``h]j)}(hjh]hlog_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(hSerialize event_buf and log useh]hSerialize event_buf and log use}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubeh}(h]h ]h"]h$]h&]uh1jnhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_poison_state (C struct)c.cxl_poison_statehNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hcxl_poison_stateh]j.)}(hstruct cxl_poison_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKubjF)}(h h]h }(hj+hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhj*hKubjW)}(hcxl_poison_stateh]j])}(hjh]hcxl_poison_state}(hj=hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj9ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhj*hKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhj*hKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hj*hKhjhhubj)}(hhh]j])}(hDriver poison state infoh]hDriver poison state info}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj\hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj*hKubeh}(h]h ](jstructeh"]h$]h&]jjjjwjjwjjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; }; **Members** ``max_errors`` Maximum media error records held in device cache ``enabled_cmds`` All poison commands enabled in the CEL ``list_out`` The poison list payload returned by device ``lock`` Protect reads of the poison listh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj{ubj)}(hstruct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; };h]hstruct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj{ubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM hj{ubjo)}(hhh](jt)}(h@``max_errors`` Maximum media error records held in device cache h](jz)}(h``max_errors``h]j)}(hjh]h max_errors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(h0Maximum media error records held in device cacheh]h0Maximum media error records held in device cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h8``enabled_cmds`` All poison commands enabled in the CEL h](jz)}(h``enabled_cmds``h]j)}(hjh]h enabled_cmds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h&All poison commands enabled in the CELh]h&All poison commands enabled in the CEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h8``list_out`` The poison list payload returned by device h](jz)}(h ``list_out``h]j)}(hj>h]hlist_out}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj8ubj)}(hhh]j])}(h*The poison list payload returned by deviceh]h*The poison list payload returned by device}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjShMhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jshjShMhjubjt)}(h)``lock`` Protect reads of the poison listh](jz)}(h``lock``h]j)}(hjwh]hlock}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjqubj)}(hhh]j])}(h Protect reads of the poison listh]h Protect reads of the poison list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubeh}(h]h ]h"]h$]h&]uh1jnhj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjNhhubj])}(hReads of the poison list are synchronized to ensure that a reader does not get an incomplete list because their request overlapped (was interrupted or preceded by) another read request of the same DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1h]hReads of the poison list are synchronized to ensure that a reader does not get an incomplete list because their request overlapped (was interrupted or preceded by) another read request of the same DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_fw_state (C struct)c.cxl_fw_statehNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h cxl_fw_stateh]j.)}(hstruct cxl_fw_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM ubjW)}(h cxl_fw_stateh]j])}(hjh]h cxl_fw_state}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM hjhhubj)}(hhh]j])}(h"Firmware upload / activation stateh]h"Firmware upload / activation state}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMMhj7hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jstructeh"]h$]h&]jjjjRjjRjjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_fw_state { unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)]; bool oneshot; int num_slots; int cur_slot; int next_slot; }; **Members** ``state`` fw_uploader state bitmask ``oneshot`` whether the fw upload fits in a single transfer ``num_slots`` Number of FW slots available ``cur_slot`` Slot number currently active ``next_slot`` Slot number for the new firmwareh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh:}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMQhjVubj)}(hstruct cxl_fw_state { unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)]; bool oneshot; int num_slots; int cur_slot; int next_slot; };h]hstruct cxl_fw_state { unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)]; bool oneshot; int num_slots; int cur_slot; int next_slot; };}hjwsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShjVubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM[hjVubjo)}(hhh](jt)}(h$``state`` fw_uploader state bitmask h](jz)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMPhjubj)}(hhh]j])}(hfw_uploader state bitmaskh]hfw_uploader state bitmask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMPhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMPhjubjt)}(h<``oneshot`` whether the fw upload fits in a single transfer h](jz)}(h ``oneshot``h]j)}(hjh]honeshot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMQhjubj)}(hhh]j])}(h/whether the fw upload fits in a single transferh]h/whether the fw upload fits in a single transfer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMQhjubjt)}(h+``num_slots`` Number of FW slots available h](jz)}(h ``num_slots``h]j)}(hjh]h num_slots}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMRhjubj)}(hhh]j])}(hNumber of FW slots availableh]hNumber of FW slots available}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj.hMRhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj.hMRhjubjt)}(h*``cur_slot`` Slot number currently active h](jz)}(h ``cur_slot``h]j)}(hjRh]hcur_slot}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShjLubj)}(hhh]j])}(hSlot number currently activeh]hSlot number currently active}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjghMShjhubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jshjghMShjubjt)}(h.``next_slot`` Slot number for the new firmwareh](jz)}(h ``next_slot``h]j)}(hjh]h next_slot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShjubj)}(hhh]j])}(h Slot number for the new firmwareh]h Slot number for the new firmware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMThjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMShjubeh}(h]h ]h"]h$]h&]uh1jnhjVubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_security_state (C struct)c.cxl_security_statehNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hcxl_security_stateh]j.)}(hstruct cxl_security_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMZubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMZubjW)}(hcxl_security_stateh]j])}(hjh]hcxl_security_state}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMZubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMZubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMZhjhhubj)}(hhh]j])}(hDevice security stateh]hDevice security state}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM^hj$hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMZubeh}(h]h ](jstructeh"]h$]h&]jjjj?jj?jjjuh1j"hhhjNhNhNubj)}(hXB**Definition**:: struct cxl_security_state { unsigned long state; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)]; int poll_tmo_secs; bool sanitize_active; struct delayed_work poll_dwork; struct kernfs_node *sanitize_node; }; **Members** ``state`` state of last security operation ``enabled_cmds`` All security commands enabled in the CEL ``poll_tmo_secs`` polling timeout ``sanitize_active`` sanitize completion pending ``poll_dwork`` polling work item ``sanitize_node`` sanitation sysfs file to notifyh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubh:}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMbhjCubj)}(hstruct cxl_security_state { unsigned long state; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)]; int poll_tmo_secs; bool sanitize_active; struct delayed_work poll_dwork; struct kernfs_node *sanitize_node; };h]hstruct cxl_security_state { unsigned long state; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)]; int poll_tmo_secs; bool sanitize_active; struct delayed_work poll_dwork; struct kernfs_node *sanitize_node; };}hjdsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMdhjCubj])}(h **Members**h]j)}(hjuh]hMembers}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMmhjCubjo)}(hhh](jt)}(h+``state`` state of last security operation h](jz)}(h ``state``h]j)}(hjh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMahjubj)}(hhh]j])}(h state of last security operationh]h state of last security operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMahjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMahjubjt)}(h:``enabled_cmds`` All security commands enabled in the CEL h](jz)}(h``enabled_cmds``h]j)}(hjh]h enabled_cmds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMbhjubj)}(hhh]j])}(h(All security commands enabled in the CELh]h(All security commands enabled in the CEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMbhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMbhjubjt)}(h"``poll_tmo_secs`` polling timeout h](jz)}(h``poll_tmo_secs``h]j)}(hjh]h poll_tmo_secs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMchjubj)}(hhh]j])}(hpolling timeouth]hpolling timeout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMchjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMchjubjt)}(h0``sanitize_active`` sanitize completion pending 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](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMlubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMlubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMlhjhhubj)}(hhh]j])}(hDPA performance property entryh]hDPA performance property entry}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjJhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMlubeh}(h]h ](jstructeh"]h$]h&]jjjjejjejjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_dpa_perf { struct range dpa_range; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; int qos_class; }; **Members** ``dpa_range`` range for DPA address ``coord`` QoS performance data (i.e. latency, bandwidth) ``cdat_coord`` raw QoS performance data from CDAT ``qos_class`` QoS Class cookiesh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubh:}(hjmhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjiubj)}(hstruct cxl_dpa_perf { struct range dpa_range; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; int qos_class; };h]hstruct cxl_dpa_perf { struct range dpa_range; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; int qos_class; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjiubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjiubjo)}(hhh](jt)}(h$``dpa_range`` range for DPA address h](jz)}(h ``dpa_range``h]j)}(hjh]h dpa_range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hrange for DPA addressh]hrange for DPA address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h9``coord`` QoS performance data (i.e. latency, bandwidth) h](jz)}(h ``coord``h]j)}(hjh]hcoord}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h.QoS performance data (i.e. latency, bandwidth)h]h.QoS performance data (i.e. latency, bandwidth)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h2``cdat_coord`` raw QoS performance data from CDAT h](jz)}(h``cdat_coord``h]j)}(hj,h]h cdat_coord}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj&ubj)}(hhh]j])}(h"raw QoS performance data from CDATh]h"raw QoS performance data from CDAT}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjAhMhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jshjAhMhjubjt)}(h``qos_class`` QoS Class cookiesh](jz)}(h ``qos_class``h]j)}(hjeh]h qos_class}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj_ubj)}(hhh]j])}(hQoS Class cookiesh]hQoS Class cookies}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshjzhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_dpa_partition (C struct)c.cxl_dpa_partitionhNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hcxl_dpa_partitionh]j.)}(hstruct cxl_dpa_partitionh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMubjW)}(hcxl_dpa_partitionh]j])}(hjh]hcxl_dpa_partition}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMhjhhubj)}(hhh]j])}(hDPA partition descriptorh]hDPA partition descriptor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j"hhhjNhNhNubj)}(hXx**Definition**:: struct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; }; **Members** ``res`` shortcut to the partition in the DPA resource tree (cxlds->dpa_res) ``perf`` performance attributes of the partition from CDAT ``mode`` operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh:}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hvstruct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; };h]hvstruct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; };}hj>sbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj])}(h **Members**h]j)}(hjOh]hMembers}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubjo)}(hhh](jt)}(hL``res`` shortcut to the partition in the DPA resource tree (cxlds->dpa_res) h](jz)}(h``res``h]j)}(hjnh]hres}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjhubj)}(hhh]j])}(hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)h]hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jshjhMhjeubjt)}(h;``perf`` performance attributes of the partition from CDAT h](jz)}(h``perf``h]j)}(hjh]hperf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h1performance attributes of the partition from CDATh]h1performance attributes of the partition from CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjeubjt)}(hH``mode`` operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](jz)}(h``mode``h]j)}(hjh]hmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h]h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjeubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_dev_state (C struct)c.cxl_dev_statehNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h cxl_dev_stateh]j.)}(hstruct cxl_dev_stateh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjF)}(h h]h }(hjHhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj6hhhjGhMubjW)}(h cxl_dev_stateh]j])}(hj4h]h cxl_dev_state}(hjZhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjVubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj6hhhjGhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj2hhhjGhMubah}(h]j-ah ](jjeh"]h$]h&]jj)jhuh1j'hjGhMhj/hhubj)}(hhh]j])}(hThe driver device stateh]hThe driver device state}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjyhhubah}(h]h ]h"]h$]h&]uh1jhj/hhhjGhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; }; **Members** ``dev`` The device associated with this CXL state ``cxlmd`` The device representing the CXL.mem capabilities of **dev** ``reg_map`` component and ras register mapping parameters ``regs`` Parsed register blocks ``cxl_dvsec`` Offset to the PCIe device DVSEC ``rcd`` operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) ``media_ready`` Indicate whether the device media is usable ``dpa_res`` Overall DPA resource tree for the device ``part`` DPA partition array ``nr_partitions`` Number of DPA partitions ``serial`` PCIe Device Serial Number ``type`` Generic Memory Class device or Vendor Specific Memory device ``cxl_mbox`` CXL mailbox context ``cxlfs`` CXL features contexth](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hXstruct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; };h]hXstruct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubjo)}(hhh](jt)}(h2``dev`` The device associated with this CXL state h](jz)}(h``dev``h]j)}(hjh]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h)The device associated with this CXL stateh]h)The device associated with this CXL state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(hF``cxlmd`` The device representing the CXL.mem capabilities of **dev** h](jz)}(h ``cxlmd``h]j)}(hj"h]hcxlmd}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h;The device representing the CXL.mem capabilities of **dev**h](h4The device representing the CXL.mem capabilities of }(hj;hhhNhNubj)}(h**dev**h]hdev}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j\hj7hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj7hMhjubjt)}(h:``reg_map`` component and ras register mapping parameters h](jz)}(h ``reg_map``h]j)}(hjih]hreg_map}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjcubj)}(hhh]j])}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj~hMhjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jshj~hMhjubjt)}(h ``regs`` Parsed register blocks h](jz)}(h``regs``h]j)}(hjh]hregs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hParsed register blocksh]hParsed register blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h.``cxl_dvsec`` Offset to the PCIe device DVSEC h](jz)}(h ``cxl_dvsec``h]j)}(hjh]h cxl_dvsec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hOffset to the PCIe device DVSECh]hOffset to the PCIe device DVSEC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(hN``rcd`` operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) h](jz)}(h``rcd``h]j)}(hjh]hrcd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)h]hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj)hMhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj)hMhjubjt)}(h<``media_ready`` Indicate whether the device media is usable h](jz)}(h``media_ready``h]j)}(hjMh]h media_ready}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjGubj)}(hhh]j])}(h+Indicate whether the device media is usableh]h+Indicate whether the device media is usable}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjbhMhjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jshjbhMhjubjt)}(h5``dpa_res`` Overall DPA resource tree for the device h](jz)}(h ``dpa_res``h]j)}(hjh]hdpa_res}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h(Overall DPA resource tree for the deviceh]h(Overall DPA resource tree for the device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h``part`` DPA partition array h](jz)}(h``part``h]j)}(hjh]hpart}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hDPA partition arrayh]hDPA partition array}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h+``nr_partitions`` Number of DPA partitions h](jz)}(h``nr_partitions``h]j)}(hjh]h nr_partitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hNumber of DPA partitionsh]hNumber of DPA partitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj hMhjubjt)}(h%``serial`` PCIe Device Serial Number h](jz)}(h ``serial``h]j)}(hj1h]hserial}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj+ubj)}(hhh]j])}(hPCIe Device Serial Numberh]hPCIe Device Serial Number}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjFhMhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jshjFhMhjubjt)}(hF``type`` Generic Memory Class device or Vendor Specific Memory device h](jz)}(h``type``h]j)}(hjjh]htype}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjdubj)}(hhh]j])}(h to validate the fields passed in by the user then submit the }(hj"hhhNhNubj)}(h **opcode**h]hopcode}(hj7"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubh to the hardware.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjNhhubj])}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hjP"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_hdm (C struct) c.cxl_hdmhNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hcxl_hdmh]j.)}(hstruct cxl_hdmh](j)}(hjh]hstruct}(hjx"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjt"hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM ubjF)}(h h]h }(hj"hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjt"hhhj"hM ubjW)}(hcxl_hdmh]j])}(hjr"h]hcxl_hdm}(hj"hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj"ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjt"hhhj"hM ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjp"hhhj"hM ubah}(h]jk"ah ](jjeh"]h$]h&]jj)jhuh1j'hj"hM hjm"hhubj)}(hhh]j])}(h7HDM Decoder registers and cached / decoded capabilitiesh]h7HDM Decoder registers and cached / decoded capabilities}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj"hhubah}(h]h ]h"]h$]h&]uh1jhjm"hhhj"hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj"jj"jjjuh1j"hhhjNhNhNubj)}(hX**Definition**:: struct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; }; **Members** ``regs`` mapped registers, see devm_cxl_setup_hdm() ``decoder_count`` number of decoders for this port ``target_count`` for switch decoders, max downstream port targets ``interleave_mask`` interleave granularity capability, see check_interleave_cap() ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() ``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubh:}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj"ubj)}(hstruct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };h]hstruct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };}hj"sbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj"ubj])}(h **Members**h]j)}(hj#h]hMembers}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj"ubjo)}(hhh](jt)}(h4``regs`` mapped registers, see devm_cxl_setup_hdm() h](jz)}(h``regs``h]j)}(hj'#h]hregs}(hj)#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%#ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj!#ubj)}(hhh]j])}(h*mapped registers, see devm_cxl_setup_hdm()h]h*mapped registers, see devm_cxl_setup_hdm()}(hj@#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj<#hMhj=#ubah}(h]h ]h"]h$]h&]uh1jhj!#ubeh}(h]h ]h"]h$]h&]uh1jshj<#hMhj#ubjt)}(h3``decoder_count`` number of decoders for this port h](jz)}(h``decoder_count``h]j)}(hj`#h]h decoder_count}(hjb#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^#ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjZ#ubj)}(hhh]j])}(h number of decoders for this porth]h number of decoders for this port}(hjy#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hju#hMhjv#ubah}(h]h ]h"]h$]h&]uh1jhjZ#ubeh}(h]h ]h"]h$]h&]uh1jshju#hMhj#ubjt)}(hB``target_count`` for switch decoders, max downstream port targets h](jz)}(h``target_count``h]j)}(hj#h]h target_count}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj#ubj)}(hhh]j])}(h0for switch decoders, max downstream port targetsh]h0for switch decoders, max downstream port targets}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jshj#hMhj#ubjt)}(hR``interleave_mask`` interleave granularity capability, see check_interleave_cap() h](jz)}(h``interleave_mask``h]j)}(hj#h]hinterleave_mask}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj#ubj)}(hhh]j])}(h=interleave granularity capability, see check_interleave_cap()h]h=interleave granularity capability, see check_interleave_cap()}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#hMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jshj#hMhj#ubjt)}(hQ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() h](jz)}(h``iw_cap_mask``h]j)}(hj $h]h iw_cap_mask}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj $ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj$ubj)}(hhh]j])}(h@bitmask of supported interleave ways, see check_interleave_cap()h]h@bitmask of supported interleave ways, see check_interleave_cap()}(hj$$hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj $hMhj!$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jshj $hMhj#ubjt)}(h2``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](jz)}(h``port``h]j)}(hjD$h]hport}(hjF$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB$ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj>$ubj)}(hhh]j])}(h)mapped cxl_port, see devm_cxl_setup_hdm()h]h)mapped cxl_port, see devm_cxl_setup_hdm()}(hj]$hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjZ$ubah}(h]h ]h"]h$]h&]uh1jhj>$ubeh}(h]h ]h"]h$]h&]uh1jshjY$hMhj#ubeh}(h]h ]h"]h$]h&]uh1jnhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'set_exclusive_cxl_commands (C function)c.set_exclusive_cxl_commandshNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hSvoid set_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j.)}(hRvoid set_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j4)}(hvoidh]hvoid}(hj$hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj$hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM=ubjF)}(h h]h }(hj$hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj$hhhj$hM=ubjW)}(hset_exclusive_cxl_commandsh]j])}(hset_exclusive_cxl_commandsh]hset_exclusive_cxl_commands}(hj$hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj$ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj$hhhj$hM=ubjv)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubjF)}(h h]h }(hj$hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj$ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj$hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]j)}jj$sbc.set_exclusive_cxl_commandsasbuh1hhj$ubjF)}(h h]h }(hj%hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj$ubj)}(hjh]h*}(hj'%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj])}(hmdsh]hmds}(hj4%hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj$ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj$ubj|)}(hunsigned long *cmdsh](j4)}(hunsignedh]hunsigned}(hjM%hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjI%ubjF)}(h h]h }(hj[%hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjI%ubj4)}(hlongh]hlong}(hji%hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjI%ubjF)}(h h]h }(hjw%hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjI%ubj)}(hjh]h*}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjI%ubj])}(hcmdsh]hcmds}(hj%hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjI%ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj$ubeh}(h]h ]h"]h$]h&]hhuh1juhj$hhhj$hM=ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj$hhhj$hM=ubah}(h]j$ah ](jjeh"]h$]h&]jj)jhuh1j'hj$hM=hj$hhubj)}(hhh]j])}(h$atomically disable user cxl commandsh]h$atomically disable user cxl commands}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM=hj%hhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj$hM=ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj%jj%jjjuh1j"hhhjNhNhNubj)}(hXP**Parameters** ``struct cxl_memdev_state *mds`` The device state to operate on ``unsigned long *cmds`` bitmap of commands to mark exclusive **Description** Grab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](j])}(h**Parameters**h]j)}(hj%h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMAhj%ubjo)}(hhh](jt)}(h@``struct cxl_memdev_state *mds`` The device state to operate on h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj%h]hstruct cxl_memdev_state *mds}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM>hj%ubj)}(hhh]j])}(hThe device state to operate onh]hThe device state to operate on}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj&hM>hj&ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jshj&hM>hj%ubjt)}(h=``unsigned long *cmds`` bitmap of commands to mark exclusive h](jz)}(h``unsigned long *cmds``h]j)}(hj6&h]hunsigned long *cmds}(hj8&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4&ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM?hj0&ubj)}(hhh]j])}(h$bitmap of commands to mark exclusiveh]h$bitmap of commands to mark exclusive}(hjO&hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjK&hM?hjL&ubah}(h]h ]h"]h$]h&]uh1jhj0&ubeh}(h]h ]h"]h$]h&]uh1jshjK&hM?hj%ubeh}(h]h ]h"]h$]h&]uh1jnhj%ubj])}(h**Description**h]j)}(hjq&h]h Description}(hjs&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo&ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMAhj%ubj])}(hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in }(hj&hhhNhNubj)}(h**cmds**h]hcmds}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubh.}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMAhj%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)clear_exclusive_cxl_commands (C function)c.clear_exclusive_cxl_commandshNtauh1jhjNhhhNhNubj#)}(hhh](j()}(hUvoid clear_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j.)}(hTvoid clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j4)}(hvoidh]hvoid}(hj&hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj&hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMQubjF)}(h h]h }(hj&hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj&hhhj&hMQubjW)}(hclear_exclusive_cxl_commandsh]j])}(hclear_exclusive_cxl_commandsh]hclear_exclusive_cxl_commands}(hj&hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj&ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj&hhhj&hMQubjv)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubjF)}(h h]h }(hj'hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj'ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj#'hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj 'ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%'modnameN classnameNjj)}j]j)}jj&sbc.clear_exclusive_cxl_commandsasbuh1hhj'ubjF)}(h h]h }(hjC'hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj'ubj)}(hjh]h*}(hjQ'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubj])}(hmdsh]hmds}(hj^'hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj'ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj&ubj|)}(hunsigned long *cmdsh](j4)}(hunsignedh]hunsigned}(hjw'hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjs'ubjF)}(h h]h }(hj'hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjs'ubj4)}(hlongh]hlong}(hj'hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjs'ubjF)}(h h]h }(hj'hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjs'ubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs'ubj])}(hcmdsh]hcmds}(hj'hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjs'ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj&ubeh}(h]h ]h"]h$]h&]hhuh1juhj&hhhj&hMQubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj&hhhj&hMQubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1j'hj&hMQhj&hhubj)}(hhh]j])}(h#atomically enable user cxl commandsh]h#atomically enable user cxl commands}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMQhj'hhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj&hMQubeh}(h]h ](jfunctioneh"]h$]h&]jjjj'jj'jjjuh1j"hhhjNhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device state to modify ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](j])}(h**Parameters**h]j)}(hj(h]h Parameters}(hj (hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMUhj(ubjo)}(hhh](jt)}(h<``struct cxl_memdev_state *mds`` The device state to modify h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj'(h]hstruct cxl_memdev_state *mds}(hj)(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%(ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMRhj!(ubj)}(hhh]j])}(hThe device state to modifyh]hThe device state to modify}(hj@(hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj<(hMRhj=(ubah}(h]h ]h"]h$]h&]uh1jhj!(ubeh}(h]h ]h"]h$]h&]uh1jshj<(hMRhj(ubjt)}(hJ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](jz)}(h``unsigned long *cmds``h]j)}(hj`(h]hunsigned long *cmds}(hjb(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^(ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMThjZ(ubj)}(hhh]j])}(h2bitmap of commands to mark available for userspaceh]h2bitmap of commands to mark available for userspace}(hjy(hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMShjv(ubah}(h]h ]h"]h$]h&]uh1jhjZ(ubeh}(h]h ]h"]h$]h&]uh1jshju(hMThj(ubeh}(h]h ]h"]h$]h&]uh1jnhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_mem_get_fw_info (C function)c.cxl_mem_get_fw_infohNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h6int cxl_mem_get_fw_info (struct cxl_memdev_state *mds)h]j.)}(h5int cxl_mem_get_fw_info(struct cxl_memdev_state *mds)h](j4)}(hinth]hint}(hj(hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj(hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMubjF)}(h h]h }(hj(hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(hhhj(hMubjW)}(hcxl_mem_get_fw_infoh]j])}(hcxl_mem_get_fw_infoh]hcxl_mem_get_fw_info}(hj(hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj(ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj(hhhj(hMubjv)}(h(struct cxl_memdev_state *mds)h]j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubjF)}(h h]h }(hj)hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj)hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj)modnameN classnameNjj)}j]j)}jj(sbc.cxl_mem_get_fw_infoasbuh1hhj(ubjF)}(h h]h }(hj5)hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(ubj)}(hjh]h*}(hjC)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj])}(hmdsh]hmds}(hjP)hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj(ubah}(h]h ]h"]h$]h&]hhuh1juhj(hhhj(hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj(hhhj(hMubah}(h]j(ah ](jjeh"]h$]h&]jj)jhuh1j'hj(hMhj(hhubj)}(hhh]j])}(hGet Firmware infoh]hGet Firmware info}(hjz)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjw)hhubah}(h]h ]h"]h$]h&]uh1jhj(hhhj(hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj)jj)jjjuh1j"hhhjNhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Retrieve firmware info for the device specified. See CXL-3.0 8.2.9.3.1 Get FW Info **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hj)h]h Parameters}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubjo)}(hhh]jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj)h]hstruct cxl_memdev_state *mds}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jshj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jnhj)ubj])}(h**Description**h]j)}(hj)h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubj])}(h0Retrieve firmware info for the device specified.h]h0Retrieve firmware info for the device specified.}(hj *hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubj])}(h!See CXL-3.0 8.2.9.3.1 Get FW Infoh]h!See CXL-3.0 8.2.9.3.1 Get FW Info}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubj])}(h **Return**h]j)}(hj,*h]hReturn}(hj.*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj**ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hjB*hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_mem_activate_fw (C function)c.cxl_mem_activate_fwhNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h@int cxl_mem_activate_fw (struct cxl_memdev_state *mds, int slot)h]j.)}(h?int cxl_mem_activate_fw(struct cxl_memdev_state *mds, int slot)h](j4)}(hinth]hint}(hjq*hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjm*hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMubjF)}(h h]h }(hj*hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjm*hhhj*hMubjW)}(hcxl_mem_activate_fwh]j])}(hcxl_mem_activate_fwh]hcxl_mem_activate_fw}(hj*hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj*ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjm*hhhj*hMubjv)}(h((struct cxl_memdev_state *mds, int slot)h](j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubjF)}(h h]h }(hj*hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj*ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj*hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj*ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj*modnameN classnameNjj)}j]j)}jj*sbc.cxl_mem_activate_fwasbuh1hhj*ubjF)}(h h]h }(hj*hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj*ubj)}(hjh]h*}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj])}(hmdsh]hmds}(hj+hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj*ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj*ubj|)}(hint sloth](j4)}(hinth]hint}(hj +hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj+ubjF)}(h h]h }(hj.+hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj+ubj])}(hsloth]hslot}(hj<+hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj*ubeh}(h]h ]h"]h$]h&]hhuh1juhjm*hhhj*hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hji*hhhj*hMubah}(h]jd*ah ](jjeh"]h$]h&]jj)jhuh1j'hj*hMhjf*hhubj)}(hhh]j])}(hActivate Firmwareh]hActivate Firmware}(hjf+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjc+hhubah}(h]h ]h"]h$]h&]uh1jhjf*hhhj*hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj~+jj~+jjjuh1j"hhhjNhNhNubj)}(hX/**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation ``int slot`` slot number to activate **Description** Activate firmware in a given slot for the device specified. See CXL-3.0 8.2.9.3.3 Activate FW **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hj+h]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubjo)}(hhh](jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj+h]hstruct cxl_memdev_state *mds}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj+hMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jshj+hMhj+ubjt)}(h%``int slot`` slot number to activate h](jz)}(h ``int slot``h]j)}(hj+h]hint slot}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj)}(hhh]j])}(hslot number to activateh]hslot number to activate}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj+hMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jshj+hMhj+ubeh}(h]h ]h"]h$]h&]uh1jnhj+ubj])}(h**Description**h]j)}(hj,h]h Description}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj])}(h;Activate firmware in a given slot for the device specified.h]h;Activate firmware in a given slot for the device specified.}(hj1,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj])}(h!See CXL-3.0 8.2.9.3.3 Activate FWh]h!See CXL-3.0 8.2.9.3.3 Activate FW}(hj@,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj])}(h **Return**h]j)}(hjQ,h]hReturn}(hjS,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO,ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hjg,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"cxl_mem_abort_fw_xfer (C function)c.cxl_mem_abort_fw_xferhNtauh1jhjNhhhNhNubj#)}(hhh](j()}(h8int cxl_mem_abort_fw_xfer (struct cxl_memdev_state *mds)h]j.)}(h7int cxl_mem_abort_fw_xfer(struct cxl_memdev_state *mds)h](j4)}(hinth]hint}(hj,hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj,hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMubjF)}(h h]h }(hj,hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj,hhhj,hMubjW)}(hcxl_mem_abort_fw_xferh]j])}(hcxl_mem_abort_fw_xferh]hcxl_mem_abort_fw_xfer}(hj,hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj,ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj,hhhj,hMubjv)}(h(struct cxl_memdev_state *mds)h]j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubjF)}(h h]h }(hj,hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj,ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj,hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj,ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,modnameN classnameNjj)}j]j)}jj,sbc.cxl_mem_abort_fw_xferasbuh1hhj,ubjF)}(h h]h }(hj-hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj,ubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubj])}(hmdsh]hmds}(hj,-hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj,ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj,ubah}(h]h ]h"]h$]h&]hhuh1juhj,hhhj,hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj,hhhj,hMubah}(h]j,ah ](jjeh"]h$]h&]jj)jhuh1j'hj,hMhj,hhubj)}(hhh]j])}(h Abort an in-progress FW transferh]h Abort an in-progress FW transfer}(hjV-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjS-hhubah}(h]h ]h"]h$]h&]uh1jhj,hhhj,hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjn-jjn-jjjuh1j"hhhjNhNhNubj)}(hX **Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Abort an in-progress firmware transfer for the device specified. See CXL-3.0 8.2.9.3.2 Transfer FW **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hjx-h]h Parameters}(hjz-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv-ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr-ubjo)}(hhh]jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj-h]hstruct cxl_memdev_state *mds}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj-ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj-hMhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jshj-hMhj-ubah}(h]h ]h"]h$]h&]uh1jnhjr-ubj])}(h**Description**h]j)}(hj-h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr-ubj])}(h@Abort an in-progress firmware transfer for the device specified.h]h@Abort an in-progress firmware transfer for the device specified.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr-ubj])}(h!See CXL-3.0 8.2.9.3.2 Transfer FWh]h!See CXL-3.0 8.2.9.3.2 Transfer FW}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr-ubj])}(h **Return**h]j)}(hj.h]hReturn}(hj .hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hjr-ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubeh}(h]cxl-memory-deviceah ]h"]cxl memory deviceah$]h&]uh1jGhj/hhhhhM@ubjH)}(hhh](jM)}(hCXL Porth]hCXL Port}(hj?.hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj<.hhhhhMRubj])}(hXThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the **component_reg_phys** value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.h](hrThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the }(hjM.hhhNhNubj)}(h**component_reg_phys**h]hcomponent_reg_phys}(hjU.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM.ubhXK value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.}(hjM.hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chK hj<.hhubj])}(hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.h]hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.}(hjn.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chKhj<.hhubeh}(h]cxl-portah ]h"]cxl portah$]h&]uh1jGhj/hhhhhMRubjH)}(hhh](jM)}(hCXL Coreh]hCXL Core}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj.hhhhhMWubj])}(hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).h]hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:430: ./drivers/cxl/cxl.hhKhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_register_map (C struct)c.cxl_register_maphNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_register_maph]j.)}(hstruct cxl_register_maph](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhKubjF)}(h h]h }(hj.hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj.hhhj.hKubjW)}(hcxl_register_maph]j])}(hj.h]hcxl_register_map}(hj.hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj.ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj.hhhj.hKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj.hhhj.hKubah}(h]j.ah ](jjeh"]h$]h&]jj)jhuh1j'hj.hKhj.hhubj)}(hhh]j])}(h1DVSEC harvested register block mapping parametersh]h1DVSEC harvested register block mapping parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj.hKubeh}(h]h ](jstructeh"]h$]h&]jjjj/jj/jjjuh1j"hhhj.hNhNubj)}(hX\**Definition**:: struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; }; **Members** ``host`` device for devm operations and logging ``base`` virtual base of the register-block-BAR + **block_offset** ``resource`` physical resource base of the register block ``max_size`` maximum mapping size to perform register search ``reg_type`` see enum cxl_regloc_type ``{unnamed_union}`` anonymous ``component_map`` cxl_reg_map for component registers ``device_map`` cxl_reg_maps for device registers ``pmu_map`` cxl_reg_maps for CXL Performance Monitoring Unitsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj$/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj /ubh:}(hj /hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj/ubj)}(hX7struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; };h]hX7struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; };}hj=/sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj/ubj])}(h **Members**h]j)}(hjN/h]hMembers}(hjP/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL/ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM"hj/ubjo)}(hhh](jt)}(h0``host`` device for devm operations and logging h](jz)}(h``host``h]j)}(hjm/h]hhost}(hjo/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk/ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjg/ubj)}(hhh]j])}(h&device for devm operations and loggingh]h&device for devm operations and logging}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhjg/ubeh}(h]h ]h"]h$]h&]uh1jshj/hMhjd/ubjt)}(hC``base`` virtual base of the register-block-BAR + **block_offset** h](jz)}(h``base``h]j)}(hj/h]hbase}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj/ubj)}(hhh]j])}(h9virtual base of the register-block-BAR + **block_offset**h](h)virtual base of the register-block-BAR + }(hj/hhhNhNubj)}(h**block_offset**h]h block_offset}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j\hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jshj/hMhjd/ubjt)}(h:``resource`` physical resource base of the register block h](jz)}(h ``resource``h]j)}(hj/h]hresource}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj/ubj)}(hhh]j])}(h,physical resource base of the register blockh]h,physical resource base of the register block}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jshj0hMhjd/ubjt)}(h=``max_size`` maximum mapping size to perform register search h](jz)}(h ``max_size``h]j)}(hj&0h]hmax_size}(hj(0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$0ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj 0ubj)}(hhh]j])}(h/maximum mapping size to perform register searchh]h/maximum mapping size to perform register search}(hj?0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;0hMhj<0ubah}(h]h ]h"]h$]h&]uh1jhj 0ubeh}(h]h ]h"]h$]h&]uh1jshj;0hMhjd/ubjt)}(h&``reg_type`` see enum cxl_regloc_type h](jz)}(h ``reg_type``h]j)}(hj_0h]hreg_type}(hja0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]0ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjY0ubj)}(hhh]j])}(hsee enum cxl_regloc_typeh]hsee enum cxl_regloc_type}(hjx0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjt0hMhju0ubah}(h]h ]h"]h$]h&]uh1jhjY0ubeh}(h]h ]h"]h$]h&]uh1jshjt0hMhjd/ubjt)}(h``{unnamed_union}`` anonymous h](jz)}(h``{unnamed_union}``h]j)}(hj0h]h{unnamed_union}}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhKhj0ubj)}(hhh]j])}(h anonymoush]h anonymous}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj0hKhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jshj0hKhjd/ubjt)}(h6``component_map`` cxl_reg_map for component registers h](jz)}(h``component_map``h]j)}(hj0h]h component_map}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj0ubj)}(hhh]j])}(h#cxl_reg_map for component registersh]h#cxl_reg_map for component registers}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jshj0hMhjd/ubjt)}(h1``device_map`` cxl_reg_maps for device registers h](jz)}(h``device_map``h]j)}(hj 1h]h device_map}(hj 1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj1ubj)}(hhh]j])}(h!cxl_reg_maps for device registersh]h!cxl_reg_maps for device registers}(hj#1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj1hMhj 1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jshj1hMhjd/ubjt)}(h=``pmu_map`` cxl_reg_maps for CXL Performance Monitoring Unitsh](jz)}(h ``pmu_map``h]j)}(hjC1h]hpmu_map}(hjE1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA1ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj=1ubj)}(hhh]j])}(h1cxl_reg_maps for CXL Performance Monitoring Unitsh]h1cxl_reg_maps for CXL Performance Monitoring Units}(hj\1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjY1ubah}(h]h ]h"]h$]h&]uh1jhj=1ubeh}(h]h ]h"]h$]h&]uh1jshjX1hMhjd/ubeh}(h]h ]h"]h$]h&]uh1jnhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder (C struct) c.cxl_decoderhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h cxl_decoderh]j.)}(hstruct cxl_decoderh](j)}(hjh]hstruct}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF)}(h h]h }(hj1hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj1hhhj1hMubjW)}(h cxl_decoderh]j])}(hj1h]h cxl_decoder}(hj1hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj1ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj1hhhj1hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj1hhhj1hMubah}(h]j1ah ](jjeh"]h$]h&]jj)jhuh1j'hj1hMhj1hhubj)}(hhh]j])}(h!Common CXL HDM Decoder Attributesh]h!Common CXL HDM Decoder Attributes}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM^hj1hhubah}(h]h ]h"]h$]h&]uh1jhj1hhhj1hMubeh}(h]h ](jstructeh"]h$]h&]jjjj1jj1jjjuh1j"hhhj.hNhNubj)}(hX**Definition**:: struct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); }; **Members** ``dev`` this decoder's device ``id`` kernel device name id ``hpa_range`` Host physical address range mapped by this decoder ``interleave_ways`` number of cxl_dports in this decode ``interleave_granularity`` data stride per dport ``target_type`` accelerator vs expander (type2 vs type3) selector ``region`` currently assigned region for this decoder ``flags`` memory type capabilities and locking ``commit`` device/decoder-type specific callback to commit settings to hw ``reset`` device/decoder-type specific callback to reset hw settingsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh:}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMbhj1ubj)}(hXHstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };h]hXHstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };}hj2sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMdhj1ubj])}(h **Members**h]j)}(hj-2h]hMembers}(hj/2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+2ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMqhj1ubjo)}(hhh](jt)}(h``dev`` this decoder's device h](jz)}(h``dev``h]j)}(hjL2h]hdev}(hjN2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ2ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM`hjF2ubj)}(hhh]j])}(hthis decoder's deviceh]hthis decoder’s device}(hje2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hja2hM`hjb2ubah}(h]h ]h"]h$]h&]uh1jhjF2ubeh}(h]h ]h"]h$]h&]uh1jshja2hM`hjC2ubjt)}(h``id`` kernel device name id h](jz)}(h``id``h]j)}(hj2h]hid}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMahj2ubj)}(hhh]j])}(hkernel device name idh]hkernel device name id}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj2hMahj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jshj2hMahjC2ubjt)}(hA``hpa_range`` Host physical address range mapped by this decoder h](jz)}(h ``hpa_range``h]j)e}(hj2h]h hpa_range}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMbhj2ubj)}(hhh]j])}(h2Host physical address range mapped by this decoderh]h2Host physical address range mapped by this decoder}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj2hMbhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jshj2hMbhjC2ubjt)}(h8``interleave_ways`` number of cxl_dports in this decode h](jz)}(h``interleave_ways``h]j)}(hj2h]hinterleave_ways}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMchj2ubj)}(hhh]j])}(h#number of cxl_dports in this decodeh]h#number of cxl_dports in this decode}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj 3hMchj 3ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jshj 3hMchjC2ubjt)}(h1``interleave_granularity`` data stride per dport h](jz)}(h``interleave_granularity``h]j)}(hj03h]hinterleave_granularity}(hj23hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.3ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMdhj*3ubj)}(hhh]j])}(hdata stride per dporth]hdata stride per dport}(hjI3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjE3hMdhjF3ubah}(h]h ]h"]h$]h&]uh1jhj*3ubeh}(h]h ]h"]h$]h&]uh1jshjE3hMdhjC2ubjt)}(hB``target_type`` accelerator vs expander (type2 vs type3) selector h](jz)}(h``target_type``h]j)}(hji3h]h target_type}(hjk3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjg3ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMehjc3ubj)}(hhh]j])}(h1accelerator vs expander (type2 vs type3) selectorh]h1accelerator vs expander (type2 vs type3) selector}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj~3hMehj3ubah}(h]h ]h"]h$]h&]uh1jhjc3ubeh}(h]h ]h"]h$]h&]uh1jshj~3hMehjC2ubjt)}(h6``region`` currently assigned region for this decoder h](jz)}(h ``region``h]j)}(hj3h]hregion}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMfhj3ubj)}(hhh]j])}(h*currently assigned region for this decoderh]h*currently assigned region for this decoder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj3hMfhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jshj3hMfhjC2ubjt)}(h/``flags`` memory type capabilities and locking h](jz)}(h ``flags``h]j)}(hj3h]hflags}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMghj3ubj)}(hhh]j])}(h$memory type capabilities and lockingh]h$memory type capabilities and locking}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj3hMghj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jshj3hMghjC2ubjt)}(hJ``commit`` device/decoder-type specific callback to commit settings to hw h](jz)}(h ``commit``h]j)}(hj4h]hcommit}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhhj4ubj)}(hhh]j])}(h>device/decoder-type specific callback to commit settings to hwh]h>device/decoder-type specific callback to commit settings to hw}(hj-4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj)4hMhhj*4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jshj)4hMhhjC2ubjt)}(hD``reset`` device/decoder-type specific callback to reset hw settingsh](jz)}(h ``reset``h]j)}(hjM4h]hreset}(hjO4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK4ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhhjG4ubj)}(hhh]j])}(h:device/decoder-type specific callback to reset hw settingsh]h:device/decoder-type specific callback to reset hw settings}(hjf4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMihjc4ubah}(h]h ]h"]h$]h&]uh1jhjG4ubeh}(h]h ]h"]h$]h&]uh1jshjb4hMhhjC2ubeh}(h]h ]h"]h$]h&]uh1jnhj1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_endpoint_decoder (C struct)c.cxl_endpoint_decoderhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_endpoint_decoderh]j.)}(hstruct cxl_endpoint_decoderh](j)}(hjh]hstruct}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMoubjF)}(h h]h }(hj4hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj4hhhj4hMoubjW)}(hcxl_endpoint_decoderh]j])}(hj4h]hcxl_endpoint_decoder}(hj4hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj4ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj4hhhj4hMoubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj4hhhj4hMoubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1j'hj4hMohj4hhubj)}(hhh]j])}(hEndpoint / SPA to DPA decoderh]hEndpoint / SPA to DPA decoder}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4hhubah}(h]h ]h"]h$]h&]uh1jhj4hhhj4hMoubeh}(h]h ](jstructeh"]h$]h&]jjjj5jj5jjjuh1j"hhhj.hNhNubj)}(hX**Definition**:: struct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; }; **Members** ``cxld`` base cxl_decoder_object ``dpa_res`` actively claimed DPA span of this decoder ``skip`` offset into **dpa_res** where **cxld.hpa_range** maps ``state`` autodiscovery state ``part`` partition index this decoder maps ``pos`` interleave position in **cxld.region**h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj 5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 5ubh:}(hj 5hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };h]hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };}hj&5sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj])}(h **Members**h]j)}(hj75h]hMembers}(hj95hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj55ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubjo)}(hhh](jt)}(h!``cxld`` base cxl_decoder_object h](jz)}(h``cxld``h]j)}(hjV5h]hcxld}(hjX5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT5ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjP5ubj)}(hhh]j])}(hbase cxl_decoder_objecth]hbase cxl_decoder_object}(hjo5hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjk5hMhjl5ubah}(h]h ]h"]h$]h&]uh1jhjP5ubeh}(h]h ]h"]h$]h&]uh1jshjk5hMhjM5ubjt)}(h6``dpa_res`` actively claimed DPA span of this decoder h](jz)}(h ``dpa_res``h]j)}(hj5h]hdpa_res}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]j])}(h)actively claimed DPA span of this decoderh]h)actively claimed DPA span of this decoder}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshj5hMhjM5ubjt)}(h?``skip`` offset into **dpa_res** where **cxld.hpa_range** maps h](jz)}(h``skip``h]j)}(hj5h]hskip}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]j])}(h5offset into **dpa_res** where **cxld.hpa_range** mapsh](h offset into }(hj5hhhNhNubj)}(h **dpa_res**h]hdpa_res}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh where }(hj5hhhNhNubj)}(h**cxld.hpa_range**h]hcxld.hpa_range}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh maps}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshj5hMhjM5ubjt)}(h``state`` autodiscovery state h](jz)}(h ``state``h]j)}(hj%6h]hstate}(hj'6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#6ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6ubj)}(hhh]j])}(hautodiscovery stateh]hautodiscovery state}(hj>6hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:6hMhj;6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jshj:6hMhjM5ubjt)}(h+``part`` partition index this decoder maps h](jz)}(h``part``h]j)}(hj^6h]hpart}(hj`6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\6ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjX6ubj)}(hhh]j])}(h!partition index this decoder mapsh]h!partition index this decoder maps}(hjw6hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjs6hMhjt6ubah}(h]h ]h"]h$]h&]uh1jhjX6ubeh}(h]h ]h"]h$]h&]uh1jshjs6hMhjM5ubjt)}(h.``pos`` interleave position in **cxld.region**h](jz)}(h``pos``h]j)}(hj6h]hpos}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6ubj)}(hhh]j])}(h&interleave position in **cxld.region**h](hinterleave position in }(hj6hhhNhNubj)}(h**cxld.region**h]h cxld.region}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jshj6hMhjM5ubeh}(h]h ]h"]h$]h&]uh1jnhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_switch_decoder (C struct)c.cxl_switch_decoderhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_switch_decoderh]j.)}(hstruct cxl_switch_decoderh](j)}(hjh]hstruct}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF)}(h h]h }(hj 7hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj6hhhj 7hMubjW)}(hcxl_switch_decoderh]j])}(hj6h]hcxl_switch_decoder}(hj7hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj7ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj6hhhj 7hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj6hhhj 7hMubah}(h]j6ah ](jjeh"]h$]h&]jj)jhuh1j'hj 7hMhj6hhubj)}(hhh]j])}(hSwitch specific CXL HDM Decoderh]hSwitch specific CXL HDM Decoder}(hjA7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj>7hhubah}(h]h ]h"]h$]h&]uh1jhj6hhhj 7hMubeh}(h]h ](jstructeh"]h$]h&]jjjjY7jjY7jjjuh1j"hhhj.hNhNubj)}(hX9**Definition**:: struct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; }; **Members** ``cxld`` base cxl_decoder object ``nr_targets`` number of elements in **target** ``target`` active ordered target list in current decoder configurationh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hje7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja7ubh:}(hja7hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj]7ubj)}(hostruct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };h]hostruct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };}hj~7sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj]7ubj])}(h **Members**h]j)}(hj7h]hMembers}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj]7ubjo)}(hhh](jt)}(h!``cxld`` base cxl_decoder object h](jz)}(h``cxld``h]j)}(hj7h]hcxld}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj7ubj)}(hhh]j])}(hbase cxl_decoder objecth]hbase cxl_decoder object}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jshj7hMhj7ubjt)}(h0``nr_targets`` number of elements in **target** h](jz)}(h``nr_targets``h]j)}(hj7h]h nr_targets}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj7ubj)}(hhh]j])}(h number of elements in **target**h](hnumber of elements in }(hj8hhhNhNubj)}(h **target**h]htarget}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1j\hj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jshj7hMhj7ubjt)}(hF``target`` active ordered target list in current decoder configurationh](jz)}(h ``target``h]j)}(hj.8h]htarget}(hj08hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,8ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(8ubj)}(hhh]j])}(h;active ordered target list in current decoder configurationh]h;active ordered target list in current decoder configuration}(hjG8hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjD8ubah}(h]h ]h"]h$]h&]uh1jhj(8ubeh}(h]h ]h"]h$]h&]uh1jshjC8hMhj7ubeh}(h]h ]h"]h$]h&]uh1jnhj]7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(h**Description**h]j)}(hjq8h]h Description}(hjs8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo8ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.hhubj])}(hXTThe 'switch' decoder type represents the decoder instances of cxl_port's that route from the root of a CXL memory decode topology to the endpoints. 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They come in two flavors, root-level decoders, statically defined by platform firmware, and mid-level decoders, where interleave-granularity, interleave-width, and the target list are mutable.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_root_decoder (C struct)c.cxl_root_decoderhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_root_decoderh]j.)}(hstruct cxl_root_decoderh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF)}(h h]h }(hj8hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj8hhhj8hMubjW)}(hcxl_root_decoderh]j])}(hj8h]hcxl_root_decoder}(hj8hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj8ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj8hhhj8hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj8hhhj8hMubah}(h]j8ah ](jjeh"]h$]h&]jj)jhuh1j'hj8hMhj8hhubj)}(hhh]j])}(h#Static platform CXL address decoderh]h#Static platform CXL address decoder}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8hhubah}(h]h ]h"]h$]h&]uh1jhj8hhhj8hMubeh}(h]h ](jstructeh"]h$]h&]jjjj 9jj 9jjjuh1j"hhhj.hNhNubj)}(hX**Definition**:: struct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; }; **Members** ``res`` host / parent resource for region allocations ``region_id`` region id for next region provisioning event ``hpa_to_spa`` translate CXL host-physical-address to Platform system-physical-address ``platform_data`` platform specific configuration data ``range_lock`` sync region autodiscovery by address range ``qos_class`` QoS performance class cookie ``cxlsd`` base cxl switch decoderh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh:}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj 9ubj)}(hstruct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; };h]hstruct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; };}hj.9sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj 9ubj])}(h **Members**h]j)}(hj?9h]hMembers}(hjA9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=9ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj 9ubjo)}(hhh](jt)}(h6``res`` host / parent resource for region allocations h](jz)}(h``res``h]j)}(hj^9h]hres}(hj`9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\9ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjX9ubj)}(hhh]j])}(h-host / parent resource for region allocationsh]h-host / parent resource for region allocations}(hjw9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjs9hMhjt9ubah}(h]h ]h"]h$]h&]uh1jhjX9ubeh}(h]h ]h"]h$]h&]uh1jshjs9hMhjU9ubjt)}(h;``region_id`` region id for next region provisioning event h](jz)}(h ``region_id``h]j)}(hj9h]h region_id}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]j])}(h,region id for next region provisioning eventh]h,region id for next region provisioning event}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshj9hMhjU9ubjt)}(hW``hpa_to_spa`` translate CXL host-physical-address to Platform system-physical-address h](jz)}(h``hpa_to_spa``h]j)}(hj9h]h hpa_to_spa}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]j])}(hGtranslate CXL host-physical-address to Platform system-physical-addressh]hGtranslate CXL host-physical-address to Platform system-physical-address}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshj9hMhjU9ubjt)}(h7``platform_data`` platform specific configuration data h](jz)}(h``platform_data``h]j)}(hj :h]h platform_data}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]j])}(h$platform specific configuration datah]h$platform specific configuration data}(hj":hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jshj:hMhjU9ubjt)}(h:``range_lock`` sync region autodiscovery by address range h](jz)}(h``range_lock``h]j)}(hjB:h]h range_lock}(hjD:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@:ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj<:ubj)}(hhh]j])}(h*sync region autodiscovery by address rangeh]h*sync region autodiscovery by address range}(hj[:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjW:hMhjX:ubah}(h]h ]h"]h$]h&]uh1jhj<:ubeh}(h]h ]h"]h$]h&]uh1jshjW:hMhjU9ubjt)}(h+``qos_class`` QoS performance class cookie h](jz)}(h ``qos_class``h]j)}(hj{:h]h qos_class}(hj}:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy:ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhju:ubj)}(hhh]j])}(hQoS performance class cookieh]hQoS performance class cookie}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhju:ubeh}(h]h ]h"]h$]h&]uh1jshj:hMhjU9ubjt)}(h!``cxlsd`` base cxl switch decoderh](jz)}(h ``cxlsd``h]j)}(hj:h]hcxlsd}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]j])}(hbase cxl switch decoderh]hbase cxl switch decoder}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jshj:hMhjU9ubeh}(h]h ]h"]h$]h&]uh1jnhj 9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_region_params (C struct)c.cxl_region_paramshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_region_paramsh]j.)}(hstruct cxl_region_paramsh](j)}(hjh]hstruct}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ;hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF)}(h h]h }(hj;hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj ;hhhj;hMubjW)}(hcxl_region_paramsh]j])}(hj;h]hcxl_region_params}(hj.;hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj*;ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj ;hhhj;hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj;hhhj;hMubah}(h]j;ah ](jjeh"]h$]h&]jj)jhuh1j'hj;hMhj;hhubj)}(hhh]j])}(hregion settingsh]hregion settings}(hjP;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjM;hhubah}(h]h ]h"]h$]h&]uh1jhj;hhhj;hMubeh}(h]h ](jstructeh"]h$]h&]jjjjh;jjh;jjjuh1j"hhhj.hNhNubj)}(hX-**Definition**:: struct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; }; **Members** ``state`` allow the driver to lockdown further parameter changes ``uuid`` unique id for persistent regions ``interleave_ways`` number of endpoints in the region ``interleave_granularity`` capacity each endpoint contributes to a stripe ``res`` allocated iomem capacity for this region ``targets`` active ordered targets in current decoder configuration ``nr_targets`` number of targets ``cache_size`` extended linear cache size if exists, otherwise zero.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjt;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjp;ubh:}(hjp;hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjl;ubj)}(hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };h]hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };}hj;sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjl;ubj])}(h **Members**h]j)}(hj;h]hMembers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjl;ubjo)}(hhh](jt)}(hA``state`` allow the driver to lockdown further parameter changes h](jz)}(h ``state``h]j)}(hj;h]hstate}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]j])}(h6allow the driver to lockdown further parameter changesh]h6allow the driver to lockdown further parameter changes}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jshj;hMhj;ubjt)}(h*``uuid`` unique id for persistent regions h](jz)}(h``uuid``h]j)}(hj;h]huuid}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]j])}(h unique id for persistent regionsh]h unique id for persistent regions}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj <hMhj <ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jshj <hMhj;ubjt)}(h6``interleave_ways`` number of endpoints in the region h](jz)}(h``interleave_ways``h]j)}(hj/<h]hinterleave_ways}(hj1<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-<ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj)<ubj)}(hhh]j])}(h!number of endpoints in the regionh]h!number of endpoints in the region}(hjH<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjD<hMhjE<ubah}(h]h ]h"]h$]h&]uh1jhj)<ubeh}(h]h ]h"]h$]h&]uh1jshjD<hMhj;ubjt)}(hJ``interleave_granularity`` capacity each endpoint contributes to a stripe h](jz)}(h``interleave_granularity``h]j)}(hjh<h]hinterleave_granularity}(hjj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf<ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjb<ubj)}(hhh]j])}(h.capacity each endpoint contributes to a stripeh]h.capacity each endpoint contributes to a stripe}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj}<hMhj~<ubah}(h]h ]h"]h$]h&]uh1jhjb<ubeh}(h]h ]h"]h$]h&]uh1jshj}<hMhj;ubjt)}(h1``res`` allocated iomem capacity for this region h](jz)}(h``res``h]j)}(hj<h]hres}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj<ubj)}(hhh]j])}(h(allocated iomem capacity for this regionh]h(allocated iomem capacity for this region}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jshj<hMhj;ubjt)}(hD``targets`` active ordered targets in current decoder configuration h](jz)}(h ``targets``h]j)}(hj<h]htargets}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj<ubj)}(hhh]j])}(h7active ordered targets in current decoder configurationh]h7active ordered targets in current decoder configuration}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jshj<hMhj;ubjt)}(h!``nr_targets`` number of targets h](jz)}(h``nr_targets``h]j)}(hj=h]h nr_targets}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj =ubj)}(hhh]j])}(hnumber of targetsh]hnumber of targets}(hj,=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj(=hMhj)=ubah}(h]h ]h"]h$]h&]uh1jhj =ubeh}(h]h ]h"]h$]h&]uh1jshj(=hMhj;ubjt)}(hD``cache_size`` extended linear cache size if exists, otherwise zero.h](jz)}(h``cache_size``h]j)}(hjL=h]h cache_size}(hjN=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJ=ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjF=ubj)}(hhh]j])}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hje=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjb=ubah}(h]h ]h"]h$]h&]uh1jhjF=ubeh}(h]h ]h"]h$]h&]uh1jshja=hMhj;ubeh}(h]h ]h"]h$]h&]uh1jnhjl;ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(h**Description**h]j)}(hj=h]h Description}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.hhubj])}(h7State transitions are protected by the cxl_region_rwsemh]h7State transitions are protected by the cxl_region_rwsem}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_region (C struct) c.cxl_regionhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h cxl_regionh]j.)}(hstruct cxl_regionh](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF)}(h h]h }(hj=hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj=hhhj=hMubjW)}(h cxl_regionh]j])}(hj=h]h cxl_region}(hj=hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj=ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj=hhhj=hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj=hhhj=hMubah}(h]j=ah ](jjeh"]h$]h&]jj)jhuh1j'hj=hMhj=hhubj)}(hhh]j])}(h CXL regionh]h CXL region}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj >hhubah}(h]h ]h"]h$]h&]uh1jhj=hhhj=hMubeh}(h]h ](jstructeh"]h$]h&]jjjj'>jj'>jjjuh1j"hhhj.hNhNubj)}(hXC**Definition**:: struct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; }; **Members** ``dev`` This region's device ``id`` This region's id. Id is globally unique across all regions ``mode`` Operational mode of the mapped capacity ``type`` Endpoint decoder target type ``cxl_nvb`` nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown ``cxlr_pmem`` (for pmem regions) cached copy of the nvdimm bridge ``flags`` Region state flags ``params`` active + config params for the region ``coord`` QoS access coordinates for the region ``memory_notifier`` notifier for setting the access coordinates to node ``adist_notifier`` notifier for calculating the abstract distance of nodeh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj3>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/>ubh:}(hj/>hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj+>ubj)}(hXstruct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; };h]hXstruct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; };}hjL>sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj+>ubj])}(h **Members**h]j)}(hj]>h]hMembers}(hj_>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[>ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj+>ubjo)}(hhh](jt)}(h``dev`` This region's device h](jz)}(h``dev``h]j)}(hj|>h]hdev}(hj~>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz>ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjv>ubj)}(hhh]j])}(hThis region's deviceh]hThis region’s device}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhjv>ubeh}(h]h ]h"]h$]h&]uh1jshj>hMhjs>ubjt)}(hB``id`` This region's id. Id is globally unique across all regions h](jz)}(h``id``h]j)}(hj>h]hid}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj>ubj)}(hhh]j])}(h:This region's id. Id is globally unique across all regionsh]hhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshj>hMhjs>ubjt)}(h1``mode`` Operational mode of the mapped capacity h](jz)}(h``mode``h]j)}(hj>h]hmode}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj>ubj)}(hhh]j])}(h'Operational mode of the mapped capacityh]h'Operational mode of the mapped capacity}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhjs>ubjt)}(h&``type`` Endpoint decoder target type h](jz)}(h``type``h]j)}(hj'?h]htype}(hj)?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%?ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj!?ubj)}(hhh]j])}(hEndpoint decoder target typeh]hEndpoint decoder target type}(hj@?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjubjt)}(hJ``cxl_nvb`` nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown h](jz)}(h ``cxl_nvb``h]j)}(hj`?h]hcxl_nvb}(hjb?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^?ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjZ?ubj)}(hhh]j])}(h=nvdimm bridge for coordinating **cxlr_pmem** setup / shutdownh](hnvdimm bridge for coordinating }(hjy?hhhNhNubj)}(h **cxlr_pmem**h]h cxlr_pmem}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy?ubh setup / shutdown}(hjy?hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hju?hMhjv?ubah}(h]h ]h"]h$]h&]uh1jhjZ?ubeh}(h]h ]h"]h$]h&]uh1jshju?hMhjs>ubjt)}(hB``cxlr_pmem`` (for pmem regions) cached copy of the nvdimm bridge h](jz)}(h ``cxlr_pmem``h]j)}(hj?h]h cxlr_pmem}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj?ubj)}(hhh]j])}(h3(for pmem regions) cached copy of the nvdimm bridgeh]h3(for pmem regions) cached copy of the nvdimm bridge}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhjs>ubjt)}(h``flags`` Region state flags h](jz)}(h ``flags``h]j)}(hj?h]hflags}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj?ubj)}(hhh]j])}(hRegion state flagsh]hRegion state flags}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhjs>ubjt)}(h1``params`` active + config params for the region h](jz)}(h ``params``h]j)}(hj@h]hparams}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ubj)}(hhh]j])}(h%active + config params for the regionh]h%active + config params for the region}(hj6@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj2@hMhj3@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jshj2@hMhjs>ubjt)}(h0``coord`` QoS access coordinates for the region h](jz)}(h ``coord``h]j)}(hjV@h]hcoord}(hjX@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT@ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjP@ubj)}(hhh]j])}(h%QoS access coordinates for the regionh]h%QoS access coordinates for the region}(hjo@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjk@hMhjl@ubah}(h]h ]h"]h$]h&]uh1jhjP@ubeh}(h]h ]h"]h$]h&]uh1jshjk@hMhjs>ubjt)}(hH``memory_notifier`` notifier for setting the access coordinates to node h](jz)}(h``memory_notifier``h]j)}(hj@h]hmemory_notifier}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ubj)}(hhh]j])}(h3notifier for setting the access coordinates to nodeh]h3notifier for setting the access coordinates to node}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jshj@hMhjs>ubjt)}(hI``adist_notifier`` notifier for calculating the abstract distance of nodeh](jz)}(h``adist_notifier``h]j)}(hj@h]hadist_notifier}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ubj)}(hhh]j])}(h6notifier for calculating the abstract distance of nodeh]h6notifier for calculating the abstract distance of node}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jshj@hMhjs>ubeh}(h]h ]h"]h$]h&]uh1jnhj+>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_port (C struct) c.cxl_porthNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_porth]j.)}(hstruct cxl_porth](j)}(hjh]hstruct}(hj"AhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM ubjF)}(h h]h }(hj0AhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjAhhhj/AhM ubjW)}(hcxl_porth]j])}(hjAh]hcxl_port}(hjBAhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj>Aubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjAhhhj/AhM ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjAhhhj/AhM ubah}(h]jAah ](jjeh"]h$]h&]jj)jhuh1j'hj/AhM hjAhhubj)}(hhh]j])}(hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.h]hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.}(hjdAhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM>hjaAhhubah}(h]h ]h"]h$]h&]uh1jhjAhhhj/AhM ubeh}(h]h ](jstructeh"]h$]h&]jjjj|Ajj|Ajjjuh1j"hhhj.hNhNubj)}(hX**Definition**:: struct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; }; **Members** ``dev`` this port's device ``uport_dev`` PCI or platform device implementing the upstream port capability ``host_bridge`` Shortcut to the platform attach point for this port ``id`` id for port device-name ``dports`` cxl_dport instances referenced by decoders ``endpoints`` cxl_ep instances, endpoints that are a descendant of this port ``regions`` cxl_region_ref instances, regions mapped by this port ``parent_dport`` dport that points to this port in the parent ``decoder_ida`` allocator for decoder ids ``reg_map`` component and ras register mapping parameters ``nr_dports`` number of entries in **dports** ``hdm_end`` track last allocated HDM decoder instance for allocation ordering ``commit_end`` cursor to track highest committed decoder for commit ordering ``dead`` last ep has been removed, force port re-creation ``depth`` How deep this port is relative to the root. depth 0 is the root. ``cdat`` Cached CDAT data ``cdat_available`` Should a CDAT attribute be available in sysfs ``pci_latency`` Upstream latency in picosecondsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh:}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMBhjAubj)}(hXstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; };h]hXstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; };}hjAsbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMDhjAubj])}(h **Members**h]j)}(hjAh]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM\hjAubjo)}(hhh](jt)}(h``dev`` this port's device h](jz)}(h``dev``h]j)}(hjAh]hdev}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMBhjAubj)}(hhh]j])}(hthis port's deviceh]hthis port’s device}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjAhMBhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshjAhMBhjAubjt)}(hO``uport_dev`` PCI or platform device implementing the upstream port capability h](jz)}(h ``uport_dev``h]j)}(hj Bh]h uport_dev}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMChjBubj)}(hhh]j])}(h@PCI or platform device implementing the upstream port capabilityh]h@PCI or platform device implementing the upstream port capability}(hj#BhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjBhMChj Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjBhMChjAubjt)}(hD``host_bridge`` Shortcut to the platform attach point for this port h](jz)}(h``host_bridge``h]j)}(hjCBh]h host_bridge}(hjEBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjABubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMDhj=Bubj)}(hhh]j])}(h3Shortcut to the platform attach point for this porth]h3Shortcut to the platform attach point for this port}(hj\BhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjXBhMDhjYBubah}(h]h ]h"]h$]h&]uh1jhj=Bubeh}(h]h ]h"]h$]h&]uh1jshjXBhMDhjAubjt)}(h``id`` id for port device-name h](jz)}(h``id``h]j)}(hj|Bh]hid}(hj~BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzBubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMEhjvBubj)}(hhh]j])}(hid for port device-nameh]hid for port device-name}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjBhMEhjBubah}(h]h ]h"]h$]h&]uh1jhjvBubeh}(h]h ]h"]h$]h&]uh1jshjBhMEhjAubjt)}(h6``dports`` cxl_dport instances referenced by decoders h](jz)}(h ``dports``h]j)}(hjBh]hdports}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMFhjBubj)}(hhh]j])}(h*cxl_dport instances referenced by decodersh]h*cxl_dport instances referenced by decoders}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjBhMFhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjBhMFhjAubjt)}(hM``endpoints`` cxl_ep instances, endpoints that are a descendant of this port h](jz)}(h ``endpoints``h]j)}(hjBh]h endpoints}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMGhjBubj)}(hhh]j])}(h>cxl_ep instances, endpoints that are a descendant of this porth]h>cxl_ep instances, endpoints that are a descendant of this port}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjChMGhjCubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjChMGhjAubjt)}(hB``regions`` cxl_region_ref instances, regions mapped by this port h](jz)}(h ``regions``h]j)}(hj'Ch]hregions}(hj)ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%Cubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMHhj!Cubj)}(hhh]j])}(h5cxl_region_ref instances, regions mapped by this porth]h5cxl_region_ref instances, regions mapped by this port}(hj@ChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj``parent_dport`` dport that points to this port in the parent h](jz)}(h``parent_dport``h]j)}(hj`Ch]h parent_dport}(hjbChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Cubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMIhjZCubj)}(hhh]j])}(h,dport that points to this port in the parenth]h,dport that points to this port in the parent}(hjyChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjuChMIhjvCubah}(h]h ]h"]h$]h&]uh1jhjZCubeh}(h]h ]h"]h$]h&]uh1jshjuChMIhjAubjt)}(h*``decoder_ida`` allocator for decoder ids h](jz)}(h``decoder_ida``h]j)}(hjCh]h decoder_ida}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMJhjCubj)}(hhh]j])}(hallocator for decoder idsh]hallocator for decoder ids}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjChMJhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jshjChMJhjAubjt)}(h:``reg_map`` component and ras register mapping parameters h](jz)}(h ``reg_map``h]j)}(hjCh]hreg_map}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMKhjCubj)}(hhh]j])}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjChMKhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jshjChMKhjAubjt)}(h.``nr_dports`` number of entries in **dports** h](jz)}(h ``nr_dports``h]j)}(hj Dh]h nr_dports}(hj DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Dubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhjDubj)}(hhh]j])}(hnumber of entries in **dports**h](hnumber of entries in }(hj$DhhhNhNubj)}(h **dports**h]hdports}(hj,DhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$Dubeh}(h]h ]h"]h$]h&]uh1j\hj DhMLhj!Dubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshj DhMLhjAubjt)}(hN``hdm_end`` track last allocated HDM decoder instance for allocation ordering h](jz)}(h ``hdm_end``h]j)}(hjRDh]hhdm_end}(hjTDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPDubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMMhjLDubj)}(hhh]j])}(hAtrack last allocated HDM decoder instance for allocation orderingh]hAtrack last allocated HDM decoder instance for allocation ordering}(hjkDhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjgDhMMhjhDubah}(h]h ]h"]h$]h&]uh1jhjLDubeh}(h]h ]h"]h$]h&]uh1jshjgDhMMhjAubjt)}(hM``commit_end`` cursor to track highest committed decoder for commit ordering h](jz)}(h``commit_end``h]j)}(hjDh]h commit_end}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMNhjDubj)}(hhh]j])}(h=cursor to track highest committed decoder for commit orderingh]h=cursor to track highest committed decoder for commit ordering}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjDhMNhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshjDhMNhjAubjt)}(h:``dead`` last ep has been removed, force port re-creation h](jz)}(h``dead``h]j)}(hjDh]hdead}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMOhjDubj)}(hhh]j])}(h0last ep has been removed, force port re-creationh]h0last ep has been removed, force port re-creation}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjDhMOhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshjDhMOhjAubjt)}(hK``depth`` How deep this port is relative to the root. depth 0 is the root. h](jz)}(h ``depth``h]j)}(hjDh]hdepth}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMPhjDubj)}(hhh]j])}(h@How deep this port is relative to the root. depth 0 is the root.h]h@How deep this port is relative to the root. depth 0 is the root.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjEhMPhjEubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshjEhMPhjAubjt)}(h``cdat`` Cached CDAT data h](jz)}(h``cdat``h]j)}(hj6Eh]hcdat}(hj8EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4Eubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hXhMQhj0Eubj)}(hhh]j])}(hCached CDAT datah]hCached CDAT data}(hjOEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjKEhMQhjLEubah}(h]h ]h"]h$]h&]uh1jhj0Eubeh}(h]h ]h"]h$]h&]uh1jshjKEhMQhjAubjt)}(hA``cdat_available`` Should a CDAT attribute be available in sysfs h](jz)}(h``cdat_available``h]j)}(hjoEh]hcdat_available}(hjqEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmEubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMRhjiEubj)}(hhh]j])}(h-Should a CDAT attribute be available in sysfsh]h-Should a CDAT attribute be available in sysfs}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjEhMRhjEubah}(h]h ]h"]h$]h&]uh1jhjiEubeh}(h]h ]h"]h$]h&]uh1jshjEhMRhjAubjt)}(h/``pci_latency`` Upstream latency in picosecondsh](jz)}(h``pci_latency``h]j)}(hjEh]h pci_latency}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMRhjEubj)}(hhh]j])}(hUpstream latency in picosecondsh]hUpstream latency in picoseconds}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMShjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jshjEhMRhjAubeh}(h]h ]h"]h$]h&]uh1jnhjAubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_root (C struct) c.cxl_roothNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcxl_rooth]j.)}(hstruct cxl_rooth](j)}(hjh]hstruct}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMYubjF)}(h h]h }(hjFhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjEhhhjFhMYubjW)}(hcxl_rooth]j])}(hjEh]hcxl_root}(hj"FhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjFubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjEhhhjFhMYubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjEhhhjFhMYubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1j'hjFhMYhjEhhubj)}(hhh]j])}(h)logical collection of root cxl_port itemsh]h)logical collection of root cxl_port items}(hjDFhhhNhNubah}(h]h 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cxl_endpoint_dvsec_info { bool mem_enabled; int ranges; struct cxl_port *port; struct range dvsec_range[2]; };h]hstruct cxl_endpoint_dvsec_info { bool mem_enabled; int ranges; struct cxl_port *port; struct range dvsec_range[2]; };}hjOsbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjNubj])}(h **Members**h]j)}(hj!Oh]hMembers}(hj#OhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM&hjNubjo)}(hhh](jt)}(hF``mem_enabled`` cached value of mem_enabled in the DVSEC at init time h](jz)}(h``mem_enabled``h]j)}(hj@Oh]h mem_enabled}(hjBOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>Oubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:Oubj)}(hhh]j])}(h5cached value of mem_enabled in the DVSEC at init timeh]h5cached value of mem_enabled in the DVSEC at init time}(hjYOhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjUOhMhjVOubah}(h]h ]h"]h$]h&]uh1jhj:Oubeh}(h]h ]h"]h$]h&]uh1jshjUOhMhj7Oubjt)}(h9``ranges`` Number of active HDM ranges this device uses. h](jz)}(h ``ranges``h]j)}(hjyOh]hranges}(hj{OhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwOubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjsOubj)}(hhh]j])}(h-Number of active HDM ranges this device uses.h]h-Number of active HDM ranges this device uses.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjOhMhjOubah}(h]h ]h"]h$]h&]uh1jhjsOubeh}(h]h ]h"]h$]h&]uh1jshjOhMhj7Oubjt)}(h:``port`` endpoint port associated with this info instance h](jz)}(h``port``h]j)}(hjOh]hport}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjOubj)}(hhh]j])}(h0endpoint port associated with this info instanceh]h0endpoint port associated with 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]jiah"]h$]h&]uh1j\hj~Pubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjzPubah}(h]h ]h"]h$]h&]hhuh1juhjAPhhhjSPhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj=PhhhjSPhMubah}(h]j8Pah ](jjeh"]h$]h&]jj)jhuh1j'hjSPhMhj:Phhubj)}(hhh]j])}(h2reflect CXL fixed memory windows in iomem_resourceh]h2reflect CXL fixed memory windows in iomem_resource}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhjQhhubah}(h]h ]h"]h$]h&]uh1jhj:PhhhjSPhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjQjjQjjjuh1j"hhhj.hNhNubj)}(hXj**Parameters** ``struct resource *cxl_res`` A standalone resource tree where each CXL window is a sibling **Description** Walk each CXL window in **cxl_res** and add it to iomem_resource potentially expanding its boundaries to ensure that any conflicting resources become children. If a window is expanded it may then conflict with a another window entry and require the window to be truncated or trimmed. Consider this situation:: |-- "CXL Window 0" --||----- "CXL Window 1" -----| |--------------- "System RAM" -------------| ...where platform firmware has established as System RAM resource across 2 windows, but has left some portion of window 1 for dynamic CXL region provisioning. In this case "Window 0" will span the entirety of the "System RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end of that "System RAM" resource.h](j])}(h**Parameters**h]j)}(hj'Qh]h Parameters}(hj)QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%Qubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj!Qubjo)}(hhh]jt)}(h[``struct resource *cxl_res`` A standalone resource tree where each CXL window is a sibling h](jz)}(h``struct resource *cxl_res``h]j)}(hjFQh]hstruct resource *cxl_res}(hjHQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDQubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj@Qubj)}(hhh]j])}(h=A standalone resource tree where each CXL window is a siblingh]h=A standalone resource tree where each CXL window is a sibling}(hj_QhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj[QhMhj\Qubah}(h]h ]h"]h$]h&]uh1jhj@Qubeh}(h]h ]h"]h$]h&]uh1jshj[QhMhj=Qubah}(h]h ]h"]h$]h&]uh1jnhj!Qubj])}(h**Description**h]j)}(hjQh]h Description}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj!Qubj])}(hX5Walk each CXL window in **cxl_res** and add it to iomem_resource potentially expanding its boundaries to ensure that any conflicting resources become children. If a window is expanded it may then conflict with a another window entry and require the window to be truncated or trimmed. Consider this situation::h](hWalk each CXL window in }(hjQhhhNhNubj)}(h **cxl_res**h]hcxl_res}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubhX and add it to iomem_resource potentially expanding its boundaries to ensure that any conflicting resources become children. If a window is expanded it may then conflict with a another window entry and require the window to be truncated or trimmed. Consider this situation:}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj!Qubj)}(h_|-- "CXL Window 0" --||----- "CXL Window 1" -----| |--------------- "System RAM" -------------|h]h_|-- "CXL Window 0" --||----- "CXL Window 1" -----| |--------------- "System RAM" -------------|}hjQsbah}(h]h ]h"]h$]h&]hhuh1jhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj!Qubj])}(hXI...where platform firmware has established as System RAM resource across 2 windows, but has left some portion of window 1 for dynamic CXL region provisioning. In this case "Window 0" will span the entirety of the "System RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end of that "System RAM" resource.h]hXY...where platform firmware has established as System RAM resource across 2 windows, but has left some portion of window 1 for dynamic CXL region provisioning. In this case “Window 0” will span the entirety of the “System RAM” span, and “CXL Window 1” is truncated to the remaining tail past the end of that “System RAM” resource.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:436: ./drivers/cxl/acpi.chMhj!Qubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(hCompute Express Link Host Managed Device Memory, starting with the CXL 2.0 specification, is managed by an array of HDM Decoder register instances per CXL port and per CXL endpoint. Define common helpers for enumerating these registers and capabilities.h]hCompute Express Link Host Managed Device Memory, starting with the CXL 2.0 specification, is managed by an array of HDM Decoder register instances per CXL port and per CXL endpoint. Define common helpers for enumerating these registers and capabilities.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:439: ./drivers/cxl/core/hdm.chK hj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdevm_cxl_setup_hdm (C function)c.devm_cxl_setup_hdmhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hastruct cxl_hdm * devm_cxl_setup_hdm (struct cxl_port *port, struct cxl_endpoint_dvsec_info *info)h]j.)}(h_struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, struct cxl_endpoint_dvsec_info *info)h](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKubjF)}(h h]h }(hjRhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRhhhjRhKubh)}(hhh]j])}(hcxl_hdmh]hcxl_hdm}(hj$RhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj!Rubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&RmodnameN classnameNjj)}j]j)}jdevm_cxl_setup_hdmsbc.devm_cxl_setup_hdmasbuh1hhjRhhhjRhKubjF)}(h h]h }(hjERhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRhhhjRhKubj)}(hjh]h*}(hjSRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRhhhjRhKubjW)}(hdevm_cxl_setup_hdmh]j])}(hjBRh]hdevm_cxl_setup_hdm}(hjdRhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj`Rubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjRhhhjRhKubjv)}(h=(struct cxl_port *port, struct cxl_endpoint_dvsec_info *info)h](j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{RubjF)}(h h]h }(hjRhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj{Rubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjRhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjRmodnameN classnameNjj)}j]j@Rc.devm_cxl_setup_hdmasbuh1hhj{RubjF)}(h h]h }(hjRhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj{Rubj)}(hjh]h*}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{Rubj])}(hporth]hport}(hjRhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj{Rubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjwRubj|)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubjF)}(h h]h }(hjRhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRubh)}(hhh]j])}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hj ShhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj Subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjSmodnameN classnameNjj)}j]j@Rc.devm_cxl_setup_hdmasbuh1hhjRubjF)}(h h]h }(hj+ShhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRubj)}(hjh]h*}(hj9ShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj])}(hinfoh]hinfo}(hjFShhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjRubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjwRubeh}(h]h ]h"]h$]h&]hhuh1juhjRhhhjRhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjQhhhjRhKubah}(h]jQah ](jjeh"]h$]h&]jj)jhuh1j'hjRhKhjQhhubj)}(hhh]j])}(h#map HDM decoder component registersh]h#map HDM decoder component registers}(hjpShhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKhjmShhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjRhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjSjjSjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_port *port`` cxl_port to map ``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](j])}(h**Parameters**h]j)}(hjSh]h Parameters}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKhjSubjo)}(hhh](jt)}(h*``struct cxl_port *port`` cxl_port to map h](jz)}(h``struct cxl_port *port``h]j)}(hjSh]hstruct cxl_port *port}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKhjSubj)}(hhh]j])}(hcxl_port to maph]hcxl_port to map}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjShKhjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jshjShKhjSubjt)}(hI``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](jz)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjSh]h$struct cxl_endpoint_dvsec_info *info}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKhjSubj)}(hhh]j])}(h cached DVSEC range register infoh]h cached DVSEC range register info}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chKhjTubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jshjShKhjSubeh}(h]h ]h"]h$]h&]uh1jnhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jrequest_skip (C function)c.request_skiphNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hint request_skip (struct cxl_dev_state *cxlds, struct cxl_endpoint_decoder *cxled, const resource_size_t skip_base, const resource_size_t skip_len)h]j.)}(hint request_skip(struct cxl_dev_state *cxlds, struct cxl_endpoint_decoder *cxled, const resource_size_t skip_base, const resource_size_t skip_len)h](j4)}(hinth]hint}(hjDThhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj@Thhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM.ubjF)}(h h]h }(hjSThhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj@ThhhjRThM.ubjW)}(h request_skiph]j])}(h request_skiph]h request_skip}(hjeThhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjaTubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj@ThhhjRThM.ubjv)}(h(struct cxl_dev_state *cxlds, struct cxl_endpoint_decoder *cxled, const resource_size_t skip_base, const resource_size_t skip_len)h](j|)}(hstruct cxl_dev_state *cxldsh](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}TubjF)}(h h]h }(hjThhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}Tubh)}(hhh]j])}(h cxl_dev_stateh]h cxl_dev_state}(hjThhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjTubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjTmodnameN classnameNjj)}j]j)}jjgTsbc.request_skipasbuh1hhj}TubjF)}(h h]h }(hjThhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}Tubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}Tubj])}(hcxldsh]hcxlds}(hjThhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj}Tubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyTubj|)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubjF)}(h h]h }(hjUhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjTubh)}(hhh]j])}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]jTc.request_skipasbuh1hhjTubjF)}(h h]h }(hj/UhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjTubj)}(hjh]h*}(hj=UhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj])}(hcxledh]hcxled}(hjJUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjTubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyTubj|)}(hconst resource_size_t skip_baseh](j)}(hconsth]hconst}(hjcUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_UubjF)}(h h]h }(hjqUhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj_Uubh)}(hhh]j])}(hresource_size_th]hresource_size_t}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]jTc.request_skipasbuh1hhj_UubjF)}(h h]h }(hjUhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj_Uubj])}(h skip_baseh]h skip_base}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj_Uubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyTubj|)}(hconst resource_size_t skip_lenh](j)}(hjeUh]hconst}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubjF)}(h h]h }(hjUhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjUubh)}(hhh]j])}(hresource_size_th]hresource_size_t}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjUmodnameN classnameNjj)}j]jTc.request_skipasbuh1hhjUubjF)}(h h]h }(hjVhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjUubj])}(hskip_lenh]hskip_len}(hjVhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjUubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyTubeh}(h]h ]h"]h$]h&]hhuh1juhj@ThhhjRThM.ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjdpa_res** resource treeh](hTrack DPA ‘skip’ in }(hj;VhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjCVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;Vubh resource tree}(hj;VhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM.hj8Vhhubah}(h]h ]h"]h$]h&]uh1jhj9ThhhjRThM.ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjeVjjeVjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** ``struct cxl_endpoint_decoder *cxled`` Endpoint decoder establishing new allocation that skips lower DPA ``const resource_size_t skip_base`` DPA < start of new DPA allocation (DPAnew) ``const resource_size_t skip_len`` **skip_base** + **skip_len** == DPAnew **Description** DPA 'skip' arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. It is a wasteful event as usable DPA gets thrown away, but if a deployment has, for example, a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM DPA, the free RAM DPA must be sacrificed to start allocating PMEM. See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder Protection" for more details. A 'skip' always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation). If **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](j])}(h**Parameters**h]j)}(hjoVh]h Parameters}(hjqVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmVubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM2hjiVubjo)}(hhh](jt)}(hN``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** h](jz)}(h``struct cxl_dev_state *cxlds``h]j)}(hjVh]hstruct cxl_dev_state *cxlds}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM/hjVubj)}(hhh]j])}(h-CXL.mem device context that parents **cxled**h](h$CXL.mem device context that parents }(hjVhhhNhNubj)}(h **cxled**h]hcxled}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j\hjVhM/hjVubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jshjVhM/hjVubjt)}(hi``struct cxl_endpoint_decoder *cxled`` Endpoint decoder establishing new allocation that skips lower DPA h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjVh]h"struct cxl_endpoint_decoder *cxled}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM0hjVubj)}(hhh]j])}(hAEndpoint decoder establishing new allocation that skips lower DPAh]hAEndpoint decoder establishing new allocation that skips lower DPA}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjVhM0hjVubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jshjVhM0hjVubjt)}(hO``const resource_size_t skip_base`` DPA < start of new DPA allocation (DPAnew) h](jz)}(h#``const resource_size_t skip_base``h]j)}(hjWh]hconst resource_size_t skip_base}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Wubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM1hjWubj)}(hhh]j])}(h*DPA < start of new DPA allocation (DPAnew)h]h*DPA < start of new DPA allocation (DPAnew)}(hj'WhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#WhM1hj$Wubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jshj#WhM1hjVubjt)}(hJ``const resource_size_t skip_len`` **skip_base** + **skip_len** == DPAnew h](jz)}(h"``const resource_size_t skip_len``h]j)}(hjGWh]hconst resource_size_t skip_len}(hjIWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEWubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM2hjAWubj)}(hhh]j])}(h&**skip_base** + **skip_len** == DPAnewh](j)}(h **skip_base**h]h skip_base}(hjdWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`Wubh + }(hj`WhhhNhNubj)}(h **skip_len**h]hskip_len}(hjvWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`Wubh == DPAnew}(hj`WhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj\WhM2hj]Wubah}(h]h ]h"]h$]h&]uh1jhjAWubeh}(h]h ]h"]h$]h&]uh1jshj\WhM2hjVubeh}(h]h ]h"]h$]h&]uh1jnhjiVubj])}(h**Description**h]j)}(hjWh]h Description}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM4hjiVubj])}(hXDPA 'skip' arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. It is a wasteful event as usable DPA gets thrown away, but if a deployment has, for example, a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM DPA, the free RAM DPA must be sacrificed to start allocating PMEM. See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder Protection" for more details.h]hXDPA ‘skip’ arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. It is a wasteful event as usable DPA gets thrown away, but if a deployment has, for example, a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM DPA, the free RAM DPA must be sacrificed to start allocating PMEM. See third “Implementation Note” in CXL 3.1 8.2.4.19.13 “Decoder Protection” for more details.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM4hjiVubj])}(hX<A 'skip' always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation).h]hX@A ‘skip’ always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation).}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM<hjiVubj])}(hXuIf **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](hIf }(hjWhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubhf was guaranteed to be <= 2 then the ‘skip’ would always be contained to a single partition. Given }(hjWhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubhX may be > 2 it results in cases where the ‘skip’ might span “tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]” to support allocating from partition[N]. That in turn interacts with the partition ‘struct resource’ boundaries within }(hjWhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh whereby ‘skip’ requests need to be divided by partition. I.e. this is a quirk of using a ‘struct resource’ tree to detect range conflicts while also tracking partition boundaries in }(hjWhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh.}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMBhjiVubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(devm_cxl_enumerate_decoders (C function)c.devm_cxl_enumerate_decodershNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h^int devm_cxl_enumerate_decoders (struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j.)}(h]int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j4)}(hinth]hint}(hjMXhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjIXhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMubjF)}(h h]h }(hj\XhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjIXhhhj[XhMubjW)}(hdevm_cxl_enumerate_decodersh]j])}(hdevm_cxl_enumerate_decodersh]hdevm_cxl_enumerate_decoders}(hjnXhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjjXubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjIXhhhj[XhMubjv)}(h>(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j|)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubjF)}(h h]h }(hjXhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjXubh)}(hhh]j])}(hcxl_hdmh]hcxl_hdm}(hjXhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjXmodnameN classnameNjj)}j]j)}jjpXsbc.devm_cxl_enumerate_decodersasbuh1hhjXubjF)}(h h]h }(hjXhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjXubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj])}(hcxlhdmh]hcxlhdm}(hjXhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjXubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjXubj|)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubjF)}(h h]h }(hj YhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjXubh)}(hhh]j])}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjYhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjYubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjYmodnameN classnameNjj)}j]jXc.devm_cxl_enumerate_decodersasbuh1hhjXubjF)}(h h]h }(hj8YhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjXubj)}(hjh]h*}(hjFYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj])}(hinfoh]hinfo}(hjSYhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjXubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjXubeh}(h]h ]h"]h$]h&]hhuh1juhjIXhhhj[XhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjEXhhhj[XhMubah}(h]j@Xah ](jjeh"]h$]h&]jj)jhuh1j'hj[XhMhjBXhhubj)}(hhh]j])}(h(add decoder objects per HDM register seth]h(add decoder objects per HDM register set}(hj}YhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjzYhhubah}(h]h ]h"]h$]h&]uh1jhjBXhhhj[XhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjYjjYjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_hdm *cxlhdm`` Structure to populate with HDM capabilities ``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](j])}(h**Parameters**h]j)}(hjYh]h Parameters}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjYubjo)}(hhh](jt)}(hG``struct cxl_hdm *cxlhdm`` Structure to populate with HDM capabilities h](jz)}(h``struct cxl_hdm *cxlhdm``h]j)}(hjYh]hstruct cxl_hdm *cxlhdm}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjYubj)}(hhh]j])}(h+Structure to populate with HDM capabilitiesh]h+Structure to populate with HDM capabilities}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjYhMhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jshjYhMhjYubjt)}(hI``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](jz)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjYh]h$struct cxl_endpoint_dvsec_info *info}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjYubj)}(hhh]j])}(h cached DVSEC range register infoh]h cached DVSEC range register info}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhj Zubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jshj ZhMhjYubeh}(h]h ]h"]h$]h&]uh1jnhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$cxl_coordinates_combine (C function)c.cxl_coordinates_combinehNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hxvoid cxl_coordinates_combine (struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h]j.)}(hwvoid cxl_coordinates_combine(struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h](j4)}(hvoidh]hvoid}(hjQZhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjMZhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM"ubjF)}(h h]h }(hj`ZhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMZhhhj_ZhM"ubjW)}(hcxl_coordinates_combineh]j])}(hcxl_coordinates_combineh]hcxl_coordinates_combine}(hjrZhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjnZubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjMZhhhj_ZhM"ubjv)}(h[(struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h](j|)}(hstruct access_coordinate *outh](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubjF)}(h h]h }(hjZhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZubh)}(hhh]j])}(haccess_coordinateh]haccess_coordinate}(hjZhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjZubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjZmodnameN classnameNjj)}j]j)}jjtZsbc.cxl_coordinates_combineasbuh1hhjZubjF)}(h h]h }(hjZhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZubj)}(hjh]h*}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj])}(houth]hout}(hjZhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjZubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjZubj|)}(hstruct access_coordinate *c1h](j)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubjF)}(h h]h }(hj [hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZubh)}(hhh]j])}(haccess_coordinateh]haccess_coordinate}(hj[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjbah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj [modnameN classnameNjj)}j]jZc.cxl_coordinates_combineasbuh1hhjZubjF)}(h h]h }(hj<[hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZubj)}(hjh]h*}(hjJ[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj])}(hc1h]hc1}(hjW[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjZubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjZubj|)}(hstruct access_coordinate *c2h](j)}(hjh]hstruct}(hjp[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl[ubjF)}(h h]h }(hj}[hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjl[ubh)}(hhh]j])}(haccess_coordinateh]haccess_coordinate}(hj[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[modnameN classnameNjj)}j]jZc.cxl_coordinates_combineasbuh1hhjl[ubjF)}(h h]h }(hj[hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjl[ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjl[ubj])}(hc2h]hc2}(hj[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjl[ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjZubeh}(h]h ]h"]h$]h&]hhuh1juhjMZhhhj_ZhM"ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjIZhhhj_ZhM"ubah}(h]jDZah ](jjeh"]h$]h&]jj)jhuh1j'hj_ZhM"hjFZhhubj)}(hhh]j])}(h!Combine the two input coordinatesh]h!Combine the two input coordinates}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM"hj[hhubah}(h]h ]h"]h$]h&]uh1jhjFZhhhj_ZhM"ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj \jj \jjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct access_coordinate *out`` Output coordinate of c1 and c2 combined ``struct access_coordinate *c1`` input coordinates ``struct access_coordinate *c2`` input coordinatesh](j])}(h**Parameters**h]j)}(hj\h]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM&hj \ubjo)}(hhh](jt)}(hJ``struct access_coordinate *out`` Output coordinate of c1 and c2 combined h](jz)}(h!``struct access_coordinate *out``h]j)}(hj2\h]hstruct access_coordinate *out}(hj4\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0\ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM$hj,\ubj)}(hhh]j])}(h'Output coordinate of c1 and c2 combinedh]h'Output coordinate of c1 and c2 combined}(hjK\hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjG\hM$hjH\ubah}(h]h ]h"]h$]h&]uh1jhj,\ubeh}(h]h ]h"]h$]h&]uh1jshjG\hM$hj)\ubjt)}(h3``struct access_coordinate *c1`` input coordinates h](jz)}(h ``struct access_coordinate *c1``h]j)}(hjk\h]hstruct access_coordinate *c1}(hjm\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji\ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM%hje\ubj)}(hhh]j])}(hinput coordinatesh]hinput coordinates}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj\hM%hj\ubah}(h]h ]h"]h$]h&]uh1jhje\ubeh}(h]h ]h"]h$]h&]uh1jshj\hM%hj)\ubjt)}(h2``struct access_coordinate *c2`` input coordinatesh](jz)}(h ``struct access_coordinate *c2``h]j)}(hj\h]hstruct access_coordinate *c2}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM'hj\ubj)}(hhh]j])}(hinput coordinatesh]hinput coordinates}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM&hj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jshj\hM'hj)\ubeh}(h]h ]h"]h$]h&]uh1jnhj \ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*cxl_endpoint_gather_bandwidth (C function)c.cxl_endpoint_gather_bandwidthhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hint cxl_endpoint_gather_bandwidth (struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h]j.)}(hint cxl_endpoint_gather_bandwidth(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j4)}(hinth]hint}(hj\hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj\hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMfubjF)}(h h]h }(hj ]hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj\hhhj ]hMfubjW)}(hcxl_endpoint_gather_bandwidthh]j])}(hcxl_endpoint_gather_bandwidthh]hcxl_endpoint_gather_bandwidth}(hj]hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj]ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj\hhhj ]hMfubjv)}(hf(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j|)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hj;]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7]ubjF)}(h h]h }(hjH]hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj7]ubh)}(hhh]j])}(h cxl_regionh]h cxl_region}(hjY]hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjV]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[]modnameN classnameNjj)}j]j)}jj!]sbc.cxl_endpoint_gather_bandwidthasbuh1hhj7]ubjF)}(h h]h }(hjy]hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj7]ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7]ubj])}(hcxlrh]hcxlr}(hj]hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj7]ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj3]ubj|)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubjF)}(h h]h }(hj]hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj]ubh)}(hhh]j])}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj]hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]ju]c.cxl_endpoint_gather_bandwidthasbuh1hhj]ubjF)}(h h]h }(hj]hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj]ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj])}(hcxledh]hcxled}(hj^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj]ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj3]ubj|)}(hstruct xarray *usp_xah](j)}(hjh]hstruct}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubjF)}(h h]h }(hj*^hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj^ubh)}(hhh]j])}(hxarrayh]hxarray}(hj;^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj8^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=^modnameN classnameNjj)}j]ju]c.cxl_endpoint_gather_bandwidthasbuh1hhj^ubjF)}(h h]h }(hjY^hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj^ubj)}(hjh]h*}(hjg^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj])}(husp_xah]husp_xa}(hjt^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj3]ubj|)}(hbool *gp_is_rooth](j4)}(hboolh]hbool}(hj^hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj^ubjF)}(h h]h }(hj^hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj^ubj)}(hjh]h*}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj])}(h gp_is_rooth]h gp_is_root}(hj^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj3]ubeh}(h]h ]h"]h$]h&]hhuh1juhj\hhhj ]hMfubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj\hhhj ]hMfubah}(h]j\ah ](jjeh"]h$]h&]jj)jhuh1j'hj ]hMfhj\hhubj)}(hhh]j])}(h/collect all the endpoint bandwidth in an xarrayh]h/collect all the endpoint bandwidth in an xarray}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMfhj^hhubah}(h]h ]h"]h$]h&]uh1jhj\hhhj ]hMfubeh}(h]h ](jfunctioneh"]h$]h&]jjjj^jj^jjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_region *cxlr`` CXL region for the bandwidth calculation ``struct cxl_endpoint_decoder *cxled`` endpoint decoder to start on ``struct xarray *usp_xa`` (output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'. ``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. **Return** 0 for success or -errno **Description** Collects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that's associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.h](j])}(h**Parameters**h]j)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMjhj^ubjo)}(hhh](jt)}(hE``struct cxl_region *cxlr`` CXL region for the bandwidth calculation h](jz)}(h``struct cxl_region *cxlr``h]j)}(hj!_h]hstruct cxl_region *cxlr}(hj#_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMghj_ubj)}(hhh]j])}(h(CXL region for the bandwidth calculationh]h(CXL region for the bandwidth calculation}(hj:_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj6_hMghj7_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshj6_hMghj_ubjt)}(hD``struct cxl_endpoint_decoder *cxled`` endpoint decoder to start on h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjZ_h]h"struct cxl_endpoint_decoder *cxled}(hj\_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX_ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhhjT_ubj)}(hhh]j])}(hendpoint decoder to start onh]hendpoint decoder to start on}(hjs_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjo_hMhhjp_ubah}(h]h ]h"]h$]h&]uh1jhjT_ubeh}(h]h ]h"]h$]h&]uh1jshjo_hMhhj_ubjt)}(h``struct xarray *usp_xa`` (output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'. h](jz)}(h``struct xarray *usp_xa``h]j)}(hj_h]hstruct xarray *usp_xa}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMjhj_ubj)}(hhh]j])}(h(output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'.h]h(output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of ‘struct cxl_perf_ctx’.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMihj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshj_hMjhj_ubjt)}(hK``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. h](jz)}(h``bool *gp_is_root``h]j)}(hj_h]hbool *gp_is_root}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMkhj_ubj)}(hhh]j])}(h5(output) bool of whether the grandparent is cxl root.h]h5(output) bool of whether the grandparent is cxl root.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj_hMkhj_ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshj_hMkhj_ubeh}(h]h ]h"]h$]h&]uh1jnhj^ubj])}(h **Return**h]j)}(hj`h]hReturn}(hj `hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMmhj^ubj])}(h0 for success or -errnoh]h0 for success or -errno}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMmhj^ubj])}(h**Description**h]j)}(hj/`h]h Description}(hj1`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-`ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMohj^ubj])}(hXCollects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that's associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.h]hXCollects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that’s associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.}(hjE`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMohj^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(cxl_switch_gather_bandwidth (C function)c.cxl_switch_gather_bandwidthhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hpstruct xarray * cxl_switch_gather_bandwidth (struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h]j.)}(hnstruct xarray *cxl_switch_gather_bandwidth(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j)}(hjh]hstruct}(hjt`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp`hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMubjF)}(h h]h }(hj`hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjp`hhhj`hMubh)}(hhh]j])}(hxarrayh]hxarray}(hj`hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj`ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj`modnameN classnameNjj)}j]j)}jcxl_switch_gather_bandwidthsbc.cxl_switch_gather_bandwidthasbuh1hhjp`hhhj`hMubjF)}(h h]h }(hj`hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjp`hhhj`hMubj)}(hjh]h*}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp`hhhj`hMubjW)}(hcxl_switch_gather_bandwidthh]j])}(hj`h]hcxl_switch_gather_bandwidth}(hj`hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj`ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjp`hhhj`hMubjv)}(hD(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j|)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubjF)}(h h]h }(hj`hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj`ubh)}(hhh]j])}(h cxl_regionh]h cxl_region}(hj ahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj aubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNjj)}j]j`c.cxl_switch_gather_bandwidthasbuh1hhj`ubjF)}(h h]h }(hj*ahhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj`ubj)}(hjh]h*}(hj8ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubj])}(hcxlrh]hcxlr}(hjEahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj`ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj`ubj|)}(hstruct xarray *input_xah](j)}(hjh]hstruct}(hj^ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZaubjF)}(h h]h }(hjkahhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZaubh)}(hhh]j])}(hxarrayh]hxarray}(hj|ahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjyaubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj~amodnameN classnameNjj)}j]j`c.cxl_switch_gather_bandwidthasbuh1hhjZaubjF)}(h h]h }(hjahhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjZaubj)}(hjh]h*}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZaubj])}(hinput_xah]hinput_xa}(hjahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjZaubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj`ubj|)}(hbool *gp_is_rooth](j4)}(hj^h]hbool}(hjahhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjaubjF)}(h h]h }(hjahhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjaubj)}(hjh]h*}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj])}(h gp_is_rooth]h gp_is_root}(hjahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjaubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj`ubeh}(h]h ]h"]h$]h&]hhuh1juhjp`hhhj`hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjl`hhhj`hMubah}(h]jg`ah ](jjeh"]h$]h&]jj)jhuh1j'hj`hMhji`hhubj)}(hhh]j])}(h6collect all the bandwidth at switch level in an xarrayh]h6collect all the bandwidth at switch level in an xarray}(hj bhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjbhhubah}(h]h ]h"]h$]h&]uh1jhji`hhhj`hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj8bjj8bjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_region *cxlr`` The region being operated on ``struct xarray *input_xa`` xarray indexed by upstream device of a switch with data of 'struct cxl_perf_ctx' ``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. **Return** a xarray of resulting cxl_perf_ctx per parent switch or root port or ERR_PTR(-errno) **Description** Iterate through the xarray. Take the minimum of the downstream calculated bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream switch if exists. Sum the resulting bandwidth under the switch upstream device or a RP device. The function can be iterated over multiple switches if the switches are present.h](j])}(h**Parameters**h]j)}(hjBbh]h Parameters}(hjDbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@bubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjchhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:chMhj;cubah}(h]h ]h"]h$]h&]uh1jhj(cubeh}(h]h ]h"]h$]h&]uh1jshj:chMhj%cubah}(h]h ]h"]h$]h&]uh1jnhjint cxl_add_ep(struct cxl_dport *dport, struct device *ep_dev)h](j4)}(hinth]hint}(hjthhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjthhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF)}(h h]h }(hjthhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjthhhjthMubjW)}(h cxl_add_eph]j])}(h cxl_add_eph]h cxl_add_ep}(hjthhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjtubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjthhhjthMubjv)}(h0(struct cxl_dport *dport, struct device *ep_dev)h](j|)}(hstruct cxl_dport *dporth](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj uubjF)}(h h]h }(hjuhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj uubh)}(hhh]j])}(h cxl_dporth]h cxl_dport}(hj.uhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj+uubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0umodnameN classnameNjj)}j]j)}jjtsb c.cxl_add_epasbuh1hhj uubjF)}(h h]h }(hjNuhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj uubj)}(hjh]h*}(hj\uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj uubj])}(hdporth]hdport}(hjiuhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj uubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjuubj|)}(hstruct device *ep_devh](j)}(hjh]hstruct}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~uubjF)}(h h]h }(hjuhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj~uubh)}(hhh]j])}(hdeviceh]hdevice}(hjuhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjumodnameN classnameNjj)}j]jJu c.cxl_add_epasbuh1hhj~uubjF)}(h h]h }(hjuhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj~uubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~uubj])}(hep_devh]hep_dev}(hjuhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj~uubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjuubeh}(h]h ]h"]h$]h&]hhuh1juhjthhhjthMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjthhhjthMubah}(h]jtah ](jjeh"]h$]h&]jj)jhuh1j'hjthMhjthhubj)}(hhh]j])}(h)register an endpoint's interest in a porth]h+register an endpoint’s interest in a port}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvhhubah}(h]h ]h"]h$]h&]uh1jhjthhhjthMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjvjjvjjjuh1j"hhhj.hNhNubj)}(hX]**Parameters** ``struct cxl_dport *dport`` the dport that routes to **ep_dev** ``struct device *ep_dev`` device representing the endpoint **Description** Intermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h](j])}(h**Parameters**h]j)}(hj%vh]h Parameters}(hj'vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#vubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvubjo)}(hhh](jt)}(h@``struct cxl_dport *dport`` the dport that routes to **ep_dev** h](jz)}(h``struct cxl_dport *dport``h]j)}(hjDvh]hstruct cxl_dport *dport}(hjFvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBvubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj>vubj)}(hhh]j])}(h#the dport that routes to **ep_dev**h](hthe dport that routes to }(hj]vhhhNhNubj)}(h **ep_dev**h]hep_dev}(hjevhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]vubeh}(h]h ]h"]h$]h&]uh1j\hjYvhMhjZvubah}(h]h ]h"]h$]h&]uh1jhj>vubeh}(h]h ]h"]h$]h&]uh1jshjYvhMhj;vubjt)}(h;``struct device *ep_dev`` device representing the endpoint h](jz)}(h``struct device *ep_dev``h]j)}(hjvh]hstruct device *ep_dev}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvubj)}(hhh]j])}(h device representing the endpointh]h device representing the endpoint}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjvhMhjvubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jshjvhMhj;vubeh}(h]h ]h"]h$]h&]uh1jnhjvubj])}(h**Description**h]j)}(hjvh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvubj])}(hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h]hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder_init (C function)c.cxl_decoder_inithNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hFint cxl_decoder_init (struct cxl_port *port, struct cxl_decoder *cxld)h]j.)}(hEint cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)h](j4)}(hinth]hint}(hj whhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjwhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF)}(h h]h }(hjwhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjwhhhjwhMubjW)}(hcxl_decoder_inith]j])}(hcxl_decoder_inith]hcxl_decoder_init}(hj,whhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj(wubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjwhhhjwhMubjv)}(h1(struct cxl_port *port, struct cxl_decoder *cxld)h](j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjHwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDwubjF)}(h h]h }(hjUwhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjDwubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjfwhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjcwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhwmodnameN classnameNjj)}j]j)}jj.wsbc.cxl_decoder_initasbuh1hhjDwubjF)}(h h]h }(hjwhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjDwubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDwubj])}(hporth]hport}(hjwhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjDwubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj@wubj|)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubjF)}(h h]h }(hjwhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjwubh)}(hhh]j])}(h cxl_decoderh]h cxl_decoder}(hjwhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjwmodnameN classnameNjj)}j]jwc.cxl_decoder_initasbuh1hhjwubjF)}(h h]h }(hjwhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjwubj)}(hjh]h*}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj])}(hcxldh]hcxld}(hjxhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjwubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj@wubeh}(h]h ]h"]h$]h&]hhuh1juhjwhhhjwhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjwhhhjwhMubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j'hjwhMhjwhhubj)}(hhh]j])}(h%Common decoder setup / initializationh]h%Common decoder setup / initialization}(hj;xhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj8xhhubah}(h]h ]h"]h$]h&]uh1jhjwhhhjwhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjSxjjSxjjjuh1j"hhhj.hNhNubj)}(hXr**Parameters** ``struct cxl_port *port`` owning port of this decoder ``struct cxl_decoder *cxld`` common decoder properties to initialize **Description** A port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()h](j])}(h**Parameters**h]j)}(hj]xh]h Parameters}(hj_xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[xubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjWxubjo)}(hhh](jt)}(h6``struct cxl_port *port`` owning port of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hj|xh]hstruct cxl_port *port}(hj~xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzxubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvxubj)}(hhh]j])}(howning port of this decoderh]howning port of this decoder}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjxhMhjxubah}(h]h ]h"]h$]h&]uh1jhjvxubeh}(h]h ]h"]h$]h&]uh1jshjxhMhjsxubjt)}(hE``struct cxl_decoder *cxld`` common decoder properties to initialize h](jz)}(h``struct cxl_decoder *cxld``h]j)}(hjxh]hstruct cxl_decoder *cxld}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjxubj)}(hhh]j])}(h'common decoder properties to initializeh]h'common decoder properties to initialize}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjxhMhjxubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jshjxhMhjsxubeh}(h]h ]h"]h$]h&]uh1jnhjWxubj])}(h**Description**h]j)}(hjxh]h Description}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjWxubj])}(hA port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()h]hA port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjWxubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#cxl_root_decoder_alloc (C function)c.cxl_root_decoder_allochNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hastruct cxl_root_decoder * cxl_root_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]j.)}(h_struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j)}(hjh]hstruct}(hj5yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1yhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF)}(h h]h }(hjCyhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj1yhhhjByhMubh)}(hhh]j])}(hcxl_root_decoderh]hcxl_root_decoder}(hjTyhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjQyubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjVymodnameN classnameNjj)}j]j)}jcxl_root_decoder_allocsbc.cxl_root_decoder_allocasbuh1hhj1yhhhjByhMubjF)}(h h]h }(hjuyhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj1yhhhjByhMubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj1yhhhjByhMubjW)}(hcxl_root_decoder_alloch]j])}(hjryh]hcxl_root_decoder_alloc}(hjyhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjyubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj1yhhhjByhMubjv)}(h0(struct cxl_port *port, unsigned int nr_targets)h](j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubjF)}(h h]h }(hjyhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjyubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjyhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjyubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjymodnameN classnameNjj)}j]jpyc.cxl_root_decoder_allocasbuh1hhjyubjF)}(h h]h }(hjyhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjyubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubj])}(hporth]hport}(hjzhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjyubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyubj|)}(hunsigned int nr_targetsh](j4)}(hunsignedh]hunsigned}(hjzhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjzubjF)}(h h]h }(hj-zhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjzubj4)}(hinth]hint}(hj;zhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjzubjF)}(h h]h }(hjIzhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjzubj])}(h nr_targetsh]h nr_targets}(hjWzhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjzubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjyubeh}(h]h ]h"]h$]h&]hhuh1juhj1yhhhjByhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj-yhhhjByhMubah}(h]j(yah ](jjeh"]h$]h&]jj)jhuh1j'hjByhMhj*yhhubj)}(hhh]j])}(hAllocate a root level decoderh]hAllocate a root level decoder}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj~zhhubah}(h]h ]h"]h$]h&]uh1jhj*yhhhjByhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjzjjzjjjuh1j"hhhj.hNhNubj)}(hXk**Parameters** ``struct cxl_port *port`` owning CXL root of this decoder ``unsigned int nr_targets`` static number of downstream targets **Return** A new cxl decoder to be registered by cxl_decoder_add(). A 'CXL root' decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.h](j])}(h**Parameters**h]j)}(hjzh]h Parameters}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubjo)}(hhh](jt)}(h:``struct cxl_port *port`` owning CXL root of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hjzh]hstruct cxl_port *port}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubj)}(hhh]j])}(howning CXL root of this decoderh]howning CXL root of this decoder}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjzhMhjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshjzhMhjzubjt)}(h@``unsigned int nr_targets`` static number of downstream targets h](jz)}(h``unsigned int nr_targets``h]j)}(hjzh]hunsigned int nr_targets}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubj)}(hhh]j])}(h#static number of downstream targetsh]h#static number of downstream targets}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj{hMhj{ubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshj{hMhjzubeh}(h]h ]h"]h$]h&]uh1jnhjzubj])}(h **Return**h]j)}(hj6{h]hReturn}(hj8{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4{ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubj])}(hA new cxl decoder to be registered by cxl_decoder_add(). A 'CXL root' decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.h]hA new cxl decoder to be registered by cxl_decoder_add(). A ‘CXL root’ decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.}(hjL{hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%cxl_switch_decoder_alloc (C function)c.cxl_switch_decoder_allochNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hestruct cxl_switch_decoder * cxl_switch_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]j.)}(hcstruct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j)}(hjh]hstruct}(hj{{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw{hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM7ubjF)}(h h]h }(hj{hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjw{hhhj{hM7ubh)}(hhh]j])}(hcxl_switch_decoderh]hcxl_switch_decoder}(hj{hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{modnameN classnameNjj)}j]j)}jcxl_switch_decoder_allocsbc.cxl_switch_decoder_allocasbuh1hhjw{hhhj{hM7ubjF)}(h h]h }(hj{hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjw{hhhj{hM7ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjw{hhhj{hM7ubjW)}(hcxl_switch_decoder_alloch]j])}(hj{h]hcxl_switch_decoder_alloc}(hj{hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj{ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjw{hhhj{hM7ubjv)}(h0(struct cxl_port *port, unsigned int nr_targets)h](j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubjF)}(h h]h }(hj|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj{ubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hj|hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj|ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj|modnameN classnameNjj)}j]j{c.cxl_switch_decoder_allocasbuh1hhj{ubjF)}(h h]h }(hj1|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj{ubj)}(hjh]h*}(hj?|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj])}(hporth]hport}(hjL|hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj{ubj|)}(hunsigned int nr_targetsh](j4)}(hunsignedh]hunsigned}(hje|hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hja|ubjF)}(h h]h }(hjs|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhja|ubj4)}(hinth]hint}(hj|hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hja|ubjF)}(h h]h }(hj|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhja|ubj])}(h nr_targetsh]h nr_targets}(hj|hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hja|ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj{ubeh}(h]h ]h"]h$]h&]hhuh1juhjw{hhhj{hM7ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjs{hhhj{hM7ubah}(h]jn{ah ](jjeh"]h$]h&]jj)jhuh1j'hj{hM7hjp{hhubj)}(hhh]j])}(hAllocate a switch level decoderh]hAllocate a switch level decoder}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM7hj|hhubah}(h]h ]h"]h$]h&]uh1jhjp{hhhj{hM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj|jj|jjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_port *port`` owning CXL switch port of this decoder ``unsigned int nr_targets`` max number of dynamically addressable downstream targets **Return** A new cxl decoder to be registered by cxl_decoder_add(). A 'switch' decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.h](j])}(h**Parameters**h]j)}(hj|h]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM;hj|ubjo)}(hhh](jt)}(hA``struct cxl_port *port`` owning CXL switch port of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hj}h]hstruct cxl_port *port}(hj }hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM8hj}ubj)}(hhh]j])}(h&owning CXL switch port of this decoderh]h&owning CXL switch port of this decoder}(hj!}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj}hM8hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jshj}hM8hj|ubjt)}(hU``unsigned int nr_targets`` max number of dynamically addressable downstream targets h](jz)}(h``unsigned int nr_targets``h]j)}(hjA}h]hunsigned int nr_targets}(hjC}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?}ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM9hj;}ubj)}(hhh]j])}(h8max number of dynamically addressable downstream targetsh]h8max number of dynamically addressable downstream targets}(hjZ}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjV}hM9hjW}ubah}(h]h ]h"]h$]h&]uh1jhj;}ubeh}(h]h ]h"]h$]h&]uh1jshjV}hM9hj|ubeh}(h]h ]h"]h$]h&]uh1jnhj|ubj])}(h **Return**h]j)}(hj|}h]hReturn}(hj~}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz}ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM;hj|ubj])}(hXA new cxl decoder to be registered by cxl_decoder_add(). A 'switch' decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.h]hX!A new cxl decoder to be registered by cxl_decoder_add(). A ‘switch’ decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM;hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'cxl_endpoint_decoder_alloc (C function)c.cxl_endpoint_decoder_allochNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hPstruct cxl_endpoint_decoder * cxl_endpoint_decoder_alloc (struct cxl_port *port)h]j.)}(hNstruct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)h](j)}(hjh]hstruct}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM\ubjF)}(h h]h }(hj}hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}hhhj}hM\ubh)}(hhh]j])}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj}hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj}ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}modnameN classnameNjj)}j]j)}jcxl_endpoint_decoder_allocsbc.cxl_endpoint_decoder_allocasbuh1hhj}hhhj}hM\ubjF)}(h h]h }(hj~hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj}hhhj}hM\ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}hhhj}hM\ubjW)}(hcxl_endpoint_decoder_alloch]j])}(hj}h]hcxl_endpoint_decoder_alloc}(hj ~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj~ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj}hhhj}hM\ubjv)}(h(struct cxl_port *port)h]j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj;~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7~ubjF)}(h h]h }(hjH~hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj7~ubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjY~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjV~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[~modnameN classnameNjj)}j]j}c.cxl_endpoint_decoder_allocasbuh1hhj7~ubjF)}(h h]h }(hjw~hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj7~ubj)}(hjh]h*}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7~ubj])}(hporth]hport}(hj~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj7~ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj3~ubah}(h]h ]h"]h$]h&]hhuh1juhj}hhhj}hM\ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj}hhhj}hM\ubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1j'hj}hM\hj}hhubj)}(hhh]j])}(hAllocate an endpoint decoderh]hAllocate an endpoint decoder}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM\hj~hhubah}(h]h ]h"]h$]h&]uh1jhj}hhhj}hM\ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj~jj~jjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_port *port`` owning port of this decoder **Return** A new cxl decoder to be registered by cxl_decoder_add()h](j])}(h**Parameters**h]j)}(hj~h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM`hj~ubjo)}(hhh]jt)}(h6``struct cxl_port *port`` owning port of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hj~h]hstruct cxl_port *port}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM]hj~ubj)}(hhh]j])}(howning port of this decoderh]howning port of this decoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM]hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jshjhM]hj~ubah}(h]h ]h"]h$]h&]uh1jnhj~ubj])}(h **Return**h]j)}(hj8h]hReturn}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM_hj~ubj])}(h7A new cxl decoder to be registered by cxl_decoder_add()h]h7A new cxl decoder to be registered by cxl_decoder_add()}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM_hj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#cxl_decoder_add_locked (C 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classnameNjj)}j]j)}jjsbc.cxl_decoder_add_lockedasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcxldh]hcxld}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hint *target_maph](j4)}(hinth]hint}(hj,hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj(ubjF)}(h h]h }(hj:hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(ubj)}(hjh]h*}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj])}(h target_maph]h target_map}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhjyhhhjhM}ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjuhhhjhM}ubah}(h]jpah ](jjeh"]h$]h&]jj)jhuh1j'hjhM}hjrhhubj)}(hhh]j])}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM}hj|hhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjhM}ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX **Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() ``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. 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Expects the device lock of the port that owns the **cxld** to be held. **Return** Negative error code if the decoder wasn't properly configured; else returns 0.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubjo)}(hhh](jt)}(hU``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() h](jz)}(h``struct cxl_decoder *cxld``h]j)}(hjh]hstruct cxl_decoder *cxld}(hj€hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM~hjubj)}(hhh]j])}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hjـhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjՀhM~hjրubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjՀhM~hjubjt)}(h``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. h](jz)}(h``int *target_map``h]j)}(hjh]hint *target_map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hj5h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj])}(hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).ih]hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj])}(h0This is the locked variant of cxl_decoder_add().h]h0This is the locked variant of cxl_decoder_add().}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj])}(h **Context**h]j)}(hjkh]hContext}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj])}(hWProcess context. Expects the device lock of the port that owns the **cxld** to be held.h](hCProcess context. Expects the device lock of the port that owns the }(hjhhhNhNubj)}(h**cxld**h]hcxld}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh to be held.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubjo)}(hhh]jt)}(hNNegative error code if the decoder wasn't properly configured; else returns 0.h](jz)}(hCNegative error code if the decoder wasn't properly configured; elseh]hENegative error code if the decoder wasn’t properly configured; else}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(h returns 0.h]h returns 0.}(hjӁhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjЁubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjρhMhjubah}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder_add (C function)c.cxl_decoder_addhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h?int cxl_decoder_add (struct cxl_decoder *cxld, int *target_map)h]j.)}(h>int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF)}(h h]h }(hj#hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhj"hMubjW)}(hcxl_decoder_addh]j])}(hcxl_decoder_addh]hcxl_decoder_add}(hj5hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj1ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhj"hMubjv)}(h+(struct cxl_decoder *cxld, int *target_map)h](j|)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubjF)}(h h]h }(hj^hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubh)}(hhh]j])}(h cxl_decoderh]h cxl_decoder}(hjohhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjlubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqmodnameN classnameNjj)}j]j)}jj7sbc.cxl_decoder_addasbuh1hhjMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj])}(hcxldh]hcxld}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjMubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjIubj|)}(hint *target_maph](j4)}(hinth]hint}(hjÂhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjubjF)}(h h]h }(hjтhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hj߂hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(h target_maph]h target_map}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjIubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhj"hMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj hhhj"hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hj"hMhj hhubj)}(hhh]j])}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj"hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj.jj.jjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() ``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. **Description** This is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked(). **Context** Process context. Takes and releases the device lock of the port that owns the **cxld**.h](j])}(h**Parameters**h]j)}(hj8h]h Parameters}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj2ubjo)}(hhh](jt)}(hU``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() h](jz)}(h``struct cxl_decoder *cxld``h]j)}(hjWh]hstruct cxl_decoder *cxld}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjQubj)}(hhh]j])}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjlhMhjmubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jshjlhMhjNubjt)}(h``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. h](jz)}(h``int *target_map``h]j)}(hjh]hint *target_map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjNubeh}(h]h ]h"]h$]h&]uh1jnhj2ubj])}(h**Description**h]j)}(hj̃h]h Description}(hj΃hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʃubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj2ubj])}(hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().h]hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj2ubj])}(h **Context**h]j)}(hjh]hContext}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj2ubj])}(hWProcess context. Takes and releases the device lock of the port that owns the **cxld**.h](hNProcess context. Takes and releases the device lock of the port that owns the }(hj hhhNhNubj)}(h**cxld**h]hcxld}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj2ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"__cxl_driver_register (C function)c.__cxl_driver_registerhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(haint __cxl_driver_register (struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h]j.)}(h`int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j4)}(hinth]hint}(hjJhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjFhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF)}(h h]h }(hjYhhhNhNubah}(h]h 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]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.__cxl_driver_registerasbuh1hhjubjF)}(h h]h }(hj5hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hownerh]howner}(hjPhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hconst char *modnameh](j)}(hjeUh]hconst}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubjF)}(h h]h }(hjvhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjeubj4)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjeubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjeubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj])}(hmodnameh]hmodname}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjeubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhjFhhhjXhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjBhhhjXhMubah}(h]j=ah ](jjeh"]h$]h&]jj)jhuh1j'hjXhMhj?hhubj)}(hhh]j])}(h!register a driver for the cxl bush]h!register a driver for the cxl bus}(hjׅhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjԅhhubah}(h]h ]h"]h$]h&]uh1jhj?hhhjXhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_driver *cxl_drv`` cxl driver structure to attach ``struct module *owner`` owning module/driver ``const char *modname`` KBUILD_MODNAME for parent driverh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubjo)}(hhh](jt)}(h>``struct cxl_driver *cxl_drv`` cxl driver structure to attach h](jz)}(h``struct cxl_driver *cxl_drv``h]j)}(hjh]hstruct cxl_driver *cxl_drv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(hcxl driver structure to attachh]hcxl driver structure to attach}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj-hMhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj-hMhjubjt)}(h.``struct module *owner`` owning module/driver h](jz)}(h``struct module *owner``h]j)}(hjQh]hstruct module *owner}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjKubj)}(hhh]j])}(howning module/driverh]howning module/driver}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjfhMhjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jshjfhMhjubjt)}(h8``const char *modname`` KBUILD_MODNAME for parent driverh](jz)}(h``const char *modname``h]j)}(hjh]hconst char *modname}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(h KBUILD_MODNAME for parent driverh]h KBUILD_MODNAME for parent driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.cxl_endpoint_get_perf_coordinates (C function)#c.cxl_endpoint_get_perf_coordinateshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h^int cxl_endpoint_get_perf_coordinates (struct cxl_port *port, struct access_coordinate *coord)h]j.)}(h]int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMtubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMtubjW)}(h!cxl_endpoint_get_perf_coordinatesh]j])}(h!cxl_endpoint_get_perf_coordinatesh]h!cxl_endpoint_get_perf_coordinates}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMtubjv)}(h8(struct cxl_port *port, struct access_coordinate *coord)h](j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hj.hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hj?hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjAmodnameN classnameNjj)}j]j)}jjsb#c.cxl_endpoint_get_perf_coordinatesasbuh1hhjubjF)}(h h]h }(hj_hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hporth]hport}(hjzhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hstruct access_coordinate *coordh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(haccess_coordinateh]haccess_coordinate}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j[#c.cxl_endpoint_get_perf_coordinatesasbuh1hhjubjF)}(h h]h }(hjχhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hj݇hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcoordh]hcoord}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhMtubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj܆hhhjhMtubah}(h]j׆ah ](jjeh"]h$]h&]jj)jhuh1j'hjhMthjنhhubj)}(hhh]j])}(h9Retrieve performance numbers stored in dports of CXL pathh]h9Retrieve performance numbers stored in dports of CXL path}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMthjhhubah}(h]h ]h"]h$]h&]uh1jhjنhhhjhMtubeh}(h]h ](jfunctioneh"]h$]h&]jjjj,jj,jjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_port *port`` endpoint cxl_port ``struct access_coordinate *coord`` output performance data **Return** errno on failure, 0 on success.h](j])}(h**Parameters**h]j)}(hj6h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMxhj0ubjo)}(hhh](jt)}(h,``struct cxl_port *port`` endpoint cxl_port h](jz)}(h``struct cxl_port *port``h]j)}(hjUh]hstruct cxl_port *port}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMvhjOubj)}(hhh]j])}(hendpoint cxl_porth]hendpoint cxl_port}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjjhMvhjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jshjjhMvhjLubjt)}(h<``struct access_coordinate *coord`` output performance data h](jz)}(h#``struct access_coordinate *coord``h]j)}(hjh]hstruct access_coordinate *coord}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMwhjubj)}(hhh]j])}(houtput performance datah]houtput performance data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMwhjLubeh}(h]h ]h"]h$]h&]uh1jnhj0ubj])}(h **Return**h]j)}(hjɈh]hReturn}(hjˈhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMyhj0ubj])}(herrno on failure, 0 on success.h]herrno on failure, 0 on success.}(hj߈hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMyhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.h]hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:454: ./drivers/cxl/core/pci.chKhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+devm_cxl_port_enumerate_dports (C function) c.devm_cxl_port_enumerate_dportshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h:int devm_cxl_port_enumerate_dports (struct cxl_port *port)h]j.)}(h9int devm_cxl_port_enumerate_dports(struct cxl_port *port)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKGubjF)}(h h]h }(hj,hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhj+hKGubjW)}(hdevm_cxl_port_enumerate_dportsh]j])}(hdevm_cxl_port_enumerate_dportsh]hdevm_cxl_port_enumerate_dports}(hj>hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj:ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhj+hKGubjv)}(h(struct cxl_port *port)h]j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubjF)}(h h]h }(hjghhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjVubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjxhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjzmodnameN classnameNjj)}j]j)}jj@sb c.devm_cxl_port_enumerate_dportsasbuh1hhjVubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjVubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubj])}(hporth]hport}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjVubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjRubah}(h]h ]h"]h$]h&]hhuh1juhjhhhj+hKGubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhj+hKGubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hj+hKGhjhhubj)}(hhh]j])}(h/enumerate downstream ports of the upstream porth]h/enumerate downstream ports of the upstream port}(hj݉hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKGhjډhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj+hKGubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_port *port`` cxl_port whose ->uport_dev is the upstream of dports to be enumerated **Description** Returns a positive number of dports enumerated or a negative error code.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKKhjubjo)}(hhh]jt)}(h```struct cxl_port *port`` cxl_port whose ->uport_dev is the upstream of dports to be enumerated h](jz)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKHhjubj)}(hhh]j])}(hEcxl_port whose ->uport_dev is the upstream of dports to be enumeratedh]hEcxl_port whose ->uport_dev is the upstream of dports to be enumerated}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj3hKHhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj3hKHhjubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjYh]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKJhjubj])}(hHReturns a positive number of dports enumerated or a negative error code.h]hHReturns a positive number of dports enumerated or a negative error code.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKJhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_hdm_decode_init (C function)c.cxl_hdm_decode_inithNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hsint cxl_hdm_decode_init (struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j.)}(hrint cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMubjW)}(hcxl_hdm_decode_inith]j])}(hcxl_hdm_decode_inith]hcxl_hdm_decode_init}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMubjv)}(h[(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j|)}(hstruct cxl_dev_state *cxldsh](j)}(hjh]hstruct}(hjۊhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj׊ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj׊ubh)}(hhh]j])}(h cxl_dev_stateh]h cxl_dev_state}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_hdm_decode_initasbuh1hhj׊ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj׊ubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj׊ubj])}(hcxldsh]hcxlds}(hj4hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj׊ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjӊubj|)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubjF)}(h h]h }(hjZhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjIubh)}(hhh]j])}(hcxl_hdmh]hcxl_hdm}(hjkhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjhubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmmodnameN classnameNjj)}j]jc.cxl_hdm_decode_initasbuh1hhjIubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjIubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIubj])}(hcxlhdmh]hcxlhdm}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjIubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjӊubj|)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjʋhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjۋhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj؋ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj݋modnameN classnameNjj)}j]jc.cxl_hdm_decode_initasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjӊubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMhjhhubj)}(hhh]j])}(h#Setup HDM decoding for the endpointh]h#Setup HDM decoding for the endpoint}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj;hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjVjjVjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` Device state ``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability ``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info **Description** Try to enable the endpoint's HDM Decoder Capabilityh](j])}(h**Parameters**h]j)}(hj`h]h Parameters}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjZubjo)}(hhh](jt)}(h-``struct cxl_dev_state *cxlds`` Device state h](jz)}(h``struct cxl_dev_state *cxlds``h]j)}(hjh]hstruct cxl_dev_state *cxlds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjyubj)}(hhh]j])}(h Device stateh]h Device state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jshjhMhjvubjt)}(h9``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability h](jz)}(h``struct cxl_hdm *cxlhdm``h]j)}(hjh]hstruct cxl_hdm *cxlhdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(hMapped HDM decoder Capabilityh]hMapped HDM decoder Capability}(hjьhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj͌hMhjΌubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj͌hMhjvubjt)}(hK``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info h](jz)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjh]h$struct cxl_endpoint_dvsec_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h!Cached DVSEC range registers infoh]h!Cached DVSEC range registers info}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjvubeh}(h]h ]h"]h$]h&]uh1jnhjZubj])}(h**Description**h]j)}(hj,h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjZubj])}(h3Try to enable the endpoint's HDM Decoder Capabilityh]h5Try to enable the endpoint’s HDM Decoder Capability}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jread_cdat_data (C function)c.read_cdat_datahNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h+void read_cdat_data (struct cxl_port *port)h]j.)}(h*void read_cdat_data(struct cxl_port *port)h](j4)}(hvoidh]hvoid}(hjqhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjmhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMOubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjmhhhjhMOubjW)}(hread_cdat_datah]j])}(hread_cdat_datah]hread_cdat_data}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjmhhhjhMOubjv)}(h(struct cxl_port *port)h]j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hj̍hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjɍubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj΍modnameN classnameNjj)}j]j)}jjsbc.read_cdat_dataasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hporth]hport}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubah}(h]h ]h"]h$]h&]hhuh1juhjmhhhjhMOubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjihhhjhMOubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j'hjhMOhjfhhubj)}(hhh]j])}(hRead the CDAT data on this porth]hRead the CDAT data on this port}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMOhj.hhubah}(h]h ]h"]h$]h&]uh1jhjfhhhjhMOubeh}(h]h ](jfunctioneh"]h$]h&]jjjjIjjIjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_port *port`` Port to read data from **Description** This call will sleep waiting for responses from the DOE mailbox.h](j])}(h**Parameters**h]j)}(hjSh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMShjMubjo)}(hhh]jt)}(h1``struct cxl_port *port`` Port to read data from h](jz)}(h``struct cxl_port *port``h]j)}(hjrh]hstruct cxl_port *port}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMPhjlubj)}(hhh]j])}(hPort to read data fromh]hPort to read data from}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMPhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jshjhMPhjiubah}(h]h ]h"]h$]h&]uh1jnhjMubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMRhjMubj])}(h@This call will sleep waiting for responses from the DOE mailbox.h]h@This call will sleep waiting for responses from the DOE mailbox.}(hjÎhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMRhjMubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)cxl_dport_init_ras_reporting (C function)c.cxl_dport_init_ras_reportinghNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hPvoid cxl_dport_init_ras_reporting (struct cxl_dport *dport, struct device *host)h]j.)}(hOvoid cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)h](j4)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM#ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM#ubjW)}(hcxl_dport_init_ras_reportingh]j])}(hcxl_dport_init_ras_reportingh]hcxl_dport_init_ras_reporting}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM#ubjv)}(h.(struct cxl_dport *dport, struct device *host)h](j|)}(hstruct cxl_dport *dporth](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubjF)}(h h]h }(hj<hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj+ubh)}(hhh]j])}(h cxl_dporth]h cxl_dport}(hjMhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]j)}jjsbc.cxl_dport_init_ras_reportingasbuh1hhj+ubjF)}(h h]h }(hjmhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj+ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubj])}(hdporth]hdport}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj'ubj|)}(hstruct device *hosth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jic.cxl_dport_init_ras_reportingasbuh1hhjubjF)}(h h]h }(hjݏhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hhosth]hhost}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj'ubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM#ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM#ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM#hjhhubj)}(hhh]j])}(h"Setup CXL RAS report on this dporth]h"Setup CXL RAS report on this dport}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM#hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM#ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj:jj:jjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct cxl_dport *dport`` the cxl_dport that needs to be initialized ``struct device *host`` host device for devm operationsh](j])}(h**Parameters**h]j)}(hjDh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM'hj>ubjo)}(hhh](jt)}(hG``struct cxl_dport *dport`` the cxl_dport that needs to be initialized h](jz)}(h``struct cxl_dport *dport``h]j)}(hjch]hstruct cxl_dport *dport}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM$hj]ubj)}(hhh]j])}(h*the cxl_dport that needs to be initializedh]h*the cxl_dport that needs to be initialized}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjxhM$hjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jshjxhM$hjZubjt)}(h7``struct device *host`` host device for devm operationsh](jz)}(h``struct device *host``h]j)}(hjh]hstruct device *host}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM&hjubj)}(hhh]j])}(hhost device for devm operationsh]hhost device for devm operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM&hjZubeh}(h]h ]h"]h$]h&]uh1jnhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_pci_get_latency (C function)c.cxl_pci_get_latencyhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h/long cxl_pci_get_latency (struct pci_dev *pdev)h]j.)}(h.long cxl_pci_get_latency(struct pci_dev *pdev)h](j4)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMubjW)}(hcxl_pci_get_latencyh]j])}(hcxl_pci_get_latencyh]hcxl_pci_get_latency}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMubjv)}(h(struct pci_dev *pdev)h]j|)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubjF)}(h h]h }(hj@hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj/ubh)}(hhh]j])}(hpci_devh]hpci_dev}(hjQhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjSmodnameN classnameNjj)}j]j)}jjsbc.cxl_pci_get_latencyasbuh1hhj/ubjF)}(h h]h }(hjqhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj/ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj])}(hpdevh]hpdev}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj/ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj+ubah}(h]h ]h"]h$]h&]hhuh1juhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMhjhhubj)}(hhh]j])}(h,calculate the link latency for the PCIe linkh]h,calculate the link latency for the PCIe link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjΑjjΑjjjuh1j"hhhj.hNhNubj)}(hX7**Parameters** ``struct pci_dev *pdev`` PCI device **Return** calculated latency or 0 for no latency **Description** CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h](j])}(h**Parameters**h]j)}(hjؑh]h Parameters}(hjڑhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֑ubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjґubjo)}(hhh]jt)}(h$``struct pci_dev *pdev`` PCI device h](jz)}(h``struct pci_dev *pdev``h]j)}(hjh]hstruct pci_dev *pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h PCI deviceh]h PCI device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj hMhjubah}(h]h ]h"]h$]h&]uh1jnhjґubj])}(h **Return**h]j)}(hj2h]hReturn}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjґubj])}(h&calculated latency or 0 for no latencyh]h&calculated latency or 0 for no latency}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjґubj])}(h**Description**h]j)}(hjYh]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjґubj])}(hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h]hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjґubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(hXIThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL 'bridge' device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus' device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.h]hXQThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL ‘bridge’ device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM ‘bus’ device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:460: ./drivers/cxl/core/pmem.chK hj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#cxl_find_nvdimm_bridge (C function)c.cxl_find_nvdimm_bridgehNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hIstruct cxl_nvdimm_bridge * cxl_find_nvdimm_bridge (struct cxl_port *port)h]j.)}(hGstruct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhK7ubh)}(hhh]j])}(hcxl_nvdimm_bridgeh]hcxl_nvdimm_bridge}(hj̒hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjɒubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjΒmodnameN classnameNjj)}j]j)}jcxl_find_nvdimm_bridgesbc.cxl_find_nvdimm_bridgeasbuh1hhjhhhjhK7ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhK7ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhK7ubjW)}(hcxl_find_nvdimm_bridgeh]j])}(hjh]hcxl_find_nvdimm_bridge}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhK7ubjv)}(h(struct cxl_port *port)h]j|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubjF)}(h h]h }(hj4hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj#ubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjEhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjBubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjGmodnameN classnameNjj)}j]jc.cxl_find_nvdimm_bridgeasbuh1hhj#ubjF)}(h h]h }(hjchhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj#ubj)}(hjh]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj])}(hporth]hport}(hj~hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubah}(h]h ]h"]h$]h&]hhuh1juhjhhhjhK7ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhK7ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhK7hjhhubj)}(hhh]j])}(h'find a bridge device relative to a porth]h'find a bridge device relative to a port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhK7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hn**Parameters** ``struct cxl_port *port`` any descendant port of an nvdimm-bridge associated root-cxl-porth](j])}(h**Parameters**h]j)}(hjʓh]h Parameters}(hj̓hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȓubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK;hjēubjo)}(hhh]jt)}(hZ``struct cxl_port *port`` any descendant port of an nvdimm-bridge associated root-cxl-porth](jz)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK8hjubj)}(hhh]j])}(h@any descendant port of an nvdimm-bridge associated root-cxl-porth]h@any descendant port of an nvdimm-bridge associated root-cxl-port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhK8hjubah}(h]h ]h"]h$]h&]uh1jnhjēubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'devm_cxl_add_nvdimm_bridge (C function)c.devm_cxl_add_nvdimm_bridgehNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hbstruct cxl_nvdimm_bridge * devm_cxl_add_nvdimm_bridge (struct device *host, struct cxl_port *port)h]j.)}(h`struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, struct cxl_port *port)h](j)}(hjh]hstruct}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKwubjF)}(h h]h }(hjPhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj>hhhjOhKwubh)}(hhh]j])}(hcxl_nvdimm_bridgeh]hcxl_nvdimm_bridge}(hjahhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjcmodnameN classnameNjj)}j]j)}jdevm_cxl_add_nvdimm_bridgesbc.devm_cxl_add_nvdimm_bridgeasbuh1hhj>hhhjOhKwubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj>hhhjOhKwubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhjOhKwubjW)}(hdevm_cxl_add_nvdimm_bridgeh]j])}(hjh]hdevm_cxl_add_nvdimm_bridge}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj>hhhjOhKwubjv)}(h,(struct device *host, struct cxl_port *port)h](j|)}(hstruct device *hosth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjɔhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hdeviceh]hdevice}(hjڔhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjהubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjܔmodnameN classnameNjj)}j]j}c.devm_cxl_add_nvdimm_bridgeasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hhosth]hhost}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubjF)}(h h]h }(hj9hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(ubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjJhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjGubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjLmodnameN classnameNjj)}j]j}c.devm_cxl_add_nvdimm_bridgeasbuh1hhj(ubjF)}(h h]h }(hjhhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj(ubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj])}(hporth]hport}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhj>hhhjOhKwubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj:hhhjOhKwubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1j'hjOhKwhj7hhubj)}(hhh]j])}(h$add the root of a LIBNVDIMM topologyh]h$add the root of a LIBNVDIMM topology}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKwhjhhubah}(h]h ]h"]h$]h&]uh1jhj7hhhjOhKwubeh}(h]h ](jfunctioneh"]h$]h&]jjjjŕjjŕjjjuh1j"hhhj.hNhNubj)}(h**Parameters** ``struct device *host`` platform firmware root device ``struct cxl_port *port`` CXL port at the root of a CXL topology **Return** bridge device that can host cxl_nvdimm objectsh](j])}(h**Parameters**h]j)}(hjϕh]h Parameters}(hjѕhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͕ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK{hjɕubjo)}(hhh](jt)}(h6``struct device *host`` platform firmware root device h](jz)}(h``struct device *host``h]j)}(hjh]hstruct device *host}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKxhjubj)}(hhh]j])}(hplatform firmware root deviceh]hplatform firmware root device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKxhjubjt)}(hA``struct cxl_port *port`` CXL port at the root of a CXL topology h](jz)}(h``struct cxl_port *port``h]j)}(hj'h]hstruct cxl_port *port}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKyhj!ubj)}(hhh]j])}(h&CXL port at the root of a CXL topologyh]h&CXL port at the root of a CXL topology}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj<hKyhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jshj<hKyhjubeh}(h]h ]h"]h$]h&]uh1jnhjɕubj])}(h **Return**h]j)}(hjbh]hReturn}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK{hjɕubj])}(h.bridge device that can host cxl_nvdimm objectsh]h.bridge device that can host cxl_nvdimm objects}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK{hjɕubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j devm_cxl_add_nvdimm (C function)c.devm_cxl_add_nvdimmhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hPint devm_cxl_add_nvdimm (struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h]j.)}(hOint devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhKubjW)}(hdevm_cxl_add_nvdimmh]j])}(hdevm_cxl_add_nvdimmh]hdevm_cxl_add_nvdimm}(hjȖhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjĖubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhKubjv)}(h8(struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h](j|)}(hstruct cxl_port *parent_porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_porth]hcxl_port}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjʖsbc.devm_cxl_add_nvdimmasbuh1hhjubjF)}(h h]h }(hj"hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(h parent_porth]h parent_port}(hj=hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjܖubj|)}(hstruct cxl_memdev *cxlmdh](j)}(hjh]hstruct}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubjF)}(h h]h }(hjchhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRubh)}(hhh]j])}(h cxl_memdevh]h cxl_memdev}(hjthhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjqubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNjj)}j]jc.devm_cxl_add_nvdimmasbuh1hhjRubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjRubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj])}(hcxlmdh]hcxlmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjRubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjܖubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhKhjhhubj)}(hhh]j])}(h/add a bridge between a cxl_memdev and an nvdimmh]h/add a bridge between a cxl_memdev and an nvdimm}(hjחhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjԗhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_port *parent_port`` parent port for the (to be added) **cxlmd** endpoint port ``struct cxl_memdev *cxlmd`` cxl_memdev instance that will perform LIBNVDIMM operations **Return** 0 on success negative error code on failure.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubjo)}(hhh](jt)}(h[``struct cxl_port *parent_port`` parent port for the (to be added) **cxlmd** endpoint port h](jz)}(h ``struct cxl_port *parent_port``h]j)}(hjh]hstruct cxl_port *parent_port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubj)}(hhh]j])}(h9parent port for the (to be added) **cxlmd** endpoint porth](h"parent port for the (to be added) }(hj1hhhNhNubj)}(h **cxlmd**h]hcxlmd}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh endpoint port}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj-hKhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj-hKhjubjt)}(hX``struct cxl_memdev *cxlmd`` cxl_memdev instance that will perform LIBNVDIMM operations h](jz)}(h``struct cxl_memdev *cxlmd``h]j)}(hjch]hstruct cxl_memdev *cxlmd}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj]ubj)}(hhh]j])}(h:cxl_memdev instance that will perform LIBNVDIMM operationsh]h:cxl_memdev instance that will perform LIBNVDIMM operations}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjxhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jshjxhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubj])}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.h]hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.}(hjʘhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhj.hhubj])}(hVProvide common infrastructure for enumerating and mapping these discrete capabilities.h]hVProvide common infrastructure for enumerating and mapping these discrete capabilities.}(hj٘hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%cxl_probe_component_regs (C function)c.cxl_probe_component_regshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hivoid cxl_probe_component_regs (struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h]j.)}(hhvoid cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](j4)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhKubjW)}(hcxl_probe_component_regsh]j])}(hcxl_probe_component_regsh]hcxl_probe_component_regs}(hj"hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhKubjv)}(hK(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](j|)}(hstruct device *devh](j)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubjF)}(h h]h }(hjKhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj:ubh)}(hhh]j])}(hdeviceh]hdevice}(hj\hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjYubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj^modnameN classnameNjj)}j]j)}jj$sbc.cxl_probe_component_regsasbuh1hhj:ubjF)}(h h]h }(hj|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj:ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj])}(hdevh]hdev}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj:ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj6ubj|)}(hvoid __iomem *baseh](j4)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh__iomem}(hjhhhNhNubjF)}(h h]h }(hjЙhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjޙhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hbaseh]hbase}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj6ubj|)}(h!struct cxl_component_reg_map *maph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_component_reg_maph]hcxl_component_reg_map}(hj"hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj$modnameN classnameNjj)}j]jxc.cxl_probe_component_regsasbuh1hhjubjF)}(h h]h }(hj@hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hmaph]hmap}(hj[hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj6ubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhKhjhhubj)}(hhh]j])}(h$Detect CXL Component register blocksh]h$Detect CXL Component register blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct device *dev`` Host device of the **base** mapping ``void __iomem *base`` Mapping containing the HDM Decoder Capability Header ``struct cxl_component_reg_map *map`` Map object describing the register block information found **Description** See CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interface Probe for component register information and return it in map object.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hjubjo)}(hhh](jt)}(h;``struct device *dev`` Host device of the **base** mapping h](jz)}(h``struct device *dev``h]j)}(hjƚh]hstruct device *dev}(hjȚhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjĚubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjubj)}(hhh]j])}(h#Host device of the **base** mappingh](hHost device of the }(hjߚhhhNhNubj)}(h**base**h]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjߚubh mapping}(hjߚhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjۚhKhjܚubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjۚhKhjubjt)}(hL``void __iomem *base`` Mapping containing the HDM Decoder Capability Header h](jz)}(h``void __iomem *base``h]j)}(hjh]hvoid __iomem *base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhj ubj)}(hhh]j])}(h4Mapping containing the HDM Decoder Capability Headerh]h4Mapping containing the HDM Decoder Capability Header}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj&hKhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj&hKhjubjt)}(ha``struct cxl_component_reg_map *map`` Map object describing the register block information found h](jz)}(h%``struct cxl_component_reg_map *map``h]j)}(hjJh]h!struct cxl_component_reg_map *map}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjDubj)}(hhh]j])}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj_hKhj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshj_hKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK!hjubj])}(hlSee CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interfaceh]hlSee CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK!hjubj])}(hEProbe for component register information and return it in map object.h]hEProbe for component register information and return it in map object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK$hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"cxl_probe_device_regs (C function)c.cxl_probe_device_regshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hcvoid cxl_probe_device_regs (struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h]j.)}(hbvoid cxl_probe_device_regs(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](j4)}(hvoidh]hvoid}(hjٛhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj՛hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKpubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj՛hhhjhKpubjW)}(hcxl_probe_device_regsh]j])}(hcxl_probe_device_regsh]hcxl_probe_device_regs}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj՛hhhjhKpubjv)}(hH(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](j|)}(hstruct device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hj#hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hdeviceh]hdevice}(hj4hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j)}jjsbc.cxl_probe_device_regsasbuh1hhjubjF)}(h h]h }(hjThhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hdevh]hdev}(hjohhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hvoid __iomem *baseh](j4)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh__iomem}(hjhhhNhNubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hbaseh]hbase}(hjÜhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hstruct cxl_device_reg_map *maph](j)}(hjh]hstruct}(hjܜhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj؜ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj؜ubh)}(hhh]j])}(hcxl_device_reg_maph]hcxl_device_reg_map}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jPc.cxl_probe_device_regsasbuh1hhj؜ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj؜ubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj؜ubj])}(hmaph]hmap}(hj3hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj؜ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhj՛hhhjhKpubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjћhhhjhKpubah}(h]j̛ah ](jjeh"]h$]h&]jj)jhuh1j'hjhKphjΛhhubj)}(hhh]j])}(h!Detect CXL Device register blocksh]h!Detect CXL Device register blocks}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKphjZhhubah}(h]h ]h"]h$]h&]uh1jhjΛhhhjhKpubeh}(h]h ](jfunctioneh"]h$]h&]jjjjujjujjjuh1j"hhhj.hNhNubj)}(hXS**Parameters** ``struct device *dev`` Host device of the **base** mapping ``void __iomem *base`` Mapping of CXL 2.0 8.2.8 CXL Device Register Interface ``struct cxl_device_reg_map *map`` Map object describing the register block information found **Description** Probe for device register information and return it in map object.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKthjyubjo)}(hhh](jt)}(h;``struct device *dev`` Host device of the **base** mapping h](jz)}(h``struct device *dev``h]j)}(hjh]hstruct device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKqhjubj)}(hhh]j])}(h#Host device of the **base** mappingh](hHost device of the }(hjhhhNhNubj)}(h**base**h]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh mapping}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjhKqhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKqhjubjt)}(hN``void __iomem *base`` Mapping of CXL 2.0 8.2.8 CXL Device Register Interface h](jz)}(h``void __iomem *base``h]j)}(hjh]hvoid __iomem *base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKrhjubj)}(hhh]j])}(h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interfaceh]h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKrhjubjt)}(h^``struct cxl_device_reg_map *map`` Map object describing the register block information found h](jz)}(h"``struct cxl_device_reg_map *map``h]j)}(hj"h]hstruct cxl_device_reg_map *map}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKshjubj)}(hhh]j])}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj7hKshj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj7hKshjubeh}(h]h ]h"]h$]h&]uh1jnhjyubj])}(h**Description**h]j)}(hj]h]h Description}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKuhjyubj])}(hBProbe for device register information and return it in map object.h]hBProbe for device register information and return it in map object.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKuhjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'cxl_find_regblock_instance (C function)c.cxl_find_regblock_instancehNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hint cxl_find_regblock_instance (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h]j.)}(hint cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM\ubjW)}(hcxl_find_regblock_instanceh]j])}(hcxl_find_regblock_instanceh]hcxl_find_regblock_instance}(hjÞhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM\ubjv)}(hc(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](j|)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hjߞhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj۞ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj۞ubh)}(hhh]j])}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjŞsbc.cxl_find_regblock_instanceasbuh1hhj۞ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj۞ubj)}(hjh]h*}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj۞ubj])}(hpdevh]hpdev}(hj8hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj۞ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjמubj|)}(henum cxl_regloc_type typeh](j)}(henumh]henum}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubjF)}(h h]h }(hj_hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubh)}(hhh]j])}(hcxl_regloc_typeh]hcxl_regloc_type}(hjphhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjmubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]jc.cxl_find_regblock_instanceasbuh1hhjMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubj])}(htypeh]htype}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjMubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjמubj|)}(hstruct cxl_register_map *maph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjŸhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_register_maph]hcxl_register_map}(hjӟhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjПubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj՟modnameN classnameNjj)}j]jc.cxl_find_regblock_instanceasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hmaph]hmap}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjמubj|)}(hunsigned int indexh](j4)}(hunsignedh]hunsigned}(hj%hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj!ubjF)}(h h]h }(hj3hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj!ubj4)}(hinth]hint}(hjAhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj!ubjF)}(h h]h }(hjOhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj!ubj])}(hindexh]hindex}(hj]hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjמubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM\ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM\ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM\hjhhubj)}(hhh]j])}(h'Locate a register block by type / indexh]h'Locate a register block by type / index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM\ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id ``struct cxl_register_map *map`` Enumeration output, clobbered on error ``unsigned int index`` Index into which particular instance of a regblock wanted in the order found in register locator DVSEC. **Return** 0 if register block enumerated, negative error code otherwise **Description** A CXL DVSEC may point to one or more register blocks, search for them by **type** and **index**.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hjubjo)}(hhh](jt)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](jz)}(h``struct pci_dev *pdev``h]j)}(hjȠh]hstruct pci_dev *pdev}(hjʠhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƠubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM]hj ubj)}(hhh]j])}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjݠhM]hjޠubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshjݠhM]hjubjt)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](jz)}(h``enum cxl_regloc_type type``h]j)}(hjh]henum cxl_regloc_type type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM^hjubj)}(hhh]j])}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM^hjubjt)}(hH``struct cxl_register_map *map`` Enumeration output, clobbered on error h](jz)}(h ``struct cxl_register_map *map``h]j)}(hj:h]hstruct cxl_register_map *map}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM_hj4ubj)}(hhh]j])}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjOhM_hjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jshjOhM_hjubjt)}(h``unsigned int index`` Index into which particular instance of a regblock wanted in the order found in register locator DVSEC. h](jz)}(h``unsigned int index``h]j)}(hjsh]hunsigned int index}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMahjmubj)}(hhh]j])}(hgIndex into which particular instance of a regblock wanted in the order found in register locator DVSEC.h]hgIndex into which particular instance of a regblock wanted in the order found in register locator DVSEC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jshjhMahjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjubj])}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hjšhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjubj])}(h**Description**h]j)}(hj֡h]h Description}(hjءhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԡubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMehjubj])}(h`A CXL DVSEC may point to one or more register blocks, search for them by **type** and **index**.h](hIA CXL DVSEC may point to one or more register blocks, search for them by }(hjhhhNhNubj)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h **index**h]hindex}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMehjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_find_regblock (C function)c.cxl_find_regblockhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(heint cxl_find_regblock (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h]j.)}(hdint cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](j4)}(hinth]hint}(hj?hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj;hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMpubjF)}(h h]h }(hjNhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj;hhhjMhMpubjW)}(hcxl_find_regblockh]j])}(hcxl_find_regblockh]hcxl_find_regblock}(hj`hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj\ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj;hhhjMhMpubjv)}(hO(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](j|)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjxubh)}(hhh]j])}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjbsbc.cxl_find_regblockasbuh1hhjxubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjxubj)}(hjh]h*}(hjȢhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj])}(hpdevh]hpdev}(hjբhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjxubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjtubj|)}(henum cxl_regloc_type typeh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_regloc_typeh]hcxl_regloc_type}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_find_regblockasbuh1hhjubjF)}(h h]h }(hj*hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj])}(htypeh]htype}(hj8hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjtubj|)}(hstruct cxl_register_map *maph](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubjF)}(h h]h }(hj^hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubh)}(hhh]j])}(hcxl_register_maph]hcxl_register_map}(hjohhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjlubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqmodnameN classnameNjj)}j]jc.cxl_find_regblockasbuh1hhjMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj])}(hmaph]hmap}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjMubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjtubeh}(h]h ]h"]h$]h&]hhuh1juhj;hhhjMhMpubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj7hhhjMhMpubah}(h]j2ah ](jjeh"]h$]h&]jj)jhuh1j'hjMhMphj4hhubj)}(hhh]j])}(hLocate register blocks by typeh]hLocate register blocks by type}(hjңhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMphjϣhhubah}(h]h ]h"]h$]h&]uh1jhj4hhhjMhMpubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id ``struct cxl_register_map *map`` Enumeration output, clobbered on error **Return** 0 if register block enumerated, negative error code otherwise **Description** A CXL DVSEC may point to one or more register blocks, search for them by **type**.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMthjubjo)}(hhh](jt)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](jz)}(h``struct pci_dev *pdev``h]j)}(hjh]hstruct pci_dev *pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMqhj ubj)}(hhh]j])}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj(hMqhj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj(hMqhj ubjt)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](jz)}(h``enum cxl_regloc_type type``h]j)}(hjLh]henum cxl_regloc_type type}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMrhjFubj)}(hhh]j])}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjahMrhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jshjahMrhj ubjt)}(hH``struct cxl_register_map *map`` Enumeration output, clobbered on error h](jz)}(h ``struct cxl_register_map *map``h]j)}(hjh]hstruct cxl_register_map *map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMshjubj)}(hhh]j])}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMshjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMshj ubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hjh]hReturn}(hj¤hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhjubj])}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hj֤hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMwhjubj])}(hRA CXL DVSEC may point to one or more register blocks, search for them by **type**.h](hIA CXL DVSEC may point to one or more register blocks, search for them by }(hjhhhNhNubj)}(h**type**h]htype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMwhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_count_regblock (C function)c.cxl_count_regblockhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hHint cxl_count_regblock (struct pci_dev *pdev, enum cxl_regloc_type type)h]j.)}(hGint cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)h](j4)}(hinth]hint}(hj>hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj:hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMubjF)}(h h]h }(hjMhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj:hhhjLhMubjW)}(hcxl_count_regblockh]j])}(hcxl_count_regblockh]hcxl_count_regblock}(hj_hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj[ubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj:hhhjLhMubjv)}(h1(struct pci_dev *pdev, enum cxl_regloc_type type)h](j|)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjwubh)}(hhh]j])}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjasbc.cxl_count_regblockasbuh1hhjwubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjwubj)}(hjh]h*}(hjǥhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubj])}(hpdevh]hpdev}(hjԥhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjwubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjsubj|)}(henum cxl_regloc_type typeh](j)}(hjSh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_regloc_typeh]hcxl_regloc_type}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jc.cxl_count_regblockasbuh1hhjubjF)}(h h]h }(hj)hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj])}(htypeh]htype}(hj7hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjsubeh}(h]h ]h"]h$]h&]hhuh1juhj:hhhjLhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj6hhhjLhMubah}(h]j1ah ](jjeh"]h$]h&]jj)jhuh1j'hjLhMhj3hhubj)}(hhh]j])}(h)Count instances of a given regblock type.h]h)Count instances of a given regblock type.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj^hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhjLhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjyjjyjjjuh1j"hhhj.hNhNubj)}(hX***Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id **Description** Some regblocks may be repeated. Count how many instances. **Return** non-negative count of matching regblocks, negative error code otherwise.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj}ubjo)}(hhh](jt)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](jz)}(h``struct pci_dev *pdev``h]j)}(hjh]hstruct pci_dev *pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjubj)}(hhh]j])}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](jz)}(h``enum cxl_regloc_type type``h]j)}(hjۦh]henum cxl_regloc_type type}(hjݦhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj٦ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjզubj)}(hhh]j])}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjզubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubeh}(h]h ]h"]h$]h&]uh1jnhj}ubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj}ubj])}(h9Some regblocks may be repeated. Count how many instances.h]h9Some regblocks may be repeated. Count how many instances.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj}ubj])}(h **Return**h]j)}(hj=h]hReturn}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj}ubj])}(hHnon-negative count of matching regblocks, negative error code otherwise.h]hHnon-negative count of matching regblocks, negative error code otherwise.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj])}(hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.h]hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:472: ./drivers/cxl/core/mbox.chKhj.hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"cxl_internal_send_cmd (C function)c.cxl_internal_send_cmdhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hWint cxl_internal_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]j.)}(hVint cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhKubjW)}(hcxl_internal_send_cmdh]j])}(hcxl_internal_send_cmdh]hcxl_internal_send_cmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhKubjv)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](j|)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hjΧhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʧubjF)}(h h]h }(hjۧhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjʧubh)}(hhh]j])}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_internal_send_cmdasbuh1hhjʧubjF)}(h h]h }(hj hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjʧubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʧubj])}(hcxl_mboxh]hcxl_mbox}(hj'hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjʧubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjƧubj|)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubjF)}(h h]h }(hjMhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj<ubh)}(hhh]j])}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj^hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj`modnameN classnameNjj)}j]jc.cxl_internal_send_cmdasbuh1hhj<ubjF)}(h h]h }(hj|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj<ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubj])}(hmbox_cmdh]hmbox_cmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj<ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjƧubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhKhjhhubj)}(hhh]j])}(h3Kernel internal interface to send a mailbox commandh]h3Kernel internal interface to send a mailbox command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj٨jj٨jjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``struct cxl_mbox_cmd *mbox_cmd`` initialized command to execute **Context** Any context. **Return** * %>=0 - Number of bytes returned in **out**. * ``-E2BIG`` - Payload is too large for hardware. * ``-EBUSY`` - Couldn't acquire exclusive mailbox access. * ``-EFAULT`` - Hardware error occurred. * ``-ENXIO`` - Command completed, but device reported an error. * ``-EIO`` - Unexpected output size. **Description** Mailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubjo)}(hhh](jt)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](jz)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubj)}(hhh]j])}(hCXL mailbox contexth]hCXL mailbox context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hA``struct cxl_mbox_cmd *mbox_cmd`` initialized command to execute h](jz)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hj;h]hstruct cxl_mbox_cmd *mbox_cmd}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj5ubj)}(hhh]j])}(hinitialized command to executeh]hinitialized command to execute}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjPhKhjQubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshjPhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjݨubj])}(h **Context**h]j)}(hjvh]hContext}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubj])}(h Any context.h]h Any context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubh block_quote)}(hX8* %>=0 - Number of bytes returned in **out**. * ``-E2BIG`` - Payload is too large for hardware. * ``-EBUSY`` - Couldn't acquire exclusive mailbox access. * ``-EFAULT`` - Hardware error occurred. * ``-ENXIO`` - Command completed, but device reported an error. * ``-EIO`` - Unexpected output size. h]j)}(hhh](j)}(h0%>=0 - Number of bytes returned in **out**.h]j])}(hjh](h(%>=0 - Number of bytes returned in }(hjhhhNhNubj)}(h**out**h]hout}(hjǩhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1``-E2BIG`` - Payload is too large for hardware.h]j])}(hjh](j)}(h ``-E2BIG``h]h-E2BIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh' - Payload is too large for hardware.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h9``-EBUSY`` - Couldn't acquire exclusive mailbox access.h]j])}(hjh](j)}(h ``-EBUSY``h]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh1 - Couldn’t acquire exclusive mailbox access.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'``-EFAULT`` - Hardware error occurred.h]j])}(hj4h](j)}(h ``-EFAULT``h]h-EFAULT}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh - Hardware error occurred.}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj2ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h?``-ENXIO`` - Command completed, but device reported an error.h]j])}(hjZh](j)}(h ``-ENXIO``h]h-ENXIO}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh5 - Command completed, but device reported an error.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjXubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'``-EIO`` - Unexpected output size. h]j])}(h&``-EIO`` - Unexpected output size.h](j)}(h``-EIO``h]h-EIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Unexpected output size.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj~ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjߩhKhjubah}(h]h ]h"]h$]h&]uh1jhjߩhKhjݨubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubj])}(hMailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.h]hMailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.}(hjɪhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjݨubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*cxl_payload_from_user_allowed (C function)c.cxl_payload_from_user_allowedhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hAbool cxl_payload_from_user_allowed (u16 opcode, void *payload_in)h]j.)}(h@bool cxl_payload_from_user_allowed(u16 opcode, void *payload_in)h](j4)}(hj^h]hbool}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM7ubjW)}(hcxl_payload_from_user_allowedh]j])}(hcxl_payload_from_user_allowedh]hcxl_payload_from_user_allowed}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM7ubjv)}(h(u16 opcode, void *payload_in)h](j|)}(h u16 opcodeh](h)}(hhh]j])}(hu16h]hu16}(hj7hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj4ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj9modnameN classnameNjj)}j]j)}jjsbc.cxl_payload_from_user_allowedasbuh1hhj0ubjF)}(h h]h }(hjWhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj0ubj])}(hopcodeh]hopcode}(hjehhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj0ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj,ubj|)}(hvoid *payload_inh](j4)}(hvoidh]hvoid}(hj~hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjzubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjzubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj])}(h payload_inh]h payload_in}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjzubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj,ubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM7ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM7ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM7hjhhubj)}(hhh]j])}(hCheck contents of in_payload.h]hCheck contents of in_payload.}(hjѫhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7hjΫhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``u16 opcode`` The mailbox command opcode. ``void *payload_in`` Pointer to the input payload passed in from user space. **Return** * true - payload_in passes check for **opcode**. * false - payload_in contains invalid or unsupported values. **Description** The driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate. The specific checks are determined by the opcode.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjubjo)}(hhh](jt)}(h+``u16 opcode`` The mailbox command opcode. h](jz)}(h``u16 opcode``h]j)}(hjh]h u16 opcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM8hj ubj)}(hhh]j])}(hThe mailbox command opcode.h]hThe mailbox command opcode.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj'hM8hj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj'hM8hj ubjt)}(hM``void *payload_in`` Pointer to the input payload passed in from user space. h](jz)}(h``void *payload_in``h]j)}(hjKh]hvoid *payload_in}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM9hjEubj)}(hhh]j])}(h7Pointer to the input payload passed in from user space.h]h7Pointer to the input payload passed in from user space.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`hM9hjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jshj`hM9hj ubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjubj)}(hw* true - payload_in passes check for **opcode**. * false - payload_in contains invalid or unsupported values. h]j)}(hhh](j)}(h3true - payload_in passes check for **opcode**.h]j])}(hjh](h(true - payload_in passes check for }(hjhhhNhNubj)}(h **opcode**h]hopcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h?false - payload_in contains invalid or unsupported values. h]j])}(h>false - payload_in contains invalid or unsupported values.h]h>false - payload_in contains invalid or unsupported values.}(hjѬhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjͬubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjƬhM;hjubah}(h]h ]h"]h$]h&]uh1jhjƬhM;hjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hjubj])}(hXpThe driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate.h]hXpThe driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjubj])}(h1The specific checks are determined by the opcode.h]h1The specific checks are determined by the opcode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMFhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'cxl_validate_cmd_from_user (C function)c.cxl_validate_cmd_from_userhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hint cxl_validate_cmd_from_user (struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h]j.)}(hint cxl_validate_cmd_from_user(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](j4)}(hinth]hint}(hjHhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjDhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjF)}(h h]h }(hjWhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjDhhhjVhMubjW)}(hcxl_validate_cmd_from_userh]j])}(hcxl_validate_cmd_from_userh]hcxl_validate_cmd_from_user}(hjihhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjeubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjDhhhjVhMubjv)}(hf(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](j|)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjksbc.cxl_validate_cmd_from_userasbuh1hhjubjF)}(h h]h }(hjíhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjѭhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hmbox_cmdh]hmbox_cmd}(hjޭhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj}ubj|)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_validate_cmd_from_userasbuh1hhjubjF)}(h h]h }(hj3hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcxl_mboxh]hcxl_mbox}(hjNhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj}ubj|)}(h'const struct cxl_send_command *send_cmdh](j)}(hjeUh]hconst}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubjF)}(h h]h }(hjthhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjcubj)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjcubh)}(hhh]j])}(hcxl_send_commandh]hcxl_send_command}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_validate_cmd_from_userasbuh1hhjcubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjcubj)}(hjh]h*}(hj̮hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj])}(hsend_cmdh]hsend_cmd}(hjٮhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjcubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj}ubeh}(h]h ]h"]h$]h&]hhuh1juhjDhhhjVhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj@hhhjVhMubah}(h]j;ah ](jjeh"]h$]h&]jj)jhuh1j'hjVhMhj=hhubj)}(hhh]j])}(h&Check fields for CXL_MEM_SEND_COMMAND.h]h&Check fields for CXL_MEM_SEND_COMMAND.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhj=hhhjVhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_mbox_cmd *mbox_cmd`` Sanitized and populated :c:type:`struct cxl_mbox_cmd `. ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``const struct cxl_send_command *send_cmd`` :c:type:`struct cxl_send_command ` copied in from userspace. **Return** * ``0`` - **out_cmd** is ready to send. * ``-ENOTTY`` - Invalid command specified. * ``-EINVAL`` - Reserved fields or invalid values were used. * ``-ENOMEM`` - Input or output buffer wasn't sized properly. * ``-EPERM`` - Attempted to use a protected command. * ``-EBUSY`` - Kernel has claimed exclusive access to this opcode **Description** The result of this command is a fully validated command in **mbox_cmd** that is safe to send to the hardware.h](j])}(h**Parameters**h]j)}(hj%h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubjo)}(hhh](jt)}(hh``struct cxl_mbox_cmd *mbox_cmd`` Sanitized and populated :c:type:`struct cxl_mbox_cmd `. h](jz)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hjDh]hstruct cxl_mbox_cmd *mbox_cmd}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj>ubj)}(hhh]j])}(hESanitized and populated :c:type:`struct cxl_mbox_cmd `.h](hSanitized and populated }(hj]hhhNhNubh)}(h,:c:type:`struct cxl_mbox_cmd `h]j)}(hjgh]hstruct cxl_mbox_cmd}(hjihhhNhNubah}(h]h ](xrefjc-typeeh"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]refdoc"driver-api/cxl/theory-of-operation refdomainjreftypetype refexplicitrefwarnjj)}j]sb reftarget cxl_mbox_cmduh1hhjYhMhj]ubh.}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjYhMhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshjYhMhj;ubjt)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](jz)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh]j])}(hCXL mailbox contexth]hCXL mailbox context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhj;ubjt)}(h{``const struct cxl_send_command *send_cmd`` :c:type:`struct cxl_send_command ` copied in from userspace. h](jz)}(h+``const struct cxl_send_command *send_cmd``h]j)}(hj߯h]h'const struct cxl_send_command *send_cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjݯubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjٯubj)}(hhh]j])}(hN:c:type:`struct cxl_send_command ` copied in from userspace.h](h)}(h4:c:type:`struct cxl_send_command `h]j)}(hjh]hstruct cxl_send_command}(hjhhhNhNubah}(h]h ](jsjc-typeeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypetype refexplicitrefwarnjjjcxl_send_commanduh1hhjhMhjubh copied in from userspace.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjٯubeh}(h]h ]h"]h$]h&]uh1jshjhMhj;ubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hj9h]hReturn}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hXS* ``0`` - **out_cmd** is ready to send. * ``-ENOTTY`` - Invalid command specified. * ``-EINVAL`` - Reserved fields or invalid values were used. * ``-ENOMEM`` - Input or output buffer wasn't sized properly. * ``-EPERM`` - Attempted to use a protected command. * ``-EBUSY`` - Kernel has claimed exclusive access to this opcode h]j)}(hhh](j)}(h,``0`` - **out_cmd** is ready to send.h]j])}(hjXh](j)}(h``0``h]h0}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh - }(hjZhhhNhNubj)}(h **out_cmd**h]hout_cmd}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh is ready to send.}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjVubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(h)``-ENOTTY`` - Invalid command specified.h]j])}(hjh](j)}(h ``-ENOTTY``h]h-ENOTTY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Invalid command specified.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(h;``-EINVAL`` - Reserved fields or invalid values were used.h]j])}(hjh](j)}(h ``-EINVAL``h]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh0 - Reserved fields or invalid values were used.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(h<``-ENOMEM`` - Input or output buffer wasn't sized properly.h]j])}(hjܰh](j)}(h ``-ENOMEM``h]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjްubh3 - Input or output buffer wasn’t sized properly.}(hjްhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjڰubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(h4``-EPERM`` - Attempted to use a protected command.h]j])}(hjh](j)}(h ``-EPERM``h]h-EPERM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh* - Attempted to use a protected command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hB``-EBUSY`` - Kernel has claimed exclusive access to this opcode h]j])}(hA``-EBUSY`` - Kernel has claimed exclusive access to this opcodeh](j)}(h ``-EBUSY``h]h-EBUSY}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubh7 - Kernel has claimed exclusive access to this opcode}(hj*hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj&ubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]jjuh1jhjhMhjOubah}(h]h ]h"]h$]h&]uh1jhjhMhjubj])}(h**Description**h]j)}(hj[h]h Description}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj])}(hmThe result of this command is a fully validated command in **mbox_cmd** that is safe to send to the hardware.h](h;The result of this command is a fully validated command in }(hjqhhhNhNubj)}(h **mbox_cmd**h]hmbox_cmd}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubh& that is safe to send to the hardware.}(hjqhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)handle_mailbox_cmd_from_user (C function)c.handle_mailbox_cmd_from_userhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hint handle_mailbox_cmd_from_user (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h]j.)}(hint handle_mailbox_cmd_from_user(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM7ubjW)}(hhandle_mailbox_cmd_from_userh]j])}(hhandle_mailbox_cmd_from_userh]hhandle_mailbox_cmd_from_user}(hjӱhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjϱubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM7ubjv)}(hj(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](j|)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(h cxl_mailboxh]h cxl_mailbox}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjձsbc.handle_mailbox_cmd_from_userasbuh1hhjubjF)}(h h]h }(hj-hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcxl_mboxh]hcxl_mbox}(hjHhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubjF)}(h h]h }(hjnhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj]ubh)}(hhh]j])}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj|ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)c.handle_mailbox_cmd_from_userasbuh1hhj]ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj]ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj])}(hmbox_cmdh]hmbox_cmd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj]ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(hu64 out_payloadh](h)}(hhh]j])}(hu64h]hu64}(hjԲhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjѲubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjֲmodnameN classnameNjj)}j]j)c.handle_mailbox_cmd_from_userasbuh1hhjͲubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjͲubj])}(h out_payloadh]h out_payload}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjͲubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(h s32 *size_outh](h)}(hhh]j])}(hs32h]hs32}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)c.handle_mailbox_cmd_from_userasbuh1hhjubjF)}(h h]h }(hj:hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hsize_outh]hsize_out}(hjUhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(h u32 *retvalh](h)}(hhh]j])}(hu32h]hu32}(hjqhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjnubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]j)c.handle_mailbox_cmd_from_userasbuh1hhjjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj])}(hretvalh]hretval}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM7ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM7ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM7hjhhubj)}(hhh]j])}(h)Dispatch a mailbox command for userspace.h]h)Dispatch a mailbox command for userspace.}(hjԳhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7hjѳhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` The mailbox context for the operation. ``struct cxl_mbox_cmd *mbox_cmd`` The validated mailbox command. ``u64 out_payload`` Pointer to userspace's output payload. ``s32 *size_out`` (Input) Max payload size to copy out. (Output) Payload size hardware generated. ``u32 *retval`` Hardware generated return code from the operation. **Return** * ``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful. * ``-ENOMEM`` - Couldn't allocate a bounce buffer. * ``-EFAULT`` - Something happened with copy_to/from_user. * ``-EINTR`` - Mailbox acquisition interrupted. * ``-EXXX`` - Transaction level failures. **Description** Dispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace. See cxl_send_cmd().h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjubjo)}(hhh](jt)}(hH``struct cxl_mailbox *cxl_mbox`` The mailbox context for the operation. h](jz)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM8hjubj)}(hhh]j])}(h&The mailbox context for the operation.h]h&The mailbox context for the operation.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj*hM8hj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj*hM8hj ubjt)}(hA``struct cxl_mbox_cmd *mbox_cmd`` The validated mailbox command. h](jz)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hjNh]hstruct cxl_mbox_cmd *mbox_cmd}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM9hjHubj)}(hhh]j])}(hThe validated mailbox command.h]hThe validated mailbox command.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjchM9hjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jshjchM9hj ubjt)}(h;``u64 out_payload`` Pointer to userspace's output payload. h](jz)}(h``u64 out_payload``h]j)}(hjh]hu64 out_payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM:hjubj)}(hhh]j])}(h&Pointer to userspace's output payload.h]h(Pointer to userspace’s output payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM:hj ubjt)}(hb``s32 *size_out`` (Input) Max payload size to copy out. (Output) Payload size hardware generated. h](jz)}(h``s32 *size_out``h]j)}(hjh]h s32 *size_out}(hj´hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjubj)}(hhh]j])}(hO(Input) Max payload size to copy out. (Output) Payload size hardware generated.h]hO(Input) Max payload size to copy out. (Output) Payload size hardware generated.}(hjٴhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjִubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjմhM<hj ubjt)}(hC``u32 *retval`` Hardware generated return code from the operation. h](jz)}(h``u32 *retval``h]j)}(hjh]h u32 *retval}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM=hjubj)}(hhh]j])}(h2Hardware generated return code from the operation.h]h2Hardware generated return code from the operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM=hj ubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hj5h]hReturn}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjubj)}(hX* ``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful. * ``-ENOMEM`` - Couldn't allocate a bounce buffer. * ``-EFAULT`` - Something happened with copy_to/from_user. * ``-EINTR`` - Mailbox acquisition interrupted. * ``-EXXX`` - Transaction level failures. h]j)}(hhh](j)}(h``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful.h]jo)}(hhh]jt)}(h``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful.h](jz)}(hF``0`` - Mailbox transaction succeeded. This implies the mailboxh](j)}(h``0``h]h0}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubhA - Mailbox transaction succeeded. This implies the mailbox}(hj]hhhNhNubeh}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hjYubj)}(hhh]j])}(hMprotocol completed successfully not that the operation itself was successful.h]hMprotocol completed successfully not that the operation itself was successful.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjyhM@hjzubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jshjyhM@hjVubah}(h]h ]h"]h$]h&]uh1jnhjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(h1``-ENOMEM`` - Couldn't allocate a bounce buffer.h]j])}(hjh](j)}(h ``-ENOMEM``h]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh( - Couldn’t allocate a bounce buffer.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(h9``-EFAULT`` - Something happened with copy_to/from_user.h]j])}(hj˵h](j)}(h ``-EFAULT``h]h-EFAULT}(hjеhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͵ubh. - Something happened with copy_to/from_user.}(hj͵hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMChjɵubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(h/``-EINTR`` - Mailbox acquisition interrupted.h]j])}(hjh](j)}(h ``-EINTR``h]h-EINTR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh% - Mailbox acquisition interrupted.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMDhjubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(h+``-EXXX`` - Transaction level failures. h]j])}(h*``-EXXX`` - Transaction level failures.h](j)}(h ``-EXXX``h]h-EXXX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh! - Transaction level failures.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMEhjubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]jjuh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjKubah}(h]h ]h"]h$]h&]uh1jhjBhM?hjubj])}(h**Description**h]j)}(hjKh]h Description}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhjubj])}(hiDispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace.h]hiDispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMHhjubj])}(hSee cxl_send_cmd().h]hSee cxl_send_cmd().}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_walk_cel (C function)c.cxl_walk_celhNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hFvoid cxl_walk_cel (struct cxl_memdev_state *mds, size_t size, u8 *cel)h]j.)}(hEvoid cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](j4)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMubjW)}(h cxl_walk_celh]j])}(h cxl_walk_celh]h cxl_walk_cel}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMubjv)}(h4(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjܶhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjضubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjضubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jj¶sbc.cxl_walk_celasbuh1hhjضubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjضubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjضubj])}(hmdsh]hmds}(hj5hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjضubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjԶubj|)}(h size_t sizeh](h)}(hhh]j])}(hsize_th]hsize_t}(hjQhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjNubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjSmodnameN classnameNjj)}j]jc.cxl_walk_celasbuh1hhjJubjF)}(h h]h }(hjohhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjJubj])}(hsizeh]hsize}(hj}hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjJubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjԶubj|)}(hu8 *celh](h)}(hhh]j])}(hu8h]hu8}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_walk_celasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjŷhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcelh]hcel}(hjҷhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjԶubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMhjhhubj)}(hhh]j])}(h%Walk through the Command Effects Log.h]h%Walk through the Command Effects Log.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hXH**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation ``size_t size`` Length of the Command Effects Log. ``u8 *cel`` CEL **Description** Iterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubjo)}(hhh](jt)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj=h]hstruct cxl_memdev_state *mds}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj7ubj)}(hhh]j])}(h!The driver data for the operationh]h!The driver data for the operation}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjRhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jshjRhMhj4ubjt)}(h3``size_t size`` Length of the Command Effects Log. h](jz)}(h``size_t size``h]j)}(hjvh]h size_t size}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjpubj)}(hhh]j])}(h"Length of the Command Effects Log.h]h"Length of the Command Effects Log.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jshjhMhj4ubjt)}(h``u8 *cel`` CEL h](jz)}(h ``u8 *cel``h]j)}(hjh]hu8 *cel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh]j])}(hCELh]hCEL}(hjȸhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjĸhMhjŸubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjĸhMhj4ubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj])}(hIterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.h]hIterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_enumerate_cmds (C function)c.cxl_enumerate_cmdshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h5int cxl_enumerate_cmds (struct cxl_memdev_state *mds)h]j.)}(h4int cxl_enumerate_cmds(struct cxl_memdev_state *mds)h](j4)}(hinth]hint}(hj/hhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hj+hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<ubjF)}(h h]h }(hj>hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj+hhhj=hM<ubjW)}(hcxl_enumerate_cmdsh]j])}(hcxl_enumerate_cmdsh]hcxl_enumerate_cmds}(hjPhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjLubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj+hhhj=hM<ubjv)}(h(struct cxl_memdev_state *mds)h]j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubjF)}(h h]h }(hjyhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjRsbc.cxl_enumerate_cmdsasbuh1hhjhubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj])}(hmdsh]hmds}(hjŹhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjhubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjdubah}(h]h ]h"]h$]h&]hhuh1juhj+hhhj=hM<ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj'hhhj=hM<ubah}(h]j"ah ](jjeh"]h$]h&]jj)jhuh1j'hj=hM<hj$hhubj)}(hhh]j])}(h Enumerate commands for a device.h]h Enumerate commands for a device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjhhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj=hM<ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hXM**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation **Description** Returns 0 if enumerate completed successfully. CXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the **mds**.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hj ubjo)}(hhh]jt)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj0h]hstruct cxl_memdev_state *mds}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM=hj*ubj)}(hhh]j])}(h!The driver data for the operationh]h!The driver data for the operation}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjEhM=hjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jshjEhM=hj'ubah}(h]h ]h"]h$]h&]uh1jnhj ubj])}(h**Description**h]j)}(hjkh]h Description}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hj ubj])}(h.Returns 0 if enumerate completed successfully.h]h.Returns 0 if enumerate completed successfully.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hj ubj])}(hCXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the **mds**.h](hCXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the }(hjhhhNhNubj)}(h**mds**h]hmds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMAhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j&cxl_mem_get_event_records (C function)c.cxl_mem_get_event_recordshNtauh1jhj.hhhNhNubj#)}(hhh](j()}(hIvoid cxl_mem_get_event_records (struct cxl_memdev_state *mds, u32 status)h]j.)}(hHvoid cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status)h](j4)}(hvoidh]hvoid}(hjѺhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjͺhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjͺhhhjߺhM>ubjW)}(hcxl_mem_get_event_recordsh]j])}(hcxl_mem_get_event_recordsh]hcxl_mem_get_event_records}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjͺhhhjߺhM>ubjv)}(h*(struct cxl_memdev_state *mds, u32 status)h](j|)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj ubh)}(hhh]j])}(hcxl_memdev_stateh]hcxl_memdev_state}(hj,hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj)ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj.modnameN classnameNjj)}j]j)}jjsbc.cxl_mem_get_event_recordsasbuh1hhj ubjF)}(h h]h }(hjLhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj ubj)}(hjh]h*}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj])}(hmdsh]hmds}(hjghhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubj|)}(h u32 statush](h)}(hhh]j])}(hu32h]hu32}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jHc.cxl_mem_get_event_recordsasbuh1hhj|ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj|ubj])}(hstatush]hstatus}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj|ubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubeh}(h]h ]h"]h$]h&]hhuh1juhjͺhhhjߺhM>ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjɺhhhjߺhM>ubah}(h]jĺah ](jjeh"]h$]h&]jj)jhuh1j'hjߺhM>hjƺhhubj)}(hhh]j])}(h!Get Event Records from the deviceh]h!Get Event Records from the device}(hjٻhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hjֻhhubah}(h]h ]h"]h$]h&]uh1jhjƺhhhjߺhM>ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhj.hNhNubj)}(hX**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation ``u32 status`` Event Status register value identifying which events are available. **Description** Retrieve all event records available on the device, report them as trace events, and clear them. See CXL rev 3.0 **8.2.9.2.2** Get Event Records See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubjo)}(hhh](jt)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hjh]hstruct cxl_memdev_state *mds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjubj)}(hhh]j])}(h!The driver data for the operationh]h!The driver data for the operation}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/hM?hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj/hM?hjubjt)}(hS``u32 status`` Event Status register value identifying which events are available. h](jz)}(h``u32 status``h]j)}(hjSh]h u32 status}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hjMubj)}(hhh]j])}(hCEvent Status register value identifying which events are available.h]hCEvent Status register value identifying which events are available.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhhM@hjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jshjhhM@hjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubj])}(h`Retrieve all event records available on the device, report them as trace events, and clear them.h]h`Retrieve all event records available on the device, report them as trace events, and clear them.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubj])}(haSee CXL rev 3.0 **8.2.9.2.2** Get Event Records See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](hSee CXL rev 3.0 }(hjhhhNhNubj)}(h **8.2.9.2.2**h]h 8.2.9.2.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh# Get Event Records See CXL rev 3.0 }(hjhhhNhNubj)}(h **8.2.9.2.3**h]h 8.2.9.2.3}(hjͼhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh Clear Event Records}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMEhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj.hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'cxl_mem_get_partition_info (C function)c.cxl_mem_get_partition_infohNtauh1jhj.hhhNhNubj#)}(hhh](j()}(h=int cxl_mem_get_partition_info (struct cxl_memdev_state *mds)h]j.)}(hport to add a new region reference ‘struct cxl_region_ref’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM!hjubjt)}(h9``struct cxl_region *cxlr`` region to attach to **port** h](jz)}(h``struct cxl_region *cxlr``h]j)}(hjh]hstruct cxl_region *cxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM"hjubj)}(hhh]j])}(hregion to attach to **port**h](hregion to attach to }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j\hjhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM"hjubjt)}(hi``struct cxl_endpoint_decoder *cxled`` endpoint decoder used to create or further pin a region reference h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hj*h]h"struct cxl_endpoint_decoder *cxled}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM#hj$ubj)}(hhh]j])}(hAendpoint decoder used to create or further pin a region referenceh]hAendpoint decoder used to create or further pin a region reference}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hM#hj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jshj?hM#hjubjt)}(h9``int pos`` interleave position of **cxled** in **cxlr** h](jz)}(h ``int pos``h]j)}(hjch]hint pos}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM$hj]ubj)}(hhh]j])}(h,interleave position of **cxled** in **cxlr**h](hinterleave position of }(hj|hhhNhNubj)}(h **cxled**h]hcxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh in }(hj|hhhNhNubj)}(h**cxlr**h]hcxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j\hjxhM$hjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jshjxhM$hjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM&hjubj])}(hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.h]hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM&hjubj])}(hThe steps are:h]hThe steps are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM*hjubj)}(hhh](j)}(h[validate that there are no other regions with a higher HPA already associated with **port**h]j])}(h[validate that there are no other regions with a higher HPA already associated with **port**h](hSvalidate that there are no other regions with a higher HPA already associated with }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM,hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hestablish a region reference if one is not already present - additionally allocate a decoder instance that will host **cxlr** on **port** h](j])}(h:establish a region reference if one is not already presenth]h:establish a region reference if one is not already present}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM.hjubj)}(hhh]j)}(hMadditionally allocate a decoder instance that will host **cxlr** on **port** h]j])}(hLadditionally allocate a decoder instance that will host **cxlr** on **port**h](h8additionally allocate a decoder instance that will host }(hj6hhhNhNubj)}(h**cxlr**h]hcxlr}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh on }(hj6hhhNhNubj)}(h**port**h]hport}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM0hj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]jjuh1jhjdhM0hjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h(pin the region reference by the endpointh]j])}(hjyh]h(pin the region reference by the endpoint}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM3hjwubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h]j])}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h](h account for how many entries in }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh@’s target list are needed to cover all of the added endpoints.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhM,hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$cxl_calc_interleave_pos (C function)c.cxl_calc_interleave_poshNtauh1jhjhhhNhNubj#)}(hhh](j()}(h@int cxl_calc_interleave_pos (struct cxl_endpoint_decoder *cxled)h]j.)}(h?int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhMubjW)}(hcxl_calc_interleave_posh]j])}(hcxl_calc_interleave_posh]hcxl_calc_interleave_pos}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhMubjv)}(h$(struct cxl_endpoint_decoder *cxled)h]j|)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hj*hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj;hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj8ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj=modnameN classnameNjj)}j]j)}jjsbc.cxl_calc_interleave_posasbuh1hhjubjF)}(h h]h }(hj[hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcxledh]hcxled}(hjvhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubah}(h]h ]h"]h$]h&]hhuh1juhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhMhjhhubj)}(hhh]j])}(h*calculate an endpoint position in a regionh]h*calculate an endpoint position in a region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhjhNhNubj)}(hX**Parameters** ``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region **Description** The endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation: position = position * parent_ways + parent_pos; ...where **position** is inferred from switch and root decoder target lists. **Return** position >= 0 on success -ENXIO on failureh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM#hjubjo)}(hhh]jt)}(hO``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjh]h"struct cxl_endpoint_decoder *cxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(h'endpoint decoder member of given regionh]h'endpoint decoder member of given region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM hjubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM"hjubj])}(hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:h]hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM"hjubj)}(h0position = position * parent_ways + parent_pos; h]j])}(h/position = position * parent_ways + parent_pos;h]h/position = position * parent_ways + parent_pos;}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM&hjAubah}(h]h ]h"]h$]h&]uh1jhjShM&hjubj])}(hL...where **position** is inferred from switch and root decoder target lists.h](h ...where }(hjZhhhNhNubj)}(h **position**h]hposition}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubh7 is inferred from switch and root decoder target lists.}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM(hjubj])}(h **Return**h]j)}(hj}h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM*hjubjo)}(hhh]jt)}(h*position >= 0 on success -ENXIO on failureh](jz)}(hposition >= 0 on successh]hposition >= 0 on success}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM*hjubj)}(hhh]j])}(h-ENXIO on failureh]h-ENXIO on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM*hjubah}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j devm_cxl_add_region (C function)c.devm_cxl_add_regionhNtauh1jhjhhhNhNubj#)}(hhh](j()}(hstruct cxl_region * devm_cxl_add_region (struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h]j.)}(hstruct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM ubh)}(hhh]j])}(h cxl_regionh]h cxl_region}(hj hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jdevm_cxl_add_regionsbc.devm_cxl_add_regionasbuh1hhjhhhjhM ubjF)}(h h]h }(hj-hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM ubj)}(hjh]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhM ubjW)}(hdevm_cxl_add_regionh]j])}(hj*h]hdevm_cxl_add_region}(hjLhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjHubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM ubjv)}(hb(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j|)}(hstruct cxl_root_decoder *cxlrdh](j)}(hjh]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubjF)}(h h]h }(hjthhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjcubh)}(hhh]j])}(hcxl_root_decoderh]hcxl_root_decoder}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j(c.devm_cxl_add_regionasbuh1hhjcubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjcubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjcubj])}(hcxlrdh]hcxlrd}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjcubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj_ubj|)}(hint idh](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj])}(hidh]hid}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj_ubj|)}(henum cxl_partition_mode modeh](j)}(hjSh]henum}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(hcxl_partition_modeh]hcxl_partition_mode}(hj*hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hj'ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,modnameN classnameNjj)}j]j(c.devm_cxl_add_regionasbuh1hhjubjF)}(h h]h }(hjHhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj])}(hmodeh]hmode}(hjVhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj_ubj|)}(henum cxl_decoder_type typeh](j)}(hjSh]henum}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubjF)}(h h]h }(hj|hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjkubh)}(hhh]j])}(hcxl_decoder_typeh]hcxl_decoder_type}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j(c.devm_cxl_add_regionasbuh1hhjkubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjkubj])}(htypeh]htype}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjkubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hj_ubeh}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM hjhhubj)}(hhh]j])}(hAdds a region to a decoderh]hAdds a region to a decoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j"hhhjhNhNubj)}(hXl**Parameters** ``struct cxl_root_decoder *cxlrd`` root decoder ``int id`` memregion id to create, or memregion_free() on failure ``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region ``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) **Description** This is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**. **Return** 0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubjo)}(hhh](jt)}(h0``struct cxl_root_decoder *cxlrd`` root decoder h](jz)}(h"``struct cxl_root_decoder *cxlrd``h]j)}(hj$h]hstruct cxl_root_decoder *cxlrd}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(h root decoderh]h root decoder}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hM hj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj9hM hjubjt)}(hB``int id`` memregion id to create, or memregion_free() on failure h](jz)}(h ``int id``h]j)}(hj]h]hint id}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjWubj)}(hhh]j])}(h6memregion id to create, or memregion_free() on failureh]h6memregion id to create, or memregion_free() on failure}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjrhM hjsubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jshjrhM hjubjt)}(hO``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region h](jz)}(h ``enum cxl_partition_mode mode``h]j)}(hjh]henum cxl_partition_mode mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(h-mode for the endpoint decoders of this regionh]h-mode for the endpoint decoders of this region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM hjubjt)}(hd``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) h](jz)}(h``enum cxl_decoder_type type``h]j)}(hjh]henum cxl_decoder_type type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(hDselect whether this is an expander or accelerator (type-2 or type-3)h]hDselect whether this is an expander or accelerator (type-2 or type-3)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM hjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj])}(hwThis is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**.h](hmThis is the second step of region initialization. Regions exist within an address space which is mapped by a }(hj hhhNhNubj)}(h **cxlrd**h]hcxlrd}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj])}(h **Return**h]j)}(hjCh]hReturn}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj])}(h0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](h!0 if the region was added to the }(hjYhhhNhNubj)}(h **cxlrd**h]hcxlrd}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubho, else returns negative error code. The region will be named “regionZ” where Z is the unique region number.}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%devm_cxl_add_pmem_region (C function)c.devm_cxl_add_pmem_regionhNtauh1jhjhhhNhNubj#)}(hhh](j()}(h6int devm_cxl_add_pmem_region (struct cxl_region *cxlr)h]j.)}(h5int devm_cxl_add_pmem_region(struct cxl_region *cxlr)h](j4)}(hinth]hint}(hjhhhNhNubah}(h]h ]j@ah"]h$]h&]uh1j3hjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM9 ubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjhhhjhM9 ubjW)}(hdevm_cxl_add_pmem_regionh]j])}(hdevm_cxl_add_pmem_regionh]hdevm_cxl_add_pmem_region}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjhhhjhM9 ubjv)}(h(struct cxl_region *cxlr)h]j|)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubh)}(hhh]j])}(h cxl_regionh]h cxl_region}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.devm_cxl_add_pmem_regionasbuh1hhjubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj])}(hcxlrh]hcxlr}(hj0hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j{hjubah}(h]h ]h"]h$]h&]hhuh1juhjhhhjhM9 ubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjhhhjhM9 ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j'hjhM9 hjhhubj)}(hhh]j])}(h$add a cxl_region-to-nd_region bridgeh]h$add a cxl_region-to-nd_region bridge}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM9 hjWhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM9 ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjrjjrjjjuh1j"hhhjhNhNubj)}(h**Parameters** ``struct cxl_region *cxlr`` parent CXL region for this pmem region bridge device **Return** 0 on success negative error code on failure.h](j])}(h**Parameters**h]j)}(hj|h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM= hjvubjo)}(hhh]jt)}(hQ``struct cxl_region *cxlr`` parent CXL region for this pmem region bridge device h](jz)}(h``struct cxl_region *cxlr``h]j)}(hjh]hstruct cxl_region *cxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM: hjubj)}(hhh]j])}(h4parent CXL region for this pmem region bridge deviceh]h4parent CXL region for this pmem region bridge device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM: hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM: hjubah}(h]h ]h"]h$]h&]uh1jnhjvubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM< hjvubj])}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM< hjvubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h] cxl-regionsah ]h"] cxl regionsah$]h&]uh1jGhj/hhhhhMubeh}(h]driver-infrastructureah ]h"]driver infrastructureah$]h&]uh1jGhjIhhhhhM;ubjH)}(hhh](jM)}(hExternal Interfacesh]hExternal Interfaces}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhMubjH)}(hhh](jM)}(hCXL IOCTL Interfaceh]hCXL IOCTL Interface}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj#hhhhhMubj])}(hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.h]hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:497: ./include/uapi/linux/cxl_mem.hhK hj#hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_command_info (C struct)c.cxl_command_infohNtauh1jhj#hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhNubj#)}(hhh](j()}(hcxl_command_infoh]j.)}(hstruct cxl_command_infoh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYhhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF)}(h h]h }(hjkhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjYhhhjjhKubjW)}(hcxl_command_infoh]j])}(hjWh]hcxl_command_info}(hj}hhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjyubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjYhhhjjhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjUhhhjjhKubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1j'hjjhKhjRhhubj)}(hhh]j])}(h*Command information returned from a query.h]h*Command information returned from a query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKfhjhhubah}(h]h ]h"]h$]h&]uh1jhjRhhhjjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j"hhhj#hjQhNubj)}(hX**Definition**:: struct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; }; **Members** ``id`` ID number for the command. ``flags`` Flags that specify command behavior. CXL_MEM_COMMAND_FLAG_USER_ENABLED The given command id is supported by the driver and is supported by a related opcode on the device. CXL_MEM_COMMAND_FLAG_EXCLUSIVE Requests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space. ``size_in`` Expected input size, or ~0 if variable length. ``size_out`` Expected output size, or ~0 if variable length.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKjhjubj)}(hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };h]hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKlhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKvhjubjo)}(hhh](jt)}(h"``id`` ID number for the command. h](jz)}(h``id``h]j)}(hj h]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhhjubj)}(hhh]j])}(hID number for the command.h]hID number for the command.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj!hKhhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj!hKhhjubjt)}(hX``flags`` Flags that specify command behavior. CXL_MEM_COMMAND_FLAG_USER_ENABLED The given command id is supported by the driver and is supported by a related opcode on the device. CXL_MEM_COMMAND_FLAG_EXCLUSIVE Requests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space. h](jz)}(h ``flags``h]j)}(hjEh]hflags}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKuhj?ubj)}(hhh](j])}(h$Flags that specify command behavior.h]h$Flags that specify command behavior.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKihj[ubj])}(h!CXL_MEM_COMMAND_FLAG_USER_ENABLEDh]h!CXL_MEM_COMMAND_FLAG_USER_ENABLED}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKkhj[ubj])}(hcThe given command id is supported by the driver and is supported by a related opcode on the device.h]hcThe given command id is supported by the driver and is supported by a related opcode on the device.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKmhj[ubj])}(hCXL_MEM_COMMAND_FLAG_EXCLUSIVEh]hCXL_MEM_COMMAND_FLAG_EXCLUSIVE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKphj[ubj])}(hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.h]hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKrhj[ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshjZhKuhjubjt)}(h;``size_in`` Expected input size, or ~0 if variable length. h](jz)}(h ``size_in``h]j)}(hjh]hsize_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhjubj)}(hhh]j])}(h.Expected input size, or ~0 if variable length.h]h.Expected input size, or ~0 if variable length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKwhjubjt)}(h<``size_out`` Expected output size, or ~0 if variable length.h](jz)}(h ``size_out``h]j)}(hjh]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhjubj)}(hhh]j])}(h/Expected output size, or ~0 if variable length.h]h/Expected output size, or ~0 if variable length.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKxhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj hKwhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj#hhhjQhNubj])}(h**Description**h]j)}(hj7h]h Description}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK{hj#hhubj])}(hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.h]hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKyhj#hhubj)}(h_- **id** = 10 - **flags** = CXL_MEM_COMMAND_FLAG_ENABLED - **size_in** = ~0 - **size_out** = 0 h]j)}(hhh](j)}(h **id** = 10h]j])}(hjeh](j)}(h**id**h]hid}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubh = 10}(hjghhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK~hjcubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(h(**flags** = CXL_MEM_COMMAND_FLAG_ENABLEDh]j])}(hjh](j)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = CXL_MEM_COMMAND_FLAG_ENABLED}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(h**size_in** = ~0h]j])}(hjh](j)}(h **size_in**h]hsize_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = ~0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj`ubj)}(h**size_out** = 0 h]j])}(h**size_out** = 0h](j)}(h **size_out**h]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]jjuh1jhjhK~hj\ubah}(h]h ]h"]h$]h&]uh1jhjhK~hj#hhubj])}(h"See struct cxl_mem_query_commands.h]h"See struct cxl_mem_query_commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj#hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!cxl_mem_query_commands (C struct)c.cxl_mem_query_commandshNtauh1jhj#hhhjQhNubj#)}(hhh](j()}(hcxl_mem_query_commandsh]j.)}(hstruct cxl_mem_query_commandsh](j)}(hjh]hstruct}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF)}(h h]h }(hj>hhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhj,hhhj=hKubjW)}(hcxl_mem_query_commandsh]j])}(hj*h]hcxl_mem_query_commands}(hjPhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjLubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhj,hhhj=hKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hj(hhhj=hKubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1j'hj=hKhj%hhubj)}(hhh]j])}(hQuery supported commands.h]hQuery supported commands.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjohhubah}(h]h ]h"]h$]h&]uh1jhj%hhhj=hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j"hhhj#hjQhNubj)}(hX5**Definition**:: struct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; }; **Members** ``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. ``rsvd`` Reserved for future use. ``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };h]hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubjo)}(hhh](jt)}(h``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. h](jz)}(h``n_commands``h]j)}(hjh]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hIn/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands.h](hIn/out parameter. When }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhL is > 0, the driver will return min(num_support_commands, n_commands). When }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhA is 0, driver will return the number of total supported commands.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h"``rsvd`` Reserved for future use. h](jz)}(h``rsvd``h]j)}(hj=h]hrsvd}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj7ubj)}(hhh]j])}(hReserved for future use.h]hReserved for future use.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjRhKhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jshjRhKhjubjt)}(h``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](jz)}(h ``commands``h]j)}(hjvh]hcommands}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjpubj)}(hhh]j])}(hOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](hwOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj#hhhjQhNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj#hhubj])}(hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren't supported by either the driver, or the hardware are not returned in the query.h]hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren’t supported by either the driver, or the hardware are not returned in the query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj#hhubj])}(h **Examples**h]j)}(hjh]hExamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj#hhubj)}(h- { .n_commands = 0 } // Get number of supported commands - { .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands See struct cxl_command_info. h](j)}(hhh](j)}(h7{ .n_commands = 0 } // Get number of supported commandsh]j])}(hjh]h7{ .n_commands = 0 } // Get number of supported commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hV{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands h]j])}(hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commandsh]hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj&ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]jjuh1jhjhKhjubj])}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhj#hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_send_command (C struct)c.cxl_send_commandhNtauh1jhj#hhhjQhNubj#)}(hhh](j()}(hcxl_send_commandh]j.)}(hstruct cxl_send_commandh](j)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF)}(h h]h }(hjhhhNhNubah}(h]h ]jRah"]h$]h&]uh1jEhjohhhjhKubjW)}(hcxl_send_commandh]j])}(hjmh]hcxl_send_command}(hjhhhNhNubah}(h]h ]jiah"]h$]h&]uh1j\hjubah}(h]h ](jpjqeh"]h$]h&]hhuh1jVhjohhhjhKubeh}(h]h ]h"]h$]h&]hhj|uh1j-j}j~hjkhhhjhKubah}(h]jfah ](jjeh"]h$]h&]jj)jhuh1j'hjhKhjhhhubj)}(hhh]j])}(h"Send a command to a memory device.h]h"Send a command to a memory device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j"hhhj#hjQhNubj)}(hX **Definition**:: struct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; }; **Members** ``id`` The command to send to the memory device. This must be one of the commands returned by the query command. ``flags`` Flags for the command (input). ``{unnamed_union}`` anonymous ``raw`` Special fields for raw commands ``raw.opcode`` Opcode passed to hardware when using the RAW command. ``raw.rsvd`` Must be zero. ``rsvd`` Must be zero. ``retval`` Return value from the memory device (output). ``in`` Parameters associated with input payload. ``in.size`` Size of the payload to provide to the device (input). ``in.rsvd`` Must be zero. ``in.payload`` Pointer to memory for payload input, payload is little endian. ``out`` Parameters associated with output payload. ``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. ``out.rsvd`` Must be zero. ``out.payload`` Pointer to memory for payload output, payload is little endian.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };h]hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubjo)}(hhh](jt)}(hq``id`` The command to send to the memory device. This must be one of the commands returned by the query command. h](jz)}(h``id``h]j)}(hj"h]hid}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hiThe command to send to the memory device. This must be one of the commands returned by the query command.h]hiThe command to send to the memory device. This must be one of the commands returned by the query command.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj7hKhjubjt)}(h)``flags`` Flags for the command (input). h](jz)}(h ``flags``h]j)}(hj\h]hflags}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjVubj)}(hhh]j])}(hFlags for the command (input).h]hFlags for the command (input).}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjqhKhjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jshjqhKhjubjt)}(h``{unnamed_union}`` anonymous h](jz)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h(``raw`` Special fields for raw commands h](jz)}(h``raw``h]j)}(hjh]hraw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hSpecial fields for raw commandsh]hSpecial fields for raw commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hE``raw.opcode`` Opcode passed to hardware when using the RAW command. h](jz)}(h``raw.opcode``h]j)}(hjh]h raw.opcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h5Opcode passed to hardware when using the RAW command.h]h5Opcode passed to hardware when using the RAW command.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h``raw.rsvd`` Must be zero. h](jz)}(h ``raw.rsvd``h]j)}(hj@h]hraw.rsvd}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj:ubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjUhKhjVubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jshjUhKhjubjt)}(h``rsvd`` Must be zero. h](jz)}(h``rsvd``h]j)}(hjyh]hrsvd}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjsubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h9``retval`` Return value from the memory device (output). h](jz)}(h ``retval``h]j)}(hjh]hretval}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h-Return value from the memory device (output).h]h-Return value from the memory device (output).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h1``in`` Parameters associated with input payload. h](jz)}(h``in``h]j)}(hjh]hin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h)Parameters associated with input payload.h]h)Parameters associated with input payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hB``in.size`` Size of the payload to provide to the device (input). h](jz)}(h ``in.size``h]j)}(hj$h]hin.size}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h5Size of the payload to provide to the device (input).h]h5Size of the payload to provide to the device (input).}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hKhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj9hKhjubjt)}(h``in.rsvd`` Must be zero. h](jz)}(h ``in.rsvd``h]j)}(hj]h]hin.rsvd}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjWubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjrhKhjsubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jshjrhKhjubjt)}(hN``in.payload`` Pointer to memory for payload input, payload is little endian. h](jz)}(h``in.payload``h]j)}(hjh]h in.payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h>Pointer to memory for payload input, payload is little endian.h]h>Pointer to memory for payload input, payload is little endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h3``out`` Parameters associated with output payload. h](jz)}(h``out``h]j)}(hjh]hout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h*Parameters associated with output payload.h]h*Parameters associated with output payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hX``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. h](jz)}(h ``out.size``h]j)}(hjh]hout.size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.h]hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h``out.rsvd`` Must be zero. h](jz)}(h ``out.rsvd``h]j)}(hjBh]hout.rsvd}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj<ubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjWhKhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jshjWhKhjubjt)}(hO``out.payload`` Pointer to memory for payload output, payload is little endian.h](jz)}(h``out.payload``h]j)}(hj{h]h out.payload}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jyhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjuubj)}(hhh]j])}(h?Pointer to memory for payload output, payload is little endian.h]h?Pointer to memory for payload output, payload is little endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj#hhhjQhNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj#hhubj])}(hX/Mechanism for userspace to send a command to the hardware for processing. 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