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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h/Compute Express Link Driver Theory of Operationh]h/Compute Express Link Driver Theory of Operation}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh paragraph)}(hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device's contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.h]hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device’s contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj]hhubj\)}(hhh](ja)}(h The CXL Bush]h The CXL Bus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhKubjq)}(hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.h]hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hXPlatform firmware enumerates a menu of interleave options at the "CXL root port" (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example, platform firmware may say a given range only decodes to one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.h]hXPlatform firmware enumerates a menu of interleave options at the “CXL root port” (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example, platform firmware may say a given range only decodes to one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hX-Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test' module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints::h]hX4Here is a sample listing of a CXL topology defined by ‘cxl_test’. The ‘cxl_test’ module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK&hjhhubh literal_block)}(hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }h]hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK+hjhhubjq)}(hXIn that listing each "root", "port", and "endpoint" object correspond a kernel 'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to its descendants. So "root" claims non-PCIe enumerable platform decode ranges and decodes them to "ports", "ports" decode to "endpoints", and "endpoints" represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).h]hXIn that listing each “root”, “port”, and “endpoint” object correspond a kernel ‘struct cxl_port’ object. A ‘cxl_port’ is a device that can decode CXL.mem to its descendants. So “root” claims non-PCIe enumerable platform decode ranges and decodes them to “ports”, “ports” decode to “endpoints”, and “endpoints” represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hXContinuing the RAID analogy, disks have both topology metadata and on-device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.h]hXContinuing the RAID analogy, disks have both topology metadata and on-device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hThe port metadata and potential decode schemes that a given memory device may participate can be determined via a command like::h]hThe port metadata and potential decode schemes that a given memory device may participate can be determined via a command like:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubj)}(hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }h]hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubjq)}(hXH...which queries the CXL topology to ask "given CXL Memory Expander with a kernel device name of 'mem3' which platform level decode ranges may this device participate". A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resources it has. In this example mem3 can participate in one or more of a PMEM interleave that spans two Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.h]hXP...which queries the CXL topology to ask “given CXL Memory Expander with a kernel device name of ‘mem3’ which platform level decode ranges may this device participate”. A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resources it has. In this example mem3 can participate in one or more of a PMEM interleave that spans two Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjhhubjq)}(hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following::h]hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhMhjhhubj)}(hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]h]hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjhhubjq)}(hL...where the naming scheme for decoders is "decoder.".h]hP...where the naming scheme for decoders is “decoder.”.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM8hjhhubeh}(h] the-cxl-busah ]h"] the cxl busah$]h&]uh1j[hj]hhhhhKubj\)}(hhh](ja)}(hDriver Infrastructureh]hDriver Infrastructure}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjChhhhhM;ubjq)}(hFThis section covers the driver infrastructure for a CXL memory device.h]hFThis section covers the driver infrastructure for a CXL memory device.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhM=hjChhubj\)}(hhh](ja)}(hCXL Memory Deviceh]hCXL Memory Device}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjbhhhhhM@ubjq)}(hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn't CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.h]hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn’t CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjbhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe driver has several responsibilities, mainly: - Create the memX device and register on the CXL bus. - Enumerate device's register interface and map them. - Registers nvdimm bridge device with cxl_core. - Registers a CXL mailbox with cxl_core. h](hterm)}(h0The driver has several responsibilities, mainly:h]h0The driver has several responsibilities, mainly:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK!hjubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h3Create the memX device and register on the CXL bus.h]jq)}(hjh]h3Create the memX device and register on the CXL bus.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h3Enumerate device's register interface and map them.h]jq)}(hjh]h5Enumerate device’s register interface and map them.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h-Registers nvdimm bridge device with cxl_core.h]jq)}(hjh]h-Registers nvdimm bridge device with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h(Registers a CXL mailbox with cxl_core. h]jq)}(h&Registers a CXL mailbox with cxl_core.h]h&Registers a CXL mailbox with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK!hjubah}(h]h ]h"]h$]h&]uh1jhjbhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single$__cxl_pci_mbox_send_cmd (C function)c.__cxl_pci_mbox_send_cmdhNtauh1j%hjbhhhNhNubhdesc)}(hhh](hdesc_signature)}(hYint __cxl_pci_mbox_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]hdesc_signature_line)}(hXint __cxl_pci_mbox_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_sig_keyword_type)}(hinth]hint}(hjIhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jGhjChhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKubhdesc_sig_space)}(h h]h }(hj[hhhNhNubah}(h]h ]wah"]h$]h&]uh1jYhjChhhjXhKubh desc_name)}(h__cxl_pci_mbox_send_cmdh]h desc_sig_name)}(h__cxl_pci_mbox_send_cmdh]h__cxl_pci_mbox_send_cmd}(hjrhhhNhNubah}(h]h ]nah"]h$]h&]uh1jphjlubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jjhjChhhjXhKubhdesc_parameterlist)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_parameter)}(hstruct cxl_mailbox *cxl_mboxh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjtsbc.__cxl_pci_mbox_send_cmdasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubjq)}(hcxl_mboxh]hcxl_mbox}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hj%hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj6hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj3ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8modnameN classnameNjj)}j]jc.__cxl_pci_mbox_send_cmdasbuh1hhjubjZ)}(h h]h }(hjThhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmbox_cmdh]hmbox_cmd}(hjohhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjChhhjXhKubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1jAsphinx_line_type declaratorhj=hhhjXhKubah}(h]j4ah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j;hjXhKhj8hhubh desc_content)}(hhh]jq)}(hExecute a mailbox commandh]hExecute a mailbox command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj8hhhjXhKubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j6hhhjbhNhNubh container)}(hX **Parameters** ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. **Context** Any context. Expects mbox_mutex to be held. **Return** -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded. **Description** This is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command. The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h](jq)}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj)}(hhh](j)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](j)}(h ``struct cxl_mailbox *cxl_mbox``h]hliteral)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubj)}(hhh]jq)}(hCXL mailbox contexth]hCXL mailbox context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjubj)}(hH``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. h](j)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hj) h]hstruct cxl_mbox_cmd *mbox_cmd}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj' ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj# ubj)}(hhh]jq)}(h%Command to send to the memory device.h]h%Command to send to the memory device.}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj> hKhj? ubah}(h]h ]h"]h$]h&]uh1jhj# ubeh}(h]h ]h"]h$]h&]uh1jhj> hKhjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Context**h]j)}(hjd h]hContext}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(h+Any context. Expects mbox_mutex to be held.h]h+Any context. Expects mbox_mutex to be held.}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(h-ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded.h](hl-ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in }(hj hhhNhNubj)}(h **mbox_cmd**h]hmbox_cmd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh to make sure it succeeded.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.h]hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubjq)}(hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h]hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubjq)}(hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.h]hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chK hjbhhubjq)}(hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.h]hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chKhjbhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_memdev (C struct) c.cxl_memdevhNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(h cxl_memdevh]jB)}(hstruct cxl_memdevh](j)}(hjh]hstruct}(hj6 hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2 hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKubjZ)}(h h]h }(hjD hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj2 hhhjC hKubjk)}(h cxl_memdevh]jq)}(hj0 h]h cxl_memdev}(hjV hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjR ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj2 hhhjC hKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj. hhhjC hKubah}(h]j) ah ](jjeh"]h$]h&]jj)jhuh1j;hjC hKhj+ hhubj)}(hhh]jq)}(h2CXL bus object representing a Type-3 Memory Deviceh]h2CXL bus object representing a Type-3 Memory Device}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK*hju hhubah}(h]h ]h"]h$]h&]uh1jhj+ hhhjC hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j6hhhjbhNhNubj)}(hX+**Definition**:: struct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; const struct cxl_memdev_attach *attach; int id; int depth; u8 scrub_cycle; int scrub_region_id; struct cxl_mem_err_rec *err_rec_array; }; **Members** ``dev`` driver core device object ``cdev`` char dev core object for ioctl operations ``cxlds`` The device state backing this device ``detach_work`` active memdev lost a port in its ancestry ``cxl_nvb`` coordinate removal of **cxl_nvd** if present ``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem ``endpoint`` connection to the CXL port topology for this memory device ``attach`` creator of this memdev depends on CXL link attach to operate ``id`` id number of this memdev instance. ``depth`` endpoint port depth ``scrub_cycle`` current scrub cycle set for this device ``scrub_region_id`` id number of a backed region (if any) for which current scrub cycle set ``err_rec_array`` List of xarrarys to store the memdev error records to check attributes for a memory repair operation are from current boot.h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK.hj ubj)}(hXstruct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; const struct cxl_memdev_attach *attach; int id; int depth; u8 scrub_cycle; int scrub_region_id; struct cxl_mem_err_rec *err_rec_array; };h]hXstruct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; const struct cxl_memdev_attach *attach; int id; int depth; u8 scrub_cycle; int scrub_region_id; struct cxl_mem_err_rec *err_rec_array; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK0hj ubjq)}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK@hj ubj)}(hhh](j)}(h"``dev`` driver core device object h](j)}(h``dev``h]j)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK,hj ubj)}(hhh]jq)}(hdriver core device objecth]hdriver core device object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hK,hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hK,hj ubj)}(h3``cdev`` char dev core object for ioctl operations h](j)}(h``cdev``h]j)}(hj h]hcdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK-hj ubj)}(hhh]jq)}(h)char dev core object for ioctl operationsh]h)char dev core object for ioctl operations}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj3 hK-hj4 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj3 hK-hj ubj)}(h/``cxlds`` The device state backing this device h](j)}(h ``cxlds``h]j)}(hjW h]hcxlds}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK.hjQ ubj)}(hhh]jq)}(h$The device state backing this deviceh]h$The device state backing this device}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjl hK.hjm ubah}(h]h ]h"]h$]h&]uh1jhjQ ubeh}(h]h ]h"]h$]h&]uh1jhjl hK.hj ubj)}(h:``detach_work`` active memdev lost a port in its ancestry h](j)}(h``detach_work``h]j)}(hj h]h detach_work}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK/hj ubj)}(hhh]jq)}(h)active memdev lost a port in its ancestryh]h)active memdev lost a port in its ancestry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hK/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hK/hj ubj)}(h9``cxl_nvb`` coordinate removal of **cxl_nvd** if present h](j)}(h ``cxl_nvb``h]j)}(hj h]hcxl_nvb}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK0hj ubj)}(hhh]jq)}(h,coordinate removal of **cxl_nvd** if presenth](hcoordinate removal of }(hj hhhNhNubj)}(h **cxl_nvd**h]hcxl_nvd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh if present}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj hK0hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj hK0hj ubj)}(hE``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem h](j)}(h ``cxl_nvd``h]j)}(hj h]hcxl_nvd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK1hj ubj)}(hhh]jq)}(h8optional bridge to an nvdimm if the device supports pmemh]h8optional bridge to an nvdimm if the device supports pmem}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj) hK1hj* ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj) hK1hj ubj)}(hH``endpoint`` connection to the CXL port topology for this memory device h](j)}(h ``endpoint``h]j)}(hjM h]hendpoint}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjK ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK2hjG ubj)}(hhh]jq)}(h:connection to the CXL port topology for this memory deviceh]h:connection to the CXL port topology for this memory device}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjb hK2hjc ubah}(h]h ]h"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]uh1jhjb hK2hj ubj)}(hH``attach`` creator of this memdev depends on CXL link attach to operate h](j)}(h ``attach``h]j)}(hj h]hattach}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK3hj ubj)}(hhh]jq)}(hubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMihjubj)}(h0``sanitize_active`` sanitize completion pending h](j)}(h``sanitize_active``h]j)}(hjah]hsanitize_active}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMjhj[ubj)}(hhh]jq)}(hsanitize completion pendingh]hsanitize completion pending}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjvhMjhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMjhjubj)}(h!``poll_dwork`` polling work item h](j)}(h``poll_dwork``h]j)}(hjh]h poll_dwork}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMkhjubj)}(hhh]jq)}(hpolling work itemh]hpolling work item}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMkhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMkhjubj)}(h1``sanitize_node`` sanitation sysfs file to notifyh](j)}(h``sanitize_node``h]j)}(hjh]h sanitize_node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMkhjubj)}(hhh]jq)}(hsanitation sysfs file to notifyh]hsanitation sysfs file to notify}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMkhjubeh}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_memdev_state (C struct)c.cxl_memdev_statehNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(hcxl_memdev_stateh]jB)}(hstruct cxl_memdev_stateh](j)}(hjh]hstruct}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMrubjZ)}(h h]h }(hj;hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj)hhhj:hMrubjk)}(hcxl_memdev_stateh]jq)}(hj'h]hcxl_memdev_state}(hjMhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjIubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj)hhhj:hMrubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj%hhhj:hMrubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j;hj:hMrhj"hhubj)}(hhh]jq)}(h.Generic Type-3 Memory Device Class driver datah]h.Generic Type-3 Memory Device Class driver data}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjlhhubah}(h]h ]h"]h$]h&]uh1jhj"hhhj:hMrubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjbhNhNubj)}(hX**Definition**:: struct cxl_memdev_state { struct cxl_dev_state cxlds; size_t lsa_size; char firmware_version[0x10]; u64 total_bytes; u64 volatile_only_bytes; u64 persistent_only_bytes; u64 partition_align_bytes; u64 active_volatile_bytes; u64 active_persistent_bytes; struct cxl_event_state event; struct cxl_poison_state poison; struct cxl_security_state security; struct cxl_fw_state fw; struct notifier_block mce_notifier; }; **Members** ``cxlds`` Core driver state common across Type-2 and Type-3 devices ``lsa_size`` Size of Label Storage Area (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) ``firmware_version`` Firmware version for the memory device. ``total_bytes`` sum of all possible capacities ``volatile_only_bytes`` hard volatile capacity ``persistent_only_bytes`` hard persistent capacity ``partition_align_bytes`` alignment size for partition-able capacity ``active_volatile_bytes`` sum of hard + soft volatile ``active_persistent_bytes`` sum of hard + soft persistent ``event`` event log driver state ``poison`` poison driver state info ``security`` security driver state info ``fw`` firmware upload / activation state ``mce_notifier`` MCE notifierh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hXstruct cxl_memdev_state { struct cxl_dev_state cxlds; size_t lsa_size; char firmware_version[0x10]; u64 total_bytes; u64 volatile_only_bytes; u64 persistent_only_bytes; u64 partition_align_bytes; u64 active_volatile_bytes; u64 active_persistent_bytes; struct cxl_event_state event; struct cxl_poison_state poison; struct cxl_security_state security; struct cxl_fw_state fw; struct notifier_block mce_notifier; };h]hXstruct cxl_memdev_state { struct cxl_dev_state cxlds; size_t lsa_size; char firmware_version[0x10]; u64 total_bytes; u64 volatile_only_bytes; u64 persistent_only_bytes; u64 partition_align_bytes; u64 active_volatile_bytes; u64 active_persistent_bytes; struct cxl_event_state event; struct cxl_poison_state poison; struct cxl_security_state security; struct cxl_fw_state fw; struct notifier_block mce_notifier; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubjq)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh](j)}(hD``cxlds`` Core driver state common across Type-2 and Type-3 devices h](j)}(h ``cxlds``h]j)}(hjh]hcxlds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(h9Core driver state common across Type-2 and Type-3 devicesh]h9Core driver state common across Type-2 and Type-3 devices}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hU``lsa_size`` Size of Label Storage Area (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) h](j)}(h ``lsa_size``h]j)}(hjh]hlsa_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hGSize of Label Storage Area (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)h]hGSize of Label Storage Area (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hMhjubj)}(h=``firmware_version`` Firmware version for the memory device. h](j)}(h``firmware_version``h]j)}(hjOh]hfirmware_version}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjIubj)}(hhh]jq)}(h'Firmware version for the memory device.h]h'Firmware version for the memory device.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjdhMhjeubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjdhMhjubj)}(h/``total_bytes`` sum of all possible capacities h](j)}(h``total_bytes``h]j)}(hjh]h total_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hsum of all possible capacitiesh]hsum of all possible capacities}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h/``volatile_only_bytes`` hard volatile capacity h](j)}(h``volatile_only_bytes``h]j)}(hjh]hvolatile_only_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hhard volatile capacityh]hhard volatile capacity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h3``persistent_only_bytes`` hard persistent capacity h](j)}(h``persistent_only_bytes``h]j)}(hjh]hpersistent_only_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hhard persistent capacityh]hhard persistent capacity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hE``partition_align_bytes`` alignment size for partition-able capacity h](j)}(h``partition_align_bytes``h]j)}(hj3h]hpartition_align_bytes}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj-ubj)}(hhh]jq)}(h*alignment size for partition-able capacityh]h*alignment size for partition-able capacity}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjHhMhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhjHhMhjubj)}(h6``active_volatile_bytes`` sum of hard + soft volatile h](j)}(h``active_volatile_bytes``h]j)}(hjlh]hactive_volatile_bytes}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjfubj)}(hhh]jq)}(hsum of hard + soft volatileh]hsum of hard + soft volatile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``active_persistent_bytes`` sum of hard + soft persistent h](j)}(h``active_persistent_bytes``h]j)}(hjh]hactive_persistent_bytes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hsum of hard + soft persistenth]hsum of hard + soft persistent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h!``event`` event log driver state h](j)}(h ``event``h]j)}(hjh]hevent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hevent log driver stateh]hevent log driver state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h$``poison`` poison driver state info h](j)}(h ``poison``h]j)}(hjh]hpoison}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(hpoison driver state infoh]hpoison driver state info}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj,hMhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj,hMhjubj)}(h(``security`` security driver state info h](j)}(h ``security``h]j)}(hjPh]hsecurity}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjJubj)}(hhh]jq)}(hsecurity driver state infoh]hsecurity driver state info}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jphjehMhjfubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjehMhjubj)}(h*``fw`` firmware upload / activation state h](j)}(h``fw``h]j)}(hjh]hfw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(h"firmware upload / activation stateh]h"firmware upload / activation state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h``mce_notifier`` MCE notifierh](j)}(h``mce_notifier``h]j)}(hjh]h mce_notifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(h MCE notifierh]h MCE notifier}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubjq)}(hCXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines common memory device functionality like the presence of a mailbox and the functionality related to that like Identify Memory Device and Get Partition Infoh]hCXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines common memory device functionality like the presence of a mailbox and the functionality related to that like Identify Memory Device and Get Partition Info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubjq)}(hbSee CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for details on capacity parameters.h]hbSee CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for details on capacity parameters.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_mem_command (C struct)c.cxl_mem_commandhNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(hcxl_mem_commandh]jB)}(hstruct cxl_mem_commandh](j)}(hjh]hstruct}(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjZ)}(h h]h }(hj`hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjNhhhj_hMubjk)}(hcxl_mem_commandh]jq)}(hjLh]hcxl_mem_command}(hjrhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjnubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjNhhhj_hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjJhhhj_hMubah}(h]jEah ](jjeh"]h$]h&]jj)jhuh1j;hj_hMhjGhhubj)}(hhh]jq)}(h0Driver representation of a memory device commandh]h0Driver representation of a memory device command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjGhhhj_hMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjbhNhNubj)}(hXh**Definition**:: struct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); }; **Members** ``info`` Command information as it exists for the UAPI ``opcode`` The actual bits used for the mailbox protocol ``flags`` Set of flags effecting driver behavior.h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hstruct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); };h]hstruct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubjq)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh](j)}(h7``info`` Command information as it exists for the UAPI h](j)}(h``info``h]j)}(hjh]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]jq)}(h-Command information as it exists for the UAPIh]h-Command information as it exists for the UAPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h9``opcode`` The actual bits used for the mailbox protocol h](j)}(h ``opcode``h]j)}(hj:h]hopcode}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj4ubj)}(hhh]jq)}(h-The actual bits used for the mailbox protocolh]h-The actual bits used for the mailbox protocol}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jphjOhMhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhMhjubj)}(h1``flags`` Set of flags effecting driver behavior.h](j)}(h ``flags``h]j)}(hjsh]hflags}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjmubj)}(hhh]jq)}(h'Set of flags effecting driver behavior.h]h'Set of flags effecting driver behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubh block_quote)}(h* ``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised. h]j)}(hhh]j)}(h``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised. h]jq)}(h``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.h](j)}(h``CXL_CMD_FLAG_FORCE_ENABLE``h]hCXL_CMD_FLAG_FORCE_ENABLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh{: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhMhjbhhubjq)}(hXThe cxl_mem_command is the driver's internal representation of commands that are supported by the driver. Some of these commands may not be supported by the hardware. The driver will use **info** to validate the fields passed in by the user then submit the **opcode** to the hardware.h](hThe cxl_mem_command is the driver’s internal representation of commands that are supported by the driver. Some of these commands may not be supported by the hardware. The driver will use }(hjhhhNhNubj)}(h**info**h]hinfo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh> to validate the fields passed in by the user then submit the }(hjhhhNhNubj)}(h **opcode**h]hopcode}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh to the hardware.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubjq)}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjbhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_hdm (C struct) c.cxl_hdmhNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(hcxl_hdmh]jB)}(hstruct cxl_hdmh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjZ)}(h h]h }(hjqhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj_hhhjphMubjk)}(hcxl_hdmh]jq)}(hj]h]hcxl_hdm}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj_hhhjphMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj[hhhjphMubah}(h]jVah ](jjeh"]h$]h&]jj)jhuh1j;hjphMhjXhhubj)}(hhh]jq)}(h7HDM Decoder registers and cached / decoded capabilitiesh]h7HDM Decoder registers and cached / decoded capabilities}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMBhjhhubah}(h]h ]h"]h$]h&]uh1jhjXhhhjphMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjbhNhNubj)}(hX**Definition**:: struct cxl_hdm { struct cxl_component_regs regs; int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; }; **Members** ``regs`` mapped registers, see devm_cxl_setup_hdm() ``decoder_count`` number of decoders for this port ``target_count`` for switch decoders, max downstream port targets ``interleave_mask`` interleave granularity capability, see check_interleave_cap() ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() ``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMFhjubj)}(hstruct cxl_hdm { struct cxl_component_regs regs; int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };h]hstruct cxl_hdm { struct cxl_component_regs regs; int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMHhjubjq)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMQhjubj)}(hhh](j)}(h4``regs`` mapped registers, see devm_cxl_setup_hdm() h](j)}(h``regs``h]j)}(hjh]hregs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMDhj ubj)}(hhh]jq)}(h*mapped registers, see devm_cxl_setup_hdm()h]h*mapped registers, see devm_cxl_setup_hdm()}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj'hMDhj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj'hMDhj ubj)}(h3``decoder_count`` number of decoders for this port h](j)}(h``decoder_count``h]j)}(hjKh]h decoder_count}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMEhjEubj)}(hhh]jq)}(h number of decoders for this porth]h number of decoders for this port}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj`hMEhjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhj`hMEhj ubj)}(hB``target_count`` for switch decoders, max downstream port targets h](j)}(h``target_count``h]j)}(hjh]h target_count}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMFhj~ubj)}(hhh]jq)}(h0for switch decoders, max downstream port targetsh]h0for switch decoders, max downstream port targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMFhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhjhMFhj ubj)}(hR``interleave_mask`` interleave granularity capability, see check_interleave_cap() h](j)}(h``interleave_mask``h]j)}(hjh]hinterleave_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMGhjubj)}(hhh]jq)}(h=interleave granularity capability, see check_interleave_cap()h]h=interleave granularity capability, see check_interleave_cap()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMGhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMGhj ubj)}(hQ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() h](j)}(h``iw_cap_mask``h]j)}(hjh]h iw_cap_mask}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMHhjubj)}(hhh]jq)}(h@bitmask of supported interleave ways, see check_interleave_cap()h]h@bitmask of supported interleave ways, see check_interleave_cap()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hMHhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMHhj ubj)}(h2``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](j)}(h``port``h]j)}(hj/h]hport}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMHhj)ubj)}(hhh]jq)}(h)mapped cxl_port, see devm_cxl_setup_hdm()h]h)mapped cxl_port, see devm_cxl_setup_hdm()}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jphh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMIhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhjDhMHhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2'set_exclusive_cxl_commands (C function)c.set_exclusive_cxl_commandshNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(hSvoid set_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]jB)}(hRvoid set_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](jH)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMMubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMMubjk)}(hset_exclusive_cxl_commandsh]jq)}(hset_exclusive_cxl_commandsh]hset_exclusive_cxl_commands}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMMubj)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.set_exclusive_cxl_commandsasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmdsh]hmds}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned long *cmdsh](jH)}(hunsignedh]hunsigned}(hj8hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj4ubjZ)}(h h]h }(hjFhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj4ubjH)}(hlongh]hlong}(hjThhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj4ubjZ)}(h h]h }(hjbhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj4ubj)}(hjh]h*}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubjq)}(hcmdsh]hcmds}(hj}hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj4ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMMubah}(h]j|ah ](jjeh"]h$]h&]jj)jhuh1j;hjhMMhj~hhubj)}(hhh]jq)}(h$atomically disable user cxl commandsh]h$atomically disable user cxl commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMMhjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhjhMMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjbhNhNubj)}(hXP**Parameters** ``struct cxl_memdev_state *mds`` The device state to operate on ``unsigned long *cmds`` bitmap of commands to mark exclusive **Description** Grab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMQhjubj)}(hhh](j)}(h@``struct cxl_memdev_state *mds`` The device state to operate on h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hjh]hstruct cxl_memdev_state *mds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMNhjubj)}(hhh]jq)}(hThe device state to operate onh]hThe device state to operate on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMNhjubj)}(h=``unsigned long *cmds`` bitmap of commands to mark exclusive h](j)}(h``unsigned long *cmds``h]j)}(hj!h]hunsigned long *cmds}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMOhjubj)}(hhh]jq)}(h$bitmap of commands to mark exclusiveh]h$bitmap of commands to mark exclusive}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj6hMOhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj6hMOhjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hj\h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMQhjubjq)}(hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in }(hjrhhhNhNubj)}(h**cmds**h]hcmds}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubh.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMPhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2)clear_exclusive_cxl_commands (C function)c.clear_exclusive_cxl_commandshNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(hUvoid clear_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]jB)}(hTvoid clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](jH)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMaubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMaubjk)}(hclear_exclusive_cxl_commandsh]jq)}(hclear_exclusive_cxl_commandsh]hclear_exclusive_cxl_commands}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMaubj)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hj hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]j)}jjsbc.clear_exclusive_cxl_commandsasbuh1hhjubjZ)}(h h]h }(hj. hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hj< hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmdsh]hmds}(hjI hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned long *cmdsh](jH)}(hunsignedh]hunsigned}(hjb hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj^ ubjZ)}(h h]h }(hjp hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj^ ubjH)}(hlongh]hlong}(hj~ hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj^ ubjZ)}(h h]h }(hj hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj^ ubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ ubjq)}(hcmdsh]hcmds}(hj hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj^ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMaubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMaubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMahjhhubj)}(hhh]jq)}(h#atomically enable user cxl commandsh]h#atomically enable user cxl commands}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMahj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMaubeh}(h]h ](jfunctioneh"]h$]h&]jjjj jj jjjuh1j6hhhjbhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device state to modify ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](jq)}(h**Parameters**h]j)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMehj ubj)}(hhh](j)}(h<``struct cxl_memdev_state *mds`` The device state to modify h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hj!h]hstruct cxl_memdev_state *mds}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMbhj !ubj)}(hhh]jq)}(hThe device state to modifyh]hThe device state to modify}(hj+!hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj'!hMbhj(!ubah}(h]h ]h"]h$]h&]uh1jhj !ubeh}(h]h ]h"]h$]h&]uh1jhj'!hMbhj !ubj)}(hJ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](j)}(h``unsigned long *cmds``h]j)}(hjK!h]hunsigned long *cmds}(hjM!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI!ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMdhjE!ubj)}(hhh]jq)}(h2bitmap of commands to mark available for userspaceh]h2bitmap of commands to mark available for userspace}(hjd!hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMchja!ubah}(h]h ]h"]h$]h&]uh1jhjE!ubeh}(h]h ]h"]h$]h&]uh1jhj`!hMdhj !ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 cxl_mem_get_fw_info (C function)c.cxl_mem_get_fw_infohNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(h6int cxl_mem_get_fw_info (struct cxl_memdev_state *mds)h]jB)}(h5int cxl_mem_get_fw_info(struct cxl_memdev_state *mds)h](jH)}(hinth]hint}(hj!hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj!hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM ubjZ)}(h h]h }(hj!hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj!hhhj!hM ubjk)}(hcxl_mem_get_fw_infoh]jq)}(hcxl_mem_get_fw_infoh]hcxl_mem_get_fw_info}(hj!hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj!ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj!hhhj!hM ubj)}(h(struct cxl_memdev_state *mds)h]j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubjZ)}(h h]h }(hj!hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj!ubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hj"hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj!ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj"modnameN classnameNjj)}j]j)}jj!sbc.cxl_mem_get_fw_infoasbuh1hhj!ubjZ)}(h h]h }(hj "hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj!ubj)}(hjh]h*}(hj."hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubjq)}(hmdsh]hmds}(hj;"hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubah}(h]h ]h"]h$]h&]hhuh1jhj!hhhj!hM ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj!hhhj!hM ubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1j;hj!hM hj!hhubj)}(hhh]jq)}(hGet Firmware infoh]hGet Firmware info}(hje"hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hjb"hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj}"jj}"jjjuh1j6hhhjbhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Retrieve firmware info for the device specified. See CXL-3.0 8.2.9.3.1 Get FW Info **Return** 0 if no error: or the result of the mailbox command.h](jq)}(h**Parameters**h]j)}(hj"h]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj"ubj)}(hhh]j)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hj"h]hstruct cxl_memdev_state *mds}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hj"ubj)}(hhh]jq)}(h!The device data for the operationh]h!The device data for the operation}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubjq)}(h**Description**h]j)}(hj"h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hj"ubjq)}(h0Retrieve firmware info for the device specified.h]h0Retrieve firmware info for the device specified.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hj"ubjq)}(h!See CXL-3.0 8.2.9.3.1 Get FW Infoh]h!See CXL-3.0 8.2.9.3.1 Get FW Info}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj"ubjq)}(h **Return**h]j)}(hj#h]hReturn}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj"ubjq)}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj-#hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 cxl_mem_activate_fw (C function)c.cxl_mem_activate_fwhNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(h@int cxl_mem_activate_fw (struct cxl_memdev_state *mds, int slot)h]jB)}(h?int cxl_mem_activate_fw(struct cxl_memdev_state *mds, int slot)h](jH)}(hinth]hint}(hj\#hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjX#hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM,ubjZ)}(h h]h }(hjk#hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjX#hhhjj#hM,ubjk)}(hcxl_mem_activate_fwh]jq)}(hcxl_mem_activate_fwh]hcxl_mem_activate_fw}(hj}#hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjy#ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjX#hhhjj#hM,ubj)}(h((struct cxl_memdev_state *mds, int slot)h](j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubjZ)}(h h]h }(hj#hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj#ubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hj#hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj#ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#modnameN classnameNjj)}j]j)}jj#sbc.cxl_mem_activate_fwasbuh1hhj#ubjZ)}(h h]h }(hj#hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj#ubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubjq)}(hmdsh]hmds}(hj#hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hint sloth](jH)}(hinth]hint}(hj $hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj$ubjZ)}(h h]h }(hj$hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj$ubjq)}(hsloth]hslot}(hj'$hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubeh}(h]h ]h"]h$]h&]hhuh1jhjX#hhhjj#hM,ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjT#hhhjj#hM,ubah}(h]jO#ah ](jjeh"]h$]h&]jj)jhuh1j;hjj#hM,hjQ#hhubj)}(hhh]jq)}(hActivate Firmwareh]hActivate Firmware}(hjQ$hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM,hjN$hhubah}(h]h ]h"]h$]h&]uh1jhjQ#hhhjj#hM,ubeh}(h]h ](jfunctioneh"]h$]h&]jjjji$jji$jjjuh1j6hhhjbhNhNubj)}(hX0**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation ``int slot`` slot number to activate **Description** Activate firmware in a given slot for the device specified. See CXL-3.0 8.2.9.3.3 Activate FW **Return** 0 if no error: or the result of the mailbox command.h](jq)}(h**Parameters**h]j)}(hjs$h]h Parameters}(hju$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq$ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM0hjm$ubj)}(hhh](j)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hj$h]hstruct cxl_memdev_state *mds}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM-hj$ubj)}(hhh]jq)}(h!The device data for the operationh]h!The device data for the operation}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj$hM-hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM-hj$ubj)}(h%``int slot`` slot number to activate h](j)}(h ``int slot``h]j)}(hj$h]hint slot}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM.hj$ubj)}(hhh]jq)}(hslot number to activateh]hslot number to activate}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj$hM.hj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hM.hj$ubeh}(h]h ]h"]h$]h&]uh1jhjm$ubjq)}(h**Description**h]j)}(hj%h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM0hjm$ubjq)}(h;Activate firmware in a given slot for the device specified.h]h;Activate firmware in a given slot for the device specified.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM/hjm$ubjq)}(h!See CXL-3.0 8.2.9.3.3 Activate FWh]h!See CXL-3.0 8.2.9.3.3 Activate FW}(hj+%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM2hjm$ubjq)}(h **Return**h]j)}(hj<%h]hReturn}(hj>%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:%ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM4hjm$ubjq)}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hjR%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM2hjm$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2"cxl_mem_abort_fw_xfer (C function)c.cxl_mem_abort_fw_xferhNtauh1j%hjbhhhNhNubj7)}(hhh](j<)}(h8int cxl_mem_abort_fw_xfer (struct cxl_memdev_state *mds)h]jB)}(h7int cxl_mem_abort_fw_xfer(struct cxl_memdev_state *mds)h](jH)}(hinth]hint}(hj%hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj}%hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMMubjZ)}(h h]h }(hj%hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj}%hhhj%hMMubjk)}(hcxl_mem_abort_fw_xferh]jq)}(hcxl_mem_abort_fw_xferh]hcxl_mem_abort_fw_xfer}(hj%hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj%ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj}%hhhj%hMMubj)}(h(struct cxl_memdev_state *mds)h]j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubjZ)}(h h]h }(hj%hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj%ubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hj%hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj%ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj%modnameN classnameNjj)}j]j)}jj%sbc.cxl_mem_abort_fw_xferasbuh1hhj%ubjZ)}(h h]h }(hj%hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj%ubj)}(hjh]h*}(hj &hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubjq)}(hmdsh]hmds}(hj&hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubah}(h]h ]h"]h$]h&]hhuh1jhj}%hhhj%hMMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjy%hhhj%hMMubah}(h]jt%ah ](jjeh"]h$]h&]jj)jhuh1j;hj%hMMhjv%hhubj)}(hhh]jq)}(h Abort an in-progress FW transferh]h Abort an in-progress FW transfer}(hjA&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMMhj>&hhubah}(h]h ]h"]h$]h&]uh1jhjv%hhhj%hMMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjY&jjY&jjjuh1j6hhhjbhNhNubj)}(hX **Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Abort an in-progress firmware transfer for the device specified. See CXL-3.0 8.2.9.3.2 Transfer FW **Return** 0 if no error: or the result of the mailbox command.h](jq)}(h**Parameters**h]j)}(hjc&h]h Parameters}(hje&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja&ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMQhj]&ubj)}(hhh]j)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hj&h]hstruct cxl_memdev_state *mds}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMNhj|&ubj)}(hhh]jq)}(h!The device data for the operationh]h!The device data for the operation}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj&hMNhj&ubah}(h]h ]h"]h$]h&]uh1jhj|&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMNhjy&ubah}(h]h ]h"]h$]h&]uh1jhj]&ubjq)}(h**Description**h]j)}(hj&h]h Description}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMPhj]&ubjq)}(h@Abort an in-progress firmware transfer for the device specified.h]h@Abort an in-progress firmware transfer for the device specified.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMOhj]&ubjq)}(h!See CXL-3.0 8.2.9.3.2 Transfer FWh]h!See CXL-3.0 8.2.9.3.2 Transfer FW}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMRhj]&ubjq)}(h **Return**h]j)}(hj&h]hReturn}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMThj]&ubjq)}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMRhj]&ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjbhhhNhNubeh}(h]cxl-memory-deviceah ]h"]cxl memory deviceah$]h&]uh1j[hjChhhhhM@ubj\)}(hhh](ja)}(hCXL Porth]hCXL Port}(hj*'hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj''hhhhhMRubjq)}(hXThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the **component_reg_phys** value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.h](hrThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the }(hj8'hhhNhNubj)}(h**component_reg_phys**h]hcomponent_reg_phys}(hj@'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8'ubhXK value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.}(hj8'hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chK hj''hhubjq)}(hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.h]hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.}(hjY'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chKhj''hhubeh}(h]cxl-portah ]h"]cxl portah$]h&]uh1j[hjChhhhhMRubj\)}(hhh](ja)}(hCXL Coreh]hCXL Core}(hjs'hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjp'hhhhhMWubjq)}(hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).h]hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:430: ./drivers/cxl/cxl.hhKhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_decoder (C struct) c.cxl_decoderhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h cxl_decoderh]jB)}(hstruct cxl_decoderh](j)}(hjh]hstruct}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhKubjZ)}(h h]h }(hj'hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj'hhhj'hKubjk)}(h cxl_decoderh]jq)}(hj'h]h cxl_decoder}(hj'hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj'ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj'hhhj'hKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj'hhhj'hKubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1j;hj'hKhj'hhubj)}(hhh]jq)}(h!Common CXL HDM Decoder Attributesh]h!Common CXL HDM Decoder Attributes}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM hj'hhubah}(h]h ]h"]h$]h&]uh1jhj'hhhj'hKubeh}(h]h ](jstructeh"]h$]h&]jjjj(jj(jjjuh1j6hhhjp'hNhNubj)}(hX**Definition**:: struct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); }; **Members** ``dev`` this decoder's device ``id`` kernel device name id ``hpa_range`` Host physical address range mapped by this decoder ``interleave_ways`` number of cxl_dports in this decode ``interleave_granularity`` data stride per dport ``target_type`` accelerator vs expander (type2 vs type3) selector ``region`` currently assigned region for this decoder ``flags`` memory type capabilities and locking ``target_map`` cached copy of hardware port-id list, available at init before all **dport** objects have been instantiated. While dport id is 8bit, CFMWS interleave targets are 32bits. ``commit`` device/decoder-type specific callback to commit settings to hw ``reset`` device/decoder-type specific callback to reset hw settingsh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj (ubh:}(hj (hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(ubj)}(hXxstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };h]hXxstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };}hj((sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(ubjq)}(h **Members**h]j)}(hj9(h]hMembers}(hj;(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7(ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM!hj(ubj)}(hhh](j)}(h``dev`` this decoder's device h](j)}(h``dev``h]j)}(hjX(h]hdev}(hjZ(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjV(ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjR(ubj)}(hhh]jq)}(hthis decoder's deviceh]hthis decoder’s device}(hjq(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjm(hMhjn(ubah}(h]h ]h"]h$]h&]uh1jhjR(ubeh}(h]h ]h"]h$]h&]uh1jhjm(hMhjO(ubj)}(h``id`` kernel device name id h](j)}(h``id``h]j)}(hj(h]hid}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(ubj)}(hhh]jq)}(hkernel device name idh]hkernel device name id}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj(hMhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjO(ubj)}(hA``hpa_range`` Host physical address range mapped by this decoder h](j)}(h ``hpa_range``h]j)}(hj(h]h hpa_range}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(ubj)}(hhh]jq)}(h2Host physical address range mapped by this decoderh]h2Host physical address range mapped by this decoder}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj(hMhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjO(ubj)}(h8``interleave_ways`` number of cxl_dports in this decode h](j)}(h``interleave_ways``h]j)}(hj)h]hinterleave_ways}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj(ubj)}(hhh]jq)}(h#number of cxl_dports in this decodeh]h#number of cxl_dports in this decode}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj)hMhjO(ubj)}(h1``interleave_granularity`` data stride per dport h](j)}(h``interleave_granularity``h]j)}(hj<)h]hinterleave_granularity}(hj>)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:)ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6)ubj)}(hhh]jq)}(hdata stride per dporth]hdata stride per dport}(hjU)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjQ)hMhjR)ubah}(h]h ]h"]h$]h&]uh1jhj6)ubeh}(h]h ]h"]h$]h&]uh1jhjQ)hMhjO(ubj)}(hB``target_type`` accelerator vs expander (type2 vs type3) selector h](j)}(h``target_type``h]j)}(hju)h]h target_type}(hjw)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs)ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjo)ubj)}(hhh]jq)}(h1accelerator vs expander (type2 vs type3) selectorh]h1accelerator vs expander (type2 vs type3) selector}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jhjo)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMhjO(ubj)}(h6``region`` currently assigned region for this decoder h](j)}(h ``region``h]j)}(hj)h]hregion}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj)ubj)}(hhh]jq)}(h*currently assigned region for this decoderh]h*currently assigned region for this decoder}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMhjO(ubj)}(h/``flags`` memory type capabilities and locking h](j)}(h ``flags``h]j)}(hj)h]hflags}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj)ubj)}(hhh]jq)}(h$memory type capabilities and lockingh]h$memory type capabilities and locking}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj)hMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)hMhjO(ubj)}(h``target_map`` cached copy of hardware port-id list, available at init before all **dport** objects have been instantiated. While dport id is 8bit, CFMWS interleave targets are 32bits. h](j)}(h``target_map``h]j)}(hj *h]h target_map}(hj"*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj*ubj)}(hhh]jq)}(hcached copy of hardware port-id list, available at init before all **dport** objects have been instantiated. While dport id is 8bit, CFMWS interleave targets are 32bits.h](hCcached copy of hardware port-id list, available at init before all }(hj9*hhhNhNubj)}(h **dport**h]hdport}(hjA*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9*ubh] objects have been instantiated. While dport id is 8bit, CFMWS interleave targets are 32bits.}(hj9*hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj5*hMhjO(ubj)}(hJ``commit`` device/decoder-type specific callback to commit settings to hw h](j)}(h ``commit``h]j)}(hjl*h]hcommit}(hjn*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj*ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjf*ubj)}(hhh]jq)}(h>device/decoder-type specific callback to commit settings to hwh]h>device/decoder-type specific callback to commit settings to hw}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jhjf*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhjO(ubj)}(hD``reset`` device/decoder-type specific callback to reset hw settingsh](j)}(h ``reset``h]j)}(hj*h]hreset}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj*ubj)}(hhh]jq)}(h:device/decoder-type specific callback to reset hw settingsh]h:device/decoder-type specific callback to reset hw settings}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhjO(ubeh}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_endpoint_decoder (C struct)c.cxl_endpoint_decoderhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_endpoint_decoderh]jB)}(hstruct cxl_endpoint_decoderh](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM!ubjZ)}(h h]h }(hj +hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj*hhhj +hM!ubjk)}(hcxl_endpoint_decoderh]jq)}(hj*h]hcxl_endpoint_decoder}(hj+hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj+ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj*hhhj +hM!ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj*hhhj +hM!ubah}(h]j*ah ](jjeh"]h$]h&]jj)jhuh1j;hj +hM!hj*hhubj)}(hhh]jq)}(hEndpoint / SPA to DPA decoderh]hEndpoint / SPA to DPA decoder}(hjA+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM6hj>+hhubah}(h]h ]h"]h$]h&]uh1jhj*hhhj +hM!ubeh}(h]h ](jstructeh"]h$]h&]jjjjY+jjY+jjjuh1j6hhhjp'hNhNubj)}(hX**Definition**:: struct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; }; **Members** ``cxld`` base cxl_decoder_object ``dpa_res`` actively claimed DPA span of this decoder ``skip`` offset into **dpa_res** where **cxld.hpa_range** maps ``state`` autodiscovery state ``part`` partition index this decoder maps ``pos`` interleave position in **cxld.region**h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hje+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja+ubh:}(hja+hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM:hj]+ubj)}(hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };h]hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };}hj~+sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM<hj]+ubjq)}(h **Members**h]j)}(hj+h]hMembers}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMEhj]+ubj)}(hhh](j)}(h!``cxld`` base cxl_decoder_object h](j)}(h``cxld``h]j)}(hj+h]hcxld}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM8hj+ubj)}(hhh]jq)}(hbase cxl_decoder_objecth]hbase cxl_decoder_object}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj+hM8hj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hM8hj+ubj)}(h6``dpa_res`` actively claimed DPA span of this decoder h](j)}(h ``dpa_res``h]j)}(hj+h]hdpa_res}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM9hj+ubj)}(hhh]jq)}(h)actively claimed DPA span of this decoderh]h)actively claimed DPA span of this decoder}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj+hM9hj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhj+hM9hj+ubj)}(h?``skip`` offset into **dpa_res** where **cxld.hpa_range** maps h](j)}(h``skip``h]j)}(hj ,h]hskip}(hj",hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM:hj,ubj)}(hhh]jq)}(h5offset into **dpa_res** where **cxld.hpa_range** mapsh](h offset into }(hj9,hhhNhNubj)}(h **dpa_res**h]hdpa_res}(hjA,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9,ubh where }(hj9,hhhNhNubj)}(h**cxld.hpa_range**h]hcxld.hpa_range}(hjS,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9,ubh maps}(hj9,hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj5,hM:hj6,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj5,hM:hj+ubj)}(h``state`` autodiscovery state h](j)}(h ``state``h]j)}(hj},h]hstate}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{,ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM;hjw,ubj)}(hhh]jq)}(hautodiscovery stateh]hautodiscovery state}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj,hM;hj,ubah}(h]h ]h"]h$]h&]uh1jhjw,ubeh}(h]h ]h"]h$]h&]uh1jhj,hM;hj+ubj)}(h+``part`` partition index this decoder maps h](j)}(h``part``h]j)}(hj,h]hpart}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM<hj,ubj)}(hhh]jq)}(h!partition index this decoder mapsh]h!partition index this decoder maps}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj,hM<hj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hM<hj+ubj)}(h.``pos`` interleave position in **cxld.region**h](j)}(h``pos``h]j)}(hj,h]hpos}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM<hj,ubj)}(hhh]jq)}(h&interleave position in **cxld.region**h](hinterleave position in }(hj-hhhNhNubj)}(h**cxld.region**h]h cxld.region}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM=hj-ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj-hM<hj+ubeh}(h]h ]h"]h$]h&]uh1jhj]+ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_switch_decoder (C struct)c.cxl_switch_decoderhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_switch_decoderh]jB)}(hstruct cxl_switch_decoderh](j)}(hjh]hstruct}(hjW-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjS-hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMCubjZ)}(h h]h }(hje-hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjS-hhhjd-hMCubjk)}(hcxl_switch_decoderh]jq)}(hjQ-h]hcxl_switch_decoder}(hjw-hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjs-ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjS-hhhjd-hMCubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjO-hhhjd-hMCubah}(h]jJ-ah ](jjeh"]h$]h&]jj)jhuh1j;hjd-hMChjL-hhubj)}(hhh]jq)}(hSwitch specific CXL HDM Decoderh]hSwitch specific CXL HDM Decoder}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMHhj-hhubah}(h]h ]h"]h$]h&]uh1jhjL-hhhjd-hMCubeh}(h]h ](jstructeh"]h$]h&]jjjj-jj-jjjuh1j6hhhjp'hNhNubj)}(hX9**Definition**:: struct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; }; **Members** ``cxld`` base cxl_decoder object ``nr_targets`` number of elements in **target** ``target`` active ordered target list in current decoder configurationh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubh:}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhj-ubj)}(hostruct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };h]hostruct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };}hj-sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMNhj-ubjq)}(h **Members**h]j)}(hj-h]hMembers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMThj-ubj)}(hhh](j)}(h!``cxld`` base cxl_decoder object h](j)}(h``cxld``h]j)}(hj.h]hcxld}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMJhj.ubj)}(hhh]jq)}(hbase cxl_decoder objecth]hbase cxl_decoder object}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj.hMJhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMJhj-ubj)}(h0``nr_targets`` number of elements in **target** h](j)}(h``nr_targets``h]j)}(hj?.h]h nr_targets}(hjA.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=.ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMKhj9.ubj)}(hhh]jq)}(h number of elements in **target**h](hnumber of elements in }(hjX.hhhNhNubj)}(h **target**h]htarget}(hj`.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX.ubeh}(h]h ]h"]h$]h&]uh1jphjT.hMKhjU.ubah}(h]h ]h"]h$]h&]uh1jhj9.ubeh}(h]h ]h"]h$]h&]uh1jhjT.hMKhj-ubj)}(hF``target`` active ordered target list in current decoder configurationh](j)}(h ``target``h]j)}(hj.h]htarget}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMKhj.ubj)}(hhh]jq)}(h;active ordered target list in current decoder configurationh]h;active ordered target list in current decoder configuration}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhj.hMKhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(h**Description**h]j)}(hj.h]h Description}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMOhjp'hhubjq)}(hXTThe 'switch' decoder type represents the decoder instances of cxl_port's that route from the root of a CXL memory decode topology to the endpoints. They come in two flavors, root-level decoders, statically defined by platform firmware, and mid-level decoders, where interleave-granularity, interleave-width, and the target list are mutable.h]hXZThe ‘switch’ decoder type represents the decoder instances of cxl_port’s that route from the root of a CXL memory decode topology to the endpoints. They come in two flavors, root-level decoders, statically defined by platform firmware, and mid-level decoders, where interleave-granularity, interleave-width, and the target list are mutable.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_rd_ops (C struct) c.cxl_rd_opshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h cxl_rd_opsh]jB)}(hstruct cxl_rd_opsh](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMUubjZ)}(h h]h }(hj/hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj/hhhj/hMUubjk)}(h cxl_rd_opsh]jq)}(hj/h]h cxl_rd_ops}(hj'/hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj#/ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj/hhhj/hMUubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj.hhhj/hMUubah}(h]j.ah ](jjeh"]h$]h&]jj)jhuh1j;hj/hMUhj.hhubj)}(hhh]jq)}(h$CXL root decoder callback operationsh]h$CXL root decoder callback operations}(hjI/hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM[hjF/hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj/hMUubeh}(h]h ](jstructeh"]h$]h&]jjjja/jja/jjjuh1j6hhhjp'hNhNubj)}(hXS**Definition**:: struct cxl_rd_ops { u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); }; **Members** ``hpa_to_spa`` Convert host physical address to system physical address ``spa_to_hpa`` Convert system physical address to host physical addressh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjm/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji/ubh:}(hji/hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM_hje/ubj)}(hstruct cxl_rd_ops { u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); };h]hstruct cxl_rd_ops { u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); };}hj/sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMahje/ubjq)}(h **Members**h]j)}(hj/h]hMembers}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMfhje/ubj)}(hhh](j)}(hH``hpa_to_spa`` Convert host physical address to system physical address h](j)}(h``hpa_to_spa``h]j)}(hj/h]h hpa_to_spa}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM]hj/ubj)}(hhh]jq)}(h8Convert host physical address to system physical addressh]h8Convert host physical address to system physical address}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/hM]hj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM]hj/ubj)}(hG``spa_to_hpa`` Convert system physical address to host physical addressh](j)}(h``spa_to_hpa``h]j)}(hj/h]h spa_to_hpa}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM]hj/ubj)}(hhh]jq)}(h8Convert system physical address to host physical addressh]h8Convert system physical address to host physical address}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM^hj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj0hM]hj/ubeh}(h]h ]h"]h$]h&]uh1jhje/ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_root_decoder (C struct)c.cxl_root_decoderhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_root_decoderh]jB)}(hstruct cxl_root_decoderh](j)}(hjh]hstruct}(hjI0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjE0hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMdubjZ)}(h h]h }(hjW0hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjE0hhhjV0hMdubjk)}(hcxl_root_decoderh]jq)}(hjC0h]hcxl_root_decoder}(hji0hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphje0ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjE0hhhjV0hMdubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjA0hhhjV0hMdubah}(h]j<0ah ](jjeh"]h$]h&]jj)jhuh1j;hjV0hMdhj>0hhubj)}(hhh]jq)}(h#Static platform CXL address decoderh]h#Static platform CXL address decoder}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMehj0hhubah}(h]h ]h"]h$]h&]uh1jhj>0hhhjV0hMdubeh}(h]h ](jstructeh"]h$]h&]jjjj0jj0jjjuh1j6hhhjp'hNhNubj)}(hX**Definition**:: struct cxl_root_decoder { struct resource *res; resource_size_t cache_size; atomic_t region_id; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_rd_ops ops; struct cxl_switch_decoder cxlsd; }; **Members** ``res`` host / parent resource for region allocations ``cache_size`` extended linear cache size if exists, otherwise zero. ``region_id`` region id for next region provisioning event ``platform_data`` platform specific configuration data ``range_lock`` sync region autodiscovery by address range ``qos_class`` QoS performance class cookie ``ops`` CXL root decoder operations ``cxlsd`` base cxl switch decoderh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh:}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMihj0ubj)}(hstruct cxl_root_decoder { struct resource *res; resource_size_t cache_size; atomic_t region_id; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_rd_ops ops; struct cxl_switch_decoder cxlsd; };h]hstruct cxl_root_decoder { struct resource *res; resource_size_t cache_size; atomic_t region_id; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_rd_ops ops; struct cxl_switch_decoder cxlsd; };}hj0sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMkhj0ubjq)}(h **Members**h]j)}(hj0h]hMembers}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMvhj0ubj)}(hhh](j)}(h6``res`` host / parent resource for region allocations h](j)}(h``res``h]j)}(hj0h]hres}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMghj0ubj)}(hhh]jq)}(h-host / parent resource for region allocationsh]h-host / parent resource for region allocations}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj 1hMghj1ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhj 1hMghj0ubj)}(hE``cache_size`` extended linear cache size if exists, otherwise zero. h](j)}(h``cache_size``h]j)}(hj11h]h cache_size}(hj31hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/1ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhhj+1ubj)}(hhh]jq)}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hjJ1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjF1hMhhjG1ubah}(h]h ]h"]h$]h&]uh1jhj+1ubeh}(h]h ]h"]h$]h&]uh1jhjF1hMhhj0ubj)}(h;``region_id`` region id for next region provisioning event h](j)}(h ``region_id``h]j)}(hjj1h]h region_id}(hjl1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh1ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMihjd1ubj)}(hhh]jq)}(h,region id for next region provisioning eventh]h,region id for next region provisioning event}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj1hMihj1ubah}(h]h ]h"]h$]h&]uh1jhjd1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMihj0ubj)}(h7``platform_data`` platform specific configuration data h](j)}(h``platform_data``h]j)}(hj1h]h platform_data}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMjhj1ubj)}(hhh]jq)}(h$platform specific configuration datah]h$platform specific configuration data}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj1hMjhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMjhj0ubj)}(h:``range_lock`` sync region autodiscovery by address range h](j)}(h``range_lock``h]j)}(hj1h]h range_lock}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMkhj1ubj)}(hhh]jq)}(h*sync region autodiscovery by address rangeh]h*sync region autodiscovery by address range}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj1hMkhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hMkhj0ubj)}(h+``qos_class`` QoS performance class cookie h](j)}(h ``qos_class``h]j)}(hj2h]h qos_class}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMlhj2ubj)}(hhh]jq)}(hQoS performance class cookieh]hQoS performance class cookie}(hj.2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj*2hMlhj+2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj*2hMlhj0ubj)}(h$``ops`` CXL root decoder operations h](j)}(h``ops``h]j)}(hjN2h]hops}(hjP2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL2ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMmhjH2ubj)}(hhh]jq)}(hCXL root decoder operationsh]hCXL root decoder operations}(hjg2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjc2hMmhjd2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubeh}(h]h ]h"]h$]h&]uh1jhjc2hMmhj0ubj)}(h!``cxlsd`` base cxl switch decoderh](j)}(h ``cxlsd``h]j)}(hj2h]hcxlsd}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMmhj2ubj)}(hhh]jq)}(hbase cxl switch decoderh]hbase cxl switch decoder}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMnhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMmhj0ubeh}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_region_params (C struct)c.cxl_region_paramshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_region_paramsh]jB)}(hstruct cxl_region_paramsh](j)}(hjh]hstruct}(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMtubjZ)}(h h]h }(hj2hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj2hhhj2hMtubjk)}(hcxl_region_paramsh]jq)}(hj2h]hcxl_region_params}(hj3hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj2hhhj2hMtubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj2hhhj2hMtubah}(h]j2ah ](jjeh"]h$]h&]jj)jhuh1j;hj2hMthj2hhubj)}(hhh]jq)}(hregion settingsh]hregion settings}(hj#3hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj 3hhubah}(h]h ]h"]h$]h&]uh1jhj2hhhj2hMtubeh}(h]h ](jstructeh"]h$]h&]jjjj;3jj;3jjjuh1j6hhhjp'hNhNubj)}(hX-**Definition**:: struct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; }; **Members** ``state`` allow the driver to lockdown further parameter changes ``uuid`` unique id for persistent regions ``interleave_ways`` number of endpoints in the region ``interleave_granularity`` capacity each endpoint contributes to a stripe ``res`` allocated iomem capacity for this region ``targets`` active ordered targets in current decoder configuration ``nr_targets`` number of targets ``cache_size`` extended linear cache size if exists, otherwise zero.h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjG3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC3ubh:}(hjC3hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj?3ubj)}(hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };h]hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };}hj`3sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj?3ubjq)}(h **Members**h]j)}(hjq3h]hMembers}(hjs3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo3ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj?3ubj)}(hhh](j)}(hA``state`` allow the driver to lockdown further parameter changes h](j)}(h ``state``h]j)}(hj3h]hstate}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj3ubj)}(hhh]jq)}(h6allow the driver to lockdown further parameter changesh]h6allow the driver to lockdown further parameter changes}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhj3ubj)}(h*``uuid`` unique id for persistent regions h](j)}(h``uuid``h]j)}(hj3h]huuid}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj3ubj)}(hhh]jq)}(h unique id for persistent regionsh]h unique id for persistent regions}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj3hMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hMhj3ubj)}(h6``interleave_ways`` number of endpoints in the region h](j)}(h``interleave_ways``h]j)}(hj4h]hinterleave_ways}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj3ubj)}(hhh]jq)}(h!number of endpoints in the regionh]h!number of endpoints in the region}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj3ubj)}(hJ``interleave_granularity`` capacity each endpoint contributes to a stripe h](j)}(h``interleave_granularity``h]j)}(hj;4h]hinterleave_granularity}(hj=4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj94ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj54ubj)}(hhh]jq)}(h.capacity each endpoint contributes to a stripeh]h.capacity each endpoint contributes to a stripe}(hjT4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjP4hMhjQ4ubah}(h]h ]h"]h$]h&]uh1jhj54ubeh}(h]h ]h"]h$]h&]uh1jhjP4hMhj3ubj)}(h1``res`` allocated iomem capacity for this region h](j)}(h``res``h]j)}(hjt4h]hres}(hjv4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjr4ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjn4ubj)}(hhh]jq)}(h(allocated iomem capacity for this regionh]h(allocated iomem capacity for this region}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhjn4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj3ubj)}(hD``targets`` active ordered targets in current decoder configuration h](j)}(h ``targets``h]j)}(hj4h]htargets}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4ubj)}(hhh]jq)}(h7active ordered targets in current decoder configurationh]h7active ordered targets in current decoder configuration}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj3ubj)}(h!``nr_targets`` number of targets h](j)}(h``nr_targets``h]j)}(hj4h]h nr_targets}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4ubj)}(hhh]jq)}(hnumber of targetsh]hnumber of targets}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj3ubj)}(hD``cache_size`` extended linear cache size if exists, otherwise zero.h](j)}(h``cache_size``h]j)}(hj5h]h cache_size}(hj!5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]jq)}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hj85hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj55ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj45hMhj3ubeh}(h]h ]h"]h$]h&]uh1jhj?3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(h**Description**h]j)}(hjb5h]h Description}(hjd5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`5ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjp'hhubjq)}(h3State transitions are protected by cxl_rwsem.regionh]h3State transitions are protected by cxl_rwsem.region}(hjx5hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_region (C struct) c.cxl_regionhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h cxl_regionh]jB)}(hstruct cxl_regionh](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjZ)}(h h]h }(hj5hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj5hhhj5hMubjk)}(h cxl_regionh]jq)}(hj5h]h cxl_region}(hj5hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj5ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj5hhhj5hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj5hhhj5hMubah}(h]j5ah ](jjeh"]h$]h&]jj)jhuh1j;hj5hMhj5hhubj)}(hhh]jq)}(h CXL regionh]h CXL region}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5hhubah}(h]h ]h"]h$]h&]uh1jhj5hhhj5hMubeh}(h]h ](jstructeh"]h$]h&]jjjj5jj5jjjuh1j6hhhjp'hNhNubj)}(hX**Definition**:: struct cxl_region { struct device dev; int id; struct cxl_root_decoder *cxlrd; struct range hpa_range; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block node_notifier; struct notifier_block adist_notifier; }; **Members** ``dev`` This region's device ``id`` This region's id. Id is globally unique across all regions ``cxlrd`` Region's root decoder ``hpa_range`` Address range occupied by the region ``mode`` Operational mode of the mapped capacity ``type`` Endpoint decoder target type ``cxl_nvb`` nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown ``cxlr_pmem`` (for pmem regions) cached copy of the nvdimm bridge ``flags`` Region state flags ``params`` active + config params for the region ``coord`` QoS access coordinates for the region ``node_notifier`` notifier for setting the access coordinates to node ``adist_notifier`` notifier for calculating the abstract distance of nodeh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh:}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hXstruct cxl_region { struct device dev; int id; struct cxl_root_decoder *cxlrd; struct range hpa_range; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block node_notifier; struct notifier_block adist_notifier; };h]hXstruct cxl_region { struct device dev; int id; struct cxl_root_decoder *cxlrd; struct range hpa_range; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block node_notifier; struct notifier_block adist_notifier; };}hj6sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubjq)}(h **Members**h]j)}(hj06h]hMembers}(hj26hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.6ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh](j)}(h``dev`` This region's device h](j)}(h``dev``h]j)}(hjO6h]hdev}(hjQ6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM6ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjI6ubj)}(hhh]jq)}(hThis region's deviceh]hThis region’s device}(hjh6hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjd6hMhje6ubah}(h]h ]h"]h$]h&]uh1jhjI6ubeh}(h]h ]h"]h$]h&]uh1jhjd6hMhjF6ubj)}(hB``id`` This region's id. Id is globally unique across all regions h](j)}(h``id``h]j)}(hj6h]hid}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6ubj)}(hhh]jq)}(h:This region's id. Id is globally unique across all regionsh]h8hMhj?8ubah}(h]h ]h"]h$]h&]uh1jhj#8ubeh}(h]h ]h"]h$]h&]uh1jhj>8hMhjF6ubj)}(h1``params`` active + config params for the region h](j)}(h ``params``h]j)}(hjb8h]hparams}(hjd8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`8ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj\8ubj)}(hhh]jq)}(h%active + config params for the regionh]h%active + config params for the region}(hj{8hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjw8hMhjx8ubah}(h]h ]h"]h$]h&]uh1jhj\8ubeh}(h]h ]h"]h$]h&]uh1jhjw8hMhjF6ubj)}(h0``coord`` QoS access coordinates for the region h](j)}(h ``coord``h]j)}(hj8h]hcoord}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8ubj)}(hhh]jq)}(h%QoS access coordinates for the regionh]h%QoS access coordinates for the region}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhjF6ubj)}(hF``node_notifier`` notifier for setting the access coordinates to node h](j)}(h``node_notifier``h]j)}(hj8h]h node_notifier}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8ubj)}(hhh]jq)}(h3notifier for setting the access coordinates to nodeh]h3notifier for setting the access coordinates to node}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhjF6ubj)}(hI``adist_notifier`` notifier for calculating the abstract distance of nodeh](j)}(h``adist_notifier``h]j)}(hj 9h]hadist_notifier}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 9ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]jq)}(h6notifier for calculating the abstract distance of nodeh]h6notifier for calculating the abstract distance of node}(hj&9hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj#9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj"9hMhjF6ubeh}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_port (C struct) c.cxl_porthNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_porth]jB)}(hstruct cxl_porth](j)}(hjh]hstruct}(hjg9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjc9hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjZ)}(h h]h }(hju9hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjc9hhhjt9hMubjk)}(hcxl_porth]jq)}(hja9h]hcxl_port}(hj9hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj9ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjc9hhhjt9hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj_9hhhjt9hMubah}(h]jZ9ah ](jjeh"]h$]h&]jj)jhuh1j;hjt9hMhj\9hhubj)}(hhh]jq)}(hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.h]hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9hhubah}(h]h ]h"]h$]h&]uh1jhj\9hhhjt9hMubeh}(h]h ](jstructeh"]h$]h&]jjjj9jj9jjjuh1j6hhhjp'hNhNubj)}(hXP**Definition**:: struct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; struct cxl_component_regs regs; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; resource_size_t component_reg_phys; }; **Members** ``dev`` this port's device ``uport_dev`` PCI or platform device implementing the upstream port capability ``host_bridge`` Shortcut to the platform attach point for this port ``id`` id for port device-name ``dports`` cxl_dport instances referenced by decoders ``endpoints`` cxl_ep instances, endpoints that are a descendant of this port ``regions`` cxl_region_ref instances, regions mapped by this port ``parent_dport`` dport that points to this port in the parent ``decoder_ida`` allocator for decoder ids ``reg_map`` component and ras register mapping parameters ``regs`` mapped component registers ``nr_dports`` number of entries in **dports** ``hdm_end`` track last allocated HDM decoder instance for allocation ordering ``commit_end`` cursor to track highest committed decoder for commit ordering ``dead`` last ep has been removed, force port re-creation ``depth`` How deep this port is relative to the root. depth 0 is the root. ``cdat`` Cached CDAT data ``cdat_available`` Should a CDAT attribute be available in sysfs ``pci_latency`` Upstream latency in picoseconds ``component_reg_phys`` Physical address of component registerh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubh:}(hj9hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hXTstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; struct cxl_component_regs regs; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; resource_size_t component_reg_phys; };h]hXTstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; struct cxl_component_regs regs; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; resource_size_t component_reg_phys; };}hj9sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9ubjq)}(h **Members**h]j)}(hj9h]hMembers}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM0hj9ubj)}(hhh](j)}(h``dev`` this port's device h](j)}(h``dev``h]j)}(hj:h]hdev}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]jq)}(hthis port's deviceh]hthis port’s device}(hj/:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj+:hMhj,:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj+:hMhj :ubj)}(hO``uport_dev`` PCI or platform device implementing the upstream port capability h](j)}(h ``uport_dev``h]j)}(hjO:h]h uport_dev}(hjQ:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM:ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjI:ubj)}(hhh]jq)}(h@PCI or platform device implementing the upstream port capabilityh]h@PCI or platform device implementing the upstream port capability}(hjh:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjd:hMhje:ubah}(h]h ]h"]h$]h&]uh1jhjI:ubeh}(h]h ]h"]h$]h&]uh1jhjd:hMhj :ubj)}(hD``host_bridge`` Shortcut to the platform attach point for this port h](j)}(h``host_bridge``h]j)}(hj:h]h host_bridge}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]jq)}(h3Shortcut to the platform attach point for this porth]h3Shortcut to the platform attach point for this port}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj :ubj)}(h``id`` id for port device-name h](j)}(h``id``h]j)}(hj:h]hid}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]jq)}(hid for port device-nameh]hid for port device-name}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj :ubj)}(h6``dports`` cxl_dport instances referenced by decoders h](j)}(h ``dports``h]j)}(hj:h]hdports}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]jq)}(h*cxl_dport instances referenced by decodersh]h*cxl_dport instances referenced by decoders}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj :ubj)}(hM``endpoints`` cxl_ep instances, endpoints that are a descendant of this port h](j)}(h ``endpoints``h]j)}(hj3;h]h endpoints}(hj5;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1;ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj-;ubj)}(hhh]jq)}(h>cxl_ep instances, endpoints that are a descendant of this porth]h>cxl_ep instances, endpoints that are a descendant of this port}(hjL;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjH;hMhjI;ubah}(h]h ]h"]h$]h&]uh1jhj-;ubeh}(h]h ]h"]h$]h&]uh1jhjH;hMhj :ubj)}(hB``regions`` cxl_region_ref instances, regions mapped by this port h](j)}(h ``regions``h]j)}(hjl;h]hregions}(hjn;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjj;ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjf;ubj)}(hhh]jq)}(h5cxl_region_ref instances, regions mapped by this porth]h5cxl_region_ref instances, regions mapped by this port}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhjf;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj :ubj)}(h>``parent_dport`` dport that points to this port in the parent h](j)}(h``parent_dport``h]j)}(hj;h]h parent_dport}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]jq)}(h,dport that points to this port in the parenth]h,dport that points to this port in the parent}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj :ubj)}(h*``decoder_ida`` allocator for decoder ids h](j)}(h``decoder_ida``h]j)}(hj;h]h decoder_ida}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]jq)}(hallocator for decoder idsh]hallocator for decoder ids}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj :ubj)}(h:``reg_map`` component and ras register mapping parameters h](j)}(h ``reg_map``h]j)}(hj<h]hreg_map}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj<ubj)}(hhh]jq)}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hj0<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj,<hMhj-<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj,<hMhj :ubj)}(h$``regs`` mapped component registers h](j)}(h``regs``h]j)}(hjP<h]hregs}(hjR<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjN<ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjJ<ubj)}(hhh]jq)}(hmapped component registersh]hmapped component registers}(hji<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphje<hMhjf<ubah}(h]h ]h"]h$]h&]uh1jhjJ<ubeh}(h]h ]h"]h$]h&]uh1jhje<hMhj :ubj)}(h.``nr_dports`` number of entries in **dports** h](j)}(h ``nr_dports``h]j)}(hj<h]h nr_dports}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj<ubj)}(hhh]jq)}(hnumber of entries in **dports**h](hnumber of entries in }(hj<hhhNhNubj)}(h **dports**h]hdports}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jphj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj :ubj)}(hN``hdm_end`` track last allocated HDM decoder instance for allocation ordering h](j)}(h ``hdm_end``h]j)}(hj<h]hhdm_end}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM hj<ubj)}(hhh]jq)}(hAtrack last allocated HDM decoder instance for allocation orderingh]hAtrack last allocated HDM decoder instance for allocation ordering}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj<hM hj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hM hj :ubj)}(hM``commit_end`` cursor to track highest committed decoder for commit ordering h](j)}(h``commit_end``h]j)}(hj =h]h commit_end}(hj =hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM!hj=ubj)}(hhh]jq)}(h=cursor to track highest committed decoder for commit orderingh]h=cursor to track highest committed decoder for commit ordering}(hj"=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj=hM!hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hM!hj :ubj)}(h:``dead`` last ep has been removed, force port re-creation h](j)}(h``dead``h]j)}(hjB=h]hdead}(hjD=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@=ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM"hj<=ubj)}(hhh]jq)}(h0last ep has been removed, force port re-creationh]h0last ep has been removed, force port re-creation}(hj[=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjW=hM"hjX=ubah}(h]h ]h"]h$]h&]uh1jhj<=ubeh}(h]h ]h"]h$]h&]uh1jhjW=hM"hj :ubj)}(hK``depth`` How deep this port is relative to the root. depth 0 is the root. h](j)}(h ``depth``h]j)}(hj{=h]hdepth}(hj}=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy=ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM#hju=ubj)}(hhh]jq)}(h@How deep this port is relative to the root. depth 0 is the root.h]h@How deep this port is relative to the root. depth 0 is the root.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj=hM#hj=ubah}(h]h ]h"]h$]h&]uh1jhju=ubeh}(h]h ]h"]h$]h&]uh1jhj=hM#hj :ubj)}(h``cdat`` Cached CDAT data h](j)}(h``cdat``h]j)}(hj=h]hcdat}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM$hj=ubj)}(hhh]jq)}(hCached CDAT datah]hCached CDAT data}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj=hM$hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hM$hj :ubj)}(hA``cdat_available`` Should a CDAT attribute be available in sysfs h](j)}(h``cdat_available``h]j)}(hj=h]hcdat_available}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM%hj=ubj)}(hhh]jq)}(h-Should a CDAT attribute be available in sysfsh]h-Should a CDAT attribute be available in sysfs}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj>hM%hj>ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj>hM%hj :ubj)}(h0``pci_latency`` Upstream latency in picoseconds h](j)}(h``pci_latency``h]j)}(hj&>h]h pci_latency}(hj(>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$>ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM&hj >ubj)}(hhh]jq)}(hUpstream latency in picosecondsh]hUpstream latency in picoseconds}(hj?>hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj;>hM&hj<>ubah}(h]h ]h"]h$]h&]uh1jhj >ubeh}(h]h ]h"]h$]h&]uh1jhj;>hM&hj :ubj)}(h=``component_reg_phys`` Physical address of component registerh](j)}(h``component_reg_phys``h]j)}(hj_>h]hcomponent_reg_phys}(hja>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]>ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM&hjY>ubj)}(hhh]jq)}(h&Physical address of component registerh]h&Physical address of component register}(hjx>hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM'hju>ubah}(h]h ]h"]h$]h&]uh1jhjY>ubeh}(h]h ]h"]h$]h&]uh1jhjt>hM&hj :ubeh}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_root (C struct) c.cxl_roothNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcxl_rooth]jB)}(hstruct cxl_rooth](j)}(hjh]hstruct}(hj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM-ubjZ)}(h h]h }(hj>hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj>hhhj>hM-ubjk)}(hcxl_rooth]jq)}(hj>h]hcxl_root}(hj>hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj>ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj>hhhj>hM-ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj>hhhj>hM-ubah}(h]j>ah ](jjeh"]h$]h&]jj)jhuh1j;hj>hM-hj>hhubj)}(hhh]jq)}(h)logical collection of root cxl_port itemsh]h)logical collection of root cxl_port items}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhj>hhubah}(h]h ]h"]h$]h&]uh1jhj>hhhj>hM-ubeh}(h]h ](jstructeh"]h$]h&]jjjj?jj?jjjuh1j6hhhjp'hNhNubj)}(h**Definition**:: struct cxl_root { struct cxl_port port; struct cxl_root_ops ops; }; **Members** ``port`` cxl_port member ``ops`` cxl root operationsh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMPhj?ubj)}(hKstruct cxl_root { struct cxl_port port; struct cxl_root_ops ops; };h]hKstruct cxl_root { struct cxl_port port; struct cxl_root_ops ops; };}hj8?sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMRhj?ubjq)}(h **Members**h]j)}(hjI?h]hMembers}(hjK?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG?ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMWhj?ubj)}(hhh](j)}(h``port`` cxl_port member h](j)}(h``port``h]j)}(hjh?h]hport}(hjj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf?ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMOhjb?ubj)}(hhh]jq)}(hcxl_port memberh]hcxl_port member}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj}?hMOhj~?ubah}(h]h ]h"]h$]h&]uh1jhjb?ubeh}(h]h ]h"]h$]h&]uh1jhj}?hMOhj_?ubj)}(h``ops`` cxl root operationsh](j)}(h``ops``h]j)}(hj?h]hops}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMOhj?ubj)}(hhh]jq)}(hcxl root operationsh]hcxl root operations}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMPhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMOhj_?ubeh}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_dport (C struct) c.cxl_dporthNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h cxl_dporth]jB)}(hstruct cxl_dporth](j)}(hjh]hstruct}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMVubjZ)}(h h]h }(hj @hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj?hhhj@hMVubjk)}(h cxl_dporth]jq)}(hj?h]h cxl_dport}(hj@hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj?hhhj@hMVubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj?hhhj@hMVubah}(h]j?ah ](jjeh"]h$]h&]jj)jhuh1j;hj@hMVhj?hhubj)}(hhh]jq)}(hCXL downstream porth]hCXL downstream port}(hj=@hhhNhNubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhhj:@hhubah}(h]h ]h"]h$]h&]uh1jhj?hhhj@hMVubeh}(h]h ](jstructeh"]h$]h&]jjjjU@jjU@jjjuh1j6hhhjp'hNhNubj)}(hX**Definition**:: struct cxl_dport { struct device *dport_dev; struct cxl_register_map reg_map; int port_id; struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port; struct cxl_regs regs; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; long link_latency; int gpf_dvsec; }; **Members** ``dport_dev`` PCI bridge or firmware device representing the downstream link ``reg_map`` component and ras register mapping parameters ``port_id`` unique hardware identifier for dport in decoder target list ``rcrb`` Data about the Root Complex Register Block layout ``rch`` Indicate whether this dport was enumerated in RCH or VH mode ``port`` reference to cxl_port that contains this downstream port ``regs`` Dport parsed register blocks ``coord`` access coordinates (bandwidth and latency performance attributes) ``link_latency`` calculated PCIe downstream latency ``gpf_dvsec`` Cached GPF port DVSECh](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hja@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]@ubh:}(hj]@hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMlhjY@ubj)}(hX0struct cxl_dport { struct device *dport_dev; struct cxl_register_map reg_map; int port_id; struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port; struct cxl_regs regs; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; long link_latency; int gpf_dvsec; };h]hX0struct cxl_dport { struct device *dport_dev; struct cxl_register_map reg_map; int port_id; struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port; struct cxl_regs regs; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; long link_latency; int gpf_dvsec; };}hjz@sbah}(h]h ]h"]h$]h&]hhuh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMnhjY@ubjq)}(h **Members**h]j)}(hj@h]hMembers}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jphe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM{hjY@ubj)}(hhh](j)}(hM``dport_dev`` PCI bridge or firmware device representing the downstream link h](j)}(h ``dport_dev``h]j)}(hj@h]h dport_dev}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMjhj@ubj)}(hhh]jq)}(h>PCI bridge or firmware device representing the downstream linkh]h>PCI bridge or firmware device representing the downstream link}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj@hMjhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMjhj@ubj)}(h:``reg_map`` component and ras register mapping parameters h](j)}(h ``reg_map``h]j)}(hj@h]hreg_map}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMkhj@ubj)}(hhh]jq)}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj@hMkhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMkhj@ubj)}(hH``port_id`` unique hardware identifier for dport in decoder target list h](j)}(h ``port_id``h]j)}(hjAh]hport_id}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMlhjAubj)}(hhh]jq)}(h;unique hardware identifier for dport in decoder target listh]h;unique hardware identifier for dport in decoder target list}(hj5AhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj1AhMlhj2Aubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj1AhMlhj@ubj)}(h;``rcrb`` Data about the Root Complex Register Block layout h](j)}(h``rcrb``h]j)}(hjUAh]hrcrb}(hjWAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSAubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMmhjOAubj)}(hhh]jq)}(h1Data about the Root Complex Register Block layouth]h1Data about the Root Complex Register Block layout}(hjnAhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjjAhMmhjkAubah}(h]h ]h"]h$]h&]uh1jhjOAubeh}(h]h ]h"]h$]h&]uh1jhjjAhMmhj@ubj)}(hE``rch`` Indicate whether this dport was enumerated in RCH or VH mode h](j)}(h``rch``h]j)}(hjAh]hrch}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMnhjAubj)}(hhh]jq)}(hdpa_res** resource treeh](hTrack DPA ‘skip’ in }(hjNhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubh resource tree}(hjNhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM hjNhhubah}(h]h ]h"]h$]h&]uh1jhjLhhhj MhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjOjjOjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** ``struct cxl_endpoint_decoder *cxled`` Endpoint decoder establishing new allocation that skips lower DPA ``const resource_size_t skip_base`` DPA < start of new DPA allocation (DPAnew) ``const resource_size_t skip_len`` **skip_base** + **skip_len** == DPAnew **Description** DPA 'skip' arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. It is a wasteful event as usable DPA gets thrown away, but if a deployment has, for example, a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM DPA, the free RAM DPA must be sacrificed to start allocating PMEM. See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder Protection" for more details. A 'skip' always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation). If **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](jq)}(h**Parameters**h]j)}(hj&Oh]h Parameters}(hj(OhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$Oubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM$hj Oubj)}(hhh](j)}(hN``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** h](j)}(h``struct cxl_dev_state *cxlds``h]j)}(hjEOh]hstruct cxl_dev_state *cxlds}(hjGOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCOubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM!hj?Oubj)}(hhh]jq)}(h-CXL.mem device context that parents **cxled**h](h$CXL.mem device context that parents }(hj^OhhhNhNubj)}(h **cxled**h]hcxled}(hjfOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Oubeh}(h]h ]h"]h$]h&]uh1jphjZOhM!hj[Oubah}(h]h ]h"]h$]h&]uh1jhj?Oubeh}(h]h ]h"]h$]h&]uh1jhjZOhM!hjnr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](hIf }(hjPhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhf was guaranteed to be <= 2 then the ‘skip’ would always be contained to a single partition. Given }(hjPhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubhX may be > 2 it results in cases where the ‘skip’ might span “tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]” to support allocating from partition[N]. That in turn interacts with the partition ‘struct resource’ boundaries within }(hjPhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubh whereby ‘skip’ requests need to be divided by partition. I.e. this is a quirk of using a ‘struct resource’ tree to detect range conflicts while also tracking partition boundaries in }(hjPhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubh.}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM3hj Oubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2(devm_cxl_enumerate_decoders (C function)c.devm_cxl_enumerate_decodershNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h^int devm_cxl_enumerate_decoders (struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]jB)}(h]int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](jH)}(hinth]hint}(hjQhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjQhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMubjZ)}(h h]h }(hjQhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjQhhhjQhMubjk)}(hdevm_cxl_enumerate_decodersh]jq)}(hdevm_cxl_enumerate_decodersh]hdevm_cxl_enumerate_decoders}(hj%QhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj!Qubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjQhhhjQhMubj)}(h>(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hjAQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=QubjZ)}(h h]h }(hjNQhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj=Qubh)}(hhh]jq)}(hcxl_hdmh]hcxl_hdm}(hj_QhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj\Qubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjaQmodnameN classnameNjj)}j]j)}jj'Qsbc.devm_cxl_enumerate_decodersasbuh1hhj=QubjZ)}(h h]h }(hjQhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj=Qubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=Qubjq)}(hcxlhdmh]hcxlhdm}(hjQhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj=Qubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj9Qubj)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubjZ)}(h h]h }(hjQhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjQubh)}(hhh]jq)}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjQhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjQubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjQmodnameN classnameNjj)}j]j{Qc.devm_cxl_enumerate_decodersasbuh1hhjQubjZ)}(h h]h }(hjQhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjQubj)}(hjh]h*}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjQubjq)}(hinfoh]hinfo}(hj RhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjQubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj9Qubeh}(h]h ]h"]h$]h&]hhuh1jhjQhhhjQhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjPhhhjQhMubah}(h]jPah ](jjeh"]h$]h&]jj)jhuh1j;hjQhMhjPhhubj)}(hhh]jq)}(h(add decoder objects per HDM register seth]h(add decoder objects per HDM register set}(hj4RhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhj1Rhhubah}(h]h ]h"]h$]h&]uh1jhjPhhhjQhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjLRjjLRjjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_hdm *cxlhdm`` Structure to populate with HDM capabilities ``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](jq)}(h**Parameters**h]j)}(hjVRh]h Parameters}(hjXRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTRubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjPRubj)}(hhh](j)}(hG``struct cxl_hdm *cxlhdm`` Structure to populate with HDM capabilities h](j)}(h``struct cxl_hdm *cxlhdm``h]j)}(hjuRh]hstruct cxl_hdm *cxlhdm}(hjwRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsRubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjoRubj)}(hhh]jq)}(h+Structure to populate with HDM capabilitiesh]h+Structure to populate with HDM capabilities}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjRhMhjRubah}(h]h ]h"]h$]h&]uh1jhjoRubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjlRubj)}(hI``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](j)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjRh]h$struct cxl_endpoint_dvsec_info *info}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjRubj)}(hhh]jq)}(h cached DVSEC range register infoh]h cached DVSEC range register info}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjlRubeh}(h]h ]h"]h$]h&]uh1jhjPRubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j20devm_cxl_switch_port_decoders_setup (C function)%c.devm_cxl_switch_port_decoders_setuphNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h?int devm_cxl_switch_port_decoders_setup (struct cxl_port *port)h]jB)}(h>int devm_cxl_switch_port_decoders_setup(struct cxl_port *port)h](jH)}(hinth]hint}(hjShhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjShhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMubjZ)}(h h]h }(hjShhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjShhhjShMubjk)}(h#devm_cxl_switch_port_decoders_setuph]jq)}(h#devm_cxl_switch_port_decoders_setuph]h#devm_cxl_switch_port_decoders_setup}(hj)ShhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj%Subah}(h]h ](jjeh"]h$]h&]hhuh1jjhjShhhjShMubj)}(h(struct cxl_port *port)h]j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjEShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjASubjZ)}(h h]h }(hjRShhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjASubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjcShhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj`Subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjeSmodnameN classnameNjj)}j]j)}jj+Ssb%c.devm_cxl_switch_port_decoders_setupasbuh1hhjASubjZ)}(h h]h }(hjShhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjASubj)}(hjh]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjASubjq)}(hporth]hport}(hjShhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjASubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj=Subah}(h]h ]h"]h$]h&]hhuh1jhjShhhjShMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjShhhjShMubah}(h]jRah ](jjeh"]h$]h&]jj)jhuh1j;hjShMhjRhhubj)}(hhh]jq)}(h"allocate and setup switch decodersh]h"allocate and setup switch decoders}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjShhubah}(h]h ]h"]h$]h&]uh1jhjRhhhjShMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjSjjSjjjuh1j6hhhjp'hNhNubj)}(hj**Parameters** ``struct cxl_port *port`` CXL port context **Description** Return 0 or -errno on errorh](jq)}(h**Parameters**h]j)}(hjSh]h Parameters}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjSubj)}(hhh]j)}(h+``struct cxl_port *port`` CXL port context h](j)}(h``struct cxl_port *port``h]j)}(hj Th]hstruct cxl_port *port}(hj ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjTubj)}(hhh]jq)}(hCXL port contexth]hCXL port context}(hj"ThhhNhNubah}(h]h ]h"]h$]h&]uh1jphjThMhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjThMhjTubah}(h]h ]h"]h$]h&]uh1jhjSubjq)}(h**Description**h]j)}(hjDTh]h Description}(hjFThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBTubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjSubjq)}(hReturn 0 or -errno on errorh]hReturn 0 or -errno on error}(hjZThhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjSubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2-devm_cxl_endpoint_decoders_setup (C function)"c.devm_cxl_endpoint_decoders_setuphNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hint cxl_add_ep(struct cxl_dport *dport, struct device *ep_dev)h](jH)}(hinth]hint}(hjbphhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj^phhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM2ubjZ)}(h h]h }(hjqphhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj^phhhjpphM2ubjk)}(h cxl_add_eph]jq)}(h cxl_add_eph]h cxl_add_ep}(hjphhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjpubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj^phhhjpphM2ubj)}(h0(struct cxl_dport *dport, struct device *ep_dev)h](j)}(hstruct cxl_dport *dporth](j)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubjZ)}(h h]h }(hjphhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjpubh)}(hhh]jq)}(h cxl_dporth]h cxl_dport}(hjphhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjpmodnameN classnameNjj)}j]j)}jjpsb c.cxl_add_epasbuh1hhjpubjZ)}(h h]h }(hjphhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjpubj)}(hjh]h*}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubjq)}(hdporth]hdport}(hjphhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjpubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjpubj)}(hstruct device *ep_devh](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj qubjZ)}(h h]h }(hjqhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj qubh)}(hhh]jq)}(hdeviceh]hdevice}(hj/qhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj,qubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj1qmodnameN classnameNjj)}j]jp c.cxl_add_epasbuh1hhj qubjZ)}(h h]h }(hjMqhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj qubj)}(hjh]h*}(hj[qhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj qubjq)}(hep_devh]hep_dev}(hjhqhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj qubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjpubeh}(h]h ]h"]h$]h&]hhuh1jhj^phhhjpphM2ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjZphhhjpphM2ubah}(h]jUpah ](jjeh"]h$]h&]jj)jhuh1j;hjpphM2hjWphhubj)}(hhh]jq)}(h)register an endpoint's interest in a porth]h+register an endpoint’s interest in a port}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM2hjqhhubah}(h]h ]h"]h$]h&]uh1jhjWphhhjpphM2ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjqjjqjjjuh1j6hhhjp'hNhNubj)}(hX]**Parameters** ``struct cxl_dport *dport`` the dport that routes to **ep_dev** ``struct device *ep_dev`` device representing the endpoint **Description** Intermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h](jq)}(h**Parameters**h]j)}(hjqh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM6hjqubj)}(hhh](j)}(h@``struct cxl_dport *dport`` the dport that routes to **ep_dev** h](j)}(h``struct cxl_dport *dport``h]j)}(hjqh]hstruct cxl_dport *dport}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM3hjqubj)}(hhh]jq)}(h#the dport that routes to **ep_dev**h](hthe dport that routes to }(hjqhhhNhNubj)}(h **ep_dev**h]hep_dev}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jphjqhM3hjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjqhM3hjqubj)}(h;``struct device *ep_dev`` device representing the endpoint h](j)}(h``struct device *ep_dev``h]j)}(hjrh]hstruct device *ep_dev}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM4hjrubj)}(hhh]jq)}(h device representing the endpointh]h device representing the endpoint}(hj3rhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/rhM4hj0rubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jhj/rhM4hjqubeh}(h]h ]h"]h$]h&]uh1jhjqubjq)}(h**Description**h]j)}(hjUrh]h Description}(hjWrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSrubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM6hjqubjq)}(hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h]hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.}(hjkrhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM5hjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2#find_cxl_port_by_uport (C function)c.find_cxl_port_by_uporthNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hCstruct cxl_port * find_cxl_port_by_uport (struct device *uport_dev)h]jB)}(hAstruct cxl_port *find_cxl_port_by_uport(struct device *uport_dev)h](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM+ubjZ)}(h h]h }(hjrhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjrhhhjrhM+ubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjrhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjrubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]j)}jfind_cxl_port_by_uportsbc.find_cxl_port_by_uportasbuh1hhjrhhhjrhM+ubjZ)}(h h]h }(hjrhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjrhhhjrhM+ubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrhhhjrhM+ubjk)}(hfind_cxl_port_by_uporth]jq)}(hjrh]hfind_cxl_port_by_uport}(hjrhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjrubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjrhhhjrhM+ubj)}(h(struct device *uport_dev)h]j)}(hstruct device *uport_devh](j)}(hjh]hstruct}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubjZ)}(h h]h }(hj!shhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjsubh)}(hhh]jq)}(hdeviceh]hdevice}(hj2shhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj/subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj4smodnameN classnameNjj)}j]jrc.find_cxl_port_by_uportasbuh1hhjsubjZ)}(h h]h }(hjPshhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjsubj)}(hjh]h*}(hj^shhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubjq)}(h uport_devh]h uport_dev}(hjkshhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjsubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj subah}(h]h ]h"]h$]h&]hhuh1jhjrhhhjrhM+ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjrhhhjrhM+ubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1j;hjrhM+hjrhhubj)}(hhh]jq)}(h Find a CXL port device companionh]h Find a CXL port device companion}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM+hjshhubah}(h]h ]h"]h$]h&]uh1jhjrhhhjrhM+ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjsjjsjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct device *uport_dev`` Device that acts as a switch or endpoint in the CXL hierarchy **Description** In the case of endpoint ports recall that port->uport_dev points to a 'struct cxl_memdev' device. So, the **uport_dev** argument is the parent device of the 'struct cxl_memdev' in that case. Function takes a device reference on the port device. Caller should do a put_device() when done.h](jq)}(h**Parameters**h]j)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM/hjsubj)}(hhh]j)}(h[``struct device *uport_dev`` Device that acts as a switch or endpoint in the CXL hierarchy h](j)}(h``struct device *uport_dev``h]j)}(hjsh]hstruct device *uport_dev}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM,hjsubj)}(hhh]jq)}(h=Device that acts as a switch or endpoint in the CXL hierarchyh]h=Device that acts as a switch or endpoint in the CXL hierarchy}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jphjshM,hjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjshM,hjsubah}(h]h ]h"]h$]h&]uh1jhjsubjq)}(h**Description**h]j)}(hjth]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM.hjsubjq)}(hIn the case of endpoint ports recall that port->uport_dev points to a 'struct cxl_memdev' device. So, the **uport_dev** argument is the parent device of the 'struct cxl_memdev' in that case.h](hnIn the case of endpoint ports recall that port->uport_dev points to a ‘struct cxl_memdev’ device. So, the }(hj'thhhNhNubj)}(h **uport_dev**h]h uport_dev}(hj/thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'tubhK argument is the parent device of the ‘struct cxl_memdev’ in that case.}(hj'thhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM-hjsubjq)}(h`Function takes a device reference on the port device. Caller should do a put_device() when done.h]h`Function takes a device reference on the port device. Caller should do a put_device() when done.}(hjHthhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM1hjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_decoder_init (C function)c.cxl_decoder_inithNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hFint cxl_decoder_init (struct cxl_port *port, struct cxl_decoder *cxld)h]jB)}(hEint cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)h](jH)}(hinth]hint}(hjwthhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjsthhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjZ)}(h h]h }(hjthhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjsthhhjthMubjk)}(hcxl_decoder_inith]jq)}(hcxl_decoder_inith]hcxl_decoder_init}(hjthhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjtubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjsthhhjthMubj)}(h1(struct cxl_port *port, struct cxl_decoder *cxld)h](j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubjZ)}(h h]h }(hjthhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjtubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjthhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjtubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjtmodnameN classnameNjj)}j]j)}jjtsbc.cxl_decoder_initasbuh1hhjtubjZ)}(h h]h }(hjthhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjtubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubjq)}(hporth]hport}(hj uhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubj)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hj&uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"uubjZ)}(h h]h }(hj3uhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj"uubh)}(hhh]jq)}(h cxl_decoderh]h cxl_decoder}(hjDuhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjAuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjFumodnameN classnameNjj)}j]jtc.cxl_decoder_initasbuh1hhj"uubjZ)}(h h]h }(hjbuhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj"uubj)}(hjh]h*}(hjpuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"uubjq)}(hcxldh]hcxld}(hj}uhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj"uubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubeh}(h]h ]h"]h$]h&]hhuh1jhjsthhhjthMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjothhhjthMubah}(h]jjtah ](jjeh"]h$]h&]jj)jhuh1j;hjthMhjlthhubj)}(hhh]jq)}(h%Common decoder setup / initializationh]h%Common decoder setup / initialization}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjuhhubah}(h]h ]h"]h$]h&]uh1jhjlthhhjthMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjujjujjjuh1j6hhhjp'hNhNubj)}(hXr**Parameters** ``struct cxl_port *port`` owning port of this decoder ``struct cxl_decoder *cxld`` common decoder properties to initialize **Description** A port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()h](jq)}(h**Parameters**h]j)}(hjuh]h Parameters}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjuubj)}(hhh](j)}(h6``struct cxl_port *port`` owning port of this decoder h](j)}(h``struct cxl_port *port``h]j)}(hjuh]hstruct cxl_port *port}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjuubj)}(hhh]jq)}(howning port of this decoderh]howning port of this decoder}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjuhMhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjuubj)}(hE``struct cxl_decoder *cxld`` common decoder properties to initialize h](j)}(h``struct cxl_decoder *cxld``h]j)}(hj!vh]hstruct cxl_decoder *cxld}(hj#vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjvubj)}(hhh]jq)}(h'common decoder properties to initializeh]h'common decoder properties to initialize}(hj:vhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj6vhMhj7vubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhj6vhMhjuubeh}(h]h ]h"]h$]h&]uh1jhjuubjq)}(h**Description**h]j)}(hj\vh]h Description}(hj^vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZvubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjuubjq)}(hA port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()h]hA port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()}(hjrvhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2#cxl_root_decoder_alloc (C function)c.cxl_root_decoder_allochNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hastruct cxl_root_decoder * cxl_root_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]jB)}(h_struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjZ)}(h h]h }(hjvhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjvhhhjvhMubh)}(hhh]jq)}(hcxl_root_decoderh]hcxl_root_decoder}(hjvhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNjj)}j]j)}jcxl_root_decoder_allocsbc.cxl_root_decoder_allocasbuh1hhjvhhhjvhMubjZ)}(h h]h }(hjvhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjvhhhjvhMubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhjvhMubjk)}(hcxl_root_decoder_alloch]jq)}(hjvh]hcxl_root_decoder_alloc}(hjwhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjvubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjvhhhjvhMubj)}(h0(struct cxl_port *port, unsigned int nr_targets)h](j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubjZ)}(h h]h }(hj(whhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjwubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hj9whhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj6wubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj;wmodnameN classnameNjj)}j]jvc.cxl_root_decoder_allocasbuh1hhjwubjZ)}(h h]h }(hjWwhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjwubj)}(hjh]h*}(hjewhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjwubjq)}(hporth]hport}(hjrwhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjwubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(hunsigned int nr_targetsh](jH)}(hunsignedh]hunsigned}(hjwhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjwubjZ)}(h h]h }(hjwhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjwubjH)}(hinth]hint}(hjwhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjwubjZ)}(h h]h }(hjwhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjwubjq)}(h nr_targetsh]h nr_targets}(hjwhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjwubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubeh}(h]h ]h"]h$]h&]hhuh1jhjvhhhjvhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjvhhhjvhMubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j;hjvhMhjvhhubj)}(hhh]jq)}(hAllocate a root level decoderh]hAllocate a root level decoder}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjxjjxjjjuh1j6hhhjp'hNhNubj)}(hXk**Parameters** ``struct cxl_port *port`` owning CXL root of this decoder ``unsigned int nr_targets`` static number of downstream targets **Return** A new cxl decoder to be registered by cxl_decoder_add(). A 'CXL root' decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.h](jq)}(h**Parameters**h]j)}(hjxh]h Parameters}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj xubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj xubj)}(hhh](j)}(h:``struct cxl_port *port`` owning CXL root of this decoder h](j)}(h``struct cxl_port *port``h]j)}(hj.xh]hstruct cxl_port *port}(hj0xhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,xubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj(xubj)}(hhh]jq)}(howning CXL root of this decoderh]howning CXL root of this decoder}(hjGxhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjCxhMhjDxubah}(h]h ]h"]h$]h&]uh1jhj(xubeh}(h]h ]h"]h$]h&]uh1jhjCxhMhj%xubj)}(h@``unsigned int nr_targets`` static number of downstream targets h](j)}(h``unsigned int nr_targets``h]j)}(hjgxh]hunsigned int nr_targets}(hjixhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjexubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjaxubj)}(hhh]jq)}(h#static number of downstream targetsh]h#static number of downstream targets}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj|xhMhj}xubah}(h]h ]h"]h$]h&]uh1jhjaxubeh}(h]h ]h"]h$]h&]uh1jhj|xhMhj%xubeh}(h]h ]h"]h$]h&]uh1jhj xubjq)}(h **Return**h]j)}(hjxh]hReturn}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj xubjq)}(hA new cxl decoder to be registered by cxl_decoder_add(). A 'CXL root' decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.h]hA new cxl decoder to be registered by cxl_decoder_add(). A ‘CXL root’ decoder is one that decodes from a top-level / static platform firmware description of CXL resources into a CXL standard decode topology.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj xubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2%cxl_switch_decoder_alloc (C function)c.cxl_switch_decoder_allochNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hestruct cxl_switch_decoder * cxl_switch_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]jB)}(hcstruct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j)}(hjh]hstruct}(hjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjZ)}(h h]h }(hjxhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjxhhhjxhMubh)}(hhh]jq)}(hcxl_switch_decoderh]hcxl_switch_decoder}(hjyhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjyubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjymodnameN classnameNjj)}j]j)}jcxl_switch_decoder_allocsbc.cxl_switch_decoder_allocasbuh1hhjxhhhjxhMubjZ)}(h h]h }(hj'yhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjxhhhjxhMubj)}(hjh]h*}(hj5yhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxhhhjxhMubjk)}(hcxl_switch_decoder_alloch]jq)}(hj$yh]hcxl_switch_decoder_alloc}(hjFyhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjByubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjxhhhjxhMubj)}(h0(struct cxl_port *port, unsigned int nr_targets)h](j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjayhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]yubjZ)}(h h]h }(hjnyhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj]yubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjyhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj|yubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjymodnameN classnameNjj)}j]j"yc.cxl_switch_decoder_allocasbuh1hhj]yubjZ)}(h h]h }(hjyhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj]yubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]yubjq)}(hporth]hport}(hjyhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj]yubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjYyubj)}(hunsigned int nr_targetsh](jH)}(hunsignedh]hunsigned}(hjyhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjyubjZ)}(h h]h }(hjyhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjyubjH)}(hinth]hint}(hjyhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjyubjZ)}(h h]h }(hjyhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjyubjq)}(h nr_targetsh]h nr_targets}(hj zhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjyubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjYyubeh}(h]h ]h"]h$]h&]hhuh1jhjxhhhjxhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjxhhhjxhMubah}(h]jxah ](jjeh"]h$]h&]jj)jhuh1j;hjxhMhjxhhubj)}(hhh]jq)}(hAllocate a switch level decoderh]hAllocate a switch level decoder}(hj3zhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj0zhhubah}(h]h ]h"]h$]h&]uh1jhjxhhhjxhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjKzjjKzjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_port *port`` owning CXL switch port of this decoder ``unsigned int nr_targets`` max number of dynamically addressable downstream targets **Return** A new cxl decoder to be registered by cxl_decoder_add(). A 'switch' decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.h](jq)}(h**Parameters**h]j)}(hjUzh]h Parameters}(hjWzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSzubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjOzubj)}(hhh](j)}(hA``struct cxl_port *port`` owning CXL switch port of this decoder h](j)}(h``struct cxl_port *port``h]j)}(hjtzh]hstruct cxl_port *port}(hjvzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrzubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjnzubj)}(hhh]jq)}(h&owning CXL switch port of this decoderh]h&owning CXL switch port of this decoder}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjzhMhjzubah}(h]h ]h"]h$]h&]uh1jhjnzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjkzubj)}(hU``unsigned int nr_targets`` max number of dynamically addressable downstream targets h](j)}(h``unsigned int nr_targets``h]j)}(hjzh]hunsigned int nr_targets}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjzubj)}(hhh]jq)}(h8max number of dynamically addressable downstream targetsh]h8max number of dynamically addressable downstream targets}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjzhMhjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjzhMhjkzubeh}(h]h ]h"]h$]h&]uh1jhjOzubjq)}(h **Return**h]j)}(hjzh]hReturn}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjOzubjq)}(hXA new cxl decoder to be registered by cxl_decoder_add(). A 'switch' decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.h]hX!A new cxl decoder to be registered by cxl_decoder_add(). A ‘switch’ decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjOzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2'cxl_endpoint_decoder_alloc (C function)c.cxl_endpoint_decoder_allochNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hPstruct cxl_endpoint_decoder * cxl_endpoint_decoder_alloc (struct cxl_port *port)h]jB)}(hNstruct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)h](j)}(hjh]hstruct}(hj-{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj){hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjZ)}(h h]h }(hj;{hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj){hhhj:{hMubh)}(hhh]jq)}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hjL{hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjI{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjN{modnameN classnameNjj)}j]j)}jcxl_endpoint_decoder_allocsbc.cxl_endpoint_decoder_allocasbuh1hhj){hhhj:{hMubjZ)}(h h]h }(hjm{hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj){hhhj:{hMubj)}(hjh]h*}(hj{{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj){hhhj:{hMubjk)}(hcxl_endpoint_decoder_alloch]jq)}(hjj{h]hcxl_endpoint_decoder_alloc}(hj{hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj{ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj){hhhj:{hMubj)}(h(struct cxl_port *port)h]j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubjZ)}(h h]h }(hj{hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj{ubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hj{hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{modnameN classnameNjj)}j]jh{c.cxl_endpoint_decoder_allocasbuh1hhj{ubjZ)}(h h]h }(hj{hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj{ubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubjq)}(hporth]hport}(hj{hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubah}(h]h ]h"]h$]h&]hhuh1jhj){hhhj:{hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj%{hhhj:{hMubah}(h]j {ah ](jjeh"]h$]h&]jj)jhuh1j;hj:{hMhj"{hhubj)}(hhh]jq)}(hAllocate an endpoint decoderh]hAllocate an endpoint decoder}(hj(|hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj%|hhubah}(h]h ]h"]h$]h&]uh1jhj"{hhhj:{hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj@|jj@|jjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_port *port`` owning port of this decoder **Return** A new cxl decoder to be registered by cxl_decoder_add()h](jq)}(h**Parameters**h]j)}(hjJ|h]h Parameters}(hjL|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjH|ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM"hjD|ubj)}(hhh]j)}(h6``struct cxl_port *port`` owning port of this decoder h](j)}(h``struct cxl_port *port``h]j)}(hji|h]hstruct cxl_port *port}(hjk|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjg|ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjc|ubj)}(hhh]jq)}(howning port of this decoderh]howning port of this decoder}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj~|hMhj|ubah}(h]h ]h"]h$]h&]uh1jhjc|ubeh}(h]h ]h"]h$]h&]uh1jhj~|hMhj`|ubah}(h]h ]h"]h$]h&]uh1jhjD|ubjq)}(h **Return**h]j)}(hj|h]hReturn}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM!hjD|ubjq)}(h7A new cxl decoder to be registered by cxl_decoder_add()h]h7A new cxl decoder to be registered by cxl_decoder_add()}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM!hjD|ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2#cxl_decoder_add_locked (C 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}(hjd}hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj"}ubj)}(hjh]h*}(hjr}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"}ubjq)}(hcxldh]hcxld}(hj}hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj"}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubah}(h]h ]h"]h$]h&]hhuh1jhj|hhhj|hM?ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj|hhhj|hM?ubah}(h]j|ah ](jjeh"]h$]h&]jj)jhuh1j;hj|hM?hj|hhubj)}(hhh]jq)}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM?hj}hhubah}(h]h ]h"]h$]h&]uh1jhj|hhhj|hM?ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj}jj}jjjuh1j6hhhjp'hNhNubj)}(hX?**Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() **Description** Certain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely). This is the locked variant of cxl_decoder_add(). **Context** Process context. Expects the device lock of the port that owns the **cxld** to be held. **Return** Negative error code if the decoder wasn't properly configured; else returns 0.h](jq)}(h**Parameters**h]j)}(hj}h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMChj}ubj)}(hhh]j)}(hU``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() h](j)}(h``struct cxl_decoder *cxld``h]j)}(hj}h]hstruct cxl_decoder *cxld}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM@hj}ubj)}(hhh]jq)}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj}hM@hj~ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhj}hM@hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubjq)}(h**Description**h]j)}(hj%~h]h Description}(hj'~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#~ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMBhj}ubjq)}(hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).h]hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).}(hj;~hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMAhj}ubjq)}(h0This is the locked variant of cxl_decoder_add().h]h0This is the locked variant of cxl_decoder_add().}(hjJ~hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMEhj}ubjq)}(h **Context**h]j)}(hj[~h]hContext}(hj]~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY~ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMGhj}ubjq)}(hWProcess context. Expects the device lock of the port that owns the **cxld** to be held.h](hCProcess context. Expects the device lock of the port that owns the }(hjq~hhhNhNubj)}(h**cxld**h]hcxld}(hjy~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq~ubh to be held.}(hjq~hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMHhj}ubjq)}(h **Return**h]j)}(hj~h]hReturn}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMKhj}ubjq)}(hNNegative error code if the decoder wasn't properly configured; else returns 0.h]hPNegative error code if the decoder wasn’t properly configured; else returns 0.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMKhj}ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_decoder_add (C function)c.cxl_decoder_addhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h.int cxl_decoder_add (struct cxl_decoder *cxld)h]jB)}(h-int cxl_decoder_add(struct cxl_decoder *cxld)h](jH)}(hinth]hint}(hj~hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj~hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMtubjZ)}(h h]h }(hj~hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj~hhhj~hMtubjk)}(hcxl_decoder_addh]jq)}(hcxl_decoder_addh]hcxl_decoder_add}(hj~hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj~ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj~hhhj~hMtubj)}(h(struct cxl_decoder *cxld)h]j)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hj#hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_decoderh]h cxl_decoder}(hj4hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj1ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj6modnameN classnameNjj)}j]j)}jj~sbc.cxl_decoder_addasbuh1hhjubjZ)}(h h]h }(hjThhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxldh]hcxld}(hjohhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj~hhhj~hMtubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj~hhhj~hMtubah}(h]j~ah ](jjeh"]h$]h&]jj)jhuh1j;hj~hMthj~hhubj)}(hhh]jq)}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMthjhhubah}(h]h ]h"]h$]h&]uh1jhj~hhhj~hMtubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX6**Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() **Description** This is the unlocked variant of cxl_decoder_add_locked(). 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Takes and releases the device lock of the port that owns the **cxld**.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMxhjubj)}(hhh]j)}(hU``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() h](j)}(h``struct cxl_decoder *cxld``h]j)}(hjh]hstruct cxl_decoder *cxld}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMuhjubj)}(hhh]jq)}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMwhjubjq)}(hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().h]hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMvhjubjq)}(h **Context**h]j)}(hj<h]hContext}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMyhjubjq)}(hWProcess context. Takes and releases the device lock of the port that owns the **cxld**.h](hNProcess context. Takes and releases the device lock of the port that owns the }(hjRhhhNhNubj)}(h**cxld**h]hcxld}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubh.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMzhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2"__cxl_driver_register (C function)c.__cxl_driver_registerhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(haint __cxl_driver_register (struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h]jB)}(h`int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMubjk)}(h__cxl_driver_registerh]jq)}(h__cxl_driver_registerh]h__cxl_driver_register}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMubj)}(hG(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j)}(hstruct cxl_driver *cxl_drvh](j)}(hjh]hstruct}(hjЀhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̀ubjZ)}(h h]h }(hj݀hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj̀ubh)}(hhh]jq)}(h cxl_driverh]h cxl_driver}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.__cxl_driver_registerasbuh1hhj̀ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj̀ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̀ubjq)}(hcxl_drvh]hcxl_drv}(hj)hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj̀ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjȀubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubjZ)}(h h]h }(hjOhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj>ubh)}(hhh]jq)}(hmoduleh]hmodule}(hj`hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj]ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjbmodnameN classnameNjj)}j]j c.__cxl_driver_registerasbuh1hhj>ubjZ)}(h h]h }(hj~hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj>ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubjq)}(hownerh]howner}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj>ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjȀubj)}(hconst char *modnameh](j)}(hjNh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjH)}(hcharh]hchar}(hj́hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjubjZ)}(h h]h }(hjہhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmodnameh]hmodname}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjȀubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMhjhhubj)}(hhh]jq)}(h!register a driver for the cxl bush]h!register a driver for the cxl bus}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj8jj8jjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_driver *cxl_drv`` cxl driver structure to attach ``struct module *owner`` owning module/driver ``const char *modname`` KBUILD_MODNAME for parent driverh](jq)}(h**Parameters**h]j)}(hjBh]h Parameters}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj<ubj)}(hhh](j)}(h>``struct cxl_driver *cxl_drv`` cxl driver structure to attach h](j)}(h``struct cxl_driver *cxl_drv``h]j)}(hjah]hstruct cxl_driver *cxl_drv}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj[ubj)}(hhh]jq)}(hcxl driver structure to attachh]hcxl driver structure to attach}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjvhMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjXubj)}(h.``struct module *owner`` owning module/driver h](j)}(h``struct module *owner``h]j)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubj)}(hhh]jq)}(howning module/driverh]howning module/driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjXubj)}(h8``const char *modname`` KBUILD_MODNAME for parent driverh](j)}(h``const char *modname``h]j)}(hjӂh]hconst char *modname}(hjՂhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjтubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj͂ubj)}(hhh]jq)}(h KBUILD_MODNAME for parent driverh]h KBUILD_MODNAME for parent driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjubah}(h]h ]h"]h$]h&]uh1jhj͂ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjXubeh}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2.cxl_endpoint_get_perf_coordinates (C function)#c.cxl_endpoint_get_perf_coordinateshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h^int cxl_endpoint_get_perf_coordinates (struct cxl_port *port, struct access_coordinate *coord)h]jB)}(h]int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord)h](jH)}(hinth]hint}(hj-hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj)hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM- ubjZ)}(h h]h }(hj<hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj)hhhj;hM- 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]jfah"]h$]h&]uh1jYhj؃ubh)}(hhh]jq)}(haccess_coordinateh]haccess_coordinate}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j#c.cxl_endpoint_get_perf_coordinatesasbuh1hhj؃ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj؃ubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj؃ubjq)}(hcoordh]hcoord}(hj3hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj؃ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjbubeh}(h]h ]h"]h$]h&]hhuh1jhj)hhhj;hM- ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj%hhhj;hM- ubah}(h]j ah ](jjeh"]h$]h&]jj)jhuh1j;hj;hM- hj"hhubj)}(hhh]jq)}(h9Retrieve performance numbers stored in dports of CXL pathh]h9Retrieve performance numbers stored in dports of CXL path}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM- hjZhhubah}(h]h ]h"]h$]h&]uh1jhj"hhhj;hM- ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjujjujjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_port *port`` endpoint cxl_port ``struct access_coordinate *coord`` output performance data **Return** errno on failure, 0 on success.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM1 hjyubj)}(hhh](j)}(h,``struct cxl_port *port`` endpoint cxl_port h](j)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM/ hjubj)}(hhh]jq)}(hendpoint cxl_porth]hendpoint cxl_port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM/ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM/ hjubj)}(h<``struct access_coordinate *coord`` output performance data h](j)}(h#``struct access_coordinate *coord``h]j)}(hjׄh]hstruct access_coordinate *coord}(hjلhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjՄubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM0 hjфubj)}(hhh]jq)}(houtput performance datah]houtput performance data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjфubeh}(h]h ]h"]h$]h&]uh1jhjhM0 hjubeh}(h]h ]h"]h$]h&]uh1jhjyubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM2 hjyubjq)}(herrno on failure, 0 on success.h]herrno on failure, 0 on success.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM2 hjyubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.h]hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:454: ./drivers/cxl/core/pci.chKhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2&devm_cxl_add_dport_by_dev (C function)c.devm_cxl_add_dport_by_devhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h^struct cxl_dport * devm_cxl_add_dport_by_dev (struct cxl_port *port, struct device *dport_dev)h]jB)}(h\struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev)h](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK,ubjZ)}(h h]h }(hjthhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjbhhhjshK,ubh)}(hhh]jq)}(h cxl_dporth]h cxl_dport}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jdevm_cxl_add_dport_by_devsbc.devm_cxl_add_dport_by_devasbuh1hhjbhhhjshK,ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjbhhhjshK,ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbhhhjshK,ubjk)}(hdevm_cxl_add_dport_by_devh]jq)}(hjh]hdevm_cxl_add_dport_by_dev}(hjŅhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjbhhhjshK,ubj)}(h1(struct cxl_port *port, struct device *dport_dev)h](j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj܅ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj܅ubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.devm_cxl_add_dport_by_devasbuh1hhj܅ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj܅ubj)}(hjh]h*}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj܅ubjq)}(hporth]hport}(hj7hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj܅ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj؅ubj)}(hstruct device *dport_devh](j)}(hjh]hstruct}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubjZ)}(h h]h }(hj]hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjLubh)}(hhh]jq)}(hdeviceh]hdevice}(hjnhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjkubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjpmodnameN classnameNjj)}j]jc.devm_cxl_add_dport_by_devasbuh1hhjLubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjLubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubjq)}(h dport_devh]h dport_dev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj؅ubeh}(h]h ]h"]h$]h&]hhuh1jhjbhhhjshK,ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj^hhhjshK,ubah}(h]jYah ](jjeh"]h$]h&]jj)jhuh1j;hjshK,hj[hhubj)}(hhh]jq)}(h allocate a dport by dport deviceh]h allocate a dport by dport device}(hjцhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK,hjΆhhubah}(h]h ]h"]h$]h&]uh1jhj[hhhjshK,ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_port *port`` cxl_port that hosts the dport ``struct device *dport_dev`` 'struct device' of the dport **Description** Returns the allocated dport on success or ERR_PTR() of -errno on errorh](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK0hjubj)}(hhh](j)}(h8``struct cxl_port *port`` cxl_port that hosts the dport h](j)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK-hj ubj)}(hhh]jq)}(hcxl_port that hosts the dporth]hcxl_port that hosts the dport}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj'hK-hj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj'hK-hj ubj)}(h:``struct device *dport_dev`` 'struct device' of the dport h](j)}(h``struct device *dport_dev``h]j)}(hjKh]hstruct device *dport_dev}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK.hjEubj)}(hhh]jq)}(h'struct device' of the dporth]h ‘struct device’ of the dport}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj`hK.hjaubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhj`hK.hj ubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK0hjubjq)}(hFReturns the allocated dport on success or ERR_PTR() of -errno on errorh]hFReturns the allocated dport on success or ERR_PTR() of -errno on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chK/hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 cxl_hdm_decode_init (C function)c.cxl_hdm_decode_inithNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hsint cxl_hdm_decode_init (struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]jB)}(hrint cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](jH)}(hinth]hint}(hjˇhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjLJhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhubjZ)}(h h]h }(hjڇhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjLJhhhjهhMhubjk)}(hcxl_hdm_decode_inith]jq)}(hcxl_hdm_decode_inith]hcxl_hdm_decode_init}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjLJhhhjهhMhubj)}(h[(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j)}(hstruct cxl_dev_state *cxldsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_dev_stateh]h cxl_dev_state}(hj&hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj#ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj(modnameN classnameNjj)}j]j)}jjsbc.cxl_hdm_decode_initasbuh1hhjubjZ)}(h h]h }(hjFhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxldsh]hcxlds}(hjahhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjvubh)}(hhh]jq)}(hcxl_hdmh]hcxl_hdm}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jBc.cxl_hdm_decode_initasbuh1hhjvubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjvubj)}(hjh]h*}(hjĈhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubjq)}(hcxlhdmh]hcxlhdm}(hjшhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjvubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj modnameN classnameNjj)}j]jBc.cxl_hdm_decode_initasbuh1hhjubjZ)}(h h]h }(hj&hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hinfoh]hinfo}(hjAhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjLJhhhjهhMhubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjÇhhhjهhMhubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjهhMhhjhhubj)}(hhh]jq)}(h#Setup HDM decoding for the endpointh]h#Setup HDM decoding for the endpoint}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhhjhhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjهhMhubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` Device state ``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability ``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info **Description** Try to enable the endpoint's HDM Decoder Capabilityh](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMlhjubj)}(hhh](j)}(h-``struct cxl_dev_state *cxlds`` Device state h](j)}(h``struct cxl_dev_state *cxlds``h]j)}(hjh]hstruct cxl_dev_state *cxlds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMihjubj)}(hhh]jq)}(h Device stateh]h Device state}(hjʼnhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMihj‰ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMihjubj)}(h9``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability h](j)}(h``struct cxl_hdm *cxlhdm``h]j)}(hjh]hstruct cxl_hdm *cxlhdm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMjhj߉ubj)}(hhh]jq)}(hMapped HDM decoder Capabilityh]hMapped HDM decoder Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMjhjubah}(h]h ]h"]h$]h&]uh1jhj߉ubeh}(h]h ]h"]h$]h&]uh1jhjhMjhjubj)}(hK``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info h](j)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjh]h$struct cxl_endpoint_dvsec_info *info}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMkhjubj)}(hhh]jq)}(h!Cached DVSEC range registers infoh]h!Cached DVSEC range registers info}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj3hMkhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj3hMkhjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjYh]h Description}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMmhjubjq)}(h3Try to enable the endpoint's HDM Decoder Capabilityh]h5Try to enable the endpoint’s HDM Decoder Capability}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMlhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2read_cdat_data (C function)c.read_cdat_datahNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h+void read_cdat_data (struct cxl_port *port)h]jB)}(h*void read_cdat_data(struct cxl_port *port)h](jH)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM/ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhM/ubjk)}(hread_cdat_datah]jq)}(hread_cdat_datah]hread_cdat_data}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhM/ubj)}(h(struct cxl_port *port)h]j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjۊhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj׊ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj׊ubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.read_cdat_dataasbuh1hhj׊ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj׊ubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj׊ubjq)}(hporth]hport}(hj4hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj׊ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjӊubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM/ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhM/ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhM/hjhhubj)}(hhh]jq)}(hRead the CDAT data on this porth]hRead the CDAT data on this port}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM/hj[hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM/ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjvjjvjjjuh1j6hhhjp'hNhNubj)}(h**Parameters** ``struct cxl_port *port`` Port to read data from **Description** This call will sleep waiting for responses from the DOE mailbox.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM3hjzubj)}(hhh]j)}(h1``struct cxl_port *port`` Port to read data from h](j)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM0hjubj)}(hhh]jq)}(hPort to read data fromh]hPort to read data from}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM0hjubah}(h]h ]h"]h$]h&]uh1jhjzubjq)}(h**Description**h]j)}(hjڋh]h Description}(hj܋hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj؋ubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM2hjzubjq)}(h@This call will sleep waiting for responses from the DOE mailbox.h]h@This call will sleep waiting for responses from the DOE mailbox.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM1hjzubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 cxl_pci_get_latency (C function)c.cxl_pci_get_latencyhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h/long cxl_pci_get_latency (struct pci_dev *pdev)h]jB)}(h.long cxl_pci_get_latency(struct pci_dev *pdev)h](jH)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMubjZ)}(h h]h }(hj.hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhj-hMubjk)}(hcxl_pci_get_latencyh]jq)}(hcxl_pci_get_latencyh]hcxl_pci_get_latency}(hj@hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj<ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhj-hMubj)}(h(struct pci_dev *pdev)h]j)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubjZ)}(h h]h }(hjihhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjXubh)}(hhh]jq)}(hpci_devh]hpci_dev}(hjzhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj|modnameN classnameNjj)}j]j)}jjBsbc.cxl_pci_get_latencyasbuh1hhjXubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjXubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubjq)}(hpdevh]hpdev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjXubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjTubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj-hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhj-hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hj-hMhjhhubj)}(hhh]jq)}(h,calculate the link latency for the PCIe linkh]h,calculate the link latency for the PCIe link}(hjߌhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj܌hhubah}(h]h ]h"]h$]h&]uh1jhjhhhj-hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX7**Parameters** ``struct pci_dev *pdev`` PCI device **Return** calculated latency or 0 for no latency **Description** CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j)}(h$``struct pci_dev *pdev`` PCI device h](j)}(h``struct pci_dev *pdev``h]j)}(hj h]hstruct pci_dev *pdev}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubj)}(hhh]jq)}(h PCI deviceh]h PCI device}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj5hMhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hMhjubah}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Return**h]j)}(hj[h]hReturn}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubjq)}(h&calculated latency or 0 for no latencyh]h&calculated latency or 0 for no latency}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubjq)}(hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h]hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(hXIThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL 'bridge' device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus' device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.h]hXQThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL ‘bridge’ device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM ‘bus’ device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:460: ./drivers/cxl/core/pmem.chK hjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2#cxl_find_nvdimm_bridge (C function)c.cxl_find_nvdimm_bridgehNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hIstruct cxl_nvdimm_bridge * cxl_find_nvdimm_bridge (struct cxl_port *port)h]jB)}(hGstruct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)h](j)}(hjh]hstruct}(hj֍hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҍhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjҍhhhjhK7ubh)}(hhh]jq)}(hcxl_nvdimm_bridgeh]hcxl_nvdimm_bridge}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jcxl_find_nvdimm_bridgesbc.cxl_find_nvdimm_bridgeasbuh1hhjҍhhhjhK7ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjҍhhhjhK7ubj)}(hjh]h*}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҍhhhjhK7ubjk)}(hcxl_find_nvdimm_bridgeh]jq)}(hjh]hcxl_find_nvdimm_bridge}(hj5hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj1ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjҍhhhjhK7ubj)}(h(struct cxl_port *port)h]j)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubjZ)}(h h]h }(hj]hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjLubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hjnhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjkubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjpmodnameN classnameNjj)}j]jc.cxl_find_nvdimm_bridgeasbuh1hhjLubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjLubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubjq)}(hporth]hport}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubah}(h]h ]h"]h$]h&]hhuh1jhjҍhhhjhK7ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj΍hhhjhK7ubah}(h]jɍah ](jjeh"]h$]h&]jj)jhuh1j;hjhK7hjˍhhubj)}(hhh]jq)}(h'find a bridge device relative to a porth]h'find a bridge device relative to a port}(hjюhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7hjΎhhubah}(h]h ]h"]h$]h&]uh1jhjˍhhhjhK7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hn**Parameters** ``struct cxl_port *port`` any descendant port of an nvdimm-bridge associated root-cxl-porth](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK;hjubj)}(hhh]j)}(hZ``struct cxl_port *port`` any descendant port of an nvdimm-bridge associated root-cxl-porth](j)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK8hj ubj)}(hhh]jq)}(h@any descendant port of an nvdimm-bridge associated root-cxl-porth]h@any descendant port of an nvdimm-bridge associated root-cxl-port}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj'hK8hj(ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj'hK8hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 devm_cxl_add_nvdimm (C function)c.devm_cxl_add_nvdimmhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h^int devm_cxl_add_nvdimm (struct device *host, struct cxl_port *port, struct cxl_memdev *cxlmd)h]jB)}(h]int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, struct cxl_memdev *cxlmd)h](jH)}(hinth]hint}(hjkhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjghhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKubjZ)}(h h]h }(hjzhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjghhhjyhKubjk)}(hdevm_cxl_add_nvdimmh]jq)}(hdevm_cxl_add_nvdimmh]hdevm_cxl_add_nvdimm}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjghhhjyhKubj)}(hF(struct device *host, struct cxl_port *port, struct cxl_memdev *cxlmd)h](j)}(hstruct device *hosth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hdeviceh]hdevice}(hjƏhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjÏubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjȏmodnameN classnameNjj)}j]j)}jjsbc.devm_cxl_add_nvdimmasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hhosth]hhost}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hj'hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_porth]hcxl_port}(hj8hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj5ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj:modnameN classnameNjj)}j]jc.devm_cxl_add_nvdimmasbuh1hhjubjZ)}(h h]h }(hjVhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hporth]hport}(hjqhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct cxl_memdev *cxlmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_memdevh]h cxl_memdev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.devm_cxl_add_nvdimmasbuh1hhjubjZ)}(h h]h }(hjƐhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjԐhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxlmdh]hcxlmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjghhhjyhKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjchhhjyhKubah}(h]j^ah ](jjeh"]h$]h&]jj)jhuh1j;hjyhKhj`hhubj)}(hhh]jq)}(h/add a bridge between a cxl_memdev and an nvdimmh]h/add a bridge between a cxl_memdev and an nvdimm}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj`hhhjyhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj#jj#jjjuh1j6hhhjp'hNhNubj)}(hX,**Parameters** ``struct device *host`` host device for devm operations ``struct cxl_port *port`` any port in the CXL topology to find the nvdimm-bridge device ``struct cxl_memdev *cxlmd`` parent of the to be created cxl_nvdimm device **Return** 0 on success negative error code on failure.h](jq)}(h**Parameters**h]j)}(hj-h]h Parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj'ubj)}(hhh](j)}(h8``struct device *host`` host device for devm operations h](j)}(h``struct device *host``h]j)}(hjLh]hstruct device *host}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjFubj)}(hhh]jq)}(hhost device for devm operationsh]hhost device for devm operations}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jphjahKhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjahKhjCubj)}(hX``struct cxl_port *port`` any port in the CXL topology to find the nvdimm-bridge device h](j)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubj)}(hhh]jq)}(h=any port in the CXL topology to find the nvdimm-bridge deviceh]h=any port in the CXL topology to find the nvdimm-bridge device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(hK``struct cxl_memdev *cxlmd`` parent of the to be created cxl_nvdimm device h](j)}(h``struct cxl_memdev *cxlmd``h]j)}(hjh]hstruct cxl_memdev *cxlmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjubj)}(hhh]jq)}(h-parent of the to be created cxl_nvdimm deviceh]h-parent of the to be created cxl_nvdimm device}(hjבhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjӑhKhjԑubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjӑhKhjCubeh}(h]h ]h"]h$]h&]uh1jhj'ubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj'ubjq)}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.h]hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhjp'hhubjq)}(hVProvide common infrastructure for enumerating and mapping these discrete capabilities.h]hVProvide common infrastructure for enumerating and mapping these discrete capabilities.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2%cxl_probe_component_regs (C function)c.cxl_probe_component_regshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hivoid cxl_probe_component_regs (struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h]jB)}(hhvoid cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](jH)}(hvoidh]hvoid}(hj\hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjXhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKubjZ)}(h h]h }(hjkhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjXhhhjjhKubjk)}(hcxl_probe_component_regsh]jq)}(hcxl_probe_component_regsh]hcxl_probe_component_regs}(hj}hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjyubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjXhhhjjhKubj)}(hK(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](j)}(hstruct device *devh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_probe_component_regsasbuh1hhjubjZ)}(h h]h }(hjגhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hdevh]hdev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hvoid __iomem *baseh](jH)}(hvoidh]hvoid}(hj hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh__iomem}(hjhhhNhNubjZ)}(h h]h }(hj+hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hbaseh]hbase}(hjFhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h!struct cxl_component_reg_map *maph](j)}(hjh]hstruct}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubjZ)}(h h]h }(hjlhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj[ubh)}(hhh]jq)}(hcxl_component_reg_maph]hcxl_component_reg_map}(hj}hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjzubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jӒc.cxl_probe_component_regsasbuh1hhj[ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj[ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubjq)}(hmaph]hmap}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjXhhhjjhKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjThhhjjhKubah}(h]jOah ](jjeh"]h$]h&]jj)jhuh1j;hjjhKhjQhhubj)}(hhh]jq)}(h$Detect CXL Component register blocksh]h$Detect CXL Component register blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjݓhhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct device *dev`` Host device of the **base** mapping ``void __iomem *base`` Mapping containing the HDM Decoder Capability Header ``struct cxl_component_reg_map *map`` Map object describing the register block information found **Description** See CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interface Probe for component register information and return it in map object.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hjubj)}(hhh](j)}(h;``struct device *dev`` Host device of the **base** mapping h](j)}(h``struct device *dev``h]j)}(hj!h]hstruct device *dev}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjubj)}(hhh]jq)}(h#Host device of the **base** mappingh](hHost device of the }(hj:hhhNhNubj)}(h**base**h]hbase}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubh mapping}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj6hKhj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj6hKhjubj)}(hL``void __iomem *base`` Mapping containing the HDM Decoder Capability Header h](j)}(h``void __iomem *base``h]j)}(hjlh]hvoid __iomem *base}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjfubj)}(hhh]jq)}(h4Mapping containing the HDM Decoder Capability Headerh]h4Mapping containing the HDM Decoder Capability Header}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(ha``struct cxl_component_reg_map *map`` Map object describing the register block information found h](j)}(h%``struct cxl_component_reg_map *map``h]j)}(hjh]h!struct cxl_component_reg_map *map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKhjubj)}(hhh]jq)}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjޔubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK!hjubjq)}(hlSee CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interfaceh]hlSee CXL 2.0 8.2.4 Component Register Layout and Definition See CXL 2.0 8.2.5.5 CXL Device Register Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hjubjq)}(hEProbe for component register information and return it in map object.h]hEProbe for component register information and return it in map object.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK#hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2"cxl_probe_device_regs (C function)c.cxl_probe_device_regshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hcvoid cxl_probe_device_regs (struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h]jB)}(hbvoid cxl_probe_device_regs(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](jH)}(hvoidh]hvoid}(hj4hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj0hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKpubjZ)}(h h]h }(hjChhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj0hhhjBhKpubjk)}(hcxl_probe_device_regsh]jq)}(hcxl_probe_device_regsh]hcxl_probe_device_regs}(hjUhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjQubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj0hhhjBhKpubj)}(hH(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](j)}(hstruct device *devh](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubjZ)}(h h]h }(hj~hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjmubh)}(hhh]jq)}(hdeviceh]hdevice}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjWsbc.cxl_probe_device_regsasbuh1hhjmubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjmubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubjq)}(hdevh]hdev}(hjʕhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjmubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjiubj)}(hvoid __iomem *baseh](jH)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjߕubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjߕubh__iomem}(hjߕhhhNhNubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjߕubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjߕubjq)}(hbaseh]hbase}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjߕubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjiubj)}(hstruct cxl_device_reg_map *maph](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubjZ)}(h h]h }(hjDhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj3ubh)}(hhh]jq)}(hcxl_device_reg_maph]hcxl_device_reg_map}(hjUhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjRubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjWmodnameN classnameNjj)}j]jc.cxl_probe_device_regsasbuh1hhj3ubjZ)}(h h]h }(hjshhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj3ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubjq)}(hmaph]hmap}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjiubeh}(h]h ]h"]h$]h&]hhuh1jhj0hhhjBhKpubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj,hhhjBhKpubah}(h]j'ah ](jjeh"]h$]h&]jj)jhuh1j;hjBhKphj)hhubj)}(hhh]jq)}(h!Detect CXL Device register blocksh]h!Detect CXL Device register blocks}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKphjhhubah}(h]h ]h"]h$]h&]uh1jhj)hhhjBhKpubeh}(h]h ](jfunctioneh"]h$]h&]jjjjЖjjЖjjjuh1j6hhhjp'hNhNubj)}(hXS**Parameters** ``struct device *dev`` Host device of the **base** mapping ``void __iomem *base`` Mapping of CXL 2.0 8.2.8 CXL Device Register Interface ``struct cxl_device_reg_map *map`` Map object describing the register block information found **Description** Probe for device register information and return it in map object.h](jq)}(h**Parameters**h]j)}(hjږh]h Parameters}(hjܖhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjؖubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKthjԖubj)}(hhh](j)}(h;``struct device *dev`` Host device of the **base** mapping h](j)}(h``struct device *dev``h]j)}(hjh]hstruct device *dev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKqhjubj)}(hhh]jq)}(h#Host device of the **base** mappingh](hHost device of the }(hjhhhNhNubj)}(h**base**h]hbase}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh mapping}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphjhKqhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKqhjubj)}(hN``void __iomem *base`` Mapping of CXL 2.0 8.2.8 CXL Device Register Interface h](j)}(h``void __iomem *base``h]j)}(hjDh]hvoid __iomem *base}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKrhj>ubj)}(hhh]jq)}(h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interfaceh]h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interface}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjYhKrhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhKrhjubj)}(h^``struct cxl_device_reg_map *map`` Map object describing the register block information found h](j)}(h"``struct cxl_device_reg_map *map``h]j)}(hj}h]hstruct cxl_device_reg_map *map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKshjwubj)}(hhh]jq)}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKshjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhKshjubeh}(h]h ]h"]h$]h&]uh1jhjԖubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKuhjԖubjq)}(hBProbe for device register information and return it in map object.h]hBProbe for device register information and return it in map object.}(hjΗhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKthjԖubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2'cxl_find_regblock_instance (C function)c.cxl_find_regblock_instancehNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hint cxl_find_regblock_instance (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h]jB)}(hint cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\ubjZ)}(h h]h }(hj hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhj hM\ubjk)}(hcxl_find_regblock_instanceh]jq)}(hcxl_find_regblock_instanceh]hcxl_find_regblock_instance}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhj hM\ubj)}(hc(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](j)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubjZ)}(h h]h }(hjGhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj6ubh)}(hhh]jq)}(hpci_devh]hpci_dev}(hjXhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjUubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjZmodnameN classnameNjj)}j]j)}jj sbc.cxl_find_regblock_instanceasbuh1hhj6ubjZ)}(h h]h }(hjxhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj6ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubjq)}(hpdevh]hpdev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj6ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(henum cxl_regloc_type typeh](j)}(henumh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_regloc_typeh]hcxl_regloc_type}(hj˘hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjȘubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj͘modnameN classnameNjj)}j]jtc.cxl_find_regblock_instanceasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(htypeh]htype}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hstruct cxl_register_map *maph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj ubh)}(hhh]jq)}(hcxl_register_maph]hcxl_register_map}(hj.hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0modnameN classnameNjj)}j]jtc.cxl_find_regblock_instanceasbuh1hhj ubjZ)}(h h]h }(hjLhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj ubj)}(hjh]h*}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubjq)}(hmaph]hmap}(hjghhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubj)}(hunsigned int indexh](jH)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj|ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj|ubjH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj|ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj|ubjq)}(hindexh]hindex}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj|ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj2ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj hM\ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhj hM\ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hj hM\hjhhubj)}(hhh]jq)}(h'Locate a register block by type / indexh]h'Locate a register block by type / index}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\hjߙhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hM\ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id ``struct cxl_register_map *map`` Enumeration output, clobbered on error ``unsigned int index`` Index into which particular instance of a regblock wanted in the order found in register locator DVSEC. **Return** 0 if register block enumerated, negative error code otherwise **Description** A CXL DVSEC may point to one or more register blocks, search for them by **type** and **index**.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hjubj)}(hhh](j)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](j)}(h``struct pci_dev *pdev``h]j)}(hj#h]hstruct pci_dev *pdev}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM]hjubj)}(hhh]jq)}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj8hM]hj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj8hM]hjubj)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](j)}(h``enum cxl_regloc_type type``h]j)}(hj\h]henum cxl_regloc_type type}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM^hjVubj)}(hhh]jq)}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjqhM^hjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhM^hjubj)}(hH``struct cxl_register_map *map`` Enumeration output, clobbered on error h](j)}(h ``struct cxl_register_map *map``h]j)}(hjh]hstruct cxl_register_map *map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM_hjubj)}(hhh]jq)}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM_hjubj)}(h``unsigned int index`` Index into which particular instance of a regblock wanted in the order found in register locator DVSEC. h](j)}(h``unsigned int index``h]j)}(hjΚh]hunsigned int index}(hjКhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj̚ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMahjȚubj)}(hhh]jq)}(hgIndex into which particular instance of a regblock wanted in the order found in register locator DVSEC.h]hgIndex into which particular instance of a regblock wanted in the order found in register locator DVSEC.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hjubah}(h]h ]h"]h$]h&]uh1jhjȚubeh}(h]h ]h"]h$]h&]uh1jhjhMahjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Return**h]j)}(hj h]hReturn}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjubjq)}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjubjq)}(h**Description**h]j)}(hj1h]h Description}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMehjubjq)}(h`A CXL DVSEC may point to one or more register blocks, search for them by **type** and **index**.h](hIA CXL DVSEC may point to one or more register blocks, search for them by }(hjGhhhNhNubj)}(h**type**h]htype}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubh and }(hjGhhhNhNubj)}(h **index**h]hindex}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubh.}(hjGhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMdhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_find_regblock (C function)c.cxl_find_regblockhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(heint cxl_find_regblock (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h]jB)}(hdint cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMpubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMpubjk)}(hcxl_find_regblockh]jq)}(hcxl_find_regblockh]hcxl_find_regblock}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMpubj)}(hO(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](j)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hjכhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӛubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjӛubh)}(hhh]jq)}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_find_regblockasbuh1hhjӛubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjӛubj)}(hjh]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӛubjq)}(hpdevh]hpdev}(hj0hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjӛubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjϛubj)}(henum cxl_regloc_type typeh](j)}(hjh]henum}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubjZ)}(h h]h }(hjVhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjEubh)}(hhh]jq)}(hcxl_regloc_typeh]hcxl_regloc_type}(hjghhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjdubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjimodnameN classnameNjj)}j]jc.cxl_find_regblockasbuh1hhjEubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjEubjq)}(htypeh]htype}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjEubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjϛubj)}(hstruct cxl_register_map *maph](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_register_maph]hcxl_register_map}(hjʜhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjǜubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj̜modnameN classnameNjj)}j]jc.cxl_find_regblockasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmaph]hmap}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjϛubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMpubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMpubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMphjhhubj)}(hhh]jq)}(hLocate register blocks by typeh]hLocate register blocks by type}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMphj*hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMpubeh}(h]h ](jfunctioneh"]h$]h&]jjjjEjjEjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id ``struct cxl_register_map *map`` Enumeration output, clobbered on error **Return** 0 if register block enumerated, negative error code otherwise **Description** A CXL DVSEC may point to one or more register blocks, search for them by **type**.h](jq)}(h**Parameters**h]j)}(hjOh]h Parameters}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMthjIubj)}(hhh](j)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](j)}(h``struct pci_dev *pdev``h]j)}(hjnh]hstruct pci_dev *pdev}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMqhjhubj)}(hhh]jq)}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMqhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjhMqhjeubj)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](j)}(h``enum cxl_regloc_type type``h]j)}(hjh]henum cxl_regloc_type type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMrhjubj)}(hhh]jq)}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMrhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMrhjeubj)}(hH``struct cxl_register_map *map`` Enumeration output, clobbered on error h](j)}(h ``struct cxl_register_map *map``h]j)}(hjh]hstruct cxl_register_map *map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjޝubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMshjڝubj)}(hhh]jq)}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMshjubah}(h]h ]h"]h$]h&]uh1jhjڝubeh}(h]h ]h"]h$]h&]uh1jhjhMshjeubeh}(h]h ]h"]h$]h&]uh1jhjIubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhjIubjq)}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhjIubjq)}(h**Description**h]j)}(hjBh]h Description}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMwhjIubjq)}(hRA CXL DVSEC may point to one or more register blocks, search for them by **type**.h](hIA CXL DVSEC may point to one or more register blocks, search for them by }(hjXhhhNhNubj)}(h**type**h]htype}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMvhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_count_regblock (C function)c.cxl_count_regblockhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hHint cxl_count_regblock (struct pci_dev *pdev, enum cxl_regloc_type type)h]jB)}(hGint cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMubjk)}(hcxl_count_regblockh]jq)}(hcxl_count_regblockh]hcxl_count_regblock}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMubj)}(h1(struct pci_dev *pdev, enum cxl_regloc_type type)h](j)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj֞hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҞubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjҞubh)}(hhh]jq)}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_count_regblockasbuh1hhjҞubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjҞubj)}(hjh]h*}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҞubjq)}(hpdevh]hpdev}(hj/hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjҞubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjΞubj)}(henum cxl_regloc_type typeh](j)}(hjh]henum}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubjZ)}(h h]h }(hjUhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjDubh)}(hhh]jq)}(hcxl_regloc_typeh]hcxl_regloc_type}(hjfhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjcubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhmodnameN classnameNjj)}j]jc.cxl_count_regblockasbuh1hhjDubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjDubjq)}(htypeh]htype}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjDubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjΞubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMhjhhubj)}(hhh]jq)}(h)Count instances of a given regblock type.h]h)Count instances of a given regblock type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjԟjjԟjjjuh1j6hhhjp'hNhNubj)}(hX***Parameters** ``struct pci_dev *pdev`` The CXL PCI device to enumerate. ``enum cxl_regloc_type type`` Register Block Indicator id **Description** Some regblocks may be repeated. Count how many instances. **Return** non-negative count of matching regblocks, negative error code otherwise.h](jq)}(h**Parameters**h]j)}(hjޟh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܟubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj؟ubj)}(hhh](j)}(h:``struct pci_dev *pdev`` The CXL PCI device to enumerate. h](j)}(h``struct pci_dev *pdev``h]j)}(hjh]hstruct pci_dev *pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjubj)}(hhh]jq)}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h:``enum cxl_regloc_type type`` Register Block Indicator id h](j)}(h``enum cxl_regloc_type type``h]j)}(hj6h]henum cxl_regloc_type type}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj0ubj)}(hhh]jq)}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjKhMhjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMhjubeh}(h]h ]h"]h$]h&]uh1jhj؟ubjq)}(h**Description**h]j)}(hjqh]h Description}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj؟ubjq)}(h9Some regblocks may be repeated. Count how many instances.h]h9Some regblocks may be repeated. Count how many instances.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj؟ubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj؟ubjq)}(hHnon-negative count of matching regblocks, negative error code otherwise.h]hHnon-negative count of matching regblocks, negative error code otherwise.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj؟ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubjq)}(hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.h]hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.}(hjĠhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:472: ./drivers/cxl/core/mbox.chKhjp'hhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2"cxl_internal_send_cmd (C function)c.cxl_internal_send_cmdhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hWint cxl_internal_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]jB)}(hVint cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhKubjk)}(hcxl_internal_send_cmdh]jq)}(hcxl_internal_send_cmdh]hcxl_internal_send_cmd}(hj hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhKubj)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](j)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubjZ)}(h h]h }(hj6hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj%ubh)}(hhh]jq)}(h cxl_mailboxh]h cxl_mailbox}(hjGhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjDubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]j)}jjsbc.cxl_internal_send_cmdasbuh1hhj%ubjZ)}(h h]h }(hjghhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj%ubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubjq)}(hcxl_mboxh]hcxl_mbox}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubj)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jcc.cxl_internal_send_cmdasbuh1hhjubjZ)}(h h]h }(hjסhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmbox_cmdh]hmbox_cmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj!ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhKubah}(h]jߠah ](jjeh"]h$]h&]jj)jhuh1j;hjhKhjhhubj)}(hhh]jq)}(h3Kernel internal interface to send a mailbox commandh]h3Kernel internal interface to send a mailbox command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jfunctioneh"]h$]h&]jjjj4jj4jjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``struct cxl_mbox_cmd *mbox_cmd`` initialized command to execute **Context** Any context. **Return** * %>=0 - Number of bytes returned in **out**. * ``-E2BIG`` - Payload is too large for hardware. * ``-EBUSY`` - Couldn't acquire exclusive mailbox access. * ``-EFAULT`` - Hardware error occurred. * ``-ENXIO`` - Command completed, but device reported an error. * ``-EIO`` - Unexpected output size. **Description** Mailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.h](jq)}(h**Parameters**h]j)}(hj>h]h Parameters}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubj)}(hhh](j)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](j)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hj]h]hstruct cxl_mailbox *cxl_mbox}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjWubj)}(hhh]jq)}(hCXL mailbox contexth]hCXL mailbox context}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjrhKhjsubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jhjrhKhjTubj)}(hA``struct cxl_mbox_cmd *mbox_cmd`` initialized command to execute h](j)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hjh]hstruct cxl_mbox_cmd *mbox_cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubj)}(hhh]jq)}(hinitialized command to executeh]hinitialized command to execute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjTubeh}(h]h ]h"]h$]h&]uh1jhj8ubjq)}(h **Context**h]j)}(hjѢh]hContext}(hjӢhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϢubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubjq)}(h Any context.h]h Any context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubj)}(hhh](j)}(h0%>=0 - Number of bytes returned in **out**.h]jq)}(hjh](h(%>=0 - Number of bytes returned in }(hjhhhNhNubj)}(h**out**h]hout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1``-E2BIG`` - Payload is too large for hardware.h]jq)}(hj=h](j)}(h ``-E2BIG``h]h-E2BIG}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh' - Payload is too large for hardware.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj;ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h9``-EBUSY`` - Couldn't acquire exclusive mailbox access.h]jq)}(hjch](j)}(h ``-EBUSY``h]h-EBUSY}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh1 - Couldn’t acquire exclusive mailbox access.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjaubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'``-EFAULT`` - Hardware error occurred.h]jq)}(hjh](j)}(h ``-EFAULT``h]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Hardware error occurred.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h?``-ENXIO`` - Command completed, but device reported an error.h]jq)}(hjh](j)}(h ``-ENXIO``h]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh5 - Command completed, but device reported an error.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'``-EIO`` - Unexpected output size. h]jq)}(h&``-EIO`` - Unexpected output size.h](j)}(h``-EIO``h]h-EIO}(hjۣhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjףubh - Unexpected output size.}(hjףhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjӣubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj4hKhj8ubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubjq)}(hMailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.h]hMailbox commands may execute successfully yet the device itself reported an error. While this distinction can be useful for commands from userspace, the kernel will only be able to use results when both are successful.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2*cxl_payload_from_user_allowed (C function)c.cxl_payload_from_user_allowedhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hQbool cxl_payload_from_user_allowed (u16 opcode, void *payload_in, size_t in_size)h]jB)}(hPbool cxl_payload_from_user_allowed(u16 opcode, void *payload_in, size_t in_size)h](jH)}(hjHZh]hbool}(hjGhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjChhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7ubjZ)}(h h]h }(hjUhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjChhhjThM7ubjk)}(hcxl_payload_from_user_allowedh]jq)}(hcxl_payload_from_user_allowedh]hcxl_payload_from_user_allowed}(hjghhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjcubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjChhhjThM7ubj)}(h.(u16 opcode, void *payload_in, size_t in_size)h](j)}(h u16 opcodeh](h)}(hhh]jq)}(hu16h]hu16}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjisbc.cxl_payload_from_user_allowedasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(hopcodeh]hopcode}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubj)}(hvoid *payload_inh](jH)}(hvoidh]hvoid}(hjͤhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjɤubjZ)}(h h]h }(hjۤhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjɤubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɤubjq)}(h payload_inh]h payload_in}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjɤubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubj)}(hsize_t in_sizeh](h)}(hhh]jq)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_payload_from_user_allowedasbuh1hhj ubjZ)}(h h]h }(hj0hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj ubjq)}(hin_sizeh]hin_size}(hj>hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj{ubeh}(h]h ]h"]h$]h&]hhuh1jhjChhhjThM7ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj?hhhjThM7ubah}(h]j:ah ](jjeh"]h$]h&]jj)jhuh1j;hjThM7hj<hhubj)}(hhh]jq)}(hCheck contents of in_payload.h]hCheck contents of in_payload.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7hjehhubah}(h]h ]h"]h$]h&]uh1jhj<hhhjThM7ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``u16 opcode`` The mailbox command opcode. ``void *payload_in`` Pointer to the input payload passed in from user space. ``size_t in_size`` Size of **payload_in** in bytes. **Return** * true - payload_in passes check for **opcode**. * false - payload_in contains invalid or unsupported values. **Description** The driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate. The specific checks are determined by the opcode.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjubj)}(hhh](j)}(h+``u16 opcode`` The mailbox command opcode. h](j)}(h``u16 opcode``h]j)}(hjh]h u16 opcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM8hjubj)}(hhh]jq)}(hThe mailbox command opcode.h]hThe mailbox command opcode.}(hj¥hhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM8hjubj)}(hM``void *payload_in`` Pointer to the input payload passed in from user space. h](j)}(h``void *payload_in``h]j)}(hjh]hvoid *payload_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM9hjܥubj)}(hhh]jq)}(h7Pointer to the input payload passed in from user space.h]h7Pointer to the input payload passed in from user space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM9hjubah}(h]h ]h"]h$]h&]uh1jhjܥubeh}(h]h ]h"]h$]h&]uh1jhjhM9hjubj)}(h4``size_t in_size`` Size of **payload_in** in bytes. h](j)}(h``size_t in_size``h]j)}(hjh]hsize_t in_size}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM:hjubj)}(hhh]jq)}(h Size of **payload_in** in bytes.h](hSize of }(hj4hhhNhNubj)}(h**payload_in**h]h payload_in}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh in bytes.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj0hM:hj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj0hM:hjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Return**h]j)}(hjhh]hReturn}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjubj)}(hhh](j)}(h3true - payload_in passes check for **opcode**.h]jq)}(hjh](h(true - payload_in passes check for }(hjhhhNhNubj)}(h **opcode**h]hopcode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(h?false - payload_in contains invalid or unsupported values. h]jq)}(h>false - payload_in contains invalid or unsupported values.h]h>false - payload_in contains invalid or unsupported values.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM=hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]jjuh1jhjhM<hjubjq)}(h**Description**h]j)}(hj̦h]h Description}(hjΦhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjʦubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjubjq)}(hXpThe driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate.h]hXpThe driver may inspect payload contents before sending a mailbox command from user space to the device. The intent is to reject commands with input payloads that are known to be unsafe. This check is not intended to replace the users careful selection of mailbox command parameters and makes no guarantee that the user command will succeed, nor that it is appropriate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjubjq)}(h1The specific checks are determined by the opcode.h]h1The specific checks are determined by the opcode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMFhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2'cxl_validate_cmd_from_user (C function)c.cxl_validate_cmd_from_userhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hint cxl_validate_cmd_from_user (struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h]jB)}(hint cxl_validate_cmd_from_user(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](jH)}(hinth]hint}(hj hhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjZ)}(h h]h }(hj/hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhj.hMubjk)}(hcxl_validate_cmd_from_userh]jq)}(hcxl_validate_cmd_from_userh]hcxl_validate_cmd_from_user}(hjAhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj=ubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhj.hMubj)}(hf(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](j)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubjZ)}(h h]h }(hjjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjYubh)}(hhh]jq)}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj{hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjxubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}modnameN classnameNjj)}j]j)}jjCsbc.cxl_validate_cmd_from_userasbuh1hhjYubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjYubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubjq)}(hmbox_cmdh]hmbox_cmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjYubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubj)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hjϧhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˧ubjZ)}(h h]h }(hjܧhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj˧ubh)}(hhh]jq)}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_validate_cmd_from_userasbuh1hhj˧ubjZ)}(h h]h }(hj hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj˧ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˧ubjq)}(hcxl_mboxh]hcxl_mbox}(hj&hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj˧ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubj)}(h'const struct cxl_send_command *send_cmdh](j)}(hjNh]hconst}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubjZ)}(h h]h }(hjLhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj;ubj)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubjZ)}(h h]h }(hjghhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj;ubh)}(hhh]jq)}(hcxl_send_commandh]hcxl_send_command}(hjxhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjzmodnameN classnameNjj)}j]jc.cxl_validate_cmd_from_userasbuh1hhj;ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj;ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubjq)}(hsend_cmdh]hsend_cmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj;ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj.hMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhj.hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hj.hMhjhhubj)}(hhh]jq)}(h&Check fields for CXL_MEM_SEND_COMMAND.h]h&Check fields for CXL_MEM_SEND_COMMAND.}(hjۨhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjبhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj.hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_mbox_cmd *mbox_cmd`` Sanitized and populated :c:type:`struct cxl_mbox_cmd `. ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``const struct cxl_send_command *send_cmd`` :c:type:`struct cxl_send_command ` copied in from userspace. **Return** * ``0`` - **out_cmd** is ready to send. * ``-ENOTTY`` - Invalid command specified. * ``-EINVAL`` - Reserved fields or invalid values were used. * ``-ENOMEM`` - Input or output buffer wasn't sized properly. * ``-EPERM`` - Attempted to use a protected command. * ``-EBUSY`` - Kernel has claimed exclusive access to this opcode **Description** The result of this command is a fully validated command in **mbox_cmd** that is safe to send to the hardware.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh](j)}(hh``struct cxl_mbox_cmd *mbox_cmd`` Sanitized and populated :c:type:`struct cxl_mbox_cmd `. h](j)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hjh]hstruct cxl_mbox_cmd *mbox_cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh]jq)}(hESanitized and populated :c:type:`struct cxl_mbox_cmd `.h](hSanitized and populated }(hj5hhhNhNubh)}(h,:c:type:`struct cxl_mbox_cmd `h]j)}(hj?h]hstruct cxl_mbox_cmd}(hjAhhhNhNubah}(h]h ](xrefjc-typeeh"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]refdoc"driver-api/cxl/theory-of-operation refdomainjreftypetype refexplicitrefwarnjj)}j]sb reftarget cxl_mbox_cmduh1hhj1hMhj5ubh.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj1hMhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hMhjubj)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](j)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hj~h]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjxubj)}(hhh]jq)}(hCXL mailbox contexth]hCXL mailbox context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h{``const struct cxl_send_command *send_cmd`` :c:type:`struct cxl_send_command ` copied in from userspace. h](j)}(h+``const struct cxl_send_command *send_cmd``h]j)}(hjh]h'const struct cxl_send_command *send_cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh]jq)}(hN:c:type:`struct cxl_send_command ` copied in from userspace.h](h)}(h4:c:type:`struct cxl_send_command `h]j)}(hj֩h]hstruct cxl_send_command}(hjةhhhNhNubah}(h]h ](jKjc-typeeh"]h$]h&]uh1jhjԩubah}(h]h ]h"]h$]h&]refdocjW refdomainjreftypetype refexplicitrefwarnjj]j`cxl_send_commanduh1hhj̩hMhjЩubh copied in from userspace.}(hjЩhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphj̩hMhjͩubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj̩hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh](j)}(h,``0`` - **out_cmd** is ready to send.h]jq)}(hj,h](j)}(h``0``h]h0}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh - }(hj.hhhNhNubj)}(h **out_cmd**h]hout_cmd}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh is ready to send.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj*ubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(h)``-ENOTTY`` - Invalid command specified.h]jq)}(hjdh](j)}(h ``-ENOTTY``h]h-ENOTTY}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh - Invalid command specified.}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjbubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(h;``-EINVAL`` - Reserved fields or invalid values were used.h]jq)}(hjh](j)}(h ``-EINVAL``h]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh0 - Reserved fields or invalid values were used.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(h<``-ENOMEM`` - Input or output buffer wasn't sized properly.h]jq)}(hjh](j)}(h ``-ENOMEM``h]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh3 - Input or output buffer wasn’t sized properly.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(h4``-EPERM`` - Attempted to use a protected command.h]jq)}(hj֪h](j)}(h ``-EPERM``h]h-EPERM}(hj۪hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjتubh* - Attempted to use a protected command.}(hjتhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjԪubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(hB``-EBUSY`` - Kernel has claimed exclusive access to this opcode h]jq)}(hA``-EBUSY`` - Kernel has claimed exclusive access to this opcodeh](j)}(h ``-EBUSY``h]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh7 - Kernel has claimed exclusive access to this opcode}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]jjuh1jhj[hMhjubjq)}(h**Description**h]j)}(hj)h]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubjq)}(hmThe result of this command is a fully validated command in **mbox_cmd** that is safe to send to the hardware.h](h;The result of this command is a fully validated command in }(hj?hhhNhNubj)}(h **mbox_cmd**h]hmbox_cmd}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh& that is safe to send to the hardware.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2)handle_mailbox_cmd_from_user (C function)c.handle_mailbox_cmd_from_userhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hint handle_mailbox_cmd_from_user (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h]jB)}(hint handle_mailbox_cmd_from_user(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj|hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj|hhhjhM>ubjk)}(hhandle_mailbox_cmd_from_userh]jq)}(hhandle_mailbox_cmd_from_userh]hhandle_mailbox_cmd_from_user}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj|hhhjhM>ubj)}(hj(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](j)}(hstruct cxl_mailbox *cxl_mboxh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjʫhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(h cxl_mailboxh]h cxl_mailbox}(hj۫hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjثubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjݫmodnameN classnameNjj)}j]j)}jjsbc.handle_mailbox_cmd_from_userasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxl_mboxh]hcxl_mbox}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubjZ)}(h h]h }(hj<hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj+ubh)}(hhh]jq)}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hjMhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jc.handle_mailbox_cmd_from_userasbuh1hhj+ubjZ)}(h h]h }(hjkhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj+ubj)}(hjh]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubjq)}(hmbox_cmdh]hmbox_cmd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu64 out_payloadh](h)}(hhh]jq)}(hu64h]hu64}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.handle_mailbox_cmd_from_userasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(h out_payloadh]h out_payload}(hjάhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h s32 *size_outh](h)}(hhh]jq)}(hs32h]hs32}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.handle_mailbox_cmd_from_userasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hsize_outh]hsize_out}(hj#hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h u32 *retvalh](h)}(hhh]jq)}(hu32h]hu32}(hj?hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj<ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjAmodnameN classnameNjj)}j]jc.handle_mailbox_cmd_from_userasbuh1hhj8ubjZ)}(h h]h }(hj]hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj8ubj)}(hjh]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubjq)}(hretvalh]hretval}(hjxhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj|hhhjhM>ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjxhhhjhM>ubah}(h]jsah ](jjeh"]h$]h&]jj)jhuh1j;hjhM>hjuhhubj)}(hhh]jq)}(h)Dispatch a mailbox command for userspace.h]h)Dispatch a mailbox command for userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hjhhubah}(h]h ]h"]h$]h&]uh1jhjuhhhjhM>ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` The mailbox context for the operation. ``struct cxl_mbox_cmd *mbox_cmd`` The validated mailbox command. ``u64 out_payload`` Pointer to userspace's output payload. ``s32 *size_out`` (Input) Max payload size to copy out. (Output) Payload size hardware generated. ``u32 *retval`` Hardware generated return code from the operation. **Return** * ``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful. * ``-ENOMEM`` - Couldn't allocate a bounce buffer. * ``-EFAULT`` - Something happened with copy_to/from_user. * ``-EINTR`` - Mailbox acquisition interrupted. * ``-EXXX`` - Transaction level failures. **Description** Dispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace. See cxl_send_cmd().h](jq)}(h**Parameters**h]j)}(hjĭh]h Parameters}(hjƭhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj­ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubj)}(hhh](j)}(hH``struct cxl_mailbox *cxl_mbox`` The mailbox context for the operation. h](j)}(h ``struct cxl_mailbox *cxl_mbox``h]j)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hjݭubj)}(hhh]jq)}(h&The mailbox context for the operation.h]h&The mailbox context for the operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM?hjubah}(h]h ]h"]h$]h&]uh1jhjݭubeh}(h]h ]h"]h$]h&]uh1jhjhM?hjڭubj)}(hA``struct cxl_mbox_cmd *mbox_cmd`` The validated mailbox command. h](j)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hjh]hstruct cxl_mbox_cmd *mbox_cmd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hjubj)}(hhh]jq)}(hThe validated mailbox command.h]hThe validated mailbox command.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj1hM@hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hM@hjڭubj)}(h;``u64 out_payload`` Pointer to userspace's output payload. h](j)}(h``u64 out_payload``h]j)}(hjUh]hu64 out_payload}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMAhjOubj)}(hhh]jq)}(h&Pointer to userspace's output payload.h]h(Pointer to userspace’s output payload.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjjhMAhjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhMAhjڭubj)}(hb``s32 *size_out`` (Input) Max payload size to copy out. (Output) Payload size hardware generated. h](j)}(h``s32 *size_out``h]j)}(hjh]h s32 *size_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMChjubj)}(hhh]jq)}(hO(Input) Max payload size to copy out. (Output) Payload size hardware generated.h]hO(Input) Max payload size to copy out. (Output) Payload size hardware generated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMChjڭubj)}(hC``u32 *retval`` Hardware generated return code from the operation. h](j)}(h``u32 *retval``h]j)}(hjȮh]h u32 *retval}(hjʮhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjƮubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMDhj®ubj)}(hhh]jq)}(h2Hardware generated return code from the operation.h]h2Hardware generated return code from the operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjݮhMDhjޮubah}(h]h ]h"]h$]h&]uh1jhj®ubeh}(h]h ]h"]h$]h&]uh1jhjݮhMDhjڭubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMFhjubj)}(hhh](j)}(h``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful.h]j)}(hhh]j)}(h``0`` - Mailbox transaction succeeded. This implies the mailbox protocol completed successfully not that the operation itself was successful.h](j)}(hF``0`` - Mailbox transaction succeeded. This implies the mailboxh](j)}(h``0``h]h0}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubhA - Mailbox transaction succeeded. This implies the mailbox}(hj'hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhj#ubj)}(hhh]jq)}(hMprotocol completed successfully not that the operation itself was successful.h]hMprotocol completed successfully not that the operation itself was successful.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjChMGhjDubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhjChMGhj ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h1``-ENOMEM`` - Couldn't allocate a bounce buffer.h]jq)}(hjoh](j)}(h ``-ENOMEM``h]h-ENOMEM}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubh( - Couldn’t allocate a bounce buffer.}(hjqhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMIhjmubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h9``-EFAULT`` - Something happened with copy_to/from_user.h]jq)}(hjh](j)}(h ``-EFAULT``h]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. - Something happened with copy_to/from_user.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMJhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h/``-EINTR`` - Mailbox acquisition interrupted.h]jq)}(hjh](j)}(h ``-EINTR``h]h-EINTR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh% - Mailbox acquisition interrupted.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h+``-EXXX`` - Transaction level failures. h]jq)}(h*``-EXXX`` - Transaction level failures.h](j)}(h ``-EXXX``h]h-EXXX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh! - Transaction level failures.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMLhj߯ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMFhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMNhjubjq)}(hiDispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace.h]hiDispatches a mailbox command on behalf of a userspace request. The output payload is copied to userspace.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMNhjubjq)}(hSee cxl_send_cmd().h]hSee cxl_send_cmd().}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMQhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_walk_cel (C function)c.cxl_walk_celhNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hFvoid cxl_walk_cel (struct cxl_memdev_state *mds, size_t size, u8 *cel)h]jB)}(hEvoid cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](jH)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhj_hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjZ)}(h h]h }(hjrhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj_hhhjqhMubjk)}(h cxl_walk_celh]jq)}(h cxl_walk_celh]h cxl_walk_cel}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj_hhhjqhMubj)}(h4(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_walk_celasbuh1hhjubjZ)}(h h]h }(hjްhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hmdsh]hmds}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h size_t sizeh](h)}(hhh]jq)}(hsize_th]hsize_t}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jڰc.cxl_walk_celasbuh1hhjubjZ)}(h h]h }(hj3hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(hsizeh]hsize}(hjAhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu8 *celh](h)}(hhh]jq)}(hu8h]hu8}(hj]hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjZubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj_modnameN classnameNjj)}j]jڰc.cxl_walk_celasbuh1hhjVubjZ)}(h h]h }(hj{hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjVubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubjq)}(hcelh]hcel}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjVubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj_hhhjqhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj[hhhjqhMubah}(h]jVah ](jjeh"]h$]h&]jj)jhuh1j;hjqhMhjXhhubj)}(hhh]jq)}(h%Walk through the Command Effects Log.h]h%Walk through the Command Effects Log.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjXhhhjqhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjرjjرjjjuh1j6hhhjp'hNhNubj)}(hXH**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation ``size_t size`` Length of the Command Effects Log. ``u8 *cel`` CEL **Description** Iterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.h](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjܱubj)}(hhh](j)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hjh]hstruct cxl_memdev_state *mds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjubj)}(hhh]jq)}(h!The driver data for the operationh]h!The driver data for the operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h3``size_t size`` Length of the Command Effects Log. h](j)}(h``size_t size``h]j)}(hj:h]h size_t size}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj4ubj)}(hhh]jq)}(h"Length of the Command Effects Log.h]h"Length of the Command Effects Log.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jphjOhMhjPubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhjOhMhjubj)}(h``u8 *cel`` CEL h](j)}(h ``u8 *cel``h]j)}(hjsh]hu8 *cel}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjmubj)}(hhh]jq)}(hCELh]hCEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjܱubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjܱubjq)}(hIterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.h]hIterate over each entry in the CEL and determine if the driver supports the command. If so, the command is enabled for the device and can be used later.}(hjIJhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjܱubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_enumerate_cmds (C function)c.cxl_enumerate_cmdshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h5int cxl_enumerate_cmds (struct cxl_memdev_state *mds)h]jB)}(h4int cxl_enumerate_cmds(struct cxl_memdev_state *mds)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMCubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMCubjk)}(hcxl_enumerate_cmdsh]jq)}(hcxl_enumerate_cmdsh]hcxl_enumerate_cmds}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMCubj)}(h(struct cxl_memdev_state *mds)h]j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubjZ)}(h h]h }(hj=hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj,ubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjNhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjKubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjPmodnameN classnameNjj)}j]j)}jjsbc.cxl_enumerate_cmdsasbuh1hhj,ubjZ)}(h h]h }(hjnhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj,ubj)}(hjh]h*}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubjq)}(hmdsh]hmds}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj,ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj(ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMCubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMCubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMChjhhubj)}(hhh]jq)}(h Enumerate commands for a device.h]h Enumerate commands for a device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMChjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMCubeh}(h]h ](jfunctioneh"]h$]h&]jjjj˳jj˳jjjuh1j6hhhjp'hNhNubj)}(hXM**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation **Description** Returns 0 if enumerate completed successfully. CXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the **mds**.h](jq)}(h**Parameters**h]j)}(hjճh]h Parameters}(hj׳hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӳubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhjϳubj)}(hhh]j)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hjh]hstruct cxl_memdev_state *mds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMDhjubj)}(hhh]jq)}(h!The driver data for the operationh]h!The driver data for the operation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hMDhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMDhjubah}(h]h ]h"]h$]h&]uh1jhjϳubjq)}(h**Description**h]j)}(hj/h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMFhjϳubjq)}(h.Returns 0 if enumerate completed successfully.h]h.Returns 0 if enumerate completed successfully.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMEhjϳubjq)}(hCXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the **mds**.h](hCXL devices have optional support for certain commands. This function will determine the set of supported commands for the hardware and update the enabled_cmds bitmap in the }(hjThhhNhNubj)}(h**mds**h]hmds}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubh.}(hjThhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhjϳubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2&cxl_mem_get_event_records (C function)c.cxl_mem_get_event_recordshNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(hIvoid cxl_mem_get_event_records (struct cxl_memdev_state *mds, u32 status)h]jB)}(hHvoid cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status)h](jH)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM^ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhM^ubjk)}(hcxl_mem_get_event_recordsh]jq)}(hcxl_mem_get_event_recordsh]hcxl_mem_get_event_records}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhM^ubj)}(h*(struct cxl_memdev_state *mds, u32 status)h](j)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjҴhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjδubjZ)}(h h]h }(hjߴhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjδubh)}(hhh]jq)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_mem_get_event_recordsasbuh1hhjδubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjδubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjδubjq)}(hmdsh]hmds}(hj+hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjδubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjʴubj)}(h u32 statush](h)}(hhh]jq)}(hu32h]hu32}(hjGhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjDubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjImodnameN classnameNjj)}j]j c.cxl_mem_get_event_recordsasbuh1hhj@ubjZ)}(h h]h }(hjehhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj@ubjq)}(hstatush]hstatus}(hjshhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjʴubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM^ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhM^ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhM^hjhhubj)}(hhh]jq)}(h!Get Event Records from the deviceh]h!Get Event Records from the device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM^hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM^ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjp'hNhNubj)}(hX**Parameters** ``struct cxl_memdev_state *mds`` The driver data for the operation ``u32 status`` Event Status register value identifying which events are available. **Description** Retrieve all event records available on the device, report them as trace events, and clear them. See CXL rev 3.0 **8.2.9.2.2** Get Event Records See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMbhjubj)}(hhh](j)}(hC``struct cxl_memdev_state *mds`` The driver data for the operation h](j)}(h ``struct cxl_memdev_state *mds``h]j)}(hj޵h]hstruct cxl_memdev_state *mds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܵubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM_hjصubj)}(hhh]jq)}(h!The driver data for the operationh]h!The driver data for the operation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM_hjubah}(h]h ]h"]h$]h&]uh1jhjصubeh}(h]h ]h"]h$]h&]uh1jhjhM_hjյubj)}(hS``u32 status`` Event Status register value identifying which events are available. h](j)}(h``u32 status``h]j)}(hjh]h u32 status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM`hjubj)}(hhh]jq)}(hCEvent Status register value identifying which events are available.h]hCEvent Status register value identifying which events are available.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj,hM`hj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj,hM`hjյubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjRh]h Description}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMbhjubjq)}(h`Retrieve all event records available on the device, report them as trace events, and clear them.h]h`Retrieve all event records available on the device, report them as trace events, and clear them.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMahjubjq)}(haSee CXL rev 3.0 **8.2.9.2.2** Get Event Records See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](hSee CXL rev 3.0 }(hjwhhhNhNubj)}(h **8.2.9.2.2**h]h 8.2.9.2.2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh# Get Event Records See CXL rev 3.0 }(hjwhhhNhNubj)}(h **8.2.9.2.3**h]h 8.2.9.2.3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubh Clear Event Records}(hjwhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMdhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjp'hhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2'cxl_mem_get_partition_info (C function)c.cxl_mem_get_partition_infohNtauh1j%hjp'hhhNhNubj7)}(hhh](j<)}(h=int cxl_mem_get_partition_info (struct cxl_memdev_state *mds)h]jB)}(hport to add a new region reference ‘struct cxl_region_ref’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubj)}(h9``struct cxl_region *cxlr`` region to attach to **port** h](j)}(h``struct cxl_region *cxlr``h]j)}(hjh]hstruct cxl_region *cxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(hhh]jq)}(hregion to attach to **port**h](hregion to attach to }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubj)}(hi``struct cxl_endpoint_decoder *cxled`` endpoint decoder used to create or further pin a region reference h](j)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjh]h"struct cxl_endpoint_decoder *cxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(hhh]jq)}(hAendpoint decoder used to create or further pin a region referenceh]hAendpoint decoder used to create or further pin a region reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubj)}(h9``int pos`` interleave position of **cxled** in **cxlr** h](j)}(h ``int pos``h]j)}(hj'h]hint pos}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhj!ubj)}(hhh]jq)}(h,interleave position of **cxled** in **cxlr**h](hinterleave position of }(hj@hhhNhNubj)}(h **cxled**h]hcxled}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh in }(hj@hhhNhNubj)}(h**cxlr**h]hcxlr}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jphj<hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhjeubeh}(h]h ]h"]h$]h&]uh1jhjIubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjIubjq)}(hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.h]hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjIubjq)}(hThe steps are:h]hThe steps are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjIubj)}(hhh](j)}(h[validate that there are no other regions with a higher HPA already associated with **port**h]jq)}(h[validate that there are no other regions with a higher HPA already associated with **port**h](hSvalidate that there are no other regions with a higher HPA already associated with }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hestablish a region reference if one is not already present - additionally allocate a decoder instance that will host **cxlr** on **port** h](jq)}(h:establish a region reference if one is not already presenth]h:establish a region reference if one is not already present}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(hhh]j)}(hMadditionally allocate a decoder instance that will host **cxlr** on **port** h]jq)}(hLadditionally allocate a decoder instance that will host **cxlr** on **port**h](h8additionally allocate a decoder instance that will host }(hjhhhNhNubj)}(h**cxlr**h]hcxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh on }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj(hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h(pin the region reference by the endpointh]jq)}(hj=h]h(pin the region reference by the endpoint}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhj;ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h]jq)}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h](h account for how many entries in }(hjWhhhNhNubj)}(h**port**h]hport}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh@’s target list are needed to cover all of the added endpoints.}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjSubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhMhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2$cxl_calc_interleave_pos (C function)c.cxl_calc_interleave_poshNtauh1j%hjhhhNhNubj7)}(hhh](j<)}(hYint cxl_calc_interleave_pos (struct cxl_endpoint_decoder *cxled, struct range *hpa_range)h]jB)}(hXint cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled, struct range *hpa_range)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhMubjk)}(hcxl_calc_interleave_posh]jq)}(hcxl_calc_interleave_posh]hcxl_calc_interleave_pos}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhMubj)}(h=(struct cxl_endpoint_decoder *cxled, struct range *hpa_range)h](j)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_calc_interleave_posasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxledh]hcxled}(hj:hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct range *hpa_rangeh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubjZ)}(h h]h }(hj`hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjOubh)}(hhh]jq)}(hrangeh]hrange}(hjqhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjnubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjsmodnameN classnameNjj)}j]jc.cxl_calc_interleave_posasbuh1hhjOubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjOubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubjq)}(h hpa_rangeh]h hpa_range}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjOubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhMhjhhubj)}(hhh]jq)}(h*calculate an endpoint position in a regionh]h*calculate an endpoint position in a region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjhNhNubj)}(hX**Parameters** ``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region ``struct range *hpa_range`` translated HPA range of the endpoint **Description** The endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation: position = position * parent_ways + parent_pos; ...where **position** is inferred from switch and root decoder target lists. **Return** position >= 0 on success -ENXIO on failureh](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(hhh](j)}(hO``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region h](j)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjh]h"struct cxl_endpoint_decoder *cxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(hhh]jq)}(h'endpoint decoder member of given regionh]h'endpoint decoder member of given region}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hMhj ubj)}(hA``struct range *hpa_range`` translated HPA range of the endpoint h](j)}(h``struct range *hpa_range``h]j)}(hjNh]hstruct range *hpa_range}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjHubj)}(hhh]jq)}(h$translated HPA range of the endpointh]h$translated HPA range of the endpoint}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jphjchMhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjchMhj ubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubjq)}(hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:h]hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubj)}(h0position = position * parent_ways + parent_pos; h]jq)}(h/position = position * parent_ways + parent_pos;h]h/position = position * parent_ways + parent_pos;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubah}(h]h ]h"]h$]h&]uh1jhjhMhjubjq)}(hL...where **position** is inferred from switch and root decoder target lists.h](h ...where }(hjhhhNhNubj)}(h **position**h]hposition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh7 is inferred from switch and root decoder target lists.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubjq)}(h*position >= 0 on success -ENXIO on failureh]h*position >= 0 on success -ENXIO on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2 devm_cxl_add_region (C function)c.devm_cxl_add_regionhNtauh1j%hjhhhNhNubj7)}(hhh](j<)}(hstruct cxl_region * devm_cxl_add_region (struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h]jB)}(hstruct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j)}(hjh]hstruct}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMu ubjZ)}(h h]h }(hj=hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj+hhhj<hMu ubh)}(hhh]jq)}(h cxl_regionh]h cxl_region}(hjNhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjKubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjPmodnameN classnameNjj)}j]j)}jdevm_cxl_add_regionsbc.devm_cxl_add_regionasbuh1hhj+hhhj<hMu ubjZ)}(h h]h }(hjohhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj+hhhj<hMu ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+hhhj<hMu ubjk)}(hdevm_cxl_add_regionh]jq)}(hjlh]hdevm_cxl_add_region}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhj+hhhj<hMu ubj)}(hb(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j)}(hstruct cxl_root_decoder *cxlrdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_root_decoderh]hcxl_root_decoder}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jjc.devm_cxl_add_regionasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjq)}(hcxlrdh]hcxlrd}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hint idh](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjubjZ)}(h h]h }(hj'hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(hidh]hid}(hj5hhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum cxl_partition_mode modeh](j)}(hjh]henum}(hjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubjZ)}(h h]h }(hj[hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjJubh)}(hhh]jq)}(hcxl_partition_modeh]hcxl_partition_mode}(hjlhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjiubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjnmodnameN classnameNjj)}j]jjc.devm_cxl_add_regionasbuh1hhjJubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjJubjq)}(hmodeh]hmode}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjJubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum cxl_decoder_type typeh](j)}(hjh]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubh)}(hhh]jq)}(hcxl_decoder_typeh]hcxl_decoder_type}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jjc.devm_cxl_add_regionasbuh1hhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(htypeh]htype}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj+hhhj<hMu ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhj'hhhj<hMu ubah}(h]j"ah ](jjeh"]h$]h&]jj)jhuh1j;hj<hMu hj$hhubj)}(hhh]jq)}(hAdds a region to a decoderh]hAdds a region to a decoder}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMu hj"hhubah}(h]h ]h"]h$]h&]uh1jhj$hhhj<hMu ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj=jj=jjjuh1j6hhhjhNhNubj)}(hXl**Parameters** ``struct cxl_root_decoder *cxlrd`` root decoder ``int id`` memregion id to create, or memregion_free() on failure ``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region ``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) **Description** This is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**. **Return** 0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](jq)}(h**Parameters**h]j)}(hjGh]h Parameters}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMy hjAubj)}(hhh](j)}(h0``struct cxl_root_decoder *cxlrd`` root decoder h](j)}(h"``struct cxl_root_decoder *cxlrd``h]j)}(hjfh]hstruct cxl_root_decoder *cxlrd}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMv hj`ubj)}(hhh]jq)}(h root decoderh]h root decoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj{hMv hj|ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj{hMv hj]ubj)}(hB``int id`` memregion id to create, or memregion_free() on failure h](j)}(h ``int id``h]j)}(hjh]hint id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMw hjubj)}(hhh]jq)}(h6memregion id to create, or memregion_free() on failureh]h6memregion id to create, or memregion_free() on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMw hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMw hj]ubj)}(hO``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region h](j)}(h ``enum cxl_partition_mode mode``h]j)}(hjh]henum cxl_partition_mode mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMx hjubj)}(hhh]jq)}(h-mode for the endpoint decoders of this regionh]h-mode for the endpoint decoders of this region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhMx hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMx hj]ubj)}(hd``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) h](j)}(h``enum cxl_decoder_type type``h]j)}(hjh]henum cxl_decoder_type type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMy hj ubj)}(hhh]jq)}(hDselect whether this is an expander or accelerator (type-2 or type-3)h]hDselect whether this is an expander or accelerator (type-2 or type-3)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj&hMy hj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj&hMy hj]ubeh}(h]h ]h"]h$]h&]uh1jhjAubjq)}(h**Description**h]j)}(hjLh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM{ hjAubjq)}(hwThis is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**.h](hmThis is the second step of region initialization. Regions exist within an address space which is mapped by a }(hjbhhhNhNubj)}(h **cxlrd**h]hcxlrd}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubh.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMz hjAubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM} hjAubjq)}(h0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](h!0 if the region was added to the }(hjhhhNhNubj)}(h **cxlrd**h]hcxlrd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubho, else returns negative error code. The region will be named “regionZ” where Z is the unique region number.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM~ hjAubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2,cxl_validate_translation_params (C function)!c.cxl_validate_translation_paramshNtauh1j%hjhhhNhNubj7)}(hhh](j<)}(h>int cxl_validate_translation_params (u8 eiw, u16 eig, int pos)h]jB)}(h=int cxl_validate_translation_params(u8 eiw, u16 eig, int pos)h](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjhhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhM ubjk)}(hcxl_validate_translation_paramsh]jq)}(hcxl_validate_translation_paramsh]hcxl_validate_translation_params}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhM ubj)}(h(u8 eiw, u16 eig, int pos)h](j)}(hu8 eiwh](h)}(hhh]jq)}(hu8h]hu8}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb!c.cxl_validate_translation_paramsasbuh1hhjubjZ)}(h h]h }(hj<hhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(heiwh]heiw}(hjJhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hu16 eigh](h)}(hhh]jq)}(hu16h]hu16}(hjfhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjcubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhmodnameN classnameNjj)}j]j8!c.cxl_validate_translation_paramsasbuh1hhj_ubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhj_ubjq)}(heigh]heig}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hint posh](jH)}(hinth]hint}(hjhhhNhNubah}(h]h ]jTah"]h$]h&]uh1jGhjubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjubjq)}(hposh]hpos}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhM hjhhubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j6hhhjhNhNubj)}(hX**Parameters** ``u8 eiw`` encoded interleave ways ``u16 eig`` encoded interleave granularity ``int pos`` position in interleave **Description** Callers pass CXL_POS_ZERO when no position parameter needs validating. **Return** 0 on success, -EINVAL on first invalid parameterh](jq)}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh](j)}(h#``u8 eiw`` encoded interleave ways h](j)}(h ``u8 eiw``h]j)}(hj#h]hu8 eiw}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]jq)}(hencoded interleave waysh]hencoded interleave ways}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj8hM hj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj8hM hjubj)}(h+``u16 eig`` encoded interleave granularity h](j)}(h ``u16 eig``h]j)}(hj\h]hu16 eig}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjVubj)}(hhh]jq)}(hencoded interleave granularityh]hencoded interleave granularity}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjqhM hjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhM hjubj)}(h#``int pos`` position in interleave h](j)}(h ``int pos``h]j)}(hjh]hint pos}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubj)}(hhh]jq)}(hposition in interleaveh]hposition in interleave}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubjq)}(hFCallers pass CXL_POS_ZERO when no position parameter needs validating.h]hFCallers pass CXL_POS_ZERO when no position parameter needs validating.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubjq)}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubjq)}(h00 on success, -EINVAL on first invalid parameterh]h00 on success, -EINVAL on first invalid parameter}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjhhhNhNubeh}(h] cxl-regionsah ]h"] cxl regionsah$]h&]uh1j[hjChhhhhMubeh}(h]driver-infrastructureah ]h"]driver infrastructureah$]h&]uh1j[hj]hhhhhM;ubj\)}(hhh](ja)}(hExternal Interfacesh]hExternal Interfaces}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj3hhhhhMubj\)}(hhh](ja)}(hCXL IOCTL Interfaceh]hCXL IOCTL Interface}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjDhhhhhMubjq)}(hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.h]hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:497: ./include/uapi/linux/cxl_mem.hhK hjDhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_command_info (C struct)c.cxl_command_infohNtauh1j%hjDhhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhNubj7)}(hhh](j<)}(hcxl_command_infoh]jB)}(hstruct cxl_command_infoh](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzhhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjzhhhjhKubjk)}(hcxl_command_infoh]jq)}(hjxh]hcxl_command_info}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjzhhhjhKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjvhhhjhKubah}(h]jpah ](jjeh"]h$]h&]jj)jhuh1j;hjhKhjshhubj)}(hhh]jq)}(h*Command information returned from a query.h]h*Command information returned from a query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKfhjhhubah}(h]h ]h"]h$]h&]uh1jhjshhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjDhjrhNubj)}(hX**Definition**:: struct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; }; **Members** ``id`` ID number for the command. ``flags`` Flags that specify command behavior. ``size_in`` Expected input size, or ~0 if variable length. ``size_out`` Expected output size, or ~0 if variable length.h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKjhjubj)}(hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };h]hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKlhjubjq)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKvhjubj)}(hhh](j)}(h"``id`` ID number for the command. h](j)}(h``id``h]j)}(hj-h]hid}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhhj'ubj)}(hhh]jq)}(hID number for the command.h]hID number for the command.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjBhKhhjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhKhhj$ubj)}(h/``flags`` Flags that specify command behavior. h](j)}(h ``flags``h]j)}(hjfh]hflags}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKihj`ubj)}(hhh]jq)}(h$Flags that specify command behavior.h]h$Flags that specify command behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj{hKihj|ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj{hKihj$ubj)}(h;``size_in`` Expected input size, or ~0 if variable length. h](j)}(h ``size_in``h]j)}(hjh]hsize_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhjubj)}(hhh]jq)}(h.Expected input size, or ~0 if variable length.h]h.Expected input size, or ~0 if variable length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKwhj$ubj)}(h<``size_out`` Expected output size, or ~0 if variable length.h](j)}(h ``size_out``h]j)}(hjh]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhjubj)}(hhh]jq)}(h/Expected output size, or ~0 if variable length.h]h/Expected output size, or ~0 if variable length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKwhj$ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjDhhhjrhNubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK{hjDhhubj)}(hXCXL_MEM_COMMAND_FLAG_USER_ENABLED The given command id is supported by the driver and is supported by a related opcode on the device. CXL_MEM_COMMAND_FLAG_EXCLUSIVE Requests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space. h](jq)}(h!CXL_MEM_COMMAND_FLAG_USER_ENABLEDh]h!CXL_MEM_COMMAND_FLAG_USER_ENABLED}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKihj1ubjq)}(hcThe given command id is supported by the driver and is supported by a related opcode on the device.h]hcThe given command id is supported by the driver and is supported by a related opcode on the device.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKkhj1ubjq)}(hCXL_MEM_COMMAND_FLAG_EXCLUSIVEh]hCXL_MEM_COMMAND_FLAG_EXCLUSIVE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKnhj1ubjq)}(hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.h]hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKphj1ubeh}(h]h ]h"]h$]h&]uh1jhjChKihjDhhubjq)}(hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.h]hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKvhjDhhubj)}(h_- **id** = 10 - **flags** = CXL_MEM_COMMAND_FLAG_ENABLED - **size_in** = ~0 - **size_out** = 0 h]j)}(hhh](j)}(h **id** = 10h]jq)}(hjh](j)}(h**id**h]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 10}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK{hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h(**flags** = CXL_MEM_COMMAND_FLAG_ENABLEDh]jq)}(hjh](j)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = CXL_MEM_COMMAND_FLAG_ENABLED}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK|hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**size_in** = ~0h]jq)}(hjh](j)}(h **size_in**h]hsize_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = ~0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK}hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**size_out** = 0 h]jq)}(h**size_out** = 0h](j)}(h **size_out**h]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhK{hjubah}(h]h ]h"]h$]h&]uh1jhjhK{hjDhhubjq)}(h"See struct cxl_mem_query_commands.h]h"See struct cxl_mem_query_commands.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjDhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2!cxl_mem_query_commands (C struct)c.cxl_mem_query_commandshNtauh1j%hjDhhhjrhNubj7)}(hhh](j<)}(hcxl_mem_query_commandsh]jB)}(hstruct cxl_mem_query_commandsh](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVhhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjZ)}(h h]h }(hjhhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjVhhhjghKubjk)}(hcxl_mem_query_commandsh]jq)}(hjTh]hcxl_mem_query_commands}(hjzhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjvubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjVhhhjghKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjRhhhjghKubah}(h]jMah ](jjeh"]h$]h&]jj)jhuh1j;hjghKhjOhhubj)}(hhh]jq)}(hQuery supported commands.h]hQuery supported commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjOhhhjghKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjDhjrhNubj)}(hX5**Definition**:: struct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; }; **Members** ``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. ``rsvd`` Reserved for future use. ``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };h]hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubjq)}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh](j)}(h``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. h](j)}(h``n_commands``h]j)}(hj h]h n_commands}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(hIn/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands.h](hIn/out parameter. When }(hj"hhhNhNubj)}(h**n_commands**h]h n_commands}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubhL is > 0, the driver will return min(num_support_commands, n_commands). When }(hj"hhhNhNubj)}(h**n_commands**h]h n_commands}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubhA is 0, driver will return the number of total supported commands.}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h"``rsvd`` Reserved for future use. h](j)}(h``rsvd``h]j)}(hjgh]hrsvd}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjaubj)}(hhh]jq)}(hReserved for future use.h]hReserved for future use.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj|hKhj}ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hKhjubj)}(h``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](j)}(h ``commands``h]j)}(hjh]hcommands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(hOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](hwOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjDhhhjrhNubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjDhhubjq)}(hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren't supported by either the driver, or the hardware are not returned in the query.h]hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren’t supported by either the driver, or the hardware are not returned in the query.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjDhhubjq)}(h **Examples**h]j)}(hjh]hExamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjDhhubj)}(h- { .n_commands = 0 } // Get number of supported commands - { .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands See struct cxl_command_info. h](j)}(hhh](j)}(h7{ .n_commands = 0 } // Get number of supported commandsh]jq)}(hj:h]h7{ .n_commands = 0 } // Get number of supported commands}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj8ubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hV{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands h]jq)}(hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commandsh]hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjPubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]jjuh1jhjIhKhj1ubjq)}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj1ubeh}(h]h ]h"]h$]h&]uh1jhjIhKhjDhhubj&)}(hhh]h}(h]h ]h"]h$]h&]entries](j2cxl_send_command (C struct)c.cxl_send_commandXhNtauh1j%hjDhhhjrhNubj7)}(hhh](j<)}(hcxl_send_commandh]jB)}(hstruct cxl_send_commandh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjZ)}(h h]h }(hjhhhNhNubah}(h]h ]jfah"]h$]h&]uh1jYhjhhhjhKubjk)}(hcxl_send_commandh]jq)}(hjh]hcxl_send_command}(hjhhhNhNubah}(h]h ]j}ah"]h$]h&]uh1jphjubah}(h]h ](jjeh"]h$]h&]hhuh1jjhjhhhjhKubeh}(h]h ]h"]h$]h&]hhjuh1jAjjhjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j;hjhKhjhhubj)}(hhh]jq)}(h"Send a command to a memory device.h]h"Send a command to a memory device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j6hhhjDhjrhNubj)}(hX **Definition**:: struct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; }; **Members** ``id`` The command to send to the memory device. This must be one of the commands returned by the query command. ``flags`` Flags for the command (input). ``{unnamed_union}`` anonymous ``raw`` Special fields for raw commands ``raw.opcode`` Opcode passed to hardware when using the RAW command. ``raw.rsvd`` Must be zero. ``rsvd`` Must be zero. ``retval`` Return value from the memory device (output). ``in`` Parameters associated with input payload. ``in.size`` Size of the payload to provide to the device (input). ``in.rsvd`` Must be zero. ``in.payload`` Pointer to memory for payload input, payload is little endian. ``out`` Parameters associated with output payload. ``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. ``out.rsvd`` Must be zero. ``out.payload`` Pointer to memory for payload output, payload is little endian.h](jq)}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };h]hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubjq)}(h **Members**h]j)}(hj-h]hMembers}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh](j)}(hq``id`` The command to send to the memory device. This must be one of the commands returned by the query command. h](j)}(h``id``h]j)}(hjLh]hid}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjFubj)}(hhh]jq)}(hiThe command to send to the memory device. This must be one of the commands returned by the query command.h]hiThe command to send to the memory device. This must be one of the commands returned by the query command.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjahKhjCubj)}(h)``flags`` Flags for the command (input). h](j)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(hFlags for the command (input).h]hFlags for the command (input).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h anonymoush]h anonymous}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h(``raw`` Special fields for raw commands h](j)}(h``raw``h]j)}(hjh]hraw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(hSpecial fields for raw commandsh]hSpecial fields for raw commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphj hKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hKhjCubj)}(hE``raw.opcode`` Opcode passed to hardware when using the RAW command. h](j)}(h``raw.opcode``h]j)}(hj1h]h raw.opcode}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj+ubj)}(hhh]jq)}(h5Opcode passed to hardware when using the RAW command.h]h5Opcode passed to hardware when using the RAW command.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjFhKhjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhjFhKhjCubj)}(h``raw.rsvd`` Must be zero. h](j)}(h ``raw.rsvd``h]j)}(hjjh]hraw.rsvd}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjdubj)}(hhh]jq)}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h``rsvd`` Must be zero. h](j)}(h``rsvd``h]j)}(hjh]hrsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h9``retval`` Return value from the memory device (output). h](j)}(h ``retval``h]j)}(hjh]hretval}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h-Return value from the memory device (output).h]h-Return value from the memory device (output).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h1``in`` Parameters associated with input payload. h](j)}(h``in``h]j)}(hjh]hin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h)Parameters associated with input payload.h]h)Parameters associated with input payload.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jphj*hKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hKhjCubj)}(hB``in.size`` Size of the payload to provide to the device (input). h](j)}(h ``in.size``h]j)}(hjNh]hin.size}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjHubj)}(hhh]jq)}(h5Size of the payload to provide to the device (input).h]h5Size of the payload to provide to the device (input).}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jphjchKhjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjchKhjCubj)}(h``in.rsvd`` Must be zero. h](j)}(h ``in.rsvd``h]j)}(hjh]hin.rsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(hN``in.payload`` Pointer to memory for payload input, payload is little endian. h](j)}(h``in.payload``h]j)}(hjh]h in.payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h>Pointer to memory for payload input, payload is little endian.h]h>Pointer to memory for payload input, payload is little endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(h3``out`` Parameters associated with output payload. h](j)}(h``out``h]j)}(hjh]hout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h*Parameters associated with output payload.h]h*Parameters associated with output payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(hX``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. h](j)}(h ``out.size``h]j)}(hj2h]hout.size}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj,ubj)}(hhh]jq)}(hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.h]hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjHubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjGhKhjCubj)}(h``out.rsvd`` Must be zero. h](j)}(h ``out.rsvd``h]j)}(hjlh]hout.rsvd}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjfubj)}(hhh]jq)}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphjhKhjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubj)}(hO``out.payload`` Pointer to memory for payload output, payload is little endian.h](j)}(h``out.payload``h]j)}(hjh]h out.payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]jq)}(h?Pointer to memory for payload output, payload is little endian.h]h?Pointer to memory for payload output, payload is little endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjDhhhjrhNubjq)}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jphp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjDhhubjq)}(hX/Mechanism for userspace to send a command to the hardware for processing. The driver will do basic validation on the command sizes. In some cases even the payload may be introspected. Userspace is required to allocate large enough buffers for size_out which can be variable length in certain situations.h]hX/Mechanism for userspace to send a command to the hardware for processing. The driver will do basic validation on the command sizes. In some cases even the payload may be introspected. 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