sphinx.addnodesdocument)}( rawsource children]( translations
LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba
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hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah }(h ]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah }(h ]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from
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.h]hDerived from the Unicode character mappings available from
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h]h¥}hj8 sbah }(h ]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h/Compute Express Link Driver Theory of Operationh]h/Compute Express Link Driver Theory of Operation}(hjN hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hjI hhhhhKubh paragraph)}(hX A Compute Express Link Memory Device is a CXL component that implements the
CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
or both. It is enumerated as a PCI device for configuration and passing
messages over an MMIO mailbox. Its contribution to the System Physical
Address space is handled via HDM (Host Managed Device Memory) decoders
that optionally define a device's contribution to an interleaved address
range across multiple devices underneath a host-bridge or interleaved
across host-bridges.h]hX A Compute Express Link Memory Device is a CXL component that implements the
CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
or both. It is enumerated as a PCI device for configuration and passing
messages over an MMIO mailbox. Its contribution to the System Physical
Address space is handled via HDM (Host Managed Device Memory) decoders
that optionally define a device’s contribution to an interleaved address
range across multiple devices underneath a host-bridge or interleaved
across host-bridges.}(hj^ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjI hhubjH )}(hhh](jM )}(h The CXL Bush]h The CXL Bus}(hjo hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hjl hhhhhKubj] )}(hXS Similar to how a RAID driver takes disk objects and assembles them into a new
logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
assemble them into a CXL.mem decode topology. The need for runtime configuration
of the CXL.mem topology is also similar to RAID in that different environments
with the same hardware configuration may decide to assemble the topology in
contrasting ways. One may choose performance (RAID0) striping memory across
multiple Host Bridges and endpoints while another may opt for fault tolerance
and disable any striping in the CXL.mem topology.h]hXS Similar to how a RAID driver takes disk objects and assembles them into a new
logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
assemble them into a CXL.mem decode topology. The need for runtime configuration
of the CXL.mem topology is also similar to RAID in that different environments
with the same hardware configuration may decide to assemble the topology in
contrasting ways. One may choose performance (RAID0) striping memory across
multiple Host Bridges and endpoints while another may opt for fault tolerance
and disable any striping in the CXL.mem topology.}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjl hhubj] )}(hX Platform firmware enumerates a menu of interleave options at the "CXL root port"
(Linux term for the top of the CXL decode topology). From there, PCIe topology
dictates which endpoints can participate in which Host Bridge decode regimes.
Each PCIe Switch in the path between the root and an endpoint introduces a point
at which the interleave can be split. For example, platform firmware may say a
given range only decodes to one Host Bridge, but that Host Bridge may in turn
interleave cycles across multiple Root Ports. An intervening Switch between a
port and an endpoint may interleave cycles across multiple Downstream Switch
Ports, etc.h]hX Platform firmware enumerates a menu of interleave options at the “CXL root port”
(Linux term for the top of the CXL decode topology). From there, PCIe topology
dictates which endpoints can participate in which Host Bridge decode regimes.
Each PCIe Switch in the path between the root and an endpoint introduces a point
at which the interleave can be split. For example, platform firmware may say a
given range only decodes to one Host Bridge, but that Host Bridge may in turn
interleave cycles across multiple Root Ports. An intervening Switch between a
port and an endpoint may interleave cycles across multiple Downstream Switch
Ports, etc.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhK hjl hhubj] )}(hX- Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test'
module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
Ports. Each of those Root Ports are connected to 2-way switches with endpoints
connected to those downstream ports for a total of 8 endpoints::h]hX4 Here is a sample listing of a CXL topology defined by ‘cxl_test’. The ‘cxl_test’
module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
Ports. Each of those Root Ports are connected to 2-way switches with endpoints
connected to those downstream ports for a total of 8 endpoints:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhK&hjl hhubh
literal_block)}(hX # cxl list -BEMPu -b cxl_test
{
"bus":"root3",
"provider":"cxl_test",
"ports:root3":[
{
"port":"port5",
"host":"cxl_host_bridge.1",
"ports:port5":[
{
"port":"port8",
"host":"cxl_switch_uport.1",
"endpoints:port8":[
{
"endpoint":"endpoint9",
"host":"mem2",
"memdev":{
"memdev":"mem2",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x1",
"numa_node":1,
"host":"cxl_mem.1"
}
},
{
"endpoint":"endpoint15",
"host":"mem6",
"memdev":{
"memdev":"mem6",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x5",
"numa_node":1,
"host":"cxl_mem.5"
}
}
]
},
{
"port":"port12",
"host":"cxl_switch_uport.3",
"endpoints:port12":[
{
"endpoint":"endpoint17",
"host":"mem8",
"memdev":{
"memdev":"mem8",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x7",
"numa_node":1,
"host":"cxl_mem.7"
}
},
{
"endpoint":"endpoint13",
"host":"mem4",
"memdev":{
"memdev":"mem4",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x3",
"numa_node":1,
"host":"cxl_mem.3"
}
}
]
}
]
},
{
"port":"port4",
"host":"cxl_host_bridge.0",
"ports:port4":[
{
"port":"port6",
"host":"cxl_switch_uport.0",
"endpoints:port6":[
{
"endpoint":"endpoint7",
"host":"mem1",
"memdev":{
"memdev":"mem1",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0",
"numa_node":0,
"host":"cxl_mem.0"
}
},
{
"endpoint":"endpoint14",
"host":"mem5",
"memdev":{
"memdev":"mem5",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x4",
"numa_node":0,
"host":"cxl_mem.4"
}
}
]
},
{
"port":"port10",
"host":"cxl_switch_uport.2",
"endpoints:port10":[
{
"endpoint":"endpoint16",
"host":"mem7",
"memdev":{
"memdev":"mem7",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x6",
"numa_node":0,
"host":"cxl_mem.6"
}
},
{
"endpoint":"endpoint11",
"host":"mem3",
"memdev":{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
}
]
}
]
}
]
}h]hX # cxl list -BEMPu -b cxl_test
{
"bus":"root3",
"provider":"cxl_test",
"ports:root3":[
{
"port":"port5",
"host":"cxl_host_bridge.1",
"ports:port5":[
{
"port":"port8",
"host":"cxl_switch_uport.1",
"endpoints:port8":[
{
"endpoint":"endpoint9",
"host":"mem2",
"memdev":{
"memdev":"mem2",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x1",
"numa_node":1,
"host":"cxl_mem.1"
}
},
{
"endpoint":"endpoint15",
"host":"mem6",
"memdev":{
"memdev":"mem6",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x5",
"numa_node":1,
"host":"cxl_mem.5"
}
}
]
},
{
"port":"port12",
"host":"cxl_switch_uport.3",
"endpoints:port12":[
{
"endpoint":"endpoint17",
"host":"mem8",
"memdev":{
"memdev":"mem8",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x7",
"numa_node":1,
"host":"cxl_mem.7"
}
},
{
"endpoint":"endpoint13",
"host":"mem4",
"memdev":{
"memdev":"mem4",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x3",
"numa_node":1,
"host":"cxl_mem.3"
}
}
]
}
]
},
{
"port":"port4",
"host":"cxl_host_bridge.0",
"ports:port4":[
{
"port":"port6",
"host":"cxl_switch_uport.0",
"endpoints:port6":[
{
"endpoint":"endpoint7",
"host":"mem1",
"memdev":{
"memdev":"mem1",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0",
"numa_node":0,
"host":"cxl_mem.0"
}
},
{
"endpoint":"endpoint14",
"host":"mem5",
"memdev":{
"memdev":"mem5",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x4",
"numa_node":0,
"host":"cxl_mem.4"
}
}
]
},
{
"port":"port10",
"host":"cxl_switch_uport.2",
"endpoints:port10":[
{
"endpoint":"endpoint16",
"host":"mem7",
"memdev":{
"memdev":"mem7",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x6",
"numa_node":0,
"host":"cxl_mem.6"
}
},
{
"endpoint":"endpoint11",
"host":"mem3",
"memdev":{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
}
]
}
]
}
]
}}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hhhK+hjl hhubj] )}(hX In that listing each "root", "port", and "endpoint" object correspond a kernel
'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to
its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
decodes them to "ports", "ports" decode to "endpoints", and "endpoints"
represent the decode from SPA (System Physical Address) to DPA (Device Physical
Address).h]hX In that listing each “root”, “port”, and “endpoint” object correspond a kernel
‘struct cxl_port’ object. A ‘cxl_port’ is a device that can decode CXL.mem to
its descendants. So “root” claims non-PCIe enumerable platform decode ranges and
decodes them to “ports”, “ports” decode to “endpoints”, and “endpoints”
represent the decode from SPA (System Physical Address) to DPA (Device Physical
Address).}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjl hhubj] )}(hX Continuing the RAID analogy, disks have both topology metadata and on-device
metadata that determine RAID set assembly. CXL Port topology and CXL Port link
status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated
by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port
objects. Conversely for hot-unplug / removal scenarios, there is no need for
the Linux PCI core to tear down switch-level CXL resources because the endpoint
->remove() event cleans up the port data that was established to support that
Memory Expander.h]hX Continuing the RAID analogy, disks have both topology metadata and on-device
metadata that determine RAID set assembly. CXL Port topology and CXL Port link
status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated
by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port
objects. Conversely for hot-unplug / removal scenarios, there is no need for
the Linux PCI core to tear down switch-level CXL resources because the endpoint
->remove() event cleans up the port data that was established to support that
Memory Expander.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjl hhubj] )}(hThe port metadata and potential decode schemes that a given memory device may
participate can be determined via a command like::h]hThe port metadata and potential decode schemes that a given memory device may
participate can be determined via a command like:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjl hhubj )}(hX # cxl list -BDMu -d root -m mem3
{
"bus":"root3",
"provider":"cxl_test",
"decoders:root3":[
{
"decoder":"decoder3.1",
"resource":"0x8030000000",
"size":"512.00 MiB (536.87 MB)",
"volatile_capable":true,
"nr_targets":2
},
{
"decoder":"decoder3.3",
"resource":"0x8060000000",
"size":"512.00 MiB (536.87 MB)",
"pmem_capable":true,
"nr_targets":2
},
{
"decoder":"decoder3.0",
"resource":"0x8020000000",
"size":"256.00 MiB (268.44 MB)",
"volatile_capable":true,
"nr_targets":1
},
{
"decoder":"decoder3.2",
"resource":"0x8050000000",
"size":"256.00 MiB (268.44 MB)",
"pmem_capable":true,
"nr_targets":1
}
],
"memdevs:root3":[
{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
]
}h]hX # cxl list -BDMu -d root -m mem3
{
"bus":"root3",
"provider":"cxl_test",
"decoders:root3":[
{
"decoder":"decoder3.1",
"resource":"0x8030000000",
"size":"512.00 MiB (536.87 MB)",
"volatile_capable":true,
"nr_targets":2
},
{
"decoder":"decoder3.3",
"resource":"0x8060000000",
"size":"512.00 MiB (536.87 MB)",
"pmem_capable":true,
"nr_targets":2
},
{
"decoder":"decoder3.0",
"resource":"0x8020000000",
"size":"256.00 MiB (268.44 MB)",
"volatile_capable":true,
"nr_targets":1
},
{
"decoder":"decoder3.2",
"resource":"0x8050000000",
"size":"256.00 MiB (268.44 MB)",
"pmem_capable":true,
"nr_targets":1
}
],
"memdevs:root3":[
{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
]
}}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hhhKhjl hhubj] )}(hXH ...which queries the CXL topology to ask "given CXL Memory Expander with a kernel
device name of 'mem3' which platform level decode ranges may this device
participate". A given expander can participate in multiple CXL.mem interleave
sets simultaneously depending on how many decoder resources it has. In this
example mem3 can participate in one or more of a PMEM interleave that spans two
Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
that only targets a single Host Bridge.h]hXP ...which queries the CXL topology to ask “given CXL Memory Expander with a kernel
device name of ‘mem3’ which platform level decode ranges may this device
participate”. A given expander can participate in multiple CXL.mem interleave
sets simultaneously depending on how many decoder resources it has. In this
example mem3 can participate in one or more of a PMEM interleave that spans two
Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
that only targets a single Host Bridge.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhKhjl hhubj] )}(hConversely the memory devices that can participate in a given platform level
decode scheme can be determined via a command like the following::h]hConversely the memory devices that can participate in a given platform level
decode scheme can be determined via a command like the following:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhMhjl hhubj )}(hXF # cxl list -MDu -d 3.2
[
{
"memdevs":[
{
"memdev":"mem1",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0",
"numa_node":0,
"host":"cxl_mem.0"
},
{
"memdev":"mem5",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x4",
"numa_node":0,
"host":"cxl_mem.4"
},
{
"memdev":"mem7",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x6",
"numa_node":0,
"host":"cxl_mem.6"
},
{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
]
},
{
"root decoders":[
{
"decoder":"decoder3.2",
"resource":"0x8050000000",
"size":"256.00 MiB (268.44 MB)",
"pmem_capable":true,
"nr_targets":1
}
]
}
]h]hXF # cxl list -MDu -d 3.2
[
{
"memdevs":[
{
"memdev":"mem1",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0",
"numa_node":0,
"host":"cxl_mem.0"
},
{
"memdev":"mem5",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x4",
"numa_node":0,
"host":"cxl_mem.4"
},
{
"memdev":"mem7",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x6",
"numa_node":0,
"host":"cxl_mem.6"
},
{
"memdev":"mem3",
"pmem_size":"256.00 MiB (268.44 MB)",
"ram_size":"256.00 MiB (268.44 MB)",
"serial":"0x2",
"numa_node":0,
"host":"cxl_mem.2"
}
]
},
{
"root decoders":[
{
"decoder":"decoder3.2",
"resource":"0x8050000000",
"size":"256.00 MiB (268.44 MB)",
"pmem_capable":true,
"nr_targets":1
}
]
}
]}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hhhMhjl hhubj] )}(hL...where the naming scheme for decoders is "decoder.".h]hP...where the naming scheme for decoders is “decoder.”.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhM8hjl hhubeh }(h ] the-cxl-busah ]h"] the cxl busah$]h&]uh1jG hjI hhhhhKubjH )}(hhh](jM )}(hDriver Infrastructureh]hDriver Infrastructure}(hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hj/ hhhhhM;ubj] )}(hFThis section covers the driver infrastructure for a CXL memory device.h]hFThis section covers the driver infrastructure for a CXL memory device.}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hhhM=hj/ hhubjH )}(hhh](jM )}(hCXL Memory Deviceh]hCXL Memory Device}(hjQ hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hjN hhhhhM@ubj] )}(hX This implements the PCI exclusive functionality for a CXL device as it is
defined by the Compute Express Link specification. CXL devices may surface
certain functionality even if it isn't CXL enabled. While this driver is
focused around the PCI specific aspects of a CXL device, it binds to the
specific CXL memory device class code, and therefore the implementation of
cxl_pci is focused around CXL memory devices.h]hX This implements the PCI exclusive functionality for a CXL device as it is
defined by the Compute Express Link specification. CXL devices may surface
certain functionality even if it isn’t CXL enabled. While this driver is
focused around the PCI specific aspects of a CXL device, it binds to the
specific CXL memory device class code, and therefore the implementation of
cxl_pci is focused around CXL memory devices.}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chKhjN hhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe driver has several responsibilities, mainly:
- Create the memX device and register on the CXL bus.
- Enumerate device's register interface and map them.
- Registers nvdimm bridge device with cxl_core.
- Registers a CXL mailbox with cxl_core.
h](hterm)}(h0The driver has several responsibilities, mainly:h]h0The driver has several responsibilities, mainly:}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK!hju ubh
definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h3Create the memX device and register on the CXL bus.h]j] )}(hj h]h3Create the memX device and register on the CXL bus.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h3Enumerate device's register interface and map them.h]j] )}(hj h]h5Enumerate device’s register interface and map them.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h-Registers nvdimm bridge device with cxl_core.h]j] )}(hj h]h-Registers nvdimm bridge device with cxl_core.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h(Registers a CXL mailbox with cxl_core.
h]j] )}(h&Registers a CXL mailbox with cxl_core.h]h&Registers a CXL mailbox with cxl_core.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:408: ./drivers/cxl/pci.chK hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]bullet-uh1j hj hK hj ubah }(h ]h ]h"]h$]h&]uh1j hju ubeh }(h ]h ]h"]h$]h&]uh1js hj hK!hjp ubah }(h ]h ]h"]h$]h&]uh1jn hjN hhhNhNubh index)}(hhh]h }(h ]h ]h"]h$]h&]entries](single$__cxl_pci_mbox_send_cmd (C function)c.__cxl_pci_mbox_send_cmdhNtauh1j hjN hhhNhNubh desc)}(hhh](h desc_signature)}(hYint __cxl_pci_mbox_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]h desc_signature_line)}(hXint __cxl_pci_mbox_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](h desc_sig_keyword_type)}(hinth]hint}(hj5 hhhNhNubah }(h ]h ]ktah"]h$]h&]uh1j3 hj/ hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKubh desc_sig_space)}(h h]h }(hjG hhhNhNubah }(h ]h ]wah"]h$]h&]uh1jE hj/ hhhjD hKubh desc_name)}(h__cxl_pci_mbox_send_cmdh]h
desc_sig_name)}(h__cxl_pci_mbox_send_cmdh]h__cxl_pci_mbox_send_cmd}(hj^ hhhNhNubah }(h ]h ]nah"]h$]h&]uh1j\ hjX ubah }(h ]h ](sig-namedescnameeh"]h$]h&]hhuh1jV hj/ hhhjD hKubh desc_parameterlist)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](h desc_parameter)}(h struct cxl_mailbox *cxl_mboxh](h desc_sig_keyword)}(hstructh]hstruct}(hj hhhNhNubah }(h ]h ]kah"]h$]h&]uh1j hj} ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} ubh)}(hhh]j] )}(h cxl_mailboxh]h cxl_mailbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomaincreftype
identifier reftargetj modnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j
ASTIdentifier)}j j` sbc.__cxl_pci_mbox_send_cmdasbuh1hhj} ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} ubh desc_sig_punctuation)}(h*h]h*}(hj hhhNhNubah }(h ]h ]pah"]h$]h&]uh1j hj} ubj] )}(hcxl_mboxh]hcxl_mbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj} ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjw ubj| )}(h struct cxl_mbox_cmd *mbox_cmdh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj" hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj$ modnameN classnameNj j )}j ]j c.__cxl_pci_mbox_send_cmdasbuh1hhj ubjF )}(h h]h }(hj@ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjN hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmbox_cmdh]hmbox_cmd}(hj[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjw ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj/ hhhjD hKubeh }(h ]h ]h"]h$]h&]hh
add_permalinkuh1j- sphinx_line_type
declaratorhj) hhhjD hKubah }(h ]j ah ](sig
sig-objecteh"]h$]h&] is_multiline
_toc_parts) _toc_namehuh1j' hjD hKhj$ hhubh desc_content)}(hhh]j] )}(hExecute a mailbox commandh]hExecute a mailbox command}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj hhubah }(h ]h ]h"]h$]h&]uh1j hj$ hhhjD hKubeh }(h ]h ](j functioneh"]h$]h&]domainj objtypej desctypej noindex noindexentrynocontentsentryuh1j" hhhjN hNhNubh container)}(hX **Parameters**
``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
``struct cxl_mbox_cmd *mbox_cmd``
Command to send to the memory device.
**Context**
Any context. Expects mbox_mutex to be held.
**Return**
-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.
Caller should check the return code in **mbox_cmd** to make sure it
succeeded.
**Description**
This is a generic form of the CXL mailbox send command thus only using the
registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory
devices, and perhaps other types of CXL devices may have further information
available upon error conditions. Driver facilities wishing to send mailbox
commands should use the wrapper command.
The CXL spec allows for up to two mailboxes. The intention is for the primary
mailbox to be OS controlled and the secondary mailbox to be used by system
firmware. This allows the OS and firmware to communicate with the device and
not need to coordinate with each other. The driver only uses the primary
mailbox.h](j] )}(h**Parameters**h]hstrong)}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubjo )}(hhh](jt )}(h5``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
h](jz )}(h ``struct cxl_mailbox *cxl_mbox``h]hliteral)}(hj h]h struct cxl_mailbox *cxl_mbox}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj )}(hhh]j] )}(hCXL mailbox contexth]hCXL mailbox context}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(hH``struct cxl_mbox_cmd *mbox_cmd``
Command to send to the memory device.
h](jz )}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j )}(hj h]h struct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj )}(hhh]j] )}(h%Command to send to the memory device.h]h%Command to send to the memory device.}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj* hKhj+ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj* hKhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h **Context**h]j )}(hjP h]hContext}(hjR hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjN ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(h+Any context. Expects mbox_mutex to be held.h]h+Any context. Expects mbox_mutex to be held.}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(h
**Return**h]j )}(hjw h]hReturn}(hjy hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hju ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(h-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.
Caller should check the return code in **mbox_cmd** to make sure it
succeeded.h](hl-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.
Caller should check the return code in }(hj hhhNhNubj )}(h **mbox_cmd**h]hmbox_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh to make sure it
succeeded.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(hXT This is a generic form of the CXL mailbox send command thus only using the
registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory
devices, and perhaps other types of CXL devices may have further information
available upon error conditions. Driver facilities wishing to send mailbox
commands should use the wrapper command.h]hXT This is a generic form of the CXL mailbox send command thus only using the
registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory
devices, and perhaps other types of CXL devices may have further information
available upon error conditions. Driver facilities wishing to send mailbox
commands should use the wrapper command.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubj] )}(hX7 The CXL spec allows for up to two mailboxes. The intention is for the primary
mailbox to be OS controlled and the secondary mailbox to be used by system
firmware. This allows the OS and firmware to communicate with the device and
not need to coordinate with each other. The driver only uses the primary
mailbox.h]hX7 The CXL spec allows for up to two mailboxes. The intention is for the primary
mailbox to be OS controlled and the secondary mailbox to be used by system
firmware. This allows the OS and firmware to communicate with the device and
not need to coordinate with each other. The driver only uses the primary
mailbox.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:411: ./drivers/cxl/pci.chKhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj] )}(hCXL memory endpoint devices and switches are CXL capable devices that are
participating in CXL.mem protocol. Their functionality builds on top of the
CXL.io protocol that allows enumerating and configuring components via
standard PCI mechanisms.h]hCXL memory endpoint devices and switches are CXL capable devices that are
participating in CXL.mem protocol. Their functionality builds on top of the
CXL.io protocol that allows enumerating and configuring components via
standard PCI mechanisms.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chK hjN hhubj] )}(hX The cxl_mem driver owns kicking off the enumeration of this CXL.mem
capability. With the detection of a CXL capable endpoint, the driver will
walk up to find the platform specific port it is connected to, and determine
if there are intervening switches in the path. If there are switches, a
secondary action is to enumerate those (implemented in cxl_core). Finally the
cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
in higher level operations.h]hX The cxl_mem driver owns kicking off the enumeration of this CXL.mem
capability. With the detection of a CXL capable endpoint, the driver will
walk up to find the platform specific port it is connected to, and determine
if there are intervening switches in the path. If there are switches, a
secondary action is to enumerate those (implemented in cxl_core). Finally the
cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
in higher level operations.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:414: ./drivers/cxl/mem.chKhjN hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_memdev (C struct) c.cxl_memdevhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h
cxl_memdevh]j. )}(hstruct cxl_memdevh](j )}(hj h]hstruct}(hj"
hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj
hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKubjF )}(h h]h }(hj0
hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj
hhhj/
hKubjW )}(h
cxl_memdevh]j] )}(hj
h]h
cxl_memdev}(hjB
hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj>
ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj
hhhj/
hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj
hhhj/
hKubah }(h ]j
ah ](j j eh"]h$]h&]j j )j huh1j' hj/
hKhj
hhubj )}(hhh]j] )}(h2CXL bus object representing a Type-3 Memory Deviceh]h2CXL bus object representing a Type-3 Memory Device}(hjd
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK&hja
hhubah }(h ]h ]h"]h$]h&]uh1j hj
hhhj/
hKubeh }(h ]h ](j structeh"]h$]h&]j j j j|
j j|
j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_memdev {
struct device dev;
struct cdev cdev;
struct cxl_dev_state *cxlds;
struct work_struct detach_work;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_nvdimm *cxl_nvd;
struct cxl_port *endpoint;
int id;
int depth;
u8 scrub_cycle;
int scrub_region_id;
void *err_rec_array;
};
**Members**
``dev``
driver core device object
``cdev``
char dev core object for ioctl operations
``cxlds``
The device state backing this device
``detach_work``
active memdev lost a port in its ancestry
``cxl_nvb``
coordinate removal of **cxl_nvd** if present
``cxl_nvd``
optional bridge to an nvdimm if the device supports pmem
``endpoint``
connection to the CXL port topology for this memory device
``id``
id number of this memdev instance.
``depth``
endpoint port depth
``scrub_cycle``
current scrub cycle set for this device
``scrub_region_id``
id number of a backed region (if any) for which current scrub cycle set
``err_rec_array``
List of xarrarys to store the memdev error records to
check attributes for a memory repair operation are from
current boot.h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubh:}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK*hj
ubj )}(hXO struct cxl_memdev {
struct device dev;
struct cdev cdev;
struct cxl_dev_state *cxlds;
struct work_struct detach_work;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_nvdimm *cxl_nvd;
struct cxl_port *endpoint;
int id;
int depth;
u8 scrub_cycle;
int scrub_region_id;
void *err_rec_array;
};h]hXO struct cxl_memdev {
struct device dev;
struct cdev cdev;
struct cxl_dev_state *cxlds;
struct work_struct detach_work;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_nvdimm *cxl_nvd;
struct cxl_port *endpoint;
int id;
int depth;
u8 scrub_cycle;
int scrub_region_id;
void *err_rec_array;
};}hj
sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK,hj
ubj] )}(h **Members**h]j )}(hj
h]hMembers}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK;hj
ubjo )}(hhh](jt )}(h"``dev``
driver core device object
h](jz )}(h``dev``h]j )}(hj
h]hdev}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK(hj
ubj )}(hhh]j] )}(hdriver core device objecth]hdriver core device object}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj
hK(hj
ubah }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1js hj
hK(hj
ubjt )}(h3``cdev``
char dev core object for ioctl operations
h](jz )}(h``cdev``h]j )}(hj
h]hcdev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK)hj ubj )}(hhh]j] )}(h)char dev core object for ioctl operationsh]h)char dev core object for ioctl operations}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK)hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK)hj
ubjt )}(h/``cxlds``
The device state backing this device
h](jz )}(h ``cxlds``h]j )}(hjC h]hcxlds}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjA ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK*hj= ubj )}(hhh]j] )}(h$The device state backing this deviceh]h$The device state backing this device}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjX hK*hjY ubah }(h ]h ]h"]h$]h&]uh1j hj= ubeh }(h ]h ]h"]h$]h&]uh1js hjX hK*hj
ubjt )}(h:``detach_work``
active memdev lost a port in its ancestry
h](jz )}(h``detach_work``h]j )}(hj| h]h detach_work}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK+hjv ubj )}(hhh]j] )}(h)active memdev lost a port in its ancestryh]h)active memdev lost a port in its ancestry}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK+hj ubah }(h ]h ]h"]h$]h&]uh1j hjv ubeh }(h ]h ]h"]h$]h&]uh1js hj hK+hj
ubjt )}(h9``cxl_nvb``
coordinate removal of **cxl_nvd** if present
h](jz )}(h ``cxl_nvb``h]j )}(hj h]hcxl_nvb}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK,hj ubj )}(hhh]j] )}(h,coordinate removal of **cxl_nvd** if presenth](hcoordinate removal of }(hj hhhNhNubj )}(h **cxl_nvd**h]hcxl_nvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh if present}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hK,hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK,hj
ubjt )}(hE``cxl_nvd``
optional bridge to an nvdimm if the device supports pmem
h](jz )}(h ``cxl_nvd``h]j )}(hj h]hcxl_nvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK-hj ubj )}(hhh]j] )}(h8optional bridge to an nvdimm if the device supports pmemh]h8optional bridge to an nvdimm if the device supports pmem}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK-hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK-hj
ubjt )}(hH``endpoint``
connection to the CXL port topology for this memory device
h](jz )}(h ``endpoint``h]j )}(hj9 h]hendpoint}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj7 ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK.hj3 ubj )}(hhh]j] )}(h:connection to the CXL port topology for this memory deviceh]h:connection to the CXL port topology for this memory device}(hjR hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjN hK.hjO ubah }(h ]h ]h"]h$]h&]uh1j hj3 ubeh }(h ]h ]h"]h$]h&]uh1js hjN hK.hj
ubjt )}(h*``id``
id number of this memdev instance.
h](jz )}(h``id``h]j )}(hjr h]hid}(hjt hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK/hjl ubj )}(hhh]j] )}(h"id number of this memdev instance.h]h"id number of this memdev instance.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK/hj ubah }(h ]h ]h"]h$]h&]uh1j hjl ubeh }(h ]h ]h"]h$]h&]uh1js hj hK/hj
ubjt )}(h ``depth``
endpoint port depth
h](jz )}(h ``depth``h]j )}(hj h]hdepth}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK0hj ubj )}(hhh]j] )}(hendpoint port depthh]hendpoint port depth}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK0hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK0hj
ubjt )}(h8``scrub_cycle``
current scrub cycle set for this device
h](jz )}(h``scrub_cycle``h]j )}(hj h]h scrub_cycle}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK1hj ubj )}(hhh]j] )}(h'current scrub cycle set for this deviceh]h'current scrub cycle set for this device}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK1hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK1hj
ubjt )}(h\``scrub_region_id``
id number of a backed region (if any) for which current scrub cycle set
h](jz )}(h``scrub_region_id``h]j )}(hj
h]hscrub_region_id}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK2hj
ubj )}(hhh]j] )}(hGid number of a backed region (if any) for which current scrub cycle seth]hGid number of a backed region (if any) for which current scrub cycle set}(hj6
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj2
hK2hj3
ubah }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1js hj2
hK2hj
ubjt )}(h``err_rec_array``
List of xarrarys to store the memdev error records to
check attributes for a memory repair operation are from
current boot.h](jz )}(h``err_rec_array``h]j )}(hjV
h]h
err_rec_array}(hjX
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjT
ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK4hjP
ubj )}(hhh]j] )}(h{List of xarrarys to store the memdev error records to
check attributes for a memory repair operation are from
current boot.h]h{List of xarrarys to store the memdev error records to
check attributes for a memory repair operation are from
current boot.}(hjo
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK3hjl
ubah }(h ]h ]h"]h$]h&]uh1j hjP
ubeh }(h ]h ]h"]h$]h&]uh1js hjk
hK4hj
ubeh }(h ]h ]h"]h$]h&]uh1jn hj
ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_event_state (C struct)c.cxl_event_statehNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hcxl_event_stateh]j. )}(hstruct cxl_event_stateh](j )}(hj h]hstruct}(hj
hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj
hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhK;ubjF )}(h h]h }(hj
hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj
hhhj
hK;ubjW )}(hcxl_event_stateh]j] )}(hj
h]hcxl_event_state}(hj
hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj
ubah }(h ]h E ](jp jq eh"]h$]h&]hhuh1jV hj
hhhj
hK;ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj
hhhj
hK;ubah }(h ]j
ah ](j j eh"]h$]h&]j j )j huh1j' hj
hK;hj
hhubj )}(hhh]j] )}(hEvent log driver stateh]hEvent log driver state}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj
hhubah }(h ]h ]h"]h$]h&]uh1j hj
hhhj
hK;ubeh }(h ]h ](j structeh"]h$]h&]j j j j
j j
j j j uh1j" hhhjN hNhNubj )}(h**Definition**::
struct cxl_event_state {
struct cxl_get_event_payload *buf;
struct mutex log_lock;
};
**Members**
``buf``
Buffer to receive event data
``log_lock``
Serialize event_buf and log useh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh:}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubj )}(h]struct cxl_event_state {
struct cxl_get_event_payload *buf;
struct mutex log_lock;
};h]h]struct cxl_event_state {
struct cxl_get_event_payload *buf;
struct mutex log_lock;
};}hj/ sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubj] )}(h **Members**h]j )}(hj@ h]hMembers}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj> ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubjo )}(hhh](jt )}(h%``buf``
Buffer to receive event data
h](jz )}(h``buf``h]j )}(hj_ h]hbuf}(hja hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj] ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhjY ubj )}(hhh]j] )}(h Buffer to receive event datah]h Buffer to receive event data}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjt hKhju ubah }(h ]h ]h"]h$]h&]uh1j hjY ubeh }(h ]h ]h"]h$]h&]uh1js hjt hKhjV ubjt )}(h,``log_lock``
Serialize event_buf and log useh](jz )}(h ``log_lock``h]j )}(hj h]hlog_lock}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubj )}(hhh]j] )}(h Serialize event_buf and log useh]h Serialize event_buf and log use}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhjV ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_poison_state (C struct)c.cxl_poison_statehNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hcxl_poison_stateh]j. )}(hstruct cxl_poison_stateh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKubjW )}(hcxl_poison_stateh]j] )}(hj h]hcxl_poison_state}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKhj hhubj )}(hhh]j] )}(hDriver poison state infoh]hDriver poison state info}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj1 hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKubeh }(h ]h ](j structeh"]h$]h&]j j j jL j jL j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_poison_state {
u32 max_errors;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)];
struct cxl_mbox_poison_out *list_out;
struct mutex mutex;
};
**Members**
``max_errors``
Maximum media error records held in device cache
``enabled_cmds``
All poison commands enabled in the CEL
``list_out``
The poison list payload returned by device
``mutex``
Protect reads of the poison listh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hjX hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjT ubh:}(hjT hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM hjP ubj )}(hstruct cxl_poison_state {
u32 max_errors;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)];
struct cxl_mbox_poison_out *list_out;
struct mutex mutex;
};h]hstruct cxl_poison_state {
u32 max_errors;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)];
struct cxl_mbox_poison_out *list_out;
struct mutex mutex;
};}hjq sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjP ubj] )}(h **Members**h]j )}(hj h]hMembers}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM hjP ubjo )}(hhh](jt )}(h@``max_errors``
Maximum media error records held in device cache
h](jz )}(h``max_errors``h]j )}(hj h]h
max_errors}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhKhj ubj )}(hhh]j] )}(h0Maximum media error records held in device cacheh]h0Maximum media error records held in device cache}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h8``enabled_cmds``
All poison commands enabled in the CEL
h](jz )}(h``enabled_cmds``h]j )}(hj h]h enabled_cmds}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM hj ubj )}(hhh]j] )}(h&All poison commands enabled in the CELh]h&All poison commands enabled in the CEL}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM hj ubjt )}(h8``list_out``
The poison list payload returned by device
h](jz )}(h ``list_out``h]j )}(hj h]hlist_out}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj
ubj )}(hhh]j] )}(h*The poison list payload returned by deviceh]h*The poison list payload returned by device}(hj, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj( hMhj) ubah }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1js hj( hMhj ubjt )}(h*``mutex``
Protect reads of the poison listh](jz )}(h ``mutex``h]j )}(hjL h]hmutex}(hjN hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjJ ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjF ubj )}(hhh]j] )}(h Protect reads of the poison listh]h Protect reads of the poison list}(hje hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjb ubah }(h ]h ]h"]h$]h&]uh1j hjF ubeh }(h ]h ]h"]h$]h&]uh1js hja hMhj ubeh }(h ]h ]h"]h$]h&]uh1jn hjP ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjN hhubj] )}(hReads of the poison list are synchronized to ensure that a reader
does not get an incomplete list because their request overlapped
(was interrupted or preceded by) another read request of the same
DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1h]hReads of the poison list are synchronized to ensure that a reader
does not get an incomplete list because their request overlapped
(was interrupted or preceded by) another read request of the same
DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjN hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_fw_state (C struct)c.cxl_fw_statehNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h cxl_fw_stateh]j. )}(hstruct cxl_fw_stateh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM
ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hM
ubjW )}(h cxl_fw_stateh]j] )}(hj h]h cxl_fw_state}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hM
ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hM
ubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hM
hj hhubj )}(hhh]j] )}(h"Firmware upload / activation stateh]h"Firmware upload / activation state}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hM
ubeh }(h ]h ](j structeh"]h$]h&]j j j j' j j' j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_fw_state {
unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)];
bool oneshot;
int num_slots;
int cur_slot;
int next_slot;
};
**Members**
``state``
fw_uploader state bitmask
``oneshot``
whether the fw upload fits in a single transfer
``num_slots``
Number of FW slots available
``cur_slot``
Slot number currently active
``next_slot``
Slot number for the new firmwareh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj/ ubh:}(hj/ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMQhj+ ubj )}(hstruct cxl_fw_state {
unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)];
bool oneshot;
int num_slots;
int cur_slot;
int next_slot;
};h]hstruct cxl_fw_state {
unsigned long state[BITS_TO_LONGS(CXL_FW_STATE_BITS)];
bool oneshot;
int num_slots;
int cur_slot;
int next_slot;
};}hjL sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShj+ ubj] )}(h **Members**h]j )}(hj] h]hMembers}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj[ ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM[hj+ ubjo )}(hhh](jt )}(h$``state``
fw_uploader state bitmask
h](jz )}(h ``state``h]j )}(hj| h]hstate}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMPhjv ubj )}(hhh]j] )}(hfw_uploader state bitmaskh]hfw_uploader state bitmask}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMPhj ubah }(h ]h ]h"]h$]h&]uh1j hjv ubeh }(h ]h ]h"]h$]h&]uh1js hj hMPhjs ubjt )}(h<``oneshot``
whether the fw upload fits in a single transfer
h](jz )}(h ``oneshot``h]j )}(hj h]honeshot}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMQhj ubj )}(hhh]j] )}(h/whether the fw upload fits in a single transferh]h/whether the fw upload fits in a single transfer}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMQhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMQhjs ubjt )}(h+``num_slots``
Number of FW slots available
h](jz )}(h
``num_slots``h]j )}(hj h]h num_slots}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMRhj ubj )}(hhh]j] )}(h Number of FW slots availableh]h Number of FW slots available}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMRhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMRhjs ubjt )}(h*``cur_slot``
Slot number currently active
h](jz )}(h ``cur_slot``h]j )}(hj' h]hcur_slot}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShj! ubj )}(hhh]j] )}(h Slot number currently activeh]h Slot number currently active}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj< hMShj= ubah }(h ]h ]h"]h$]h&]uh1j hj! ubeh }(h ]h ]h"]h$]h&]uh1js hj< hMShjs ubjt )}(h.``next_slot``
Slot number for the new firmwareh](jz )}(h
``next_slot``h]j )}(hj` h]h next_slot}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj^ ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMShjZ ubj )}(hhh]j] )}(h Slot number for the new firmwareh]h Slot number for the new firmware}(hjy hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMThjv ubah }(h ]h ]h"]h$]h&]uh1j hjZ ubeh }(h ]h ]h"]h$]h&]uh1js hju hMShjs ubeh }(h ]h ]h"]h$]h&]uh1jn hj+ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_security_state (C struct)c.cxl_security_statehNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hcxl_security_stateh]j. )}(hstruct cxl_security_stateh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMZubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMZubjW )}(hcxl_security_stateh]j] )}(hj h]hcxl_security_state}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMZubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMZubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMZhj hhubj )}(hhh]j] )}(hDevice security stateh]hDevice security state}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM^hj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMZubeh }(h ]h ](j structeh"]h$]h&]j j j j j j j j j uh1j" hhhjN hNhNubj )}(hXB **Definition**::
struct cxl_security_state {
unsigned long state;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)];
int poll_tmo_secs;
bool sanitize_active;
struct delayed_work poll_dwork;
struct kernfs_node *sanitize_node;
};
**Members**
``state``
state of last security operation
``enabled_cmds``
All security commands enabled in the CEL
``poll_tmo_secs``
polling timeout
``sanitize_active``
sanitize completion pending
``poll_dwork``
polling work item
``sanitize_node``
sanitation sysfs file to notifyh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh:}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMbhj ubj )}(hstruct cxl_security_state {
unsigned long state;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)];
int poll_tmo_secs;
bool sanitize_active;
struct delayed_work poll_dwork;
struct kernfs_node *sanitize_node;
};h]hstruct cxl_security_state {
unsigned long state;
unsigned long enabled_cmds[BITS_TO_LONGS(CXL_SEC_ENABLED_MAX)];
int poll_tmo_secs;
bool sanitize_active;
struct delayed_work poll_dwork;
struct kernfs_node *sanitize_node;
};}hj9 sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMdhj ubj] )}(h **Members**h]j )}(hjJ h]hMembers}(hjL hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMmhj ubjo )}(hhh](jt )}(h+``state``
state of last security operation
h](jz )}(h ``state``h]j )}(hji h]hstate}(hjk hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjg ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMahjc ubj )}(hhh]j] )}(h state of last security operationh]h state of last security operation}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj~ hMahj ubah }(h ]h ]h"]h$]h&]uh1j hjc ubeh }(h ]h ]h"]h$]h&]uh1js hj~ hMahj` ubjt )}(h:``enabled_cmds``
All security commands enabled in the CEL
h](jz )}(h``enabled_cmds``h]j )}(hj h]h enabled_cmds}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMbhj ubj )}(hhh]j] )}(h(All security commands enabled in the CELh]h(All security commands enabled in the CEL}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMbhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMbhj` ubjt )}(h"``poll_tmo_secs``
polling timeout
h](jz )}(h``poll_tmo_secs``h]j )}(hj h]h
poll_tmo_secs}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMchj ubj )}(hhh]j] )}(hpolling timeouth]hpolling timeout}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMchj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMchj` ubjt )}(h0``sanitize_active``
sanitize completion pending
h](jz )}(h``sanitize_active``h]j )}(hj h]hsanitize_active}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMdhj ubj )}(hhh]j] )}(hsanitize completion pendingh]hsanitize completion pending}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj) hMdhj* ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj) hMdhj` ubjt )}(h!``poll_dwork``
polling work item
h](jz )}(h``poll_dwork``h]j )}(hjM h]h
poll_dwork}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjK ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMehjG ubj )}(hhh]j] )}(hpolling work itemh]hpolling work item}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjb hMehjc ubah }(h ]h ]h"]h$]h&]uh1j hjG ubeh }(h ]h ]h"]h$]h&]uh1js hjb hMehj` ubjt )}(h1``sanitize_node``
sanitation sysfs file to notifyh](jz )}(h``sanitize_node``h]j )}(hj h]h
sanitize_node}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMehj ubj )}(hhh]j] )}(h sanitation sysfs file to notifyh]h sanitation sysfs file to notify}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMfhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMehj` ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_dpa_perf (C struct)c.cxl_dpa_perfhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h cxl_dpa_perfh]j. )}(hstruct cxl_dpa_perfh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMlubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMlubjW )}(h cxl_dpa_perfh]j] )}(hj h]h cxl_dpa_perf}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMlubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMlubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMlhj hhubj )}(hhh]j] )}(h DPA performance property entryh]h DPA performance property entry}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMlubeh }(h ]h ](j structeh"]h$]h&]j j j j: j j: j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_dpa_perf {
struct range dpa_range;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
int qos_class;
};
**Members**
``dpa_range``
range for DPA address
``coord``
QoS performance data (i.e. latency, bandwidth)
``cdat_coord``
raw QoS performance data from CDAT
``qos_class``
QoS Class cookiesh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hjF hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjB ubh:}(hjB hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj> ubj )}(hstruct cxl_dpa_perf {
struct range dpa_range;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
int qos_class;
};h]hstruct cxl_dpa_perf {
struct range dpa_range;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
int qos_class;
};}hj_ sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj> ubj] )}(h **Members**h]j )}(hjp h]hMembers}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjn ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj> ubjo )}(hhh](jt )}(h$``dpa_range``
range for DPA address
h](jz )}(h
``dpa_range``h]j )}(hj h]h dpa_range}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(hrange for DPA addressh]hrange for DPA address}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h9``coord``
QoS performance data (i.e. latency, bandwidth)
h](jz )}(h ``coord``h]j )}(hj h]hcoord}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h.QoS performance data (i.e. latency, bandwidth)h]h.QoS performance data (i.e. latency, bandwidth)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h2``cdat_coord``
raw QoS performance data from CDAT
h](jz )}(h``cdat_coord``h]j )}(hj h]h
cdat_coord}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h"raw QoS performance data from CDATh]h"raw QoS performance data from CDAT}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h ``qos_class``
QoS Class cookiesh](jz )}(h
``qos_class``h]j )}(hj: h]h qos_class}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj8 ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj4 ubj )}(hhh]j] )}(hQoS Class cookiesh]hQoS Class cookies}(hjS hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjP ubah }(h ]h ]h"]h$]h&]uh1j hj4 ubeh }(h ]h ]h"]h$]h&]uh1js hjO hMhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj> ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_dpa_partition (C struct)c.cxl_dpa_partitionhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hcxl_dpa_partitionh]j. )}(hstruct cxl_dpa_partitionh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMubjW )}(hcxl_dpa_partitionh]j] )}(hj h]hcxl_dpa_partition}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhj hhubj )}(hhh]j] )}(hDPA partition descriptorh]hDPA partition descriptor}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMubeh }(h ]h ](j structeh"]h$]h&]j j j j j j j j j uh1j" hhhjN hNhNubj )}(hXx **Definition**::
struct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
};
**Members**
``res``
shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
``perf``
performance attributes of the partition from CDAT
``mode``
operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh:}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hvstruct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
};h]hvstruct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
};}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj] )}(h **Members**h]j )}(hj$ h]hMembers}(hj& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj" ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubjo )}(hhh](jt )}(hL``res``
shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
h](jz )}(h``res``h]j )}(hjC h]hres}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjA ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj= ubj )}(hhh]j] )}(hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)h]hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjX hMhjY ubah }(h ]h ]h"]h$]h&]uh1j hj= ubeh }(h ]h ]h"]h$]h&]uh1js hjX hMhj: ubjt )}(h;``perf``
performance attributes of the partition from CDAT
h](jz )}(h``perf``h]j )}(hj| h]hperf}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjv ubj )}(hhh]j] )}(h1performance attributes of the partition from CDATh]h1performance attributes of the partition from CDAT}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hjv ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj: ubjt )}(hH``mode``
operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](jz )}(h``mode``h]j )}(hj h]hmode}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h]h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj: ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_dev_state (C struct)c.cxl_dev_statehNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h
cxl_dev_stateh]j. )}(hstruct cxl_dev_stateh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMubjW )}(h
cxl_dev_stateh]j] )}(hj h]h
cxl_dev_state}(hj/ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj+ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhj hhubj )}(hhh]j] )}(hThe driver device stateh]hThe driver device state}(hjQ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjN hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMubeh }(h ]h ](j structeh"]h$]h&]j j j ji j ji j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
bool media_ready;
struct resource dpa_res;
struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
unsigned int nr_partitions;
u64 serial;
enum cxl_devtype type;
struct cxl_mailbox cxl_mbox;
#ifdef CONFIG_CXL_FEATURES;
struct cxl_features_state *cxlfs;
#endif;
};
**Members**
``dev``
The device associated with this CXL state
``cxlmd``
The device representing the CXL.mem capabilities of **dev**
``reg_map``
component and ras register mapping parameters
``regs``
Parsed register blocks
``cxl_dvsec``
Offset to the PCIe device DVSEC
``rcd``
operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
``media_ready``
Indicate whether the device media is usable
``dpa_res``
Overall DPA resource tree for the device
``part``
DPA partition array
``nr_partitions``
Number of DPA partitions
``serial``
PCIe Device Serial Number
``type``
Generic Memory Class device or Vendor Specific Memory device
``cxl_mbox``
CXL mailbox context
``cxlfs``
CXL features contexth](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hju hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjq ubh:}(hjq hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjm ubj )}(hX struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
bool media_ready;
struct resource dpa_res;
struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
unsigned int nr_partitions;
u64 serial;
enum cxl_devtype type;
struct cxl_mailbox cxl_mbox;
#ifdef CONFIG_CXL_FEATURES;
struct cxl_features_state *cxlfs;
#endif;
};h]hX struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
struct cxl_register_map reg_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
bool media_ready;
struct resource dpa_res;
struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
unsigned int nr_partitions;
u64 serial;
enum cxl_devtype type;
struct cxl_mailbox cxl_mbox;
#ifdef CONFIG_CXL_FEATURES;
struct cxl_features_state *cxlfs;
#endif;
};}hj sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjm ubj] )}(h **Members**h]j )}(hj h]hMembers}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjm ubjo )}(hhh](jt )}(h2``dev``
The device associated with this CXL state
h](jz )}(h``dev``h]j )}(hj h]hdev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h)The device associated with this CXL stateh]h)The device associated with this CXL state}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(hF``cxlmd``
The device representing the CXL.mem capabilities of **dev**
h](jz )}(h ``cxlmd``h]j )}(hj h]hcxlmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h;The device representing the CXL.mem capabilities of **dev**h](h4The device representing the CXL.mem capabilities of }(hj hhhNhNubj )}(h**dev**h]hdev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hj hMhj
ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h:``reg_map``
component and ras register mapping parameters
h](jz )}(h ``reg_map``h]j )}(hj> h]hreg_map}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj< ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj8 ubj )}(hhh]j] )}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjS hMhjT ubah }(h ]h ]h"]h$]h&]uh1j hj8 ubeh }(h ]h ]h"]h$]h&]uh1js hjS hMhj ubjt )}(h ``regs``
Parsed register blocks
h](jz )}(h``regs``h]j )}(hjw h]hregs}(hjy hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hju ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjq ubj )}(hhh]j] )}(hParsed register blocksh]hParsed register blocks}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hjq ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h.``cxl_dvsec``
Offset to the PCIe device DVSEC
h](jz )}(h
``cxl_dvsec``h]j )}(hj h]h cxl_dvsec}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h Offset to the PCIe device DVSECh]h Offset to the PCIe device DVSEC}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(hN``rcd``
operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
h](jz )}(h``rcd``h]j )}(hj h]hrcd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)h]hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h<``media_ready``
Indicate whether the device media is usable
h](jz )}(h``media_ready``h]j )}(hj" h]h media_ready}(hj$ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(h+Indicate whether the device media is usableh]h+Indicate whether the device media is usable}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj7 hMhj8 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj7 hMhj ubjt )}(h5``dpa_res``
Overall DPA resource tree for the device
h](jz )}(h ``dpa_res``h]j )}(hj[ h]hdpa_res}(hj] hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjY ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjU ubj )}(hhh]j] )}(h(Overall DPA resource tree for the deviceh]h(Overall DPA resource tree for the device}(hjt hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjp hMhjq ubah }(h ]h ]h"]h$]h&]uh1j hjU ubeh }(h ]h ]h"]h$]h&]uh1js hjp hMhj ubjt )}(h ``part``
DPA partition array
h](jz )}(h``part``h]j )}(hj h]hpart}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(hDPA partition arrayh]hDPA partition array}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h+``nr_partitions``
Number of DPA partitions
h](jz )}(h``nr_partitions``h]j )}(hj h]h
nr_partitions}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(hNumber of DPA partitionsh]hNumber of DPA partitions}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h%``serial``
PCIe Device Serial Number
h](jz )}(h
``serial``h]j )}(hj h]hserial}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj ubj )}(hhh]j] )}(hPCIe Device Serial Numberh]hPCIe Device Serial Number}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(hF``type``
Generic Memory Class device or Vendor Specific Memory device
h](jz )}(h``type``h]j )}(hj? h]htype}(hjA hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj= ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj9 ubj )}(hhh]j] )}(h to validate the fields passed in by
the user then submit the }(hj
" hhhNhNubj )}(h
**opcode**h]hopcode}(hj'" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
" ubh to the hardware.}(hj
" hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM hjN hhubj] )}(h See struct cxl_command_info.h]h See struct cxl_command_info.}(hj@" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM"hjN hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_hdm (C struct) c.cxl_hdmhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hcxl_hdmh]j. )}(hstruct cxl_hdmh](j )}(hj h]hstruct}(hjh" hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjd" hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhM'ubjF )}(h h]h }(hjv" hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjd" hhhju" hM'ubjW )}(hcxl_hdmh]j] )}(hjb" h]hcxl_hdm}(hj" hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj" ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjd" hhhju" hM'ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj`" hhhju" hM'ubah }(h ]j[" ah ](j j eh"]h$]h&]j j )j huh1j' hju" hM'hj]" hhubj )}(hhh]j] )}(h7HDM Decoder registers and cached / decoded capabilitiesh]h7HDM Decoder registers and cached / decoded capabilities}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj" hhubah }(h ]h ]h"]h$]h&]uh1j hj]" hhhju" hM'ubeh }(h ]h ](j structeh"]h$]h&]j j j j" j j" j j j uh1j" hhhjN hNhNubj )}(hX **Definition**::
struct cxl_hdm {
struct cxl_component_regs regs;
unsigned int decoder_count;
unsigned int target_count;
unsigned int interleave_mask;
unsigned long iw_cap_mask;
struct cxl_port *port;
};
**Members**
``regs``
mapped registers, see devm_cxl_setup_hdm()
``decoder_count``
number of decoders for this port
``target_count``
for switch decoders, max downstream port targets
``interleave_mask``
interleave granularity capability, see check_interleave_cap()
``iw_cap_mask``
bitmask of supported interleave ways, see check_interleave_cap()
``port``
mapped cxl_port, see devm_cxl_setup_hdm()h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj" ubh:}(hj" hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj" ubj )}(hstruct cxl_hdm {
struct cxl_component_regs regs;
unsigned int decoder_count;
unsigned int target_count;
unsigned int interleave_mask;
unsigned long iw_cap_mask;
struct cxl_port *port;
};h]hstruct cxl_hdm {
struct cxl_component_regs regs;
unsigned int decoder_count;
unsigned int target_count;
unsigned int interleave_mask;
unsigned long iw_cap_mask;
struct cxl_port *port;
};}hj" sbah }(h ]h ]h"]h$]h&]hhuh1j hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj" ubj] )}(h **Members**h]j )}(hj" h]hMembers}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj" ubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj" ubjo )}(hhh](jt )}(h4``regs``
mapped registers, see devm_cxl_setup_hdm()
h](jz )}(h``regs``h]j )}(hj# h]hregs}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj# ubj )}(hhh]j] )}(h*mapped registers, see devm_cxl_setup_hdm()h]h*mapped registers, see devm_cxl_setup_hdm()}(hj0# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj,# hMhj-# ubah }(h ]h ]h"]h$]h&]uh1j hj# ubeh }(h ]h ]h"]h$]h&]uh1js hj,# hMhj# ubjt )}(h3``decoder_count``
number of decoders for this port
h](jz )}(h``decoder_count``h]j )}(hjP# h]h
decoder_count}(hjR# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjN# ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjJ# ubj )}(hhh]j] )}(h number of decoders for this porth]h number of decoders for this port}(hji# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hje# hMhjf# ubah }(h ]h ]h"]h$]h&]uh1j hjJ# ubeh }(h ]h ]h"]h$]h&]uh1js hje# hMhj# ubjt )}(hB``target_count``
for switch decoders, max downstream port targets
h](jz )}(h``target_count``h]j )}(hj# h]h target_count}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj# ubj )}(hhh]j] )}(h0for switch decoders, max downstream port targetsh]h0for switch decoders, max downstream port targets}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj# hMhj# ubah }(h ]h ]h"]h$]h&]uh1j hj# ubeh }(h ]h ]h"]h$]h&]uh1js hj# hMhj# ubjt )}(hR``interleave_mask``
interleave granularity capability, see check_interleave_cap()
h](jz )}(h``interleave_mask``h]j )}(hj# h]hinterleave_mask}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj# ubj )}(hhh]j] )}(h=interleave granularity capability, see check_interleave_cap()h]h=interleave granularity capability, see check_interleave_cap()}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj# hMhj# ubah }(h ]h ]h"]h$]h&]uh1j hj# ubeh }(h ]h ]h"]h$]h&]uh1js hj# hMhj# ubjt )}(hQ``iw_cap_mask``
bitmask of supported interleave ways, see check_interleave_cap()
h](jz )}(h``iw_cap_mask``h]j )}(hj# h]h iw_cap_mask}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj# ubj )}(hhh]j] )}(h@bitmask of supported interleave ways, see check_interleave_cap()h]h@bitmask of supported interleave ways, see check_interleave_cap()}(hj$ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj$ hMhj$ ubah }(h ]h ]h"]h$]h&]uh1j hj# ubeh }(h ]h ]h"]h$]h&]uh1js hj$ hMhj# ubjt )}(h2``port``
mapped cxl_port, see devm_cxl_setup_hdm()h](jz )}(h``port``h]j )}(hj4$ h]hport}(hj6$ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2$ ubah }(h ]h ]h"]h$]h&]uh1jy hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhj.$ ubj )}(hhh]j] )}(h)mapped cxl_port, see devm_cxl_setup_hdm()h]h)mapped cxl_port, see devm_cxl_setup_hdm()}(hjM$ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:417: ./drivers/cxl/cxlmem.hhMhjJ$ ubah }(h ]h ]h"]h$]h&]uh1j hj.$ ubeh }(h ]h ]h"]h$]h&]uh1js hjI$ hMhj# ubeh }(h ]h ]h"]h$]h&]uh1jn hj" ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'set_exclusive_cxl_commands (C function) c.set_exclusive_cxl_commandshNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hSvoid set_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j. )}(hRvoid set_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j4 )}(hvoidh]hvoid}(hj$ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj$ hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM/ubjF )}(h h]h }(hj$ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj$ hhhj$ hM/ubjW )}(hset_exclusive_cxl_commandsh]j] )}(hset_exclusive_cxl_commandsh]hset_exclusive_cxl_commands}(hj$ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj$ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj$ hhhj$ hM/ubjv )}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj$ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj$ ubjF )}(h h]h }(hj$ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj$ ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj$ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj$ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj$ modnameN classnameNj j )}j ]j )}j j$ sb c.set_exclusive_cxl_commandsasbuh1hhj$ ubjF )}(h h]h }(hj % hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj$ ubj )}(hj h]h*}(hj% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj$ ubj] )}(hmdsh]hmds}(hj$% hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj$ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj$ ubj| )}(hunsigned long *cmdsh](j4 )}(hunsignedh]hunsigned}(hj=% hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj9% ubjF )}(h h]h }(hjK% hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj9% ubj4 )}(hlongh]hlong}(hjY% hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj9% ubjF )}(h h]h }(hjg% hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj9% ubj )}(hj h]h*}(hju% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj9% ubj] )}(hcmdsh]hcmds}(hj% hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj9% ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj$ ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj$ hhhj$ hM/ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj$ hhhj$ hM/ubah }(h ]j$ ah ](j j eh"]h$]h&]j j )j huh1j' hj$ hM/hj$ hhubj )}(hhh]j] )}(h$atomically disable user cxl commandsh]h$atomically disable user cxl commands}(hj% hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM/hj% hhubah }(h ]h ]h"]h$]h&]uh1j hj$ hhhj$ hM/ubeh }(h ]h ](j functioneh"]h$]h&]j j j j% j j% j j j uh1j" hhhjN hNhNubj )}(hXP **Parameters**
``struct cxl_memdev_state *mds``
The device state to operate on
``unsigned long *cmds``
bitmap of commands to mark exclusive
**Description**
Grab the cxl_memdev_rwsem in write mode to flush in-flight
invocations of the ioctl path and then disable future execution of
commands with the command ids set in **cmds**.h](j] )}(h**Parameters**h]j )}(hj% h]h
Parameters}(hj% hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM3hj% ubjo )}(hhh](jt )}(h@``struct cxl_memdev_state *mds``
The device state to operate on
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj% h]h struct cxl_memdev_state *mds}(hj% hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM0hj% ubj )}(hhh]j] )}(h The device state to operate onh]h The device state to operate on}(hj& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj& hM0hj& ubah }(h ]h ]h"]h$]h&]uh1j hj% ubeh }(h ]h ]h"]h$]h&]uh1js hj& hM0hj% ubjt )}(h=``unsigned long *cmds``
bitmap of commands to mark exclusive
h](jz )}(h``unsigned long *cmds``h]j )}(hj&& h]hunsigned long *cmds}(hj(& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj$& ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM1hj & ubj )}(hhh]j] )}(h$bitmap of commands to mark exclusiveh]h$bitmap of commands to mark exclusive}(hj?& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj;& hM1hj<& ubah }(h ]h ]h"]h$]h&]uh1j hj & ubeh }(h ]h ]h"]h$]h&]uh1js hj;& hM1hj% ubeh }(h ]h ]h"]h$]h&]uh1jn hj% ubj] )}(h**Description**h]j )}(hja& h]h Description}(hjc& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj_& ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM3hj% ubj] )}(hGrab the cxl_memdev_rwsem in write mode to flush in-flight
invocations of the ioctl path and then disable future execution of
commands with the command ids set in **cmds**.h](hGrab the cxl_memdev_rwsem in write mode to flush in-flight
invocations of the ioctl path and then disable future execution of
commands with the command ids set in }(hjw& hhhNhNubj )}(h**cmds**h]hcmds}(hj& hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjw& ubh.}(hjw& hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM2hj% ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j )clear_exclusive_cxl_commands (C function) c.clear_exclusive_cxl_commandshNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(hUvoid clear_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j. )}(hTvoid clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j4 )}(hvoidh]hvoid}(hj& hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj& hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMCubjF )}(h h]h }(hj& hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& hhhj& hMCubjW )}(h clear_exclusive_cxl_commandsh]j] )}(h clear_exclusive_cxl_commandsh]h clear_exclusive_cxl_commands}(hj& hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj& ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj& hhhj& hMCubjv )}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj& hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj& ubjF )}(h h]h }(hj' hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj' hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj' ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj' modnameN classnameNj j )}j ]j )}j j& sb c.clear_exclusive_cxl_commandsasbuh1hhj& ubjF )}(h h]h }(hj3' hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& ubj )}(hj h]h*}(hjA' hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj& ubj] )}(hmdsh]hmds}(hjN' hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj& ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj& ubj| )}(hunsigned long *cmdsh](j4 )}(hunsignedh]hunsigned}(hjg' hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjc' ubjF )}(h h]h }(hju' hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc' ubj4 )}(hlongh]hlong}(hj' hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjc' ubjF )}(h h]h }(hj' hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc' ubj )}(hj h]h*}(hj' hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjc' ubj] )}(hcmdsh]hcmds}(hj' hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjc' ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj& ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj& hhhj& hMCubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj& hhhj& hMCubah }(h ]j& ah ](j j eh"]h$]h&]j j )j huh1j' hj& hMChj& hhubj )}(hhh]j] )}(h#atomically enable user cxl commandsh]h#atomically enable user cxl commands}(hj' hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMChj' hhubah }(h ]h ]h"]h$]h&]uh1j hj& hhhj& hMCubeh }(h ]h ](j functioneh"]h$]h&]j j j j' j j' j j j uh1j" hhhjN hNhNubj )}(h**Parameters**
``struct cxl_memdev_state *mds``
The device state to modify
``unsigned long *cmds``
bitmap of commands to mark available for userspaceh](j] )}(h**Parameters**h]j )}(hj' h]h
Parameters}(hj' hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj' ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMGhj' ubjo )}(hhh](jt )}(h<``struct cxl_memdev_state *mds``
The device state to modify
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj( h]h struct cxl_memdev_state *mds}(hj( hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj( ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMDhj( ubj )}(hhh]j] )}(hThe device state to modifyh]hThe device state to modify}(hj0( hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj,( hMDhj-( ubah }(h ]h ]h"]h$]h&]uh1j hj( ubeh }(h ]h ]h"]h$]h&]uh1js hj,( hMDhj( ubjt )}(hJ``unsigned long *cmds``
bitmap of commands to mark available for userspaceh](jz )}(h``unsigned long *cmds``h]j )}(hjP( h]hunsigned long *cmds}(hjR( hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjN( ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMFhjJ( ubj )}(hhh]j] )}(h2bitmap of commands to mark available for userspaceh]h2bitmap of commands to mark available for userspace}(hji( hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMEhjf( ubah }(h ]h ]h"]h$]h&]uh1j hjJ( ubeh }(h ]h ]h"]h$]h&]uh1js hje( hMFhj( ubeh }(h ]h ]h"]h$]h&]uh1jn hj' ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_mem_get_fw_info (C function)c.cxl_mem_get_fw_infohNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h6int cxl_mem_get_fw_info (struct cxl_memdev_state *mds)h]j. )}(h5int cxl_mem_get_fw_info(struct cxl_memdev_state *mds)h](j4 )}(hinth]hint}(hj( hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj( hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMubjF )}(h h]h }(hj( hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj( hhhj( hMubjW )}(hcxl_mem_get_fw_infoh]j] )}(hcxl_mem_get_fw_infoh]hcxl_mem_get_fw_info}(hj( hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj( ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj( hhhj( hMubjv )}(h (struct cxl_memdev_state *mds)h]j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj( hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj( ubjF )}(h h]h }(hj( hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj( ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj) hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj) ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj) modnameN classnameNj j )}j ]j )}j j( sbc.cxl_mem_get_fw_infoasbuh1hhj( ubjF )}(h h]h }(hj%) hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj( ubj )}(hj h]h*}(hj3) hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj( ubj] )}(hmdsh]hmds}(hj@) hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj( ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj( ubah }(h ]h ]h"]h$]h&]hhuh1ju hj( hhhj( hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj( hhhj( hMubah }(h ]j( ah ](j j eh"]h$]h&]j j )j huh1j' hj( hMhj( hhubj )}(hhh]j] )}(hGet Firmware infoh]hGet Firmware info}(hjj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjg) hhubah }(h ]h ]h"]h$]h&]uh1j hj( hhhj( hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j) j j) j j j uh1j" hhhjN hNhNubj )}(h**Parameters**
``struct cxl_memdev_state *mds``
The device data for the operation
**Description**
Retrieve firmware info for the device specified.
See CXL-3.0 8.2.9.3.1 Get FW Info
**Return**
0 if no error: or the result of the mailbox command.h](j] )}(h**Parameters**h]j )}(hj) h]h
Parameters}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj) ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubjo )}(hhh]jt )}(hC``struct cxl_memdev_state *mds``
The device data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj) h]h struct cxl_memdev_state *mds}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj) ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubj )}(hhh]j] )}(h!The device data for the operationh]h!The device data for the operation}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj) hMhj) ubah }(h ]h ]h"]h$]h&]uh1j hj) ubeh }(h ]h ]h"]h$]h&]uh1js hj) hMhj) ubah }(h ]h ]h"]h$]h&]uh1jn hj) ubj] )}(h**Description**h]j )}(hj) h]h Description}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj) ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubj] )}(h0Retrieve firmware info for the device specified.h]h0Retrieve firmware info for the device specified.}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubj] )}(h!See CXL-3.0 8.2.9.3.1 Get FW Infoh]h!See CXL-3.0 8.2.9.3.1 Get FW Info}(hj * hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubj] )}(h
**Return**h]j )}(hj * h]hReturn}(hj * hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj* ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubj] )}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj2* hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj) ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_mem_activate_fw (C function)c.cxl_mem_activate_fwhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h@int cxl_mem_activate_fw (struct cxl_memdev_state *mds, int slot)h]j. )}(h?int cxl_mem_activate_fw(struct cxl_memdev_state *mds, int slot)h](j4 )}(hinth]hint}(hja* hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj]* hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMubjF )}(h h]h }(hjp* hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj]* hhhjo* hMubjW )}(hcxl_mem_activate_fwh]j] )}(hcxl_mem_activate_fwh]hcxl_mem_activate_fw}(hj* hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj~* ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj]* hhhjo* hMubjv )}(h((struct cxl_memdev_state *mds, int slot)h](j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj* hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj* ubjF )}(h h]h }(hj* hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj* ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj* hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj* ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj* modnameN classnameNj j )}j ]j )}j j* sbc.cxl_mem_activate_fwasbuh1hhj* ubjF )}(h h]h }(hj* hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj* ubj )}(hj h]h*}(hj* hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj* ubj] )}(hmdsh]hmds}(hj* hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj* ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj* ubj| )}(hint sloth](j4 )}(hinth]hint}(hj+ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj + ubjF )}(h h]h }(hj + hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj + ubj] )}(hsloth]hslot}(hj,+ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj + ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj* ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj]* hhhjo* hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjY* hhhjo* hMubah }(h ]jT* ah ](j j eh"]h$]h&]j j )j huh1j' hjo* hMhjV* hhubj )}(hhh]j] )}(hActivate Firmwareh]hActivate Firmware}(hjV+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjS+ hhubah }(h ]h ]h"]h$]h&]uh1j hjV* hhhjo* hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jn+ j jn+ j j j uh1j" hhhjN hNhNubj )}(hX0 **Parameters**
``struct cxl_memdev_state *mds``
The device data for the operation
``int slot``
slot number to activate
**Description**
Activate firmware in a given slot for the device specified.
See CXL-3.0 8.2.9.3.3 Activate FW
**Return**
0 if no error: or the result of the mailbox command.h](j] )}(h**Parameters**h]j )}(hjx+ h]h
Parameters}(hjz+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjv+ ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubjo )}(hhh](jt )}(hC``struct cxl_memdev_state *mds``
The device data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj+ h]h struct cxl_memdev_state *mds}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj+ ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ ubj )}(hhh]j] )}(h!The device data for the operationh]h!The device data for the operation}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj+ hMhj+ ubah }(h ]h ]h"]h$]h&]uh1j hj+ ubeh }(h ]h ]h"]h$]h&]uh1js hj+ hMhj+ ubjt )}(h%``int slot``
slot number to activate
h](jz )}(h ``int slot``h]j )}(hj+ h]hint slot}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj+ ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhj+ ubj )}(hhh]j] )}(hslot number to activateh]hslot number to activate}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj+ hMhj+ ubah }(h ]h ]h"]h$]h&]uh1j hj+ ubeh }(h ]h ]h"]h$]h&]uh1js hj+ hMhj+ ubeh }(h ]h ]h"]h$]h&]uh1jn hjr+ ubj] )}(h**Description**h]j )}(hj , h]h Description}(hj
, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj , ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubj] )}(h;Activate firmware in a given slot for the device specified.h]h;Activate firmware in a given slot for the device specified.}(hj!, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubj] )}(h!See CXL-3.0 8.2.9.3.3 Activate FWh]h!See CXL-3.0 8.2.9.3.3 Activate FW}(hj0, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubj] )}(h
**Return**h]j )}(hjA, h]hReturn}(hjC, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj?, ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubj] )}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hjW, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjr+ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j "cxl_mem_abort_fw_xfer (C function)c.cxl_mem_abort_fw_xferhNtauh1j hjN hhhNhNubj# )}(hhh](j( )}(h8int cxl_mem_abort_fw_xfer (struct cxl_memdev_state *mds)h]j. )}(h7int cxl_mem_abort_fw_xfer(struct cxl_memdev_state *mds)h](j4 )}(hinth]hint}(hj, hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj, hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM ubjF )}(h h]h }(hj, hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj, hhhj, hM ubjW )}(hcxl_mem_abort_fw_xferh]j] )}(hcxl_mem_abort_fw_xferh]hcxl_mem_abort_fw_xfer}(hj, hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj, ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj, hhhj, hM ubjv )}(h (struct cxl_memdev_state *mds)h]j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj, hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj, ubjF )}(h h]h }(hj, hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj, ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj, hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj, ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj, modnameN classnameNj j )}j ]j )}j j, sbc.cxl_mem_abort_fw_xferasbuh1hhj, ubjF )}(h h]h }(hj- hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj, ubj )}(hj h]h*}(hj- hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj, ubj] )}(hmdsh]hmds}(hj - hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj, ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj, ubah }(h ]h ]h"]h$]h&]hhuh1ju hj, hhhj, hM ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj~, hhhj, hM ubah }(h ]jy, ah ](j j eh"]h$]h&]j j )j huh1j' hj, hM hj{, hhubj )}(hhh]j] )}(h Abort an in-progress FW transferh]h Abort an in-progress FW transfer}(hjF- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hjC- hhubah }(h ]h ]h"]h$]h&]uh1j hj{, hhhj, hM ubeh }(h ]h ](j functioneh"]h$]h&]j j j j^- j j^- j j j uh1j" hhhjN hNhNubj )}(hX
**Parameters**
``struct cxl_memdev_state *mds``
The device data for the operation
**Description**
Abort an in-progress firmware transfer for the device specified.
See CXL-3.0 8.2.9.3.2 Transfer FW
**Return**
0 if no error: or the result of the mailbox command.h](j] )}(h**Parameters**h]j )}(hjh- h]h
Parameters}(hjj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjf- ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjb- ubjo )}(hhh]jt )}(hC``struct cxl_memdev_state *mds``
The device data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj- h]h struct cxl_memdev_state *mds}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj- ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM hj- ubj )}(hhh]j] )}(h!The device data for the operationh]h!The device data for the operation}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj- hM hj- ubah }(h ]h ]h"]h$]h&]uh1j hj- ubeh }(h ]h ]h"]h$]h&]uh1js hj- hM hj~- ubah }(h ]h ]h"]h$]h&]uh1jn hjb- ubj] )}(h**Description**h]j )}(hj- h]h Description}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj- ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjb- ubj] )}(h@Abort an in-progress firmware transfer for the device specified.h]h@Abort an in-progress firmware transfer for the device specified.}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chM
hjb- ubj] )}(h!See CXL-3.0 8.2.9.3.2 Transfer FWh]h!See CXL-3.0 8.2.9.3.2 Transfer FW}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjb- ubj] )}(h
**Return**h]j )}(hj- h]hReturn}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj- ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjb- ubj] )}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:420: ./drivers/cxl/core/memdev.chMhjb- ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hjN hhhNhNubeh }(h ]cxl-memory-deviceah ]h"]cxl memory deviceah$]h&]uh1jG hj/ hhhhhM@ubjH )}(hhh](jM )}(hCXL Porth]hCXL Port}(hj/. hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hj,. hhhhhMRubj] )}(hX The port driver enumerates dport via PCI and scans for HDM
(Host-managed-Device-Memory) decoder resources via the
**component_reg_phys** value passed in by the agent that registered the
port. All descendant ports of a CXL root port (described by platform
firmware) are managed in this drivers context. Each driver instance
is responsible for tearing down the driver context of immediate
descendant ports. The locking for this is validated by
CONFIG_PROVE_CXL_LOCKING.h](hrThe port driver enumerates dport via PCI and scans for HDM
(Host-managed-Device-Memory) decoder resources via the
}(hj=. hhhNhNubj )}(h**component_reg_phys**h]hcomponent_reg_phys}(hjE. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj=. ubhXK value passed in by the agent that registered the
port. All descendant ports of a CXL root port (described by platform
firmware) are managed in this drivers context. Each driver instance
is responsible for tearing down the driver context of immediate
descendant ports. The locking for this is validated by
CONFIG_PROVE_CXL_LOCKING.}(hj=. hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chK hj,. hhubj] )}(hThe primary service this driver provides is presenting APIs to other
drivers to utilize the decoders, and indicating to userspace (via bind
status) the connectivity of the CXL.mem protocol throughout the
PCIe topology.h]hThe primary service this driver provides is presenting APIs to other
drivers to utilize the decoders, and indicating to userspace (via bind
status) the connectivity of the CXL.mem protocol throughout the
PCIe topology.}(hj^. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:425: ./drivers/cxl/port.chKhj,. hhubeh }(h ]cxl-portah ]h"]cxl portah$]h&]uh1jG hj/ hhhhhMRubjH )}(hhh](jM )}(hCXL Coreh]hCXL Core}(hjx. hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hju. hhhhhMWubj] )}(hThe CXL core objects like ports, decoders, and regions are shared
between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
(port-driver, region-driver, nvdimm object-drivers... etc).h]hThe CXL core objects like ports, decoders, and regions are shared
between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
(port-driver, region-driver, nvdimm object-drivers... etc).}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:430: ./drivers/cxl/cxl.hhKhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_register_map (C struct)c.cxl_register_maphNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_register_maph]j. )}(hstruct cxl_register_maph](j )}(hj h]hstruct}(hj. hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj. hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhKubjF )}(h h]h }(hj. hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj. hhhj. hKubjW )}(hcxl_register_maph]j] )}(hj. h]hcxl_register_map}(hj. hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj. ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj. hhhj. hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj. hhhj. hKubah }(h ]j. ah ](j j eh"]h$]h&]j j )j huh1j' hj. hKhj. hhubj )}(hhh]j] )}(h1DVSEC harvested register block mapping parametersh]h1DVSEC harvested register block mapping parameters}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj. hhubah }(h ]h ]h"]h$]h&]uh1j hj. hhhj. hKubeh }(h ]h ](j structeh"]h$]h&]j j j j/ j j/ j j j uh1j" hhhju. hNhNubj )}(hX\ **Definition**::
struct cxl_register_map {
struct device *host;
void __iomem *base;
resource_size_t resource;
resource_size_t max_size;
u8 reg_type;
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
struct cxl_pmu_reg_map pmu_map;
};
};
**Members**
``host``
device for devm operations and logging
``base``
virtual base of the register-block-BAR + **block_offset**
``resource``
physical resource base of the register block
``max_size``
maximum mapping size to perform register search
``reg_type``
see enum cxl_regloc_type
``{unnamed_union}``
anonymous
``component_map``
cxl_reg_map for component registers
``device_map``
cxl_reg_maps for device registers
``pmu_map``
cxl_reg_maps for CXL Performance Monitoring Unitsh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj/ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj/ ubh:}(hj/ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj / ubj )}(hX7 struct cxl_register_map {
struct device *host;
void __iomem *base;
resource_size_t resource;
resource_size_t max_size;
u8 reg_type;
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
struct cxl_pmu_reg_map pmu_map;
};
};h]hX7 struct cxl_register_map {
struct device *host;
void __iomem *base;
resource_size_t resource;
resource_size_t max_size;
u8 reg_type;
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
struct cxl_pmu_reg_map pmu_map;
};
};}hj-/ sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj / ubj] )}(h **Members**h]j )}(hj>/ h]hMembers}(hj@/ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj:2 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMahj62 ubj )}(hhh]j] )}(hthis decoder's deviceh]hthis decoder’s device}(hjU2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjQ2 hMahjR2 ubah }(h ]h ]h"]h$]h&]uh1j hj62 ubeh }(h ]h ]h"]h$]h&]uh1js hjQ2 hMahj32 ubjt )}(h ``id``
kernel device name id
h](jz )}(h``id``h]j )}(hju2 h]hid}(hjw2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjs2 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMbhjo2 ubj )}(hhh]j] )}(hkernel device name idh]hkernel device name id}(hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj2 hMbhj2 ubah }(h ]h ]h"]h$]h&]uh1j hjo2 ubeh }(h ]h ]h"]h$]h&]uh1js hj2 hMbhj32 ubjt )}(hA``hpa_range``
Host physical address range mapped by this decoder
h](jz )}(h
``hpa_range``h]j )}(hj2 h]h hpa_range}(hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMchj2 ubj )}(hhh]j] )}(h2Host physical address range mapped by this decoderh]h2Host physical address range mapped by this decoder}(hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj2 hMchj2 ubah }( h ]h ]h"]h$]h&]uh1j hj2 ubeh }(h ]h ]h"]h$]h&]uh1js hj2 hMchj32 ubjt )}(h8``interleave_ways``
number of cxl_dports in this decode
h](jz )}(h``interleave_ways``h]j )}(hj2 h]hinterleave_ways}(hj2 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMdhj2 ubj )}(hhh]j] )}(h#number of cxl_dports in this decodeh]h#number of cxl_dports in this decode}(hj 3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj2 hMdhj2 ubah }(h ]h ]h"]h$]h&]uh1j hj2 ubeh }(h ]h ]h"]h$]h&]uh1js hj2 hMdhj32 ubjt )}(h1``interleave_granularity``
data stride per dport
h](jz )}(h``interleave_granularity``h]j )}(hj 3 h]hinterleave_granularity}(hj"3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj 3 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMehj3 ubj )}(hhh]j] )}(hdata stride per dporth]hdata stride per dport}(hj93 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj53 hMehj63 ubah }(h ]h ]h"]h$]h&]uh1j hj3 ubeh }(h ]h ]h"]h$]h&]uh1js hj53 hMehj32 ubjt )}(hB``target_type``
accelerator vs expander (type2 vs type3) selector
h](jz )}(h``target_type``h]j )}(hjY3 h]h target_type}(hj[3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW3 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMfhjS3 ubj )}(hhh]j] )}(h1accelerator vs expander (type2 vs type3) selectorh]h1accelerator vs expander (type2 vs type3) selector}(hjr3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjn3 hMfhjo3 ubah }(h ]h ]h"]h$]h&]uh1j hjS3 ubeh }(h ]h ]h"]h$]h&]uh1js hjn3 hMfhj32 ubjt )}(h6``region``
currently assigned region for this decoder
h](jz )}(h
``region``h]j )}(hj3 h]hregion}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj3 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMghj3 ubj )}(hhh]j] )}(h*currently assigned region for this decoderh]h*currently assigned region for this decoder}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj3 hMghj3 ubah }(h ]h ]h"]h$]h&]uh1j hj3 ubeh }(h ]h ]h"]h$]h&]uh1js hj3 hMghj32 ubjt )}(h/``flags``
memory type capabilities and locking
h](jz )}(h ``flags``h]j )}(hj3 h]hflags}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj3 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhhj3 ubj )}(hhh]j] )}(h$memory type capabilities and lockingh]h$memory type capabilities and locking}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj3 hMhhj3 ubah }(h ]h ]h"]h$]h&]uh1j hj3 ubeh }(h ]h ]h"]h$]h&]uh1js hj3 hMhhj32 ubjt )}(hJ``commit``
device/decoder-type specific callback to commit settings to hw
h](jz )}(h
``commit``h]j )}(hj4 h]hcommit}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj4 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMihj3 ubj )}(hhh]j] )}(h>device/decoder-type specific callback to commit settings to hwh]h>device/decoder-type specific callback to commit settings to hw}(hj 4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj4 hMihj4 ubah }(h ]h ]h"]h$]h&]uh1j hj3 ubeh }(h ]h ]h"]h$]h&]uh1js hj4 hMihj32 ubjt )}(hD``reset``
device/decoder-type specific callback to reset hw settingsh](jz )}(h ``reset``h]j )}(hj=4 h]hreset}(hj?4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj;4 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMihj74 ubj )}(hhh]j] )}(h:device/decoder-type specific callback to reset hw settingsh]h:device/decoder-type specific callback to reset hw settings}(hjV4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMjhjS4 ubah }(h ]h ]h"]h$]h&]uh1j hj74 ubeh }(h ]h ]h"]h$]h&]uh1js hjR4 hMihj32 ubeh }(h ]h ]h"]h$]h&]uh1jn hj1 ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_endpoint_decoder (C struct)c.cxl_endpoint_decoderhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_endpoint_decoderh]j. )}(hstruct cxl_endpoint_decoderh](j )}(hj h]hstruct}(hj4 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj4 hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMpubjF )}(h h]h }(hj4 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj4 hhhj4 hMpubjW )}(hcxl_endpoint_decoderh]j] )}(hj4 h]hcxl_endpoint_decoder}(hj4 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj4 ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj4 hhhj4 hMpubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj4 hhhj4 hMpubah }(h ]j4 ah ](j j eh"]h$]h&]j j )j huh1j' hj4 hMphj4 hhubj )}(hhh]j] )}(h Endpoint / SPA to DPA decoderh]h Endpoint / SPA to DPA decoder}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4 hhubah }(h ]h ]h"]h$]h&]uh1j hj4 hhhj4 hMpubeh }(h ]h ](j structeh"]h$]h&]j j j j4 j j4 j j j uh1j" hhhju. hNhNubj )}(hX **Definition**::
struct cxl_endpoint_decoder {
struct cxl_decoder cxld;
struct resource *dpa_res;
resource_size_t skip;
enum cxl_decoder_state state;
int part;
int pos;
};
**Members**
``cxld``
base cxl_decoder_object
``dpa_res``
actively claimed DPA span of this decoder
``skip``
offset into **dpa_res** where **cxld.hpa_range** maps
``state``
autodiscovery state
``part``
partition index this decoder maps
``pos``
interleave position in **cxld.region**h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj4 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj4 ubh:}(hj4 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4 ubj )}(hstruct cxl_endpoint_decoder {
struct cxl_decoder cxld;
struct resource *dpa_res;
resource_size_t skip;
enum cxl_decoder_state state;
int part;
int pos;
};h]hstruct cxl_endpoint_decoder {
struct cxl_decoder cxld;
struct resource *dpa_res;
resource_size_t skip;
enum cxl_decoder_state state;
int part;
int pos;
};}hj5 sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4 ubj] )}(h **Members**h]j )}(hj'5 h]hMembers}(hj)5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj%5 ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj4 ubjo )}(hhh](jt )}(h!``cxld``
base cxl_decoder_object
h](jz )}(h``cxld``h]j )}(hjF5 h]hcxld}(hjH5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD5 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@5 ubj )}(hhh]j] )}(hbase cxl_decoder_objecth]hbase cxl_decoder_object}(hj_5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj[5 hMhj\5 ubah }(h ]h ]h"]h$]h&]uh1j hj@5 ubeh }(h ]h ]h"]h$]h&]uh1js hj[5 hMhj=5 ubjt )}(h6``dpa_res``
actively claimed DPA span of this decoder
h](jz )}(h ``dpa_res``h]j )}(hj5 h]hdpa_res}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj}5 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjy5 ubj )}(hhh]j] )}(h)actively claimed DPA span of this decoderh]h)actively claimed DPA span of this decoder}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj5 hMhj5 ubah }(h ]h ]h"]h$]h&]uh1j hjy5 ubeh }(h ]h ]h"]h$]h&]uh1js hj5 hMhj=5 ubjt )}(h?``skip``
offset into **dpa_res** where **cxld.hpa_range** maps
h](jz )}(h``skip``h]j )}(hj5 h]hskip}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5 ubj )}(hhh]j] )}(h5offset into **dpa_res** where **cxld.hpa_range** mapsh](h offset into }(hj5 hhhNhNubj )}(h **dpa_res**h]hdpa_res}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubh where }(hj5 hhhNhNubj )}(h**cxld.hpa_range**h]hcxld.hpa_range}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubh maps}(hj5 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj5 hMhj5 ubah }(h ]h ]h"]h$]h&]uh1j hj5 ubeh }(h ]h ]h"]h$]h&]uh1js hj5 hMhj=5 ubjt )}(h ``state``
autodiscovery state
h](jz )}(h ``state``h]j )}(hj6 h]hstate}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj6 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6 ubj )}(hhh]j] )}(hautodiscovery stateh]hautodiscovery state}(hj.6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj*6 hMhj+6 ubah }(h ]h ]h"]h$]h&]uh1j hj6 ubeh }(h ]h ]h"]h$]h&]uh1js hj*6 hMhj=5 ubjt )}(h+``part``
partition index this decoder maps
h](jz )}(h``part``h]j )}(hjN6 h]hpart}(hjP6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjL6 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjH6 ubj )}(hhh]j] )}(h!partition index this decoder mapsh]h!partition index this decoder maps}(hjg6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjc6 hMhjd6 ubah }(h ]h ]h"]h$]h&]uh1j hjH6 ubeh }(h ]h ]h"]h$]h&]uh1js hjc6 hMhj=5 ubjt )}(h.``pos``
interleave position in **cxld.region**h](jz )}(h``pos``h]j )}(hj6 h]hpos}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj6 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6 ubj )}(hhh]j] )}(h&interleave position in **cxld.region**h](hinterleave position in }(hj6 hhhNhNubj )}(h**cxld.region**h]h cxld.region}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj6 ubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6 ubah }(h ]h ]h"]h$]h&]uh1j hj6 ubeh }(h ]h ]h"]h$]h&]uh1js hj6 hMhj=5 ubeh }(h ]h ]h"]h$]h&]uh1jn hj4 ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_switch_decoder (C struct)c.cxl_switch_decoderhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_switch_decoderh]j. )}(hstruct cxl_switch_decoderh](j )}(hj h]hstruct}(hj6 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj6 hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF )}(h h]h }(hj6 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj6 hhhj6 hMubjW )}(hcxl_switch_decoderh]j] )}(hj6 h]hcxl_switch_decoder}(hj7 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj 7 ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj6 hhhj6 hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj6 hhhj6 hMubah }(h ]j6 ah ](j j eh"]h$]h&]j j )j huh1j' hj6 hMhj6 hhubj )}(hhh]j] )}(h Switch specific CXL HDM Decoderh]h Switch specific CXL HDM Decoder}(hj17 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj.7 hhubah }(h ]h ]h"]h$]h&]uh1j hj6 hhhj6 hMubeh }(h ]h ](j structeh"]h$]h&]j j j jI7 j jI7 j j j uh1j" hhhju. hNhNubj )}(hX9 **Definition**::
struct cxl_switch_decoder {
struct cxl_decoder cxld;
int nr_targets;
struct cxl_dport *target[];
};
**Members**
``cxld``
base cxl_decoder object
``nr_targets``
number of elements in **target**
``target``
active ordered target list in current decoder configurationh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hjU7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjQ7 ubh:}(hjQ7 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjM7 ubj )}(hostruct cxl_switch_decoder {
struct cxl_decoder cxld;
int nr_targets;
struct cxl_dport *target[];
};h]hostruct cxl_switch_decoder {
struct cxl_decoder cxld;
int nr_targets;
struct cxl_dport *target[];
};}hjn7 sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjM7 ubj] )}(h **Members**h]j )}(hj7 h]hMembers}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj}7 ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjM7 ubjo )}(hhh](jt )}(h!``cxld``
base cxl_decoder object
h](jz )}(h``cxld``h]j )}(hj7 h]hcxld}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj7 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj7 ubj )}(hhh]j] )}(hbase cxl_decoder objecth]hbase cxl_decoder object}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj7 hMhj7 ubah }(h ]h ]h"]h$]h&]uh1j hj7 ubeh }(h ]h ]h"]h$]h&]uh1js hj7 hMhj7 ubjt )}(h0``nr_targets``
number of elements in **target**
h](jz )}(h``nr_targets``h]j )}(hj7 h]h
nr_targets}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj7 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj7 ubj )}(hhh]j] )}(h number of elements in **target**h](hnumber of elements in }(hj7 hhhNhNubj )}(h
**target**h]htarget}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj7 ubeh }(h ]h ]h"]h$]h&]uh1j\ hj7 hMhj7 ubah }(h ]h ]h"]h$]h&]uh1j hj7 ubeh }(h ]h ]h"]h$]h&]uh1js hj7 hMhj7 ubjt )}(hF``target``
active ordered target list in current decoder configurationh](jz )}(h
``target``h]j )}(hj 8 h]htarget}(hj 8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj 8 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8 ubj )}(hhh]j] )}(h;active ordered target list in current decoder configurationh]h;active ordered target list in current decoder configuration}(hj78 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj48 ubah }(h ]h ]h"]h$]h&]uh1j hj8 ubeh }(h ]h ]h"]h$]h&]uh1js hj38 hMhj7 ubeh }(h ]h ]h"]h$]h&]uh1jn hjM7 ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(h**Description**h]j )}(hja8 h]h Description}(hjc8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj_8 ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhju. hhubj] )}(hXT The 'switch' decoder type represents the decoder instances of cxl_port's that
route from the root of a CXL memory decode topology to the endpoints. They
come in two flavors, root-level decoders, statically defined by platform
firmware, and mid-level decoders, where interleave-granularity,
interleave-width, and the target list are mutable.h]hXZ The ‘switch’ decoder type represents the decoder instances of cxl_port’s that
route from the root of a CXL memory decode topology to the endpoints. They
come in two flavors, root-level decoders, statically defined by platform
firmware, and mid-level decoders, where interleave-granularity,
interleave-width, and the target list are mutable.}(hjw8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_root_decoder (C struct)c.cxl_root_decoderhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_root_decoderh]j. )}(hstruct cxl_root_decoderh](j )}(hj h]hstruct}(hj8 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj8 hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF )}(h h]h }(hj8 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj8 hhhj8 hMubjW )}(hcxl_root_decoderh]j] )}(hj8 h]hcxl_root_decoder}(hj8 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj8 ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj8 hhhj8 hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj8 hhhj8 hMubah }(h ]j8 ah ](j j eh"]h$]h&]j j )j huh1j' hj8 hMhj8 hhubj )}(hhh]j] )}(h#Static platform CXL address decoderh]h#Static platform CXL address decoder}(hj8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8 hhubah }(h ]h ]h"]h$]h&]uh1j hj8 hhhj8 hMubeh }(h ]h ](j structeh"]h$]h&]j j j j8 j j8 j j j uh1j" hhhju. hNhNubj )}(hX **Definition**::
struct cxl_root_decoder {
struct resource *res;
resource_size_t cache_size;
atomic_t region_id;
cxl_hpa_to_spa_fn hpa_to_spa;
void *platform_data;
struct mutex range_lock;
int qos_class;
struct cxl_switch_decoder cxlsd;
};
**Members**
``res``
host / parent resource for region allocations
``cache_size``
extended linear cache size if exists, otherwise zero.
``region_id``
region id for next region provisioning event
``hpa_to_spa``
translate CXL host-physical-address to Platform system-physical-address
``platform_data``
platform specific configuration data
``range_lock``
sync region autodiscovery by address range
``qos_class``
QoS performance class cookie
``cxlsd``
base cxl switch decoderh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj9 ubh:}(hj9 hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8 ubj )}(hstruct cxl_root_decoder {
struct resource *res;
resource_size_t cache_size;
atomic_t region_id;
cxl_hpa_to_spa_fn hpa_to_spa;
void *platform_data;
struct mutex range_lock;
int qos_class;
struct cxl_switch_decoder cxlsd;
};h]hstruct cxl_root_decoder {
struct resource *res;
resource_size_t cache_size;
atomic_t region_id;
cxl_hpa_to_spa_fn hpa_to_spa;
void *platform_data;
struct mutex range_lock;
int qos_class;
struct cxl_switch_decoder cxlsd;
};}hj 9 sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8 ubj] )}(h **Members**h]j )}(hj/9 h]hMembers}(hj19 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj-9 ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj8 ubjo )}(hhh](jt )}(h6``res``
host / parent resource for region allocations
h](jz )}(h``res``h]j )}(hjN9 h]hres}(hjP9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjL9 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjH9 ubj )}(hhh]j] )}(h-host / parent resource for region allocationsh]h-host / parent resource for region allocations}(hjg9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjc9 hMhjd9 ubah }(h ]h ]h"]h$]h&]uh1j hjH9 ubeh }(h ]h ]h"]h$]h&]uh1js hjc9 hMhjE9 ubjt )}(hE``cache_size``
extended linear cache size if exists, otherwise zero.
h](jz )}(h``cache_size``h]j )}(hj9 h]h
cache_size}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj9 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9 ubj )}(hhh]j] )}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj9 hMhj9 ubah }(h ]h ]h"]h$]h&]uh1j hj9 ubeh }(h ]h ]h"]h$]h&]uh1js hj9 hMhjE9 ubjt )}(h;``region_id``
region id for next region provisioning event
h](jz )}(h
``region_id``h]j )}(hj9 h]h region_id}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj9 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9 ubj )}(hhh]j] )}(h,region id for next region provisioning eventh]h,region id for next region provisioning event}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj9 hMhj9 ubah }(h ]h ]h"]h$]h&]uh1j hj9 ubeh }(h ]h ]h"]h$]h&]uh1js hj9 hMhjE9 ubjt )}(hW``hpa_to_spa``
translate CXL host-physical-address to Platform system-physical-address
h](jz )}(h``hpa_to_spa``h]j )}(hj9 h]h
hpa_to_spa}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj9 ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj9 ubj )}(hhh]j] )}(hGtranslate CXL host-physical-address to Platform system-physical-addressh]hGtranslate CXL host-physical-address to Platform system-physical-address}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj: hMhj: ubah }(h ]h ]h"]h$]h&]uh1j hj9 ubeh }(h ]h ]h"]h$]h&]uh1js hj: hMhjE9 ubjt )}(h7``platform_data``
platform specific configuration data
h](jz )}(h``platform_data``h]j )}(hj2: h]h
platform_data}(hj4: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj0: ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj,: ubj )}(hhh]j] )}(h$platform specific configuration datah]h$platform specific configuration data}(hjK: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjG: hMhjH: ubah }(h ]h ]h"]h$]h&]uh1j hj,: ubeh }(h ]h ]h"]h$]h&]uh1js hjG: hMhjE9 ubjt )}(h:``range_lock``
sync region autodiscovery by address range
h](jz )}(h``range_lock``h]j )}(hjk: h]h
range_lock}(hjm: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hji: ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhje: ubj )}(hhh]j] )}(h*sync region autodiscovery by address rangeh]h*sync region autodiscovery by address range}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj: hMhj: ubah }(h ]h ]h"]h$]h&]uh1j hje: ubeh }(h ]h ]h"]h$]h&]uh1js hj: hMhjE9 ubjt )}(h+``qos_class``
QoS performance class cookie
h](jz )}(h
``qos_class``h]j )}(hj: h]h qos_class}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj: ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj: ubj )}(hhh]j] )}(h QoS performance class cookieh]h QoS performance class cookie}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj: hMhj: ubah }(h ]h ]h"]h$]h&]uh1j hj: ubeh }(h ]h ]h"]h$]h&]uh1js hj: hMhjE9 ubjt )}(h!``cxlsd``
base cxl switch decoderh](jz )}(h ``cxlsd``h]j )}(hj: h]hcxlsd}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj: ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj: ubj )}(hhh]j] )}(hbase cxl switch decoderh]hbase cxl switch decoder}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj: ubah }(h ]h ]h"]h$]h&]uh1j hj: ubeh }(h ]h ]h"]h$]h&]uh1js hj: hMhjE9 ubeh }(h ]h ]h"]h$]h&]uh1jn hj8 ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_region_params (C struct)c.cxl_region_paramshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_region_paramsh]j. )}(hstruct cxl_region_paramsh](j )}(hj h]hstruct}(hj7; hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj3; hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF )}(h h]h }(hjE; hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj3; hhhjD; hMubjW )}(hcxl_region_paramsh]j] )}(hj1; h]hcxl_region_params}(hjW; hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjS; ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj3; hhhjD; hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj/; hhhjD; hMubah }(h ]j*; ah ](j j eh"]h$]h&]j j )j huh1j' hjD; hMhj,; hhubj )}(hhh]j] )}(hregion settingsh]hregion settings}(hjy; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjv; hhubah }(h ]h ]h"]h$]h&]uh1j hj,; hhhjD; hMubeh }(h ]h ](j structeh"]h$]h&]j j j j; j j; j j j uh1j" hhhju. hNhNubj )}(hX- **Definition**::
struct cxl_region_params {
enum cxl_config_state state;
uuid_t uuid;
int interleave_ways;
int interleave_granularity;
struct resource *res;
struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
int nr_targets;
resource_size_t cache_size;
};
**Members**
``state``
allow the driver to lockdown further parameter changes
``uuid``
unique id for persistent regions
``interleave_ways``
number of endpoints in the region
``interleave_granularity``
capacity each endpoint contributes to a stripe
``res``
allocated iomem capacity for this region
``targets``
active ordered targets in current decoder configuration
``nr_targets``
number of targets
``cache_size``
extended linear cache size if exists, otherwise zero.h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj; ubh:}(hj; hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj; ubj )}(hX struct cxl_region_params {
enum cxl_config_state state;
uuid_t uuid;
int interleave_ways;
int interleave_granularity;
struct resource *res;
struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
int nr_targets;
resource_size_t cache_size;
};h]hX struct cxl_region_params {
enum cxl_config_state state;
uuid_t uuid;
int interleave_ways;
int interleave_granularity;
struct resource *res;
struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
int nr_targets;
resource_size_t cache_size;
};}hj; sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj; ubj] )}(h **Members**h]j )}(hj; h]hMembers}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj; ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj; ubjo )}(hhh](jt )}(hA``state``
allow the driver to lockdown further parameter changes
h](jz )}(h ``state``h]j )}(hj; h]hstate}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj; ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj; ubj )}(hhh]j] )}(h6allow the driver to lockdown further parameter changesh]h6allow the driver to lockdown further parameter changes}(hj; hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj; hMhj; ubah }(h ]h ]h"]h$]h&]uh1j hj; ubeh }(h ]h ]h"]h$]h&]uh1js hj; hMhj; ubjt )}(h*``uuid``
unique id for persistent regions
h](jz )}(h``uuid``h]j )}(hj < h]huuid}(hj!< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj < ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj< ubj )}(hhh]j] )}(h unique id for persistent regionsh]h unique id for persistent regions}(hj8< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj4< hMhj5< ubah }(h ]h ]h"]h$]h&]uh1j hj< ubeh }(h ]h ]h"]h$]h&]uh1js hj4< hMhj; ubjt )}(h6``interleave_ways``
number of endpoints in the region
h](jz )}(h``interleave_ways``h]j )}(hjX< h]hinterleave_ways}(hjZ< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV< ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjR< ubj )}(hhh]j] )}(h!number of endpoints in the regionh]h!number of endpoints in the region}(hjq< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjm< hMhjn< ubah }(h ]h ]h"]h$]h&]uh1j hjR< ubeh }(h ]h ]h"]h$]h&]uh1js hjm< hMhj; ubjt )}(hJ``interleave_granularity``
capacity each endpoint contributes to a stripe
h](jz )}(h``interleave_granularity``h]j )}(hj< h]hinterleave_granularity}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj< ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj< ubj )}(hhh]j] )}(h.capacity each endpoint contributes to a stripeh]h.capacity each endpoint contributes to a stripe}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj< hMhj< ubah }(h ]h ]h"]h$]h&]uh1j hj< ubeh }(h ]h ]h"]h$]h&]uh1js hj< hMhj; ubjt )}(h1``res``
allocated iomem capacity for this region
h](jz )}(h``res``h]j )}(hj< h]hres}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj< ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj< ubj )}(hhh]j] )}(h(allocated iomem capacity for this regionh]h(allocated iomem capacity for this region}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj< hMhj< ubah }(h ]h ]h"]h$]h&]uh1j hj< ubeh }(h ]h ]h"]h$]h&]uh1js hj< hMhj; ubjt )}(hD``targets``
active ordered targets in current decoder configuration
h](jz )}(h ``targets``h]j )}(hj= h]htargets}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj= ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj< ubj )}(hhh]j] )}(h7active ordered targets in current decoder configurationh]h7active ordered targets in current decoder configuration}(hj = hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj= hMhj= ubah }(h ]h ]h"]h$]h&]uh1j hj< ubeh }(h ]h ]h"]h$]h&]uh1js hj= hMhj; ubjt )}(h!``nr_targets``
number of targets
h](jz )}(h``nr_targets``h]j )}(hj<= h]h
nr_targets}(hj>= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj:= ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj6= ubj )}(hhh]j] )}(hnumber of targetsh]hnumber of targets}(hjU= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjQ= hMhjR= ubah }(h ]h ]h"]h$]h&]uh1j hj6= ubeh }(h ]h ]h"]h$]h&]uh1js hjQ= hMhj; ubjt )}(hD``cache_size``
extended linear cache size if exists, otherwise zero.h](jz )}(h``cache_size``h]j )}(hju= h]h
cache_size}(hjw= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjs= ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjo= ubj )}(hhh]j] )}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj= ubah }(h ]h ]h"]h$]h&]uh1j hjo= ubeh }(h ]h ]h"]h$]h&]uh1js hj= hMhj; ubeh }(h ]h ]h"]h$]h&]uh1jn hj; ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(h**Description**h]j )}(hj= h]h Description}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj= ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhju. hhubj] )}(h3State transitions are protected by cxl_rwsem.regionh]h3State transitions are protected by cxl_rwsem.region}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_region (C struct) c.cxl_regionhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h
cxl_regionh]j. )}(hstruct cxl_regionh](j )}(hj h]hstruct}(hj= hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj= hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF )}(h h]h }(hj> hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj= hhhj> hMubjW )}(h
cxl_regionh]j] )}(hj= h]h
cxl_region}(hj> hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj> ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj= hhhj> hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj= hhhj> hMubah }(h ]j= ah ](j j eh"]h$]h&]j j )j huh1j' hj> hMhj= hhubj )}(hhh]j] )}(h
CXL regionh]h
CXL region}(hj8> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj5> hhubah }(h ]h ]h"]h$]h&]uh1j hj= hhhj> hMubeh }(h ]h ](j structeh"]h$]h&]j j j jP> j jP> j j j uh1j" hhhju. hNhNubj )}(hX? **Definition**::
struct cxl_region {
struct device dev;
int id;
enum cxl_partition_mode mode;
enum cxl_decoder_type type;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_pmem_region *cxlr_pmem;
unsigned long flags;
struct cxl_region_params params;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct notifier_block node_notifier;
struct notifier_block adist_notifier;
};
**Members**
``dev``
This region's device
``id``
This region's id. Id is globally unique across all regions
``mode``
Operational mode of the mapped capacity
``type``
Endpoint decoder target type
``cxl_nvb``
nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown
``cxlr_pmem``
(for pmem regions) cached copy of the nvdimm bridge
``flags``
Region state flags
``params``
active + config params for the region
``coord``
QoS access coordinates for the region
``node_notifier``
notifier for setting the access coordinates to node
``adist_notifier``
notifier for calculating the abstract distance of nodeh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj\> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjX> ubh:}(hjX> hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjT> ubj )}(hX struct cxl_region {
struct device dev;
int id;
enum cxl_partition_mode mode;
enum cxl_decoder_type type;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_pmem_region *cxlr_pmem;
unsigned long flags;
struct cxl_region_params params;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct notifier_block node_notifier;
struct notifier_block adist_notifier;
};h]hX struct cxl_region {
struct device dev;
int id;
enum cxl_partition_mode mode;
enum cxl_decoder_type type;
struct cxl_nvdimm_bridge *cxl_nvb;
struct cxl_pmem_region *cxlr_pmem;
unsigned long flags;
struct cxl_region_params params;
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
struct notifier_block node_notifier;
struct notifier_block adist_notifier;
};}hju> sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjT> ubj] )}(h **Members**h]j )}(hj> h]hMembers}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj> ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjT> ubjo )}(hhh](jt )}(h ``dev``
This region's device
h](jz )}(h``dev``h]j )}(hj> h]hdev}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj> ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj> ubj )}(hhh]j] )}(hThis region's deviceh]hThis region’s device}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj> hMhj> ubah }(h ]h ]h"]h$]h&]uh1j hj> ubeh }(h ]h ]h"]h$]h&]uh1js hj> hMhj> ubjt )}(hB``id``
This region's id. Id is globally unique across all regions
h](jz )}(h``id``h]j )}(hj> h]hid}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj> ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM hj> ubj )}(hhh]j] )}(h:This region's id. Id is globally unique across all regionsh]h hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj> hM hj> ubah }(h ]h ]h"]h$]h&]uh1j hj> ubeh }(h ]h ]h"]h$]h&]uh1js hj> hM hj> ubjt )}(h1``mode``
Operational mode of the mapped capacity
h](jz )}(h``mode``h]j )}(hj? h]hmode}(hj? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj? ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj? ubj )}(hhh]j] )}(h'Operational mode of the mapped capacityh]h'Operational mode of the mapped capacity}(hj0? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj,? hMhj-? ubah }(h ]h ]h"]h$]h&]uh1j hj? ubeh }(h ]h ]h"]h$]h&]uh1js hj,? hMhj> ubjt )}(h&``type``
Endpoint decoder target type
h](jz )}(h``type``h]j )}(hjP? h]htype}(hjR? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjN? ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjJ? ubj )}(hhh]j] )}(h Endpoint decoder target typeh]h Endpoint decoder target type}(hji? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hje? hMhjf? ubah }(h ]h ]h"]h$]h&]uh1j hjJ? ubeh }(h ]h ]h"]h$]h&]uh1js hje? hMhj> ubjt )}(hJ``cxl_nvb``
nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown
h](jz )}(h ``cxl_nvb``h]j )}(hj? h]hcxl_nvb}(hj? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj? ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj? ubj )}(hhh]j] )}(h=nvdimm bridge for coordinating **cxlr_pmem** setup / shutdownh](h nvdimm bridge for coordinating }(hj? hhhNhNubj )}(h
**cxlr_pmem**h]h cxlr_pmem}(hj? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj? ubh setup / shutdown}(hj? hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj? hMhj? ubah }(h ]h ]h"]h$]h&]uh1j hj? ubeh }(h ]h ]h"]h$]h&]uh1js hj? hMhj> ubjt )}(hB``cxlr_pmem``
(for pmem regions) cached copy of the nvdimm bridge
h](jz )}(h
``cxlr_pmem``h]j )}(hj? h]h cxlr_pmem}(hj? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj? ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj? ubj )}(hhh]j] )}(h3(for pmem regions) cached copy of the nvdimm bridgeh]h3(for pmem regions) cached copy of the nvdimm bridge}(hj? hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj? hMhj? ubah }(h ]h ]h"]h$]h&]uh1j hj? ubeh }(h ]h ]h"]h$]h&]uh1js hj? hMhj> ubjt )}(h ``flags``
Region state flags
h](jz )}(h ``flags``h]j )}(hj
@ h]hflags}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj @ ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ ubj )}(hhh]j] )}(hRegion state flagsh]hRegion state flags}(hj&@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj"@ hMhj#@ ubah }(h ]h ]h"]h$]h&]uh1j hj@ ubeh }(h ]h ]h"]h$]h&]uh1js hj"@ hMhj> ubjt )}(h1``params``
active + config params for the region
h](jz )}(h
``params``h]j )}(hjF@ h]hparams}(hjH@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD@ ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@@ ubj )}(hhh]j] )}(h%active + config params for the regionh]h%active + config params for the region}(hj_@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj[@ hMhj\@ ubah }(h ]h ]h"]h$]h&]uh1j hj@@ ubeh }(h ]h ]h"]h$]h&]uh1js hj[@ hMhj> ubjt )}(h0``coord``
QoS access coordinates for the region
h](jz )}(h ``coord``h]j )}(hj@ h]hcoord}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj}@ ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjy@ ubj )}(hhh]j] )}(h%QoS access coordinates for the regionh]h%QoS access coordinates for the region}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj@ hMhj@ ubah }(h ]h ]h"]h$]h&]uh1j hjy@ ubeh }(h ]h ]h"]h$]h&]uh1js hj@ hMhj> ubjt )}(hF``node_notifier``
notifier for setting the access coordinates to node
h](jz )}(h``node_notifier``h]j )}(hj@ h]h
node_notifier}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj@ ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ ubj )}(hhh]j] )}(h3notifier for setting the access coordinates to nodeh]h3notifier for setting the access coordinates to node}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj@ hMhj@ ubah }(h ]h ]h"]h$]h&]uh1j hj@ ubeh }(h ]h ]h"]h$]h&]uh1js hj@ hMhj> ubjt )}(hI``adist_notifier``
notifier for calculating the abstract distance of nodeh](jz )}(h``adist_notifier``h]j )}(hj@ h]hadist_notifier}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj@ ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhj@ ubj )}(hhh]j] )}(h6notifier for calculating the abstract distance of nodeh]h6notifier for calculating the abstract distance of node}(hj
A hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM hjA ubah }(h ]h ]h"]h$]h&]uh1j hj@ ubeh }(h ]h ]h"]h$]h&]uh1js hjA hMhj> ubeh }(h ]h ]h"]h$]h&]uh1jn hjT> ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_port (C struct)
c.cxl_porthNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcxl_porth]j. )}(hstruct cxl_porth](j )}(hj h]hstruct}(hjKA hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjGA hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMubjF )}(h h]h }(hjYA hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjGA hhhjXA hMubjW )}(hcxl_porth]j] )}(hjEA h]hcxl_port}(hjkA hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjgA ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjGA hhhjXA hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjCA hhhjXA hMubah }(h ]j>A ah ](j j eh"]h$]h&]j j )j huh1j' hjXA hMhj@A hhubj )}(hhh]j] )}(hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.h]hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.}(hjA hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMAhjA hhubah }(h ]h ]h"]h$]h&]uh1j hj@A hhhjXA hMubeh }(h ]h ](j structeh"]h$]h&]j j j jA j jA j j j uh1j" hhhju. hNhNubj )}(hX **Definition**::
struct cxl_port {
struct device dev;
struct device *uport_dev;
struct device *host_bridge;
int id;
struct xarray dports;
struct xarray endpoints;
struct xarray regions;
struct cxl_dport *parent_dport;
struct ida decoder_ida;
struct cxl_register_map reg_map;
int nr_dports;
int hdm_end;
int commit_end;
bool dead;
unsigned int depth;
struct cxl_cdat {
void *table;
size_t length;
} cdat;
bool cdat_available;
long pci_latency;
};
**Members**
``dev``
this port's device
``uport_dev``
PCI or platform device implementing the upstream port capability
``host_bridge``
Shortcut to the platform attach point for this port
``id``
id for port device-name
``dports``
cxl_dport instances referenced by decoders
``endpoints``
cxl_ep instances, endpoints that are a descendant of this port
``regions``
cxl_region_ref instances, regions mapped by this port
``parent_dport``
dport that points to this port in the parent
``decoder_ida``
allocator for decoder ids
``reg_map``
component and ras register mapping parameters
``nr_dports``
number of entries in **dports**
``hdm_end``
track last allocated HDM decoder instance for allocation ordering
``commit_end``
cursor to track highest committed decoder for commit ordering
``dead``
last ep has been removed, force port re-creation
``depth``
How deep this port is relative to the root. depth 0 is the root.
``cdat``
Cached CDAT data
``cdat_available``
Should a CDAT attribute be available in sysfs
``pci_latency``
Upstream latency in picosecondsh](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hjA hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjA ubh:}(hjA hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMEhjA ubj )}(hX struct cxl_port {
struct device dev;
struct device *uport_dev;
struct device *host_bridge;
int id;
struct xarray dports;
struct xarray endpoints;
struct xarray regions;
struct cxl_dport *parent_dport;
struct ida decoder_ida;
struct cxl_register_map reg_map;
int nr_dports;
int hdm_end;
int commit_end;
bool dead;
unsigned int depth;
struct cxl_cdat {
void *table;
size_t length;
} cdat;
bool cdat_available;
long pci_latency;
};h]hX struct cxl_port {
struct device dev;
struct device *uport_dev;
struct device *host_bridge;
int id;
struct xarray dports;
struct xarray endpoints;
struct xarray regions;
struct cxl_dport *parent_dport;
struct ida decoder_ida;
struct cxl_register_map reg_map;
int nr_dports;
int hdm_end;
int commit_end;
bool dead;
unsigned int depth;
struct cxl_cdat {
void *table;
size_t length;
} cdat;
bool cdat_available;
long pci_latency;
};}hjA sbah }(h ]h ]h"]h$]h&]hhuh1j he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMGhjA ubj] )}(h **Members**h]j )}(hjA h]hMembers}(hjA hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjA ubah }(h ]h ]h"]h$]h&]uh1j\ he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhM_hjA ubjo )}(hhh](jt )}(h``dev``
this port's device
h](jz )}(h``dev``h]j )}(hjA h]hdev}(hjA hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjA ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMEhjA ubj )}(hhh]j] )}(hthis port's deviceh]hthis port’s device}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjB hMEhjB ubah }(h ]h ]h"]h$]h&]uh1j hjA ubeh }(h ]h ]h"]h$]h&]uh1js hjB hMEhjA ubjt )}(hO``uport_dev``
PCI or platform device implementing the upstream port capability
h](jz )}(h
``uport_dev``h]j )}(hj3B h]h uport_dev}(hj5B hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj1B ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMFhj-B ubj )}(hhh]j] )}(h@PCI or platform device implementing the upstream port capabilityh]h@PCI or platform device implementing the upstream port capability}(hjLB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjHB hMFhjIB ubah }(h ]h ]h"]h$]h&]uh1j hj-B ubeh }(h ]h ]h"]h$]h&]uh1js hjHB hMFhjA ubjt )}(hD``host_bridge``
Shortcut to the platform attach point for this port
h](jz )}(h``host_bridge``h]j )}(hjlB h]h host_bridge}(hjnB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjjB ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMGhjfB ubj )}(hhh]j] )}(h3Shortcut to the platform attach point for this porth]h3Shortcut to the platform attach point for this port}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjB hMGhjB ubah }(h ]h ]h"]h$]h&]uh1j hjfB ubeh }(h ]h ]h"]h$]h&]uh1js hjB hMGhjA ubjt )}(h ``id``
id for port device-name
h](jz )}(h``id``h]j )}(hjB h]hid}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjB ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMHhjB ubj )}(hhh]j] )}(hid for port device-nameh]hid for port device-name}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjB hMHhjB ubah }(h ]h ]h"]h$]h&]uh1j hjB ubeh }(h ]h ]h"]h$]h&]uh1js hjB hMHhjA ubjt )}(h6``dports``
cxl_dport instances referenced by decoders
h](jz )}(h
``dports``h]j )}(hjB h]hdports}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjB ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMIhjB ubj )}(hhh]j] )}(h*cxl_dport instances referenced by decodersh]h*cxl_dport instances referenced by decoders}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjB hMIhjB ubah }(h ]h ]h"]h$]h&]uh1j hjB ubeh }(h ]h ]h"]h$]h&]uh1js hjB hMIhjA ubjt )}(hM``endpoints``
cxl_ep instances, endpoints that are a descendant of this port
h](jz )}(h
``endpoints``h]j )}(hjC h]h endpoints}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjC ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMJhjC ubj )}(hhh]j] )}(h>cxl_ep instances, endpoints that are a descendant of this porth]h>cxl_ep instances, endpoints that are a descendant of this port}(hj0C hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj,C hMJhj-C ubah }(h ]h ]h"]h$]h&]uh1j hjC ubeh }(h ]h ]h"]h$]h&]uh1js hj,C hMJhjA ubjt )}(hB``regions``
cxl_region_ref instances, regions mapped by this port
h](jz )}(h ``regions``h]j )}(hjPC h]hregions}(hjRC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjNC ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMKhjJC ubj )}(hhh]j] )}(h5cxl_region_ref instances, regions mapped by this porth]h5cxl_region_ref instances, regions mapped by this port}(hjiC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjeC hMKhjfC ubah }(h ]h ]h"]h$]h&]uh1j hjJC ubeh }(h ]h ]h"]h$]h&]uh1js hjeC hMKhjA ubjt )}(h>``parent_dport``
dport that points to this port in the parent
h](jz )}(h``parent_dport``h]j )}(hjC h]h parent_dport}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjC ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMLhjC ubj )}(hhh]j] )}(h,dport that points to this port in the parenth]h,dport that points to this port in the parent}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjC hMLhjC ubah }(h ]h ]h"]h$]h&]uh1j hjC ubeh }(h ]h ]h"]h$]h&]uh1js hjC hMLhjA ubjt )}(h*``decoder_ida``
allocator for decoder ids
h](jz )}(h``decoder_ida``h]j )}(hjC h]h decoder_ida}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjC ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMMhjC ubj )}(hhh]j] )}(hallocator for decoder idsh]hallocator for decoder ids}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjC hMMhjC ubah }(h ]h ]h"]h$]h&]uh1j hjC ubeh }(h ]h ]h"]h$]h&]uh1js hjC hMMhjA ubjt )}(h:``reg_map``
component and ras register mapping parameters
h](jz )}(h ``reg_map``h]j )}(hjC h]hreg_map}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjC ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMNhjC ubj )}(hhh]j] )}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjD hMNhjD ubah }(h ]h ]h"]h$]h&]uh1j hjC ubeh }(h ]h ]h"]h$]h&]uh1js hjD hMNhjA ubjt )}(h.``nr_dports``
number of entries in **dports**
h](jz )}(h
``nr_dports``h]j )}(hj4D h]h nr_dports}(hj6D hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2D ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMOhj.D ubj )}(hhh]j] )}(h number of entries in **dports**h](hnumber of entries in }(hjMD hhhNhNubj )}(h
**dports**h]hdports}(hjUD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjMD ubeh }(h ]h ]h"]h$]h&]uh1j\ hjID hMOhjJD ubah }(h ]h ]h"]h$]h&]uh1j hj.D ubeh }(h ]h ]h"]h$]h&]uh1js hjID hMOhjA ubjt )}(hN``hdm_end``
track last allocated HDM decoder instance for allocation ordering
h](jz )}(h ``hdm_end``h]j )}(hj{D h]hhdm_end}(hj}D hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjyD ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMPhjuD ubj )}(hhh]j] )}(hAtrack last allocated HDM decoder instance for allocation orderingh]hAtrack last allocated HDM decoder instance for allocation ordering}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjD hMPhjD ubah }(h ]h ]h"]h$]h&]uh1j hjuD ubeh }(h ]h ]h"]h$]h&]uh1js hjD hMPhjA ubjt )}(hM``commit_end``
cursor to track highest committed decoder for commit ordering
h](jz )}(h``commit_end``h]j )}(hjD h]h
commit_end}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMQhjD ubj )}(hhh]j] )}(h=cursor to track highest committed decoder for commit orderingh]h=cursor to track highest committed decoder for commit ordering}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjD hMQhjD ubah }(h ]h ]h"]h$]h&]uh1j hjD ubeh }(h ]h ]h"]h$]h&]uh1js hjD hMQhjA ubjt )}(h:``dead``
last ep has been removed, force port re-creation
h](jz )}(h``dead``h]j )}(hjD h]hdead}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMRhjD ubj )}(hhh]j] )}(h0last ep has been removed, force port re-creationh]h0last ep has been removed, force port re-creation}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjE hMRhjE ubah }(h ]h ]h"]h$]h&]uh1j hjD ubeh }(h ]h ]h"]h$]h&]uh1js hjE hMRhjA ubjt )}(hK``depth``
How deep this port is relative to the root. depth 0 is the root.
h](jz )}(h ``depth``h]j )}(hj&E h]hdepth}(hj(E hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj$E ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMShj E ubj )}(hhh]j] )}(h@How deep this port is relative to the root. depth 0 is the root.h]h@How deep this port is relative to the root. depth 0 is the root.}(hj?E 8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj;E hMShjPCI bridge or firmware device representing the downstream linkh]h>PCI bridge or firmware device representing the downstream link}(hj5H hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj1H hMhj2H ubah }(h ]h ]h"]h$]h&]uh1j hjH ubeh }(h ]h ]h"]h$]h&]uh1js hj1H hMhjH ubjt )}(h:``reg_map``
component and ras register mapping parameters
h](jz )}(h ``reg_map``h]j )}(hjUH h]hreg_map}(hjWH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjSH ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjOH ubj )}(hhh]j] )}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjnH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjjH hMhjkH ubah }(h ]h ]h"]h$]h&]uh1j hjOH ubeh }(h ]h ]h"]h$]h&]uh1js hjjH hMhjH ubjt )}(hH``port_id``
unique hardware identifier for dport in decoder target list
h](jz )}(h ``port_id``h]j )}(hjH h]hport_id}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjH ubj )}(hhh]j] )}(h;unique hardware identifier for dport in decoder target listh]h;unique hardware identifier for dport in decoder target list}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjH hMhjH ubah }(h ]h ]h"]h$]h&]uh1j hjH ubeh }(h ]h ]h"]h$]h&]uh1js hjH hMhjH ubjt )}(h;``rcrb``
Data about the Root Complex Register Block layout
h](jz )}(h``rcrb``h]j )}(hjH h]hrcrb}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjH ubj )}(hhh]j] )}(h1Data about the Root Complex Register Block layouth]h1Data about the Root Complex Register Block layout}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjH hMhjH ubah }(h ]h ]h"]h$]h&]uh1j hjH ubeh }(h ]h ]h"]h$]h&]uh1js hjH hMhjH ubjt )}(hE``rch``
Indicate whether this dport was enumerated in RCH or VH mode
h](jz )}(h``rch``h]j )}(hj I h]hrch}(hjI hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH ubah }(h ]h ]h"]h$]h&]uh1jy he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:433: ./drivers/cxl/cxl.hhMhjH ubj )}(hhh]j] )}(hdpa_res** resource treeh](hTrack DPA ‘skip’ in }(hjdV hhhNhNubj )}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjlV hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjdV ubh resource tree}(hjdV hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM1hjaV hhubah }(h ]h ]h"]h$]h&]uh1j hjbT hhhj{T hM1ubeh }(h ]h ](j functioneh"]h$]h&]j j j jV j jV j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_dev_state *cxlds``
CXL.mem device context that parents **cxled**
``struct cxl_endpoint_decoder *cxled``
Endpoint decoder establishing new allocation that skips lower DPA
``const resource_size_t skip_base``
DPA < start of new DPA allocation (DPAnew)
``const resource_size_t skip_len``
**skip_base** + **skip_len** == DPAnew
**Description**
DPA 'skip' arises from out-of-sequence DPA allocation events relative
to free capacity across multiple partitions. It is a wasteful event
as usable DPA gets thrown away, but if a deployment has, for example,
a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM
DPA, the free RAM DPA must be sacrificed to start allocating PMEM.
See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder
Protection" for more details.
A 'skip' always covers the last allocated DPA in a previous partition
to the start of the current partition to allocate. Allocations never
start in the middle of a partition, and allocations are always
de-allocated in reverse order (see cxl_dpa_free(), or natural devm
unwind order from forced in-order allocation).
If **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip'
would always be contained to a single partition. Given
**cxlds->nr_partitions** may be > 2 it results in cases where the 'skip'
might span "tail capacity of partition[0], all of partition[1], ...,
all of partition[N-1]" to support allocating from partition[N]. That
in turn interacts with the partition 'struct resource' boundaries
within **cxlds->dpa_res** whereby 'skip' requests need to be divided by
partition. I.e. this is a quirk of using a 'struct resource' tree to
detect range conflicts while also tracking partition boundaries in
**cxlds->dpa_res**.h](j] )}(h**Parameters**h]j )}(hjV h]h
Parameters}(hjV hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM5hjV ubjo )}(hhh](jt )}(hN``struct cxl_dev_state *cxlds``
CXL.mem device context that parents **cxled**
h](jz )}(h ``struct cxl_dev_state *cxlds``h]j )}(hjV h]hstruct cxl_dev_state *cxlds}(hjV hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM2hjV ubj )}(hhh]j] )}(h-CXL.mem device context that parents **cxled**h](h$CXL.mem device context that parents }(hjV hhhNhNubj )}(h **cxled**h]hcxled}(hjV hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV ubeh }(h ]h ]h"]h$]h&]uh1j\ hjV hM2hjV ubah }(h ]h ]h"]h$]h&]uh1j hjV ubeh }(h ]h ]h"]h$]h&]uh1js hjV hM2hjV ubjt )}(hi``struct cxl_endpoint_decoder *cxled``
Endpoint decoder establishing new allocation that skips lower DPA
h](jz )}(h&``struct cxl_endpoint_decoder *cxled``h]j )}(hjV h]h"struct cxl_endpoint_decoder *cxled}(hj W hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM3hjV ubj )}(hhh]j] )}(hAEndpoint decoder establishing new allocation that skips lower DPAh]hAEndpoint decoder establishing new allocation that skips lower DPA}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjW hM3hjW ubah }(h ]h ]h"]h$]h&]uh1j hjV ubeh }(h ]h ]h"]h$]h&]uh1js hjW hM3hjV ubjt )}(hO``const resource_size_t skip_base``
DPA < start of new DPA allocation (DPAnew)
h](jz )}(h#``const resource_size_t skip_base``h]j )}(hj7W h]h const resource_size_t skip_base}(hj9W hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5W ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM4hj1W ubj )}(hhh]j] )}(h*DPA < start of new DPA allocation (DPAnew)h]h*DPA < start of new DPA allocation (DPAnew)}(hjPW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjLW hM4hjMW ubah }(h ]h ]h"]h$]h&]uh1j hj1W ubeh }(h ]h ]h"]h$]h&]uh1js hjLW hM4hjV ubjt )}(hJ``const resource_size_t skip_len``
**skip_base** + **skip_len** == DPAnew
h](jz )}(h"``const resource_size_t skip_len``h]j )}(hjpW h]h const resource_size_t skip_len}(hjrW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjnW ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM5hjjW ubj )}(hhh]j] )}(h&**skip_base** + **skip_len** == DPAnewh](j )}(h
**skip_base**h]h skip_base}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubh + }(hjW hhhNhNubj )}(h **skip_len**h]hskip_len}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubh
== DPAnew}(hjW hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hjW hM5hjW ubah }(h ]h ]h"]h$]h&]uh1j hjjW ubeh }(h ]h ]h"]h$]h&]uh1js hjW hM5hjV ubeh }(h ]h ]h"]h$]h&]uh1jn hjV ubj] )}(h**Description**h]j )}(hjW h]h Description}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM7hjV ubj] )}(hX DPA 'skip' arises from out-of-sequence DPA allocation events relative
to free capacity across multiple partitions. It is a wasteful event
as usable DPA gets thrown away, but if a deployment has, for example,
a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM
DPA, the free RAM DPA must be sacrificed to start allocating PMEM.
See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder
Protection" for more details.h]hX DPA ‘skip’ arises from out-of-sequence DPA allocation events relative
to free capacity across multiple partitions. It is a wasteful event
as usable DPA gets thrown away, but if a deployment has, for example,
a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM
DPA, the free RAM DPA must be sacrificed to start allocating PMEM.
See third “Implementation Note” in CXL 3.1 8.2.4.19.13 “Decoder
Protection” for more details.}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM6hjV ubj] )}(hX< A 'skip' always covers the last allocated DPA in a previous partition
to the start of the current partition to allocate. Allocations never
start in the middle of a partition, and allocations are always
de-allocated in reverse order (see cxl_dpa_free(), or natural devm
unwind order from forced in-order allocation).h]hX@ A ‘skip’ always covers the last allocated DPA in a previous partition
to the start of the current partition to allocate. Allocations never
start in the middle of a partition, and allocations are always
de-allocated in reverse order (see cxl_dpa_free(), or natural devm
unwind order from forced in-order allocation).}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chM>hjV ubj] )}(hXu If **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip'
would always be contained to a single partition. Given
**cxlds->nr_partitions** may be > 2 it results in cases where the 'skip'
might span "tail capacity of partition[0], all of partition[1], ...,
all of partition[N-1]" to support allocating from partition[N]. That
in turn interacts with the partition 'struct resource' boundaries
within **cxlds->dpa_res** whereby 'skip' requests need to be divided by
partition. I.e. this is a quirk of using a 'struct resource' tree to
detect range conflicts while also tracking partition boundaries in
**cxlds->dpa_res**. h](hIf }(hjW hhhNhNubj )}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjX hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubhf was guaranteed to be <= 2 then the ‘skip’
would always be contained to a single partition. Given
}(hjW hhhNhNubj )}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjX hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubhX may be > 2 it results in cases where the ‘skip’
might span “tail capacity of partition[0], all of partition[1], ...,
all of partition[N-1]” to support allocating from partition[N]. That
in turn interacts with the partition ‘struct resource’ boundaries
within }(hjW hhhNhNubj )}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hj+X hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubh whereby ‘skip’ requests need to be divided by
partition. I.e. this is a quirk of using a ‘struct resource’ tree to
detect range conflicts while also tracking partition boundaries in
}(hjW hhhNhNubj )}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hj=X hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubh.}(hjW hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMDhjV ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j (devm_cxl_enumerate_decoders (C function) c.devm_cxl_enumerate_decodershNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h^int devm_cxl_enumerate_decoders (struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j. )}(h]int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j4 )}(hinth]hint}(hjvX hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjrX hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMubjF )}(h h]h }(hjX hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjrX hhhjX hMubjW )}(hdevm_cxl_enumerate_decodersh]j] )}(hdevm_cxl_enumerate_decodersh]hdevm_cxl_enumerate_decoders}(hjX hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjX ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjrX hhhjX hMubjv )}(h>(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j| )}(hstruct cxl_hdm *cxlhdmh](j )}(hj h]hstruct}(hjX hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjX ubjF )}(h h]h }(hjX hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjX ubh)}(hhh]j] )}(hcxl_hdmh]hcxl_hdm}(hjX hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjX ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjX modnameN classnameNj j )}j ]j )}j jX sb c.devm_cxl_enumerate_decodersasbuh1hhjX ubjF )}(h h]h }(hjX hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjX ubj )}(hj h]h*}(hjX hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjX ubj] )}(hcxlhdmh]hcxlhdm}(hj Y hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjX ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjX ubj| )}(h$struct cxl_endpoint_dvsec_info *infoh](j )}(hj h]hstruct}(hj%Y hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj!Y ubjF )}(h h]h }(hj2Y hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj!Y ubh)}(hhh]j] )}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjCY hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj@Y ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjEY modnameN classnameNj j )}j ]jX c.devm_cxl_enumerate_decodersasbuh1hhj!Y ubjF )}(h h]h }(hjaY hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj!Y ubj )}(hj h]h*}(hjoY hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj!Y ubj] )}(hinfoh]hinfo}(hj|Y hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj!Y ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjX ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjrX hhhjX hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjnX hhhjX hMubah }(h ]jiX ah ](j j eh"]h$]h&]j j )j huh1j' hjX hMhjkX hhubj )}(hhh]j] )}(h(add decoder objects per HDM register seth]h(add decoder objects per HDM register set}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjY hhubah }(h ]h ]h"]h$]h&]uh1j hjkX hhhjX hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jY j jY j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_hdm *cxlhdm``
Structure to populate with HDM capabilities
``struct cxl_endpoint_dvsec_info *info``
cached DVSEC range register infoh](j] )}(h**Parameters**h]j )}(hjY h]h
Parameters}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjY ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjY ubjo )}(hhh](jt )}(hG``struct cxl_hdm *cxlhdm``
Structure to populate with HDM capabilities
h](jz )}(h``struct cxl_hdm *cxlhdm``h]j )}(hjY h]hstruct cxl_hdm *cxlhdm}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjY ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjY ubj )}(hhh]j] )}(h+Structure to populate with HDM capabilitiesh]h+Structure to populate with HDM capabilities}(hj Z hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjY hMhjY ubah }(h ]h ]h"]h$]h&]uh1j hjY ubeh }(h ]h ]h"]h$]h&]uh1js hjY hMhjY ubjt )}(hI``struct cxl_endpoint_dvsec_info *info``
cached DVSEC range register infoh](jz )}(h(``struct cxl_endpoint_dvsec_info *info``h]j )}(hj Z h]h$struct cxl_endpoint_dvsec_info *info}(hj"Z hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj Z ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhjZ ubj )}(hhh]j] )}(h cached DVSEC range register infoh]h cached DVSEC range register info}(hj9Z hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:442: ./drivers/cxl/core/hdm.chMhj6Z ubah }(h ]h ]h"]h$]h&]uh1j hjZ ubeh }(h ]h ]h"]h$]h&]uh1js hj5Z hMhjY ubeh }(h ]h ]h"]h$]h&]uh1jn hjY ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j $cxl_coordinates_combine (C function)c.cxl_coordinates_combinehNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hxvoid cxl_coordinates_combine (struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h]j. )}(hwvoid cxl_coordinates_combine(struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h](j4 )}(hvoidh]hvoid}(hjzZ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjvZ hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM"ubjF )}(h h]h }(hjZ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjvZ hhhjZ hM"ubjW )}(hcxl_coordinates_combineh]j] )}(hcxl_coordinates_combineh]hcxl_coordinates_combine}(hjZ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjZ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjvZ hhhjZ hM"ubjv )}(h[(struct access_coordinate *out, struct access_coordinate *c1, struct access_coordinate *c2)h](j| )}(h struct access_coordinate *outh](j )}(hj h]hstruct}(hjZ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjZ ubjF )}(h h]h }(hjZ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjZ ubh)}(hhh]j] )}(haccess_coordinateh]haccess_coordinate}(hjZ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjZ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjZ modnameN classnameNj j )}j ]j )}j jZ sbc.cxl_coordinates_combineasbuh1hhjZ ubjF )}(h h]h }(hjZ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjZ ubj )}(hj h]h*}(hj[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjZ ubj] )}(houth]hout}(hj[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjZ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjZ ubj| )}(h struct access_coordinate *c1h](j )}(hj h]hstruct}(hj)[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj%[ ubjF )}(h h]h }(hj6[ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj%[ ubh)}(hhh]j] )}(haccess_coordinateh]haccess_coordinate}(hjG[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjD[ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjI[ modnameN classnameNj j )}j ]jZ c.cxl_coordinates_combineasbuh1hhj%[ ubjF )}(h h]h }(hje[ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj%[ ubj )}(hj h]h*}(hjs[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj%[ ubj] )}(hc1h]hc1}(hj[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj%[ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjZ ubj| )}(h struct access_coordinate *c2h](j )}(hj h]hstruct}(hj[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[ ubjF )}(h h]h }(hj[ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[ ubh)}(hhh]j] )}(haccess_coordinateh]haccess_coordinate}(hj[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj[ modnameN classnameNj j )}j ]jZ c.cxl_coordinates_combineasbuh1hhj[ ubjF )}(h h]h }(hj[ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[ ubj )}(hj h]h*}(hj[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[ ubj] )}(hc2h]hc2}(hj[ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjZ ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjvZ hhhjZ hM"ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjrZ hhhjZ hM"ubah }(h ]jmZ ah ](j j eh"]h$]h&]j j )j huh1j' hjZ hM"hjoZ hhubj )}(hhh]j] )}(h!Combine the two input coordinatesh]h!Combine the two input coordinates}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM"hj\ hhubah }(h ]h ]h"]h$]h&]uh1j hjoZ hhhjZ hM"ubeh }(h ]h ](j functioneh"]h$]h&]j j j j2\ j j2\ j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct access_coordinate *out``
Output coordinate of c1 and c2 combined
``struct access_coordinate *c1``
input coordinates
``struct access_coordinate *c2``
input coordinatesh](j] )}(h**Parameters**h]j )}(hj<\ h]h
Parameters}(hj>\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj:\ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM&hj6\ ubjo )}(hhh](jt )}(hJ``struct access_coordinate *out``
Output coordinate of c1 and c2 combined
h](jz )}(h!``struct access_coordinate *out``h]j )}(hj[\ h]h struct access_coordinate *out}(hj]\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjY\ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM$hjU\ ubj )}(hhh]j] )}(h'Output coordinate of c1 and c2 combinedh]h'Output coordinate of c1 and c2 combined}(hjt\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjp\ hM$hjq\ ubah }(h ]h ]h"]h$]h&]uh1j hjU\ ubeh }(h ]h ]h"]h$]h&]uh1js hjp\ hM$hjR\ ubjt )}(h3``struct access_coordinate *c1``
input coordinates
h](jz )}(h ``struct access_coordinate *c1``h]j )}(hj\ h]h struct access_coordinate *c1}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj\ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM%hj\ ubj )}(hhh]j] )}(hinput coordinatesh]hinput coordinates}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj\ hM%hj\ ubah }(h ]h ]h"]h$]h&]uh1j hj\ ubeh }(h ]h ]h"]h$]h&]uh1js hj\ hM%hjR\ ubjt )}(h2``struct access_coordinate *c2``
input coordinatesh](jz )}(h ``struct access_coordinate *c2``h]j )}(hj\ h]h struct access_coordinate *c2}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj\ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM'hj\ ubj )}(hhh]j] )}(hinput coordinatesh]hinput coordinates}(hj\ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM&hj\ ubah }(h ]h ]h"]h$]h&]uh1j hj\ ubeh }(h ]h ]h"]h$]h&]uh1js hj\ hM'hjR\ ubeh }(h ]h ]h"]h$]h&]uh1jn hj6\ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j *cxl_endpoint_gather_bandwidth (C function) c.cxl_endpoint_gather_bandwidthhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hint cxl_endpoint_gather_bandwidth (struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h]j. )}(hint cxl_endpoint_gather_bandwidth(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j4 )}(hinth]hint}(hj'] hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj#] hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMfubjF )}(h h]h }(hj6] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj#] hhhj5] hMfubjW )}(h cxl_endpoint_gather_bandwidthh]j] )}(h cxl_endpoint_gather_bandwidthh]h cxl_endpoint_gather_bandwidth}(hjH] hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjD] ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj#] hhhj5] hMfubjv )}(hf(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hjd] hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj`] ubjF )}(h h]h }(hjq] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj`] ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj] hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj] ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj] modnameN classnameNj j )}j ]j )}j jJ] sb c.cxl_endpoint_gather_bandwidthasbuh1hhj`] ubjF )}(h h]h }(hj] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj`] ubj )}(hj h]h*}(hj] hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj`] ubj] )}(hcxlrh]hcxlr}(hj] hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj`] ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj\] ubj| )}(h"struct cxl_endpoint_decoder *cxledh](j )}(hj h]hstruct}(hj] hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj] ubjF )}(h h]h }(hj] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj] ubh)}(hhh]j] )}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj] hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj] ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj] modnameN classnameNj j )}j ]j] c.cxl_endpoint_gather_bandwidthasbuh1hhj] ubjF )}(h h]h }(hj^ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj] ubj )}(hj h]h*}(hj ^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj] ubj] )}(hcxledh]hcxled}(hj-^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj] ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj\] ubj| )}(hstruct xarray *usp_xah](j )}(hj h]hstruct}(hjF^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjB^ ubjF )}(h h]h }(hjS^ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjB^ ubh)}(hhh]j] )}(hxarrayh]hxarray}(hjd^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hja^ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjf^ modnameN classnameNj j )}j ]j] c.cxl_endpoint_gather_bandwidthasbuh1hhjB^ ubjF )}(h h]h }(hj^ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjB^ ubj )}(hj h]h*}(hj^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjB^ ubj] )}(husp_xah]husp_xa}(hj^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjB^ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj\] ubj| )}(hbool *gp_is_rooth](j4 )}(hboolh]hbool}(hj^ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj^ ubjF )}(h h]h }(hj^ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj^ ubj )}(hj h]h*}(hj^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj^ ubj] )}(h
gp_is_rooth]h
gp_is_root}(hj^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj^ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj\] ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj#] hhhj5] hMfubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj ] hhhj5] hMfubah }(h ]j] ah ](j j eh"]h$]h&]j j )j huh1j' hj5] hMfhj ] hhubj )}(hhh]j] )}(h/collect all the endpoint bandwidth in an xarrayh]h/collect all the endpoint bandwidth in an xarray}(hj _ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMfhj_ hhubah }(h ]h ]h"]h$]h&]uh1j hj ] hhhj5] hMfubeh }(h ]h ](j functioneh"]h$]h&]j j j j!_ j j!_ j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_region *cxlr``
CXL region for the bandwidth calculation
``struct cxl_endpoint_decoder *cxled``
endpoint decoder to start on
``struct xarray *usp_xa``
(output) the xarray that collects all the bandwidth coordinates
indexed by the upstream device with data of 'struct cxl_perf_ctx'.
``bool *gp_is_root``
(output) bool of whether the grandparent is cxl root.
**Return**
0 for success or -errno
**Description**
Collects aggregated endpoint bandwidth and store the bandwidth in
an xarray indexed by the upstream device of the switch or the RP
device. Each endpoint consists the minimum of the bandwidth from DSLBIS
from the endpoint CDAT, the endpoint upstream link bandwidth, and the
bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to
the downstream port that's associated with the endpoint. If the
device is directly connected to a RP, then no SSLBIS is involved.h](j] )}(h**Parameters**h]j )}(hj+_ h]h
Parameters}(hj-_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj)_ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMjhj%_ ubjo )}(hhh](jt )}(hE``struct cxl_region *cxlr``
CXL region for the bandwidth calculation
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hjJ_ h]hstruct cxl_region *cxlr}(hjL_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH_ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMghjD_ ubj )}(hhh]j] )}(h(CXL region for the bandwidth calculationh]h(CXL region for the bandwidth calculation}(hjc_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj__ hMghj`_ ubah }(h ]h ]h"]h$]h&]uh1j hjD_ ubeh }(h ]h ]h"]h$]h&]uh1js hj__ hMghjA_ ubjt )}(hD``struct cxl_endpoint_decoder *cxled``
endpoint decoder to start on
h](jz )}(h&``struct cxl_endpoint_decoder *cxled``h]j )}(hj_ h]h"struct cxl_endpoint_decoder *cxled}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj_ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhhj}_ ubj )}(hhh]j] )}(h endpoint decoder to start onh]h endpoint decoder to start on}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj_ hMhhj_ ubah }(h ]h ]h"]h$]h&]uh1j hj}_ ubeh }(h ]h ]h"]h$]h&]uh1js hj_ hMhhjA_ ubjt )}(h``struct xarray *usp_xa``
(output) the xarray that collects all the bandwidth coordinates
indexed by the upstream device with data of 'struct cxl_perf_ctx'.
h](jz )}(h``struct xarray *usp_xa``h]j )}(hj_ h]hstruct xarray *usp_xa}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj_ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMjhj_ ubj )}(hhh]j] )}(h(output) the xarray that collects all the bandwidth coordinates
indexed by the upstream device with data of 'struct cxl_perf_ctx'.h]h(output) the xarray that collects all the bandwidth coordinates
indexed by the upstream device with data of ‘struct cxl_perf_ctx’.}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMihj_ ubah }(h ]h ]h"]h$]h&]uh1j hj_ ubeh }(h ]h ]h"]h$]h&]uh1js hj_ hMjhjA_ ubjt )}(hK``bool *gp_is_root``
(output) bool of whether the grandparent is cxl root.
h](jz )}(h``bool *gp_is_root``h]j )}(hj_ h]hbool *gp_is_root}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj_ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMkhj_ ubj )}(hhh]j] )}(h5(output) bool of whether the grandparent is cxl root.h]h5(output) bool of whether the grandparent is cxl root.}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj ` hMkhj ` ubah }(h ]h ]h"]h$]h&]uh1j hj_ ubeh }(h ]h ]h"]h$]h&]uh1js hj ` hMkhjA_ ubeh }(h ]h ]h"]h$]h&]uh1jn hj%_ ubj] )}(h
**Return**h]j )}(hj1` h]hReturn}(hj3` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj/` ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMmhj%_ ubj] )}(h0 for success or -errnoh]h0 for success or -errno}(hjG` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMmhj%_ ubj] )}(h**Description**h]j )}(hjX` h]h Description}(hjZ` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjV` ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMohj%_ ubj] )}(hX Collects aggregated endpoint bandwidth and store the bandwidth in
an xarray indexed by the upstream device of the switch or the RP
device. Each endpoint consists the minimum of the bandwidth from DSLBIS
from the endpoint CDAT, the endpoint upstream link bandwidth, and the
bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to
the downstream port that's associated with the endpoint. If the
device is directly connected to a RP, then no SSLBIS is involved.h]hX Collects aggregated endpoint bandwidth and store the bandwidth in
an xarray indexed by the upstream device of the switch or the RP
device. Each endpoint consists the minimum of the bandwidth from DSLBIS
from the endpoint CDAT, the endpoint upstream link bandwidth, and the
bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to
the downstream port that’s associated with the endpoint. If the
device is directly connected to a RP, then no SSLBIS is involved.}(hjn` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMnhj%_ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j (cxl_switch_gather_bandwidth (C function) c.cxl_switch_gather_bandwidthhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hpstruct xarray * cxl_switch_gather_bandwidth (struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h]j. )}(hnstruct xarray *cxl_switch_gather_bandwidth(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j )}(hj h]hstruct}(hj` hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj` hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMubjF )}(h h]h }(hj` hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj` hhhj` hMubh)}(hhh]j] )}(hxarrayh]hxarray}(hj` hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj` ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj` modnameN classnameNj j )}j ]j )}j cxl_switch_gather_bandwidthsb c.cxl_switch_gather_bandwidthasbuh1hhj` hhhj` hMubjF )}(h h]h }(hj` hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj` hhhj` hMubj )}(hj h]h*}(hj` hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj` hhhj` hMubjW )}(hcxl_switch_gather_bandwidthh]j] )}(hj` h]hcxl_switch_gather_bandwidth}(hj` hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj` ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj` hhhj` hMubjv )}(hD(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hja hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hja ubjF )}(h h]h }(hj$a hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj5a hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj2a ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj7a modnameN classnameNj j )}j ]j` c.cxl_switch_gather_bandwidthasbuh1hhja ubjF )}(h h]h }(hjSa hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja ubj )}(hj h]h*}(hjaa hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hja ubj] )}(hcxlrh]hcxlr}(hjna hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hja ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hja ubj| )}(hstruct xarray *input_xah](j )}(hj h]hstruct}(hja hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hja ubjF )}(h h]h }(hja hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja ubh)}(hhh]j] )}(hxarrayh]hxarray}(hja hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hja ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetja modnameN classnameNj j )}j ]j` c.cxl_switch_gather_bandwidthasbuh1hhja ubjF )}(h h]h }(hja hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja ubj )}(hj h]h*}(hja hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hja ubj] )}(hinput_xah]hinput_xa}(hja hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hja ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hja ubj| )}(hbool *gp_is_rooth](j4 )}(hj^ h]hbool}(hja hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hja ubjF )}(h h]h }(hjb hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja ubj )}(hj h]h*}(hjb hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hja ubj] )}(h
gp_is_rooth]h
gp_is_root}(hj b hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hja ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hja ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj` hhhj` hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj` hhhj` hMubah }(h ]j` ah ](j j eh"]h$]h&]j j )j huh1j' hj` hMhj` hhubj )}(hhh]j] )}(h6collect all the bandwidth at switch level in an xarrayh]h6collect all the bandwidth at switch level in an xarray}(hjIb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjFb hhubah }(h ]h ]h"]h$]h&]uh1j hj` hhhj` hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jab j jab j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_region *cxlr``
The region being operated on
``struct xarray *input_xa``
xarray indexed by upstream device of a switch with data of 'struct
cxl_perf_ctx'
``bool *gp_is_root``
(output) bool of whether the grandparent is cxl root.
**Return**
a xarray of resulting cxl_perf_ctx per parent switch or root port
or ERR_PTR(-errno)
**Description**
Iterate through the xarray. Take the minimum of the downstream calculated
bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream
switch if exists. Sum the resulting bandwidth under the switch upstream
device or a RP device. The function can be iterated over multiple switches
if the switches are present.h](j] )}(h**Parameters**h]j )}(hjkb h]h
Parameters}(hjmb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjib ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjeb ubjo )}(hhh](jt )}(h9``struct cxl_region *cxlr``
The region being operated on
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hjb h]hstruct cxl_region *cxlr}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjb ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjb ubj )}(hhh]j] )}(h The region being operated onh]h The region being operated on}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjb hMhjb ubah }(h ]h ]h"]h$]h&]uh1j hjb ubeh }(h ]h ]h"]h$]h&]uh1js hjb hMhjb ubjt )}(hm``struct xarray *input_xa``
xarray indexed by upstream device of a switch with data of 'struct
cxl_perf_ctx'
h](jz )}(h``struct xarray *input_xa``h]j )}(hjb h]hstruct xarray *input_xa}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjb ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjb ubj )}(hhh]j] )}(hPxarray indexed by upstream device of a switch with data of 'struct
cxl_perf_ctx'h]hTxarray indexed by upstream device of a switch with data of ‘struct
cxl_perf_ctx’}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjb ubah }(h ]h ]h"]h$]h&]uh1j hjb ubeh }(h ]h ]h"]h$]h&]uh1js hjb hMhjb ubjt )}(hK``bool *gp_is_root``
(output) bool of whether the grandparent is cxl root.
h](jz )}(h``bool *gp_is_root``h]j )}(hjb h]hbool *gp_is_root}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjb ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjb ubj )}(hhh]j] )}(h5(output) bool of whether the grandparent is cxl root.h]h5(output) bool of whether the grandparent is cxl root.}(hjc hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjc hMhjc ubah }(h ]h ]h"]h$]h&]uh1j hjb ubeh }(h ]h ]h"]h$]h&]uh1js hjc hMhjb ubeh }(h ]h ]h"]h$]h&]uh1jn hjeb ubj] )}(h
**Return**h]j )}(hj8c h]hReturn}(hj:c hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj6c ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjeb ubj] )}(hTa xarray of resulting cxl_perf_ctx per parent switch or root port
or ERR_PTR(-errno)h]hTa xarray of resulting cxl_perf_ctx per parent switch or root port
or ERR_PTR(-errno)}(hjNc hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjeb ubj] )}(h**Description**h]j )}(hj_c h]h Description}(hjac hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj]c ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjeb ubj] )}(hX@ Iterate through the xarray. Take the minimum of the downstream calculated
bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream
switch if exists. Sum the resulting bandwidth under the switch upstream
device or a RP device. The function can be iterated over multiple switches
if the switches are present.h]hX@ Iterate through the xarray. Take the minimum of the downstream calculated
bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream
switch if exists. Sum the resulting bandwidth under the switch upstream
device or a RP device. The function can be iterated over multiple switches
if the switches are present.}(hjuc hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjeb ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j $cxl_rp_gather_bandwidth (C function)c.cxl_rp_gather_bandwidthhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h;struct xarray * cxl_rp_gather_bandwidth (struct xarray *xa)h]j. )}(h9struct xarray *cxl_rp_gather_bandwidth(struct xarray *xa)h](j )}(hj h]hstruct}(hjc hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjc hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM[ubjF )}(h h]h }(hjc hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc hhhjc hM[ubh)}(hhh]j] )}(hxarrayh]hxarray}(hjc hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjc ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjc modnameN classnameNj j )}j ]j )}j cxl_rp_gather_bandwidthsbc.cxl_rp_gather_bandwidthasbuh1hhjc hhhjc hM[ubjF )}(h h]h }(hjc hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc hhhjc hM[ubj )}(hj h]h*}(hjc hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjc hhhjc hM[ubjW )}(hcxl_rp_gather_bandwidthh]j] )}(hjc h]hcxl_rp_gather_bandwidth}(hjd hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjc ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjc hhhjc hM[ubjv )}(h(struct xarray *xa)h]j| )}(hstruct xarray *xah](j )}(hj h]hstruct}(hj d hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjd ubjF )}(h h]h }(hj+d hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjd ubh)}(hhh]j] )}(hxarrayh]hxarray}(hjd modnameN classnameNj j )}j ]jc c.cxl_rp_gather_bandwidthasbuh1hhjd ubjF )}(h h]h }(hjZd hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjd ubj )}(hj h]h*}(hjhd hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjd ubj] )}(hxah]hxa}(hjud hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjd ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjd ubah }(h ]h ]h"]h$]h&]hhuh1ju hjc hhhjc hM[ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjc hhhjc hM[ubah }(h ]jc ah ](j j eh"]h$]h&]j j )j huh1j' hjc hM[hjc hhubj )}(hhh]j] )}(h/handle the root port level bandwidth collectionh]h/handle the root port level bandwidth collection}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM[hjd hhubah }(h ]h ]h"]h$]h&]uh1j hjc hhhjc hM[ubeh }(h ]h ](j functioneh"]h$]h&]j j j jd j jd j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct xarray *xa``
the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each root port device.
**Return**
xarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)h](j] )}(h**Parameters**h]j )}(hjd h]h
Parameters}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjd ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM_hjd ubjo )}(hhh]jt )}(h|``struct xarray *xa``
the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each root port device.
h](jz )}(h``struct xarray *xa``h]j )}(hjd h]hstruct xarray *xa}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjd ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM]hjd ubj )}(hhh]j] )}(hethe xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each root port device.h]hethe xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each root port device.}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM\hjd ubah }(h ]h ]h"]h$]h&]uh1j hjd ubeh }(h ]h ]h"]h$]h&]uh1js hjd hM]hjd ubah }(h ]h ]h"]h$]h&]uh1jn hjd ubj] )}(h
**Return**h]j )}(hj e h]hReturn}(hj e hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hje ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM_hjd ubj] )}(hAxarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)h]hAxarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)}(hj2e hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chM_hjd ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j $cxl_hb_gather_bandwidth (C function)c.cxl_hb_gather_bandwidthhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h;struct xarray * cxl_hb_gather_bandwidth (struct xarray *xa)h]j. )}(h9struct xarray *cxl_hb_gather_bandwidth(struct xarray *xa)h](j )}(hj h]hstruct}(hjae hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj]e hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMubjF )}(h h]h }(hjoe hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj]e hhhjne hMubh)}(hhh]j] )}(hxarrayh]hxarray}(hje hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj}e ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetje modnameN classnameNj j )}j ]j )}j cxl_hb_gather_bandwidthsbc.cxl_hb_gather_bandwidthasbuh1hhj]e hhhjne hMubjF )}(h h]h }(hje hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj]e hhhjne hMubj )}(hj h]h*}(hje hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj]e hhhjne hMubjW )}(hcxl_hb_gather_bandwidthh]j] )}(hje h]hcxl_hb_gather_bandwidth}(hje hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hje ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj]e hhhjne hMubjv )}(h(struct xarray *xa)h]j| )}(hstruct xarray *xah](j )}(hj h]hstruct}(hje hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hje ubjF )}(h h]h }(hje hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hje ubh)}(hhh]j] )}(hxarrayh]hxarray}(hje hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hje ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetje modnameN classnameNj j )}j ]je c.cxl_hb_gather_bandwidthasbuh1hhje ubjF )}(h h]h }(hjf hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hje ubj )}(hj h]h*}(hj%f hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hje ubj] )}(hxah]hxa}(hj2f hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hje ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hje ubah }(h ]h ]h"]h$]h&]hhuh1ju hj]e hhhjne hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjYe hhhjne hMubah }(h ]jTe ah ](j j eh"]h$]h&]j j )j huh1j' hjne hMhjVe hhubj )}(hhh]j] )}(h1handle the host bridge level bandwidth collectionh]h1handle the host bridge level bandwidth collection}(hj\f hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjYf hhubah }(h ]h ]h"]h$]h&]uh1j hjVe hhhjne hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jtf j jtf j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct xarray *xa``
the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each host bridge.
**Return**
xarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)h](j] )}(h**Parameters**h]j )}(hj~f h]h
Parameters}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj|f ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjxf ubjo )}(hhh]jt )}(hw``struct xarray *xa``
the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each host bridge.
h](jz )}(h``struct xarray *xa``h]j )}(hjf h]hstruct xarray *xa}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjf ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjf ubj )}(hhh]j] )}(h`the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each host bridge.h]h`the xarray that holds the cxl_perf_ctx that has the bandwidth calculated
below each host bridge.}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjf ubah }(h ]h ]h"]h$]h&]uh1j hjf ubeh }(h ]h ]h"]h$]h&]uh1js hjf hMhjf ubah }(h ]h ]h"]h$]h&]uh1jn hjxf ubj] )}(h
**Return**h]j )}(hjf h]hReturn}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjf ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjxf ubj] )}(hExarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)h]hExarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjxf ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j (cxl_region_update_bandwidth (C function) c.cxl_region_update_bandwidthhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hSvoid cxl_region_update_bandwidth (struct cxl_region *cxlr, struct xarray *input_xa)h]j. )}(hRvoid cxl_region_update_bandwidth(struct cxl_region *cxlr, struct xarray *input_xa)h](j4 )}(hvoidh]hvoid}(hj g hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjg hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMubjF )}(h h]h }(hj-g hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjg hhhj,g hMubjW )}(hcxl_region_update_bandwidthh]j] )}(hcxl_region_update_bandwidthh]hcxl_region_update_bandwidth}(hj?g hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj;g ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjg hhhj,g hMubjv )}(h2(struct cxl_region *cxlr, struct xarray *input_xa)h](j| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hj[g hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjWg ubjF )}(h h]h }(hjhg hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjWg ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hjyg hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjvg ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj{g modnameN classnameNj j )}j ]j )}j jAg sb c.cxl_region_update_bandwidthasbuh1hhjWg ubjF )}(h h]h }(hjg hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjWg ubj )}(hj h]h*}(hjg hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjWg ubj] )}(hcxlrh]hcxlr}(hjg hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjWg ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjSg ubj| )}(hstruct xarray *input_xah](j )}(hj h]hstruct}(hjg hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjg ubjF )}(h h]h }(hjg hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjg ubh)}(hhh]j] )}(hxarrayh]hxarray}(hjg hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjg ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjg modnameN classnameNj j )}j ]jg c.cxl_region_update_bandwidthasbuh1hhjg ubjF )}(h h]h }(hj h hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjg ubj )}(hj h]h*}(hjh hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjg ubj] )}(hinput_xah]hinput_xa}(hj$h hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjg ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjSg ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjg hhhj,g hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjg hhhj,g hMubah }(h ]jg ah ](j j eh"]h$]h&]j j )j huh1j' hj,g hMhjg hhubj )}(hhh]j] )}(h3Update the bandwidth access coordinates of a regionh]h3Update the bandwidth access coordinates of a region}(hjNh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjKh hhubah }(h ]h ]h"]h$]h&]uh1j hjg hhhj,g hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jfh j jfh j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_region *cxlr``
The region being operated on
``struct xarray *input_xa``
xarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh](j] )}(h**Parameters**h]j )}(hjph h]h
Parameters}(hjrh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjnh ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjjh ubjo )}(hhh](jt )}(h9``struct cxl_region *cxlr``
The region being operated on
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hjh h]hstruct cxl_region *cxlr}(hjh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjh ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjh ubj )}(hhh]j] )}(h The region being operated onh]h The region being operated on}(hjh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjh hMhjh ubah }(h ]h ]h"]h$]h&]uh1j hjh ubeh }(h ]h ]h"]h$]h&]uh1js hjh hMhjh ubjt )}(hd``struct xarray *input_xa``
xarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh](jz )}(h``struct xarray *input_xa``h]j )}(hjh h]hstruct xarray *input_xa}(hjh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjh ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjh ubj )}(hhh]j] )}(hHxarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh]hHxarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instance}(hjh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhjh ubah }(h ]h ]h"]h$]h&]uh1j hjh ubeh }(h ]h ]h"]h$]h&]uh1js hjh hMhjh ubeh }(h ]h ]h"]h$]h&]uh1jn hjjh ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 8cxl_region_shared_upstream_bandwidth_update (C function)-c.cxl_region_shared_upstream_bandwidth_updatehNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hJvoid cxl_region_shared_upstream_bandwidth_update (struct cxl_region *cxlr)h]j. )}(hIvoid cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr)h](j4 )}(hvoidh]hvoid}(hj"i hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj i hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMubjF )}(h h]h }(hj1i hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj i hhhj0i hMubjW )}(h+cxl_region_shared_upstream_bandwidth_updateh]j] )}(h+cxl_region_shared_upstream_bandwidth_updateh]h+cxl_region_shared_upstream_bandwidth_update}(hjCi hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj?i ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj i hhhj0i hMubjv )}(h(struct cxl_region *cxlr)h]j| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hj_i hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[i ubjF )}(h h]h }(hjli hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[i ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj}i hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjzi ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetji modnameN classnameNj j )}j ]j )}j jEi sb-c.cxl_region_shared_upstream_bandwidth_updateasbuh1hhj[i ubjF )}(h h]h }(hji hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[i ubj )}(hj h]h*}(hji hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[i ubj] )}(hcxlrh]hcxlr}(hji hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[i ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjWi ubah }(h ]h ]h"]h$]h&]hhuh1ju hj i hhhj0i hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hji hhhj0i hMubah }(h ]ji ah ](j j eh"]h$]h&]j j )j huh1j' hj0i hMhji hhubj )}(hhh]j] )}(h(Recalculate the bandwidth for the regionh]h(Recalculate the bandwidth for the region}(hji hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhji hhubah }(h ]h ]h"]h$]h&]uh1j hji hhhj0i hMubeh }(h ]h ](j functioneh"]h$]h&]j j j ji j ji j j j uh1j" hhhju. hNhNubj )}(hXI **Parameters**
``struct cxl_region *cxlr``
the cxl region to recalculate
**Description**
The function walks the topology from bottom up and calculates the bandwidth. It
starts at the endpoints, processes at the switches if any, processes at the rootport
level, at the host bridge level, and finally aggregates at the region.h](j] )}(h**Parameters**h]j )}(hjj h]h
Parameters}(hjj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhji ubjo )}(hhh]jt )}(h:``struct cxl_region *cxlr``
the cxl region to recalculate
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hj#j h]hstruct cxl_region *cxlr}(hj%j hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj!j ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:445: ./drivers/cxl/core/cdat.chMhj j ubj )}(hhh]j] )}(h the cxl region to recalculateh]h the cxl region to recalculate}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj:m hMhj;m ubah }(h ]h ]h"]h$]h&]uh1j hj m ubeh }(h ]h ]h"]h$]h&]uh1js hj:m hMhj m ubjt )}(hO``struct device *uport_dev``
"physical" device implementing this upstream port
h](jz )}(h ``struct device *uport_dev``h]j )}(hj^m h]hstruct device *uport_dev}(hj`m hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj\m ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjXm ubj )}(hhh]j] )}(h1"physical" device implementing this upstream porth]h5“physical” device implementing this upstream port}(hjwm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjsm hMhjtm ubah }(h ]h ]h"]h$]h&]uh1j hjXm ubeh }(h ]h ]h"]h$]h&]uh1js hjsm hMhj m ubjt )}(hV``resource_size_t component_reg_phys``
(optional) for configurable cxl_port instances
h](jz )}(h&``resource_size_t component_reg_phys``h]j )}(hjm h]h"resource_size_t component_reg_phys}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjm ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjm ubj )}(hhh]j] )}(h.(optional) for configurable cxl_port instancesh]h.(optional) for configurable cxl_port instances}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjm hMhjm ubah }(h ]h ]h"]h$]h&]uh1j hjm ubeh }(h ]h ]h"]h$]h&]uh1js hjm hMhj m ubjt )}(hQ``struct cxl_dport *parent_dport``
next hop up in the CXL memory decode hierarchyh](jz )}(h"``struct cxl_dport *parent_dport``h]j )}(hjm h]h struct cxl_dport *parent_dport}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjm ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjm ubj )}(hhh]j] )}(h.next hop up in the CXL memory decode hierarchyh]h.next hop up in the CXL memory decode hierarchy}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjm ubah }(h ]h ]h"]h$]h&]uh1j hjm ubeh }(h ]h ]h"]h$]h&]uh1js hjm hMhj m ubeh }(h ]h ]h"]h$]h&]uh1jn hj m ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j devm_cxl_add_dport (C function)c.devm_cxl_add_dporthNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hstruct cxl_dport * devm_cxl_add_dport (struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h]j. )}(hstruct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h](j )}(hj h]hstruct}(hj*n hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj&n hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hj8n hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj&n hhhj7n hMubh)}(hhh]j] )}(h cxl_dporth]h cxl_dport}(hjIn hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjFn ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjKn modnameN classnameNj j )}j ]j )}j devm_cxl_add_dportsbc.devm_cxl_add_dportasbuh1hhj&n hhhj7n hMubjF )}(h h]h }(hjjn hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj&n hhhj7n hMubj )}(hj h]h*}(hjxn hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj&n hhhj7n hMubjW )}(hdevm_cxl_add_dporth]j] )}(hjgn h]hdevm_cxl_add_dport}(hjn hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjn ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj&n hhhj7n hMubjv )}(hb(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hjn hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjn ubjF )}(h h]h }(hjn hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjn ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjn hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjn ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjn modnameN classnameNj j )}j ]jen c.devm_cxl_add_dportasbuh1hhjn ubjF )}(h h]h }(hjn hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjn ubj )}(hj h]h*}(hjn hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjn ubj] )}(hporth]hport}(hjn hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjn ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjn ubj| )}(hstruct device *dport_devh](j )}(hj h]hstruct}(hjo hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjo ubjF )}(h h]h }(hj!o hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjo ubh)}(hhh]j] )}(hdeviceh]hdevice}(hj2o hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj/o ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj4o modnameN classnameNj j )}j ]jen c.devm_cxl_add_dportasbuh1hhjo ubjF )}(h h]h }(hjPo hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjo ubj )}(hj h]h*}(hj^o hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjo ubj] )}(h dport_devh]h dport_dev}(hjko hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjo ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjn ubj| )}(h int port_idh](j4 )}(hinth]hint}(hjo hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjo ubjF )}(h h]h }(hjo hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjo ubj] )}(hport_idh]hport_id}(hjo hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjo ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjn ubj| )}(h"resource_size_t component_reg_physh](h)}(hhh]j] )}(hresource_size_th]hresource_size_t}(hjo hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjo ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjo modnameN classnameNj j )}j ]jen c.devm_cxl_add_dportasbuh1hhjo ubjF )}(h h]h }(hjo hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjo ubj] )}(hcomponent_reg_physh]hcomponent_reg_phys}(hjo hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjo ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjn ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj&n hhhj7n hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj"n hhhj7n hMubah }(h ]j n ah ](j j eh"]h$]h&]j j )j huh1j' hj7n hMhj n hhubj )}(hhh]j] )}(h,append VH downstream port data to a cxl_porth]h,append VH downstream port data to a cxl_port}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjp hhubah }(h ]h ]h"]h$]h&]uh1j hj n hhhj7n hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j*p j j*p j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_port *port``
the cxl_port that references this dport
``struct device *dport_dev``
firmware or PCI device representing the dport
``int port_id``
identifier for this dport in a decoder's target list
``resource_size_t component_reg_phys``
optional location of CXL component registers
**Description**
Note that dports are appended to the devm release action's of the
either the port's host (for root ports), or the port itself (for
switch ports)h](j] )}(h**Parameters**h]j )}(hj4p h]h
Parameters}(hj6p hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2p ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj.p ubjo )}(hhh](jt )}(hB``struct cxl_port *port``
the cxl_port that references this dport
h](jz )}(h``struct cxl_port *port``h]j )}(hjSp h]hstruct cxl_port *port}(hjUp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjQp ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjMp ubj )}(hhh]j] )}(h'the cxl_port that references this dporth]h'the cxl_port that references this dport}(hjlp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjhp hMhjip ubah }(h ]h ]h"]h$]h&]uh1j hjMp ubeh }(h ]h ]h"]h$]h&]uh1js hjhp hMhjJp ubjt )}(hK``struct device *dport_dev``
firmware or PCI device representing the dport
h](jz )}(h ``struct device *dport_dev``h]j )}(hjp h]hstruct device *dport_dev}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjp ubj )}(hhh]j] )}(h-firmware or PCI device representing the dporth]h-firmware or PCI device representing the dport}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjp hMhjp ubah }(h ]h ]h"]h$]h&]uh1j hjp ubeh }(h ]h ]h"]h$]h&]uh1js hjp hMhjJp ubjt )}(hE``int port_id``
identifier for this dport in a decoder's target list
h](jz )}(h``int port_id``h]j )}(hjp h]h int port_id}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjp ubj )}(hhh]j] )}(h4identifier for this dport in a decoder's target listh]h6identifier for this dport in a decoder’s target list}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjp hMhjp ubah }(h ]h ]h"]h$]h&]uh1j hjp ubeh }(h ]h ]h"]h$]h&]uh1js hjp hMhjJp ubjt )}(hT``resource_size_t component_reg_phys``
optional location of CXL component registers
h](jz )}(h&``resource_size_t component_reg_phys``h]j )}(hjp h]h"resource_size_t component_reg_phys}(hj q hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjp ubj )}(hhh]j] )}(h,optional location of CXL component registersh]h,optional location of CXL component registers}(hjq hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjq hMhjq ubah }(h ]h ]h"]h$]h&]uh1j hjp ubeh }(h ]h ]h"]h$]h&]uh1js hjq hMhjJp ubeh }(h ]h ]h"]h$]h&]uh1jn hj.p ubj] )}(h**Description**h]j )}(hj9q h]h Description}(hj;q hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj7q ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj.p ubj] )}(hNote that dports are appended to the devm release action's of the
either the port's host (for root ports), or the port itself (for
switch ports)h]hNote that dports are appended to the devm release action’s of the
either the port’s host (for root ports), or the port itself (for
switch ports)}(hjOq hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj.p ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j #devm_cxl_add_rch_dport (C function)c.devm_cxl_add_rch_dporthNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h~struct cxl_dport * devm_cxl_add_rch_dport (struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h]j. )}(h|struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h](j )}(hj h]hstruct}(hj~q hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjzq hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hjq hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjzq hhhjq hMubh)}(hhh]j] )}(h cxl_dporth]h cxl_dport}(hjq hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjq modnameN classnameNj j )}j ]j )}j devm_cxl_add_rch_dportsbc.devm_cxl_add_rch_dportasbuh1hhjzq hhhjq hMubjF )}(h h]h }(hjq hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjzq hhhjq hMubj )}(hj h]h*}(hjq hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjzq hhhjq hMubjW )}(hdevm_cxl_add_rch_dporth]j] )}(hjq h]hdevm_cxl_add_rch_dport}(hjq hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjzq hhhjq hMubjv )}(hT(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hjq hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjq ubjF )}(h h]h }(hjr hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjq ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjr ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjr modnameN classnameNj j )}j ]jq c.devm_cxl_add_rch_dportasbuh1hhjq ubjF )}(h h]h }(hj4r hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjq ubj )}(hj h]h*}(hjBr hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjq ubj] )}(hporth]hport}(hjOr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjq ubj| )}(hstruct device *dport_devh](j )}(hj h]hstruct}(hjhr hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjdr ubjF )}(h h]h }(hjur hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjdr ubh)}(hhh]j] )}(hdeviceh]hdevice}(hjr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjr ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjr modnameN classnameNj j )}j ]jq c.devm_cxl_add_rch_dportasbuh1hhjdr ubjF )}(h h]h }(hjr hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjdr ubj )}(hj h]h*}(hjr hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjdr ubj] )}(h dport_devh]h dport_dev}(hjr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjdr ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjq ubj| )}(h int port_idh](j4 )}(hinth]hint}(hjr hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjr ubjF )}(h h]h }(hjr hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjr ubj] )}(hport_idh]hport_id}(hjr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjr ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjq ubj| )}(hresource_size_t rcrbh](h)}(hhh]j] )}(hresource_size_th]hresource_size_t}(hjs hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj
s ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjs modnameN classnameNj j )}j ]jq c.devm_cxl_add_rch_dportasbuh1hhj s ubjF )}(h h]h }(hj.s hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj s ubj] )}(hrcrbh]hrcrb}(hjint cxl_add_ep(struct cxl_dport *dport, struct device *ep_dev)h](j4 )}(hinth]hint}(hjt hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjt hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hjt hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjt hhhjt hMubjW )}(h
cxl_add_eph]j] )}(h
cxl_add_eph]h
cxl_add_ep}(hjt hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjt ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjt hhhjt hMubjv )}(h0(struct cxl_dport *dport, struct device *ep_dev)h](j| )}(hstruct cxl_dport *dporth](j )}(hj h]hstruct}(hju hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj u ubjF )}(h h]h }(hj u hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj u ubh)}(hhh]j] )}(h cxl_dporth]h cxl_dport}(hj-u hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj*u ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj/u modnameN classnameNj j )}j ]j )}j jt sb c.cxl_add_epasbuh1hhj u ubjF )}(h h]h }(hjMu hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj u ubj )}(hj h]h*}(hj[u hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj u ubj] )}(hdporth]hdport}(hjhu hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj u ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hju ubj| )}(hstruct device *ep_devh](j )}(hj h]hstruct}(hju hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj}u ubjF )}(h h]h }(hju hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj}u ubh)}(hhh]j] )}(hdeviceh]hdevice}(hju hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hju ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetju modnameN classnameNj j )}j ]jIu c.cxl_add_epasbuh1hhj}u ubjF )}(h h]h }(hju hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj}u ubj )}(hj h]h*}(hju hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj}u ubj] )}(hep_devh]hep_dev}(hju hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj}u ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hju ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjt hhhjt hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjt hhhjt hMubah }(h ]jt ah ](j j eh"]h$]h&]j j )j huh1j' hjt hMhjt hhubj )}(hhh]j] )}(h)register an endpoint's interest in a porth]h+register an endpoint’s interest in a port}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhju hhubah }(h ]h ]h"]h$]h&]uh1j hjt hhhjt hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jv j jv j j j uh1j" hhhju. hNhNubj )}(hX] **Parameters**
``struct cxl_dport *dport``
the dport that routes to **ep_dev**
``struct device *ep_dev``
device representing the endpoint
**Description**
Intermediate CXL ports are scanned based on the arrival of endpoints.
When those endpoints depart the port can be destroyed once all
endpoints that care about that port have been removed.h](j] )}(h**Parameters**h]j )}(hj$v h]h
Parameters}(hj&v hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj"v ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj v ubjo )}(hhh](jt )}(h@``struct cxl_dport *dport``
the dport that routes to **ep_dev**
h](jz )}(h``struct cxl_dport *dport``h]j )}(hjCv h]hstruct cxl_dport *dport}(hjEv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjAv ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj=v ubj )}(hhh]j] )}(h#the dport that routes to **ep_dev**h](hthe dport that routes to }(hj\v hhhNhNubj )}(h
**ep_dev**h]hep_dev}(hjdv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj\v ubeh }(h ]h ]h"]h$]h&]uh1j\ hjXv hMhjYv ubah }(h ]h ]h"]h$]h&]uh1j hj=v ubeh }(h ]h ]h"]h$]h&]uh1js hjXv hMhj:v ubjt )}(h;``struct device *ep_dev``
device representing the endpoint
h](jz )}(h``struct device *ep_dev``h]j )}(hjv h]hstruct device *ep_dev}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjv ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjv ubj )}(hhh]j] )}(h device representing the endpointh]h device representing the endpoint}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjv hMhjv ubah }(h ]h ]h"]h$]h&]uh1j hjv ubeh }(h ]h ]h"]h$]h&]uh1js hjv hMhj:v ubeh }(h ]h ]h"]h$]h&]uh1jn hj v ubj] )}(h**Description**h]j )}(hjv h]h Description}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjv ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj v ubj] )}(hIntermediate CXL ports are scanned based on the arrival of endpoints.
When those endpoints depart the port can be destroyed once all
endpoints that care about that port have been removed.h]hIntermediate CXL ports are scanned based on the arrival of endpoints.
When those endpoints depart the port can be destroyed once all
endpoints that care about that port have been removed.}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj v ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_decoder_init (C function)c.cxl_decoder_inithNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hFint cxl_decoder_init (struct cxl_port *port, struct cxl_decoder *cxld)h]j. )}(hEint cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)h](j4 )}(hinth]hint}(hj
w hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjw hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hjw hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw hhhjw hMubjW )}(hcxl_decoder_inith]j] )}(hcxl_decoder_inith]hcxl_decoder_init}(hj+w hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj'w ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjw hhhjw hMubjv )}(h1(struct cxl_port *port, struct cxl_decoder *cxld)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hjGw hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjCw ubjF )}(h h]h }(hjTw hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjCw ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjew hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjbw ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjgw modnameN classnameNj j )}j ]j )}j j-w sbc.cxl_decoder_initasbuh1hhjCw ubjF )}(h h]h }(hjw hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjCw ubj )}(hj h]h*}(hjw hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjCw ubj] )}(hporth]hport}(hjw hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjCw ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj?w ubj| )}(hstruct cxl_decoder *cxldh](j )}(hj h]hstruct}(hjw hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjw ubjF )}(h h]h }(hjw hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw ubh)}(hhh]j] )}(h cxl_decoderh]h cxl_decoder}(hjw hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjw ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjw modnameN classnameNj j )}j ]jw c.cxl_decoder_initasbuh1hhjw ubjF )}(h h]h }(hjw hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw ubj )}(hj h]h*}(hjx hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjw ubj] )}(hcxldh]hcxld}(hjx hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjw ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj?w ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjw hhhjw hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjw hhhjw hMubah }(h ]jv ah ](j j eh"]h$]h&]j j )j huh1j' hjw hMhjv hhubj )}(hhh]j] )}(h%Common decoder setup / initializationh]h%Common decoder setup / initialization}(hj:x hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj7x hhubah }(h ]h ]h"]h$]h&]uh1j hjv hhhjw hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jRx j jRx j j j uh1j" hhhju. hNhNubj )}(hXr **Parameters**
``struct cxl_port *port``
owning port of this decoder
``struct cxl_decoder *cxld``
common decoder properties to initialize
**Description**
A port may contain one or more decoders. Each of those decoders
enable some address space for CXL.mem utilization. A decoder is
expected to be configured by the caller before registering via
cxl_decoder_add()h](j] )}(h**Parameters**h]j )}(hj\x h]h
Parameters}(hj^x hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjZx ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjVx ubjo )}(hhh](jt )}(h6``struct cxl_port *port``
owning port of this decoder
h](jz )}(h``struct cxl_port *port``h]j )}(hj{x h]hstruct cxl_port *port}(hj}x hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjyx ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjux ubj )}(hhh]j] )}(howning port of this decoderh]howning port of this decoder}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjx hMhjx ubah }(h ]h ]h"]h$]h&]uh1j hjux ubeh }(h ]h ]h"]h$]h&]uh1js hjx hMhjrx ubjt )}(hE``struct cxl_decoder *cxld``
common decoder properties to initialize
h](jz )}(h ``struct cxl_decoder *cxld``h]j )}(hjx h]hstruct cxl_decoder *cxld}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjx ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjx ubj )}(hhh]j] )}(h'common decoder properties to initializeh]h'common decoder properties to initialize}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjx hMhjx ubah }(h ]h ]h"]h$]h&]uh1j hjx ubeh }(h ]h ]h"]h$]h&]uh1js hjx hMhjrx ubeh }(h ]h ]h"]h$]h&]uh1jn hjVx ubj] )}(h**Description**h]j )}(hjx h]h Description}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjx ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjVx ubj] )}(hA port may contain one or more decoders. Each of those decoders
enable some address space for CXL.mem utilization. A decoder is
expected to be configured by the caller before registering via
cxl_decoder_add()h]hA port may contain one or more decoders. Each of those decoders
enable some address space for CXL.mem utilization. A decoder is
expected to be configured by the caller before registering via
cxl_decoder_add()}(hjy hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjVx ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j #cxl_root_decoder_alloc (C function)c.cxl_root_decoder_allochNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hastruct cxl_root_decoder * cxl_root_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]j. )}(h_struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j )}(hj h]hstruct}(hj4y hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj0y hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hjBy hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj0y hhhjAy hMubh)}(hhh]j] )}(hcxl_root_decoderh]hcxl_root_decoder}(hjSy hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjPy ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjUy modnameN classnameNj j )}j ]j )}j cxl_root_decoder_allocsbc.cxl_root_decoder_allocasbuh1hhj0y hhhjAy hMubjF )}(h h]h }(hjty hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj0y hhhjAy hMubj )}(hj h]h*}(hjy hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj0y hhhjAy hMubjW )}(hcxl_root_decoder_alloch]j] )}(hjqy h]hcxl_root_decoder_alloc}(hjy hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjy ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj0y hhhjAy hMubjv )}(h0(struct cxl_port *port, unsigned int nr_targets)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hjy hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjy ubjF )}(h h]h }(hjy hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjy ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjy hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjy ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjy modnameN classnameNj j )}j ]joy c.cxl_root_decoder_allocasbuh1hhjy ubjF )}(h h]h }(hjy hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjy ubj )}(hj h]h*}(hjy hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjy ubj] )}(hporth]hport}(hjz hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjy ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjy ubj| )}(hunsigned int nr_targetsh](j4 )}(hunsignedh]hunsigned}(hj z hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjz ubjF )}(h h]h }(hj,z hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjz ubj4 )}(hinth]hint}(hj:z hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjz ubjF )}(h h]h }(hjHz hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjz ubj] )}(h
nr_targetsh]h
nr_targets}(hjVz hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjz ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjy ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj0y hhhjAy hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj,y hhhjAy hMubah }(h ]j'y ah ](j j eh"]h$]h&]j j )j huh1j' hjAy hMhj)y hhubj )}(hhh]j] )}(h Allocate a root level decoderh]h Allocate a root level decoder}(hjz hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj}z hhubah }(h ]h ]h"]h$]h&]uh1j hj)y hhhjAy hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jz j jz j j j uh1j" hhhju. hNhNubj )}(hXk **Parameters**
``struct cxl_port *port``
owning CXL root of this decoder
``unsigned int nr_targets``
static number of downstream targets
**Return**
A new cxl decoder to be registered by cxl_decoder_add(). A
'CXL root' decoder is one that decodes from a top-level / static platform
firmware description of CXL resources into a CXL standard decode
topology.h](j] )}(h**Parameters**h]j )}(hjz h]h
Parameters}(hjz hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubjo )}(hhh](jt )}(h:``struct cxl_port *port``
owning CXL root of this decoder
h](jz )}(h``struct cxl_port *port``h]j )}(hjz h]hstruct cxl_port *port}(hjz hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubj )}(hhh]j] )}(h owning CXL root of this decoderh]h owning CXL root of this decoder}(hjz hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjz hMhjz ubah }(h ]h ]h"]h$]h&]uh1j hjz ubeh }(h ]h ]h"]h$]h&]uh1js hjz hMhjz ubjt )}(h@``unsigned int nr_targets``
static number of downstream targets
h](jz )}(h``unsigned int nr_targets``h]j )}(hjz h]hunsigned int nr_targets}(hjz hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjz ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubj )}(hhh]j] )}(h#static number of downstream targetsh]h#static number of downstream targets}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj{ hMhj{ ubah }(h ]h ]h"]h$]h&]uh1j hjz ubeh }(h ]h ]h"]h$]h&]uh1js hj{ hMhjz ubeh }(h ]h ]h"]h$]h&]uh1jn hjz ubj] )}(h
**Return**h]j )}(hj5{ h]hReturn}(hj7{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj3{ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubj] )}(hA new cxl decoder to be registered by cxl_decoder_add(). A
'CXL root' decoder is one that decodes from a top-level / static platform
firmware description of CXL resources into a CXL standard decode
topology.h]hA new cxl decoder to be registered by cxl_decoder_add(). A
‘CXL root’ decoder is one that decodes from a top-level / static platform
firmware description of CXL resources into a CXL standard decode
topology.}(hjK{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j %cxl_switch_decoder_alloc (C function)c.cxl_switch_decoder_allochNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hestruct cxl_switch_decoder * cxl_switch_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]j. )}(hcstruct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j )}(hj h]hstruct}(hjz{ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjv{ hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM1ubjF )}(h h]h }(hj{ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjv{ hhhj{ hM1ubh)}(hhh]j] )}(hcxl_switch_decoderh]hcxl_switch_decoder}(hj{ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj{ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj{ modnameN classnameNj j )}j ]j )}j cxl_switch_decoder_allocsbc.cxl_switch_decoder_allocasbuh1hhjv{ hhhj{ hM1ubjF )}(h h]h }(hj{ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjv{ hhhj{ hM1ubj )}(hj h]h*}(hj{ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjv{ hhhj{ hM1ubjW )}(hcxl_switch_decoder_alloch]j] )}(hj{ h]hcxl_switch_decoder_alloc}(hj{ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj{ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjv{ hhhj{ hM1ubjv )}(h0(struct cxl_port *port, unsigned int nr_targets)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj{ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj{ ubjF )}(h h]h }(hj| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj{ ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj| ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj| modnameN classnameNj j )}j ]j{ c.cxl_switch_decoder_allocasbuh1hhj{ ubjF )}(h h]h }(hj0| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj{ ubj )}(hj h]h*}(hj>| hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj{ ubj] )}(hporth]hport}(hjK| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj{ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj{ ubj| )}(hunsigned int nr_targetsh](j4 )}(hunsignedh]hunsigned}(hjd| hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj`| ubjF )}(h h]h }(hjr| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj`| ubj4 )}(hinth]hint}(hj| hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj`| ubjF )}(h h]h }(hj| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj`| ubj] )}(h
nr_targetsh]h
nr_targets}(hj| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj`| ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj{ ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjv{ hhhj{ hM1ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjr{ hhhj{ hM1ubah }(h ]jm{ ah ](j j eh"]h$]h&]j j )j huh1j' hj{ hM1hjo{ hhubj )}(hhh]j] )}(h Allocate a switch level decoderh]h Allocate a switch level decoder}(hj| hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM1hj| hhubah }(h ]h ]h"]h$]h&]uh1j hjo{ hhhj{ hM1ubeh }(h ]h ](j functioneh"]h$]h&]j j j j| j j| j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_port *port``
owning CXL switch port of this decoder
``unsigned int nr_targets``
max number of dynamically addressable downstream targets
**Return**
A new cxl decoder to be registered by cxl_decoder_add(). A
'switch' decoder is any decoder that can be enumerated by PCIe
topology and the HDM Decoder Capability. This includes the decoders
that sit between Switch Upstream Ports / Switch Downstream Ports and
Host Bridges / Root Ports.h](j] )}(h**Parameters**h]j )}(hj| h]h
Parameters}(hj| hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj| ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM5hj| ubjo )}(hhh](jt )}(hA``struct cxl_port *port``
owning CXL switch port of this decoder
h](jz )}(h``struct cxl_port *port``h]j )}(hj} h]hstruct cxl_port *port}(hj } hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj} ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM2hj} ubj )}(hhh]j] )}(h&owning CXL switch port of this decoderh]h&owning CXL switch port of this decoder}(hj } hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj } hM2hj } ubah }(h ]h ]h"]h$]h&]uh1j hj} ubeh }(h ]h ]h"]h$]h&]uh1js hj } hM2hj| ubjt )}(hU``unsigned int nr_targets``
max number of dynamically addressable downstream targets
h](jz )}(h``unsigned int nr_targets``h]j )}(hj@} h]hunsigned int nr_targets}(hjB} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj>} ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM3hj:} ubj )}(hhh]j] )}(h8max number of dynamically addressable downstream targetsh]h8max number of dynamically addressable downstream targets}(hjY} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjU} hM3hjV} ubah }(h ]h ]h"]h$]h&]uh1j hj:} ubeh }(h ]h ]h"]h$]h&]uh1js hjU} hM3hj| ubeh }(h ]h ]h"]h$]h&]uh1jn hj| ubj] )}(h
**Return**h]j )}(hj{} h]hReturn}(hj}} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjy} ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM5hj| ubj] )}(hX A new cxl decoder to be registered by cxl_decoder_add(). A
'switch' decoder is any decoder that can be enumerated by PCIe
topology and the HDM Decoder Capability. This includes the decoders
that sit between Switch Upstream Ports / Switch Downstream Ports and
Host Bridges / Root Ports.h]hX! A new cxl decoder to be registered by cxl_decoder_add(). A
‘switch’ decoder is any decoder that can be enumerated by PCIe
topology and the HDM Decoder Capability. This includes the decoders
that sit between Switch Upstream Ports / Switch Downstream Ports and
Host Bridges / Root Ports.}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM5hj| ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'cxl_endpoint_decoder_alloc (C function) c.cxl_endpoint_decoder_allochNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hPstruct cxl_endpoint_decoder * cxl_endpoint_decoder_alloc (struct cxl_port *port)h]j. )}(hNstruct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)h](j )}(hj h]hstruct}(hj} hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj} hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMVubjF )}(h h]h }(hj} hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} hhhj} hMVubh)}(hhh]j] )}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj} hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj} ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj} modnameN classnameNj j )}j ]j )}j cxl_endpoint_decoder_allocsb c.cxl_endpoint_decoder_allocasbuh1hhj} hhhj} hMVubjF )}(h h]h }(hj ~ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} hhhj} hMVubj )}(hj h]h*}(hj~ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj} hhhj} hMVubjW )}(hcxl_endpoint_decoder_alloch]j] )}(hj} h]hcxl_endpoint_decoder_alloc}(hj ~ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj~ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj} hhhj} hMVubjv )}(h(struct cxl_port *port)h]j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj:~ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj6~ ubjF )}(h h]h }(hjG~ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj6~ ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjX~ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjU~ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjZ~ modnameN classnameNj j )}j ]j} c.cxl_endpoint_decoder_allocasbuh1hhj6~ ubjF )}(h h]h }(hjv~ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj6~ ubj )}(hj h]h*}(hj~ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj6~ ubj] )}(hporth]hport}(hj~ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj6~ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj2~ ubah }(h ]h ]h"]h$]h&]hhuh1ju hj} hhhj} hMVubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj} hhhj} hMVubah }(h ]j} ah ](j j eh"]h$]h&]j j )j huh1j' hj} hMVhj} hhubj )}(hhh]j] )}(h Allocate an endpoint decoderh]h Allocate an endpoint decoder}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMVhj~ hhubah }(h ]h ]h"]h$]h&]uh1j hj} hhhj} hMVubeh }(h ]h ](j functioneh"]h$]h&]j j j j~ j j~ j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_port *port``
owning port of this decoder
**Return**
A new cxl decoder to be registered by cxl_decoder_add()h](j] )}(h**Parameters**h]j )}(hj~ h]h
Parameters}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj~ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMZhj~ ubjo )}(hhh]jt )}(h6``struct cxl_port *port``
owning port of this decoder
h](jz )}(h``struct cxl_port *port``h]j )}(hj~ h]hstruct cxl_port *port}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj~ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMWhj~ ubj )}(hhh]j] )}(howning port of this decoderh]howning port of this decoder}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMWhj ubah }(h ]h ]h"]h$]h&]uh1j hj~ ubeh }(h ]h ]h"]h$]h&]uh1js hj hMWhj~ ubah }(h ]h ]h"]h$]h&]uh1jn hj~ ubj] )}(h
**Return**h]j )}(hj7 h]hReturn}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMYhj~ ubj] )}(h7A new cxl decoder to be registered by cxl_decoder_add()h]h7A new cxl decoder to be registered by cxl_decoder_add()}(hjM hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMYhj~ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j #cxl_decoder_add_locked (C function)c.cxl_decoder_add_lockedhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hFint cxl_decoder_add_locked (struct cxl_decoder *cxld, int *target_map)h]j. )}(hEint cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map)h](j4 )}(hinth]hint}(hj| hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjx hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMwubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjx hhhj hMwubjW )}(hcxl_decoder_add_lockedh]j] )}(hcxl_decoder_add_lockedh]hcxl_decoder_add_locked}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjx hhhj hMwubjv )}(h+(struct cxl_decoder *cxld, int *target_map)h](j| )}(hstruct cxl_decoder *cxldh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_decoderh]h cxl_decoder}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j j sbc.cxl_decoder_add_lockedasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxldh]hcxld}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hint *target_maph](j4 )}(hinth]hint}(hj+ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj' ubjF )}(h h]h }(hj9 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj' ubj )}(hj h]h*}(hjG hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj' ubj] )}(h
target_maph]h
target_map}(hjT hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj' ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjx hhhj hMwubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjt hhhj hMwubah }(h ]jo ah ](j j eh"]h$]h&]j j )j huh1j' hj hMwhjq hhubj )}(hhh]j] )}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMwhj{ hhubah }(h ]h ]h"]h$]h&]uh1j hjq hhhj hMwubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_decoder *cxld``
The cxl decoder allocated by cxl__decoder_alloc()
``int *target_map``
A list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.
**Description**
Certain types of decoders may not have any targets. The main example of this
is an endpoint device. A more awkward example is a hostbridge whose root
ports get hot added (technically possible, though unlikely).
This is the locked variant of cxl_decoder_add().
**Context**
Process context. Expects the device lock of the port that owns the
**cxld** to be held.
**Return**
Negative error code if the decoder wasn't properly configured; else
returns 0.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM{hj ubjo )}(hhh](jt )}(hU``struct cxl_decoder *cxld``
The cxl decoder allocated by cxl__decoder_alloc()
h](jz )}(h ``struct cxl_decoder *cxld``h]j )}(hj h]hstruct cxl_decoder *cxld}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMxhj ubj )}(hhh]j] )}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjԀ hMxhjՀ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjԀ hMxhj ubjt )}(h``int *target_map``
A list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.
h](jz )}(h``int *target_map``h]j )}(hj h]hint *target_map}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM{hj ubj )}(hhh]j] )}(hA list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMyhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj
hM{hj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h**Description**h]j )}(hj4 h]h Description}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2 ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM}hj ubj] )}(hCertain types of decoders may not have any targets. The main example of this
is an endpoint device. A more awkward example is a hostbridge whose root
ports get hot added (technically possible, though unlikely).h]hCertain types of decoders may not have any targets. The main example of this
is an endpoint device. A more awkward example is a hostbridge whose root
ports get hot added (technically possible, though unlikely). }(hjJ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chM|hj ubj] )}(h0This is the locked variant of cxl_decoder_add().h]h0This is the locked variant of cxl_decoder_add().}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(h **Context**h]j )}(hjj h]hContext}(hjl hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjh ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(hWProcess context. Expects the device lock of the port that owns the
**cxld** to be held.h](hCProcess context. Expects the device lock of the port that owns the
}(hj hhhNhNubj )}(h**cxld**h]hcxld}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh to be held.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(hNNegative error code if the decoder wasn't properly configured; else
returns 0.h]hPNegative error code if the decoder wasn’t properly configured; else
returns 0.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_decoder_add (C function)c.cxl_decoder_addhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h?int cxl_decoder_add (struct cxl_decoder *cxld, int *target_map)h]j. )}(h>int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMubjW )}(hcxl_decoder_addh]j] )}(hcxl_decoder_addh]hcxl_decoder_add}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMubjv )}(h+(struct cxl_decoder *cxld, int *target_map)h](j| )}(hstruct cxl_decoder *cxldh](j )}(hj h]hstruct}(hj% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubjF )}(h h]h }(hj2 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubh)}(hhh]j] )}(h cxl_decoderh]h cxl_decoder}(hjC hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj@ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjE modnameN classnameNj j )}j ]j )}j j sbc.cxl_decoder_addasbuh1hhj! ubjF )}(h h]h }(hjc hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubj )}(hj h]h*}(hjq hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubj] )}(hcxldh]hcxld}(hj~ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj! ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hint *target_maph](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(h
target_maph]h
target_map}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMubah }(h ]jہ ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhj݁ hhubj )}(hhh]j] )}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj݁ hhhj hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_decoder *cxld``
The cxl decoder allocated by cxl__decoder_alloc()
``int *target_map``
A list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.
**Description**
This is the unlocked variant of cxl_decoder_add_locked().
See cxl_decoder_add_locked().
**Context**
Process context. Takes and releases the device lock of the port that
owns the **cxld**.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubjo )}(hhh](jt )}(hU``struct cxl_decoder *cxld``
The cxl decoder allocated by cxl__decoder_alloc()
h](jz )}(h ``struct cxl_decoder *cxld``h]j )}(hj+ h]hstruct cxl_decoder *cxld}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj) ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj% ubj )}(hhh]j] )}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hjD hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj@ hMhjA ubah }(h ]h ]h"]h$]h&]uh1j hj% ubeh }(h ]h ]h"]h$]h&]uh1js hj@ hMhj" ubjt )}(h``int *target_map``
A list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.
h](jz )}(h``int *target_map``h]j )}(hjd h]hint *target_map}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjb ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj^ ubj )}(hhh]j] )}(hA list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory
traffic to. These numbers should correspond with the port number
in the PCIe Link Capabilities structure.}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjz ubah }(h ]h ]h"]h$]h&]uh1j hj^ ubeh }(h ]h ]h"]h$]h&]uh1js hjy hMhj" ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(hWThis is the unlocked variant of cxl_decoder_add_locked().
See cxl_decoder_add_locked().h]hWThis is the unlocked variant of cxl_decoder_add_locked().
See cxl_decoder_add_locked().}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(h **Context**h]j )}(hjǃ h]hContext}(hjɃ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjŃ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj] )}(hWProcess context. Takes and releases the device lock of the port that
owns the **cxld**.h](hNProcess context. Takes and releases the device lock of the port that
owns the }(hj݃ hhhNhNubj )}(h**cxld**h]hcxld}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj݃ ubh.}(hj݃ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j "__cxl_driver_register (C function)c.__cxl_driver_registerhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(haint __cxl_driver_register (struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h]j. )}(h`int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMubjF )}(h h]h }(hj- hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj, hMubjW )}(h__cxl_driver_registerh]j] )}(h__cxl_driver_registerh]h__cxl_driver_register}(hj? hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj; ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj, hMubjv )}(hG(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j| )}(hstruct cxl_driver *cxl_drvh](j )}(hj h]hstruct}(hj[ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjW ubjF )}(h h]h }(hjh hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjW ubh)}(hhh]j] )}(h
cxl_driverh]h
cxl_driver}(hjy hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjv ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj{ modnameN classnameNj j )}j ]j )}j jA sbc.__cxl_driver_registerasbuh1hhjW ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjW ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjW ubj] )}(hcxl_drvh]hcxl_drv}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjW ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjS ubj| )}(hstruct module *ownerh](j )}(hj h]hstruct}(hj̈́ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjɄ ubjF )}(h h]h }(hjڄ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjɄ ubh)}(hhh]j] )}(hmoduleh]hmodule}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.__cxl_driver_registerasbuh1hhjɄ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjɄ ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjɄ ubj] )}(hownerh]howner}(hj$ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjɄ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjS ubj| )}(hconst char *modnameh](j )}(hjU h]hconst}(hj= hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj9 ubjF )}(h h]h }(hjJ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj9 ubj4 )}(hcharh]hchar}(hjX hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj9 ubjF )}(h h]h }(hjf hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj9 ubj )}(hj h]h*}(hjt hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj9 ubj] )}(hmodnameh]hmodname}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj9 ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjS ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj, hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj, hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj, hMhj hhubj )}(hhh]j] )}(h!register a driver for the cxl bush]h!register a driver for the cxl bus}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj, hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jÅ j jÅ j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_driver *cxl_drv``
cxl driver structure to attach
``struct module *owner``
owning module/driver
``const char *modname``
KBUILD_MODNAME for parent driverh](j] )}(h**Parameters**h]j )}(hjͅ h]h
Parameters}(hjυ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj˅ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjDž ubjo )}(hhh](jt )}(h>``struct cxl_driver *cxl_drv``
cxl driver structure to attach
h](jz )}(h ``struct cxl_driver *cxl_drv``h]j )}(hj h]hstruct cxl_driver *cxl_drv}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj )}(hhh]j] )}(h cxl driver structure to attachh]h cxl driver structure to attach}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h.``struct module *owner``
owning module/driver
h](jz )}(h``struct module *owner``h]j )}(hj% h]hstruct module *owner}(hj' hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhj ubj )}(hhh]j] )}(howning module/driverh]howning module/driver}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj: hMhj; ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj: hMhj ubjt )}(h8``const char *modname``
KBUILD_MODNAME for parent driverh](jz )}(h``const char *modname``h]j )}(hj^ h]hconst char *modname}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj\ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjX ubj )}(hhh]j] )}(h KBUILD_MODNAME for parent driverh]h KBUILD_MODNAME for parent driver}(hjw hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMhjt ubah }(h ]h ]h"]h$]h&]uh1j hjX ubeh }(h ]h ]h"]h$]h&]uh1js hjs hMhj ubeh }(h ]h ]h"]h$]h&]uh1jn hjDž ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j .cxl_endpoint_get_perf_coordinates (C function)#c.cxl_endpoint_get_perf_coordinateshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h^int cxl_endpoint_get_perf_coordinates (struct cxl_port *port, struct access_coordinate *coord)h]j. )}(h]int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMkubjF )}(h h]h }(hjdž hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhjƆ hMkubjW )}(h!cxl_endpoint_get_perf_coordinatesh]j] )}(h!cxl_endpoint_get_perf_coordinatesh]h!cxl_endpoint_get_perf_coordinates}(hjن hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjՆ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhjƆ hMkubjv )}(h8(struct cxl_port *port, struct access_coordinate *coord)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j jۆ sb#c.cxl_endpoint_get_perf_coordinatesasbuh1hhj ubjF )}(h h]h }(hj3 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjA hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hporth]hport}(hjN hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h struct access_coordinate *coordh](j )}(hj h]hstruct}(hjg hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjc ubjF )}(h h]h }(hjt hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc ubh)}(hhh]j] )}(haccess_coordinateh]haccess_coordinate}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j/ #c.cxl_endpoint_get_perf_coordinatesasbuh1hhjc ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjc ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjc ubj] )}(hcoordh]hcoord}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjc ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhjƆ hMkubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhjƆ hMkubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hjƆ hMkhj hhubj )}(hhh]j] )}(h9Retrieve performance numbers stored in dports of CXL pathh]h9Retrieve performance numbers stored in dports of CXL path}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMkhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhjƆ hMkubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_port *port``
endpoint cxl_port
``struct access_coordinate *coord``
output performance data
**Return**
errno on failure, 0 on success.h](j] )}(h**Parameters**h]j )}(hj
h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMohj ubjo )}(hhh](jt )}(h,``struct cxl_port *port``
endpoint cxl_port
h](jz )}(h``struct cxl_port *port``h]j )}(hj) h]hstruct cxl_port *port}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj' ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMmhj# ubj )}(hhh]j] )}(hendpoint cxl_porth]hendpoint cxl_port}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj> hMmhj? ubah }(h ]h ]h"]h$]h&]uh1j hj# ubeh }(h ]h ]h"]h$]h&]uh1js hj> hMmhj ubjt )}(h<``struct access_coordinate *coord``
output performance data
h](jz )}(h#``struct access_coordinate *coord``h]j )}(hjb h]h struct access_coordinate *coord}(hjd hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj` ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMnhj\ ubj )}(hhh]j] )}(houtput performance datah]houtput performance data}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjw hMnhjx ubah }(h ]h ]h"]h$]h&]uh1j hj\ ubeh }(h ]h ]h"]h$]h&]uh1js hjw hMnhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMphj ubj] )}(h errno on failure, 0 on success.h]h errno on failure, 0 on success.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:451: ./drivers/cxl/core/port.chMphj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(hCompute Express Link protocols are layered on top of PCIe. CXL core provides
a set of helpers for CXL interactions which occur via PCIe.h]hCompute Express Link protocols are layered on top of PCIe. CXL core provides
a set of helpers for CXL interactions which occur via PCIe.}(hjɈ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:454: ./drivers/cxl/core/pci.chKhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j +devm_cxl_port_enumerate_dports (C function) c.devm_cxl_port_enumerate_dportshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h:int devm_cxl_port_enumerate_dports (struct cxl_port *port)h]j. )}(h9int devm_cxl_port_enumerate_dports(struct cxl_port *port)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKGubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKGubjW )}(h devm_cxl_port_enumerate_dportsh]j] )}(h devm_cxl_port_enumerate_dportsh]h devm_cxl_port_enumerate_dports}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKGubjv )}(h(struct cxl_port *port)h]j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj. hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj* ubjF )}(h h]h }(hj; hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj* ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hjL hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjI ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjN modnameN classnameNj j )}j ]j )}j j sb c.devm_cxl_port_enumerate_dportsasbuh1hhj* ubjF )}(h h]h }(hjl hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj* ubj )}(hj h]h*}(hjz hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj* ubj] )}(hporth]hport}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj* ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj& ubah }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hKGubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKGubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKGhj hhubj )}(hhh]j] )}(h/enumerate downstream ports of the upstream porth]h/enumerate downstream ports of the upstream port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKGhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKGubeh }(h ]h ](j functioneh"]h$]h&]j j j jɉ j jɉ j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_port *port``
cxl_port whose ->uport_dev is the upstream of dports to be enumerated
**Description**
Returns a positive number of dports enumerated or a negative error
code.h](j] )}(h**Parameters**h]j )}(hjӉ h]h
Parameters}(hjՉ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjщ ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKKhj͉ ubjo )}(hhh]jt )}(h```struct cxl_port *port``
cxl_port whose ->uport_dev is the upstream of dports to be enumerated
h](jz )}(h``struct cxl_port *port``h]j )}(hj h]hstruct cxl_port *port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKHhj ubj )}(hhh]j] )}(hEcxl_port whose ->uport_dev is the upstream of dports to be enumeratedh]hEcxl_port whose ->uport_dev is the upstream of dports to be enumerated}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKHhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKHhj ubah }(h ]h ]h"]h$]h&]uh1jn hj͉ ubj] )}(h**Description**h]j )}(hj- h]h Description}(hj/ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj+ ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKJhj͉ ubj] )}(hHReturns a positive number of dports enumerated or a negative error
code.h]hHReturns a positive number of dports enumerated or a negative error
code.}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chKIhj͉ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_hdm_decode_init (C function)c.cxl_hdm_decode_inithNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hsint cxl_hdm_decode_init (struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j. )}(hrint cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j4 )}(hinth]hint}(hjr hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjn hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjn hhhj hMubjW )}(hcxl_hdm_decode_inith]j] )}(hcxl_hdm_decode_inith]hcxl_hdm_decode_init}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjn hhhj hMubjv )}(h[(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j| )}(hstruct cxl_dev_state *cxldsh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h
cxl_dev_stateh]h
cxl_dev_state}(hj͊ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjʊ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjϊ modnameN classnameNj j )}j ]j )}j j sbc.cxl_hdm_decode_initasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxldsh]hcxlds}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hstruct cxl_hdm *cxlhdmh](j )}(hj h]hstruct}(hj! hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj. hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_hdmh]hcxl_hdm}(hj? hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj< ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjA modnameN classnameNj j )}j ]j c.cxl_hdm_decode_initasbuh1hhj ubjF )}(h h]h }(hj] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjk hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxlhdmh]hcxlhdm}(hjx hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h$struct cxl_endpoint_dvsec_info *infoh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_hdm_decode_initasbuh1hhj ubjF )}(h h]h }(hj͋ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjۋ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hinfoh]hinfo}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjn hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjj hhhj hMubah }(h ]je ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhjg hhubj )}(hhh]j] )}(h#Setup HDM decoding for the endpointh]h#Setup HDM decoding for the endpoint}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hjg hhhj hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j* j j* j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_dev_state *cxlds``
Device state
``struct cxl_hdm *cxlhdm``
Mapped HDM decoder Capability
``struct cxl_endpoint_dvsec_info *info``
Cached DVSEC range registers info
**Description**
Try to enable the endpoint's HDM Decoder Capabilityh](j] )}(h**Parameters**h]j )}(hj4 h]h
Parameters}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj2 ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj. ubjo )}(hhh](jt )}(h-``struct cxl_dev_state *cxlds``
Device state
h](jz )}(h ``struct cxl_dev_state *cxlds``h]j )}(hjS h]hstruct cxl_dev_state *cxlds}(hjU hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjQ ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjM ubj )}(hhh]j] )}(h Device stateh]h Device state}(hjl hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjh hMhji ubah }(h ]h ]h"]h$]h&]uh1j hjM ubeh }(h ]h ]h"]h$]h&]uh1js hjh hMhjJ ubjt )}(h9``struct cxl_hdm *cxlhdm``
Mapped HDM decoder Capability
h](jz )}(h``struct cxl_hdm *cxlhdm``h]j )}(hj h]hstruct cxl_hdm *cxlhdm}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubj )}(hhh]j] )}(h Mapped HDM decoder Capabilityh]h Mapped HDM decoder Capability}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhjJ ubjt )}(hK``struct cxl_endpoint_dvsec_info *info``
Cached DVSEC range registers info
h](jz )}(h(``struct cxl_endpoint_dvsec_info *info``h]j )}(hjŌ h]h$struct cxl_endpoint_dvsec_info *info}(hjnj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjÌ ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubj )}(hhh]j] )}(h!Cached DVSEC range registers infoh]h!Cached DVSEC range registers info}(hjތ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjڌ hMhjی ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjڌ hMhjJ ubeh }(h ]h ]h"]h$]h&]uh1jn hj. ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj. ubj] )}(h3Try to enable the endpoint's HDM Decoder Capabilityh]h5Try to enable the endpoint’s HDM Decoder Capability}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj. ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j read_cdat_data (C function)c.read_cdat_datahNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h+void read_cdat_data (struct cxl_port *port)h]j. )}(h*void read_cdat_data(struct cxl_port *port)h](j4 )}(hvoidh]hvoid}(hjE hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjA hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMOubjF )}(h h]h }(hjT hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjA hhhjS hMOubjW )}(hread_cdat_datah]j] )}(hread_cdat_datah]hread_cdat_data}(hjf hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjb ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjA hhhjS hMOubjv )}(h(struct cxl_port *port)h]j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj~ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj~ ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j jh sbc.read_cdat_dataasbuh1hhj~ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj~ ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj~ ubj] )}(hporth]hport}(hjۍ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj~ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjz ubah }(h ]h ]h"]h$]h&]hhuh1ju hjA hhhjS hMOubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj= hhhjS hMOubah }(h ]j8 ah ](j j eh"]h$]h&]j j )j huh1j' hjS hMOhj: hhubj )}(hhh]j] )}(h Read the CDAT data on this porth]h Read the CDAT data on this port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMOhj hhubah }(h ]h ]h"]h$]h&]uh1j hj: hhhjS hMOubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_port *port``
Port to read data from
**Description**
This call will sleep waiting for responses from the DOE mailbox.h](j] )}(h**Parameters**h]j )}(hj' h]h
Parameters}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMShj! ubjo )}(hhh]jt )}(h1``struct cxl_port *port``
Port to read data from
h](jz )}(h``struct cxl_port *port``h]j )}(hjF h]hstruct cxl_port *port}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMPhj@ ubj )}(hhh]j] )}(hPort to read data fromh]hPort to read data from}(hj_ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj[ hMPhj\ ubah }(h ]h ]h"]h$]h&]uh1j hj@ ubeh }(h ]h ]h"]h$]h&]uh1js hj[ hMPhj= ubah }(h ]h ]h"]h$]h&]uh1jn hj! ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMRhj! ubj] )}(h@This call will sleep waiting for responses from the DOE mailbox.h]h@This call will sleep waiting for responses from the DOE mailbox.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMQhj! ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j )cxl_dport_init_ras_reporting (C function) c.cxl_dport_init_ras_reportinghNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hPvoid cxl_dport_init_ras_reporting (struct cxl_dport *dport, struct device *host)h]j. )}(hOvoid cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)h](j4 )}(hvoidh]hvoid}(hjƎ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM#ubjF )}(h h]h }(hjՎ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhjԎ hM#ubjW )}(h cxl_dport_init_ras_reportingh]j] )}(h cxl_dport_init_ras_reportingh]h cxl_dport_init_ras_reporting}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhjԎ hM#ubjv )}(h.(struct cxl_dport *dport, struct device *host)h](j| )}(hstruct cxl_dport *dporth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_dporth]h cxl_dport}(hj! hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj# modnameN classnameNj j )}j ]j )}j j sb c.cxl_dport_init_ras_reportingasbuh1hhj ubjF )}(h h]h }(hjA hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjO hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hdporth]hdport}(hj\ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hstruct device *hosth](j )}(hj h]hstruct}(hju hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjq ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjq ubh)}(hhh]j] )}(hdeviceh]hdevice}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j= c.cxl_dport_init_ras_reportingasbuh1hhjq ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjq ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjq ubj] )}(hhosth]hhost}(hj̏ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhjԎ hM#ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhjԎ hM#ubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hjԎ hM#hj hhubj )}(hhh]j] )}(h"Setup CXL RAS report on this dporth]h"Setup CXL RAS report on this dport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM#hj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhjԎ hM#ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct cxl_dport *dport``
the cxl_dport that needs to be initialized
``struct device *host``
host device for devm operationsh](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM'hj ubjo )}(hhh](jt )}(hG``struct cxl_dport *dport``
the cxl_dport that needs to be initialized
h](jz )}(h``struct cxl_dport *dport``h]j )}(hj7 h]hstruct cxl_dport *dport}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM$hj1 ubj )}(hhh]j] )}(h*the cxl_dport that needs to be initializedh]h*the cxl_dport that needs to be initialized}(hjP hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjL hM$hjM ubah }(h ]h ]h"]h$]h&]uh1j hj1 ubeh }(h ]h ]h"]h$]h&]uh1js hjL hM$hj. ubjt )}(h7``struct device *host``
host device for devm operationsh](jz )}(h``struct device *host``h]j )}(hjp h]hstruct device *host}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjn ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM&hjj ubj )}(hhh]j] )}(h host device for devm operationsh]h host device for devm operations}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chM%hj ubah }(h ]h ]h"]h$]h&]uh1j hjj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM&hj. ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_pci_get_latency (C function)c.cxl_pci_get_latencyhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h/long cxl_pci_get_latency (struct pci_dev *pdev)h]j. )}(h.long cxl_pci_get_latency(struct pci_dev *pdev)h](j4 )}(hlongh]hlong}(hjʐ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjƐ hhhj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMubjF )}(h h]h }(hjِ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjƐ hhhjؐ hMubjW )}(hcxl_pci_get_latencyh]j] )}(hcxl_pci_get_latencyh]hcxl_pci_get_latency}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjƐ hhhjؐ hMubjv )}(h(struct pci_dev *pdev)h]j| )}(hstruct pci_dev *pdevh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hpci_devh]hpci_dev}(hj% hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj" ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj' modnameN classnameNj j )}j ]j )}j j sbc.cxl_pci_get_latencyasbuh1hhj ubjF )}(h h]h }(hjE hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjS hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hpdevh]hpdev}(hj` hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubah }(h ]h ]h"]h$]h&]hhuh1ju hjƐ hhhjؐ hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhjؐ hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hjؐ hMhj hhubj )}(hhh]j] )}(h,calculate the link latency for the PCIe linkh]h,calculate the link latency for the PCIe link}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhjؐ hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX7 **Parameters**
``struct pci_dev *pdev``
PCI device
**Return**
calculated latency or 0 for no latency
**Description**
CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation
Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency
LinkProgationLatency is negligible, so 0 will be used
RetimerLatency is assumed to be negligible and 0 will be used
FlitLatency = FlitSize / LinkBandwidth
FlitSize is defined by spec. CXL rev3.0 4.2.1.
68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used.
The FlitLatency is converted to picoseconds.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubjo )}(hhh]jt )}(h$``struct pci_dev *pdev``
PCI device
h](jz )}(h``struct pci_dev *pdev``h]j )}(hjˑ h]hstruct pci_dev *pdev}(hj͑ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjɑ ubah }(h ]h ]h"]h$]h&]uh1jy hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhjő ubj )}(hhh]j] )}(h
PCI deviceh]h
PCI device}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hjő ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubah }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubj] )}(h&calculated latency or 0 for no latencyh]h&calculated latency or 0 for no latency}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubj] )}(h**Description**h]j )}(hj- h]h Description}(hj/ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj+ ubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubj] )}(hX CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation
Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency
LinkProgationLatency is negligible, so 0 will be used
RetimerLatency is assumed to be negligible and 0 will be used
FlitLatency = FlitSize / LinkBandwidth
FlitSize is defined by spec. CXL rev3.0 4.2.1.
68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used.
The FlitLatency is converted to picoseconds.h]hX CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation
Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency
LinkProgationLatency is negligible, so 0 will be used
RetimerLatency is assumed to be negligible and 0 will be used
FlitLatency = FlitSize / LinkBandwidth
FlitSize is defined by spec. CXL rev3.0 4.2.1.
68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used.
The FlitLatency is converted to picoseconds.}(hjC hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:457: ./drivers/cxl/core/pci.chMhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(hXI The core CXL PMEM infrastructure supports persistent memory
provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
'bridge' device is added at the root of a CXL device topology if
platform firmware advertises at least one persistent memory capable
CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
device. Then for each cxl_memdev in the CXL device topology a bridge
device is added to host a LIBNVDIMM dimm object. When these bridges
are registered native LIBNVDIMM uapis are translated to CXL
operations, for example, namespace label access commands.h]hXQ The core CXL PMEM infrastructure supports persistent memory
provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
‘bridge’ device is added at the root of a CXL device topology if
platform firmware advertises at least one persistent memory capable
CXL window. That root-level bridge corresponds to a LIBNVDIMM ‘bus’
device. Then for each cxl_memdev in the CXL device topology a bridge
device is added to host a LIBNVDIMM dimm object. When these bridges
are registered native LIBNVDIMM uapis are translated to CXL
operations, for example, namespace label access commands.}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:460: ./drivers/cxl/core/pmem.chK hju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j #cxl_find_nvdimm_bridge (C function)c.cxl_find_nvdimm_bridgehNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hIstruct cxl_nvdimm_bridge * cxl_find_nvdimm_bridge (struct cxl_port *port)h]j. )}(hGstruct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)h](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj} hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} hhhj hK7ubh)}(hhh]j] )}(hcxl_nvdimm_bridgeh]hcxl_nvdimm_bridge}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j cxl_find_nvdimm_bridgesbc.cxl_find_nvdimm_bridgeasbuh1hhj} hhhj hK7ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj} hhhj hK7ubj )}(hj h]h*}(hjϒ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj} hhhj hK7ubjW )}(hcxl_find_nvdimm_bridgeh]j] )}(hj h]hcxl_find_nvdimm_bridge}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjܒ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj} hhhj hK7ubjv )}(h(struct cxl_port *port)h]j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_find_nvdimm_bridgeasbuh1hhj ubjF )}(h h]h }(hj7 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjE hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hporth]hport}(hjR hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubah }(h ]h ]h"]h$]h&]hhuh1ju hj} hhhj hK7ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjy hhhj hK7ubah }(h ]jt ah ](j j eh"]h$]h&]j j )j huh1j' hj hK7hjv hhubj )}(hhh]j] )}(h'find a bridge device relative to a porth]h'find a bridge device relative to a port}(hj| hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK7hjy hhubah }(h ]h ]h"]h$]h&]uh1j hjv hhhj hK7ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hn**Parameters**
``struct cxl_port *port``
any descendant port of an nvdimm-bridge associated
root-cxl-porth](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK;hj ubjo )}(hhh]jt )}(hZ``struct cxl_port *port``
any descendant port of an nvdimm-bridge associated
root-cxl-porth](jz )}(h``struct cxl_port *port``h]j )}(hj h]hstruct cxl_port *port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK8hj ubj )}(hhh]j] )}(h@any descendant port of an nvdimm-bridge associated
root-cxl-porth]h@any descendant port of an nvdimm-bridge associated
root-cxl-port}(hj֓ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjғ hK8hjӓ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjғ hK8hj ubah }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'devm_cxl_add_nvdimm_bridge (C function) c.devm_cxl_add_nvdimm_bridgehNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hbstruct cxl_nvdimm_bridge * devm_cxl_add_nvdimm_bridge (struct device *host, struct cxl_port *port)h]j. )}(h`struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, struct cxl_port *port)h](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKwubjF )}(h h]h }(hj$ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj# hKwubh)}(hhh]j] )}(hcxl_nvdimm_bridgeh]hcxl_nvdimm_bridge}(hj5 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj2 ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj7 modnameN classnameNj j )}j ]j )}j devm_cxl_add_nvdimm_bridgesb c.devm_cxl_add_nvdimm_bridgeasbuh1hhj hhhj# hKwubjF )}(h h]h }(hjV hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj# hKwubj )}(hj h]h*}(hjd hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhj# hKwubjW )}(hdevm_cxl_add_nvdimm_bridgeh]j] )}(hjS h]hdevm_cxl_add_nvdimm_bridge}(hju hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj# hKwubjv )}(h,(struct device *host, struct cxl_port *port)h](j| )}(hstruct device *hosth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hdeviceh]hdevice}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]jQ c.devm_cxl_add_nvdimm_bridgeasbuh1hhj ubjF )}(h h]h }(hj̔ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjڔ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hhosth]hhost}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj
hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]jQ c.devm_cxl_add_nvdimm_bridgeasbuh1hhj ubjF )}(h h]h }(hj< hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjJ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hporth]hport}(hjW hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj# hKwubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj# hKwubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj# hKwhj hhubj )}(hhh]j] )}(h$add the root of a LIBNVDIMM topologyh]h$add the root of a LIBNVDIMM topology}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKwhj~ hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj# hKwubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(h**Parameters**
``struct device *host``
platform firmware root device
``struct cxl_port *port``
CXL port at the root of a CXL topology
**Return**
bridge device that can host cxl_nvdimm objectsh](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK{hj ubjo )}(hhh](jt )}(h6``struct device *host``
platform firmware root device
h](jz )}(h``struct device *host``h]j )}(hj h]hstruct device *host}(hjĕ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKxhj ubj )}(hhh]j] )}(h platform firmware root deviceh]h platform firmware root device}(hjە hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjו hKxhjؕ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjו hKxhj ubjt )}(hA``struct cxl_port *port``
CXL port at the root of a CXL topology
h](jz )}(h``struct cxl_port *port``h]j )}(hj h]hstruct cxl_port *port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKyhj ubj )}(hhh]j] )}(h&CXL port at the root of a CXL topologyh]h&CXL port at the root of a CXL topology}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKyhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKyhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hj6 h]hReturn}(hj8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj4 ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.c hK{hj ubj] )}(h.bridge device that can host cxl_nvdimm objectsh]h.bridge device that can host cxl_nvdimm objects}(hjL hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chK{hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j devm_cxl_add_nvdimm (C function)c.devm_cxl_add_nvdimmhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hPint devm_cxl_add_nvdimm (struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h]j. )}(hOint devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h](j4 )}(hinth]hint}(hj{ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjw hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw hhhj hKubjW )}(hdevm_cxl_add_nvdimmh]j] )}(hdevm_cxl_add_nvdimmh]hdevm_cxl_add_nvdimm}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjw hhhj hKubjv )}(h8(struct cxl_port *parent_port, struct cxl_memdev *cxlmd)h](j| )}(h struct cxl_port *parent_porth](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hjŖ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj֖ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjӖ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjؖ modnameN classnameNj j )}j ]j )}j j sbc.devm_cxl_add_nvdimmasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(h parent_porth]h parent_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hstruct cxl_memdev *cxlmdh](j )}(hj h]hstruct}(hj* hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj& ubjF )}(h h]h }(hj7 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& ubh)}(hhh]j] )}(h
cxl_memdevh]h
cxl_memdev}(hjH hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjE ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjJ modnameN classnameNj j )}j ]j c.devm_cxl_add_nvdimmasbuh1hhj& ubjF )}(h h]h }(hjf hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& ubj )}(hj h]h*}(hjt hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj& ubj] )}(hcxlmdh]hcxlmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj& ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjw hhhj hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjs hhhj hKubah }(h ]jn ah ](j j eh"]h$]h&]j j )j huh1j' hj hKhjp hhubj )}(hhh]j] )}(h/add a bridge between a cxl_memdev and an nvdimmh]h/add a bridge between a cxl_memdev and an nvdimm}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj hhubah }(h ]h ]h"]h$]h&]uh1j hjp hhhj hKubeh }(h ]h ](j functioneh"]h$]h&]j j j j× j j× j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_port *parent_port``
parent port for the (to be added) **cxlmd** endpoint port
``struct cxl_memdev *cxlmd``
cxl_memdev instance that will perform LIBNVDIMM operations
**Return**
0 on success negative error code on failure.h](j] )}(h**Parameters**h]j )}(hj͗ h]h
Parameters}(hjϗ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj˗ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjǗ ubjo )}(hhh](jt )}(h[``struct cxl_port *parent_port``
parent port for the (to be added) **cxlmd** endpoint port
h](jz )}(h ``struct cxl_port *parent_port``h]j )}(hj h]h struct cxl_port *parent_port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj ubj )}(hhh]j] )}(h9parent port for the (to be added) **cxlmd** endpoint porth](h"parent port for the (to be added) }(hj hhhNhNubj )}(h **cxlmd**h]hcxlmd}(hj
hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh endpoint port}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(hX``struct cxl_memdev *cxlmd``
cxl_memdev instance that will perform LIBNVDIMM operations
h](jz )}(h ``struct cxl_memdev *cxlmd``h]j )}(hj7 h]hstruct cxl_memdev *cxlmd}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj5 ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhj1 ubj )}(hhh]j] )}(h:cxl_memdev instance that will perform LIBNVDIMM operationsh]h:cxl_memdev instance that will perform LIBNVDIMM operations}(hjP hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjL hKhjM ubah }(h ]h ]h"]h$]h&]uh1j hj1 ubeh }(h ]h ]h"]h$]h&]uh1js hjL hKhj ubeh }(h ]h ]h"]h$]h&]uh1jn hjǗ ubj] )}(h
**Return**h]j )}(hjr h]hReturn}(hjt hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjǗ ubj] )}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:463: ./drivers/cxl/core/pmem.chKhjǗ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(hXv CXL device capabilities are enumerated by PCI DVSEC (Designated
Vendor-specific) and / or descriptors provided by platform firmware.
They can be defined as a set like the device and component registers
mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
Extended Capabilities, or they can be individual capabilities
appended to bridged and endpoint devices.h]hXv CXL device capabilities are enumerated by PCI DVSEC (Designated
Vendor-specific) and / or descriptors provided by platform firmware.
They can be defined as a set like the device and component registers
mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
Extended Capabilities, or they can be individual capabilities
appended to bridged and endpoint devices.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhju. hhubj] )}(hVProvide common infrastructure for enumerating and mapping these
discrete capabilities.h]hVProvide common infrastructure for enumerating and mapping these
discrete capabilities.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:466: ./drivers/cxl/core/regs.chKhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j %cxl_probe_component_regs (C function)c.cxl_probe_component_regshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hivoid cxl_probe_component_regs (struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h]j. )}(hhvoid cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](j4 )}(hvoidh]hvoid}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjј hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjј hhhj hK ubjW )}(hcxl_probe_component_regsh]j] )}(hcxl_probe_component_regsh]hcxl_probe_component_regs}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjј hhhj hK ubjv )}(hK(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map)h](j| )}(hstruct device *devh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hdeviceh]hdevice}(hj0 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj- ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj2 modnameN classnameNj j )}j ]j )}j j sbc.cxl_probe_component_regsasbuh1hhj ubjF )}(h h]h }(hjP hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hdevh]hdev}(hjk hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj
ubj| )}(hvoid __iomem *baseh](j4 )}(hvoidh]hvoid}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh__iomem}(hj hhhNhNubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hbaseh]hbase}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj
ubj| )}(h!struct cxl_component_reg_map *maph](j )}(hj h]hstruct}(hjؙ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjԙ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjԙ ubh)}(hhh]j] )}(hcxl_component_reg_maph]hcxl_component_reg_map}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]jL c.cxl_probe_component_regsasbuh1hhjԙ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjԙ ubj )}(hj h]h*}(hj" hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjԙ ubj] )}(hmaph]hmap}(hj/ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjԙ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj
ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjј hhhj hK ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj͘ hhhj hK ubah }(h ]jȘ ah ](j j eh"]h$]h&]j j )j huh1j' hj hK hjʘ hhubj )}(hhh]j] )}(h$Detect CXL Component register blocksh]h$Detect CXL Component register blocks}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hjV hhubah }(h ]h ]h"]h$]h&]uh1j hjʘ hhhj hK ubeh }(h ]h ](j functioneh"]h$]h&]j j j jq j jq j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct device *dev``
Host device of the **base** mapping
``void __iomem *base``
Mapping containing the HDM Decoder Capability Header
``struct cxl_component_reg_map *map``
Map object describing the register block information found
**Description**
See CXL 2.0 8.2.4 Component Register Layout and Definition
See CXL 2.0 8.2.5.5 CXL Device Register Interface
Probe for component register information and return it in map object.h](j] )}(h**Parameters**h]j )}(hj{ h]h
Parameters}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjy ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hju ubjo )}(hhh](jt )}(h;``struct device *dev``
Host device of the **base** mapping
h](jz )}(h``struct device *dev``h]j )}(hj h]hstruct device *dev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hj ubj )}(hhh]j] )}(h#Host device of the **base** mappingh](hHost device of the }(hj hhhNhNubj )}(h**base**h]hbase}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh mapping}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hK hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hK hj ubjt )}(hL``void __iomem *base``
Mapping containing the HDM Decoder Capability Header
h](jz )}(h``void __iomem *base``h]j )}(hj h]hvoid __iomem *base}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hjߚ ubj )}(hhh]j] )}(h4Mapping containing the HDM Decoder Capability Headerh]h4Mapping containing the HDM Decoder Capability Header}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hK hj ubah }(h ]h ]h"]h$]h&]uh1j hjߚ ubeh }(h ]h ]h"]h$]h&]uh1js hj hK hj ubjt )}(ha``struct cxl_component_reg_map *map``
Map object describing the register block information found
h](jz )}(h%``struct cxl_component_reg_map *map``h]j )}(hj h]h!struct cxl_component_reg_map *map}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hj ubj )}(hhh]j] )}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj3 hK hj4 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj3 hK hj ubeh }(h ]h ]h"]h$]h&]uh1jn hju ubj] )}(h**Description**h]j )}(hjY h]h Description}(hj[ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK!hju ubj] )}(hlSee CXL 2.0 8.2.4 Component Register Layout and Definition
See CXL 2.0 8.2.5.5 CXL Device Register Interfaceh]hlSee CXL 2.0 8.2.4 Component Register Layout and Definition
See CXL 2.0 8.2.5.5 CXL Device Register Interface}(hjo hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK hju ubj] )}(hEProbe for component register information and return it in map object.h]hEProbe for component register information and return it in map object.}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chK#hju ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j "cxl_probe_device_regs (C function)c.cxl_probe_device_regshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hcvoid cxl_probe_device_regs (struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h]j. )}(hbvoid cxl_probe_device_regs(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](j4 )}(hvoidh]hvoid}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKpubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKpubjW )}(hcxl_probe_device_regsh]j] )}(hcxl_probe_device_regsh]hcxl_probe_device_regs}(hjΛ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjʛ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKpubjv )}(hH(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map)h](j| )}(hstruct device *devh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hdeviceh]hdevice}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj
modnameN classnameNj j )}j ]j )}j jЛ sbc.cxl_probe_device_regsasbuh1hhj ubjF )}(h h]h }(hj( hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj6 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hdevh]hdev}(hjC hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hvoid __iomem *baseh](j4 )}(hvoidh]hvoid}(hj\ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjX ubjF )}(h h]h }(hjj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjX ubh__iomem}(hjX hhhNhNubjF )}(h h]h }(hj| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjX ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjX ubj] )}(hbaseh]hbase}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjX ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h struct cxl_device_reg_map *maph](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_device_reg_maph]hcxl_device_reg_map}(hjΜ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj˜ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjМ modnameN classnameNj j )}j ]j$ c.cxl_probe_device_regsasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmaph]hmap}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hKpubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKpubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKphj hhubj )}(hhh]j] )}(h!Detect CXL Device register blocksh]h!Detect CXL Device register blocks}(hj1 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKphj. hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKpubeh }(h ]h ](j functioneh"]h$]h&]j j j jI j jI j j j uh1j" hhhju. hNhNubj )}(hXS **Parameters**
``struct device *dev``
Host device of the **base** mapping
``void __iomem *base``
Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
``struct cxl_device_reg_map *map``
Map object describing the register block information found
**Description**
Probe for device register information and return it in map object.h](j] )}(h**Parameters**h]j )}(hjS h]h
Parameters}(hjU hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjQ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKthjM ubjo )}(hhh](jt )}(h;``struct device *dev``
Host device of the **base** mapping
h](jz )}(h``struct device *dev``h]j )}(hjr h]hstruct device *dev}(hjt hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjp ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKqhjl ubj )}(hhh]j] )}(h#Host device of the **base** mappingh](hHost device of the }(hj hhhNhNubj )}(h**base**h]hbase}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh mapping}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hKqhj ubah }(h ]h ]h"]h$]h&]uh1j hjl ubeh }(h ]h ]h"]h$]h&]uh1js hj hKqhji ubjt )}(hN``void __iomem *base``
Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
h](jz )}(h``void __iomem *base``h]j )}(hj h]hvoid __iomem *base}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKrhj ubj )}(hhh]j] )}(h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interfaceh]h6Mapping of CXL 2.0 8.2.8 CXL Device Register Interface}(hj֝ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjҝ hKrhjӝ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjҝ hKrhji ubjt )}(h^``struct cxl_device_reg_map *map``
Map object describing the register block information found
h](jz )}(h"``struct cxl_device_reg_map *map``h]j )}(hj h]h struct cxl_device_reg_map *map}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKshj ubj )}(hhh]j] )}(h:Map object describing the register block information foundh]h:Map object describing the register block information found}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKshj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKshji ubeh }(h ]h ]h"]h$]h&]uh1jn hjM ubj] )}(h**Description**h]j )}(hj1 h]h Description}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj/ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKuhjM ubj] )}(hBProbe for device register information and return it in map object.h]hBProbe for device register information and return it in map object.}(hjG hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chKthjM ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'cxl_find_regblock_instance (C function) c.cxl_find_regblock_instancehNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hint cxl_find_regblock_instance (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h]j. )}(hint cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](j4 )}(hinth]hint}(hjv hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjr hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjr hhhj hM\ubjW )}(hcxl_find_regblock_instanceh]j] )}(hcxl_find_regblock_instanceh]hcxl_find_regblock_instance}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjr hhhj hM\ubjv )}(hc(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, unsigned int index)h](j| )}(hstruct pci_dev *pdevh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hpci_devh]hpci_dev}(hjў hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjΞ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjӞ modnameN classnameNj j )}j ]j )}j j sb c.cxl_find_regblock_instanceasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hpdevh]hpdev}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(henum cxl_regloc_type typeh](j )}(henumh]henum}(hj% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubjF )}(h h]h }(hj3 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubh)}(hhh]j] )}(hcxl_regloc_typeh]hcxl_regloc_type}(hjD hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjA ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjF modnameN classnameNj j )}j ]j c.cxl_find_regblock_instanceasbuh1hhj! ubjF )}(h h]h }(hjb hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubj] )}(htypeh]htype}(hjp hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj! ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h struct cxl_register_map *maph](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_register_maph]hcxl_register_map}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_find_regblock_instanceasbuh1hhj ubjF )}(h h]h }(hjş hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjӟ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmaph]hmap}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hunsigned int indexh](j4 )}(hunsignedh]hunsigned}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj ubjF )}(h h]h }(hj# hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hindexh]hindex}(hj1 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjr hhhj hM\ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjn hhhj hM\ubah }(h ]ji ah ](j j eh"]h$]h&]j j )j huh1j' hj hM\hjk hhubj )}(hhh]j] )}(h'Locate a register block by type / indexh]h'Locate a register block by type / index}(hj[ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM\hjX hhubah }(h ]h ]h"]h$]h&]uh1j hjk hhhj hM\ubeh }(h ]h ](j functioneh"]h$]h&]j j j js j js j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct pci_dev *pdev``
The CXL PCI device to enumerate.
``enum cxl_regloc_type type``
Register Block Indicator id
``struct cxl_register_map *map``
Enumeration output, clobbered on error
``unsigned int index``
Index into which particular instance of a regblock wanted in the
order found in register locator DVSEC.
**Return**
0 if register block enumerated, negative error code otherwise
**Description**
A CXL DVSEC may point to one or more register blocks, search for them
by **type** and **index**.h](j] )}(h**Parameters**h]j )}(hj} h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj{ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hjw ubjo )}(hhh](jt )}(h:``struct pci_dev *pdev``
The CXL PCI device to enumerate.
h](jz )}(h``struct pci_dev *pdev``h]j )}(hj h]hstruct pci_dev *pdev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM]hj ubj )}(hhh]j] )}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM]hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM]hj ubjt )}(h:``enum cxl_regloc_type type``
Register Block Indicator id
h](jz )}(h ``enum cxl_regloc_type type``h]j )}(hjՠ h]henum cxl_regloc_type type}(hjנ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjӠ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM^hjϠ ubj )}(hhh]j] )}(hRegister Block Indicator idh]hRegister Block Indicator id}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM^hj ubah }(h ]h ]h"]h$]h&]uh1j hjϠ ubeh }(h ]h ]h"]h$]h&]uh1js hj hM^hj ubjt )}(hH``struct cxl_register_map *map``
Enumeration output, clobbered on error
h](jz )}(h ``struct cxl_register_map *map``h]j )}(hj h]h struct cxl_register_map *map}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM_hj ubj )}(hhh]j] )}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hj' hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj# hM_hj$ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj# hM_hj ubjt )}(h``unsigned int index``
Index into which particular instance of a regblock wanted in the
order found in register locator DVSEC.
h](jz )}(h``unsigned int index``h]j )}(hjG h]hunsigned int index}(hjI hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjE ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMahjA ubj )}(hhh]j] )}(hgIndex into which particular instance of a regblock wanted in the
order found in register locator DVSEC.h]hgIndex into which particular instance of a regblock wanted in the
order found in register locator DVSEC.}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chM`hj] ubah }(h ]h ]h"]h$]h&]uh1j hjA ubeh }(h ]h ]h"]h$]h&]uh1js hj\ hMahj ubeh }(h ]h ]h"]h$]h&]uh1jn hjw ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjw ubj] )}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMchjw ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMehjw ubj] )}(h`A CXL DVSEC may point to one or more register blocks, search for them
by **type** and **index**.h](hIA CXL DVSEC may point to one or more register blocks, search for them
by }(hj hhhNhNubj )}(h**type**h]htype}(hjȡ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh and }(hj hhhNhNubj )}(h **index**h]hindex}(hjڡ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMdhjw ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_find_regblock (C function)c.cxl_find_regblockhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(heint cxl_find_regblock (struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h]j. )}(hdint cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMpubjF )}(h h]h }(hj" hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj! hMpubjW )}(hcxl_find_regblockh]j] )}(hcxl_find_regblockh]hcxl_find_regblock}(hj4 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj0 ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj! hMpubjv )}(hO(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map)h](j| )}(hstruct pci_dev *pdevh](j )}(hj h]hstruct}(hjP hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjL ubjF )}(h h]h }(hj] hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjL ubh)}(hhh]j] )}(hpci_devh]hpci_dev}(hjn hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjk ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjp modnameN classnameNj j )}j ]j )}j j6 sbc.cxl_find_regblockasbuh1hhjL ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjL ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjL ubj] )}(hpdevh]hpdev}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjL ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjH ubj| )}(henum cxl_regloc_type typeh](j )}(hj' h]henum}(hj¢ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hjϢ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_regloc_typeh]hcxl_regloc_type}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjݢ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_find_regblockasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(htypeh]htype}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjH ubj| )}(h struct cxl_register_map *maph](j )}(hj h]hstruct}(hj% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubjF )}(h h]h }(hj2 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubh)}(hhh]j] )}(hcxl_register_maph]hcxl_register_map}(hjC hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj@ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjE modnameN classnameNj j )}j ]j c.cxl_find_regblockasbuh1hhj! ubjF )}(h h]h }(hja hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubj )}(hj h]h*}(hjo hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubj] )}(hmaph]hmap}(hj| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj! ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjH ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj! hMpubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj! hMpubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj! hMphj hhubj )}(hhh]j] )}(h Locate register blocks by typeh]h Locate register blocks by type}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMphj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj! hMpubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct pci_dev *pdev``
The CXL PCI device to enumerate.
``enum cxl_regloc_type type``
Register Block Indicator id
``struct cxl_register_map *map``
Enumeration output, clobbered on error
**Return**
0 if register block enumerated, negative error code otherwise
**Description**
A CXL DVSEC may point to one or more register blocks, search for them
by **type**.h](j] )}(h**Parameters**h]j )}(hjȣ h]h
Parameters}(hjʣ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjƣ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMthj£ ubjo )}(hhh](jt )}(h:``struct pci_dev *pdev``
The CXL PCI device to enumerate.
h](jz )}(h``struct pci_dev *pdev``h]j )}(hj h]hstruct pci_dev *pdev}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMqhj ubj )}(hhh]j] )}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMqhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMqhjޣ ubjt )}(h:``enum cxl_regloc_type type``
Register Block Indicator id
h](jz )}(h ``enum cxl_regloc_type type``h]j )}(hj h]henum cxl_regloc_type type}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMrhj ubj )}(hhh]j] )}(hRegister Block Indicator idh]hRegister Block Indicator id}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj5 hMrhj6 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj5 hMrhjޣ ubjt )}(hH``struct cxl_register_map *map``
Enumeration output, clobbered on error
h](jz )}(h ``struct cxl_register_map *map``h]j )}(hjY h]h struct cxl_register_map *map}(hj[ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMshjS ubj )}(hhh]j] )}(h&Enumeration output, clobbered on errorh]h&Enumeration output, clobbered on error}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjn hMshjo ubah }(h ]h ]h"]h$]h&]uh1j hjS ubeh }(h ]h ]h"]h$]h&]uh1js hjn hMshjޣ ubeh }(h ]h ]h"]h$]h&]uh1jn hj£ ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhj£ ubj] )}(h=0 if register block enumerated, negative error code otherwiseh]h=0 if register block enumerated, negative error code otherwise}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMuhj£ ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMwhj£ ubj] )}(hRA CXL DVSEC may point to one or more register blocks, search for them
by **type**.h](hIA CXL DVSEC may point to one or more register blocks, search for them
by }(hjѤ hhhNhNubj )}(h**type**h]htype}(hj٤ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjѤ ubh.}(hjѤ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMvhj£ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_count_regblock (C function)c.cxl_count_regblockhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hHint cxl_count_regblock (struct pci_dev *pdev, enum cxl_regloc_type type)h]j. )}(hGint cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMubjF )}(h h]h }(hj! hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMubjW )}(hcxl_count_regblockh]j] )}(hcxl_count_regblockh]hcxl_count_regblock}(hj3 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj/ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMubjv )}(h1(struct pci_dev *pdev, enum cxl_regloc_type type)h](j| )}(hstruct pci_dev *pdevh](j )}(hj h]hstruct}(hjO hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjK ubjF )}(h h]h }(hj\ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjK ubh)}(hhh]j] )}(hpci_devh]hpci_dev}(hjm hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjo modnameN classnameNj j )}j ]j )}j j5 sbc.cxl_count_regblockasbuh1hhjK ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjK ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjK ubj] )}(hpdevh]hpdev}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjK ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjG ubj| )}(henum cxl_regloc_type typeh](j )}(hj' h]henum}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hjΥ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_regloc_typeh]hcxl_regloc_type}(hjߥ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjܥ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_count_regblockasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(htypeh]htype}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjG ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj
hhhj hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhj hhubj )}(hhh]j] )}(h)Count instances of a given regblock type.h]h)Count instances of a given regblock type.}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj2 hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jM j jM j j j uh1j" hhhju. hNhNubj )}(hX* **Parameters**
``struct pci_dev *pdev``
The CXL PCI device to enumerate.
``enum cxl_regloc_type type``
Register Block Indicator id
**Description**
Some regblocks may be repeated. Count how many instances.
**Return**
non-negative count of matching regblocks, negative error code otherwise.h](j] )}(h**Parameters**h]j )}(hjW h]h
Parameters}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjU ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjQ ubjo )}(hhh](jt )}(h:``struct pci_dev *pdev``
The CXL PCI device to enumerate.
h](jz )}(h``struct pci_dev *pdev``h]j )}(hjv h]hstruct pci_dev *pdev}(hjx hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjt ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjp ubj )}(hhh]j] )}(h The CXL PCI device to enumerate.h]h The CXL PCI device to enumerate.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hjp ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhjm ubjt )}(h:``enum cxl_regloc_type type``
Register Block Indicator id
h](jz )}(h ``enum cxl_regloc_type type``h]j )}(hj h]henum cxl_regloc_type type}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhj ubj )}(hhh]j] )}(hRegister Block Indicator idh]hRegister Block Indicator id}(hjȦ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjĦ hMhjŦ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjĦ hMhjm ubeh }(h ]h ]h"]h$]h&]uh1jn hjQ ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjQ ubj] )}(h9Some regblocks may be repeated. Count how many instances.h]h9Some regblocks may be repeated. Count how many instances.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjQ ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjQ ubj] )}(hHnon-negative count of matching regblocks, negative error code otherwise.h]hHnon-negative count of matching regblocks, negative error code otherwise.}(hj' hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:469: ./drivers/cxl/core/regs.chMhjQ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(hX Core implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The
implementation is used by the cxl_pci driver to initialize the device
and implement the cxl_mem.h IOCTL UAPI. It also implements the
backend of the cxl_pmem_ctl() transport for LIBNVDIMM.h]hX Core implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The
implementation is used by the cxl_pci driver to initialize the device
and implement the cxl_mem.h IOCTL UAPI. It also implements the
backend of the cxl_pmem_ctl() transport for LIBNVDIMM.}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:472: ./drivers/cxl/core/mbox.chKhju. hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j "cxl_internal_send_cmd (C function)c.cxl_internal_send_cmdhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hWint cxl_internal_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]j. )}(hVint cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](j4 )}(hinth]hint}(hje hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hja hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKubjF )}(h h]h }(hjt hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hja hhhjs hKubjW )}(hcxl_internal_send_cmdh]j] )}(hcxl_internal_send_cmdh]hcxl_internal_send_cmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hja hhhjs hKubjv )}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](j| )}(h struct cxl_mailbox *cxl_mboxh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mailboxh]h cxl_mailbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj§ modnameN classnameNj j )}j ]j )}j j sbc.cxl_internal_send_cmdasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxl_mboxh]hcxl_mbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h struct cxl_mbox_cmd *mbox_cmdh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj! hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj2 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj/ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj4 modnameN classnameNj j )}j ]jܧ c.cxl_internal_send_cmdasbuh1hhj ubjF )}(h h]h }(hjP hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmbox_cmdh]hmbox_cmd}(hjk hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hja hhhjs hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj] hhhjs hKubah }(h ]jX ah ](j j eh"]h$]h&]j j )j huh1j' hjs hKhjZ hhubj )}(hhh]j] )}(h3Kernel internal interface to send a mailbox commandh]h3Kernel internal interface to send a mailbox command}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj hhubah }(h ]h ]h"]h$]h&]uh1j hjZ hhhjs hKubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
``struct cxl_mbox_cmd *mbox_cmd``
initialized command to execute
**Context**
Any context.
**Return**
* %>=0 - Number of bytes returned in **out**.
* ``-E2BIG`` - Payload is too large for hardware.
* ``-EBUSY`` - Couldn't acquire exclusive mailbox access.
* ``-EFAULT`` - Hardware error occurred.
* ``-ENXIO`` - Command completed, but device reported an error.
* ``-EIO`` - Unexpected output size.
**Description**
Mailbox commands may execute successfully yet the device itself reported an
error. While this distinction can be useful for commands from userspace, the
kernel will only be able to use results when both are successful.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubjo )}(hhh](jt )}(h5``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
h](jz )}(h ``struct cxl_mailbox *cxl_mbox``h]j )}(hj֨ h]h struct cxl_mailbox *cxl_mbox}(hjب hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjԨ ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjШ ubj )}(hhh]j] )}(hCXL mailbox contexth]hCXL mailbox context}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hjШ ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhjͨ ubjt )}(hA``struct cxl_mbox_cmd *mbox_cmd``
initialized command to execute
h](jz )}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j )}(hj h]h struct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubj )}(hhh]j] )}(h initialized command to executeh]h initialized command to execute}(hj( hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj$ hKhj% ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj$ hKhjͨ ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h **Context**h]j )}(hjJ h]hContext}(hjL hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjH ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubj] )}(h Any context.h]h Any context.}(hj` hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubj] )}(h
**Return**h]j )}(hjq h]hReturn}(hjs hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjo ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubj )}(hhh](j )}(h0%>=0 - Number of bytes returned in **out**.h]j] )}(hj h](h(%>=0 - Number of bytes returned in }(hj hhhNhNubj )}(h**out**h]hout}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h1``-E2BIG`` - Payload is too large for hardware.h]j] )}(hj h](j )}(h
``-E2BIG``h]h-E2BIG}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh' - Payload is too large for hardware.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h9``-EBUSY`` - Couldn't acquire exclusive mailbox access.h]j] )}(hjܩ h](j )}(h
``-EBUSY``h]h-EBUSY}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjީ ubh1 - Couldn’t acquire exclusive mailbox access.}(hjީ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjک ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h'``-EFAULT`` - Hardware error occurred.h]j] )}(hj h](j )}(h ``-EFAULT``h]h-EFAULT}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh - Hardware error occurred.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h?``-ENXIO`` - Command completed, but device reported an error.h]j] )}(hj( h](j )}(h
``-ENXIO``h]h-ENXIO}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj* ubh5 - Command completed, but device reported an error.}(hj* hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj& ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h'``-EIO`` - Unexpected output size.
h]j] )}(h&``-EIO`` - Unexpected output size.h](j )}(h``-EIO``h]h-EIO}(hjT hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjP ubh - Unexpected output size.}(hjP hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhjL ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]j j uh1j hj hKhj ubj] )}(h**Description**h]j )}(hj{ h]h Description}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjy ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubj] )}(hMailbox commands may execute successfully yet the device itself reported an
error. While this distinction can be useful for commands from userspace, the
kernel will only be able to use results when both are successful.h]hMailbox commands may execute successfully yet the device itself reported an
error. While this distinction can be useful for commands from userspace, the
kernel will only be able to use results when both are successful.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chKhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j *cxl_payload_from_user_allowed (C function) c.cxl_payload_from_user_allowedhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hAbool cxl_payload_from_user_allowed (u16 opcode, void *payload_in)h]j. )}(h@bool cxl_payload_from_user_allowed(u16 opcode, void *payload_in)h](j4 )}(hj^ h]hbool}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7ubjF )}(h h]h }(hjΪ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhjͪ hM7ubjW )}(h cxl_payload_from_user_allowedh]j] )}(h cxl_payload_from_user_allowedh]h cxl_payload_from_user_allowed}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjܪ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhjͪ hM7ubjv )}(h (u16 opcode, void *payload_in)h](j| )}(h
u16 opcodeh](h)}(hhh]j] )}(hu16h]hu16}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j j sb c.cxl_payload_from_user_allowedasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hopcodeh]hopcode}(hj- hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h& ]noemphhhuh1j{ hj ubj| )}(hvoid *payload_inh](j4 )}(hvoidh]hvoid}(hjF hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjB ubjF )}(h h]h }(hjT hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjB ubj )}(hj h]h*}(hjb hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjB ubj] )}(h
payload_inh]h
payload_in}(hjo hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjB ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhjͪ hM7ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhjͪ hM7ubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hjͪ hM7hj hhubj )}(hhh]j] )}(h Check contents of in_payload.h]h Check contents of in_payload.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7hj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhjͪ hM7ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``u16 opcode``
The mailbox command opcode.
``void *payload_in``
Pointer to the input payload passed in from user space.
**Return**
* true - payload_in passes check for **opcode**.
* false - payload_in contains invalid or unsupported values.
**Description**
The driver may inspect payload contents before sending a mailbox
command from user space to the device. The intent is to reject
commands with input payloads that are known to be unsafe. This
check is not intended to replace the users careful selection of
mailbox command parameters and makes no guarantee that the user
command will succeed, nor that it is appropriate.
The specific checks are determined by the opcode.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hj ubjo )}(hhh](jt )}(h+``u16 opcode``
The mailbox command opcode.
h](jz )}(h``u16 opcode``h]j )}(hjګ h]h
u16 opcode}(hjܫ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjث ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM8hjԫ ubj )}(hhh]j] )}(hThe mailbox command opcode.h]hThe mailbox command opcode.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM8hj ubah }(h ]h ]h"]h$]h&]uh1j hjԫ ubeh }(h ]h ]h"]h$]h&]uh1js hj hM8hjѫ ubjt )}(hM``void *payload_in``
Pointer to the input payload passed in from user space.
h](jz )}(h``void *payload_in``h]j )}(hj h]hvoid *payload_in}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM9hj
ubj )}(hhh]j] )}(h7Pointer to the input payload passed in from user space.h]h7Pointer to the input payload passed in from user space.}(hj, hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj( hM9hj) ubah }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]uh1js hj( hM9hjѫ ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hjN h]hReturn}(hjP hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjL ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hj ubj )}(hhh](j )}(h3true - payload_in passes check for **opcode**.h]j] )}(hji h](h(true - payload_in passes check for }(hjk hhhNhNubj )}(h
**opcode**h]hopcode}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjk ubh.}(hjk hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hjg ubah }(h ]h ]h"]h$]h&]uh1j hjd ubj )}(h?false - payload_in contains invalid or unsupported values.
h]j] )}(h>false - payload_in contains invalid or unsupported values.h]h>false - payload_in contains invalid or unsupported values.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hj ubah }(h ]h ]h"]h$]h&]uh1j hjd ubeh }(h ]h ]h"]h$]h&]j j uh1j hj hM;hj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hj ubj] )}(hXp The driver may inspect payload contents before sending a mailbox
command from user space to the device. The intent is to reject
commands with input payloads that are known to be unsafe. This
check is not intended to replace the users careful selection of
mailbox command parameters and makes no guarantee that the user
command will succeed, nor that it is appropriate.h]hXp The driver may inspect payload contents before sending a mailbox
command from user space to the device. The intent is to reject
commands with input payloads that are known to be unsafe. This
check is not intended to replace the users careful selection of
mailbox command parameters and makes no guarantee that the user
command will succeed, nor that it is appropriate.}(hjȬ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hj ubj] )}(h1The specific checks are determined by the opcode.h]h1The specific checks are determined by the opcode.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMEhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'cxl_validate_cmd_from_user (C function) c.cxl_validate_cmd_from_userhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hint cxl_validate_cmd_from_user (struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h]j. )}(hint cxl_validate_cmd_from_user(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMubjW )}(hcxl_validate_cmd_from_userh]j] )}(hcxl_validate_cmd_from_userh]hcxl_validate_cmd_from_user}(hj' hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj# ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMubjv )}(hf(struct cxl_mbox_cmd *mbox_cmd, struct cxl_mailbox *cxl_mbox, const struct cxl_send_command *send_cmd)h](j| )}(h struct cxl_mbox_cmd *mbox_cmdh](j )}(hj h]hstruct}(hjC hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj? ubjF )}(h h]h }(hjP hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj? ubh)}(hhh]j] )}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hja hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj^ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjc modnameN classnameNj j )}j ]j )}j j) sb c.cxl_validate_cmd_from_userasbuh1hhj? ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj? ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj? ubj] )}(hmbox_cmdh]hmbox_cmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj? ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj; ubj| )}(h struct cxl_mailbox *cxl_mboxh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mailboxh]h cxl_mailbox}(hjӭ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjЭ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjխ modnameN classnameNj j )}j ]j} c.cxl_validate_cmd_from_userasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxl_mboxh]hcxl_mbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj; ubj| )}(h'const struct cxl_send_command *send_cmdh](j )}(hjU h]hconst}(hj% hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubjF )}(h h]h }(hj2 hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubj )}(hj h]hstruct}(hj@ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubjF )}(h h]h }(hjM hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubh)}(hhh]j] )}(hcxl_send_commandh]hcxl_send_command}(hj^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj` modnameN classnameNj j )}j ]j} c.cxl_validate_cmd_from_userasbuh1hhj! ubjF )}(h h]h }(hj| hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj! ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj! ubj] )}(hsend_cmdh]hsend_cmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj! ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj; ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMhj hhubj )}(hhh]j] )}(h&Check fields for CXL_MEM_SEND_COMMAND.h]h&Check fields for CXL_MEM_SEND_COMMAND.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jٮ j jٮ j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_mbox_cmd *mbox_cmd``
Sanitized and populated :c:type:`struct cxl_mbox_cmd `.
``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
``const struct cxl_send_command *send_cmd``
:c:type:`struct cxl_send_command ` copied in from userspace.
**Return**
* ``0`` - **out_cmd** is ready to send.
* ``-ENOTTY`` - Invalid command specified.
* ``-EINVAL`` - Reserved fields or invalid values were used.
* ``-ENOMEM`` - Input or output buffer wasn't sized properly.
* ``-EPERM`` - Attempted to use a protected command.
* ``-EBUSY`` - Kernel has claimed exclusive access to this opcode
**Description**
The result of this command is a fully validated command in **mbox_cmd** that is
safe to send to the hardware.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjݮ ubjo )}(hhh](jt )}(hh``struct cxl_mbox_cmd *mbox_cmd``
Sanitized and populated :c:type:`struct cxl_mbox_cmd `.
h](jz )}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j )}(hj h]h struct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubj )}(hhh]j] )}(hESanitized and populated :c:type:`struct cxl_mbox_cmd `.h](hSanitized and populated }(hj hhhNhNubh)}(h,:c:type:`struct cxl_mbox_cmd `h]j )}(hj% h]hstruct cxl_mbox_cmd}(hj' hhhNhNubah }(h ]h ](xrefj c-typeeh"]h$]h&]uh1j hj# ubah }(h ]h ]h"]h$]h&]refdoc"driver-api/cxl/theory-of-operation refdomainj reftypetype refexplicitrefwarnj j )}j ]sb reftarget cxl_mbox_cmduh1hhj hMhj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h5``struct cxl_mailbox *cxl_mbox``
CXL mailbox context
h](jz )}(h ``struct cxl_mailbox *cxl_mbox``h]j )}(hjd h]h struct cxl_mailbox *cxl_mbox}(hjf hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjb ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj^ ubj )}(hhh]j] )}(hCXL mailbox contexth]hCXL mailbox context}(hj} hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjy hMhjz ubah }(h ]h ]h"]h$]h&]uh1j hj^ ubeh }(h ]h ]h"]h$]h&]uh1js hjy hMhj ubjt )}(h{``const struct cxl_send_command *send_cmd``
:c:type:`struct cxl_send_command ` copied in from userspace.
h](jz )}(h+``const struct cxl_send_command *send_cmd``h]j )}(hj h]h'const struct cxl_send_command *send_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubj )}(hhh]j] )}(hN:c:type:`struct cxl_send_command ` copied in from userspace.h](h)}(h4:c:type:`struct cxl_send_command `h]j )}(hj h]hstruct cxl_send_command}(hj hhhNhNubah }(h ]h ](j1 j c-typeeh"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]refdocj= refdomainj reftypetype refexplicitrefwarnj jC jF cxl_send_commanduh1hhj hMhj ubh copied in from userspace.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubeh }(h ]h ]h"]h$]h&]uh1jn hjݮ ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjݮ ubj )}(hhh](j )}(h,``0`` - **out_cmd** is ready to send.h]j] )}(hj h](j )}(h``0``h]h0}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh
- }(hj hhhNhNubj )}(h **out_cmd**h]hout_cmd}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh is ready to send.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubah }(h ]h ]h"]h$]h&]uh1j hj
ubj )}(h)``-ENOTTY`` - Invalid command specified.h]j] )}(hjJ h](j )}(h ``-ENOTTY``h]h-ENOTTY}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjL ubh - Invalid command specified.}(hjL hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjH ubah }(h ]h ]h"]h$]h&]uh1j hj
ubj )}(h;``-EINVAL`` - Reserved fields or invalid values were used.h]j] )}(hjp h](j )}(h ``-EINVAL``h]h-EINVAL}(hju hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjr ubh0 - Reserved fields or invalid values were used.}(hjr hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjn ubah }(h ]h ]h"]h$]h&]uh1j hj
ubj )}(h<``-ENOMEM`` - Input or output buffer wasn't sized properly.h]j] )}(hj h](j )}(h ``-ENOMEM``h]h-ENOMEM}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh3 - Input or output buffer wasn’t sized properly.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubah }(h ]h ]h"]h$]h&]uh1j hj
ubj )}(h4``-EPERM`` - Attempted to use a protected command.h]j] )}(hj h](j )}(h
``-EPERM``h]h-EPERM}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh* - Attempted to use a protected command.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubah }(h ]h ]h"]h$]h&]uh1j hj
ubj )}(hB``-EBUSY`` - Kernel has claimed exclusive access to this opcode
h]j] )}(hA``-EBUSY`` - Kernel has claimed exclusive access to this opcodeh](j )}(h
``-EBUSY``h]h-EBUSY}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh7 - Kernel has claimed exclusive access to this opcode}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubah }(h ]h ]h"]h$]h&]uh1j hj
ubeh }(h ]h ]h"]h$]h&]j j uh1j hjA hMhjݮ ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjݮ ubj] )}(hmThe result of this command is a fully validated command in **mbox_cmd** that is
safe to send to the hardware.h](h;The result of this command is a fully validated command in }(hj% hhhNhNubj )}(h **mbox_cmd**h]hmbox_cmd}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubh& that is
safe to send to the hardware.}(hj% hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjݮ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j )handle_mailbox_cmd_from_user (C function) c.handle_mailbox_cmd_from_userhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hint handle_mailbox_cmd_from_user (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h]j. )}(hint handle_mailbox_cmd_from_user(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](j4 )}(hinth]hint}(hjf hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjb hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7ubjF )}(h h]h }(hju hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjb hhhjt hM7ubjW )}(h handle_mailbox_cmd_from_userh]j] )}(h handle_mailbox_cmd_from_userh]h handle_mailbox_cmd_from_user}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjb hhhjt hM7ubjv )}(hj(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd, u64 out_payload, s32 *size_out, u32 *retval)h](j| )}(h struct cxl_mailbox *cxl_mboxh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mailboxh]h cxl_mailbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjñ modnameN classnameNj j )}j ]j )}j j sb c.handle_mailbox_cmd_from_userasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxl_mboxh]hcxl_mbox}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h struct cxl_mbox_cmd *mbox_cmdh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj" hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj3 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj0 ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj5 modnameN classnameNj j )}j ]jݱ c.handle_mailbox_cmd_from_userasbuh1hhj ubjF )}(h h]h }(hjQ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj_ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmbox_cmdh]hmbox_cmd}(hjl hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hu64 out_payloadh](h)}(hhh]j] )}(hu64h]hu64}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]jݱ c.handle_mailbox_cmd_from_userasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(h out_payloadh]h out_payload}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h
s32 *size_outh](h)}(hhh]j] )}(hs32h]hs32}(hjв hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjͲ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjҲ modnameN classnameNj j )}j ]jݱ c.handle_mailbox_cmd_from_userasbuh1hhjɲ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjɲ ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjɲ ubj] )}(hsize_outh]hsize_out}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjɲ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h u32 *retvalh](h)}(hhh]j] )}(hu32h]hu32}(hj% hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj" ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj' modnameN classnameNj j )}j ]jݱ c.handle_mailbox_cmd_from_userasbuh1hhj ubjF )}(h h]h }(hjC hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjQ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hretvalh]hretval}(hj^ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjb hhhjt hM7ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj^ hhhjt hM7ubah }(h ]jY ah ](j j eh"]h$]h&]j j )j huh1j' hjt hM7hj[ hhubj )}(hhh]j] )}(h)Dispatch a mailbox command for userspace.h]h)Dispatch a mailbox command for userspace.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM7hj hhubah }(h ]h ]h"]h$]h&]uh1j hj[ hhhjt hM7ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_mailbox *cxl_mbox``
The mailbox context for the operation.
``struct cxl_mbox_cmd *mbox_cmd``
The validated mailbox command.
``u64 out_payload``
Pointer to userspace's output payload.
``s32 *size_out``
(Input) Max payload size to copy out.
(Output) Payload size hardware generated.
``u32 *retval``
Hardware generated return code from the operation.
**Return**
* ``0`` - Mailbox transaction succeeded. This implies the mailbox
protocol completed successfully not that the operation itself
was successful.
* ``-ENOMEM`` - Couldn't allocate a bounce buffer.
* ``-EFAULT`` - Something happened with copy_to/from_user.
* ``-EINTR`` - Mailbox acquisition interrupted.
* ``-EXXX`` - Transaction level failures.
**Description**
Dispatches a mailbox command on behalf of a userspace request.
The output payload is copied to userspace.
See cxl_send_cmd().h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hj ubjo )}(hhh](jt )}(hH``struct cxl_mailbox *cxl_mbox``
The mailbox context for the operation.
h](jz )}(h ``struct cxl_mailbox *cxl_mbox``h]j )}(hjɳ h]h struct cxl_mailbox *cxl_mbox}(hj˳ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjdz ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM8hjó ubj )}(hhh]j] )}(h&The mailbox context for the operation.h]h&The mailbox context for the operation.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM8hj߳ ubah }(h ]h ]h"]h$]h&]uh1j hjó ubeh }(h ]h ]h"]h$]h&]uh1js hj hM8hj ubjt )}(hA``struct cxl_mbox_cmd *mbox_cmd``
The validated mailbox command.
h](jz )}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j )}(hj h]h struct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM9hj ubj )}(hhh]j] )}(h The validated mailbox command.h]h The validated mailbox command.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM9hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM9hj ubjt )}(h;``u64 out_payload``
Pointer to userspace's output payload.
h](jz )}(h``u64 out_payload``h]j )}(hj; h]hu64 out_payload}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj9 ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM:hj5 ubj )}(hhh]j] )}(h&Pointer to userspace's output payload.h]h(Pointer to userspace’s output payload.}(hjT hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjP hM:hjQ ubah }(h ]h ]h"]h$]h&]uh1j hj5 ubeh }(h ]h ]h"]h$]h&]uh1js hjP hM:hj ubjt )}(hb``s32 *size_out``
(Input) Max payload size to copy out.
(Output) Payload size hardware generated.
h](jz )}(h``s32 *size_out``h]j )}(hjt h]h
s32 *size_out}(hjv hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjr ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hjn ubj )}(hhh]j] )}(hO(Input) Max payload size to copy out.
(Output) Payload size hardware generated.h]hO(Input) Max payload size to copy out.
(Output) Payload size hardware generated.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM;hj ubah }(h ]h ]h"]h$]h&]uh1j hjn ubeh }(h ]h ]h"]h$]h&]uh1js hj hM<hj ubjt )}(hC``u32 *retval``
Hardware generated return code from the operation.
h](jz )}(h``u32 *retval``h]j )}(hj h]h u32 *retval}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM=hj ubj )}(hhh]j] )}(h2Hardware generated return code from the operation.h]h2Hardware generated return code from the operation.}(hjǴ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjô hM=hjĴ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjô hM=hj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hj ubj )}(hhh](j )}(h``0`` - Mailbox transaction succeeded. This implies the mailbox
protocol completed successfully not that the operation itself
was successful.h]jo )}(hhh]jt )}(h``0`` - Mailbox transaction succeeded. This implies the mailbox
protocol completed successfully not that the operation itself
was successful.h](jz )}(hF``0`` - Mailbox transaction succeeded. This implies the mailboxh](j )}(h``0``h]h0}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj
ubhA - Mailbox transaction succeeded. This implies the mailbox}(hj
hhhNhNubeh }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hj ubj )}(hhh]j] )}(hMprotocol completed successfully not that the operation itself
was successful.h]hMprotocol completed successfully not that the operation itself
was successful.}(hj- hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj) hM@hj* ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj) hM@hj ubah }(h ]h ]h"]h$]h&]uh1jn hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h1``-ENOMEM`` - Couldn't allocate a bounce buffer.h]j] )}(hjU h](j )}(h ``-ENOMEM``h]h-ENOMEM}(hjZ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubh( - Couldn’t allocate a bounce buffer.}(hjW hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMBhjS ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h9``-EFAULT`` - Something happened with copy_to/from_user.h]j] )}(hj{ h](j )}(h ``-EFAULT``h]h-EFAULT}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj} ubh. - Something happened with copy_to/from_user.}(hj} hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMChjy ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h/``-EINTR`` - Mailbox acquisition interrupted.h]j] )}(hj h](j )}(h
``-EINTR``h]h-EINTR}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh% - Mailbox acquisition interrupted.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMDhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h+``-EXXX`` - Transaction level failures.
h]j] )}(h*``-EXXX`` - Transaction level failures.h](j )}(h ``-EXXX``h]h-EXXX}(hj͵ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjɵ ubh! - Transaction level failures.}(hjɵ hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMEhjŵ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]j j uh1j hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhj ubj] )}(hiDispatches a mailbox command on behalf of a userspace request.
The output payload is copied to userspace.h]hiDispatches a mailbox command on behalf of a userspace request.
The output payload is copied to userspace.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMGhj ubj] )}(hSee cxl_send_cmd().h]hSee cxl_send_cmd().}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMJhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_walk_cel (C function)c.cxl_walk_celhNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hFvoid cxl_walk_cel (struct cxl_memdev_state *mds, size_t size, u8 *cel)h]j. )}(hEvoid cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](j4 )}(hvoidh]hvoid}(hjI hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjE hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMubjF )}(h h]h }(hjX hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjE hhhjW hMubjW )}(h cxl_walk_celh]j] )}(h cxl_walk_celh]h cxl_walk_cel}(hjj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjf ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjE hhhjW hMubjv )}(h4(struct cxl_memdev_state *mds, size_t size, u8 *cel)h](j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j jl sbc.cxl_walk_celasbuh1hhj ubjF )}(h h]h }(hjĶ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjҶ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmdsh]hmds}(hj߶ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj~ ubj| )}(h size_t sizeh](h)}(hhh]j] )}(hsize_th]hsize_t}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_walk_celasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hsizeh]hsize}(hj' hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj~ ubj| )}(hu8 *celh](h)}(hhh]j] )}(hu8h]hu8}(hjC hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj@ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjE modnameN classnameNj j )}j ]j c.cxl_walk_celasbuh1hhj< ubjF )}(h h]h }(hja hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj< ubj )}(hj h]h*}(hjo hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj< ubj] )}(hcelh]hcel}(hj| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj< ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj~ ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjE hhhjW hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjA hhhjW hMubah }(h ]j< ah ](j j eh"]h$]h&]j j )j huh1j' hjW hMhj> hhubj )}(hhh]j] )}(h%Walk through the Command Effects Log.h]h%Walk through the Command Effects Log.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj hhubah }(h ]h ]h"]h$]h&]uh1j hj> hhhjW hMubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hXH **Parameters**
``struct cxl_memdev_state *mds``
The driver data for the operation
``size_t size``
Length of the Command Effects Log.
``u8 *cel``
CEL
**Description**
Iterate over each entry in the CEL and determine if the driver supports the
command. If so, the command is enabled for the device and can be used later.h](j] )}(h**Parameters**h]j )}(hjȷ h]h
Parameters}(hjʷ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjƷ ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj· ubjo )}(hhh](jt )}(hC``struct cxl_memdev_state *mds``
The driver data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hj h]h struct cxl_memdev_state *mds}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubj )}(hhh]j] )}(h!The driver data for the operationh]h!The driver data for the operation}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhj ubjt )}(h3``size_t size``
Length of the Command Effects Log.
h](jz )}(h``size_t size``h]j )}(hj h]h size_t size}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubj )}(hhh]j] )}(h"Length of the Command Effects Log.h]h"Length of the Command Effects Log.}(hj9 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj5 hMhj6 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj5 hMhj ubjt )}(h``u8 *cel``
CEL
h](jz )}(h ``u8 *cel``h]j )}(hjY h]hu8 *cel}(hj[ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjW ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjS ubj )}(hhh]j] )}(hCELh]hCEL}(hjr hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjn hMhjo ubah }(h ]h ]h"]h$]h&]uh1j hjS ubeh }(h ]h ]h"]h$]h&]uh1js hjn hMhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj· ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj· ubj] )}(hIterate over each entry in the CEL and determine if the driver supports the
command. If so, the command is enabled for the device and can be used later.h]hIterate over each entry in the CEL and determine if the driver supports the
command. If so, the command is enabled for the device and can be used later.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj· ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_enumerate_cmds (C function)c.cxl_enumerate_cmdshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h5int cxl_enumerate_cmds (struct cxl_memdev_state *mds)h]j. )}(h4int cxl_enumerate_cmds(struct cxl_memdev_state *mds)h](j4 )}(hinth]hint}(hjٸ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjո hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjո hhhj hM<ubjW )}(hcxl_enumerate_cmdsh]j] )}(hcxl_enumerate_cmdsh]hcxl_enumerate_cmds}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjո hhhj hM<ubjv )}(h (struct cxl_memdev_state *mds)h]j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj# hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hj4 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj1 ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj6 modnameN classnameNj j )}j ]j )}j j sbc.cxl_enumerate_cmdsasbuh1hhj ubjF )}(h h]h }(hjT hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hjb hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmdsh]hmds}(hjo hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubah }(h ]h ]h"]h$]h&]hhuh1ju hjո hhhj hM<ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjѸ hhhj hM<ubah }(h ]j̸ ah ](j j eh"]h$]h&]j j )j huh1j' hj hM<hjθ hhubj )}(hhh]j] )}(h Enumerate commands for a device.h]h Enumerate commands for a device.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM<hj hhubah }(h ]h ]h"]h$]h&]uh1j hjθ hhhj hM<ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hXM **Parameters**
``struct cxl_memdev_state *mds``
The driver data for the operation
**Description**
Returns 0 if enumerate completed successfully.
CXL devices have optional support for certain commands. This function will
determine the set of supported commands for the hardware and update the
enabled_cmds bitmap in the **mds**.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hj ubjo )}(hhh]jt )}(hC``struct cxl_memdev_state *mds``
The driver data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hjڹ h]h struct cxl_memdev_state *mds}(hjܹ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjع ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM=hjԹ ubj )}(hhh]j] )}(h!The driver data for the operationh]h!The driver data for the operation}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM=hj ubah }(h ]h ]h"]h$]h&]uh1j hjԹ ubeh }(h ]h ]h"]h$]h&]uh1js hj hM=hjѹ ubah }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM?hj ubj] )}(h.Returns 0 if enumerate completed successfully.h]h.Returns 0 if enumerate completed successfully.}(hj+ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM>hj ubj] )}(hCXL devices have optional support for certain commands. This function will
determine the set of supported commands for the hardware and update the
enabled_cmds bitmap in the **mds**.h](hCXL devices have optional support for certain commands. This function will
determine the set of supported commands for the hardware and update the
enabled_cmds bitmap in the }(hj: hhhNhNubj )}(h**mds**h]hmds}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj: ubh.}(hj: hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM@hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j &cxl_mem_get_event_records (C function)c.cxl_mem_get_event_recordshNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(hIvoid cxl_mem_get_event_records (struct cxl_memdev_state *mds, u32 status)h]j. )}(hHvoid cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status)h](j4 )}(hvoidh]hvoid}(hj{ hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjw hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMVubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw hhhj hMVubjW )}(hcxl_mem_get_event_recordsh]j] )}(hcxl_mem_get_event_recordsh]hcxl_mem_get_event_records}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjw hhhj hMVubjv )}(h*(struct cxl_memdev_state *mds, u32 status)h](j| )}(h struct cxl_memdev_state *mdsh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hjź hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_memdev_stateh]hcxl_memdev_state}(hjֺ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjӺ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjغ modnameN classnameNj j )}j ]j )}j j sbc.cxl_mem_get_event_recordsasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hmdsh]hmds}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h
u32 statush](h)}(hhh]j] )}(hu32h]hu32}(hj- hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj* ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj/ modnameN classnameNj j )}j ]j c.cxl_mem_get_event_recordsasbuh1hhj& ubjF )}(h h]h }(hjK hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj& ubj] )}(hstatush]hstatus}(hjY hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj& ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjw hhhj hMVubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjs hhhj hMVubah }(h ]jn ah ](j j eh"]h$]h&]j j )j huh1j' hj hMVhjp hhubj )}(hhh]j] )}(h!Get Event Records from the deviceh]h!Get Event Records from the device}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMVhj hhubah }(h ]h ]h"]h$]h&]uh1j hjp hhhj hMVubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhju. hNhNubj )}(hX **Parameters**
``struct cxl_memdev_state *mds``
The driver data for the operation
``u32 status``
Event Status register value identifying which events are available.
**Description**
Retrieve all event records available on the device, report them as trace
events, and clear them.
See CXL rev 3.0 **8.2.9.2.2** Get Event Records
See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMZhj ubjo )}(hhh](jt )}(hC``struct cxl_memdev_state *mds``
The driver data for the operation
h](jz )}(h ``struct cxl_memdev_state *mds``h]j )}(hjĻ h]h struct cxl_memdev_state *mds}(hjƻ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj» ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMWhj ubj )}(hhh]j] )}(h!The driver data for the operationh]h!The driver data for the operation}(hjݻ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjٻ hMWhjڻ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hjٻ hMWhj ubjt )}(hS``u32 status``
Event Status register value identifying which events are available.
h](jz )}(h``u32 status``h]j )}(hj h]h
u32 status}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMXhj ubj )}(hhh]j] )}(hCEvent Status register value identifying which events are available.h]hCEvent Status register value identifying which events are available.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMXhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMXhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h**Description**h]j )}(hj8 h]h Description}(hj: hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj6 ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMZhj ubj] )}(h`Retrieve all event records available on the device, report them as trace
events, and clear them.h]h`Retrieve all event records available on the device, report them as trace
events, and clear them.}(hjN hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMYhj ubj] )}(haSee CXL rev 3.0 **8.2.9.2.2** Get Event Records
See CXL rev 3.0 **8.2.9.2.3** Clear Event Recordsh](hSee CXL rev 3.0 }(hj] hhhNhNubj )}(h
**8.2.9.2.2**h]h 8.2.9.2.2}(hje hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj] ubh# Get Event Records
See CXL rev 3.0 }(hj] hhhNhNubj )}(h
**8.2.9.2.3**h]h 8.2.9.2.3}(hjw hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj] ubh Clear Event Records}(hj] hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chM\hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j 'cxl_mem_get_partition_info (C function) c.cxl_mem_get_partition_infohNtauh1j hju. hhhNhNubj# )}(hhh](j( )}(h=int cxl_mem_get_partition_info (struct cxl_memdev_state *mds)h]j. )}(h ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj/ hMubjv )}(h#(struct cxl_memdev *cxlmd, u16 cmd)h](j| )}(hstruct cxl_memdev *cxlmdh](j )}(hj h]hstruct}(hj^ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjZ ubjF )}(h h]h }(hjk hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjZ ubh)}(hhh]j] )}(h
cxl_memdevh]h
cxl_memdev}(hj| hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjy ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj~ modnameN classnameNj j )}j ]j )}j jD sbc.cxl_mem_sanitizeasbuh1hhjZ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjZ ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjZ ubj] )}(hcxlmdh]hcxlmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjZ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjV ubj| )}(hu16 cmdh](h)}(hhh]j] )}(hu16h]hu16}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_mem_sanitizeasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hcmdh]hcmd}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjV ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj/ hMubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj/ hMubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj/ hMhj hhubj )}(hhh]j] )}(h*Send a sanitization command to the device.h]h*Send a sanitization command to the device.}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj& hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj/ hMubeh }(h ]h ](j functioneh"]h$]h&]j j j jA j jA j j j uh1j" hhhju. hNhNubj )}(hXF **Parameters**
``struct cxl_memdev *cxlmd``
The device for the operation
``u16 cmd``
The specific sanitization command opcode
**Return**
0 if the command was executed successfully, regardless of
whether or not the actual security operation is done in the background,
such as for the Sanitize case.
Error return values can be the result of the mailbox command, -EINVAL
when security requirements are not met or invalid contexts, or -EBUSY
if the sanitize operation is already in flight.
**Description**
See CXL 3.0 **8.2.9.8.5.1** Sanitize and **8.2.9.8.5.2** Secure Erase.h](j] )}(h**Parameters**h]j )}(hjK h]h
Parameters}(hjM hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjI ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjE ubjo )}(hhh](jt )}(h:``struct cxl_memdev *cxlmd``
The device for the operation
h](jz )}(h ``struct cxl_memdev *cxlmd``h]j )}(hjj h]hstruct cxl_memdev *cxlmd}(hjl hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjh ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjd ubj )}(hhh]j] )}(h The device for the operationh]h The device for the operation}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hjd ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhja ubjt )}(h5``u16 cmd``
The specific sanitization command opcode
h](jz )}(h ``u16 cmd``h]j )}(hj h]hu16 cmd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhj ubj )}(hhh]j] )}(h(The specific sanitization command opcodeh]h(The specific sanitization command opcode}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hMhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMhja ubeh }(h ]h ]h"]h$]h&]uh1jn hjE ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjE ubj] )}(hX\ 0 if the command was executed successfully, regardless of
whether or not the actual security operation is done in the background,
such as for the Sanitize case.
Error return values can be the result of the mailbox command, -EINVAL
when security requirements are not met or invalid contexts, or -EBUSY
if the sanitize operation is already in flight.h]hX\ 0 if the command was executed successfully, regardless of
whether or not the actual security operation is done in the background,
such as for the Sanitize case.
Error return values can be the result of the mailbox command, -EINVAL
when security requirements are not met or invalid contexts, or -EBUSY
if the sanitize operation is already in flight.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjE ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjE ubj] )}(hFSee CXL 3.0 **8.2.9.8.5.1** Sanitize and **8.2.9.8.5.2** Secure Erase.h](h See CXL 3.0 }(hj hhhNhNubj )}(h**8.2.9.8.5.1**h]h 8.2.9.8.5.1}(hj# hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh Sanitize and }(hj hhhNhNubj )}(h**8.2.9.8.5.2**h]h 8.2.9.8.5.2}(hj5 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh Secure Erase.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:475: ./drivers/cxl/core/mbox.chMhjE ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hju. hhhNhNubj] )}(hCXL Features:
A CXL device that includes a mailbox supports commands that allows
listing, getting, and setting of optionally defined features such
as memory sparing or post package sparing. Vendors may define custom
features for the device.h]hCXL Features:
A CXL device that includes a mailbox supports commands that allows
listing, getting, and setting of optionally defined features such
as memory sparing or post package sparing. Vendors may define custom
features for the device.}(hjU hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ ho/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:478: ./drivers/cxl/core/features.chK
hju. hhubj] )}(h6See :c:func:`devm_cxl_setup_features` for API details.h](hSee }(hjd hhhNhNubh)}(h!:c:func:`devm_cxl_setup_features`h]j )}(hjn h]hdevm_cxl_setup_features()}(hjp hhhNhNubah }(h ]h ](j1 j c-funceh"]h$]h&]uh1j hjl ubah }(h ]h ]h"]h$]h&]refdocj= refdomainj reftypefunc refexplicitrefwarnj jC jF devm_cxl_setup_featuresuh1hhhhMhjd ubh for API details.}(hjd hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hhhMhju. hhubeh }(h ]cxl-coreah ]h"]cxl coreah$]h&]uh1jG hj/ hhhhhMWubjH )}(hhh](jM )}(h CXL Regionsh]h CXL Regions}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hj hhhhhMubj] )}(hX< CXL Regions represent mapped memory capacity in system physical address
space. Whereas the CXL Root Decoders identify the bounds of potential CXL
Memory ranges, Regions represent the active mapped capacity by the HDM
Decoder Capability structures throughout the Host Bridges, Switches, and
Endpoints in the topology.h]hX< CXL Regions represent mapped memory capacity in system physical address
space. Whereas the CXL Root Decoders identify the bounds of potential CXL
Memory ranges, Regions represent the active mapped capacity by the HDM
Decoder Capability structures throughout the Host Bridges, Switches, and
Endpoints in the topology.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:485: ./drivers/cxl/core/region.chKhj hhubj] )}(hRegion configuration has ordering constraints. UUID may be set at any time
but is only visible for persistent regions.
1. Interleave granularity
2. Interleave size
3. Decoder targetsh]hRegion configuration has ordering constraints. UUID may be set at any time
but is only visible for persistent regions.
1. Interleave granularity
2. Interleave size
3. Decoder targets}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:485: ./drivers/cxl/core/region.chKhj hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j )cxl_port_pick_region_decoder (C function) c.cxl_port_pick_region_decoderhNtauh1j hj hhhNhNubj# )}(hhh](j( )}(hstruct cxl_decoder * cxl_port_pick_region_decoder (struct cxl_port *port, struct cxl_endpoint_decoder *cxled, struct cxl_region *cxlr)h]j. )}(hstruct cxl_decoder *cxl_port_pick_region_decoder(struct cxl_port *port, struct cxl_endpoint_decoder *cxled, struct cxl_region *cxlr)h](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMcubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMcubh)}(hhh]j] )}(h cxl_decoderh]h cxl_decoder}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j cxl_port_pick_region_decodersb c.cxl_port_pick_region_decoderasbuh1hhj hhhj hMcubjF )}(h h]h }(hj% hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hMcubj )}(hj h]h*}(hj3 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhj hMcubjW )}(h cxl_port_pick_region_decoderh]j] )}(hj" h]h cxl_port_pick_region_decoder}(hjD hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj@ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hMcubjv )}(hT(struct cxl_port *port, struct cxl_endpoint_decoder *cxled, struct cxl_region *cxlr)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj_ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[ ubjF )}(h h]h }(hjl hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[ ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj} hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjz ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_port_pick_region_decoderasbuh1hhj[ ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj[ ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj[ ubj] )}(hporth]hport}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[ ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjW ubj| )}(h"struct cxl_endpoint_decoder *cxledh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.cxl_port_pick_region_decoderasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxledh]hcxled}(hj& hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjW ubj| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hj? hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj; ubjF )}(h h]h }(hjL hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj; ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj] hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjZ ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj_ modnameN classnameNj j )}j ]j c.cxl_port_pick_region_decoderasbuh1hhj; ubjF )}(h h]h }(hj{ hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj; ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj; ubj] )}(hcxlrh]hcxlr}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj; ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjW ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hMcubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hMcubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hMchj hhubj )}(hhh]j] )}(h'assign or lookup a decoder for a regionh]h'assign or lookup a decoder for a region}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMchj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hMcubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhj hNhNubj )}(hX? **Parameters**
``struct cxl_port *port``
a port in the ancestry of the endpoint implied by **cxled**
``struct cxl_endpoint_decoder *cxled``
endpoint decoder to be, or currently, mapped by **port**
``struct cxl_region *cxlr``
region to establish, or validate, decode **port**
**Description**
In the region creation path cxl_port_pick_region_decoder() is an
allocator to find a free port. In the region assembly path, it is
recalling the decoder that platform firmware picked for validation
purposes.
The result is recorded in a 'struct cxl_region_ref' in **port**.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMghj ubjo )}(hhh](jt )}(hV``struct cxl_port *port``
a port in the ancestry of the endpoint implied by **cxled**
h](jz )}(h``struct cxl_port *port``h]j )}(hj h]hstruct cxl_port *port}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMdhj ubj )}(hhh]j] )}(h;a port in the ancestry of the endpoint implied by **cxled**h](h2a port in the ancestry of the endpoint implied by }(hj hhhNhNubj )}(h **cxled**h]hcxled}(hj" hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hj hMdhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMdhj ubjt )}(h```struct cxl_endpoint_decoder *cxled``
endpoint decoder to be, or currently, mapped by **port**
h](jz )}(h&``struct cxl_endpoint_decoder *cxled``h]j )}(hjH h]h"struct cxl_endpoint_decoder *cxled}(hjJ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjF ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMehjB ubj )}(hhh]j] )}(h8endpoint decoder to be, or currently, mapped by **port**h](h0endpoint decoder to be, or currently, mapped by }(hja hhhNhNubj )}(h**port**h]hport}(hji hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hja ubeh }(h ]h ]h"]h$]h&]uh1j\ hj] hMehj^ ubah }(h ]h ]h"]h$]h&]uh1j hjB ubeh }(h ]h ]h"]h$]h&]uh1js hj] hMehj ubjt )}(hN``struct cxl_region *cxlr``
region to establish, or validate, decode **port**
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hj h]hstruct cxl_region *cxlr}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMfhj ubj )}(hhh]j] )}(h1region to establish, or validate, decode **port**h](h)region to establish, or validate, decode }(hj hhhNhNubj )}(h**port**h]hport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hj hMfhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hMfhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMhhj ubj] )}(hIn the region creation path cxl_port_pick_region_decoder() is an
allocator to find a free port. In the region assembly path, it is
recalling the decoder that platform firmware picked for validation
purposes.h]hIn the region creation path cxl_port_pick_region_decoder() is an
allocator to find a free port. In the region assembly path, it is
recalling the decoder that platform firmware picked for validation
purposes.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMghj ubj] )}(h@The result is recorded in a 'struct cxl_region_ref' in **port**.h](h;The result is recorded in a ‘struct cxl_region_ref’ in }(hj hhhNhNubj )}(h**port**h]hport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMlhj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j #cxl_port_attach_region (C function)c.cxl_port_attach_regionhNtauh1j hj hhhNhNubj# )}(hhh](j( )}(hxint cxl_port_attach_region (struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h]j. )}(hwint cxl_port_attach_region(struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h](j4 )}(hinth]hint}(hj> hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj: hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM ubjF )}(h h]h }(hjM hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj: hhhjL hM ubjW )}(hcxl_port_attach_regionh]j] )}(hcxl_port_attach_regionh]hcxl_port_attach_region}(hj_ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj[ ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj: hhhjL hM ubjv )}(h](struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h](j| )}(hstruct cxl_port *porth](j )}(hj h]hstruct}(hj{ hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjw ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw ubh)}(hhh]j] )}(hcxl_porth]hcxl_port}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j ja sbc.cxl_port_attach_regionasbuh1hhjw ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjw ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjw ubj] )}(hporth]hport}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjw ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjs ubj| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj
modnameN classnameNj j )}j ]j c.cxl_port_attach_regionasbuh1hhj ubjF )}(h h]h }(hj) hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj7 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxlrh]hcxlr}(hjD hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjs ubj| )}(h"struct cxl_endpoint_decoder *cxledh](j )}(hj h]hstruct}(hj] hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjY ubjF )}(h h]h }(hjj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjY ubh)}(hhh]j] )}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj{ hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjx ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj} modnameN classnameNj j )}j ]j c.cxl_port_attach_regionasbuh1hhjY ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjY ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjY ubj] )}(hcxledh]hcxled}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjY ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjs ubj| )}(hint posh](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hposh]hpos}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjs ubeh }(h ]h ]h"]h$]h&]hhuh1ju hj: hhhjL hM ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj6 hhhjL hM ubah }(h ]j1 ah ](j j eh"]h$]h&]j j )j huh1j' hjL hM hj3 hhubj )}(hhh]j] )}(h/track a region's interest in a port by endpointh]h1track a region’s interest in a port by endpoint}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj hhubah }(h ]h ]h"]h$]h&]uh1j hj3 hhhjL hM ubeh }(h ]h ](j functioneh"]h$]h&]j j j j+ j j+ j j j uh1j" hhhj hNhNubj )}(hX **Parameters**
``struct cxl_port *port``
port to add a new region reference 'struct cxl_region_ref'
``struct cxl_region *cxlr``
region to attach to **port**
``struct cxl_endpoint_decoder *cxled``
endpoint decoder used to create or further pin a region reference
``int pos``
interleave position of **cxled** in **cxlr**
**Description**
The attach event is an opportunity to validate CXL decode setup
constraints and record metadata needed for programming HDM decoders,
in particular decoder target lists.
The steps are:
- validate that there are no other regions with a higher HPA already
associated with **port**
- establish a region reference if one is not already present
- additionally allocate a decoder instance that will host **cxlr** on
**port**
- pin the region reference by the endpoint
- account for how many entries in **port**'s target list are needed to
cover all of the added endpoints.h](j] )}(h**Parameters**h]j )}(hj5 h]h
Parameters}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj3 ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM#hj/ ubjo )}(hhh](jt )}(hU``struct cxl_port *port``
port to add a new region reference 'struct cxl_region_ref'
h](jz )}(h``struct cxl_port *port``h]j )}(hjT h]hstruct cxl_port *port}(hjV hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjR ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjN ubj )}(hhh]j] )}(h:port to add a new region reference 'struct cxl_region_ref'h]h>port to add a new region reference ‘struct cxl_region_ref’}(hjm hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hji hM hjj ubah }(h ]h ]h"]h$]h&]uh1j hjN ubeh }(h ]h ]h"]h$]h&]uh1js hji hM hjK ubjt )}(h9``struct cxl_region *cxlr``
region to attach to **port**
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hj h]hstruct cxl_region *cxlr}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM!hj ubj )}(hhh]j] )}(h region to attach to **port**h](hregion to attach to }(hj hhhNhNubj )}(h**port**h]hport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hj hM!hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM!hjK ubjt )}(hi``struct cxl_endpoint_decoder *cxled``
endpoint decoder used to create or further pin a region reference
h](jz )}(h&``struct cxl_endpoint_decoder *cxled``h]j )}(hj h]h"struct cxl_endpoint_decoder *cxled}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM"hj ubj )}(hhh]j] )}(hAendpoint decoder used to create or further pin a region referenceh]hAendpoint decoder used to create or further pin a region reference}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM"hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM"hjK ubjt )}(h9``int pos``
interleave position of **cxled** in **cxlr**
h](jz )}(h ``int pos``h]j )}(hj
h]hint pos}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM#hj ubj )}(hhh]j] )}(h,interleave position of **cxled** in **cxlr**h](hinterleave position of }(hj& hhhNhNubj )}(h **cxled**h]hcxled}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj& ubh in }(hj& hhhNhNubj )}(h**cxlr**h]hcxlr}(hj@ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj& ubeh }(h ]h ]h"]h$]h&]uh1j\ hj" hM#hj# ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj" hM#hjK ubeh }(h ]h ]h"]h$]h&]uh1jn hj/ ubj] )}(h**Description**h]j )}(hjh h]h Description}(hjj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjf ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM%hj/ ubj] )}(hThe attach event is an opportunity to validate CXL decode setup
constraints and record metadata needed for programming HDM decoders,
in particular decoder target lists.h]hThe attach event is an opportunity to validate CXL decode setup
constraints and record metadata needed for programming HDM decoders,
in particular decoder target lists.}(hj~ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM$hj/ ubj] )}(hThe steps are:h]hThe steps are:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM(hj/ ubj )}(hhh](j )}(h[validate that there are no other regions with a higher HPA already
associated with **port**h]j] )}(h[validate that there are no other regions with a higher HPA already
associated with **port**h](hSvalidate that there are no other regions with a higher HPA already
associated with }(hj hhhNhNubj )}(h**port**h]hport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM*hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(hestablish a region reference if one is not already present
- additionally allocate a decoder instance that will host **cxlr** on
**port**
h](j] )}(h:establish a region reference if one is not already presenth]h:establish a region reference if one is not already present}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM,hj ubj )}(hhh]j )}(hMadditionally allocate a decoder instance that will host **cxlr** on
**port**
h]j] )}(hLadditionally allocate a decoder instance that will host **cxlr** on
**port**h](h8additionally allocate a decoder instance that will host }(hj hhhNhNubj )}(h**cxlr**h]hcxlr}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh on
}(hj hhhNhNubj )}(h**port**h]hport}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM.hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]j j uh1j hj hM.hj ubeh }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h(pin the region reference by the endpointh]j] )}(hj# h]h(pin the region reference by the endpoint}(hj% hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM1hj! ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(hfaccount for how many entries in **port**'s target list are needed to
cover all of the added endpoints.h]j] )}(hfaccount for how many entries in **port**'s target list are needed to
cover all of the added endpoints.h](h account for how many entries in }(hj= hhhNhNubj )}(h**port**h]hport}(hjE hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj= ubh@’s target list are needed to
cover all of the added endpoints.}(hj= hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM2hj9 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]j j uh1j hj hM*hj/ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j $cxl_calc_interleave_pos (C function)c.cxl_calc_interleave_poshNtauh1j hj hhhNhNubj# )}(hhh](j( )}(h@int cxl_calc_interleave_pos (struct cxl_endpoint_decoder *cxled)h]j. )}(h?int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hM ubjW )}(hcxl_calc_interleave_posh]j] )}(hcxl_calc_interleave_posh]hcxl_calc_interleave_pos}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hM ubjv )}(h$(struct cxl_endpoint_decoder *cxled)h]j| )}(h"struct cxl_endpoint_decoder *cxledh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j j sbc.cxl_calc_interleave_posasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxledh]hcxled}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubah }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj hM ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hM ubah }(h ]j} ah ](j j eh"]h$]h&]j j )j huh1j' hj hM hj hhubj )}(hhh]j] )}(h*calculate an endpoint position in a regionh]h*calculate an endpoint position in a region}(hjJ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjG hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hM ubeh }(h ]h ](j functioneh"]h$]h&]j j j jb j jb j j j uh1j" hhhj hNhNubj )}(hX **Parameters**
``struct cxl_endpoint_decoder *cxled``
endpoint decoder member of given region
**Description**
The endpoint position is calculated by traversing the topology from
the endpoint to the root decoder and iteratively applying this
calculation:
position = position * parent_ways + parent_pos;
...where **position** is inferred from switch and root decoder target lists.
**Return**
position >= 0 on success
-ENXIO on failureh](j] )}(h**Parameters**h]j )}(hjl h]h
Parameters}(hjn hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM"hjf ubjo )}(hhh]jt )}(hO``struct cxl_endpoint_decoder *cxled``
endpoint decoder member of given region
h](jz )}(h&``struct cxl_endpoint_decoder *cxled``h]j )}(hj h]h"struct cxl_endpoint_decoder *cxled}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj ubj )}(hhh]j] )}(h'endpoint decoder member of given regionh]h'endpoint decoder member of given region}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM hj ubah }(h ]h ]h"]h$]h&]uh1jn hjf ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM!hjf ubj] )}(hThe endpoint position is calculated by traversing the topology from
the endpoint to the root decoder and iteratively applying this
calculation:h]hThe endpoint position is calculated by traversing the topology from
the endpoint to the root decoder and iteratively applying this
calculation:}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjf ubj! )}(h0position = position * parent_ways + parent_pos;
h]j] )}(h/position = position * parent_ways + parent_pos;h]h/position = position * parent_ways + parent_pos;}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM$hj ubah }(h ]h ]h"]h$]h&]uh1j! hj hM$hjf ubj] )}(hL...where **position** is inferred from switch and root decoder target lists.h](h ...where }(hj hhhNhNubj )}(h **position**h]hposition}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh7 is inferred from switch and root decoder target lists.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM&hjf ubj] )}(h
**Return**h]j )}(hj' h]hReturn}(hj) hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj% ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM(hjf ubj] )}(h*position >= 0 on success
-ENXIO on failureh]h*position >= 0 on success
-ENXIO on failure}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM)hjf ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j devm_cxl_add_region (C function)c.devm_cxl_add_regionhNtauh1j hj hhhNhNubj# )}(hhh](j( )}(hstruct cxl_region * devm_cxl_add_region (struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h]j. )}(hstruct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j )}(hj h]hstruct}(hjl hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjh hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM ubjF )}(h h]h }(hjz hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjh hhhjy hM ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j )}j devm_cxl_add_regionsbc.devm_cxl_add_regionasbuh1hhjh hhhjy hM ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjh hhhjy hM ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjh hhhjy hM ubjW )}(hdevm_cxl_add_regionh]j] )}(hj h]hdevm_cxl_add_region}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hjh hhhjy hM ubjv )}(hb(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j| )}(h struct cxl_root_decoder *cxlrdh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_root_decoderh]hcxl_root_decoder}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.devm_cxl_add_regionasbuh1hhj ubjF )}(h h]h }(hj" hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj )}(hj h]h*}(hj0 hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubj] )}(hcxlrdh]hcxlrd}(hj= hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(hint idh](j4 )}(hinth]hint}(hjV hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hjR ubjF )}(h h]h }(hjd hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjR ubj] )}(hidh]hid}(hjr hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjR ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(h enum cxl_partition_mode modeh](j )}(hj' h]henum}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_partition_modeh]hcxl_partition_mode}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.devm_cxl_add_regionasbuh1hhj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(hmodeh]hmode}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubj| )}(henum cxl_decoder_type typeh](j )}(hj' h]henum}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubh)}(hhh]j] )}(hcxl_decoder_typeh]hcxl_decoder_type}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]j c.devm_cxl_add_regionasbuh1hhj ubjF )}(h h]h }(hj* hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj ubj] )}(htypeh]htype}(hj8 hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hj ubeh }(h ]h ]h"]h$]h&]hhuh1ju hjh hhhjy hM ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hjd hhhjy hM ubah }(h ]j_ ah ](j j eh"]h$]h&]j j )j huh1j' hjy hM hja hhubj )}(hhh]j] )}(hAdds a region to a decoderh]hAdds a region to a decoder}(hjb hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj_ hhubah }(h ]h ]h"]h$]h&]uh1j hja hhhjy hM ubeh }(h ]h ](j functioneh"]h$]h&]j j j jz j jz j j j uh1j" hhhj hNhNubj )}(hXl **Parameters**
``struct cxl_root_decoder *cxlrd``
root decoder
``int id``
memregion id to create, or memregion_free() on failure
``enum cxl_partition_mode mode``
mode for the endpoint decoders of this region
``enum cxl_decoder_type type``
select whether this is an expander or accelerator (type-2 or type-3)
**Description**
This is the second step of region initialization. Regions exist within an
address space which is mapped by a **cxlrd**.
**Return**
0 if the region was added to the **cxlrd**, else returns negative error
code. The region will be named "regionZ" where Z is the unique region number.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj~ ubjo )}(hhh](jt )}(h0``struct cxl_root_decoder *cxlrd``
root decoder
h](jz )}(h"``struct cxl_root_decoder *cxlrd``h]j )}(hj h]h struct cxl_root_decoder *cxlrd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj ubj )}(hhh]j] )}(h root decoderh]h root decoder}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM hj ubjt )}(hB``int id``
memregion id to create, or memregion_free() on failure
h](jz )}(h
``int id``h]j )}(hj h]hint id}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj ubj )}(hhh]j] )}(h6memregion id to create, or memregion_free() on failureh]h6memregion id to create, or memregion_free() on failure}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hM hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hM hj ubjt )}(hO``enum cxl_partition_mode mode``
mode for the endpoint decoders of this region
h](jz )}(h ``enum cxl_partition_mode mode``h]j )}(hj h]h enum cxl_partition_mode mode}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj ubj )}(hhh]j] )}(h-mode for the endpoint decoders of this regionh]h-mode for the endpoint decoders of this region}(hj. hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj* hM hj+ ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj* hM hj ubjt )}(hd``enum cxl_decoder_type type``
select whether this is an expander or accelerator (type-2 or type-3)
h](jz )}(h ``enum cxl_decoder_type type``h]j )}(hjN h]henum cxl_decoder_type type}(hjP hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjL ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hjH ubj )}(hhh]j] )}(hDselect whether this is an expander or accelerator (type-2 or type-3)h]hDselect whether this is an expander or accelerator (type-2 or type-3)}(hjg hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjc hM hjd ubah }(h ]h ]h"]h$]h&]uh1j hjH ubeh }(h ]h ]h"]h$]h&]uh1js hjc hM hj ubeh }(h ]h ]h"]h$]h&]uh1jn hj~ ubj] )}(h**Description**h]j )}(hj h]h Description}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj~ ubj] )}(hwThis is the second step of region initialization. Regions exist within an
address space which is mapped by a **cxlrd**.h](hmThis is the second step of region initialization. Regions exist within an
address space which is mapped by a }(hj hhhNhNubj )}(h **cxlrd**h]hcxlrd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj~ ubj] )}(h
**Return**h]j )}(hj h]hReturn}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj~ ubj] )}(h0 if the region was added to the **cxlrd**, else returns negative error
code. The region will be named "regionZ" where Z is the unique region number.h](h!0 if the region was added to the }(hj hhhNhNubj )}(h **cxlrd**h]hcxlrd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubho, else returns negative error
code. The region will be named “regionZ” where Z is the unique region number.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chM hj~ ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhNhNubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j %devm_cxl_add_pmem_region (C function)c.devm_cxl_add_pmem_regionhNtauh1j hj hhhNhNubj# )}(hhh](j( )}(h6int devm_cxl_add_pmem_region (struct cxl_region *cxlr)h]j. )}(h5int devm_cxl_add_pmem_region(struct cxl_region *cxlr)h](j4 )}(hinth]hint}(hj hhhNhNubah }(h ]h ]j@ ah"]h$]h&]uh1j3 hj hhhm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMI ubjF )}(h h]h }(hj( hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj' hMI ubjW )}(hdevm_cxl_add_pmem_regionh]j] )}(hdevm_cxl_add_pmem_regionh]hdevm_cxl_add_pmem_region}(hj: hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj6 ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj' hMI ubjv )}(h(struct cxl_region *cxlr)h]j| )}(hstruct cxl_region *cxlrh](j )}(hj h]hstruct}(hjV hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjR ubjF )}(h h]h }(hjc hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjR ubh)}(hhh]j] )}(h
cxl_regionh]h
cxl_region}(hjt hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjq ubah }(h ]h ]h"]h$]h&] refdomainj reftypej reftargetjv modnameN classnameNj j )}j ]j )}j j< sbc.devm_cxl_add_pmem_regionasbuh1hhjR ubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hjR ubj )}(hj h]h*}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hjR ubj] )}(hcxlrh]hcxlr}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hjR ubeh }(h ]h ]h"]h$]h&]noemphhhuh1j{ hjN ubah }(h ]h ]h"]h$]h&]hhuh1ju hj hhhj' hMI ubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj' hMI ubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj' hMI hj hhubj )}(hhh]j] )}(h$add a cxl_region-to-nd_region bridgeh]h$add a cxl_region-to-nd_region bridge}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMI hj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj' hMI ubeh }(h ]h ](j functioneh"]h$]h&]j j j j j j j j j uh1j" hhhj hNhNubj )}(h**Parameters**
``struct cxl_region *cxlr``
parent CXL region for this pmem region bridge device
**Return**
0 on success negative error code on failure.h](j] )}(h**Parameters**h]j )}(hj h]h
Parameters}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMM hj ubjo )}(hhh]jt )}(hQ``struct cxl_region *cxlr``
parent CXL region for this pmem region bridge device
h](jz )}(h``struct cxl_region *cxlr``h]j )}(hj h]hstruct cxl_region *cxlr}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chMJ hj ubj )}(hhh]j] )}(h4parent CXL region for this pmem region bridge deviceh]h4parent CXL region for this pmem region bridge device}(hj3 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj/ hMJ hj0 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj/ hMJ hj ubah }(h ]h ]h"]h$]h&]uh1jn hj ubj] )}(h
**Return**h]j )}(hjU h]hReturn}(hjW hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjS ubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chML hj ubj] )}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hjk hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hm/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:488: ./drivers/cxl/core/region.chML hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhNhNubeh }(h ] cxl-regionsah ]h"] cxl regionsah$]h&]uh1jG hj/ hhhhhMubeh }(h ]driver-infrastructureah ]h"]driver infrastructureah$]h&]uh1jG hjI hhhhhM;ubjH )}(hhh](jM )}(hExternal Interfacesh]hExternal Interfaces}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hj hhhhhMubjH )}(hhh](jM )}(hCXL IOCTL Interfaceh]hCXL IOCTL Interface}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1jL hj hhhhhMubj] )}(hNot all of the commands that the driver supports are available for use by
userspace at all times. Userspace can check the result of the QUERY command
to determine the live set of commands. Alternatively, it can issue the
command and check for failure.h]hNot all of the commands that the driver supports are available for use by
userspace at all times. Userspace can check the result of the QUERY command
to determine the live set of commands. Alternatively, it can issue the
command and check for failure.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:497: ./include/uapi/linux/cxl_mem.hhK hj hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_command_info (C struct)c.cxl_command_infohNtauh1j hj hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhNubj# )}(hhh](j( )}(hcxl_command_infoh]j. )}(hstruct cxl_command_infoh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKubjW )}(hcxl_command_infoh]j] )}(hj h]hcxl_command_info}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKhj hhubj )}(hhh]j] )}(h*Command information returned from a query.h]h*Command information returned from a query.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKfhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKubeh }(h ]h ](j structeh"]h$]h&]j j j j6 j j6 j j j uh1j" hhhj hj hNubj )}(hX **Definition**::
struct cxl_command_info {
__u32 id;
__u32 flags;
#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0);
#define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0);
#define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1);
__u32 size_in;
__u32 size_out;
};
**Members**
``id``
ID number for the command.
``flags``
Flags that specify command behavior.
``size_in``
Expected input size, or ~0 if variable length.
``size_out``
Expected output size, or ~0 if variable length.h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hjB hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj> ubh:}(hj> hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKjhj: ubj )}(hX struct cxl_command_info {
__u32 id;
__u32 flags;
#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0);
#define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0);
#define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1);
__u32 size_in;
__u32 size_out;
};h]hX struct cxl_command_info {
__u32 id;
__u32 flags;
#define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0);
#define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0);
#define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1);
__u32 size_in;
__u32 size_out;
};}hj[ sbah }(h ]h ]h"]h$]h&]hhuh1j hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKlhj: ubj] )}(h **Members**h]j )}(hjl h]hMembers}(hjn hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjj ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKvhj: ubjo )}(hhh](jt )}(h"``id``
ID number for the command.
h](jz )}(h``id``h]j )}(hj h]hid}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhhj ubR j )}(hhh]j] )}(hID number for the command.h]hID number for the command.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhhj ubjt )}(h/``flags``
Flags that specify command behavior.
h](jz )}(h ``flags``h]j )}(hj h]hflags}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKihj ubj )}(hhh]j] )}(h$Flags that specify command behavior.h]h$Flags that specify command behavior.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKihj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKihj ubjt )}(h;``size_in``
Expected input size, or ~0 if variable length.
h](jz )}(h ``size_in``h]j )}(hj h]hsize_in}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhj ubj )}(hhh]j] )}(h.Expected input size, or ~0 if variable length.h]h.Expected input size, or ~0 if variable length.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKwhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKwhj ubjt )}(h<``size_out``
Expected output size, or ~0 if variable length.h](jz )}(h ``size_out``h]j )}(hj6 h]hsize_out}(hj8 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj4 ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKwhj0 ubj )}(hhh]j] )}(h/Expected output size, or ~0 if variable length.h]h/Expected output size, or ~0 if variable length.}(hjO hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKxhjL ubah }(h ]h ]h"]h$]h&]uh1j hj0 ubeh }(h ]h ]h"]h$]h&]uh1js hjK hKwhj ubeh }(h ]h ]h"]h$]h&]uh1jn hj: ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhj hNubj] )}(h**Description**h]j )}(hjy h]h Description}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjw ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK{hj hhubj! )}(hX CXL_MEM_COMMAND_FLAG_USER_ENABLED
The given command id is supported by the driver and is supported by
a related opcode on the device.
CXL_MEM_COMMAND_FLAG_EXCLUSIVE
Requests with the given command id will terminate with EBUSY as the
kernel actively owns management of the given resource. For example,
the label-storage-area can not be written while the kernel is
actively managing that space.
h](j] )}(h!CXL_MEM_COMMAND_FLAG_USER_ENABLEDh]h!CXL_MEM_COMMAND_FLAG_USER_ENABLED}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKihj ubj] )}(hcThe given command id is supported by the driver and is supported by
a related opcode on the device.h]hcThe given command id is supported by the driver and is supported by
a related opcode on the device.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKkhj ubj] )}(h CXL_MEM_COMMAND_FLAG_EXCLUSIVEh]h CXL_MEM_COMMAND_FLAG_EXCLUSIVE}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKnhj ubj] )}(hRequests with the given command id will terminate with EBUSY as the
kernel actively owns management of the given resource. For example,
the label-storage-area can not be written while the kernel is
actively managing that space.h]hRequests with the given command id will terminate with EBUSY as the
kernel actively owns management of the given resource. For example,
the label-storage-area can not be written while the kernel is
actively managing that space.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKphj ubeh }(h ]h ]h"]h$]h&]uh1j! hj hKihj hhubj] )}(hRepresents a single command that is supported by both the driver and the
hardware. This is returned as part of an array from the query ioctl. The
following would be a command that takes a variable length input and returns 0
bytes of output.h]hRepresents a single command that is supported by both the driver and the
hardware. This is returned as part of an array from the query ioctl. The
following would be a command that takes a variable length input and returns 0
bytes of output.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKvhj hhubj! )}(h_- **id** = 10
- **flags** = CXL_MEM_COMMAND_FLAG_ENABLED
- **size_in** = ~0
- **size_out** = 0
h]j )}(hhh](j )}(h **id** = 10h]j] )}(hj h](j )}(h**id**h]hid}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh = 10}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK{hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h(**flags** = CXL_MEM_COMMAND_FLAG_ENABLEDh]j] )}(hj h](j )}(h **flags**h]hflags}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh = CXL_MEM_COMMAND_FLAG_ENABLED}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK|hj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h**size_in** = ~0h]j] )}(hj9 h](j )}(h **size_in**h]hsize_in}(hj> hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj; ubh = ~0}(hj; hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK}hj7 ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(h**size_out** = 0
h]j] )}(h**size_out** = 0h](j )}(h **size_out**h]hsize_out}(hje hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hja ubh = 0}(hja hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhK~hj] ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]j j uh1j hj
hK{hj ubah }(h ]h ]h"]h$]h&]uh1j! hj
hK{hj hhubj] )}(h"See struct cxl_mem_query_commands.h]h"See struct cxl_mem_query_commands.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j !cxl_mem_query_commands (C struct)c.cxl_mem_query_commandshNtauh1j hj hhhj hNubj# )}(hhh](j( )}(hcxl_mem_query_commandsh]j. )}(h struct cxl_mem_query_commandsh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKubjW )}(hcxl_mem_query_commandsh]j] )}(hj h]hcxl_mem_query_commands}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKhj hhubj )}(hhh]j] )}(hQuery supported commands.h]hQuery supported commands.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKubeh }(h ]h ](j structeh"]h$]h&]j j j j j j j j j uh1j" hhhj hj hNubj )}(hX5 **Definition**::
struct cxl_mem_query_commands {
__u32 n_commands;
__u32 rsvd;
struct cxl_command_info __user commands[];
};
**Members**
``n_commands``
In/out parameter. When **n_commands** is > 0, the driver will
return min(num_support_commands, n_commands). When **n_commands**
is 0, driver will return the number of total supported commands.
``rsvd``
Reserved for future use.
``commands``
Output array of supported commands. This array must be allocated
by userspace to be at least min(num_support_commands, **n_commands**)h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh:}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hwstruct cxl_mem_query_commands {
__u32 n_commands;
__u32 rsvd;
struct cxl_command_info __user commands[];
};h]hwstruct cxl_mem_query_commands {
__u32 n_commands;
__u32 rsvd;
struct cxl_command_info __user commands[];
};}hj7 sbah }(h ]h ]h"]h$]h&]hhuh1j hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj] )}(h **Members**h]j )}(hjH h]hMembers}(hjJ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjF ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubjo )}(hhh](jt )}(h``n_commands``
In/out parameter. When **n_commands** is > 0, the driver will
return min(num_support_commands, n_commands). When **n_commands**
is 0, driver will return the number of total supported commands.
h](jz )}(h``n_commands``h]j )}(hjg h]h
n_commands}(hji hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hje ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhja ubj )}(hhh]j] )}(hIn/out parameter. When **n_commands** is > 0, the driver will
return min(num_support_commands, n_commands). When **n_commands**
is 0, driver will return the number of total supported commands.h](hIn/out parameter. When }(hj hhhNhNubj )}(h**n_commands**h]h
n_commands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubhL is > 0, the driver will
return min(num_support_commands, n_commands). When }(hj hhhNhNubj )}(h**n_commands**h]h
n_commands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubhA
is 0, driver will return the number of total supported commands.}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj} ubah }(h ]h ]h"]h$]h&]uh1j hja ubeh }(h ]h ]h"]h$]h&]uh1js hj| hKhj^ ubjt )}(h"``rsvd``
Reserved for future use.
h](jz )}(h``rsvd``h]j )}(hj h]hrsvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(hReserved for future use.h]hReserved for future use.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj^ ubjt )}(h``commands``
Output array of supported commands. This array must be allocated
by userspace to be at least min(num_support_commands, **n_commands**)h](jz )}(h ``commands``h]j )}(hj h]hcommands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(hOutput array of supported commands. This array must be allocated
by userspace to be at least min(num_support_commands, **n_commands**)h](hwOutput array of supported commands. This array must be allocated
by userspace to be at least min(num_support_commands, }(hj hhhNhNubj )}(h**n_commands**h]h
n_commands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubh)}(hj hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj^ ubeh }(h ]h ]h"]h$]h&]uh1jn hj ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhj hNubj] )}(h**Description**h]j )}(hjR h]h Description}(hjT hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjP ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubj] )}(hAllow userspace to query the available commands supported by both the driver,
and the hardware. Commands that aren't supported by either the driver, or the
hardware are not returned in the query.h]hAllow userspace to query the available commands supported by both the driver,
and the hardware. Commands that aren’t supported by either the driver, or the
hardware are not returned in the query.}(hjh hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubj] )}(h **Examples**h]j )}(hjy h]hExamples}(hj{ hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjw ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubj! )}(h- { .n_commands = 0 } // Get number of supported commands
- { .n_commands = 15, .commands = buf } // Return first 15 (or less)
supported commands
See struct cxl_command_info.
h](j )}(hhh](j )}(h7{ .n_commands = 0 } // Get number of supported commandsh]j] )}(hj h]h7{ .n_commands = 0 } // Get number of supported commands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubj )}(hV{ .n_commands = 15, .commands = buf } // Return first 15 (or less)
supported commands
h]j] )}(hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less)
supported commandsh]hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less)
supported commands}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]j j uh1j hj hKhj ubj] )}(h See struct cxl_command_info.h]h See struct cxl_command_info.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubeh }(h ]h ]h"]h$]h&]uh1j! hj hKhj hhubj )}(hhh]h }(h ]h ]h"]h$]h&]entries](j cxl_send_command (C struct)c.cxl_send_commandhNtauh1j hj hhhj hNubj# )}(hhh](j( )}(hcxl_send_commandh]j. )}(hstruct cxl_send_commandh](j )}(hj h]hstruct}(hj hhhNhNubah }(h ]h ]j ah"]h$]h&]uh1j hj hhhp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKubjF )}(h h]h }(hj hhhNhNubah }(h ]h ]jR ah"]h$]h&]uh1jE hj hhhj hKubjW )}(hcxl_send_commandh]j] )}(hj h]hcxl_send_command}(hj hhhNhNubah }(h ]h ]ji ah"]h$]h&]uh1j\ hj ubah }(h ]h ](jp jq eh"]h$]h&]hhuh1jV hj hhhj hKubeh }(h ]h ]h"]h$]h&]hhj| uh1j- j} j~ hj hhhj hKubah }(h ]j ah ](j j eh"]h$]h&]j j )j huh1j' hj hKhj hhubj )}(hhh]j] )}(h"Send a command to a memory device.h]h"Send a command to a memory device.}(hj= hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj: hhubah }(h ]h ]h"]h$]h&]uh1j hj hhhj hKubeh }(h ]h ](j structeh"]h$]h&]j j j jU j jU j j j uh1j" hhhj hj hNubj )}(hX
**Definition**::
struct cxl_send_command {
__u32 id;
__u32 flags;
union {
struct {
__u16 opcode;
__u16 rsvd;
} raw;
__u32 rsvd;
};
__u32 retval;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} in;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} out;
};
**Members**
``id``
The command to send to the memory device. This must be one of the
commands returned by the query command.
``flags``
Flags for the command (input).
``{unnamed_union}``
anonymous
``raw``
Special fields for raw commands
``raw.opcode``
Opcode passed to hardware when using the RAW command.
``raw.rsvd``
Must be zero.
``rsvd``
Must be zero.
``retval``
Return value from the memory device (output).
``in``
Parameters associated with input payload.
``in.size``
Size of the payload to provide to the device (input).
``in.rsvd``
Must be zero.
``in.payload``
Pointer to memory for payload input, payload is little endian.
``out``
Parameters associated with output payload.
``out.size``
Size of the payload received from the device (input/output). This
field is filled in by userspace to let the driver know how much
space was allocated for output. It is populated by the driver to
let userspace know how large the output payload actually was.
``out.rsvd``
Must be zero.
``out.payload``
Pointer to memory for payload output, payload is little endian.h](j] )}(h**Definition**::h](j )}(h**Definition**h]h
Definition}(hja hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj] ubh:}(hj] hhhNhNubeh }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjY ubj )}(hXs struct cxl_send_command {
__u32 id;
__u32 flags;
union {
struct {
__u16 opcode;
__u16 rsvd;
} raw;
__u32 rsvd;
};
__u32 retval;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} in;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} out;
};h]hXs struct cxl_send_command {
__u32 id;
__u32 flags;
union {
struct {
__u16 opcode;
__u16 rsvd;
} raw;
__u32 rsvd;
};
__u32 retval;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} in;
struct {
__u32 size;
__u32 rsvd;
__u64 payload;
} out;
};}hjz sbah }(h ]h ]h"]h$]h&]hhuh1j hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjY ubj] )}(h **Members**h]j )}(hj h]hMembers}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjY ubjo )}(hhh](jt )}(hq``id``
The command to send to the memory device. This must be one of the
commands returned by the query command.
h](jz )}(h``id``h]j )}(hj h]hid}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(hiThe command to send to the memory device. This must be one of the
commands returned by the query command.h]hiThe command to send to the memory device. This must be one of the
commands returned by the query command.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h)``flags``
Flags for the command (input).
h](jz )}(h ``flags``h]j )}(hj h]hflags}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h Flags for the command (input).h]h Flags for the command (input).}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h ``{unnamed_union}``
anonymous
h](jz )}(h``{unnamed_union}``h]j )}(hj h]h{unnamed_union}}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h anonymoush]h anonymous}(hj6 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj2 hKhj3 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj2 hKhj ubjt )}(h(``raw``
Special fields for raw commands
h](jz )}(h``raw``h]j )}(hjV h]hraw}(hjX hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjT ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjP ubj )}(hhh]j] )}(h Special fields for raw commandsh]h Special fields for raw commands}(hjo hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjk hKhjl ubah }(h ]h ]h"]h$]h&]uh1j hjP ubeh }(h ]h ]h"]h$]h&]uh1js hjk hKhj ubjt )}(hE``raw.opcode``
Opcode passed to hardware when using the RAW command.
h](jz )}(h``raw.opcode``h]j )}(hj h]h
raw.opcode}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h5Opcode passed to hardware when using the RAW command.h]h5Opcode passed to hardware when using the RAW command.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h``raw.rsvd``
Must be zero.
h](jz )}(h ``raw.rsvd``h]j )}(hj h]hraw.rsvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h
Must be zero.h]h
Must be zero.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h``rsvd``
Must be zero.
h](jz )}(h``rsvd``h]j )}(hj h]hrsvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h
Must be zero.h]h
Must be zero.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h9``retval``
Return value from the memory device (output).
h](jz )}(h
``retval``h]j )}(hj: h]hretval}(hj< hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj8 ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj4 ubj )}(hhh]j] )}(h-Return value from the memory device (output).h]h-Return value from the memory device (output).}(hjS hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjO hKhjP ubah }(h ]h ]h"]h$]h&]uh1j hj4 ubeh }(h ]h ]h"]h$]h&]uh1js hjO hKhj ubjt )}(h1``in``
Parameters associated with input payload.
h](jz )}(h``in``h]j )}(hjs h]hin}(hju hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjq ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjm ubj )}(hhh]j] )}(h)Parameters associated with input payload.h]h)Parameters associated with input payload.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hjm ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(hB``in.size``
Size of the payload to provide to the device (input).
h](jz )}(h ``in.size``h]j )}(hj h]hin.size}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h5Size of the payload to provide to the device (input).h]h5Size of the payload to provide to the device (input).}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h``in.rsvd``
Must be zero.
h](jz )}(h ``in.rsvd``h]j )}(hj h]hin.rsvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h
Must be zero.h]h
Must be zero.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(hN``in.payload``
Pointer to memory for payload input, payload is little endian.
h](jz )}(h``in.payload``h]j )}(hj h]h
in.payload}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h>Pointer to memory for payload input, payload is little endian.h]h>Pointer to memory for payload input, payload is little endian.}(hj7 hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj3 hKhj4 ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj3 hKhj ubjt )}(h3``out``
Parameters associated with output payload.
h](jz )}(h``out``h]j )}(hjW h]hout}(hjY hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjU ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhjQ ubj )}(hhh]j] )}(h*Parameters associated with output payload.h]h*Parameters associated with output payload.}(hjp hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hjl hKhjm ubah }(h ]h ]h"]h$]h&]uh1j hjQ ubeh }(h ]h ]h"]h$]h&]uh1js hjl hKhj ubjt )}(hX ``out.size``
Size of the payload received from the device (input/output). This
field is filled in by userspace to let the driver know how much
space was allocated for output. It is populated by the driver to
let userspace know how large the output payload actually was.
h](jz )}(h ``out.size``h]j )}(hj h]hout.size}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(hX Size of the payload received from the device (input/output). This
field is filled in by userspace to let the driver know how much
space was allocated for output. It is populated by the driver to
let userspace know how large the output payload actually was.h]hX Size of the payload received from the device (input/output). This
field is filled in by userspace to let the driver know how much
space was allocated for output. It is populated by the driver to
let userspace know how large the output payload actually was.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(h``out.rsvd``
Must be zero.
h](jz )}(h ``out.rsvd``h]j )}(hj h]hout.rsvd}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h
Must be zero.h]h
Must be zero.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hj hKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubjt )}(hO``out.payload``
Pointer to memory for payload output, payload is little endian.h](jz )}(h``out.payload``h]j )}(hj h]h out.payload}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hj ubah }(h ]h ]h"]h$]h&]uh1jy hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubj )}(hhh]j] )}(h?Pointer to memory for payload output, payload is little endian.h]h?Pointer to memory for payload output, payload is little endian.}(hj hhhNhNubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj ubah }(h ]h ]h"]h$]h&]uh1j hj ubeh }(h ]h ]h"]h$]h&]uh1js hj hKhj ubeh }(h ]h ]h"]h$]h&]uh1jn hjY ubeh }(h ]h ] kernelindentah"]h$]h&]uh1j hj hhhj hNubj] )}(h**Description**h]j )}(hjF h]h Description}(hjH hhhNhNubah }(h ]h ]h"]h$]h&]uh1j hjD ubah }(h ]h ]h"]h$]h&]uh1j\ hp/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/theory-of-operation:500: ./include/uapi/linux/cxl_mem.hhKhj hhubj] )}(hX/ Mechanism for userspace to send a command to the hardware for processing. The
driver will do basic validation on the command sizes. In some cases even the
payload may be introspected. Userspace is required to allocate large enough
buffers for size_out which can be variable length in certain situations.h]hX/ Mechanism for userspace to send a command to the hardware for processing. The
driver will do basic validation on the command sizes. In some cases even the
payload may be introspected. Userspace is required to allocate large enough
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