€•Â;      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ0/translations/zh_CN/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/zh_TW/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/it_IT/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ja_JP/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ko_KR/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/pt_BR/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/sp_SP/driver-api/cxl/platform/cdat”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³ŒJ/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/platform/cdat.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ&Coherent Device Attribute Table (CDAT)”h]”hŒ&Coherent Device Attribute Table (CDAT)”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hX  The CDAT provides functional and performance attributes of devices such
as CXL accelerators, switches, or endpoints.  The table formatting is
similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
be enumerated at runtime (after device hotplug, for example).”h]”hX  The CDAT provides functional and performance attributes of devices such
as CXL accelerators, switches, or endpoints.  The table formatting is
similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
be enumerated at runtime (after device hotplug, for example).”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hŒuTerminology:
DPA - Device Physical Address, used by the CXL device to denote the address
it supports for that device.”h]”hŒuTerminology:
DPA - Device Physical Address, used by the CXL device to denote the address
it supports for that device.”…””}”(hhíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hŒdDSMADHandle - A device unique handle that is associated with a DPA range
defined by the DSMAS table.”h]”hŒdDSMADHandle - A device unique handle that is associated with a DPA range
defined by the DSMAS table.”…””}”(hhûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubeh}”(h]”Œ$coherent-device-attribute-table-cdat”ah ]”h"]”Œ&coherent device attribute table (cdat)”ah$]”h&]”uh1hÈhhh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ/Device Scoped Memory Affinity Structure (DSMAS)”h]”hŒ/Device Scoped Memory Affinity Structure (DSMAS)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj  h²hh³hÇh´KubhÞ)”}”(hŒQThe DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
Length.”h]”hŒQThe DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
Length.”…””}”(hj"  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj  h²hubhÞ)”}”(hŒ¸This table is used by Linux in conjunction with the Device Scoped Latency and
Bandwidth Information Structure (DSLBIS) to determine the performance
attributes of the CXL device itself.”h]”hŒ¸This table is used by Linux in conjunction with the Device Scoped Latency and
Bandwidth Information Structure (DSLBIS) to determine the performance
attributes of the CXL device itself.”…””}”(hj0  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj  h²hubhÞ)”}”(hŒ
Example ::”h]”hŒExample”…””}”(hj>  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj  h²hubhŒliteral_block”“”)”}”(hX
  Structure Type : 00 [DSMAS]
      Reserved : 00
        Length : 0018              <- 24d, size of structure
   DSMADHandle : 01
         Flags : 00
      Reserved : 0000
      DPA Base : 0000000040000000  <- 1GiB base
    DPA Length : 0000000080000000  <- 2GiB size”h]”hX
  Structure Type : 00 [DSMAS]
      Reserved : 00
        Length : 0018              <- 24d, size of structure
   DSMADHandle : 01
         Flags : 00
      Reserved : 0000
      DPA Base : 0000000040000000  <- 1GiB base
    DPA Length : 0000000080000000  <- 2GiB size”…””}”hjN  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jL  h³hÇh´K!hj  h²hubeh}”(h]”Œ-device-scoped-memory-affinity-structure-dsmas”ah ]”h"]”Œ/device scoped memory affinity structure (dsmas)”ah$]”h&]”uh1hÈhhh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒBDevice Scoped Latency and Bandwidth Information Structure (DSLBIS)”h]”hŒBDevice Scoped Latency and Bandwidth Information Structure (DSLBIS)”…””}”(hjg  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjd  h²hh³hÇh´K-ubhÞ)”}”(hŒÄThis table is used by Linux in conjunction with DSMAS to determine the
performance attributes of a CXL device.  The DSLBIS contains latency
and bandwidth information based on DSMADHandle matching.”h]”hŒÄThis table is used by Linux in conjunction with DSMAS to determine the
performance attributes of a CXL device.  The DSLBIS contains latency
and bandwidth information based on DSMADHandle matching.”…””}”(hju  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K/hjd  h²hubhÞ)”}”(hŒ
Example ::”h]”hŒExample”…””}”(hjƒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K3hjd  h²hubjM  )”}”(hXÛ    Structure Type : 01 [DSLBIS]
        Reserved : 00
          Length : 18                     <- 24d, size of structure
          Handle : 0001                   <- DSMAS handle
           Flags : 00                     <- Matches flag field for HMAT SLLBIS
       Data Type : 00                     <- Latency
Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
           Entry : 010000000000           <- First byte used here, CXL LTC
        Reserved : 0000

  Structure Type : 01 [DSLBIS]
        Reserved : 00
          Length : 18                     <- 24d, size of structure
          Handle : 0001                   <- DSMAS handle
           Flags : 00                     <- Matches flag field for HMAT SLLBIS
       Data Type : 03                     <- Bandwidth
Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
           Entry : 020000000000           <- First byte used here, CXL BW
        Reserved : 0000”h]”hXÛ    Structure Type : 01 [DSLBIS]
        Reserved : 00
          Length : 18                     <- 24d, size of structure
          Handle : 0001                   <- DSMAS handle
           Flags : 00                     <- Matches flag field for HMAT SLLBIS
       Data Type : 00                     <- Latency
Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
           Entry : 010000000000           <- First byte used here, CXL LTC
        Reserved : 0000

  Structure Type : 01 [DSLBIS]
        Reserved : 00
          Length : 18                     <- 24d, size of structure
          Handle : 0001                   <- DSMAS handle
           Flags : 00                     <- Matches flag field for HMAT SLLBIS
       Data Type : 03                     <- Bandwidth
Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
           Entry : 020000000000           <- First byte used here, CXL BW
        Reserved : 0000”…””}”hj‘  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jL  h³hÇh´K5hjd  h²hubeh}”(h]”Œ@device-scoped-latency-and-bandwidth-information-structure-dslbis”ah ]”h"]”ŒBdevice scoped latency and bandwidth information structure (dslbis)”ah$]”h&]”uh1hÈhhh²hh³hÇh´K-ubhÉ)”}”(hhh]”(hÎ)”}”(hŒBSwitch Scoped Latency and Bandwidth Information Structure (SSLBIS)”h]”hŒBSwitch Scoped Latency and Bandwidth Information Structure (SSLBIS)”…””}”(hjª  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj§  h²hh³hÇh´KLubhÞ)”}”(hŒLThe SSLBIS contains information about the latency and bandwidth of a switch.”h]”hŒLThe SSLBIS contains information about the latency and bandwidth of a switch.”…””}”(hj¸  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KNhj§  h²hubhÞ)”}”(hŒ”The table is used by Linux to compute the performance coordinates of a CXL path
from the device to the root port where a switch is part of the path.”h]”hŒ”The table is used by Linux to compute the performance coordinates of a CXL path
from the device to the root port where a switch is part of the path.”…””}”(hjÆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KPhj§  h²hubhÞ)”}”(hŒ
Example ::”h]”hŒExample”…””}”(hjÔ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KShj§  h²hubjM  )”}”(hX±   Structure Type : 05 [SSLBIS]
       Reserved : 00
         Length : 20                           <- 32d, length of record, including SSLB entries
      Data Type : 00                           <- Latency
       Reserved : 000000
Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS

                                               <- SSLB Entry 0
      Port X ID : 0100                         <- First port, 0100h represents an upstream port
      Port Y ID : 0000                         <- Second port, downstream port 0
        Latency : 0100                         <- Port latency
       Reserved : 0000
                                               <- SSLB Entry 1
      Port X ID : 0100
      Port Y ID : 0001
        Latency : 0100
       Reserved : 0000


 Structure Type : 05 [SSLBIS]
       Reserved : 00
         Length : 18                           <- 24d, length of record, including SSLB entry
      Data Type : 03                           <- Bandwidth
       Reserved : 000000
Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS

                                               <- SSLB Entry 0
      Port X ID : 0100                         <- First port, 0100h represents an upstream port
      Port Y ID : FFFF                         <- Second port, FFFFh indicates any port
      Bandwidth : 1200                         <- Port bandwidth
       Reserved : 0000”h]”hX±   Structure Type : 05 [SSLBIS]
       Reserved : 00
         Length : 20                           <- 32d, length of record, including SSLB entries
      Data Type : 00                           <- Latency
       Reserved : 000000
Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS

                                               <- SSLB Entry 0
      Port X ID : 0100                         <- First port, 0100h represents an upstream port
      Port Y ID : 0000                         <- Second port, downstream port 0
        Latency : 0100                         <- Port latency
       Reserved : 0000
                                               <- SSLB Entry 1
      Port X ID : 0100
      Port Y ID : 0001
        Latency : 0100
       Reserved : 0000


 Structure Type : 05 [SSLBIS]
       Reserved : 00
         Length : 18                           <- 24d, length of record, including SSLB entry
      Data Type : 03                           <- Bandwidth
       Reserved : 000000
Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS

                                               <- SSLB Entry 0
      Port X ID : 0100                         <- First port, 0100h represents an upstream port
      Port Y ID : FFFF                         <- Second port, FFFFh indicates any port
      Bandwidth : 1200                         <- Port bandwidth
       Reserved : 0000”…””}”hjâ  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jL  h³hÇh´KUhj§  h²hubhÞ)”}”(hŒThe CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
generate "whole path performance" data for a CXL device.”h]”hŒ…The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
generate â€œwhole path performanceâ€ data for a CXL device.”…””}”(hjð  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kuhj§  h²hubeh}”(h]”Œ@switch-scoped-latency-and-bandwidth-information-structure-sslbis”ah ]”h"]”ŒBswitch scoped latency and bandwidth information structure (sslbis)”ah$]”h&]”uh1hÈhhh²hh³hÇh´KLubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
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