ˍsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget8/translations/zh_CN/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget8/translations/zh_TW/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget8/translations/it_IT/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget8/translations/ja_JP/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget8/translations/ko_KR/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget8/translations/sp_SP/driver-api/cxl/platform/bios-and-efimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhR/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/platform/bios-and-efi.rsthKubhsection)}(hhh](htitle)}(hBIOS/EFI Configurationh]hBIOS/EFI Configuration}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hBIOS and EFI are largely responsible for configuring static information about devices (or potential future devices) such that Linux can build the appropriate logical representations of these devices.h]hBIOS and EFI are largely responsible for configuring static information about devices (or potential future devices) such that Linux can build the appropriate logical representations of these devices.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hHAt a high level, this is what occurs during this phase of configuration.h]hHAt a high level, this is what occurs during this phase of configuration.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh bullet_list)}(hhh](h list_item)}(h$The bootloader starts the BIOS/EFI. h]h)}(h#The bootloader starts the BIOS/EFI.h]h#The bootloader starts the BIOS/EFI.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hABIOS/EFI do early device probe to determine static configuration h]h)}(h@BIOS/EFI do early device probe to determine static configurationh]h@BIOS/EFI do early device probe to determine static configuration}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hDBIOS/EFI creates ACPI Tables that describe static config for the OS h]h)}(hCBIOS/EFI creates ACPI Tables that describe static config for the OSh]hCBIOS/EFI creates ACPI Tables that describe static config for the OS}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hBBIOS/EFI create the system memory map (EFI Memory Map, E820, etc) h]h)}(hABIOS/EFI create the system memory map (EFI Memory Map, E820, etc)h]hABIOS/EFI create the system memory map (EFI Memory Map, E820, etc)}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hMBIOS/EFI calls :code:`start_kernel` and begins the Linux Early Boot process. h]h)}(hLBIOS/EFI calls :code:`start_kernel` and begins the Linux Early Boot process.h](hBIOS/EFI calls }(hjRhhhNhNubhliteral)}(h:code:`start_kernel`h]h start_kernel}(hj\hhhNhNubah}(h]h ]codeah"]h$]h&]languagehuh1jZhjRubh) and begins the Linux Early Boot process.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1hhhhK hhhhubh)}(hMuch of what this section is concerned with is ACPI Table production and static memory map configuration. More detail on these tables can be found at :doc:`ACPI Tables `.h](hMuch of what this section is concerned with is ACPI Table production and static memory map configuration. More detail on these tables can be found at }(hjhhhNhNubh)}(h:doc:`ACPI Tables `h]hinline)}(hjh]h ACPI Tables}(hjhhhNhNubah}(h]h ](xrefstdstd-doceh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc$driver-api/cxl/platform/bios-and-efi refdomainjreftypedoc refexplicitrefwarn reftargetacpiuh1hhhhKhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhnote)}(hPlatform Vendors should read carefully, as this sections has recommendations on physical memory region size and alignment, memory holes, HDM interleave, and what linux expects of HDM decoders trying to work with these features.h]h)}(hPlatform Vendors should read carefully, as this sections has recommendations on physical memory region size and alignment, memory holes, HDM interleave, and what linux expects of HDM decoders trying to work with these features.h]hPlatform Vendors should read carefully, as this sections has recommendations on physical memory region size and alignment, memory holes, HDM interleave, and what linux expects of HDM decoders trying to work with these features.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubh)}(hhh](h)}(h UEFI Settingsh]h UEFI Settings}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK!ubh)}(hIf your platform supports it, the :code:`uefisettings` command can be used to read/write EFI settings. Changes will be reflected on the next reboot. Kexec is not a sufficient reboot.h](h"If your platform supports it, the }(hjhhhNhNubj[)}(h:code:`uefisettings`h]h uefisettings}(hjhhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhjubh command can be used to read/write EFI settings. Changes will be reflected on the next reboot. Kexec is not a sufficient reboot.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjhhubh)}(hX:One notable configuration here is the EFI_MEMORY_SP (Specific Purpose) bit. When this is enabled, this bit tells linux to defer management of a memory region to a driver (in this case, the CXL driver). Otherwise, the memory is treated as "normal memory", and is exposed to the page allocator during :code:`__init`.h](hX/One notable configuration here is the EFI_MEMORY_SP (Specific Purpose) bit. When this is enabled, this bit tells linux to defer management of a memory region to a driver (in this case, the CXL driver). Otherwise, the memory is treated as “normal memory”, and is exposed to the page allocator during }(hjhhhNhNubj[)}(h:code:`__init`h]h__init}(hjhhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubh)}(hhh](h)}(huefisettings examplesh]huefisettings examples}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhK-ubh)}(h :code:`uefisettings identify` ::h]j[)}(h:code:`uefisettings identify`h]huefisettings identify}(hj=hhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhj9ubah}(h]h ]h"]h$]h&]uh1hhhhK/hj(hhubh literal_block)}(huefisettings identify bios_vendor: xxx bios_version: xxx bios_release: xxx bios_date: xxx product_name: xxx product_family: xxx product_version: xxxh]huefisettings identify bios_vendor: xxx bios_version: xxx bios_release: xxx bios_date: xxx product_name: xxx product_family: xxx product_version: xxx}hjTsbah}(h]h ]h"]h$]h&]hhuh1jRhhhK1hj(hhubh)}(hOn some AMD platforms, the :code:`EFI_MEMORY_SP` bit is set via the :code:`CXL Memory Attribute` field. This may be called something else on your platform.h](hOn some AMD platforms, the }(hjbhhhNhNubj[)}(h:code:`EFI_MEMORY_SP`h]h EFI_MEMORY_SP}(hjjhhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhjbubh bit is set via the }(hjbhhhNhNubj[)}(h:code:`CXL Memory Attribute`h]hCXL Memory Attribute}(hj}hhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhjbubh< field. This may be called something else on your platform.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK;hj(hhubh)}(h2:code:`uefisettings get "CXL Memory Attribute"` ::h]j[)}(h/:code:`uefisettings get "CXL Memory Attribute"`h]h'uefisettings get "CXL Memory Attribute"}(hjhhhNhNubah}(h]h ]jgah"]h$]h&]languagehuh1jZhjubah}(h]h ]h"]h$]h&]uh1hhhhK>hj(hhubjS)}(hiselector: xxx ... question: Question { name: "CXL Memory Attribute", answer: "Enabled", ... }h]hiselector: xxx ... question: Question { name: "CXL Memory Attribute", answer: "Enabled", ... }}hjsbah}(h]h ]h"]h$]h&]hhuh1jRhhhK@hj(hhubeh}(h]uefisettings-examplesah ]h"]uefisettings examplesah$]h&]uh1hhjhhhhhK-ubeh}(h] uefi-settingsah ]h"] uefi settingsah$]h&]uh1hhhhhhhhK!ubh)}(hhh](h)}(hPhysical Memory Maph]hPhysical Memory Map}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKIubh)}(hhh](h)}(h!Physical Address Region Alignmenth]h!Physical Address Region Alignment}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKLubh)}(hXAs of Linux v6.14, the hotplug memory system requires memory regions to be uniform in size and alignment. While the CXL specification allows for memory regions as small as 256MB, the supported memory block size and alignment for hotplugged memory is architecture-defined.h]hXAs of Linux v6.14, the hotplug memory system requires memory regions to be uniform in size and alignment. While the CXL specification allows for memory regions as small as 256MB, the supported memory block size and alignment for hotplugged memory is architecture-defined.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh)}(hMA Linux memory blocks may be as small as 128MB and increase in powers of two.h]hMA Linux memory blocks may be as small as 128MB and increase in powers of two.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjhhubh)}(hhh](h)}(hGOn ARM, the default block size and alignment is either 128MB or 256MB. h]h)}(hFOn ARM, the default block size and alignment is either 128MB or 256MB.h]hFOn ARM, the default block size and alignment is either 128MB or 256MB.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hrOn x86, the default block size is 256MB, and increases to 2GB as the capacity of the system increases up to 64GB. h]h)}(hqOn x86, the default block size is 256MB, and increases to 2GB as the capacity of the system increases up to 64GB.h]hqOn x86, the default block size is 256MB, and increases to 2GB as the capacity of the system increases up to 64GB.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhj&ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKUhjhhubh)}(hFor best support across versions, platform vendors should place CXL memory at a 2GB aligned base address, and regions should be 2GB aligned. This also helps prevent the creating thousands of memory devices (one per block).h]hFor best support across versions, platform vendors should place CXL memory at a 2GB aligned base address, and regions should be 2GB aligned. This also helps prevent the creating thousands of memory devices (one per block).}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjhhubeh}(h]!physical-address-region-alignmentah ]h"]!physical address region alignmentah$]h&]uh1hhjhhhhhKLubh)}(hhh](h)}(h Memory Holesh]h Memory Holes}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhK_ubh)}(hHoles in the memory map are tricky. Consider a 4GB device located at base address 0x100000000, but with the following memory map ::h]hHoles in the memory map are tricky. Consider a 4GB device located at base address 0x100000000, but with the following memory map}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjZhhubjS)}(hX--------------------- | 0x100000000 | | CXL | | 0x1BFFFFFFF | --------------------- | 0x1C0000000 | | MEMORY HOLE | | 0x1FFFFFFFF | --------------------- | 0x200000000 | | CXL CONT. | | 0x23FFFFFFF | ---------------------h]hX--------------------- | 0x100000000 | | CXL | | 0x1BFFFFFFF | --------------------- | 0x1C0000000 | | MEMORY HOLE | | 0x1FFFFFFFF | --------------------- | 0x200000000 | | CXL CONT. | | 0x23FFFFFFF | ---------------------}hjysbah}(h]h ]h"]h$]h&]hhuh1jRhhhKdhjZhhubh)}(h!There are two issues to consider:h]h!There are two issues to consider:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhjZhhubh)}(hhh](h)}(hdecoder programming, andh]h)}(hjh]hdecoder programming, and}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(hmemory block alignment. h]h)}(hmemory block alignment.h]hmemory block alignment.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKthjZhhubh)}(hX If your architecture requires 2GB uniform size and aligned memory blocks, the only capacity Linux is capable of mapping (as of v6.14) would be the capacity from `0x100000000-0x180000000`. The remaining capacity will be stranded, as they are not of 2GB aligned length.h](hIf your architecture requires 2GB uniform size and aligned memory blocks, the only capacity Linux is capable of mapping (as of v6.14) would be the capacity from }(hjhhhNhNubhtitle_reference)}(h`0x100000000-0x180000000`h]h0x100000000-0x180000000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhR. The remaining capacity will be stranded, as they are not of 2GB aligned length.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjZhhubh)}(hAssuming your architecture and memory configuration allows 1GB memory blocks, this memory map is supported and this should be presented as multiple CFMWS in the CEDT that describe each side of the memory hole separately - along with matching decoders.h]hAssuming your architecture and memory configuration allows 1GB memory blocks, this memory map is supported and this should be presented as multiple CFMWS in the CEDT that describe each side of the memory hole separately - along with matching decoders.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjZhhubh)}(hXEMultiple decoders can (and should) be used to manage such a memory hole (see below), but each chunk of a memory hole should be aligned to a reasonable block size (larger alignment is always better). If you intend to have memory holes in the memory map, expect to use one decoder per contiguous chunk of host physical memory.h]hXEMultiple decoders can (and should) be used to manage such a memory hole (see below), but each chunk of a memory hole should be aligned to a reasonable block size (larger alignment is always better). If you intend to have memory holes in the memory map, expect to use one decoder per contiguous chunk of host physical memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZhhubh)}(hAs of v6.14, Linux does provide support for memory hotplug of multiple physical memory regions separated by a memory hole described by a single HDM decoder.h]hAs of v6.14, Linux does provide support for memory hotplug of multiple physical memory regions separated by a memory hole described by a single HDM decoder.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZhhubeh}(h] memory-holesah ]h"]h$] memory holesah&]uh1hhjhhhhhK_ referencedKubeh}(h]physical-memory-mapah ]h"]physical memory mapah$]h&]uh1hhhhhhhhKIubh)}(hhh](h)}(hDecoder Programmingh]hDecoder Programming}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhhhKubh)}(hX'If BIOS/EFI intends to program the decoders to be statically configured, there are a few things to consider to avoid major pitfalls that will prevent Linux compatibility. Some of these recommendations are not required "per the specification", but Linux makes no guarantees of support otherwise.h]hX+If BIOS/EFI intends to program the decoders to be statically configured, there are a few things to consider to avoid major pitfalls that will prevent Linux compatibility. Some of these recommendations are not required “per the specification”, but Linux makes no guarantees of support otherwise.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj*hhubh)}(hhh](h)}(hTranslation Pointh]hTranslation Point}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhhhKubh)}(hPer the specification, the only decoders which **TRANSLATE** Host Physical Address (HPA) to Device Physical Address (DPA) are the **Endpoint Decoders**. All other decoders in the fabric are intended to route accesses without translating the addresses.h](h/Per the specification, the only decoders which }(hjZhhhNhNubhstrong)}(h **TRANSLATE**h]h TRANSLATE}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjZubhF Host Physical Address (HPA) to Device Physical Address (DPA) are the }(hjZhhhNhNubjc)}(h**Endpoint Decoders**h]hEndpoint Decoders}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjZubhd. All other decoders in the fabric are intended to route accesses without translating the addresses.}(hjZhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh)}(h5This is heavily implied by the specification, see: ::h]h2This is heavily implied by the specification, see:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubjS)}(hCXL Specification 3.1 8.2.4.20: CXL HDM Decoder Capability Structure - Implementation Note: CXL Host Bridge and Upstream Switch Port Decoder Flow - Implementation Note: Device Decoder Logich]hCXL Specification 3.1 8.2.4.20: CXL HDM Decoder Capability Structure - Implementation Note: CXL Host Bridge and Upstream Switch Port Decoder Flow - Implementation Note: Device Decoder Logic}hjsbah}(h]h ]h"]h$]h&]hhuh1jRhhhKhjIhhubh)}(hGiven this, Linux makes a strong assumption that decoders between CPU and endpoint will all be programmed with addresses ranges that are subsets of their parent decoder.h]hGiven this, Linux makes a strong assumption that decoders between CPU and endpoint will all be programmed with addresses ranges that are subsets of their parent decoder.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh)}(hXiDue to some ambiguity in how Architecture, ACPI, PCI, and CXL specifications "hand off" responsibility between domains, some early adopting platforms attempted to do translation at the originating memory controller or host bridge. This configuration requires a platform specific extension to the driver and is not officially endorsed - despite being supported.h]hXmDue to some ambiguity in how Architecture, ACPI, PCI, and CXL specifications “hand off” responsibility between domains, some early adopting platforms attempted to do translation at the originating memory controller or host bridge. This configuration requires a platform specific extension to the driver and is not officially endorsed - despite being supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh)}(h|It is *highly recommended* **NOT** to do this; otherwise, you are on your own to implement driver support for your platform.h](hIt is }(hjhhhNhNubhemphasis)}(h*highly recommended*h]hhighly recommended}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh }(hjhhhNhNubjc)}(h**NOT**h]hNOT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jbhjubhZ to do this; otherwise, you are on your own to implement driver support for your platform.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubeh}(h]translation-pointah ]h"]translation pointah$]h&]uh1hhj*hhhhhKubh)}(hhh](h)}(h(Interleave and Configuration Flexibilityh]h(Interleave and Configuration Flexibility}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hIf providing cross-host-bridge interleave, a CFMWS entry in the :doc:`CEDT ` must be presented with target host-bridges for the interleaved device sets (there may be multiple behind each host bridge).h](h@If providing cross-host-bridge interleave, a CFMWS entry in the }(hjhhhNhNubh)}(h:doc:`CEDT `h]j)}(hjh]hCEDT}(hjhhhNhNubah}(h]h ](jstdstd-doceh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainj)reftypedoc refexplicitrefwarnj acpi/cedtuh1hhhhKhjubh| must be presented with target host-bridges for the interleaved device sets (there may be multiple behind each host bridge).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hIf providing intra-host-bridge interleaving, only 1 CFMWS entry in the CEDT is required for that host bridge - if it covers the entire capacity of the devices behind the host bridge.h]hIf providing intra-host-bridge interleaving, only 1 CFMWS entry in the CEDT is required for that host bridge - if it covers the entire capacity of the devices behind the host bridge.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hIf intending to provide users flexibility in programming decoders beyond the root, you may want to provide multiple CFMWS entries in the CEDT intended for different purposes. For example, you may want to consider adding:h]hIf intending to provide users flexibility in programming decoders beyond the root, you may want to provide multiple CFMWS entries in the CEDT intended for different purposes. For example, you may want to consider adding:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhenumerated_list)}(hhh](h)}(h6A CFMWS entry to cover all interleavable host bridges.h]h)}(hjhh]h6A CFMWS entry to cover all interleavable host bridges.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjfubah}(h]h ]h"]h$]h&]uh1hhjchhhhhNubh)}(h;A CFMWS entry to cover all devices on a single host bridge.h]h)}(hjh]h;A CFMWS entry to cover all devices on a single host bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1hhjchhhhhNubh)}(h$A CFMWS entry to cover each device. h]h)}(h#A CFMWS entry to cover each device.h]h#A CFMWS entry to cover each device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjchhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1jahjhhhhhKubh)}(hXA platform may choose to add all of these, or change the mode based on a BIOS setting. For each CFMWS entry, Linux expects descriptions of the described memory regions in the :doc:`SRAT ` to determine the number of NUMA nodes it should reserve during early boot / init.h](hA platform may choose to add all of these, or change the mode based on a BIOS setting. For each CFMWS entry, Linux expects descriptions of the described memory regions in the }(hjhhhNhNubh)}(h:doc:`SRAT `h]j)}(hjh]hSRAT}(hjhhhNhNubah}(h]h ](jstdstd-doceh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypedoc refexplicitrefwarnj acpi/sratuh1hhhhKhjubhR to determine the number of NUMA nodes it should reserve during early boot / init.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hAs of v6.14, Linux will create a NUMA node for each CEDT CFMWS entry, even if a matching SRAT entry does not exist; however, this is not guaranteed in the future and such a configuration should be avoided.h]hAs of v6.14, Linux will create a NUMA node for each CEDT CFMWS entry, even if a matching SRAT entry does not exist; however, this is not guaranteed in the future and such a configuration should be avoided.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h](interleave-and-configuration-flexibilityah ]h"](interleave and configuration flexibilityah$]h&]uh1hhj*hhhhhKubh)}(hhh](h)}(h Memory Holesh]h Memory Holes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXIf your platform includes memory holes intersparsed between your CXL memory, it is recommended to utilize multiple decoders to cover these regions of memory, rather than try to program the decoders to accept the entire range and expect Linux to manage the overlap.h]hXIf your platform includes memory holes intersparsed between your CXL memory, it is recommended to utilize multiple decoders to cover these regions of memory, rather than try to program the decoders to accept the entire range and expect Linux to manage the overlap.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h8For example, consider the Memory Hole described above ::h]h5For example, consider the Memory Hole described above}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjS)}(hX--------------------- | 0x100000000 | | CXL | | 0x1BFFFFFFF | --------------------- | 0x1C0000000 | | MEMORY HOLE | | 0x1FFFFFFFF | --------------------- | 0x200000000 | | CXL CONT. | | 0x23FFFFFFF | ---------------------h]hX--------------------- | 0x100000000 | | CXL | | 0x1BFFFFFFF | --------------------- | 0x1C0000000 | | MEMORY HOLE | | 0x1FFFFFFFF | --------------------- | 0x200000000 | | CXL CONT. | | 0x23FFFFFFF | ---------------------}hj,sbah}(h]h ]h"]h$]h&]hhuh1jRhhhKhjhhubh)}(hAssuming this is provided by a single device attached directly to a host bridge, Linux would expect the following decoder programming ::h]hAssuming this is provided by a single device attached directly to a host bridge, Linux would expect the following decoder programming}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubjS)}(hX;----------------------- ----------------------- | root-decoder-0 | | root-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- ----------------------- | | ----------------------- ----------------------- | HB-decoder-0 | | HB-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- ----------------------- | | ----------------------- ----------------------- | ep-decoder-0 | | ep-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- -----------------------h]hX;----------------------- ----------------------- | root-decoder-0 | | root-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- ----------------------- | | ----------------------- ----------------------- | HB-decoder-0 | | HB-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- ----------------------- | | ----------------------- ----------------------- | ep-decoder-0 | | ep-decoder-1 | | base: 0x100000000 | | base: 0x200000000 | | size: 0xC0000000 | | size: 0x40000000 | ----------------------- -----------------------}hjHsbah}(h]h ]h"]h$]h&]hhuh1jRhhhKhjhhubh)}(hLWith a CEDT configuration with two CFMWS describing the above root decoders.h]hLWith a CEDT configuration with two CFMWS describing the above root decoders.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hGLinux makes no guarantee of support for strange memory hole situations.h]hGLinux makes no guarantee of support for strange memory hole situations.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]id1ah ]h"]h$]jah&]uh1hhj*hhhhhKj!Kubh)}(hhh](h)}(hMulti-Media Devicesh]hMulti-Media Devices}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhhhhhKubh)}(hThe CFMWS field of the CEDT has special restriction bits which describe whether the described memory region allows volatile or persistent memory (or both). If the platform intends to support either:h]hThe CFMWS field of the CEDT has special restriction bits which describe whether the described memory region allows volatile or persistent memory (or both). If the platform intends to support either:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyhhubjb)}(hhh](h)}(h!A device with multiple medias, orh]h)}(hjh]h!A device with multiple medias, or}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubh)}(h2Using a persistent memory device as normal memory h]h)}(h1Using a persistent memory device as normal memoryh]h1Using a persistent memory device as normal memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjhhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jahjyhhhhhMubh)}(hA platform may wish to create multiple CEDT CFMWS entries to describe the same memory, with the intent of allowing the end user flexibility in how that memory is configured. Linux does not presently have strong requirements in this area.h]hA platform may wish to create multiple CEDT CFMWS entries to describe the same memory, with the intent of allowing the end user flexibility in how that memory is configured. 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