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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h#Compute Express Link Memory Devicesh]h#Compute Express Link Memory Devices}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh paragraph)}(hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device's contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.h]hXA Compute Express Link Memory Device is a CXL component that implements the CXL.mem protocol. It contains some amount of volatile memory, persistent memory, or both. It is enumerated as a PCI device for configuration and passing messages over an MMIO mailbox. Its contribution to the System Physical Address space is handled via HDM (Host Managed Device Memory) decoders that optionally define a device’s contribution to an interleaved address range across multiple devices underneath a host-bridge or interleaved across host-bridges.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjIhhubjH)}(hhh](jM)}(hCXL Bus: Theory of Operationh]hCXL Bus: Theory of Operation}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjlhhhhhKubj])}(hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.h]hXSSimilar to how a RAID driver takes disk objects and assembles them into a new logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and assemble them into a CXL.mem decode topology. The need for runtime configuration of the CXL.mem topology is also similar to RAID in that different environments with the same hardware configuration may decide to assemble the topology in contrasting ways. One may choose performance (RAID0) striping memory across multiple Host Bridges and endpoints while another may opt for fault tolerance and disable any striping in the CXL.mem topology.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hXPlatform firmware enumerates a menu of interleave options at the "CXL root port" (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example platform firmware may say at a given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.h]hXPlatform firmware enumerates a menu of interleave options at the “CXL root port” (Linux term for the top of the CXL decode topology). From there, PCIe topology dictates which endpoints can participate in which Host Bridge decode regimes. Each PCIe Switch in the path between the root and an endpoint introduces a point at which the interleave can be split. For example platform firmware may say at a given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn interleave cycles across multiple Root Ports. An intervening Switch between a port and an endpoint may interleave cycles across multiple Downstream Switch Ports, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hX-Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test' module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints::h]hX4Here is a sample listing of a CXL topology defined by ‘cxl_test’. The ‘cxl_test’ module generates an emulated CXL topology of 2 Host Bridges each with 2 Root Ports. Each of those Root Ports are connected to 2-way switches with endpoints connected to those downstream ports for a total of 8 endpoints:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK&hjlhhubh literal_block)}(hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }h]hX# cxl list -BEMPu -b cxl_test { "bus":"root3", "provider":"cxl_test", "ports:root3":[ { "port":"port5", "host":"cxl_host_bridge.1", "ports:port5":[ { "port":"port8", "host":"cxl_switch_uport.1", "endpoints:port8":[ { "endpoint":"endpoint9", "host":"mem2", "memdev":{ "memdev":"mem2", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x1", "numa_node":1, "host":"cxl_mem.1" } }, { "endpoint":"endpoint15", "host":"mem6", "memdev":{ "memdev":"mem6", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x5", "numa_node":1, "host":"cxl_mem.5" } } ] }, { "port":"port12", "host":"cxl_switch_uport.3", "endpoints:port12":[ { "endpoint":"endpoint17", "host":"mem8", "memdev":{ "memdev":"mem8", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x7", "numa_node":1, "host":"cxl_mem.7" } }, { "endpoint":"endpoint13", "host":"mem4", "memdev":{ "memdev":"mem4", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x3", "numa_node":1, "host":"cxl_mem.3" } } ] } ] }, { "port":"port4", "host":"cxl_host_bridge.0", "ports:port4":[ { "port":"port6", "host":"cxl_switch_uport.0", "endpoints:port6":[ { "endpoint":"endpoint7", "host":"mem1", "memdev":{ "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" } }, { "endpoint":"endpoint14", "host":"mem5", "memdev":{ "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" } } ] }, { "port":"port10", "host":"cxl_switch_uport.2", "endpoints:port10":[ { "endpoint":"endpoint16", "host":"mem7", "memdev":{ "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } }, { "endpoint":"endpoint11", "host":"mem3", "memdev":{ "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } } ] } ] } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK+hjlhhubj])}(hXIn that listing each "root", "port", and "endpoint" object correspond a kernel 'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to its descendants. So "root" claims non-PCIe enumerable platform decode ranges and decodes them to "ports", "ports" decode to "endpoints", and "endpoints" represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).h]hXIn that listing each “root”, “port”, and “endpoint” object correspond a kernel ‘struct cxl_port’ object. A ‘cxl_port’ is a device that can decode CXL.mem to its descendants. So “root” claims non-PCIe enumerable platform decode ranges and decodes them to “ports”, “ports” decode to “endpoints”, and “endpoints” represent the decode from SPA (System Physical Address) to DPA (Device Physical Address).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hXContinuing the RAID analogy, disks have both topology metadata and on device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.h]hXContinuing the RAID analogy, disks have both topology metadata and on device metadata that determine RAID set assembly. CXL Port topology and CXL Port link status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port objects. Conversely for hot-unplug / removal scenarios, there is no need for the Linux PCI core to tear down switch-level CXL resources because the endpoint ->remove() event cleans up the port data that was established to support that Memory Expander.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hThe port metadata and potential decode schemes that a give memory device may participate can be determined via a command like::h]h~The port metadata and potential decode schemes that a give memory device may participate can be determined via a command like:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj)}(hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }h]hX# cxl list -BDMu -d root -m mem3 { "bus":"root3", "provider":"cxl_test", "decoders:root3":[ { "decoder":"decoder3.1", "resource":"0x8030000000", "size":"512.00 MiB (536.87 MB)", "volatile_capable":true, "nr_targets":2 }, { "decoder":"decoder3.3", "resource":"0x8060000000", "size":"512.00 MiB (536.87 MB)", "pmem_capable":true, "nr_targets":2 }, { "decoder":"decoder3.0", "resource":"0x8020000000", "size":"256.00 MiB (268.44 MB)", "volatile_capable":true, "nr_targets":1 }, { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ], "memdevs:root3":[ { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjlhhubj])}(hXF...which queries the CXL topology to ask "given CXL Memory Expander with a kernel device name of 'mem3' which platform level decode ranges may this device participate". A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resource it has. In this example mem3 can participate in one or more of a PMEM interleave that spans to Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.h]hXN...which queries the CXL topology to ask “given CXL Memory Expander with a kernel device name of ‘mem3’ which platform level decode ranges may this device participate”. A given expander can participate in multiple CXL.mem interleave sets simultaneously depending on how many decoder resource it has. In this example mem3 can participate in one or more of a PMEM interleave that spans to Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile memory interleave that spans 2 Host Bridges, and a Volatile memory interleave that only targets a single Host Bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjlhhubj])}(hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following::h]hConversely the memory devices that can participate in a given platform level decode scheme can be determined via a command like the following:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhMhjlhhubj)}(hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]h]hXF# cxl list -MDu -d 3.2 [ { "memdevs":[ { "memdev":"mem1", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0", "numa_node":0, "host":"cxl_mem.0" }, { "memdev":"mem5", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x4", "numa_node":0, "host":"cxl_mem.4" }, { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" }, { "memdev":"mem3", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x2", "numa_node":0, "host":"cxl_mem.2" } ] }, { "root decoders":[ { "decoder":"decoder3.2", "resource":"0x8050000000", "size":"256.00 MiB (268.44 MB)", "pmem_capable":true, "nr_targets":1 } ] } ]}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjlhhubj])}(hL...where the naming scheme for decoders is "decoder.".h]hP...where the naming scheme for decoders is “decoder.”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhM8hjlhhubeh}(h]cxl-bus-theory-of-operationah ]h"]cxl bus: theory of operationah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(hDriver Infrastructureh]hDriver Infrastructure}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj/hhhhhM;ubj])}(hFThis section covers the driver infrastructure for a CXL memory device.h]hFThis section covers the driver infrastructure for a CXL memory device.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhM=hj/hhubjH)}(hhh](jM)}(hCXL Memory Deviceh]hCXL Memory Device}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjNhhhhhM@ubj])}(hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn't CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.h]hXThis implements the PCI exclusive functionality for a CXL device as it is defined by the Compute Express Link specification. CXL devices may surface certain functionality even if it isn’t CXL enabled. While this driver is focused around the PCI specific aspects of a CXL device, it binds to the specific CXL memory device class code, and therefore the implementation of cxl_pci is focused around CXL memory devices.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:408: ./drivers/cxl/pci.chKhjNhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hThe driver has several responsibilities, mainly: - Create the memX device and register on the CXL bus. - Enumerate device's register interface and map them. - Registers nvdimm bridge device with cxl_core. - Registers a CXL mailbox with cxl_core. h](hterm)}(h0The driver has several responsibilities, mainly:h]h0The driver has several responsibilities, mainly:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:408: ./drivers/cxl/pci.chK hjuubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(h3Create the memX device and register on the CXL bus.h]j])}(hjh]h3Create the memX device and register on the CXL bus.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h3Enumerate device's register interface and map them.h]j])}(hjh]h5Enumerate device’s register interface and map them.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h-Registers nvdimm bridge device with cxl_core.h]j])}(hjh]h-Registers nvdimm bridge device with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:408: ./drivers/cxl/pci.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h'Registers a CXL mailbox with cxl_core. h]j])}(h&Registers a CXL mailbox with cxl_core.h]h&Registers a CXL mailbox with cxl_core.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jshjhK hjpubah}(h]h ]h"]h$]h&]uh1jnhjNhhhNhNubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](single$__cxl_pci_mbox_send_cmd (C function)c.__cxl_pci_mbox_send_cmdhNtauh1jhjNhhhNhNubhdesc)}(hhh](hdesc_signature)}(hYint __cxl_pci_mbox_send_cmd (struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h]hdesc_signature_line)}(hXint __cxl_pci_mbox_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_sig_keyword_type)}(hinth]hint}(hj4hhhNhNubah}(h]h ]ktah"]h$]h&]uh1j2hj.hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKubhdesc_sig_space)}(h h]h }(hjFhhhNhNubah}(h]h ]wah"]h$]h&]uh1jDhj.hhhjChKubh desc_name)}(h__cxl_pci_mbox_send_cmdh]h desc_sig_name)}(h__cxl_pci_mbox_send_cmdh]h__cxl_pci_mbox_send_cmd}(hj]hhhNhNubah}(h]h ]nah"]h$]h&]uh1j[hjWubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jUhj.hhhjChKubhdesc_parameterlist)}(h=(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *mbox_cmd)h](hdesc_parameter)}(hstruct cxl_mailbox *cxl_mboxh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhj|ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj|ubh)}(hhh]j\)}(h cxl_mailboxh]h cxl_mailbox}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jj_sbc.__cxl_pci_mbox_send_cmdasbuh1hhj|ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj|ubhdesc_sig_punctuation)}(h*h]h*}(hjhhhNhNubah}(h]h ]pah"]h$]h&]uh1jhj|ubj\)}(hcxl_mboxh]hcxl_mbox}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj|ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjvubj{)}(hstruct cxl_mbox_cmd *mbox_cmdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(h cxl_mbox_cmdh]h cxl_mbox_cmd}(hj!hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#modnameN classnameNjj)}j]jc.__cxl_pci_mbox_send_cmdasbuh1hhjubjE)}(h h]h }(hj?hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hmbox_cmdh]hmbox_cmd}(hjZhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjvubeh}(h]h ]h"]h$]h&]hhuh1jthj.hhhjChKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1j,sphinx_line_type declaratorhj(hhhjChKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j&hjChKhj#hhubh desc_content)}(hhh]j])}(hExecute a mailbox commandh]hExecute a mailbox command}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjhhubah}(h]h ]h"]h$]h&]uh1jhj#hhhjChKubeh}(h]h ](jfunctioneh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1j!hhhjNhNhNubh container)}(hX**Parameters** ``struct cxl_mailbox *cxl_mbox`` CXL mailbox context ``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. **Context** Any context. Expects mbox_mutex to be held. **Return** -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded. **Description** This is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command. The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h](j])}(h**Parameters**h]hstrong)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubjo)}(hhh](jt)}(h5``struct cxl_mailbox *cxl_mbox`` CXL mailbox context h](jz)}(h ``struct cxl_mailbox *cxl_mbox``h]hliteral)}(hjh]hstruct cxl_mailbox *cxl_mbox}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubj)}(hhh]j])}(hCXL mailbox contexth]hCXL mailbox context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(hH``struct cxl_mbox_cmd *mbox_cmd`` Command to send to the memory device. h](jz)}(h!``struct cxl_mbox_cmd *mbox_cmd``h]j)}(hj h]hstruct cxl_mbox_cmd *mbox_cmd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhj ubj)}(hhh]j])}(h%Command to send to the memory device.h]h%Command to send to the memory device.}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj) hKhj* ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj) hKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Context**h]j)}(hjO h]hContext}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubj])}(h+Any context. Expects mbox_mutex to be held.h]h+Any context. Expects mbox_mutex to be held.}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubj])}(h **Return**h]j)}(hjv h]hReturn}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubjo)}(hhh]jt)}(h-ETIMEDOUT if timeout occurred waiting for completion. 0 on success. Caller should check the return code in **mbox_cmd** to make sure it succeeded. h](jz)}(hD-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.h]hD-ETIMEDOUT if timeout occurred waiting for completion. 0 on success.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhj ubj)}(hhh]j])}(hNCaller should check the return code in **mbox_cmd** to make sure it succeeded.h](h'Caller should check the return code in }(hj hhhNhNubj)}(h **mbox_cmd**h]hmbox_cmd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh to make sure it succeeded.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hKhj ubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hj h]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubj])}(hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.h]hXTThis is a generic form of the CXL mailbox send command thus only using the registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory devices, and perhaps other types of CXL devices may have further information available upon error conditions. Driver facilities wishing to send mailbox commands should use the wrapper command.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubj])}(hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.h]hX7The CXL spec allows for up to two mailboxes. The intention is for the primary mailbox to be OS controlled and the secondary mailbox to be used by system firmware. This allows the OS and firmware to communicate with the device and not need to coordinate with each other. The driver only uses the primary mailbox.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:411: ./drivers/cxl/pci.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.h]hCXL memory endpoint devices and switches are CXL capable devices that are participating in CXL.mem protocol. Their functionality builds on top of the CXL.io protocol that allows enumerating and configuring components via standard PCI mechanisms.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:414: ./drivers/cxl/mem.chK hjNhhubj])}(hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.h]hXThe cxl_mem driver owns kicking off the enumeration of this CXL.mem capability. With the detection of a CXL capable endpoint, the driver will walk up to find the platform specific port it is connected to, and determine if there are intervening switches in the path. If there are switches, a secondary action is to enumerate those (implemented in cxl_core). Finally the cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use in higher level operations.}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:414: ./drivers/cxl/mem.chKhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_memdev (C struct) c.cxl_memdevhNtauh1jhjNhhhNhNubj")}(hhh](j')}(h cxl_memdevh]j-)}(hstruct cxl_memdevh](j)}(hjh]hstruct}(hjL hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjH hhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKubjE)}(h h]h }(hjZ hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjH hhhjY hKubjV)}(h cxl_memdevh]j\)}(hjF h]h cxl_memdev}(hjl hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjh ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjH hhhjY hKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjD hhhjY hKubah}(h]j? ah ](jjeh"]h$]h&]jj)jhuh1j&hjY hKhjA hhubj)}(hhh]j])}(h2CXL bus object representing a Type-3 Memory Deviceh]h2CXL bus object representing a Type-3 Memory Device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK&hj hhubah}(h]h ]h"]h$]h&]uh1jhjA hhhjY hKubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j!hhhjNhNhNubj)}(hX%**Definition**:: struct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; }; **Members** ``dev`` driver core device object ``cdev`` char dev core object for ioctl operations ``cxlds`` The device state backing this device ``detach_work`` active memdev lost a port in its ancestry ``cxl_nvb`` coordinate removal of **cxl_nvd** if present ``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem ``endpoint`` connection to the CXL port topology for this memory device ``id`` id number of this memdev instance. ``depth`` endpoint port depthh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK*hj ubj)}(hX struct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; };h]hX struct cxl_memdev { struct device dev; struct cdev cdev; struct cxl_dev_state *cxlds; struct work_struct detach_work; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_nvdimm *cxl_nvd; struct cxl_port *endpoint; int id; int depth; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK,hj ubj])}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK8hj ubjo)}(hhh](jt)}(h"``dev`` driver core device object h](jz)}(h``dev``h]j)}(hj h]hdev}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK(hj ubj)}(hhh]j])}(hdriver core device objecth]hdriver core device object}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK(hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK(hj ubjt)}(h3``cdev`` char dev core object for ioctl operations h](jz)}(h``cdev``h]j)}(hj4 h]hcdev}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2 ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK)hj. ubj)}(hhh]j])}(h)char dev core object for ioctl operationsh]h)char dev core object for ioctl operations}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjI hK)hjJ ubah}(h]h ]h"]h$]h&]uh1jhj. ubeh}(h]h ]h"]h$]h&]uh1jshjI hK)hj ubjt)}(h/``cxlds`` The device state backing this device h](jz)}(h ``cxlds``h]j)}(hjm h]hcxlds}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK*hjg ubj)}(hhh]j])}(h$The device state backing this deviceh]h$The device state backing this device}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK*hj ubah}(h]h ]h"]h$]h&]uh1jhjg ubeh}(h]h ]h"]h$]h&]uh1jshj hK*hj ubjt)}(h:``detach_work`` active memdev lost a port in its ancestry h](jz)}(h``detach_work``h]j)}(hj h]h detach_work}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK+hj ubj)}(hhh]j])}(h)active memdev lost a port in its ancestryh]h)active memdev lost a port in its ancestry}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK+hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK+hj ubjt)}(h9``cxl_nvb`` coordinate removal of **cxl_nvd** if present h](jz)}(h ``cxl_nvb``h]j)}(hj h]hcxl_nvb}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK,hj ubj)}(hhh]j])}(h,coordinate removal of **cxl_nvd** if presenth](hcoordinate removal of }(hj hhhNhNubj)}(h **cxl_nvd**h]hcxl_nvd}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh if present}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj hK,hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK,hj ubjt)}(hE``cxl_nvd`` optional bridge to an nvdimm if the device supports pmem h](jz)}(h ``cxl_nvd``h]j)}(hj* h]hcxl_nvd}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj( ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK-hj$ ubj)}(hhh]j])}(h8optional bridge to an nvdimm if the device supports pmemh]h8optional bridge to an nvdimm if the device supports pmem}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj? hK-hj@ ubah}(h]h ]h"]h$]h&]uh1jhj$ ubeh}(h]h ]h"]h$]h&]uh1jshj? hK-hj ubjt)}(hH``endpoint`` connection to the CXL port topology for this memory device h](jz)}(h ``endpoint``h]j)}(hjc h]hendpoint}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK.hj] ubj)}(hhh]j])}(h:connection to the CXL port topology for this memory deviceh]h:connection to the CXL port topology for this memory device}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjx hK.hjy ubah}(h]h ]h"]h$]h&]uh1jhj] ubeh}(h]h ]h"]h$]h&]uh1jshjx hK.hj ubjt)}(h*``id`` id number of this memdev instance. h](jz)}(h``id``h]j)}(hj h]hid}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK/hj ubj)}(hhh]j])}(h"id number of this memdev instance.h]h"id number of this memdev instance.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hK/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK/hj ubjt)}(h``depth`` endpoint port depthh](jz)}(h ``depth``h]j)}(hj h]hdepth}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK/hj ubj)}(hhh]j])}(hendpoint port depthh]hendpoint port depth}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK0hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hK/hj ubeh}(h]h ]h"]h$]h&]uh1jnhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_event_state (C struct)c.cxl_event_statehNtauh1jhjNhhhNhNubj")}(hhh](j')}(hcxl_event_stateh]j-)}(hstruct cxl_event_stateh](j)}(hjh]hstruct}(hj/ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ hhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhK6ubjE)}(h h]h }(hj= hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj+ hhhj< hK6ubjV)}(hcxl_event_stateh]j\)}(hj) h]hcxl_event_state}(hjO hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjK ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj+ hhhj< hK6ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj' hhhj< hK6ubah}(h]j" ah ](jjeh"]h$]h&]jj)jhuh1j&hj< hK6hj$ hhubj)}(hhh]j])}(hEvent log driver stateh]hEvent log driver state}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjn hhubah}(h]h ]h"]h$]h&]uh1jhj$ hhhj< hK6ubeh}(h]h ](jstructeh"]h$]h&]jjjj jj jjjuh1j!hhhjNhNhNubj)}(h**Definition**:: struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; }; **Members** ``buf`` Buffer to receive event data ``log_lock`` Serialize event_buf and log useh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhj ubj)}(h]struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; };h]h]struct cxl_event_state { struct cxl_get_event_payload *buf; struct mutex log_lock; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhj ubj])}(h **Members**h]j)}(hj h]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhj ubjo)}(hhh](jt)}(h%``buf`` Buffer to receive event data h](jz)}(h``buf``h]j)}(hj h]hbuf}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhj ubj)}(hhh]j])}(hBuffer to receive event datah]hBuffer to receive event data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hKhj ubjt)}(h,``log_lock`` Serialize event_buf and log useh](jz)}(h ``log_lock``h]j)}(hjh]hlog_lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(hSerialize event_buf and log useh]hSerialize event_buf and log use}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj,hKhj ubeh}(h]h ]h"]h$]h&]uh1jnhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_poison_state (C struct)c.cxl_poison_statehNtauh1jhjNhhhNhNubj")}(hhh](j')}(hcxl_poison_stateh]j-)}(hstruct cxl_poison_stateh](j)}(hjh]hstruct}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjmhhhj~hKubjV)}(hcxl_poison_stateh]j\)}(hjkh]hcxl_poison_state}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjmhhhj~hKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjihhhj~hKubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j&hj~hKhjfhhubj)}(hhh]j])}(hDriver poison state infoh]hDriver poison state info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjfhhhj~hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j!hhhjNhNhNubj)}(hX**Definition**:: struct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; }; **Members** ``max_errors`` Maximum media error records held in device cache ``enabled_cmds`` All poison commands enabled in the CEL ``list_out`` The poison list payload returned by device ``lock`` Protect reads of the poison listh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hstruct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; };h]hstruct cxl_poison_state { u32 max_errors; unsigned long enabled_cmds[BITS_TO_LONGS(CXL_POISON_ENABLED_MAX)]; struct cxl_mbox_poison_out *list_out; struct mutex lock; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubjo)}(hhh](jt)}(h@``max_errors`` Maximum media error records held in device cache h](jz)}(h``max_errors``h]j)}(hj h]h max_errors}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(h0Maximum media error records held in device cacheh]h0Maximum media error records held in device cache}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj5hKhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj5hKhjubjt)}(h8``enabled_cmds`` All poison commands enabled in the CEL h](jz)}(h``enabled_cmds``h]j)}(hjYh]h enabled_cmds}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjSubj)}(hhh]j])}(h&All poison commands enabled in the CELh]h&All poison commands enabled in the CEL}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjnhKhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jshjnhKhjubjt)}(h8``list_out`` The poison list payload returned by device h](jz)}(h ``list_out``h]j)}(hjh]hlist_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(h*The poison list payload returned by deviceh]h*The poison list payload returned by device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h)``lock`` Protect reads of the poison listh](jz)}(h``lock``h]j)}(hjh]hlock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubj)}(hhh]j])}(h Protect reads of the poison listh]h Protect reads of the poison list}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhKhjNhhubj])}(hReads of the poison list are synchronized to ensure that a reader does not get an incomplete list because their request overlapped (was interrupted or preceded by) another read request of the same DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1h]hReads of the poison list are synchronized to ensure that a reader does not get an incomplete list because their request overlapped (was interrupted or preceded by) another read request of the same DPA range. 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]jQah"]h$]h&]uh1jDhjhhhj hMubjV)}(hcxl_dpa_partitionh]j\)}(hj h]hcxl_dpa_partition}(hj3hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj/ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhj hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj hhhj hMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hj hMhjhhubj)}(hhh]j])}(hDPA partition descriptorh]hDPA partition descriptor}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjRhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj hMubeh}(h]h ](jstructeh"]h$]h&]jjjjmjjmjjjuh1j!hhhjNhNhNubj)}(hXx**Definition**:: struct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; }; **Members** ``res`` shortcut to the partition in the DPA resource tree (cxlds->dpa_res) ``perf`` performance attributes of the partition from CDAT ``mode`` operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubh:}(hjuhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjqubj)}(hvstruct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; };h]hvstruct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjqubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjqubjo)}(hhh](jt)}(hL``res`` shortcut to the partition in the DPA resource tree (cxlds->dpa_res) h](jz)}(h``res``h]j)}(hjh]hres}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)h]hCshortcut to the partition in the DPA resource tree (cxlds->dpa_res)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h;``perf`` performance attributes of the partition from CDAT h](jz)}(h``perf``h]j)}(hjh]hperf}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h1performance attributes of the partition from CDATh]h1performance attributes of the partition from CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(hH``mode`` operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h](jz)}(h``mode``h]j)}(hj4h]hmode}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj.ubj)}(hhh]j])}(h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...h]h?operation mode for the DPA capacity, e.g. ram, pmem, dynamic...}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jshjIhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_dev_state (C struct)c.cxl_dev_statehNtauh1jhjNhhhNhNubj")}(hhh](j')}(h cxl_dev_stateh]j-)}(hstruct cxl_dev_stateh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(h cxl_dev_stateh]j\)}(hjh]h cxl_dev_state}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(hThe driver device stateh]hThe driver device state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j!hhhjNhNhNubj)}(hX**Definition**:: struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; }; **Members** ``dev`` The device associated with this CXL state ``cxlmd`` The device representing the CXL.mem capabilities of **dev** ``reg_map`` component and ras register mapping parameters ``regs`` Parsed register blocks ``cxl_dvsec`` Offset to the PCIe device DVSEC ``rcd`` operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) ``media_ready`` Indicate whether the device media is usable ``dpa_res`` Overall DPA resource tree for the device ``part`` DPA partition array ``nr_partitions`` Number of DPA partitions ``serial`` PCIe Device Serial Number ``type`` Generic Memory Class device or Vendor Specific Memory device ``cxl_mbox`` CXL mailbox context ``cxlfs`` CXL features contexth](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hXstruct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; };h]hXstruct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; bool media_ready; struct resource dpa_res; struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; unsigned int nr_partitions; u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; #ifdef CONFIG_CXL_FEATURES; struct cxl_features_state *cxlfs; #endif; };}hj sbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj])}(h **Members**h]j)}(hjh]hMembers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubjo)}(hhh](jt)}(h2``dev`` The device associated with this CXL state h](jz)}(h``dev``h]j)}(hj=h]hdev}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj7ubj)}(hhh]j])}(h)The device associated with this CXL stateh]h)The device associated with this CXL state}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjRhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jshjRhMhj4ubjt)}(hF``cxlmd`` The device representing the CXL.mem capabilities of **dev** h](jz)}(h ``cxlmd``h]j)}(hjvh]hcxlmd}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjpubj)}(hhh]j])}(h;The device representing the CXL.mem capabilities of **dev**h](h4The device representing the CXL.mem capabilities of }(hjhhhNhNubj)}(h**dev**h]hdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h 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the PCIe device DVSEC h](jz)}(h ``cxl_dvsec``h]j)}(hj/h]h cxl_dvsec}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj)ubj)}(hhh]j])}(hOffset to the PCIe device DVSECh]hOffset to the PCIe device DVSEC}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjDhMhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jshjDhMhj4ubjt)}(hN``rcd`` operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) h](jz)}(h``rcd``h]j)}(hjhh]hrcd}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjbubj)}(hhh]j])}(hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)h]hEoperating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj}hMhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jshj}hMhj4ubjt)}(h<``media_ready`` Indicate whether the device media is usable h](jz)}(h``media_ready``h]j)}(hjh]h media_ready}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h+Indicate whether the device media is usableh]h+Indicate whether the device media is usable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhj4ubjt)}(h5``dpa_res`` Overall DPA resource tree for the device h](jz)}(h ``dpa_res``h]j)}(hjh]hdpa_res}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h(Overall DPA resource tree for the deviceh]h(Overall DPA resource tree for the device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhj4ubjt)}(h``part`` DPA partition array h](jz)}(h``part``h]j)}(hjh]hpart}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj ubj)}(hhh]j])}(hDPA partition arrayh]hDPA partition array}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj(hMhj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj(hMhj4ubjt)}(h+``nr_partitions`` Number of DPA partitions h](jz)}(h``nr_partitions``h]j)}(hjLh]h nr_partitions}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjFubj)}(hhh]j])}(hNumber of DPA partitionsh]hNumber of DPA partitions}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjahMhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jshjahMhj4ubjt)}(h%``serial`` PCIe Device Serial Number h](jz)}(h ``serial``h]j)}(hjh]hserial}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h 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h]hfw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjubj)}(hhh]j])}(h"firmware upload / activation stateh]h"firmware upload / activation state}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj"hMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj"hMhjWubjt)}(h``mce_notifier`` MCE notifierh](jz)}(h``mce_notifier``h]j)}(hjFh]h mce_notifier}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj@ubj)}(hhh]j])}(h MCE notifierh]h MCE notifier}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jshj[hMhjWubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjNhhubj])}(hXACXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines common memory device functionality like the presence of a mailbox and the functionality related to that like Identify Memory Device and Get Partition Info See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for details on capacity parameters.h]hXACXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines common memory device functionality like the presence of a mailbox and the functionality related to that like Identify Memory Device and Get Partition Info See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for details on capacity parameters.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_mem_command (C struct)c.cxl_mem_commandhNtauh1jhjNhhhNhNubj")}(hhh](j')}(hcxl_mem_commandh]j-)}(hstruct cxl_mem_commandh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(hcxl_mem_commandh]j\)}(hjh]hcxl_mem_command}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(h0Driver representation of a memory device commandh]h0Driver representation of a memory device command}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jstructeh"]h$]h&]jjjj! jj! jjjuh1j!hhhjNhNhNubj)}(hX**Definition**:: struct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); }; **Members** ``info`` Command information as it exists for the UAPI ``opcode`` The actual bits used for the mailbox protocol ``flags`` Set of flags effecting driver behavior. * ``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj- hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj) ubh:}(hj) hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj% ubj)}(hstruct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); };h]hstruct cxl_mem_command { struct cxl_command_info info; enum cxl_opcode opcode; u32 flags; #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0); };}hjF sbah}(h[]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhM hj% ubj])}(h **Members**h]j)}(hjW h]hMembers}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj% ubjo)}(hhh](jt)}(h7``info`` Command information as it exists for the UAPI h](jz)}(h``info``h]j)}(hjv h]hinfo}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjp ubj)}(hhh]j])}(h-Command information as it exists for the UAPIh]h-Command information as it exists for the UAPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjp ubeh}(h]h ]h"]h$]h&]uh1jshj hMhjm ubjt)}(h9``opcode`` The actual bits used for the mailbox protocol h](jz)}(h ``opcode``h]j)}(hj h]hopcode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj ubj)}(hhh]j])}(h-The actual bits used for the mailbox protocolh]h-The actual bits used for the mailbox protocol}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hMhjm ubjt)}(h``flags`` Set of flags effecting driver behavior. * ``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.h](jz)}(h ``flags``h]j)}(hj h]hflags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhM hj ubj)}(hhh](j])}(h'Set of flags effecting driver behavior.h]h'Set of flags effecting driver behavior.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhj ubj)}(hhh]j)}(h``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.h]j])}(h``CXL_CMD_FLAG_FORCE_ENABLE``: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.h](j)}(h``CXL_CMD_FLAG_FORCE_ENABLE``h]hCXL_CMD_FLAG_FORCE_ENABLE}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubh{: In cases of error, commands with this flag will be enabled by the driver regardless of what hardware may have advertised.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhM hj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]jjuh1jhj3!hM hj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jshj hM hjm ubeh}(h]h ]h"]h$]h&]uh1jnhj% ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj])}(h**Description**h]j)}(hj[!h]h Description}(hj]!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY!ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjNhhubj])}(hXThe cxl_mem_command is the driver's internal representation of commands that are supported by the driver. Some of these commands may not be supported by the hardware. The driver will use **info** to validate the fields passed in by the user then submit the **opcode** to the hardware.h](hThe cxl_mem_command is the driver’s internal representation of commands that are supported by the driver. Some of these commands may not be supported by the hardware. The driver will use }(hjq!hhhNhNubj)}(h**info**h]hinfo}(hjy!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq!ubh> to validate the fields passed in by the user then submit the }(hjq!hhhNhNubj)}(h **opcode**h]hopcode}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq!ubh to the hardware.}(hjq!hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhM hjNhhubj])}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMhjNhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_hdm (C struct) c.cxl_hdmhNtauh1jhjNhhhNhNubj")}(hhh](j')}(hcxl_hdmh]j-)}(hstruct cxl_hdmh](j)}(hjh]hstruct}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!hhhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMubjE)}(h h]h }(hj!hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj!hhhj!hMubjV)}(hcxl_hdmh]j\)}(hj!h]hcxl_hdm}(hj!hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj!ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj!hhhj!hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj!hhhj!hMubah}(h]j!ah ](jjeh"]h$]h&]jj)jhuh1j&hj!hMhj!hhubj)}(hhh]j])}(h7HDM Decoder registers and cached / decoded capabilitiesh]h7HDM Decoder registers and cached / decoded capabilities}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMghj "hhubah}(h]h ]h"]h$]h&]uh1jhj!hhhj!hMubeh}(h]h ](jstructeh"]h$]h&]jjjj&"jj&"jjjuh1j!hhhjNhNhNubj)}(hX**Definition**:: struct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; }; **Members** ``regs`` mapped registers, see devm_cxl_setup_hdm() ``decoder_count`` number of decoders for this port ``target_count`` for switch decoders, max downstream port targets ``interleave_mask`` interleave granularity capability, see check_interleave_cap() ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() ``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj2"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj."ubh:}(hj."hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMkhj*"ubj)}(hstruct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };h]hstruct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; unsigned long iw_cap_mask; struct cxl_port *port; };}hjK"sbah}(h]h ]h"]h$]h&]hhuh1jhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMmhj*"ubj])}(h **Members**h]j)}(hj\"h]hMembers}(hj^"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ"ubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMvhj*"ubjo)}(hhh](jt)}(h4``regs`` mapped registers, see devm_cxl_setup_hdm() h](jz)}(h``regs``h]j)}(hj{"h]hregs}(hj}"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy"ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMihju"ubj)}(hhh]j])}(h*mapped registers, see devm_cxl_setup_hdm()h]h*mapped registers, see devm_cxl_setup_hdm()}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj"hMihj"ubah}(h]h ]h"]h$]h&]uh1jhju"ubeh}(h]h ]h"]h$]h&]uh1jshj"hMihjr"ubjt)}(h3``decoder_count`` number of decoders for this port h](jz)}(h``decoder_count``h]j)}(hj"h]h decoder_count}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMjhj"ubj)}(hhh]j])}(h number of decoders for this porth]h number of decoders for this port}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj"hMjhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jshj"hMjhjr"ubjt)}(hB``target_count`` for switch decoders, max downstream port targets h](jz)}(h``target_count``h]j)}(hj"h]h target_count}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMkhj"ubj)}(hhh]j])}(h0for switch decoders, max downstream port targetsh]h0for switch decoders, max downstream port targets}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#hMkhj#ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jshj#hMkhjr"ubjt)}(hR``interleave_mask`` interleave granularity capability, see check_interleave_cap() h](jz)}(h``interleave_mask``h]j)}(hj&#h]hinterleave_mask}(hj(#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$#ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMlhj #ubj)}(hhh]j])}(h=interleave granularity capability, see check_interleave_cap()h]h=interleave granularity capability, see check_interleave_cap()}(hj?#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;#hMlhj<#ubah}(h]h ]h"]h$]h&]uh1jhj #ubeh}(h]h ]h"]h$]h&]uh1jshj;#hMlhjr"ubjt)}(hQ``iw_cap_mask`` bitmask of supported interleave ways, see check_interleave_cap() h](jz)}(h``iw_cap_mask``h]j)}(hj_#h]h iw_cap_mask}(hja#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]#ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMmhjY#ubj)}(hhh]j])}(h@bitmask of supported interleave ways, see check_interleave_cap()h]h@bitmask of supported interleave ways, see check_interleave_cap()}(hjx#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjt#hMmhju#ubah}(h]h ]h"]h$]h&]uh1jhjY#ubeh}(h]h ]h"]h$]h&]uh1jshjt#hMmhjr"ubjt)}(h2``port`` mapped cxl_port, see devm_cxl_setup_hdm()h](jz)}(h``port``h]j)}(hj#h]hport}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jyhc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMmhj#ubj)}(hhh]j])}(h)mapped cxl_port, see devm_cxl_setup_hdm()h]h)mapped cxl_port, see devm_cxl_setup_hdm()}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hc/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:417: ./drivers/cxl/cxlmem.hhMnhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jshj#hMmhjr"ubeh}(h]h ]h"]h$]h&]uh1jnhj*"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j'set_exclusive_cxl_commands (C function)c.set_exclusive_cxl_commandshNtauh1jhjNhhhNhNubj")}(hhh](j')}(hSvoid set_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j-)}(hRvoid set_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j3)}(hvoidh]hvoid}(hj#hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj#hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMDubjE)}(h h]h }(hj$hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj#hhhj$hMDubjV)}(hset_exclusive_cxl_commandsh]j\)}(hset_exclusive_cxl_commandsh]hset_exclusive_cxl_commands}(hj$hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj$ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj#hhhj$hMDubju)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j{)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj/$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+$ubjE)}(h h]h }(hj<$hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj+$ubh)}(hhh]j\)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjM$hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjJ$ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjO$modnameN classnameNjj)}j]j)}jj$sbc.set_exclusive_cxl_commandsasbuh1hhj+$ubjE)}(h h]h }(hjm$hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj+$ubj)}(hjh]h*}(hj{$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+$ubj\)}(hmdsh]hmds}(hj$hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj+$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj'$ubj{)}(hunsigned long *cmdsh](j3)}(hunsignedh]hunsigned}(hj$hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj$ubjE)}(h h]h }(hj$hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj$ubj3)}(hlongh]hlong}(hj$hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj$ubjE)}(h h]h }(hj$hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj$ubj)}(hjh]h*}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubj\)}(hcmdsh]hcmds}(hj$hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj'$ubeh}(h]h ]h"]h$]h&]hhuh1jthj#hhhj$hMDubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj#hhhj$hMDubah}(h]j#ah ](jjeh"]h$]h&]jj)jhuh1j&hj$hMDhj#hhubj)}(hhh]j])}(h$atomically disable user cxl commandsh]h$atomically disable user cxl commands}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM<hj %hhubah}(h]h ]h"]h$]h&]uh1jhj#hhhj$hMDubeh}(h]h ](jfunctioneh"]h$]h&]jjjj(%jj(%jjjuh1j!hhhjNhNhNubj)}(hXP**Parameters** ``struct cxl_memdev_state *mds`` The device state to operate on ``unsigned long *cmds`` bitmap of commands to mark exclusive **Description** Grab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](j])}(h**Parameters**h]j)}(hj2%h]h Parameters}(hj4%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0%ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM@hj,%ubjo)}(hhh](jt)}(h@``struct cxl_memdev_state *mds`` The device state to operate on h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hjQ%h]hstruct cxl_memdev_state *mds}(hjS%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjO%ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM=hjK%ubj)}(hhh]j])}(hThe device state to operate onh]hThe device state to operate on}(hjj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjf%hM=hjg%ubah}(h]h ]h"]h$]h&]uh1jhjK%ubeh}(h]h ]h"]h$]h&]uh1jshjf%hM=hjH%ubjt)}(h=``unsigned long *cmds`` bitmap of commands to mark exclusive h](jz)}(h``unsigned long *cmds``h]j)}(hj%h]hunsigned long *cmds}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM>hj%ubj)}(hhh]j])}(h$bitmap of commands to mark exclusiveh]h$bitmap of commands to mark exclusive}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj%hM>hj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jshj%hM>hjH%ubeh}(h]h ]h"]h$]h&]uh1jnhj,%ubj])}(h**Description**h]j)}(hj%h]h Description}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM@hj,%ubj])}(hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in **cmds**.h](hGrab the cxl_memdev_rwsem in write mode to flush in-flight invocations of the ioctl path and then disable future execution of commands with the command ids set in }(hj%hhhNhNubj)}(h**cmds**h]hcmds}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM@hj,%ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)clear_exclusive_cxl_commands (C function)c.clear_exclusive_cxl_commandshNtauh1jhjNhhhNhNubj")}(hhh](j')}(hUvoid clear_exclusive_cxl_commands (struct cxl_memdev_state *mds, unsigned long *cmds)h]j-)}(hTvoid clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, unsigned long *cmds)h](j3)}(hvoidh]hvoid}(hj&hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj&hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMTubjE)}(h h]h }(hj+&hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj&hhhj*&hMTubjV)}(hclear_exclusive_cxl_commandsh]j\)}(hclear_exclusive_cxl_commandsh]hclear_exclusive_cxl_commands}(hj=&hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj9&ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj&hhhj*&hMTubju)}(h3(struct cxl_memdev_state *mds, unsigned long *cmds)h](j{)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjY&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU&ubjE)}(h h]h }(hjf&hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjU&ubh)}(hhh]j\)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjw&hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjt&ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjy&modnameN classnameNjj)}j]j)}jj?&sbc.clear_exclusive_cxl_commandsasbuh1hhjU&ubjE)}(h h]h }(hj&hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjU&ubj)}(hjh]h*}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjU&ubj\)}(hmdsh]hmds}(hj&hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjU&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjQ&ubj{)}(hunsigned long *cmdsh](j3)}(hunsignedh]hunsigned}(hj&hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj&ubjE)}(h h]h }(hj&hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj&ubj3)}(hlongh]hlong}(hj&hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj&ubjE)}(h h]h }(hj&hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj&ubj)}(hjh]h*}(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj\)}(hcmdsh]hcmds}(hj'hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjQ&ubeh}(h]h ]h"]h$]h&]hhuh1jthj&hhhj*&hMTubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj&hhhj*&hMTubah}(h]j&ah ](jjeh"]h$]h&]jj)jhuh1j&hj*&hMThj&hhubj)}(hhh]j])}(h#atomically enable user cxl commandsh]h#atomically enable user cxl commands}(hj:'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMPhj7'hhubah}(h]h ]h"]h$]h&]uh1jhj&hhhj*&hMTubeh}(h]h ](jfunctioneh"]h$]h&]jjjjR'jjR'jjjuh1j!hhhjNhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device state to modify ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](j])}(h**Parameters**h]j)}(hj\'h]h Parameters}(hj^'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ'ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMThjV'ubjo)}(hhh](jt)}(h<``struct cxl_memdev_state *mds`` The device state to modify h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj{'h]hstruct cxl_memdev_state *mds}(hj}'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy'ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMQhju'ubj)}(hhh]j])}(hThe device state to modifyh]hThe device state to modify}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj'hMQhj'ubah}(h]h ]h"]h$]h&]uh1jhju'ubeh}(h]h ]h"]h$]h&]uh1jshj'hMQhjr'ubjt)}(hJ``unsigned long *cmds`` bitmap of commands to mark available for userspaceh](jz)}(h``unsigned long *cmds``h]j)}(hj'h]hunsigned long *cmds}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMShj'ubj)}(hhh]j])}(h2bitmap of commands to mark available for userspaceh]h2bitmap of commands to mark available for userspace}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMRhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jshj'hMShjr'ubeh}(h]h ]h"]h$]h&]uh1jnhjV'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_mem_get_fw_info (C function)c.cxl_mem_get_fw_infohNtauh1jhjNhhhNhNubj")}(hhh](j')}(h6int cxl_mem_get_fw_info (struct cxl_memdev_state *mds)h]j-)}(h5int cxl_mem_get_fw_info(struct cxl_memdev_state *mds)h](j3)}(hinth]hint}(hj(hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj (hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMubjE)}(h h]h }(hj(hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj (hhhj(hMubjV)}(hcxl_mem_get_fw_infoh]j\)}(hcxl_mem_get_fw_infoh]hcxl_mem_get_fw_info}(hj/(hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj+(ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj (hhhj(hMubju)}(h(struct cxl_memdev_state *mds)h]j{)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hjK(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG(ubjE)}(h h]h }(hjX(hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjG(ubh)}(hhh]j\)}(hcxl_memdev_stateh]hcxl_memdev_state}(hji(hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjf(ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjk(modnameN classnameNjj)}j]j)}jj1(sbc.cxl_mem_get_fw_infoasbuh1hhjG(ubjE)}(h h]h }(hj(hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjG(ubj)}(hjh]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjG(ubj\)}(hmdsh]hmds}(hj(hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjG(ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjC(ubah}(h]h ]h"]h$]h&]hhuh1jthj (hhhj(hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj(hhhj(hMubah}(h]j(ah ](jjeh"]h$]h&]jj)jhuh1j&hj(hMhj(hhubj)}(hhh]j])}(hGet Firmware infoh]hGet Firmware info}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(hhubah}(h]h ]h"]h$]h&]uh1jhj(hhhj(hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj(jj(jjjuh1j!hhhjNhNhNubj)}(h**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Retrieve firmware info for the device specified. See CXL-3.0 8.2.9.3.1 Get FW Info **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hj(h]h Parameters}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubjo)}(hhh]jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj)h]hstruct cxl_memdev_state *mds}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj )ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj )ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj()hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj$)hMhj%)ubah}(h]h ]h"]h$]h&]uh1jhj )ubeh}(h]h ]h"]h$]h&]uh1jshj$)hMhj)ubah}(h]h ]h"]h$]h&]uh1jnhj(ubj])}(h**Description**h]j)}(hjJ)h]h Description}(hjL)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjH)ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubj])}(h0Retrieve firmware info for the device specified.h]h0Retrieve firmware info for the device specified.}(hj`)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubj])}(h!See CXL-3.0 8.2.9.3.1 Get FW Infoh]h!See CXL-3.0 8.2.9.3.1 Get FW Info}(hjo)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubj])}(h **Return**h]j)}(hj)h]hReturn}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~)ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_mem_activate_fw (C function)c.cxl_mem_activate_fwhNtauh1jhjNhhhNhNubj")}(hhh](j')}(h@int cxl_mem_activate_fw (struct cxl_memdev_state *mds, int slot)h]j-)}(h?int cxl_mem_activate_fw(struct cxl_memdev_state *mds, int slot)h](j3)}(hinth]hint}(hj)hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj)hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMubjE)}(h h]h }(hj)hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj)hhhj)hMubjV)}(hcxl_mem_activate_fwh]j\)}(hcxl_mem_activate_fwh]hcxl_mem_activate_fw}(hj)hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj)ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj)hhhj)hMubju)}(h((struct cxl_memdev_state *mds, int slot)h](j{)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubjE)}(h h]h }(hj*hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj)ubh)}(hhh]j\)}(hcxl_memdev_stateh]hcxl_memdev_state}(hj *hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj*ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj"*modnameN classnameNjj)}j]j)}jj)sbc.cxl_mem_activate_fwasbuh1hhj)ubjE)}(h h]h }(hj@*hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj)ubj)}(hjh]h*}(hjN*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj\)}(hmdsh]hmds}(hj[*hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj)ubj{)}(hint sloth](j3)}(hinth]hint}(hjt*hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjp*ubjE)}(h h]h }(hj*hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjp*ubj\)}(hsloth]hslot}(hj*hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjp*ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj)ubeh}(h]h ]h"]h$]h&]hhuh1jthj)hhhj)hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj)hhhj)hMubah}(h]j)ah ](jjeh"]h$]h&]jj)jhuh1j&hj)hMhj)hhubj)}(hhh]j])}(hActivate Firmwareh]hActivate Firmware}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*hhubah}(h]h ]h"]h$]h&]uh1jhj)hhhj)hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj*jj*jjjuh1j!hhhjNhNhNubj)}(hX/**Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation ``int slot`` slot number to activate **Description** Activate firmware in a given slot for the device specified. See CXL-3.0 8.2.9.3.3 Activate FW **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hj*h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubjo)}(hhh](jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj*h]hstruct cxl_memdev_state *mds}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj+hMhj+ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jshj+hMhj*ubjt)}(h%``int slot`` slot number to activate h](jz)}(h ``int slot``h]j)}(hj4+h]hint slot}(hj6+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2+ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj.+ubj)}(hhh]j])}(hslot number to activateh]hslot number to activate}(hjM+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjI+hMhjJ+ubah}(h]h ]h"]h$]h&]uh1jhj.+ubeh}(h]h ]h"]h$]h&]uh1jshjI+hMhj*ubeh}(h]h ]h"]h$]h&]uh1jnhj*ubj])}(h**Description**h]j)}(hjo+h]h Description}(hjq+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm+ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubj])}(h;Activate firmware in a given slot for the device specified.h]h;Activate firmware in a given slot for the device specified.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubj])}(h!See CXL-3.0 8.2.9.3.3 Activate FWh]h!See CXL-3.0 8.2.9.3.3 Activate FW}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubj])}(h **Return**h]j)}(hj+h]hReturn}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj*ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"cxl_mem_abort_fw_xfer (C function)c.cxl_mem_abort_fw_xferhNtauh1jhjNhhhNhNubj")}(hhh](j')}(h8int cxl_mem_abort_fw_xfer (struct cxl_memdev_state *mds)h]j-)}(h7int cxl_mem_abort_fw_xfer(struct cxl_memdev_state *mds)h](j3)}(hinth]hint}(hj+hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj+hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chM!ubjE)}(h h]h }(hj+hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj+hhhj+hM!ubjV)}(hcxl_mem_abort_fw_xferh]j\)}(hcxl_mem_abort_fw_xferh]hcxl_mem_abort_fw_xfer}(hj ,hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj,ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj+hhhj+hM!ubju)}(h(struct cxl_memdev_state *mds)h]j{)}(hstruct cxl_memdev_state *mdsh](j)}(hjh]hstruct}(hj',hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#,ubjE)}(h h]h }(hj4,hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj#,ubh)}(hhh]j\)}(hcxl_memdev_stateh]hcxl_memdev_state}(hjE,hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjB,ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjG,modnameN classnameNjj)}j]j)}jj ,sbc.cxl_mem_abort_fw_xferasbuh1hhj#,ubjE)}(h h]h }(hje,hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj#,ubj)}(hjh]h*}(hjs,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#,ubj\)}(hmdsh]hmds}(hj,hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj#,ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj,ubah}(h]h ]h"]h$]h&]hhuh1jthj+hhhj+hM!ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj+hhhj+hM!ubah}(h]j+ah ](jjeh"]h$]h&]jj)jhuh1j&hj+hM!hj+hhubj)}(hhh]j])}(h Abort an in-progress FW transferh]h Abort an in-progress FW transfer}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,hhubah}(h]h ]h"]h$]h&]uh1jhj+hhhj+hM!ubeh}(h]h ](jfunctioneh"]h$]h&]jjjj,jj,jjjuh1j!hhhjNhNhNubj)}(hX **Parameters** ``struct cxl_memdev_state *mds`` The device data for the operation **Description** Abort an in-progress firmware transfer for the device specified. See CXL-3.0 8.2.9.3.2 Transfer FW **Return** 0 if no error: or the result of the mailbox command.h](j])}(h**Parameters**h]j)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubjo)}(hhh]jt)}(hC``struct cxl_memdev_state *mds`` The device data for the operation h](jz)}(h ``struct cxl_memdev_state *mds``h]j)}(hj,h]hstruct cxl_memdev_state *mds}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubj)}(hhh]j])}(h!The device data for the operationh]h!The device data for the operation}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj-hMhj-ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jshj-hMhj,ubah}(h]h ]h"]h$]h&]uh1jnhj,ubj])}(h**Description**h]j)}(hj&-h]h Description}(hj(-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$-ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubj])}(h@Abort an in-progress firmware transfer for the device specified.h]h@Abort an in-progress firmware transfer for the device specified.}(hj<-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubj])}(h!See CXL-3.0 8.2.9.3.2 Transfer FWh]h!See CXL-3.0 8.2.9.3.2 Transfer FW}(hjK-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubj])}(h **Return**h]j)}(hj\-h]hReturn}(hj^-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ-ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubj])}(h40 if no error: or the result of the mailbox command.h]h40 if no error: or the result of the mailbox command.}(hjr-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:420: ./drivers/cxl/core/memdev.chMhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjNhhhNhNubeh}(h]cxl-memory-deviceah ]h"]cxl memory deviceah$]h&]uh1jGhj/hhhhhM@ubjH)}(hhh](jM)}(hCXL Porth]hCXL Port}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj-hhhhhMRubj])}(hXThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the **component_reg_phys** value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.h](hrThe port driver enumerates dport via PCI and scans for HDM (Host-managed-Device-Memory) decoder resources via the }(hj-hhhNhNubj)}(h**component_reg_phys**h]hcomponent_reg_phys}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubhXK value passed in by the agent that registered the port. All descendant ports of a CXL root port (described by platform firmware) are managed in this drivers context. Each driver instance is responsible for tearing down the driver context of immediate descendant ports. The locking for this is validated by CONFIG_PROVE_CXL_LOCKING.}(hj-hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\ha/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:425: ./drivers/cxl/port.chK hj-hhubj])}(hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.h]hThe primary service this driver provides is presenting APIs to other drivers to utilize the decoders, and indicating to userspace (via bind status) the connectivity of the CXL.mem protocol throughout the PCIe topology.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\ha/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:425: ./drivers/cxl/port.chKhj-hhubeh}(h]cxl-portah ]h"]cxl portah$]h&]uh1jGhj/hhhhhMRubjH)}(hhh](jM)}(hCXL Coreh]hCXL Core}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj-hhhhhMWubj])}(hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).h]hThe CXL core objects like ports, decoders, and regions are shared between the subsystem drivers cxl_acpi, cxl_pci, and core drivers (port-driver, region-driver, nvdimm object-drivers... etc).}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:430: ./drivers/cxl/cxl.hhKhj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_register_map (C struct)c.cxl_register_maphNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_register_maph]j-)}(hstruct cxl_register_maph](j)}(hjh]hstruct}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhKubjE)}(h h]h }(hj .hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj.hhhj.hKubjV)}(hcxl_register_maph]j\)}(hj .h]hcxl_register_map}(hj2.hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj..ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj.hhhj.hKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj .hhhj.hKubah}(h]j.ah ](jjeh"]h$]h&]jj)jhuh1j&hj.hKhj.hhubj)}(hhh]j])}(h1DVSEC harvested register block mapping parametersh]h1DVSEC harvested register block mapping parameters}(hjT.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjQ.hhubah}(h]h ]h"]h$]h&]uh1jhj.hhhj.hKubeh}(h]h ](jstructeh"]h$]h&]jjjjl.jjl.jjjuh1j!hhhj-hNhNubj)}(hX\**Definition**:: struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; }; **Members** ``host`` device for devm operations and logging ``base`` virtual base of the register-block-BAR + **block_offset** ``resource`` physical resource base of the register block ``max_size`` maximum mapping size to perform register search ``reg_type`` see enum cxl_regloc_type ``{unnamed_union}`` anonymous ``component_map`` cxl_reg_map for component registers ``device_map`` cxl_reg_maps for device registers ``pmu_map`` cxl_reg_maps for CXL Performance Monitoring Unitsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjx.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt.ubh:}(hjt.hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjp.ubj)}(hX7struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; };h]hX7struct cxl_register_map { struct device *host; void __iomem *base; resource_size_t resource; resource_size_t max_size; u8 reg_type; union { struct cxl_component_reg_map component_map; struct cxl_device_reg_map device_map; struct cxl_pmu_reg_map pmu_map; }; };}hj.sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjp.ubj])}(h **Members**h]j)}(hj.h]hMembers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM"hjp.ubjo)}(hhh](jt)}(h0``host`` device for devm operations and logging h](jz)}(h``host``h]j)}(hj.h]hhost}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj.ubj)}(hhh]j])}(h&device for devm operations and loggingh]h&device for devm operations and logging}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj.hMhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jshj.hMhj.ubjt)}(hC``base`` virtual base of the register-block-BAR + **block_offset** h](jz)}(h``base``h]j)}(hj.h]hbase}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj.ubj)}(hhh]j])}(h9virtual base of the register-block-BAR + **block_offset**h](h)virtual base of the register-block-BAR + }(hj/hhhNhNubj)}(h**block_offset**h]h block_offset}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j\hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jshj/hMhj.ubjt)}(h:``resource`` physical resource base of the register block h](jz)}(h ``resource``h]j)}(hjA/h]hresource}(hjC/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?/ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj;/ubj)}(hhh]j])}(h,physical resource base of the register blockh]h,physical resource base of the register block}(hjZ/hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjV/hMhjW/ubah}(h]h ]h"]h$]h&]uh1jhj;/ubeh}(h]h ]h"]h$]h&]uh1jshjV/hMhj.ubjt)}(h=``max_size`` maximum mapping size to perform register search h](jz)}(h ``max_size``h]j)}(hjz/h]hmax_size}(hj|/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjx/ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjt/ubj)}(hhh]j])}(h/maximum mapping size to perform register searchh]h/maximum mapping size to perform register search}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhjt/ubeh}(h]h ]h"]h$]h&]uh1jshj/hMhj.ubjt)}(h&``reg_type`` see enum cxl_regloc_type h](jz)}(h ``reg_type``h]j)}(hj/h]hreg_type}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj/ubj)}(hhh]j])}(hsee enum cxl_regloc_typeh]hsee enum cxl_regloc_type}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj/hMhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jshj/hMhj.ubjt)}(h``{unnamed_union}`` anonymous h](jz)}(h``{unnamed_union}``h]j)}(hj/h]h{unnamed_union}}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj/ubj)}(hhh]j])}(h anonymoush]h anonymous}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj0hMhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jshj0hMhj.ubjt)}(h6``component_map`` cxl_reg_map for component registers h](jz)}(h``component_map``h]j)}(hj%0h]h component_map}(hj'0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#0ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj0ubj)}(hhh]j])}(h#cxl_reg_map for component registersh]h#cxl_reg_map for component registers}(hj>0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:0hMhj;0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jshj:0hMhj.ubjt)}(h1``device_map`` cxl_reg_maps for device registers h](jz)}(h``device_map``h]j)}(hj^0h]h device_map}(hj`0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\0ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjX0ubj)}(hhh]j])}(h!cxl_reg_maps for device registersh]h!cxl_reg_maps for device registers}(hjw0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjs0hMhjt0ubah}(h]h ]h"]h$]h&]uh1jhjX0ubeh}(h]h ]h"]h$]h&]uh1jshjs0hMhj.ubjt)}(h=``pmu_map`` cxl_reg_maps for CXL Performance Monitoring Unitsh](jz)}(h ``pmu_map``h]j)}(hj0h]hpmu_map}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj0ubj)}(hhh]j])}(h1cxl_reg_maps for CXL Performance Monitoring Unitsh]h1cxl_reg_maps for CXL Performance Monitoring Units}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj0ubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jshj0hMhj.ubeh}(h]h ]h"]h$]h&]uh1jnhjp.ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder (C struct) c.cxl_decoderhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h cxl_decoderh]j-)}(hstruct cxl_decoderh](j)}(hjh]hstruct}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hj0hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj0hhhj0hMubjV)}(h cxl_decoderh]j\)}(hj0h]h cxl_decoder}(hj1hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj 1ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj0hhhj0hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj0hhhj0hMubah}(h]j0ah ](jjeh"]h$]h&]jj)jhuh1j&hj0hMhj0hhubj)}(hhh]j])}(h!Common CXL HDM Decoder Attributesh]h!Common CXL HDM Decoder Attributes}(hj31hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM^hj01hhubah}(h]h ]h"]h$]h&]uh1jhj0hhhj0hMubeh}(h]h ](jstructeh"]h$]h&]jjjjK1jjK1jjjuh1j!hhhj-hNhNubj)}(hX**Definition**:: struct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); }; **Members** ``dev`` this decoder's device ``id`` kernel device name id ``hpa_range`` Host physical address range mapped by this decoder ``interleave_ways`` number of cxl_dports in this decode ``interleave_granularity`` data stride per dport ``target_type`` accelerator vs expander (type2 vs type3) selector ``region`` currently assigned region for this decoder ``flags`` memory type capabilities and locking ``commit`` device/decoder-type specific callback to commit settings to hw ``reset`` device/decoder-type specific callback to reset hw settingsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjW1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS1ubh:}(hjS1hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMbhjO1ubj)}(hXHstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };h]hXHstruct cxl_decoder { struct device dev; int id; struct range hpa_range; int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); void (*reset)(struct cxl_decoder *cxld); };}hjp1sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMdhjO1ubj])}(h **Members**h]j)}(hj1h]hMembers}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMqhjO1ubjo)}(hhh](jt)}(h``dev`` this decoder's device h](jz)}(h``dev``h]j)}(hj1h]hdev}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM`hj1ubj)}(hhh]j])}(hthis decoder's deviceh]hthis decoder’s device}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj1hM`hj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jshj1hM`hj1ubjt)}(h``id`` kernel device name id h](jz)}(h``id``h]j)}(hj1h]hid}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMahj1ubj)}(hhh]j])}(hkernel device name idh]hkernel device name id}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj1hMahj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jshj1hMahj1ubjt)}(hA``hpa_range`` Host physical address range mapped by this decoder h](jz)}(h ``hpa_range``h]j)}(hj2h]h hpa_range}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMbhj 2ubj)}(hhh]j])}(h2Host physical address range mapped by this decoderh]h2Host physical address range mapped by this decoder}(hj+2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj'2hMbhj(2ubah}(h]h ]h"]h$]h&]uh1jhj 2ubeh}(h]h ]h"]h$]h&]uh1jshj'2hMbhj1ubjt)}(h8``interleave_ways`` number of cxl_dports in this decode h](jz)}(h``interleave_ways``h]j)}(hjK2h]hinterleave_ways}(hjM2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI2ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMchjE2ubj)}(hhh]j])}(h#number of cxl_dports in this decodeh]h#number of cxl_dports in this decode}(hjd2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`2hMchja2ubah}(h]h ]h"]h$]h&]uh1jhjE2ubeh}(h]h ]h"]h$]h&]uh1jshj`2hMchj1ubjt)}(h1``interleave_granularity`` data stride per dport h](jz)}(h``interleave_granularity``h]j)}(hj2h]hinterleave_granularity}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMdhj~2ubj)}(hhh]j])}(hdata stride per dporth]hdata stride per dport}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj2hMdhj2ubah}(h]h ]h"]h$]h&]uh1jhj~2ubeh}(h]h ]h"]h$]h&]uh1jshj2hMdhj1ubjt)}(hB``target_type`` accelerator vs expander (type2 vs type3) selector h](jz)}(h``target_type``h]j)}(hj2h]h target_type}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMehj2ubj)}(hhh]j])}(h1accelerator vs expander (type2 vs type3) selectorh]h1accelerator vs expander (type2 vs type3) selector}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj2hMehj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jshj2hMehj1ubjt)}(h6``region`` currently assigned region for this decoder h](jz)}(h ``region``h]j)}(hj2h]hregion}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMfhj2ubj)}(hhh]j])}(h*currently assigned region for this decoderh]h*currently assigned region for this decoder}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj 3hMfhj 3ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jshj 3hMfhj1ubjt)}(h/``flags`` memory type capabilities and locking h](jz)}(h ``flags``h]j)}(hj/3h]hflags}(hj13hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-3ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMghj)3ubj)}(hhh]j])}(h$memory type capabilities and lockingh]h$memory type capabilities and locking}(hjH3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjD3hMghjE3ubah}(h]h ]h"]h$]h&]uh1jhj)3ubeh}(h]h ]h"]h$]h&]uh1jshjD3hMghj1ubjt)}(hJ``commit`` device/decoder-type specific callback to commit settings to hw h](jz)}(h ``commit``h]j)}(hjh3h]hcommit}(hjj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf3ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.h^hMhhjb3ubj)}(hhh]j])}(h>device/decoder-type specific callback to commit settings to hwh]h>device/decoder-type specific callback to commit settings to hw}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj}3hMhhj~3ubah}(h]h ]h"]h$]h&]uh1jhjb3ubeh}(h]h ]h"]h$]h&]uh1jshj}3hMhhj1ubjt)}(hD``reset`` device/decoder-type specific callback to reset hw settingsh](jz)}(h ``reset``h]j)}(hj3h]hreset}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhhj3ubj)}(hhh]j])}(h:device/decoder-type specific callback to reset hw settingsh]h:device/decoder-type specific callback to reset hw settings}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMihj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jshj3hMhhj1ubeh}(h]h ]h"]h$]h&]uh1jnhjO1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_endpoint_decoder (C struct)c.cxl_endpoint_decoderhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_endpoint_decoderh]j-)}(hstruct cxl_endpoint_decoderh](j)}(hjh]hstruct}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMoubjE)}(h h]h }(hj 4hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj3hhhj4hMoubjV)}(hcxl_endpoint_decoderh]j\)}(hj3h]hcxl_endpoint_decoder}(hj4hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj4ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj3hhhj4hMoubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj3hhhj4hMoubah}(h]j3ah ](jjeh"]h$]h&]jj)jhuh1j&hj4hMohj3hhubj)}(hhh]j])}(hEndpoint / SPA to DPA decoderh]hEndpoint / SPA to DPA decoder}(hj=4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:4hhubah}(h]h ]h"]h$]h&]uh1jhj3hhhj4hMoubeh}(h]h ](jstructeh"]h$]h&]jjjjU4jjU4jjjuh1j!hhhj-hNhNubj)}(hX**Definition**:: struct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; }; **Members** ``cxld`` base cxl_decoder_object ``dpa_res`` actively claimed DPA span of this decoder ``skip`` offset into **dpa_res** where **cxld.hpa_range** maps ``state`` autodiscovery state ``part`` partition index this decoder maps ``pos`` interleave position in **cxld.region**h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hja4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]4ubh:}(hj]4hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjY4ubj)}(hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };h]hstruct cxl_endpoint_decoder { struct cxl_decoder cxld; struct resource *dpa_res; resource_size_t skip; enum cxl_decoder_state state; int part; int pos; };}hjz4sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjY4ubj])}(h **Members**h]j)}(hj4h]hMembers}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjY4ubjo)}(hhh](jt)}(h!``cxld`` base cxl_decoder_object h](jz)}(h``cxld``h]j)}(hj4h]hcxld}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj4ubj)}(hhh]j])}(hbase cxl_decoder_objecth]hbase cxl_decoder_object}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jshj4hMhj4ubjt)}(h6``dpa_res`` actively claimed DPA span of this decoder h](jz)}(h ``dpa_res``h]j)}(hj4h]hdpa_res}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj4ubj)}(hhh]j])}(h)actively claimed DPA span of this decoderh]h)actively claimed DPA span of this decoder}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jshj4hMhj4ubjt)}(h?``skip`` offset into **dpa_res** where **cxld.hpa_range** maps h](jz)}(h``skip``h]j)}(hj5h]hskip}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]j])}(h5offset into **dpa_res** where **cxld.hpa_range** mapsh](h offset into }(hj55hhhNhNubj)}(h **dpa_res**h]hdpa_res}(hj=5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj55ubh where }(hj55hhhNhNubj)}(h**cxld.hpa_range**h]hcxld.hpa_range}(hjO5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj55ubh maps}(hj55hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj15hMhj25ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshj15hMhj4ubjt)}(h``state`` autodiscovery state h](jz)}(h ``state``h]j)}(hjy5h]hstate}(hj{5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw5ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjs5ubj)}(hhh]j])}(hautodiscovery stateh]hautodiscovery state}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhjs5ubeh}(h]h ]h"]h$]h&]uh1jshj5hMhj4ubjt)}(h+``part`` partition index this decoder maps h](jz)}(h``part``h]j)}(hj5h]hpart}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]j])}(h!partition index this decoder mapsh]h!partition index this decoder maps}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshj5hMhj4ubjt)}(h.``pos`` interleave position in **cxld.region**h](jz)}(h``pos``h]j)}(hj5h]hpos}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj5ubj)}(hhh]j])}(h&interleave position in **cxld.region**h](hinterleave position in }(hj6hhhNhNubj)}(h**cxld.region**h]h cxld.region}(hj 6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jshj6hMhj4ubeh}(h]h ]h"]h$]h&]uh1jnhjY4ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_switch_decoder (C struct)c.cxl_switch_decoderhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_switch_decoderh]j-)}(hstruct cxl_switch_decoderh](j)}(hjh]hstruct}(hjS6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjO6hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hja6hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjO6hhhj`6hMubjV)}(hcxl_switch_decoderh]j\)}(hjM6h]hcxl_switch_decoder}(hjs6hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjo6ubah}(h]h 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cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };h]hostruct cxl_switch_decoder { struct cxl_decoder cxld; int nr_targets; struct cxl_dport *target[]; };}hj6sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj6ubj])}(h **Members**h]j)}(hj6h]hMembers}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj6ubjo)}(hhh](jt)}(h!``cxld`` base cxl_decoder object h](jz)}(h``cxld``h]j)}(hj7h]hcxld}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj6ubj)}(hhh]j])}(hbase cxl_decoder objecth]hbase cxl_decoder object}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jshj7hMhj6ubjt)}(h0``nr_targets`` number of elements in **target** h](jz)}(h``nr_targets``h]j)}(hj;7h]h nr_targets}(hj=7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj97ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj57ubj)}(hhh]j])}(h number of elements in **target**h](hnumber of elements in }(hjT7hhhNhNubj)}(h **target**h]htarget}(hj\7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjT7ubeh}(h]h ]h"]h$]h&]uh1j\hjP7hMhjQ7ubah}(h]h ]h"]h$]h&]uh1jhj57ubeh}(h]h ]h"]h$]h&]uh1jshjP7hMhj6ubjt)}(hF``target`` active ordered target list in current decoder configurationh](jz)}(h ``target``h]j)}(hj7h]htarget}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj|7ubj)}(hhh]j])}(h;active ordered target list in current decoder configurationh]h;active ordered target list in current decoder configuration}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj7ubah}(h]h ]h"]h$]h&]uh1jhj|7ubeh}(h]h ]h"]h$]h&]uh1jshj7hMhj6ubeh}(h]h ]h"]h$]h&]uh1jnhj6ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj])}(h**Description**h]j)}(hj7h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj-hhubj])}(hXTThe 'switch' decoder type represents the decoder instances of cxl_port's that route from the root of a CXL memory decode topology to the endpoints. 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They come in two flavors, root-level decoders, statically defined by platform firmware, and mid-level decoders, where interleave-granularity, interleave-width, and the target list are mutable.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_root_decoder (C struct)c.cxl_root_decoderhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_root_decoderh]j-)}(hstruct cxl_root_decoderh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hj8hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj7hhhj8hMubjV)}(hcxl_root_decoderh]j\)}(hj7h]hcxl_root_decoder}(hj#8hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj8ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj7hhhj8hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj7hhhj8hMubah}(h]j7ah ](jjeh"]h$]h&]jj)jhuh1j&hj8hMhj7hhubj)}(hhh]j])}(h#Static platform CXL address decoderh]h#Static platform CXL address decoder}(hjE8hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjB8hhubah}(h]h ]h"]h$]h&]uh1jhj7hhhj8hMubeh}(h]h ](jstructeh"]h$]h&]jjjj]8jj]8jjjuh1j!hhhj-hNhNubj)}(hX**Definition**:: struct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; }; **Members** ``res`` host / parent resource for region allocations ``region_id`` region id for next region provisioning event ``hpa_to_spa`` translate CXL host-physical-address to Platform system-physical-address ``platform_data`` platform specific configuration data ``range_lock`` sync region autodiscovery by address range ``qos_class`` QoS performance class cookie ``cxlsd`` base cxl switch decoderh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hji8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje8ubh:}(hje8hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhja8ubj)}(hstruct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; };h]hstruct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_hpa_to_spa_fn hpa_to_spa; void *platform_data; struct mutex range_lock; int qos_class; struct cxl_switch_decoder cxlsd; };}hj8sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhja8ubj])}(h **Members**h]j)}(hj8h]hMembers}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhja8ubjo)}(hhh](jt)}(h6``res`` host / parent resource for region allocations h](jz)}(h``res``h]j)}(hj8h]hres}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj8ubj)}(hhh]j])}(h-host / parent resource for region allocationsh]h-host / parent resource for region allocations}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jshj8hMhj8ubjt)}(h;``region_id`` region id for next region provisioning event h](jz)}(h ``region_id``h]j)}(hj8h]h region_id}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj8ubj)}(hhh]j])}(h,region id for next region provisioning eventh]h,region id for next region provisioning event}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jshj9hMhj8ubjt)}(hW``hpa_to_spa`` translate CXL host-physical-address to Platform system-physical-address h](jz)}(h``hpa_to_spa``h]j)}(hj$9h]h hpa_to_spa}(hj&9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"9ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]j])}(hGtranslate CXL host-physical-address to Platform system-physical-addressh]hGtranslate CXL host-physical-address to Platform system-physical-address}(hj=9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj99hMhj:9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshj99hMhj8ubjt)}(h7``platform_data`` platform specific configuration data h](jz)}(h``platform_data``h]j)}(hj]9h]h platform_data}(hj_9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[9ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjW9ubj)}(hhh]j])}(h$platform specific configuration datah]h$platform specific configuration data}(hjv9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjr9hMhjs9ubah}(h]h ]h"]h$]h&]uh1jhjW9ubeh}(h]h ]h"]h$]h&]uh1jshjr9hMhj8ubjt)}(h:``range_lock`` sync region autodiscovery by address range h](jz)}(h``range_lock``h]j)}(hj9h]h range_lock}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]j])}(h*sync region autodiscovery by address rangeh]h*sync region autodiscovery by address range}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshj9hMhj8ubjt)}(h+``qos_class`` QoS performance class cookie h](jz)}(h ``qos_class``h]j)}(hj9h]h qos_class}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj9ubj)}(hhh]j])}(hQoS performance class cookieh]hQoS performance class cookie}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshj9hMhj8ubjt)}(h!``cxlsd`` base cxl switch decoderh](jz)}(h ``cxlsd``h]j)}(hj:h]hcxlsd}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hhh]j])}(hbase cxl switch decoderh]hbase cxl switch decoder}(hj!:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jshj:hMhj8ubeh}(h]h ]h"]h$]h&]uh1jnhja8ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_region_params (C struct)c.cxl_region_paramshNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_region_paramsh]j-)}(hstruct cxl_region_paramsh](j)}(hjh]hstruct}(hjb:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^:hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hjp:hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^:hhhjo:hMubjV)}(hcxl_region_paramsh]j\)}(hj\:h]hcxl_region_params}(hj:hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj~:ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj^:hhhjo:hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjZ:hhhjo:hMubah}(h]jU:ah ](jjeh"]h$]h&]jj)jhuh1j&hjo:hMhjW:hhubj)}(hhh]j])}(hregion settingsh]hregion settings}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:hhubah}(h]h ]h"]h$]h&]uh1jhjW:hhhjo:hMubeh}(h]h ](jstructeh"]h$]h&]jjjj:jj:jjjuh1j!hhhj-hNhNubj)}(hX-**Definition**:: struct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; }; **Members** ``state`` allow the driver to lockdown further parameter changes ``uuid`` unique id for persistent regions ``interleave_ways`` number of endpoints in the region ``interleave_granularity`` capacity each endpoint contributes to a stripe ``res`` allocated iomem capacity for this region ``targets`` active ordered targets in current decoder configuration ``nr_targets`` number of targets ``cache_size`` extended linear cache size if exists, otherwise zero.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubh:}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:ubj)}(hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };h]hXstruct cxl_region_params { enum cxl_config_state state; uuid_t uuid; int interleave_ways; int interleave_granularity; struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; resource_size_t cache_size; };}hj:sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:ubj])}(h **Members**h]j)}(hj:h]hMembers}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj:ubjo)}(hhh](jt)}(hA``state`` allow the driver to lockdown further parameter changes h](jz)}(h ``state``h]j)}(hj;h]hstate}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj ;ubj)}(hhh]j])}(h6allow the driver to lockdown further parameter changesh]h6allow the driver to lockdown further parameter changes}(hj*;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj&;hMhj';ubah}(h]h ]h"]h$]h&]uh1jhj ;ubeh}(h]h ]h"]h$]h&]uh1jshj&;hMhj;ubjt)}(h*``uuid`` unique id for persistent regions h](jz)}(h``uuid``h]j)}(hjJ;h]huuid}(hjL;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjH;ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjD;ubj)}(hhh]j])}(h unique id for persistent regionsh]h unique id for persistent regions}(hjc;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj_;hMhj`;ubah}(h]h ]h"]h$]h&]uh1jhjD;ubeh}(h]h ]h"]h$]h&]uh1jshj_;hMhj;ubjt)}(h6``interleave_ways`` number of endpoints in the region h](jz)}(h``interleave_ways``h]j)}(hj;h]hinterleave_ways}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj};ubj)}(hhh]j])}(h!number of endpoints in the regionh]h!number of endpoints in the region}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj};ubeh}(h]h ]h"]h$]h&]uh1jshj;hMhj;ubjt)}(hJ``interleave_granularity`` capacity each endpoint contributes to a stripe h](jz)}(h``interleave_granularity``h]j)}(hj;h]hinterleave_granularity}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]j])}(h.capacity each endpoint contributes to a stripeh]h.capacity each endpoint contributes to a stripe}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jshj;hMhj;ubjt)}(h1``res`` allocated iomem capacity for this region h](jz)}(h``res``h]j)}(hj;h]hres}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj;ubj)}(hhh]j])}(h(allocated iomem capacity for this regionh]h(allocated iomem capacity for this region}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj <hMhj <ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jshj <hMhj;ubjt)}(hD``targets`` active ordered targets in current decoder configuration h](jz)}(h ``targets``h]j)}(hj.<h]htargets}(hj0<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,<ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj(<ubj)}(hhh]j])}(h7active ordered targets in current decoder configurationh]h7active ordered targets in current decoder configuration}(hjG<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjC<hMhjD<ubah}(h]h ]h"]h$]h&]uh1jhj(<ubeh}(h]h ]h"]h$]h&]uh1jshjC<hMhj;ubjt)}(h!``nr_targets`` number of targets h](jz)}(h``nr_targets``h]j)}(hjg<h]h nr_targets}(hji<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje<ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhja<ubj)}(hhh]j])}(hnumber of targetsh]hnumber of targets}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj|<hMhj}<ubah}(h]h ]h"]h$]h&]uh1jhja<ubeh}(h]h ]h"]h$]h&]uh1jshj|<hMhj;ubjt)}(hD``cache_size`` extended linear cache size if exists, otherwise zero.h](jz)}(h``cache_size``h]j)}(hj<h]h cache_size}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj<ubj)}(hhh]j])}(h5extended linear cache size if exists, otherwise zero.h]h5extended linear cache size if exists, otherwise zero.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jshj<hMhj;ubeh}(h]h ]h"]h$]h&]uh1jnhj:ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj])}(h**Description**h]j)}(hj<h]h Description}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj-hhubj])}(h7State transitions are protected by the cxl_region_rwsemh]h7State transitions are protected by the cxl_region_rwsem}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_region (C struct) c.cxl_regionhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h cxl_regionh]j-)}(hstruct cxl_regionh](j)}(hjh]hstruct}(hj!=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hj/=hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj=hhhj.=hMubjV)}(h cxl_regionh]j\)}(hj=h]h cxl_region}(hjA=hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj==ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj=hhhj.=hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj=hhhj.=hMubah}(h]j=ah ](jjeh"]h$]h&]jj)jhuh1j&hj.=hMhj=hhubj)}(hhh]j])}(h CXL regionh]h CXL region}(hjc=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj`=hhubah}(h]h ]h"]h$]h&]uh1jhj=hhhj.=hMubeh}(h]h ](jstructeh"]h$]h&]jjjj{=jj{=jjjuh1j!hhhj-hNhNubj)}(hXC**Definition**:: struct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; }; **Members** ``dev`` This region's device ``id`` This region's id. Id is globally unique across all regions ``mode`` Operational mode of the mapped capacity ``type`` Endpoint decoder target type ``cxl_nvb`` nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown ``cxlr_pmem`` (for pmem regions) cached copy of the nvdimm bridge ``flags`` Region state flags ``params`` active + config params for the region ``coord`` QoS access coordinates for the region ``memory_notifier`` notifier for setting the access coordinates to node ``adist_notifier`` notifier for calculating the abstract distance of nodeh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh:}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj=ubj)}(hXstruct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; };h]hXstruct cxl_region { struct device dev; int id; enum cxl_partition_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; struct access_coordinate coord[ACCESS_COORDINATE_MAX]; struct notifier_block memory_notifier; struct notifier_block adist_notifier; };}hj=sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj=ubj])}(h **Members**h]j)}(hj=h]hMembers}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj=ubjo)}(hhh](jt)}(h``dev`` This region's device h](jz)}(h``dev``h]j)}(hj=h]hdev}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj=ubj)}(hhh]j])}(hThis region's deviceh]hThis region’s device}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jshj=hMhj=ubjt)}(hB``id`` This region's id. Id is globally unique across all regions h](jz)}(h``id``h]j)}(hj >h]hid}(hj >hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj>ubj)}(hhh]j])}(h:This region's id. Id is globally unique across all regionsh]hhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshj>hMhj=ubjt)}(h1``mode`` Operational mode of the mapped capacity h](jz)}(h``mode``h]j)}(hjB>h]hmode}(hjD>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@>ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj<>ubj)}(hhh]j])}(h'Operational mode of the mapped capacityh]h'Operational mode of the mapped capacity}(hj[>hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjW>hMhjX>ubah}(h]h ]h"]h$]h&]uh1jhj<>ubeh}(h]h ]h"]h$]h&]uh1jshjW>hMhj=ubjt)}(h&``type`` Endpoint decoder target type h](jz)}(h``type``h]j)}(hj{>h]htype}(hj}>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy>ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhju>ubj)}(hhh]j])}(hEndpoint decoder target typeh]hEndpoint decoder target type}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhju>ubeh}(h]h ]h"]h$]h&]uh1jshj>hMhj=ubjt)}(hJ``cxl_nvb`` nvdimm bridge for coordinating **cxlr_pmem** setup / shutdown h](jz)}(h ``cxl_nvb``h]j)}(hj>h]hcxl_nvb}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj>ubj)}(hhh]j])}(h=nvdimm bridge for coordinating **cxlr_pmem** setup / shutdownh](hnvdimm bridge for coordinating }(hj>hhhNhNubj)}(h **cxlr_pmem**h]h cxlr_pmem}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh setup / shutdown}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hj>hMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshj>hMhj=ubjt)}(hB``cxlr_pmem`` (for pmem regions) cached copy of the nvdimm bridge h](jz)}(h ``cxlr_pmem``h]j)}(hj>h]h cxlr_pmem}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj>ubj)}(hhh]j])}(h3(for pmem regions) cached copy of the nvdimm bridgeh]h3(for pmem regions) cached copy of the nvdimm bridge}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhj=ubjt)}(h``flags`` Region state flags h](jz)}(h ``flags``h]j)}(hj8?h]hflags}(hj:?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6?ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj2?ubj)}(hhh]j])}(hRegion state flagsh]hRegion state flags}(hjQ?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjM?hMhjN?ubah}(h]h ]h"]h$]h&]uh1jhj2?ubeh}(h]h ]h"]h$]h&]uh1jshjM?hMhj=ubjt)}(h1``params`` active + config params for the region h](jz)}(h ``params``h]j)}(hjq?h]hparams}(hjs?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo?ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjk?ubj)}(hhh]j])}(h%active + config params for the regionh]h%active + config params for the region}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhjk?ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhj=ubjt)}(h0``coord`` QoS access coordinates for the region h](jz)}(h ``coord``h]j)}(hj?h]hcoord}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj?ubj)}(hhh]j])}(h%QoS access coordinates for the regionh]h%QoS access coordinates for the region}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhj=ubjt)}(hH``memory_notifier`` notifier for setting the access coordinates to node h](jz)}(h``memory_notifier``h]j)}(hj?h]hmemory_notifier}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj?ubj)}(hhh]j])}(h3notifier for setting the access coordinates to nodeh]h3notifier for setting the access coordinates to node}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshj?hMhj=ubjt)}(hI``adist_notifier`` notifier for calculating the abstract distance of nodeh](jz)}(h``adist_notifier``h]j)}(hj@h]hadist_notifier}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj@ubj)}(hhh]j])}(h6notifier for calculating the abstract distance of nodeh]h6notifier for calculating the abstract distance of node}(hj5@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj2@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jshj1@hMhj=ubeh}(h]h ]h"]h$]h&]uh1jnhj=ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_port (C struct) c.cxl_porthNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_porth]j-)}(hstruct cxl_porth](j)}(hjh]hstruct}(hjv@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjr@hhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM ubjE)}(h h]h }(hj@hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjr@hhhj@hM ubjV)}(hcxl_porth]j\)}(hjp@h]hcxl_port}(hj@hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj@ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjr@hhhj@hM ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjn@hhhj@hM ubah}(h]ji@ah ](jjeh"]h$]h&]jj)jhuh1j&hj@hM hjk@hhubj)}(hhh]j])}(hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.h]hslogical collection of upstream port devices and downstream port devices to construct a CXL memory decode hierarchy.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM>hj@hhubah}(h]h ]h"]h$]h&]uh1jhjk@hhhj@hM ubeh}(h]h ](jstructeh"]h$]h&]jjjj@jj@jjjuh1j!hhhj-hNhNubj)}(hX**Definition**:: struct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; }; **Members** ``dev`` this port's device ``uport_dev`` PCI or platform device implementing the upstream port capability ``host_bridge`` Shortcut to the platform attach point for this port ``id`` id for port device-name ``dports`` cxl_dport instances referenced by decoders ``endpoints`` cxl_ep instances, endpoints that are a descendant of this port ``regions`` cxl_region_ref instances, regions mapped by this port ``parent_dport`` dport that points to this port in the parent ``decoder_ida`` allocator for decoder ids ``reg_map`` component and ras register mapping parameters ``nr_dports`` number of entries in **dports** ``hdm_end`` track last allocated HDM decoder instance for allocation ordering ``commit_end`` cursor to track highest committed decoder for commit ordering ``dead`` last ep has been removed, force port re-creation ``depth`` How deep this port is relative to the root. depth 0 is the root. ``cdat`` Cached CDAT data ``cdat_available`` Should a CDAT attribute be available in sysfs ``pci_latency`` Upstream latency in picosecondsh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubh:}(hj@hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMBhj@ubj)}(hXstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; };h]hXstruct cxl_port { struct device dev; struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; struct xarray endpoints; struct xarray regions; struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; int nr_dports; int hdm_end; int commit_end; bool dead; unsigned int depth; struct cxl_cdat { void *table; size_t length; } cdat; bool cdat_available; long pci_latency; };}hj@sbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMDhj@ubj])}(h **Members**h]j)}(hjAh]hMembers}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhM\hj@ubjo)}(hhh](jt)}(h``dev`` this port's device h](jz)}(h``dev``h]j)}(hj%Ah]hdev}(hj'AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#Aubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMBhjAubj)}(hhh]j])}(hthis port's deviceh]hthis port’s device}(hj>AhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj:AhMBhj;Aubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshj:AhMBhjAubjt)}(hO``uport_dev`` PCI or platform device implementing the upstream port capability h](jz)}(h ``uport_dev``h]j)}(hj^Ah]h uport_dev}(hj`AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\Aubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMChjXAubj)}(hhh]j])}(h@PCI or platform device implementing the upstream port capabilityh]h@PCI or platform device implementing the upstream port capability}(hjwAhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjsAhMChjtAubah}(h]h ]h"]h$]h&]uh1jhjXAubeh}(h]h ]h"]h$]h&]uh1jshjsAhMChjAubjt)}(hD``host_bridge`` Shortcut to the platform attach point for this port h](jz)}(h``host_bridge``h]j)}(hjAh]h host_bridge}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMDhjAubj)}(hhh]j])}(h3Shortcut to the platform attach point for this porth]h3Shortcut to the platform attach point for this port}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjAhMDhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshjAhMDhjAubjt)}(h``id`` id for port device-name h](jz)}(h``id``h]j)}(hjAh]hid}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMEhjAubj)}(hhh]j])}(hid for port device-nameh]hid for port device-name}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjAhMEhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshjAhMEhjAubjt)}(h6``dports`` cxl_dport instances referenced by decoders h](jz)}(h ``dports``h]j)}(hj Bh]hdports}(hj BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMFhjBubj)}(hhh]j])}(h*cxl_dport instances referenced by decodersh]h*cxl_dport instances referenced by decoders}(hj"BhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjBhMFhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjBhMFhjAubjt)}(hM``endpoints`` cxl_ep instances, endpoints that are a descendant of this port h](jz)}(h ``endpoints``h]j)}(hjBBh]h endpoints}(hjDBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@Bubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMGhjcxl_ep instances, endpoints that are a descendant of this porth]h>cxl_ep instances, endpoints that are a descendant of this port}(hj[BhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjWBhMGhjXBubah}(h]h ]h"]h$]h&]uh1jhj``parent_dport`` dport that points to this port in the parent h](jz)}(h``parent_dport``h]j)}(hjBh]h parent_dport}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMIhjBubj)}(hhh]j])}(h,dport that points to this port in the parenth]h,dport that points to this port in the parent}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjBhMIhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjBhMIhjAubjt)}(h*``decoder_ida`` allocator for decoder ids h](jz)}(h``decoder_ida``h]j)}(hjBh]h decoder_ida}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMJhjBubj)}(hhh]j])}(hallocator for decoder idsh]hallocator for decoder ids}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjChMJhjCubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jshjChMJhjAubjt)}(h:``reg_map`` component and ras register mapping parameters h](jz)}(h ``reg_map``h]j)}(hj&Ch]hreg_map}(hj(ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$Cubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMKhj Cubj)}(hhh]j])}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hj?ChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj;ChMKhjFh]hops}(hj@FhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPCI bridge or firmware device representing the downstream linkh]h>PCI bridge or firmware device representing the downstream link}(hj`GhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj\GhMhj]Gubah}(h]h ]h"]h$]h&]uh1jhjAGubeh}(h]h ]h"]h$]h&]uh1jshj\GhMhj>Gubjt)}(h:``reg_map`` component and ras register mapping parameters h](jz)}(h ``reg_map``h]j)}(hjGh]hreg_map}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~Gubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjzGubj)}(hhh]j])}(h-component and ras register mapping parametersh]h-component and ras register mapping parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjzGubeh}(h]h ]h"]h$]h&]uh1jshjGhMhj>Gubjt)}(hH``port_id`` unique hardware identifier for dport in decoder target list h](jz)}(h ``port_id``h]j)}(hjGh]hport_id}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjGubj)}(hhh]j])}(h;unique hardware identifier for dport in decoder target listh]h;unique hardware identifier for dport in decoder target list}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjGhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jshjGhMhj>Gubjt)}(h;``rcrb`` Data about the Root Complex Register Block layout h](jz)}(h``rcrb``h]j)}(hjGh]hrcrb}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjGubj)}(hhh]j])}(h1Data about the Root Complex Register Block layouth]h1Data about the Root Complex Register Block layout}(hj HhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jshjHhMhj>Gubjt)}(hE``rch`` Indicate whether this dport was enumerated in RCH or VH mode h](jz)}(h``rch``h]j)}(hj+Hh]hrch}(hj-HhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Hubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj%Hubj)}(hhh]j])}(hGubjt)}(hB``port`` reference to cxl_port that contains this downstream port h](jz)}(h``port``h]j)}(hjdHh]hport}(hjfHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbHubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj^Hubj)}(hhh]j])}(h8reference to cxl_port that contains this downstream porth]h8reference to cxl_port that contains this downstream port}(hj}HhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjyHhMhjzHubah}(h]h ]h"]h$]h&]uh1jhj^Hubeh}(h]h ]h"]h$]h&]uh1jshjyHhMhj>Gubjt)}(h&``regs`` Dport parsed register blocks h](jz)}(h``regs``h]j)}(hjHh]hregs}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjHubj)}(hhh]j])}(hDport parsed register blocksh]hDport parsed register blocks}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jshjHhMhj>Gubjt)}(hL``coord`` access coordinates (bandwidth and latency performance attributes) h](jz)}(h ``coord``h]j)}(hjHh]hcoord}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjHubj)}(hhh]j])}(hAaccess coordinates (bandwidth and latency performance attributes)h]hAaccess coordinates (bandwidth and latency performance attributes)}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjHhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jshjHhMhj>Gubjt)}(h4``link_latency`` calculated PCIe downstream latency h](jz)}(h``link_latency``h]j)}(hjIh]h link_latency}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Iubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj Iubj)}(hhh]j])}(h"calculated PCIe downstream latencyh]h"calculated PCIe downstream latency}(hj(IhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj$IhMhj%Iubah}(h]h ]h"]h$]h&]uh1jhj Iubeh}(h]h ]h"]h$]h&]uh1jshj$IhMhj>Gubjt)}(h#``gpf_dvsec`` Cached GPF port DVSECh](jz)}(h ``gpf_dvsec``h]j)}(hjHIh]h gpf_dvsec}(hjJIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFIubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjBIubj)}(hhh]j])}(hCached GPF port DVSECh]hCached GPF port DVSEC}(hjaIhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhj^Iubah}(h]h ]h"]h$]h&]uh1jhjBIubeh}(h]h ]h"]h$]h&]uh1jshj]IhMhj>Gubeh}(h]h ]h"]h$]h&]uh1jnhjFubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_ep (C struct)c.cxl_ephNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_eph]j-)}(h struct cxl_eph](j)}(hjh]hstruct}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjIhhh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMubjE)}(h h]h }(hjIhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjIhhhjIhMubjV)}(hcxl_eph]j\)}(hjIh]hcxl_ep}(hjIhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjIubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjIhhhjIhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjIhhhjIhMubah}(h]jIah ](jjeh"]h$]h&]jj)jhuh1j&hjIhMhjIhhubj)}(hhh]j])}(h&track an endpoint's interest in a porth]h(track an endpoint’s interest in a port}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjIhhubah}(h]h ]h"]h$]h&]uh1jhjIhhhjIhMubeh}(h]h ](jstructeh"]h$]h&]jjjjIjjIjjjuh1j!hhhj-hNhNubj)}(hXx**Definition**:: struct cxl_ep { struct device *ep; struct cxl_dport *dport; struct cxl_port *next; }; **Members** ``ep`` device that hosts a generic CXL endpoint (expander or accelerator) ``dport`` which dport routes to this endpoint on **port** ``next`` cxl switch port across the link attached to **dport** NULL if attached to an endpointh](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubh:}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\h`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjJubj)}(hastruct cxl_ep { struct device *ep; struct cxl_dport *dport; struct cxl_port *next; };h]hastruct cxl_ep { struct device *ep; struct cxl_dport *dport; struct cxl_port *next; };}hj!Jsbah}(h]h ]h"]h$]h&]hhuh1jh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjJubj])}(h **Members**h]j)}(hj2Jh]hMembers}(hj4JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0Jubah}(h]h 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**port**h](h'which dport routes to this endpoint on }(hjJhhhNhNubj)}(h**port**h]hport}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1j\hjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jshjJhMhjHJubjt)}(h^``next`` cxl switch port across the link attached to **dport** NULL if attached to an endpointh](jz)}(h``next``h]j)}(hjJh]hnext}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jyh`/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:433: ./drivers/cxl/cxl.hhMhjJubj)}(hhh]j])}(hUcxl switch port across the link attached to **dport** NULL if attached to an endpointh](h,cxl switch port across the link attached to }(hjJhhhNhNubj)}(h **dport**h]hdport}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubh NULL if attached to an endpoint}(hjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jshjJhMhjHJubeh}(h]h ]h"]h$]h&]uh1jnhjJubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_region_ref (C struct)c.cxl_region_refhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hcxl_region_refh]j-)}(hstruct cxl_region_refh](j)}(hjh]hstruct}(hjdpa_res** resource treeh](hTrack DPA ‘skip’ in }(hjShhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh resource tree}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM-hjShhubah}(h]h ]h"]h$]h&]uh1jhjQhhhjQhMLubeh}(h]h ](jfunctioneh"]h$]h&]jjjjTjjTjjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** ``struct cxl_endpoint_decoder *cxled`` Endpoint decoder establishing new allocation that skips lower DPA ``const resource_size_t skip_base`` DPA < start of new DPA allocation (DPAnew) ``const resource_size_t skip_len`` **skip_base** + **skip_len** == DPAnew **Description** DPA 'skip' arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. It is a wasteful event as usable DPA gets thrown away, but if a deployment has, for example, a dual RAM+PMEM device, wants to use PMEM, and has unallocated RAM DPA, the free RAM DPA must be sacrificed to start allocating PMEM. See third "Implementation Note" in CXL 3.1 8.2.4.19.13 "Decoder Protection" for more details. A 'skip' always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation). If **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](j])}(h**Parameters**h]j)}(hjTh]h Parameters}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM1hj Tubjo)}(hhh](jt)}(hN``struct cxl_dev_state *cxlds`` CXL.mem device context that parents **cxled** h](jz)}(h``struct cxl_dev_state *cxlds``h]j)}(hj1Th]hstruct cxl_dev_state *cxlds}(hj3ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/Tubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM.hj+Tubj)}(hhh]j])}(h-CXL.mem device context that parents **cxled**h](h$CXL.mem device context that parents }(hjJThhhNhNubj)}(h **cxled**h]hcxled}(hjRThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJTubeh}(h]h ]h"]h$]h&]uh1j\hjFThM.hjGTubah}(h]h ]h"]h$]h&]uh1jhj+Tubeh}(h]h ]h"]h$]h&]uh1jshjFThM.hj(Tubjt)}(hi``struct cxl_endpoint_decoder *cxled`` Endpoint decoder establishing new allocation that skips lower DPA h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjxTh]h"struct cxl_endpoint_decoder *cxled}(hjzThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvTubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM/hjrTubj)}(hhh]j])}(hAEndpoint decoder establishing new allocation that skips lower DPAh]hAEndpoint decoder establishing new allocation that skips lower DPA}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjThM/hjTubah}(h]h ]h"]h$]h&]uh1jhjrTubeh}(h]h ]h"]h$]h&]uh1jshjThM/hj(Tubjt)}(hO``const resource_size_t skip_base`` DPA < start of new DPA allocation (DPAnew) h](jz)}(h#``const resource_size_t skip_base``h]j)}(hjTh]hconst resource_size_t skip_base}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM0hjTubj)}(hhh]j])}(h*DPA < start of new DPA allocation (DPAnew)h]h*DPA < start of new DPA allocation (DPAnew)}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjThM0hjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jshjThM0hj(Tubjt)}(hJ``const resource_size_t skip_len`` **skip_base** + **skip_len** == DPAnew h](jz)}(h"``const resource_size_t skip_len``h]j)}(hjTh]hconst resource_size_t skip_len}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM1hjTubj)}(hhh]j])}(h&**skip_base** + **skip_len** == DPAnewh](j)}(h **skip_base**h]h skip_base}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh + }(hjUhhhNhNubj)}(h **skip_len**h]hskip_len}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh == DPAnew}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjThM1hjUubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jshjThM1hj(Tubeh}(h]h ]h"]h$]h&]uh1jnhj Tubj])}(h**Description**h]j)}(hjEUh]h Description}(hjGUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCUubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM3hj Tubj])}(hXDPA 'skip' arises from out-of-sequence DPA allocation events relative to free capacity across multiple partitions. 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See third “Implementation Note” in CXL 3.1 8.2.4.19.13 “Decoder Protection” for more details.}(hj[UhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM3hj Tubj])}(hX<A 'skip' always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation).h]hX@A ‘skip’ always covers the last allocated DPA in a previous partition to the start of the current partition to allocate. Allocations never start in the middle of a partition, and allocations are always de-allocated in reverse order (see cxl_dpa_free(), or natural devm unwind order from forced in-order allocation).}(hjjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chM;hj Tubj])}(hXuIf **cxlds->nr_partitions** was guaranteed to be <= 2 then the 'skip' would always be contained to a single partition. Given **cxlds->nr_partitions** may be > 2 it results in cases where the 'skip' might span "tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]" to support allocating from partition[N]. That in turn interacts with the partition 'struct resource' boundaries within **cxlds->dpa_res** whereby 'skip' requests need to be divided by partition. I.e. this is a quirk of using a 'struct resource' tree to detect range conflicts while also tracking partition boundaries in **cxlds->dpa_res**.h](hIf }(hjyUhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyUubhf was guaranteed to be <= 2 then the ‘skip’ would always be contained to a single partition. Given }(hjyUhhhNhNubj)}(h**cxlds->nr_partitions**h]hcxlds->nr_partitions}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyUubhX may be > 2 it results in cases where the ‘skip’ might span “tail capacity of partition[0], all of partition[1], ..., all of partition[N-1]” to support allocating from partition[N]. That in turn interacts with the partition ‘struct resource’ boundaries within }(hjyUhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyUubh whereby ‘skip’ requests need to be divided by partition. I.e. this is a quirk of using a ‘struct resource’ tree to detect range conflicts while also tracking partition boundaries in }(hjyUhhhNhNubj)}(h**cxlds->dpa_res**h]hcxlds->dpa_res}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyUubh.}(hjyUhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chMAhj Tubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(devm_cxl_enumerate_decoders (C function)c.devm_cxl_enumerate_decodershNtauh1jhj-hhhNhNubj")}(hhh](j')}(h^int devm_cxl_enumerate_decoders (struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j-)}(h]int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j3)}(hinth]hint}(hjUhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjUhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chMubjE)}(h h]h }(hjUhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjUhhhjUhMubjV)}(hdevm_cxl_enumerate_decodersh]j\)}(hdevm_cxl_enumerate_decodersh]hdevm_cxl_enumerate_decoders}(hjVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj Vubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjUhhhjUhMubju)}(h>(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j{)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hj-VhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)VubjE)}(h h]h }(hj:VhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj)Vubh)}(hhh]j\)}(hcxl_hdmh]hcxl_hdm}(hjKVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjHVubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjMVmodnameN classnameNjj)}j]j)}jjVsbc.devm_cxl_enumerate_decodersasbuh1hhj)VubjE)}(h h]h }(hjkVhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj)Vubj)}(hjh]h*}(hjyVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)Vubj\)}(hcxlhdmh]hcxlhdm}(hjVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj)Vubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj%Vubj{)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubjE)}(h h]h }(hjVhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjVubh)}(hhh]j\)}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hjVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjVubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjVmodnameN classnameNjj)}j]jgVc.devm_cxl_enumerate_decodersasbuh1hhjVubjE)}(h h]h }(hjVhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjVubj)}(hjh]h*}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubj\)}(hinfoh]hinfo}(hjVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjVubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj%Vubeh}(h]h ]h"]h$]h&]hhuh1jthjUhhhjUhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjUhhhjUhMubah}(h]jUah ](jjeh"]h$]h&]jj)jhuh1j&hjUhMhjUhhubj)}(hhh]j])}(h(add decoder objects per HDM register seth]h(add decoder objects per HDM register set}(hj WhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chMhjWhhubah}(h]h ]h"]h$]h&]uh1jhjUhhhjUhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj8Wjj8Wjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_hdm *cxlhdm`` Structure to populate with HDM capabilities ``struct cxl_endpoint_dvsec_info *info`` cached DVSEC range register infoh](j])}(h**Parameters**h]j)}(hjBWh]h Parameters}(hjDWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@Wubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:439: ./drivers/cxl/core/hdm.chMhjXhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj-Xubh)}(hhh]j\)}(haccess_coordinateh]haccess_coordinate}(hjOXhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjLXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjQXmodnameN classnameNjj)}j]j)}jjXsbc.cxl_coordinates_combineasbuh1hhj-XubjE)}(h h]h }(hjoXhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj-Xubj)}(hjh]h*}(hj}XhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-Xubj\)}(houth]hout}(hjXhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj-Xubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj)Xubj{)}(hstruct access_coordinate *c1h](j)}(hjh]hstruct}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubjE)}(h h]h }(hjXhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjXubh)}(hhh]j\)}(haccess_coordinateh]haccess_coordinate}(hjXhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjXmodnameN classnameNjj)}j]jkXc.cxl_coordinates_combineasbuh1hhjXubjE)}(h h]h }(hjXhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjXubj)}(hjh]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubj\)}(hc1h]hc1}(hjXhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjXubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj)Xubj{)}(hstruct access_coordinate *c2h](j)}(hjh]hstruct}(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubjE)}(h h]h }(hj YhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjYubh)}(hhh]j\)}(haccess_coordinateh]haccess_coordinate}(hj1YhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj.Yubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj3YmodnameN classnameNjj)}j]jkXc.cxl_coordinates_combineasbuh1hhjYubjE)}(h h]h }(hjOYhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjYubj)}(hjh]h*}(hj]YhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj\)}(hc2h]hc2}(hjjYhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjYubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj)Xubeh}(h]h ]h"]h$]h&]hhuh1jthjWhhhjXhM(ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjWhhhjXhM(ubah}(h]jWah ](jjeh"]h$]h&]jj)jhuh1j&hjXhM(hjWhhubj)}(hhh]j])}(h!Combine the two input coordinatesh]h!Combine the two input coordinates}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM"hjYhhubah}(h]h ]h"]h$]h&]uh1jhjWhhhjXhM(ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjYjjYjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct access_coordinate *out`` Output coordinate of c1 and c2 combined ``struct access_coordinate *c1`` input coordinates ``struct access_coordinate *c2`` input coordinatesh](j])}(h**Parameters**h]j)}(hjYh]h Parameters}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM&hjYubjo)}(hhh](jt)}(hJ``struct access_coordinate *out`` Output coordinate of c1 and c2 combined h](jz)}(h!``struct access_coordinate *out``h]j)}(hjYh]hstruct access_coordinate *out}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM$hjYubj)}(hhh]j])}(h'Output coordinate of c1 and c2 combinedh]h'Output coordinate of c1 and c2 combined}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjYhM$hjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jshjYhM$hjYubjt)}(h3``struct access_coordinate *c1`` input coordinates h](jz)}(h ``struct access_coordinate *c1``h]j)}(hjZh]hstruct access_coordinate *c1}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Zubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM%hjZubj)}(hhh]j])}(hinput coordinatesh]hinput coordinates}(hj'ZhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#ZhM%hj$Zubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jshj#ZhM%hjYubjt)}(h2``struct access_coordinate *c2`` input coordinatesh](jz)}(h ``struct access_coordinate *c2``h]j)}(hjGZh]hstruct access_coordinate *c2}(hjIZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEZubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM'hjAZubj)}(hhh]j])}(hinput coordinatesh]hinput coordinates}(hj`ZhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM&hj]Zubah}(h]h ]h"]h$]h&]uh1jhjAZubeh}(h]h ]h"]h$]h&]uh1jshj\ZhM'hjYubeh}(h]h ]h"]h$]h&]uh1jnhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j*cxl_endpoint_gather_bandwidth (C function)c.cxl_endpoint_gather_bandwidthhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hint cxl_endpoint_gather_bandwidth (struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h]j-)}(hint cxl_endpoint_gather_bandwidth(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j3)}(hinth]hint}(hjZhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjZhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMwubjE)}(h h]h }(hjZhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjZhhhjZhMwubjV)}(hcxl_endpoint_gather_bandwidthh]j\)}(hcxl_endpoint_gather_bandwidthh]hcxl_endpoint_gather_bandwidth}(hjZhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjZubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjZhhhjZhMwubju)}(hf(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, struct xarray *usp_xa, bool *gp_is_root)h](j{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubjE)}(h h]h }(hjZhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjZubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hjZhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjZubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjZmodnameN classnameNjj)}j]j)}jjZsbc.cxl_endpoint_gather_bandwidthasbuh1hhjZubjE)}(h h]h }(hj[hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjZubj)}(hjh]h*}(hj*[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj\)}(hcxlrh]hcxlr}(hj7[hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjZubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjZubj{)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hjP[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL[ubjE)}(h h]h }(hj][hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjL[ubh)}(hhh]j\)}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hjn[hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjk[ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjp[modnameN classnameNjj)}j]j[c.cxl_endpoint_gather_bandwidthasbuh1hhjL[ubjE)}(h h]h }(hj[hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjL[ubj)}(hjh]h*}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjL[ubj\)}(hcxledh]hcxled}(hj[hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjL[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjZubj{)}(hstruct xarray *usp_xah](j)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubjE)}(h h]h }(hj[hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj[ubh)}(hhh]j\)}(hxarrayh]hxarray}(hj[hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj[ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj[modnameN classnameNjj)}j]j[c.cxl_endpoint_gather_bandwidthasbuh1hhj[ubjE)}(h h]h }(hj[hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj[ubj)}(hjh]h*}(hj \hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubj\)}(husp_xah]husp_xa}(hj\hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjZubj{)}(hbool *gp_is_rooth](j3)}(hboolh]hbool}(hj0\hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj,\ubjE)}(h h]h }(hj>\hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj,\ubj)}(hjh]h*}(hjL\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,\ubj\)}(h gp_is_rooth]h gp_is_root}(hjY\hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj,\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjZubeh}(h]h ]h"]h$]h&]hhuh1jthjZhhhjZhMwubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjZhhhjZhMwubah}(h]jZah ](jjeh"]h$]h&]jj)jhuh1j&hjZhMwhjZhhubj)}(hhh]j])}(h/collect all the endpoint bandwidth in an xarrayh]h/collect all the endpoint bandwidth in an xarray}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMfhj\hhubah}(h]h ]h"]h$]h&]uh1jhjZhhhjZhMwubeh}(h]h ](jfunctioneh"]h$]h&]jjjj\jj\jjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_region *cxlr`` CXL region for the bandwidth calculation ``struct cxl_endpoint_decoder *cxled`` endpoint decoder to start on ``struct xarray *usp_xa`` (output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'. ``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. **Return** 0 for success or -errno **Description** Collects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that's associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.h](j])}(h**Parameters**h]j)}(hj\h]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMjhj\ubjo)}(hhh](jt)}(hE``struct cxl_region *cxlr`` CXL region for the bandwidth calculation h](jz)}(h``struct cxl_region *cxlr``h]j)}(hj\h]hstruct cxl_region *cxlr}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMghj\ubj)}(hhh]j])}(h(CXL region for the bandwidth calculationh]h(CXL region for the bandwidth calculation}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj\hMghj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jshj\hMghj\ubjt)}(hD``struct cxl_endpoint_decoder *cxled`` endpoint decoder to start on h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hj\h]h"struct cxl_endpoint_decoder *cxled}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhhj\ubj)}(hhh]j])}(hendpoint decoder to start onh]hendpoint decoder to start on}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj]hMhhj]ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jshj]hMhhj\ubjt)}(h``struct xarray *usp_xa`` (output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'. h](jz)}(h``struct xarray *usp_xa``h]j)}(hj6]h]hstruct xarray *usp_xa}(hj8]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4]ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMjhj0]ubj)}(hhh]j])}(h(output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of 'struct cxl_perf_ctx'.h]h(output) the xarray that collects all the bandwidth coordinates indexed by the upstream device with data of ‘struct cxl_perf_ctx’.}(hjO]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMihjL]ubah}(h]h ]h"]h$]h&]uh1jhj0]ubeh}(h]h ]h"]h$]h&]uh1jshjK]hMjhj\ubjt)}(hK``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. h](jz)}(h``bool *gp_is_root``h]j)}(hjp]h]hbool *gp_is_root}(hjr]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn]ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMkhjj]ubj)}(hhh]j])}(h5(output) bool of whether the grandparent is cxl root.h]h5(output) bool of whether the grandparent is cxl root.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj]hMkhj]ubah}(h]h ]h"]h$]h&]uh1jhjj]ubeh}(h]h ]h"]h$]h&]uh1jshj]hMkhj\ubeh}(h]h ]h"]h$]h&]uh1jnhj\ubj])}(h **Return**h]j)}(hj]h]hReturn}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMmhj\ubj])}(h0 for success or -errnoh]h0 for success or -errno}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMmhj\ubj])}(h**Description**h]j)}(hj]h]h Description}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMohj\ubj])}(hXCollects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that's associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.h]hXCollects aggregated endpoint bandwidth and store the bandwidth in an xarray indexed by the upstream device of the switch or the RP device. Each endpoint consists the minimum of the bandwidth from DSLBIS from the endpoint CDAT, the endpoint upstream link bandwidth, and the bandwidth from the SSLBIS of the switch CDAT for the switch upstream port to the downstream port that’s associated with the endpoint. If the device is directly connected to a RP, then no SSLBIS is involved.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMohj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(cxl_switch_gather_bandwidth (C function)c.cxl_switch_gather_bandwidthhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hpstruct xarray * cxl_switch_gather_bandwidth (struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h]j-)}(hnstruct xarray *cxl_switch_gather_bandwidth(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j)}(hjh]hstruct}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMubjE)}(h h]h }(hj%^hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^hhhj$^hMubh)}(hhh]j\)}(hxarrayh]hxarray}(hj6^hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj3^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj8^modnameN classnameNjj)}j]j)}jcxl_switch_gather_bandwidthsbc.cxl_switch_gather_bandwidthasbuh1hhj^hhhj$^hMubjE)}(h h]h }(hjW^hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^hhhj$^hMubj)}(hjh]h*}(hje^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^hhhj$^hMubjV)}(hcxl_switch_gather_bandwidthh]j\)}(hjT^h]hcxl_switch_gather_bandwidth}(hjv^hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjr^ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj^hhhj$^hMubju)}(hD(struct cxl_region *cxlr, struct xarray *input_xa, bool *gp_is_root)h](j{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubjE)}(h h]h }(hj^hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^ubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hj^hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj^ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj^modnameN classnameNjj)}j]jR^c.cxl_switch_gather_bandwidthasbuh1hhj^ubjE)}(h h]h }(hj^hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^ubj)}(hjh]h*}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj\)}(hcxlrh]hcxlr}(hj^hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj^ubj{)}(hstruct xarray *input_xah](j)}(hjh]hstruct}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubjE)}(h h]h }(hj_hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^ubh)}(hhh]j\)}(hxarrayh]hxarray}(hj_hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj!_modnameN classnameNjj)}j]jR^c.cxl_switch_gather_bandwidthasbuh1hhj^ubjE)}(h h]h }(hj=_hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj^ubj)}(hjh]h*}(hjK_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj\)}(hinput_xah]hinput_xa}(hjX_hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj^ubj{)}(hbool *gp_is_rooth](j3)}(hj2\h]hbool}(hjq_hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjm_ubjE)}(h h]h }(hj~_hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjm_ubj)}(hjh]h*}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm_ubj\)}(h gp_is_rooth]h gp_is_root}(hj_hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjm_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj^ubeh}(h]h ]h"]h$]h&]hhuh1jthj^hhhj$^hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj^hhhj$^hMubah}(h]j ^ah ](jjeh"]h$]h&]jj)jhuh1j&hj$^hMhj ^hhubj)}(hhh]j])}(h6collect all the bandwidth at switch level in an xarrayh]h6collect all the bandwidth at switch level in an xarray}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_hhubah}(h]h ]h"]h$]h&]uh1jhj ^hhhj$^hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj_jj_jjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_region *cxlr`` The region being operated on ``struct xarray *input_xa`` xarray indexed by upstream device of a switch with data of 'struct cxl_perf_ctx' ``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. **Return** a xarray of resulting cxl_perf_ctx per parent switch or root port or ERR_PTR(-errno) **Description** Iterate through the xarray. Take the minimum of the downstream calculated bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream switch if exists. Sum the resulting bandwidth under the switch upstream device or a RP device. The function can be iterated over multiple switches if the switches are present.h](j])}(h**Parameters**h]j)}(hj_h]h Parameters}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_ubjo)}(hhh](jt)}(h9``struct cxl_region *cxlr`` The region being operated on h](jz)}(h``struct cxl_region *cxlr``h]j)}(hj`h]hstruct cxl_region *cxlr}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_ubj)}(hhh]j])}(hThe region being operated onh]hThe region being operated on}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`hMhj`ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshj`hMhj_ubjt)}(hm``struct xarray *input_xa`` xarray indexed by upstream device of a switch with data of 'struct cxl_perf_ctx' h](jz)}(h``struct xarray *input_xa``h]j)}(hj=`h]hstruct xarray *input_xa}(hj?`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;`ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj7`ubj)}(hhh]j])}(hPxarray indexed by upstream device of a switch with data of 'struct cxl_perf_ctx'h]hTxarray indexed by upstream device of a switch with data of ‘struct cxl_perf_ctx’}(hjV`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjS`ubah}(h]h ]h"]h$]h&]uh1jhj7`ubeh}(h]h ]h"]h$]h&]uh1jshjR`hMhj_ubjt)}(hK``bool *gp_is_root`` (output) bool of whether the grandparent is cxl root. h](jz)}(h``bool *gp_is_root``h]j)}(hjw`h]hbool *gp_is_root}(hjy`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju`ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjq`ubj)}(hhh]j])}(h5(output) bool of whether the grandparent is cxl root.h]h5(output) bool of whether the grandparent is cxl root.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`hMhj`ubah}(h]h ]h"]h$]h&]uh1jhjq`ubeh}(h]h ]h"]h$]h&]uh1jshj`hMhj_ubeh}(h]h ]h"]h$]h&]uh1jnhj_ubj])}(h **Return**h]j)}(hj`h]hReturn}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_ubjo)}(hhh]jt)}(hUa xarray of resulting cxl_perf_ctx per parent switch or root port or ERR_PTR(-errno) h](jz)}(hAa xarray of resulting cxl_perf_ctx per parent switch or root porth]hAa xarray of resulting cxl_perf_ctx per parent switch or root port}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj`ubj)}(hhh]j])}(hor ERR_PTR(-errno)h]hor ERR_PTR(-errno)}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`hMhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jshj`hMhj`ubah}(h]h ]h"]h$]h&]uh1jnhj_ubj])}(h**Description**h]j)}(hjah]h Description}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_ubj])}(hX@Iterate through the xarray. Take the minimum of the downstream calculated bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream switch if exists. Sum the resulting bandwidth under the switch upstream device or a RP device. The function can be iterated over multiple switches if the switches are present.h]hX@Iterate through the xarray. Take the minimum of the downstream calculated bandwidth, the upstream link bandwidth, and the SSLBIS of the upstream switch if exists. Sum the resulting bandwidth under the switch upstream device or a RP device. The function can be iterated over multiple switches if the switches are present.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$cxl_rp_gather_bandwidth (C function)c.cxl_rp_gather_bandwidthhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h;struct xarray * cxl_rp_gather_bandwidth (struct xarray *xa)h]j-)}(h9struct xarray *cxl_rp_gather_bandwidth(struct xarray *xa)h](j)}(hjh]hstruct}(hjHahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDahhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMaubjE)}(h h]h }(hjVahhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjDahhhjUahMaubh)}(hhh]j\)}(hxarrayh]hxarray}(hjgahhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjdaubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjiamodnameN classnameNjj)}j]j)}jcxl_rp_gather_bandwidthsbc.cxl_rp_gather_bandwidthasbuh1hhjDahhhjUahMaubjE)}(h h]h }(hjahhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjDahhhjUahMaubj)}(hjh]h*}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDahhhjUahMaubjV)}(hcxl_rp_gather_bandwidthh]j\)}(hjah]hcxl_rp_gather_bandwidth}(hjahhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjaubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjDahhhjUahMaubju)}(h(struct xarray *xa)h]j{)}(hstruct xarray *xah](j)}(hjh]hstruct}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubjE)}(h h]h }(hjahhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjaubh)}(hhh]j\)}(hxarrayh]hxarray}(hjahhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjaubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjamodnameN classnameNjj)}j]jac.cxl_rp_gather_bandwidthasbuh1hhjaubjE)}(h h]h }(hjahhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjaubj)}(hjh]h*}(hj bhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj\)}(hxah]hxa}(hjbhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjaubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjaubah}(h]h ]h"]h$]h&]hhuh1jthjDahhhjUahMaubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj@ahhhjUahMaubah}(h]j;aah ](jjeh"]h$]h&]jj)jhuh1j&hjUahMahj=ahhubj)}(hhh]j])}(h/handle the root port level bandwidth collectionh]h/handle the root port level bandwidth collection}(hjCbhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM[hj@bhhubah}(h]h ]h"]h$]h&]uh1jhj=ahhhjUahMaubeh}(h]h ](jfunctioneh"]h$]h&]jjjj[bjj[bjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct xarray *xa`` the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each root port device. **Return** xarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)h](j])}(h**Parameters**h]j)}(hjebh]h Parameters}(hjgbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcbubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM_hj_bubjo)}(hhh]jt)}(h|``struct xarray *xa`` the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each root port device. h](jz)}(h``struct xarray *xa``h]j)}(hjbh]hstruct xarray *xa}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM]hj~bubj)}(hhh]j])}(hethe xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each root port device.h]hethe xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each root port device.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM\hjbubah}(h]h ]h"]h$]h&]uh1jhj~bubeh}(h]h ]h"]h$]h&]uh1jshjbhM]hj{bubah}(h]h ]h"]h$]h&]uh1jnhj_bubj])}(h **Return**h]j)}(hjbh]hReturn}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM_hj_bubj])}(hAxarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)h]hAxarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chM_hj_bubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$cxl_hb_gather_bandwidth (C function)c.cxl_hb_gather_bandwidthhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h;struct xarray * cxl_hb_gather_bandwidth (struct xarray *xa)h]j-)}(h9struct xarray *cxl_hb_gather_bandwidth(struct xarray *xa)h](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMubjE)}(h h]h }(hjchhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjchhhjchMubh)}(hhh]j\)}(hxarrayh]hxarray}(hj$chhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj!cubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj&cmodnameN classnameNjj)}j]j)}jcxl_hb_gather_bandwidthsbc.cxl_hb_gather_bandwidthasbuh1hhjchhhjchMubjE)}(h h]h }(hjEchhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjchhhjchMubj)}(hjh]h*}(hjSchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjchhhjchMubjV)}(hcxl_hb_gather_bandwidthh]j\)}(hjBch]hcxl_hb_gather_bandwidth}(hjdchhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj`cubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjchhhjchMubju)}(h(struct xarray *xa)h]j{)}(hstruct xarray *xah](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{cubjE)}(h h]h }(hjchhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj{cubh)}(hhh]j\)}(hxarrayh]hxarray}(hjchhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjcubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjcmodnameN classnameNjj)}j]j@cc.cxl_hb_gather_bandwidthasbuh1hhj{cubjE)}(h h]h }(hjchhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj{cubj)}(hjh]h*}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{cubj\)}(hxah]hxa}(hjchhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj{cubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjwcubah}(h]h ]h"]h$]h&]hhuh1jthjchhhjchMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjbhhhjchMubah}(h]jbah ](jjeh"]h$]h&]jj)jhuh1j&hjchMhjbhhubj)}(hhh]j])}(h1handle the host bridge level bandwidth collectionh]h1handle the host bridge level bandwidth collection}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjchhubah}(h]h ]h"]h$]h&]uh1jhjbhhhjchMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjdjjdjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct xarray *xa`` the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each host bridge. **Return** xarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)h](j])}(h**Parameters**h]j)}(hj"dh]h Parameters}(hj$dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj dubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjdubjo)}(hhh]jt)}(hw``struct xarray *xa`` the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each host bridge. h](jz)}(h``struct xarray *xa``h]j)}(hjAdh]hstruct xarray *xa}(hjCdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?dubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj;dubj)}(hhh]j])}(h`the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each host bridge.h]h`the xarray that holds the cxl_perf_ctx that has the bandwidth calculated below each host bridge.}(hjZdhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjWdubah}(h]h ]h"]h$]h&]uh1jhj;dubeh}(h]h ]h"]h$]h&]uh1jshjVdhMhj8dubah}(h]h ]h"]h$]h&]uh1jnhjdubj])}(h **Return**h]j)}(hj}dh]hReturn}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{dubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjdubj])}(hExarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)h]hExarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjdubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j(cxl_region_update_bandwidth (C function)c.cxl_region_update_bandwidthhNtauh1jhj-hhhNhNubj")}(hhh](j')}(hSvoid cxl_region_update_bandwidth (struct cxl_region *cxlr, struct xarray *input_xa)h]j-)}(hRvoid cxl_region_update_bandwidth(struct cxl_region *cxlr, struct xarray *input_xa)h](j3)}(hvoidh]hvoid}(hjdhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjdhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMubjE)}(h h]h }(hjdhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjdhhhjdhMubjV)}(hcxl_region_update_bandwidthh]j\)}(hcxl_region_update_bandwidthh]hcxl_region_update_bandwidth}(hjdhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjdubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjdhhhjdhMubju)}(h2(struct cxl_region *cxlr, struct xarray *input_xa)h](j{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubjE)}(h h]h }(hj ehhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjdubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hjehhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjeubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjemodnameN classnameNjj)}j]j)}jjdsbc.cxl_region_update_bandwidthasbuh1hhjdubjE)}(h h]h }(hj=ehhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjdubj)}(hjh]h*}(hjKehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubj\)}(hcxlrh]hcxlr}(hjXehhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjdubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjdubj{)}(hstruct xarray *input_xah](j)}(hjh]hstruct}(hjqehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmeubjE)}(h h]h }(hj~ehhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjmeubh)}(hhh]j\)}(hxarrayh]hxarray}(hjehhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjeubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjemodnameN classnameNjj)}j]j9ec.cxl_region_update_bandwidthasbuh1hhjmeubjE)}(h h]h }(hjehhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjmeubj)}(hjh]h*}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmeubj\)}(hinput_xah]hinput_xa}(hjehhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjmeubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjdubeh}(h]h ]h"]h$]h&]hhuh1jthjdhhhjdhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjdhhhjdhMubah}(h]jdah ](jjeh"]h$]h&]jj)jhuh1j&hjdhMhjdhhubj)}(hhh]j])}(h3Update the bandwidth access coordinates of a regionh]h3Update the bandwidth access coordinates of a region}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjehhubah}(h]h ]h"]h$]h&]uh1jhjdhhhjdhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj fjj fjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_region *cxlr`` The region being operated on ``struct xarray *input_xa`` xarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh](j])}(h**Parameters**h]j)}(hjfh]h Parameters}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjfubjo)}(hhh](jt)}(h9``struct cxl_region *cxlr`` The region being operated on h](jz)}(h``struct cxl_region *cxlr``h]j)}(hj3fh]hstruct cxl_region *cxlr}(hj5fhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1fubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhj-fubj)}(hhh]j])}(hThe region being operated onh]hThe region being operated on}(hjLfhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjHfhMhjIfubah}(h]h ]h"]h$]h&]uh1jhj-fubeh}(h]h ]h"]h$]h&]uh1jshjHfhMhj*fubjt)}(hd``struct xarray *input_xa`` xarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh](jz)}(h``struct xarray *input_xa``h]j)}(hjlfh]hstruct xarray *input_xa}(hjnfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjfubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjffubj)}(hhh]j])}(hHxarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instanceh]hHxarray holds cxl_perf_ctx wht calculated bandwidth per ACPI0017 instance}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjfubah}(h]h ]h"]h$]h&]uh1jhjffubeh}(h]h ]h"]h$]h&]uh1jshjfhMhj*fubeh}(h]h ]h"]h$]h&]uh1jnhjfubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j8cxl_region_shared_upstream_bandwidth_update (C function)-c.cxl_region_shared_upstream_bandwidth_updatehNtauh1jhj-hhhNhNubj")}(hhh](j')}(hJvoid cxl_region_shared_upstream_bandwidth_update (struct cxl_region *cxlr)h]j-)}(hIvoid cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr)h](j3)}(hvoidh]hvoid}(hjfhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjfhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMubjE)}(h h]h }(hjfhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjfhhhjfhMubjV)}(h+cxl_region_shared_upstream_bandwidth_updateh]j\)}(h+cxl_region_shared_upstream_bandwidth_updateh]h+cxl_region_shared_upstream_bandwidth_update}(hjfhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjfubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjfhhhjfhMubju)}(h(struct cxl_region *cxlr)h]j{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubjE)}(h h]h }(hjghhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjfubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hj!ghhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjgubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj#gmodnameN classnameNjj)}j]j)}jjfsb-c.cxl_region_shared_upstream_bandwidth_updateasbuh1hhjfubjE)}(h h]h }(hjAghhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjfubj)}(hjh]h*}(hjOghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubj\)}(hcxlrh]hcxlr}(hj\ghhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjfubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjfubah}(h]h ]h"]h$]h&]hhuh1jthjfhhhjfhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjfhhhjfhMubah}(h]jfah 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It starts at the endpoints, processes at the switches if any, processes at the rootport level, at the host bridge level, and finally aggregates at the region.h](j])}(h**Parameters**h]j)}(hjgh]h Parameters}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjgubjo)}(hhh]jt)}(h:``struct cxl_region *cxlr`` the cxl region to recalculate h](jz)}(h``struct cxl_region *cxlr``h]j)}(hjgh]hstruct cxl_region *cxlr}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjgubj)}(hhh]j])}(hthe cxl region to recalculateh]hthe cxl region to recalculate}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjghMhjgubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jshjghMhjgubah}(h]h ]h"]h$]h&]uh1jnhjgubj])}(h**Description**h]j)}(hjhh]h Description}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjgubj])}(hThe function walks the topology from bottom up and calculates the bandwidth. It starts at the endpoints, processes at the switches if any, processes at the rootport level, at the host bridge level, and finally aggregates at the region.h]hThe function walks the topology from bottom up and calculates the bandwidth. It starts at the endpoints, processes at the switches if any, processes at the rootport level, at the host bridge level, and finally aggregates at the region.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:442: ./drivers/cxl/core/cdat.chMhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj])}(hXThe CXL core provides a set of interfaces that can be consumed by CXL aware drivers. The interfaces allow for creation, modification, and destruction of regions, memory devices, ports, and decoders. CXL aware drivers must register with the CXL core via these interfaces in order to be able to participate in cross-device interleave coordination. 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The CXL core also establishes and maintains the bridge to the nvdimm subsystem.}(hj.hhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:445: ./drivers/cxl/core/port.chKhj-hhubj])}(h]CXL core introduces sysfs hierarchy to control the devices that are instantiated by the core.h]h]CXL core introduces sysfs hierarchy to control the devices that are instantiated by the core.}(hj=hhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:445: ./drivers/cxl/core/port.chKhj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdevm_cxl_add_port (C function)c.devm_cxl_add_porthNtauh1jhj-hhhNhNubj")}(hhh](j')}(hstruct cxl_port * devm_cxl_add_port (struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport)h]j-)}(hstruct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport)h](j)}(hjh]hstruct}(hjehhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjahhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjshhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjahhhhjrhhMubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjhhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjhubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhmodnameN classnameNjj)}j]j)}jdevm_cxl_add_portsbc.devm_cxl_add_portasbuh1hhjahhhhjrhhMubjE)}(h h]h }(hjhhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjahhhhjrhhMubj)}(hjh]h*}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjahhhhjrhhMubjV)}(hdevm_cxl_add_porth]j\)}(hjhh]hdevm_cxl_add_port}(hjhhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjhubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjahhhhjrhhMubju)}(hs(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport)h](j{)}(hstruct device *hosth](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubjE)}(h h]h }(hjhhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhubh)}(hhh]j\)}(hdeviceh]hdevice}(hjhhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjhubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhmodnameN classnameNjj)}j]jhc.devm_cxl_add_portasbuh1hhjhubjE)}(h h]h }(hjihhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhubj)}(hjh]h*}(hj)ihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj\)}(hhosth]hhost}(hj6ihhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjhubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjhubj{)}(hstruct device *uport_devh](j)}(hjh]hstruct}(hjOihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKiubjE)}(h h]h }(hj\ihhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjKiubh)}(hhh]j\)}(hdeviceh]hdevice}(hjmihhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjjiubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjoimodnameN classnameNjj)}j]jhc.devm_cxl_add_portasbuh1hhjKiubjE)}(h h]h }(hjihhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjKiubj)}(hjh]h*}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKiubj\)}(h uport_devh]h uport_dev}(hjihhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjKiubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjhubj{)}(h"resource_size_t component_reg_physh](h)}(hhh]j\)}(hresource_size_th]hresource_size_t}(hjihhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjiubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjimodnameN classnameNjj)}j]jhc.devm_cxl_add_portasbuh1hhjiubjE)}(h h]h }(hjihhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjiubj\)}(hcomponent_reg_physh]hcomponent_reg_phys}(hjihhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjiubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjhubj{)}(hstruct cxl_dport *parent_dporth](j)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubjE)}(h h]h }(hjjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjjubh)}(hhh]j\)}(h cxl_dporth]h cxl_dport}(hj%jhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj"jubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj'jmodnameN classnameNjj)}j]jhc.devm_cxl_add_portasbuh1hhjjubjE)}(h h]h }(hjCjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjjubj)}(hjh]h*}(hjQjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj\)}(h parent_dporth]h parent_dport}(hj^jhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjhubeh}(h]h ]h"]h$]h&]hhuh1jthjahhhhjrhhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj]hhhhjrhhMubah}(h]jXhah ](jjeh"]h$]h&]jj)jhuh1j&hjrhhMhjZhhhubj)}(hhh]j])}(h2register a cxl_port in CXL memory decode hierarchyh]h2register a cxl_port in CXL memory decode hierarchy}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjjhhubah}(h]h ]h"]h$]h&]uh1jhjZhhhhjrhhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjjjuh1j!hhhj-hNhNubj)}(hXI**Parameters** ``struct device *host`` host device for devm operations ``struct device *uport_dev`` "physical" device implementing this upstream port ``resource_size_t component_reg_phys`` (optional) for configurable cxl_port instances ``struct cxl_dport *parent_dport`` next hop up in the CXL memory decode hierarchyh](j])}(h**Parameters**h]j)}(hjjh]h Parameters}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjjubjo)}(hhh](jt)}(h8``struct device *host`` host device for devm operations h](jz)}(h``struct device *host``h]j)}(hjjh]hstruct device *host}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjjubj)}(hhh]j])}(hhost device for devm operationsh]hhost device for devm operations}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjjhMhjjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jshjjhMhjjubjt)}(hO``struct device *uport_dev`` "physical" device implementing this upstream port h](jz)}(h``struct device *uport_dev``h]j)}(hjkh]hstruct device *uport_dev}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjjubj)}(hhh]j])}(h1"physical" device implementing this upstream porth]h5“physical” device implementing this upstream port}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjkhMhjkubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jshjkhMhjjubjt)}(hV``resource_size_t component_reg_phys`` (optional) for configurable cxl_port instances h](jz)}(h&``resource_size_t component_reg_phys``h]j)}(hj;kh]h"resource_size_t component_reg_phys}(hj=khhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9kubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj5kubj)}(hhh]j])}(h.(optional) for configurable cxl_port instancesh]h.(optional) for configurable cxl_port instances}(hjTkhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjPkhMhjQkubah}(h]h ]h"]h$]h&]uh1jhj5kubeh}(h]h ]h"]h$]h&]uh1jshjPkhMhjjubjt)}(hQ``struct cxl_dport *parent_dport`` next hop up in the CXL memory decode hierarchyh](jz)}(h"``struct cxl_dport *parent_dport``h]j)}(hjtkh]hstruct cxl_dport *parent_dport}(hjvkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrkubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjnkubj)}(hhh]j])}(h.next hop up in the CXL memory decode hierarchyh]h.next hop up in the CXL memory decode hierarchy}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjkubah}(h]h ]h"]h$]h&]uh1jhjnkubeh}(h]h ]h"]h$]h&]uh1jshjkhMhjjubeh}(h]h ]h"]h$]h&]uh1jnhjjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jdevm_cxl_add_dport (C function)c.devm_cxl_add_dporthNtauh1jhj-hhhNhNubj")}(hhh](j')}(hstruct cxl_dport * devm_cxl_add_dport (struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h]j-)}(hstruct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h](j)}(hjh]hstruct}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjkhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjkhhhjkhMubh)}(hhh]j\)}(h cxl_dporth]h cxl_dport}(hjkhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjkubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjkmodnameN classnameNjj)}j]j)}jdevm_cxl_add_dportsbc.devm_cxl_add_dportasbuh1hhjkhhhjkhMubjE)}(h h]h }(hjlhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjkhhhjkhMubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkhhhjkhMubjV)}(hdevm_cxl_add_dporth]j\)}(hj lh]hdevm_cxl_add_dport}(hj-lhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj)lubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjkhhhjkhMubju)}(hb(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t component_reg_phys)h](j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjHlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDlubjE)}(h h]h }(hjUlhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjDlubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjflhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjclubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjhlmodnameN classnameNjj)}j]j lc.devm_cxl_add_dportasbuh1hhjDlubjE)}(h h]h }(hjlhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjDlubj)}(hjh]h*}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDlubj\)}(hporth]hport}(hjlhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjDlubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj@lubj{)}(hstruct device *dport_devh](j)}(hjh]hstruct}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubjE)}(h h]h }(hjlhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjlubh)}(hhh]j\)}(hdeviceh]hdevice}(hjlhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjlubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjlmodnameN classnameNjj)}j]j lc.devm_cxl_add_dportasbuh1hhjlubjE)}(h h]h }(hjlhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjlubj)}(hjh]h*}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj\)}(h dport_devh]h dport_dev}(hjmhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjlubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj@lubj{)}(h int port_idh](j3)}(hinth]hint}(hj(mhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj$mubjE)}(h h]h }(hj6mhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj$mubj\)}(hport_idh]hport_id}(hjDmhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj$mubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj@lubj{)}(h"resource_size_t component_reg_physh](h)}(hhh]j\)}(hresource_size_th]hresource_size_t}(hj`mhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj]mubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjbmmodnameN classnameNjj)}j]j lc.devm_cxl_add_dportasbuh1hhjYmubjE)}(h h]h }(hj~mhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjYmubj\)}(hcomponent_reg_physh]hcomponent_reg_phys}(hjmhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjYmubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj@lubeh}(h]h ]h"]h$]h&]hhuh1jthjkhhhjkhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjkhhhjkhMubah}(h]jkah ](jjeh"]h$]h&]jj)jhuh1j&hjkhMhjkhhubj)}(hhh]j])}(h,append VH downstream port data to a cxl_porth]h,append VH downstream port data to a cxl_port}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjmhhubah}(h]h ]h"]h$]h&]uh1jhjkhhhjkhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjmjjmjjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_port *port`` the cxl_port that references this dport ``struct device *dport_dev`` firmware or PCI device representing the dport ``int port_id`` identifier for this dport in a decoder's target list ``resource_size_t component_reg_phys`` optional location of CXL component registers **Description** Note that dports are appended to the devm release action's of the either the port's host (for root ports), or the port itself (for switch ports)h](j])}(h**Parameters**h]j)}(hjmh]h Parameters}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjmubjo)}(hhh](jt)}(hB``struct cxl_port *port`` the cxl_port that references this dport h](jz)}(h``struct cxl_port *port``h]j)}(hjmh]hstruct cxl_port *port}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjmubj)}(hhh]j])}(h'the cxl_port that references this dporth]h'the cxl_port that references this dport}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj nhMhj nubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jshj nhMhjmubjt)}(hK``struct device *dport_dev`` firmware or PCI device representing the dport h](jz)}(h``struct device *dport_dev``h]j)}(hj0nh]hstruct device *dport_dev}(hj2nhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.nubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj*nubj)}(hhh]j])}(h-firmware or PCI device representing the dporth]h-firmware or PCI device representing the dport}(hjInhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjEnhMhjFnubah}(h]h ]h"]h$]h&]uh1jhj*nubeh}(h]h ]h"]h$]h&]uh1jshjEnhMhjmubjt)}(hE``int port_id`` identifier for this dport in a decoder's target list h](jz)}(h``int port_id``h]j)}(hjinh]h int port_id}(hjknhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgnubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjcnubj)}(hhh]j])}(h4identifier for this dport in a decoder's target listh]h6identifier for this dport in a decoder’s target list}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj~nhMhjnubah}(h]h ]h"]h$]h&]uh1jhjcnubeh}(h]h ]h"]h$]h&]uh1jshj~nhMhjmubjt)}(hT``resource_size_t component_reg_phys`` optional location of CXL component registers h](jz)}(h&``resource_size_t component_reg_phys``h]j)}(hjnh]h"resource_size_t component_reg_phys}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjnubj)}(hhh]j])}(h,optional location of CXL component registersh]h,optional location of CXL component registers}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjnhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jshjnhMhjmubeh}(h]h ]h"]h$]h&]uh1jnhjmubj])}(h**Description**h]j)}(hjnh]h Description}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjmubj])}(hNote that dports are appended to the devm release action's of the either the port's host (for root ports), or the port itself (for switch ports)h]hNote that dports are appended to the devm release action’s of the either the port’s host (for root ports), or the port itself (for switch ports)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#devm_cxl_add_rch_dport (C function)c.devm_cxl_add_rch_dporthNtauh1jhj-hhhNhNubj")}(hhh](j')}(h~struct cxl_dport * devm_cxl_add_rch_dport (struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h]j-)}(h|struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h](j)}(hjh]hstruct}(hj"ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hj0ohhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjohhhj/ohMubh)}(hhh]j\)}(h cxl_dporth]h cxl_dport}(hjAohhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj>oubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjComodnameN classnameNjj)}j]j)}jdevm_cxl_add_rch_dportsbc.devm_cxl_add_rch_dportasbuh1hhjohhhj/ohMubjE)}(h h]h }(hjbohhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjohhhj/ohMubj)}(hjh]h*}(hjpohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjohhhj/ohMubjV)}(hdevm_cxl_add_rch_dporth]j\)}(hj_oh]hdevm_cxl_add_rch_dport}(hjohhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj}oubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjohhhj/ohMubju)}(hT(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb)h](j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubjE)}(h h]h }(hjohhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjoubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjohhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjoubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjomodnameN classnameNjj)}j]j]oc.devm_cxl_add_rch_dportasbuh1hhjoubjE)}(h h]h }(hjohhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjoubj)}(hjh]h*}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj\)}(hporth]hport}(hjohhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjoubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjoubj{)}(hstruct device *dport_devh](j)}(hjh]hstruct}(hj phhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubjE)}(h h]h }(hjphhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjpubh)}(hhh]j\)}(hdeviceh]hdevice}(hj*phhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj'pubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj,pmodnameN classnameNjj)}j]j]oc.devm_cxl_add_rch_dportasbuh1hhjpubjE)}(h h]h }(hjHphhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjpubj)}(hjh]h*}(hjVphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubj\)}(h dport_devh]h dport_dev}(hjcphhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjpubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjoubj{)}(h int port_idh](j3)}(hinth]hint}(hj|phhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjxpubjE)}(h h]h }(hjphhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjxpubj\)}(hport_idh]hport_id}(hjphhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjxpubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjoubj{)}(hresource_size_t rcrbh](h)}(hhh]j\)}(hresource_size_th]hresource_size_t}(hjphhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjpubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjpmodnameN classnameNjj)}j]j]oc.devm_cxl_add_rch_dportasbuh1hhjpubjE)}(h h]h }(hjphhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjpubj\)}(hrcrbh]hrcrb}(hjphhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjpubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjoubeh}(h]h ]h"]h$]h&]hhuh1jthjohhhj/ohMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjohhhj/ohMubah}(h]joah ](jjeh"]h$]h&]jj)jhuh1j&hj/ohMhjohhubj)}(hhh]j])}(h-append RCH downstream port data to a cxl_porth]h-append RCH downstream port data to a cxl_port}(hj qhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjqhhubah}(h]h ]h"]h$]h&]uh1jhjohhhj/ohMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj"qjj"qjjjuh1j!hhhj-hNhNubj)}(hX}**Parameters** ``struct cxl_port *port`` the cxl_port that references this dport ``struct device *dport_dev`` firmware or PCI device representing the dport ``int port_id`` identifier for this dport in a decoder's target list ``resource_size_t rcrb`` mandatory location of a Root Complex Register Block **Description** See CXL 3.0 9.11.8 CXL Devices Attached to an RCHh](j])}(h**Parameters**h]j)}(hj,qh]h Parameters}(hj.qhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*qubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj&qubjo)}(hhh](jt)}(hB``struct cxl_port *port`` the cxl_port that references this dport h](jz)}(h``struct cxl_port *port``h]j)}(hjKqh]hstruct cxl_port *port}(hjMqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIqubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjEqubj)}(hhh]j])}(h'the cxl_port that references this dporth]h'the cxl_port that references this dport}(hjdqhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj`qhMhjaqubah}(h]h ]h"]h$]h&]uh1jhjEqubeh}(h]h ]h"]h$]h&]uh1jshj`qhMhjBqubjt)}(hK``struct device *dport_dev`` firmware or PCI device representing the dport h](jz)}(h``struct device *dport_dev``h]j)}(hjqh]hstruct device *dport_dev}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj~qubj)}(hhh]j])}(h-firmware or PCI device representing the dporth]h-firmware or PCI device representing the dport}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjqhMhjqubah}(h]h ]h"]h$]h&]uh1jhj~qubeh}(h]h ]h"]h$]h&]uh1jshjqhMhjBqubjt)}(hE``int port_id`` identifier for this dport in a decoder's target list h](jz)}(h``int port_id``h]j)}(hjqh]h int port_id}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjqubj)}(hhh]j])}(h4identifier for this dport in a decoder's target listh]h6identifier for this dport in a decoder’s target list}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjqhMhjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jshjqhMhjBqubjt)}(hM``resource_size_t rcrb`` mandatory location of a Root Complex Register Block h](jz)}(h``resource_size_t rcrb``h]j)}(hjqh]hresource_size_t rcrb}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjqubj)}(hhh]j])}(h3mandatory location of a Root Complex Register Blockh]h3mandatory location of a Root Complex Register Block}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj rhMhj rubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jshj rhMhjBqubeh}(h]h ]h"]h$]h&]uh1jnhj&qubj])}(h**Description**h]j)}(hj1rh]h Description}(hj3rhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/rubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj&qubj])}(h1See CXL 3.0 9.11.8 CXL Devices Attached to an RCHh]h1See CXL 3.0 9.11.8 CXL Devices Attached to an RCH}(hjGrhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj&qubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_add_ep (C function) c.cxl_add_ephNtauh1jhj-hhhNhNubj")}(hhh](j')}(h?int cxl_add_ep (struct cxl_dport *dport, struct device *ep_dev)h]j-)}(h>int cxl_add_ep(struct cxl_dport *dport, struct device *ep_dev)h](j3)}(hinth]hint}(hjvrhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjrrhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjrhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjrrhhhjrhMubjV)}(h cxl_add_eph]j\)}(h cxl_add_eph]h cxl_add_ep}(hjrhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjrubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjrrhhhjrhMubju)}(h0(struct cxl_dport *dport, struct device *ep_dev)h](j{)}(hstruct cxl_dport *dporth](j)}(hjh]hstruct}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubjE)}(h h]h }(hjrhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjrubh)}(hhh]j\)}(h cxl_dporth]h cxl_dport}(hjrhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjrubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrmodnameN classnameNjj)}j]j)}jjrsb c.cxl_add_epasbuh1hhjrubjE)}(h h]h }(hjrhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjrubj)}(hjh]h*}(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj\)}(hdporth]hdport}(hj shhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjrubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjrubj{)}(hstruct device *ep_devh](j)}(hjh]hstruct}(hj%shhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!subjE)}(h h]h }(hj2shhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj!subh)}(hhh]j\)}(hdeviceh]hdevice}(hjCshhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj@subah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjEsmodnameN classnameNjj)}j]jr c.cxl_add_epasbuh1hhj!subjE)}(h h]h }(hjashhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj!subj)}(hjh]h*}(hjoshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!subj\)}(hep_devh]hep_dev}(hj|shhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj!subeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjrubeh}(h]h ]h"]h$]h&]hhuh1jthjrrhhhjrhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjnrhhhjrhMubah}(h]jirah ](jjeh"]h$]h&]jj)jhuh1j&hjrhMhjkrhhubj)}(hhh]j])}(h)register an endpoint's interest in a porth]h+register an endpoint’s interest in a port}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjshhubah}(h]h ]h"]h$]h&]uh1jhjkrhhhjrhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjsjjsjjjuh1j!hhhj-hNhNubj)}(hX]**Parameters** ``struct cxl_dport *dport`` the dport that routes to **ep_dev** ``struct device *ep_dev`` device representing the endpoint **Description** Intermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h](j])}(h**Parameters**h]j)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM hjsubjo)}(hhh](jt)}(h@``struct cxl_dport *dport`` the dport that routes to **ep_dev** h](jz)}(h``struct cxl_dport *dport``h]j)}(hjsh]hstruct cxl_dport *dport}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM hjsubj)}(hhh]j])}(h#the dport that routes to **ep_dev**h](hthe dport that routes to }(hjthhhNhNubj)}(h **ep_dev**h]hep_dev}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1j\hjshM hjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jshjshM hjsubjt)}(h;``struct device *ep_dev`` device representing the endpoint h](jz)}(h``struct device *ep_dev``h]j)}(hj.th]hstruct device *ep_dev}(hj0thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,tubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM hj(tubj)}(hhh]j])}(h device representing the endpointh]h device representing the endpoint}(hjGthhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjCthM hjDtubah}(h]h ]h"]h$]h&]uh1jhj(tubeh}(h]h ]h"]h$]h&]uh1jshjCthM hjsubeh}(h]h ]h"]h$]h&]uh1jnhjsubj])}(h**Description**h]j)}(hjith]h Description}(hjkthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgtubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM hjsubj])}(hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.h]hIntermediate CXL ports are scanned based on the arrival of endpoints. When those endpoints depart the port can be destroyed once all endpoints that care about that port have been removed.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM hjsubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder_init (C function)c.cxl_decoder_inithNtauh1jhj-hhhNhNubj")}(hhh](j')}(hFint cxl_decoder_init (struct cxl_port *port, struct cxl_decoder *cxld)h]j-)}(hEint cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)h](j3)}(hinth]hint}(hjthhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjthhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjthhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjthhhjthMubjV)}(hcxl_decoder_inith]j\)}(hcxl_decoder_inith]hcxl_decoder_init}(hjthhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjtubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjthhhjthMubju)}(h1(struct cxl_port *port, struct cxl_decoder *cxld)h](j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubjE)}(h h]h }(hjthhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjtubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hj uhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj umodnameN classnameNjj)}j]j)}jjtsbc.cxl_decoder_initasbuh1hhjtubjE)}(h h]h }(hj)uhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjtubj)}(hjh]h*}(hj7uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj\)}(hporth]hport}(hjDuhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjtubj{)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hj]uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYuubjE)}(h h]h }(hjjuhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjYuubh)}(hhh]j\)}(h cxl_decoderh]h cxl_decoder}(hj{uhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjxuubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}umodnameN classnameNjj)}j]j%uc.cxl_decoder_initasbuh1hhjYuubjE)}(h h]h }(hjuhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjYuubj)}(hjh]h*}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYuubj\)}(hcxldh]hcxld}(hjuhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjYuubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjtubeh}(h]h ]h"]h$]h&]hhuh1jthjthhhjthMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjthhhjthMubah}(h]jtah ](jjeh"]h$]h&]jj)jhuh1j&hjthMhjthhubj)}(hhh]j])}(h%Common decoder setup / initializationh]h%Common decoder setup / initialization}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjuhhubah}(h]h ]h"]h$]h&]uh1jhjthhhjthMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjujjujjjuh1j!hhhj-hNhNubj)}(hXr**Parameters** ``struct cxl_port *port`` owning port of this decoder ``struct cxl_decoder *cxld`` common decoder properties to initialize **Description** A port may contain one or more decoders. Each of those decoders enable some address space for CXL.mem utilization. A decoder is expected to be configured by the caller before registering via cxl_decoder_add()h](j])}(h**Parameters**h]j)}(hjvh]h Parameters}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjuubjo)}(hhh](jt)}(h6``struct cxl_port *port`` owning port of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hjvh]hstruct cxl_port *port}(hj!vhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjvubj)}(hhh]j])}(howning port of this decoderh]howning port of this decoder}(hj8vhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj4vhMhj5vubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jshj4vhMhjvubjt)}(hE``struct cxl_decoder *cxld`` common decoder properties to initialize h](jz)}(h``struct cxl_decoder *cxld``h]j)}(hjXvh]hstruct cxl_decoder *cxld}(hjZvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVvubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjRvubj)}(hhh]j])}(h'common decoder properties to initializeh]h'common decoder properties to initialize}(hjqvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjmvhMhjnvubah}(h]h ]h"]h$]h&]uh1jhjRvubeh}(h]h ]h"]h$]h&]uh1jshjmvhMhjvubeh}(h]h ]h"]h$]h&]uh1jnhjuubj])}(h**Description**h]j)}(hjvh]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjuubj])}(hA port may contain one or more decoders. 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A decoder is expected to be configured by the caller before registering via cxl_decoder_add()}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#cxl_root_decoder_alloc (C function)c.cxl_root_decoder_allochNtauh1jhj-hhhNhNubj")}(hhh](j')}(hastruct cxl_root_decoder * cxl_root_decoder_alloc (struct cxl_port *port, unsigned int nr_targets)h]j-)}(h_struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets)h](j)}(hjh]hstruct}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjvhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjvhhhjvhMubh)}(hhh]j\)}(hcxl_root_decoderh]hcxl_root_decoder}(hjvhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjvubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjvmodnameN classnameNjj)}j]j)}jcxl_root_decoder_allocsbc.cxl_root_decoder_allocasbuh1hhjvhhhjvhMubjE)}(h h]h }(hjwhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjvhhhjvhMubj)}(hjh]h*}(hj&whhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvhhhjvhMubjV)}(hcxl_root_decoder_alloch]j\)}(hjwh]hcxl_root_decoder_alloc}(hj7whhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj3wubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjvhhhjvhMubju)}(h0(struct cxl_port *port, unsigned int nr_targets)h](j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjRwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNwubjE)}(h h]h }(hj_whhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjNwubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjpwhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjmwubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjrwmodnameN classnameNjj)}j]jwc.cxl_root_decoder_allocasbuh1hhjNwubjE)}(h h]h }(hjwhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjNwubj)}(hjh]h*}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNwubj\)}(hporth]hport}(hjwhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjNwubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjJwubj{)}(hunsigned int nr_targetsh](j3)}(hunsignedh]hunsigned}(hjwhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjwubjE)}(h h]h }(hjwhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjwubj3)}(hinth]hint}(hjwhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjwubjE)}(h h]h }(hjwhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjwubj\)}(h nr_targetsh]h nr_targets}(hjwhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjwubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjJwubeh}(h]h ]h"]h$]h&]hhuh1jthjvhhhjvhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjvhhhjvhMubah}(h]jvah ](jjeh"]h$]h&]jj)jhuh1j&hjvhMhjvhhubj)}(hhh]j])}(hAllocate a root level decoderh]hAllocate a root level decoder}(hj$xhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj!xhhubah}(h]h ]h"]h$]h&]uh1jhjvhhhjvhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjhjgzhhubah}(h]h ]h"]h$]h&]uh1jhjyhhhj+yhMHubeh}(h]h ](jfunctioneh"]h$]h&]jjjjzjjzjjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_port *port`` owning CXL switch port of this decoder ``unsigned int nr_targets`` max number of dynamically addressable downstream targets **Return** A new cxl decoder to be registered by cxl_decoder_add(). A 'switch' decoder is any decoder that can be enumerated by PCIe topology and the HDM Decoder Capability. This includes the decoders that sit between Switch Upstream Ports / Switch Downstream Ports and Host Bridges / Root Ports.h](j])}(h**Parameters**h]j)}(hjzh]h Parameters}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMBhjzubjo)}(hhh](jt)}(hA``struct cxl_port *port`` owning CXL switch port of this decoder h](jz)}(h``struct cxl_port *port``h]j)}(hjzh]hstruct cxl_port *port}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM?hjzubj)}(hhh]j])}(h&owning CXL switch port of this decoderh]h&owning CXL switch port of this decoder}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjzhM?hjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshjzhM?hjzubjt)}(hU``unsigned int nr_targets`` max number of dynamically addressable downstream targets h](jz)}(h``unsigned int nr_targets``h]j)}(hjzh]hunsigned int nr_targets}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM@hjzubj)}(hhh]j])}(h8max number of dynamically addressable downstream targetsh]h8max number of dynamically addressable downstream targets}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjzhM@hjzubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshjzhM@hjzubeh}(h]h ]h"]h$]h&]uh1jnhjzubj])}(h **Return**h]j)}(hj{h]hReturn}(hj!{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMBhjzubj])}(hXA new cxl decoder to be registered by cxl_decoder_add(). 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reftargetj{modnameN classnameNjj)}j]j)}jcxl_endpoint_decoder_allocsbc.cxl_endpoint_decoder_allocasbuh1hhj`{hhhjq{hMhubjE)}(h h]h }(hj{hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj`{hhhjq{hMhubj)}(hjh]h*}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`{hhhjq{hMhubjV)}(hcxl_endpoint_decoder_alloch]j\)}(hj{h]hcxl_endpoint_decoder_alloc}(hj{hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj{ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj`{hhhjq{hMhubju)}(h(struct cxl_port *port)h]j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubjE)}(h h]h }(hj{hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj{ubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hj{hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj{modnameN classnameNjj)}j]j{c.cxl_endpoint_decoder_allocasbuh1hhj{ubjE)}(h h]h }(hj|hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj{ubj)}(hjh]h*}(hj(|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj\)}(hporth]hport}(hj5|hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj{ubah}(h]h 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cxl_decoder_add_locked (struct cxl_decoder *cxld, int *target_map)h]j-)}(hEint cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map)h](j3)}(hinth]hint}(hj }hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj}hhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hj/}hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj}hhhj.}hMubjV)}(hcxl_decoder_add_lockedh]j\)}(hcxl_decoder_add_lockedh]hcxl_decoder_add_locked}(hjA}hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj=}ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj}hhhj.}hMubju)}(h+(struct cxl_decoder *cxld, int *target_map)h](j{)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hj]}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY}ubjE)}(h h]h }(hjj}hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjY}ubh)}(hhh]j\)}(h cxl_decoderh]h cxl_decoder}(hj{}hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjx}ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj}}modnameN classnameNjj)}j]j)}jjC}sbc.cxl_decoder_add_lockedasbuh1hhjY}ubjE)}(h h]h }(hj}hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjY}ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY}ubj\)}(hcxldh]hcxld}(hj}hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjY}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjU}ubj{)}(hint *target_maph](j3)}(hinth]hint}(hj}hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj}ubjE)}(h h]h }(hj}hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj}ubj)}(hjh]h*}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj\)}(h target_maph]h target_map}(hj}hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjU}ubeh}(h]h ]h"]h$]h&]hhuh1jthj}hhhj.}hMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj}hhhj.}hMubah}(h]j}ah ](jjeh"]h$]h&]jj)jhuh1j&hj.}hMhj}hhubj)}(hhh]j])}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hj"~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj~hhubah}(h]h ]h"]h$]h&]uh1jhj}hhhj.}hMubeh}(h]h ](jfunctioneh"]h$]h&]jjjj:~jj:~jjjuh1j!hhhj-hNhNubj)}(hX **Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() ``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. **Description** Certain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely). This is the locked variant of cxl_decoder_add(). **Context** Process context. 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These numbers should correspond with the port number in the PCIe Link Capabilities structure. h](jz)}(h``int *target_map``h]j)}(hj~h]hint *target_map}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj~ubj)}(hhh]j])}(hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jshj~hMhjZ~ubeh}(h]h ]h"]h$]h&]uh1jnhj>~ubj])}(h**Description**h]j)}(hj~h]h Description}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubj])}(hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).h]hCertain types of decoders may not have any targets. The main example of this is an endpoint device. A more awkward example is a hostbridge whose root ports get hot added (technically possible, though unlikely).}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubj])}(h0This is the locked variant of cxl_decoder_add().h]h0This is the locked variant of cxl_decoder_add().}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubj])}(h **Context**h]j)}(hjh]hContext}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubj])}(hWProcess context. Expects the device lock of the port that owns the **cxld** to be held.h](hCProcess context. Expects the device lock of the port that owns the }(hj$hhhNhNubj)}(h**cxld**h]hcxld}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh to be held.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubj])}(h **Return**h]j)}(hjGh]hReturn}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj>~ubjo)}(hhh]jt)}(hNNegative error code if the decoder wasn't properly configured; else returns 0.h](jz)}(hCNegative error code if the decoder wasn't properly configured; elseh]hENegative error code if the decoder wasn’t properly configured; else}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj`ubj)}(hhh]j])}(h returns 0.h]h returns 0.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjsubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jshjrhMhj]ubah}(h]h ]h"]h$]h&]uh1jnhj>~ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_decoder_add (C function)c.cxl_decoder_addhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h?int cxl_decoder_add (struct cxl_decoder *cxld, int *target_map)h]j-)}(h>int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(hcxl_decoder_addh]j\)}(hcxl_decoder_addh]hcxl_decoder_add}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubju)}(h+(struct cxl_decoder *cxld, int *target_map)h](j{)}(hstruct cxl_decoder *cxldh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(h cxl_decoderh]h cxl_decoder}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_decoder_addasbuh1hhjubjE)}(h h]h }(hj2hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hcxldh]hcxld}(hjMhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(hint *target_maph](j3)}(hinth]hint}(hjfhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjbubjE)}(h h]h }(hjthhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjbubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj\)}(h target_maph]h target_map}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjbubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubeh}(h]h ]h"]h$]h&]hhuh1jthjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(hAdd a decoder with targetsh]hAdd a decoder with targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjрjjрjjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() ``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. **Description** This is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked(). **Context** Process context. Takes and releases the device lock of the port that owns the **cxld**.h](j])}(h**Parameters**h]j)}(hjۀh]h Parameters}(hj݀hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjـubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjՀubjo)}(hhh](jt)}(hU``struct cxl_decoder *cxld`` The cxl decoder allocated by cxl__decoder_alloc() h](jz)}(h``struct cxl_decoder *cxld``h]j)}(hjh]hstruct cxl_decoder *cxld}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(h7The cxl decoder allocated by cxl__decoder_alloc()h]h7The cxl decoder allocated by cxl__decoder_alloc()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h``int *target_map`` A list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure. h](jz)}(h``int *target_map``h]j)}(hj3h]hint *target_map}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhj-ubj)}(hhh]j])}(hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.h]hA list of downstream ports that this decoder can direct memory traffic to. These numbers should correspond with the port number in the PCIe Link Capabilities structure.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjIubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jshjHhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjՀubj])}(h**Description**h]j)}(hjoh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjՀubj])}(hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().h]hWThis is the unlocked variant of cxl_decoder_add_locked(). See cxl_decoder_add_locked().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjՀubj])}(h **Context**h]j)}(hjh]hContext}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjՀubj])}(hWProcess context. Takes and releases the device lock of the port that owns the **cxld**.h](hNProcess context. Takes and releases the device lock of the port that owns the }(hjhhhNhNubj)}(h**cxld**h]hcxld}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjՀubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j"__cxl_driver_register (C function)c.__cxl_driver_registerhNtauh1jhj-hhhNhNubj")}(hhh](j')}(haint __cxl_driver_register (struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h]j-)}(h`int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(h__cxl_driver_registerh]j\)}(h__cxl_driver_registerh]h__cxl_driver_register}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubju)}(hG(struct cxl_driver *cxl_drv, struct module *owner, const char *modname)h](j{)}(hstruct cxl_driver *cxl_drvh](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubjE)}(h h]h }(hj7hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj&ubh)}(hhh]j\)}(h cxl_driverh]h cxl_driver}(hjHhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjEubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjJmodnameN classnameNjj)}j]j)}jjsbc.__cxl_driver_registerasbuh1hhj&ubjE)}(h h]h }(hjhhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj&ubj)}(hjh]h*}(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj\)}(hcxl_drvh]hcxl_drv}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj"ubj{)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jdc.__cxl_driver_registerasbuh1hhjubjE)}(h h]h }(hj؂hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hownerh]howner}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj"ubj{)}(hconst char *modnameh](j)}(hjSh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj3)}(hcharh]hchar}(hj'hhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjubjE)}(h h]h }(hj5hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hmodnameh]hmodname}(hjPhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj"ubeh}(h]h ]h"]h$]h&]hhuh1jthjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(h!register a driver for the cxl bush]h!register a driver for the cxl bus}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_driver *cxl_drv`` cxl driver structure to attach ``struct module *owner`` owning module/driver ``const char *modname`` KBUILD_MODNAME for parent driverh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjubjo)}(hhh](jt)}(h>``struct cxl_driver *cxl_drv`` cxl driver structure to attach h](jz)}(h``struct cxl_driver *cxl_drv``h]j)}(hjh]hstruct cxl_driver *cxl_drv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjubj)}(hhh]j])}(hcxl driver structure to attachh]hcxl driver structure to attach}(hjԃhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjЃhMhjуubah}(h]h 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./drivers/cxl/core/port.chMhjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jshjBhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j.cxl_endpoint_get_perf_coordinates (C function)#c.cxl_endpoint_get_perf_coordinateshNtauh1jhj-hhhNhNubj")}(hhh](j')}(h^int cxl_endpoint_get_perf_coordinates (struct cxl_port *port, struct access_coordinate *coord)h]j-)}(h]int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(h!cxl_endpoint_get_perf_coordinatesh]j\)}(h!cxl_endpoint_get_perf_coordinatesh]h!cxl_endpoint_get_perf_coordinates}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubju)}(h8(struct cxl_port *port, struct access_coordinate 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]jQah"]h$]h&]uh1jDhj2ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubj\)}(hcoordh]hcoord}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj2ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubeh}(h]h ]h"]h$]h&]hhuh1jthjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jzah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhj|hhubj)}(hhh]j])}(h9Retrieve performance numbers stored in dports of CXL pathh]h9Retrieve performance numbers stored in dports of CXL path}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM{hjhhubah}(h]h ]h"]h$]h&]uh1jhj|hhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjυjjυjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_port *port`` endpoint cxl_port ``struct access_coordinate *coord`` output performance data **Return** errno on failure, 0 on success.h](j])}(h**Parameters**h]j)}(hjمh]h Parameters}(hjۅhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjׅubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjӅubjo)}(hhh](jt)}(h,``struct cxl_port *port`` endpoint cxl_port h](jz)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM}hjubj)}(hhh]j])}(hendpoint cxl_porth]hendpoint cxl_port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj hM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj hM}hjubjt)}(h<``struct access_coordinate *coord`` output performance data h](jz)}(h#``struct access_coordinate *coord``h]j)}(hj1h]hstruct access_coordinate *coord}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jyhf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chM~hj+ubj)}(hhh]j])}(houtput performance datah]houtput performance data}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjFhM~hjGubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jshjFhM~hjubeh}(h]h ]h"]h$]h&]uh1jnhjӅubj])}(h **Return**h]j)}(hjlh]hReturn}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjӅubj])}(herrno on failure, 0 on success.h]herrno on failure, 0 on success.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:448: ./drivers/cxl/core/port.chMhjӅubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj])}(hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.h]hCompute Express Link protocols are layered on top of PCIe. CXL core provides a set of helpers for CXL interactions which occur via PCIe.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:451: ./drivers/cxl/core/pci.chKhj-hhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j+devm_cxl_port_enumerate_dports (C function) c.devm_cxl_port_enumerate_dportshNtauh1jhj-hhhNhNubj")}(hhh](j')}(h:int devm_cxl_port_enumerate_dports (struct cxl_port *port)h]j-)}(h9int devm_cxl_port_enumerate_dports(struct cxl_port *port)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKMubjE)}(h h]h }(hjφhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjΆhKMubjV)}(hdevm_cxl_port_enumerate_dportsh]j\)}(hdevm_cxl_port_enumerate_dportsh]hdevm_cxl_port_enumerate_dports}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj݆ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjΆhKMubju)}(h(struct cxl_port *port)h]j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hj hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb c.devm_cxl_port_enumerate_dportsasbuh1hhjubjE)}(h h]h }(hj;hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hporth]hport}(hjVhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubah}(h]h ]h"]h$]h&]hhuh1jthjhhhjΆhKMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjΆhKMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjΆhKMhjhhubj)}(hhh]j])}(h/enumerate downstream ports of the upstream porth]h/enumerate downstream ports of the upstream port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKGhj}hhubah}(h]h ]h"]h$]h&]uh1jhjhhhjΆhKMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_port *port`` cxl_port whose ->uport_dev is the upstream of dports to be enumerated **Description** Returns a positive number of dports enumerated or a negative error code.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKKhjubjo)}(hhh]jt)}(h```struct cxl_port *port`` cxl_port whose ->uport_dev is the upstream of dports to be enumerated h](jz)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjÇhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKHhjubj)}(hhh]j])}(hEcxl_port whose ->uport_dev is the upstream of dports to be enumeratedh]hEcxl_port whose ->uport_dev is the upstream of dports to be enumerated}(hjڇhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjևhKHhjׇubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjևhKHhjubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKJhjubj])}(hHReturns a positive number of dports enumerated or a negative error code.h]hHReturns a positive number of dports enumerated or a negative error code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chKJhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_hdm_decode_init (C function)c.cxl_hdm_decode_inithNtauh1jhj-hhhNhNubj")}(hhh](j')}(hsint cxl_hdm_decode_init (struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h]j-)}(hrint cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j3)}(hinth]hint}(hjAhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj=hhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMubjE)}(h h]h }(hjPhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj=hhhjOhMubjV)}(hcxl_hdm_decode_inith]j\)}(hcxl_hdm_decode_inith]hcxl_hdm_decode_init}(hjbhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj^ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj=hhhjOhMubju)}(h[(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info)h](j{)}(hstruct cxl_dev_state *cxldsh](j)}(hjh]hstruct}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjzubh)}(hhh]j\)}(h cxl_dev_stateh]h cxl_dev_state}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjdsbc.cxl_hdm_decode_initasbuh1hhjzubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjzubj)}(hjh]h*}(hjʈhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubj\)}(hcxldsh]hcxlds}(hj׈hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjzubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjvubj{)}(hstruct cxl_hdm *cxlhdmh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hcxl_hdmh]hcxl_hdm}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_hdm_decode_initasbuh1hhjubjE)}(h h]h }(hj,hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hcxlhdmh]hcxlhdm}(hjGhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjvubj{)}(h$struct cxl_endpoint_dvsec_info *infoh](j)}(hjh]hstruct}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubjE)}(h h]h }(hjmhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj\ubh)}(hhh]j\)}(hcxl_endpoint_dvsec_infoh]hcxl_endpoint_dvsec_info}(hj~hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj{ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jc.cxl_hdm_decode_initasbuh1hhj\ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj\ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj\)}(hinfoh]hinfo}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjvubeh}(h]h ]h"]h$]h&]hhuh1jthj=hhhjOhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj9hhhjOhMubah}(h]j4ah ](jjeh"]h$]h&]jj)jhuh1j&hjOhMhj6hhubj)}(hhh]j])}(h#Setup HDM decoding for the endpointh]h#Setup HDM decoding for the endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjމhhubah}(h]h ]h"]h$]h&]uh1jhj6hhhjOhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhj-hNhNubj)}(hX**Parameters** ``struct cxl_dev_state *cxlds`` Device state ``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability ``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info **Description** Try to enable the endpoint's HDM Decoder Capabilityh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubjo)}(hhh](jt)}(h-``struct cxl_dev_state *cxlds`` Device state h](jz)}(h``struct cxl_dev_state *cxlds``h]j)}(hj"h]hstruct cxl_dev_state *cxlds}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h Device stateh]h Device state}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj7hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj7hMhjubjt)}(h9``struct cxl_hdm *cxlhdm`` Mapped HDM decoder Capability h](jz)}(h``struct cxl_hdm *cxlhdm``h]j)}(hj[h]hstruct cxl_hdm *cxlhdm}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjUubj)}(hhh]j])}(hMapped HDM decoder Capabilityh]hMapped HDM decoder Capability}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjphMhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jshjphMhjubjt)}(hK``struct cxl_endpoint_dvsec_info *info`` Cached DVSEC range registers info h](jz)}(h(``struct cxl_endpoint_dvsec_info *info``h]j)}(hjh]h$struct cxl_endpoint_dvsec_info *info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h!Cached DVSEC range registers infoh]h!Cached DVSEC range registers info}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjϊh]h Description}(hjъhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj͊ubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubj])}(h3Try to enable the endpoint's HDM Decoder Capabilityh]h5Try to enable the endpoint’s HDM Decoder Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jread_cdat_data (C function)c.read_cdat_datahNtauh1jhj-hhhNhNubj")}(hhh](j')}(h+void read_cdat_data (struct cxl_port *port)h]j-)}(h*void read_cdat_data(struct cxl_port *port)h](j3)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMFubjE)}(h h]h }(hj#hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhj"hMFubjV)}(hread_cdat_datah]j\)}(hread_cdat_datah]hread_cdat_data}(hj5hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj1ubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhj"hMFubju)}(h(struct cxl_port *port)h]j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubjE)}(h h]h }(hj^hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjMubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjohhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjlubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjqmodnameN classnameNjj)}j]j)}jj7sbc.read_cdat_dataasbuh1hhjMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjMubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubj\)}(hporth]hport}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjMubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjIubah}(h]h ]h"]h$]h&]hhuh1jthjhhhj"hMFubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hj hhhj"hMFubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hj"hMFhj hhubj)}(hhh]j])}(hRead the CDAT data on this porth]hRead the CDAT data on this port}(hjԋhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMAhjыhhubah}(h]h ]h"]h$]h&]uh1jhj hhhj"hMFubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_port *port`` Port to read data from **Description** This call will sleep waiting for responses from the DOE mailbox.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMEhjubjo)}(hhh]jt)}(h1``struct cxl_port *port`` Port to read data from h](jz)}(h``struct cxl_port *port``h]j)}(hjh]hstruct cxl_port *port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMBhjubj)}(hhh]j])}(hPort to read data fromh]hPort to read data from}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj*hMBhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj*hMBhj ubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjPh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMDhjubj])}(h@This call will sleep waiting for responses from the DOE mailbox.h]h@This call will sleep waiting for responses from the DOE mailbox.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j)cxl_dport_init_ras_reporting (C function)c.cxl_dport_init_ras_reportinghNtauh1jhj-hhhNhNubj")}(hhh](j')}(hPvoid cxl_dport_init_ras_reporting (struct cxl_dport *dport, struct device *host)h]j-)}(hOvoid cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)h](j3)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(hcxl_dport_init_ras_reportingh]j\)}(hcxl_dport_init_ras_reportingh]hcxl_dport_init_ras_reporting}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubju)}(h.(struct cxl_dport *dport, struct device *host)h](j{)}(hstruct cxl_dport *dporth](j)}(hjh]hstruct}(hjҌhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΌubjE)}(h h]h }(hjߌhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjΌubh)}(hhh]j\)}(h cxl_dporth]h cxl_dport}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_dport_init_ras_reportingasbuh1hhjΌubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjΌubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΌubj\)}(hdporth]hdport}(hj+hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjΌubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjʌubj{)}(hstruct device *hosth](j)}(hjh]hstruct}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubjE)}(h h]h }(hjQhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj@ubh)}(hhh]j\)}(hdeviceh]hdevice}(hjbhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj_ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjdmodnameN classnameNjj)}j]j c.cxl_dport_init_ras_reportingasbuh1hhj@ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj@ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubj\)}(hhosth]hhost}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjʌubeh}(h]h ]h"]h$]h&]hhuh1jthjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(h"Setup CXL RAS report on this dporth]h"Setup CXL RAS report on this dport}(hjōhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjݍjjݍjjjuh1j!hhhj-hNhNubj)}(h**Parameters** ``struct cxl_dport *dport`` the cxl_dport that needs to be initialized ``struct device *host`` host device for devm operationsh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubjo)}(hhh](jt)}(hG``struct cxl_dport *dport`` the cxl_dport that needs to be initialized h](jz)}(h``struct cxl_dport *dport``h]j)}(hjh]hstruct cxl_dport *dport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h*the cxl_dport that needs to be initializedh]h*the cxl_dport that needs to be initialized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubjt)}(h7``struct device *host`` host device for devm operationsh](jz)}(h``struct device *host``h]j)}(hj?h]hstruct device *host}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhj9ubj)}(hhh]j])}(hhost device for devm operationsh]hhost device for devm operations}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jshjThMhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j cxl_pci_get_latency (C function)c.cxl_pci_get_latencyhNtauh1jhj-hhhNhNubj")}(hhh](j')}(h/long cxl_pci_get_latency (struct pci_dev *pdev)h]j-)}(h.long cxl_pci_get_latency(struct pci_dev *pdev)h](j3)}(hlongh]hlong}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhMubjV)}(hcxl_pci_get_latencyh]j\)}(hcxl_pci_get_latencyh]hcxl_pci_get_latency}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhMubju)}(h(struct pci_dev *pdev)h]j{)}(hstruct pci_dev *pdevh](j)}(hjh]hstruct}(hj֎hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҎubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjҎubh)}(hhh]j\)}(hpci_devh]hpci_dev}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.cxl_pci_get_latencyasbuh1hhjҎubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjҎubj)}(hjh]h*}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҎubj\)}(hpdevh]hpdev}(hj/hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjҎubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjΎubah}(h]h ]h"]h$]h&]hhuh1jthjhhhjhMubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhMubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhMhjhhubj)}(hhh]j])}(h,calculate the link latency for the PCIe linkh]h,calculate the link latency for the PCIe link}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjVhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhMubeh}(h]h ](jfunctioneh"]h$]h&]jjjjqjjqjjjuh1j!hhhj-hNhNubj)}(hX7**Parameters** ``struct pci_dev *pdev`` PCI device **Return** calculated latency or 0 for no latency **Description** CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h](j])}(h**Parameters**h]j)}(hj{h]h Parameters}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjuubjo)}(hhh]jt)}(h$``struct pci_dev *pdev`` PCI device h](jz)}(h``struct pci_dev *pdev``h]j)}(hjh]hstruct pci_dev *pdev}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhe/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjubj)}(hhh]j])}(h PCI deviceh]h PCI device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubah}(h]h ]h"]h$]h&]uh1jnhjuubj])}(h **Return**h]j)}(hjՏh]hReturn}(hj׏hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӏubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjuubj])}(h&calculated latency or 0 for no latencyh]h&calculated latency or 0 for no latency}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjuubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjuubj])}(hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.h]hXCXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency LinkProgationLatency is negligible, so 0 will be used RetimerLatency is assumed to be negligible and 0 will be used FlitLatency = FlitSize / LinkBandwidth FlitSize is defined by spec. CXL rev3.0 4.2.1. 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used. The FlitLatency is converted to picoseconds.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\he/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:454: ./drivers/cxl/core/pci.chMhjuubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj-hhhNhNubj])}(hXIThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL 'bridge' device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus' device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.h]hXQThe core CXL PMEM infrastructure supports persistent memory provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL ‘bridge’ device is added at the root of a CXL device topology if platform firmware advertises at least one persistent memory capable CXL window. That root-level bridge corresponds to a LIBNVDIMM ‘bus’ device. Then for each cxl_memdev in the CXL device topology a bridge device is added to host a LIBNVDIMM dimm object. When these bridges are registered native LIBNVDIMM uapis are translated to CXL operations, for example, namespace label access commands.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:457: ./drivers/cxl/core/pmem.chK hj-hhubj])}(hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.h]hXvCXL device capabilities are enumerated by PCI DVSEC (Designated Vendor-specific) and / or descriptors provided by platform firmware. They can be defined as a set like the device and component registers mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and Extended Capabilities, or they can be individual capabilities appended to bridged and endpoint devices.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:460: ./drivers/cxl/core/regs.chKhj-hhubj])}(hVProvide common infrastructure for enumerating and mapping these discrete capabilities.h]hVProvide common infrastructure for enumerating and mapping these discrete capabilities.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:460: ./drivers/cxl/core/regs.chKhj-hhubj])}(hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.h]hXCore implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The implementation is used by the cxl_pci driver to initialize the device and implement the cxl_mem.h IOCTL UAPI. It also implements the backend of the cxl_pmem_ctl() transport for LIBNVDIMM.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hf/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:463: ./drivers/cxl/core/mbox.chKhj-hhubeh}(h]cxl-coreah ]h"]cxl coreah$]h&]uh1jGhj/hhhhhMWubjH)}(hhh](jM)}(h CXL Regionsh]h CXL Regions}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjlhhhhhM}ubj])}(hX<CXL Regions represent mapped memory capacity in system physical address space. Whereas the CXL Root Decoders identify the bounds of potential CXL Memory ranges, Regions represent the active mapped capacity by the HDM Decoder Capability structures throughout the Host Bridges, Switches, and Endpoints in the topology.h]hX<CXL Regions represent mapped memory capacity in system physical address space. Whereas the CXL Root Decoders identify the bounds of potential CXL Memory ranges, Regions represent the active mapped capacity by the HDM Decoder Capability structures throughout the Host Bridges, Switches, and Endpoints in the topology.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:468: ./drivers/cxl/core/region.chKhjlhhubj])}(hRegion configuration has ordering constraints. UUID may be set at any time but is only visible for persistent regions. 1. Interleave granularity 2. Interleave size 3. Decoder targetsh]hRegion configuration has ordering constraints. UUID may be set at any time but is only visible for persistent regions. 1. Interleave granularity 2. Interleave size 3. Decoder targets}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:468: ./drivers/cxl/core/region.chKhjlhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j#cxl_port_attach_region (C function)c.cxl_port_attach_regionhNtauh1jhjlhhhNhNubj")}(hhh](j')}(hxint cxl_port_attach_region (struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h]j-)}(hwint cxl_port_attach_region(struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM5ubjE)}(h h]h }(hjÐhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhM5ubjV)}(hcxl_port_attach_regionh]j\)}(hcxl_port_attach_regionh]hcxl_port_attach_region}(hjՐhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjѐubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhM5ubju)}(h](struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos)h](j{)}(hstruct cxl_port *porth](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hcxl_porth]hcxl_port}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjאsbc.cxl_port_attach_regionasbuh1hhjubjE)}(h h]h }(hj/hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hporth]hport}(hjJhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubjE)}(h h]h }(hjphhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj_ubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj~ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j+c.cxl_port_attach_regionasbuh1hhj_ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj_ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj\)}(hcxlrh]hcxlr}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hjӑhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϑubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjϑubh)}(hhh]j\)}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j+c.cxl_port_attach_regionasbuh1hhjϑubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjϑubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϑubj\)}(hcxledh]hcxled}(hj*hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjϑubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(hint posh](j3)}(hinth]hint}(hjChhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hj?ubjE)}(h h]h }(hjQhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj?ubj\)}(hposh]hpos}(hj_hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj?ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubeh}(h]h ]h"]h$]h&]hhuh1jthjhhhjhM5ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhM5ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhM5hjhhubj)}(hhh]j])}(h/track a region's interest in a port by endpointh]h1track a region’s interest in a port by endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM5ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhjlhNhNubj)}(hX**Parameters** ``struct cxl_port *port`` port to add a new region reference 'struct cxl_region_ref' ``struct cxl_region *cxlr`` region to attach to **port** ``struct cxl_endpoint_decoder *cxled`` endpoint decoder used to create or further pin a region reference ``int pos`` interleave position of **cxled** in **cxlr** **Description** The attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists. The steps are: - validate that there are no other regions with a higher HPA already associated with **port** - establish a region reference if one is not already present - additionally allocate a decoder instance that will host **cxlr** on **port** - pin the region reference by the endpoint - account for how many entries in **port**'s target list are needed to cover all of the added endpoints.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM"hjubjo)}(hhh](jt)}(hU``struct cxl_port *port`` port to add a new region reference 'struct cxl_region_ref' h](jz)}(h``struct cxl_port *port``h]j)}(hjʒh]hstruct cxl_port *port}(hj̒hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȒubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjĒubj)}(hhh]j])}(h:port to add a new region reference 'struct cxl_region_ref'h]h>port to add a new region reference ‘struct cxl_region_ref’}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjߒhMhjubah}(h]h ]h"]h$]h&]uh1jhjĒubeh}(h]h ]h"]h$]h&]uh1jshjߒhMhjubjt)}(h9``struct cxl_region *cxlr`` region to attach to **port** h](jz)}(h``struct cxl_region *cxlr``h]j)}(hjh]hstruct cxl_region *cxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(hregion to attach to **port**h](hregion to attach to }(hjhhhNhNubj)}(h**port**h]hport}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM hjubjt)}(hi``struct cxl_endpoint_decoder *cxled`` endpoint decoder used to create or further pin a region reference h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjJh]h"struct cxl_endpoint_decoder *cxled}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM!hjDubj)}(hhh]j])}(hAendpoint decoder used to create or further pin a region referenceh]hAendpoint decoder used to create or further pin a region reference}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj_hM!hj`ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jshj_hM!hjubjt)}(h9``int pos`` interleave position of **cxled** in **cxlr** h](jz)}(h ``int pos``h]j)}(hjh]hint pos}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM"hj}ubj)}(hhh]j])}(h,interleave position of **cxled** in **cxlr**h](hinterleave position of }(hjhhhNhNubj)}(h **cxled**h]hcxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh in }(hjhhhNhNubj)}(h**cxlr**h]hcxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j\hjhM"hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jshjhM"hjubeh}(h]h ]h"]h$]h&]uh1jnhjubj])}(h**Description**h]j)}(hjޓh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܓubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM$hjubj])}(hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.h]hThe attach event is an opportunity to validate CXL decode setup constraints and record metadata needed for programming HDM decoders, in particular decoder target lists.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM$hjubj])}(hThe steps are:h]hThe steps are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM(hjubj)}(hhh](j)}(h[validate that there are no other regions with a higher HPA already associated with **port**h]j])}(h[validate that there are no other regions with a higher HPA already associated with **port**h](hSvalidate that there are no other regions with a higher HPA already associated with }(hjhhhNhNubj)}(h**port**h]hport}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM*hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hestablish a region reference if one is not already present - additionally allocate a decoder instance that will host **cxlr** on **port** h](j])}(h:establish a region reference if one is not already presenth]h:establish a region reference if one is not already present}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM,hj<ubj)}(hhh]j)}(hMadditionally allocate a decoder instance that will host **cxlr** on **port** h]j])}(hLadditionally allocate a decoder instance that will host **cxlr** on **port**h](h8additionally allocate a decoder instance that will host }(hjVhhhNhNubj)}(h**cxlr**h]hcxlr}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh on }(hjVhhhNhNubj)}(h**port**h]hport}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM.hjRubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]jjuh1jhjhM.hj<ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h(pin the region reference by the endpointh]j])}(hjh]h(pin the region reference by the endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM1hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h]j])}(hfaccount for how many entries in **port**'s target list are needed to cover all of the added endpoints.h](h account for how many entries in }(hjhhhNhNubj)}(h**port**h]hport}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh@’s target list are needed to cover all of the added endpoints.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM2hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhj5hM*hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjlhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j$cxl_calc_interleave_pos (C function)c.cxl_calc_interleave_poshNtauh1jhjlhhhNhNubj")}(hhh](j')}(h@int cxl_calc_interleave_pos (struct cxl_endpoint_decoder *cxled)h]j-)}(h?int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM"ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhM"ubjV)}(hcxl_calc_interleave_posh]j\)}(hcxl_calc_interleave_posh]hcxl_calc_interleave_pos}(hj!hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhM"ubju)}(h$(struct cxl_endpoint_decoder *cxled)h]j{)}(h"struct cxl_endpoint_decoder *cxledh](j)}(hjh]hstruct}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubjE)}(h h]h }(hjJhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj9ubh)}(hhh]j\)}(hcxl_endpoint_decoderh]hcxl_endpoint_decoder}(hj[hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjXubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj]modnameN classnameNjj)}j]j)}jj#sbc.cxl_calc_interleave_posasbuh1hhj9ubjE)}(h h]h }(hj{hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj9ubj)}(hjh]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9ubj\)}(hcxledh]hcxled}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj9ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhj5ubah}(h]h ]h"]h$]h&]hhuh1jthjhhhjhM"ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhM"ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhM"hjhhubj)}(hhh]j])}(h*calculate an endpoint position in a regionh]h*calculate an endpoint position in a region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM"ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjؕjjؕjjjuh1j!hhhjlhNhNubj)}(hX**Parameters** ``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region **Description** The endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation: position = position * parent_ways + parent_pos; ...where **position** is inferred from switch and root decoder target lists. **Return** position >= 0 on success -ENXIO on failureh](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjܕubjo)}(hhh]jt)}(hO``struct cxl_endpoint_decoder *cxled`` endpoint decoder member of given region h](jz)}(h&``struct cxl_endpoint_decoder *cxled``h]j)}(hjh]h"struct cxl_endpoint_decoder *cxled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjubj)}(hhh]j])}(h'endpoint decoder member of given regionh]h'endpoint decoder member of given region}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhMhjubah}(h]h ]h"]h$]h&]uh1jnhjܕubj])}(h**Description**h]j)}(hj<h]h Description}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjܕubj])}(hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:h]hThe endpoint position is calculated by traversing the topology from the endpoint to the root decoder and iteratively applying this calculation:}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjܕubh block_quote)}(h0position = position * parent_ways + parent_pos; h]j])}(h/position = position * parent_ways + parent_pos;h]h/position = position * parent_ways + parent_pos;}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjcubah}(h]h ]h"]h$]h&]uh1jahjuhMhjܕubj])}(hL...where **position** is inferred from switch and root decoder target lists.h](h ...where }(hj|hhhNhNubj)}(h **position**h]hposition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubh7 is inferred from switch and root decoder target lists.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjܕubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjܕubjo)}(hhh]jt)}(h*position >= 0 on success -ENXIO on failureh](jz)}(hposition >= 0 on successh]hposition >= 0 on success}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chMhjubj)}(hhh]j])}(h-ENXIO on failureh]h-ENXIO on failure}(hjΖhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj˖ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjʖhMhjubah}(h]h ]h"]h$]h&]uh1jnhjܕubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjlhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j devm_cxl_add_region (C function)c.devm_cxl_add_regionhNtauh1jhjlhhhNhNubj")}(hhh](j')}(hstruct cxl_region * devm_cxl_add_region (struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h]j-)}(hstruct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM ubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj hhhjhM ubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hj.hhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj+ubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetj0modnameN classnameNjj)}j]j)}jdevm_cxl_add_regionsbc.devm_cxl_add_regionasbuh1hhj hhhjhM ubjE)}(h h]h }(hjOhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj hhhjhM ubj)}(hjh]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj hhhjhM ubjV)}(hdevm_cxl_add_regionh]j\)}(hjLh]hdevm_cxl_add_region}(hjnhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj hhhjhM ubju)}(hb(struct cxl_root_decoder *cxlrd, int id, enum cxl_partition_mode mode, enum cxl_decoder_type type)h](j{)}(hstruct cxl_root_decoder *cxlrdh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hcxl_root_decoderh]hcxl_root_decoder}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jJc.devm_cxl_add_regionasbuh1hhjubjE)}(h h]h }(hjŗhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjӗhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hcxlrdh]hcxlrd}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(hint idh](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj\)}(hidh]hid}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(henum cxl_partition_mode modeh](j)}(henumh]henum}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubjE)}(h h]h }(hj<hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj*ubh)}(hhh]j\)}(hcxl_partition_modeh]hcxl_partition_mode}(hjMhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjJubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjOmodnameN classnameNjj)}j]jJc.devm_cxl_add_regionasbuh1hhj*ubjE)}(h h]h }(hjkhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj*ubj\)}(hmodeh]hmode}(hjyhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hj*ubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubj{)}(henum cxl_decoder_type typeh](j)}(hj0h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(hcxl_decoder_typeh]hcxl_decoder_type}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]jJc.devm_cxl_add_regionasbuh1hhjubjE)}(h h]h }(hjΘhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj\)}(htypeh]htype}(hjܘhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubeh}(h]h ]h"]h$]h&]hhuh1jthj hhhjhM ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhM ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhM hjhhubj)}(hhh]j])}(hAdds a region to a decoderh]hAdds a region to a decoder}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhM ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhjlhNhNubj)}(hXl**Parameters** ``struct cxl_root_decoder *cxlrd`` root decoder ``int id`` memregion id to create, or memregion_free() on failure ``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region ``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) **Description** This is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**. **Return** 0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](j])}(h**Parameters**h]j)}(hj(h]h Parameters}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj"ubjo)}(hhh](jt)}(h0``struct cxl_root_decoder *cxlrd`` root decoder h](jz)}(h"``struct cxl_root_decoder *cxlrd``h]j)}(hjGh]hstruct cxl_root_decoder *cxlrd}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjAubj)}(hhh]j])}(h root decoderh]h root decoder}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj\hM hj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshj\hM hj>ubjt)}(hB``int id`` memregion id to create, or memregion_free() on failure h](jz)}(h ``int id``h]j)}(hjh]hint id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjzubj)}(hhh]j])}(h6memregion id to create, or memregion_free() on failureh]h6memregion id to create, or memregion_free() on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshjhM hj>ubjt)}(hO``enum cxl_partition_mode mode`` mode for the endpoint decoders of this region h](jz)}(h ``enum cxl_partition_mode mode``h]j)}(hjh]henum cxl_partition_mode mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(h-mode for the endpoint decoders of this regionh]h-mode for the endpoint decoders of this region}(hjҙhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjΙhM hjϙubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjΙhM hj>ubjt)}(hd``enum cxl_decoder_type type`` select whether this is an expander or accelerator (type-2 or type-3) h](jz)}(h``enum cxl_decoder_type type``h]j)}(hjh]henum cxl_decoder_type type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hjubj)}(hhh]j])}(hDselect whether this is an expander or accelerator (type-2 or type-3)h]hDselect whether this is an expander or accelerator (type-2 or type-3)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhM hj>ubeh}(h]h ]h"]h$]h&]uh1jnhj"ubj])}(h**Description**h]j)}(hj-h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj"ubj])}(hwThis is the second step of region initialization. Regions exist within an address space which is mapped by a **cxlrd**.h](hmThis is the second step of region initialization. Regions exist within an address space which is mapped by a }(hjChhhNhNubj)}(h **cxlrd**h]hcxlrd}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubh.}(hjChhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj"ubj])}(h **Return**h]j)}(hjfh]hReturn}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj"ubj])}(h0 if the region was added to the **cxlrd**, else returns negative error code. The region will be named "regionZ" where Z is the unique region number.h](h!0 if the region was added to the }(hj|hhhNhNubj)}(h **cxlrd**h]hcxlrd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubho, else returns negative error code. The region will be named “regionZ” where Z is the unique region number.}(hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM hj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjlhhhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j%devm_cxl_add_pmem_region (C function)c.devm_cxl_add_pmem_regionhNtauh1jhjlhhhNhNubj")}(hhh](j')}(h6int devm_cxl_add_pmem_region (struct cxl_region *cxlr)h]j-)}(h5int devm_cxl_add_pmem_region(struct cxl_region *cxlr)h](j3)}(hinth]hint}(hjhhhNhNubah}(h]h ]j?ah"]h$]h&]uh1j2hjhhhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM+ ubjE)}(h h]h }(hj̚hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhj˚hM+ ubjV)}(hdevm_cxl_add_pmem_regionh]j\)}(hdevm_cxl_add_pmem_regionh]hdevm_cxl_add_pmem_region}(hjޚhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjښubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhj˚hM+ ubju)}(h(struct cxl_region *cxlr)h]j{)}(hstruct cxl_region *cxlrh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubh)}(hhh]j\)}(h cxl_regionh]h cxl_region}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ]h"]h$]h&] refdomainjreftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.devm_cxl_add_pmem_regionasbuh1hhjubjE)}(h h]h }(hj8hhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjubj)}(hjh]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj\)}(hcxlrh]hcxlr}(hjShhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubeh}(h]h ]h"]h$]h&]noemphhhuh1jzhjubah}(h]h ]h"]h$]h&]hhuh1jthjhhhj˚hM+ ubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhj˚hM+ ubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hj˚hM+ hjhhubj)}(hhh]j])}(h$add a cxl_region-to-nd_region bridgeh]h$add a cxl_region-to-nd_region bridge}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM& hjzhhubah}(h]h ]h"]h$]h&]uh1jhjhhhj˚hM+ ubeh}(h]h ](jfunctioneh"]h$]h&]jjjjjjjjjuh1j!hhhjlhNhNubj)}(h**Parameters** ``struct cxl_region *cxlr`` parent CXL region for this pmem region bridge device **Return** 0 on success negative error code on failure.h](j])}(h**Parameters**h]j)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM* hjubjo)}(hhh]jt)}(hQ``struct cxl_region *cxlr`` parent CXL region for this pmem region bridge device h](jz)}(h``struct cxl_region *cxlr``h]j)}(hjh]hstruct cxl_region *cxlr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM' hjubj)}(hhh]j])}(h4parent CXL region for this pmem region bridge deviceh]h4parent CXL region for this pmem region bridge device}(hjכhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjӛhM' hjԛubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjӛhM' hjubah}(h]h ]h"]h$]h&]uh1jnhjubj])}(h **Return**h]j)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM) hjubj])}(h,0 on success negative error code on failure.h]h,0 on success negative error code on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hh/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:471: ./drivers/cxl/core/region.chM) hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjlhhhNhNubeh}(h] cxl-regionsah ]h"] cxl regionsah$]h&]uh1jGhj/hhhhhM}ubeh}(h]driver-infrastructureah ]h"]driver infrastructureah$]h&]uh1jGhjIhhhhhM;ubjH)}(hhh](jM)}(hExternal Interfacesh]hExternal Interfaces}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj5hhhhhMubjH)}(hhh](jM)}(hCXL IOCTL Interfaceh]hCXL IOCTL Interface}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjFhhhhhMubj])}(hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.h]hNot all of the commands that the driver supports are available for use by userspace at all times. Userspace can check the result of the QUERY command to determine the live set of commands. Alternatively, it can issue the command and check for failure.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:480: ./include/uapi/linux/cxl_mem.hhK hjFhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_command_info (C struct)c.cxl_command_infohNtauh1jhjFhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhNubj")}(hhh](j')}(hcxl_command_infoh]j-)}(hstruct cxl_command_infoh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|hhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhj|hhhjhKubjV)}(hcxl_command_infoh]j\)}(hjzh]hcxl_command_info}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhj|hhhjhKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjxhhhjhKubah}(h]jrah ](jjeh"]h$]h&]jj)jhuh1j&hjhKhjuhhubj)}(hhh]j])}(h*Command information returned from a query.h]h*Command information returned from a query.}(hjœhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKfhjhhubah}(h]h ]h"]h$]h&]uh1jhjuhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjڜjjڜjjjuh1j!hhhjFhjthNubj)}(hX**Definition**:: struct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; }; **Members** ``id`` ID number for the command. ``flags`` Flags that specify command behavior. CXL_MEM_COMMAND_FLAG_USER_ENABLED The given command id is supported by the driver and is supported by a related opcode on the device. CXL_MEM_COMMAND_FLAG_EXCLUSIVE Requests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space. ``size_in`` Expected input size, or ~0 if variable length. ``size_out`` Expected output size, or ~0 if variable length.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKjhjޜubj)}(hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };h]hXstruct cxl_command_info { __u32 id; __u32 flags; #define CXL_MEM_COMMAND_FLAG_MASK GENMASK(1, 0); #define CXL_MEM_COMMAND_FLAG_ENABLED BIT(0); #define CXL_MEM_COMMAND_FLAG_EXCLUSIVE BIT(1); __u32 size_in; __u32 size_out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKlhjޜubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKvhjޜubjo)}(hhh](jt)}(h"``id`` ID number for the command. h](jz)}(h``id``h]j)}(hj/h]hid}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhhj)ubj)}(hhh]j])}(hID number for the command.h]hID number for the command.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjDhKhhjEubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jshjDhKhhj&ubjt)}(hX``flags`` Flags that specify command behavior. CXL_MEM_COMMAND_FLAG_USER_ENABLED The given command id is supported by the driver and is supported by a related opcode on the device. CXL_MEM_COMMAND_FLAG_EXCLUSIVE Requests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space. h](jz)}(h ``flags``h]j)}(hjhh]hflags}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKuhjbubj)}(hhh](j])}(h$Flags that specify command behavior.h]h$Flags that specify command behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKihj~ubj])}(h!CXL_MEM_COMMAND_FLAG_USER_ENABLEDh]h!CXL_MEM_COMMAND_FLAG_USER_ENABLED}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKkhj~ubj])}(hcThe given command id is supported by the driver and is supported by a related opcode on the device.h]hcThe given command id is supported by the driver and is supported by a related opcode on the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKmhj~ubj])}(hCXL_MEM_COMMAND_FLAG_EXCLUSIVEh]hCXL_MEM_COMMAND_FLAG_EXCLUSIVE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKphj~ubj])}(hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.h]hRequests with the given command id will terminate with EBUSY as the kernel actively owns management of the given resource. For example, the label-storage-area can not be written while the kernel is actively managing that space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKrhj~ubeh}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jshj}hKuhj&ubjt)}(h;``size_in`` Expected input size, or ~0 if variable length. h](jz)}(h ``size_in``h]j)}(hjޝh]hsize_in}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܝubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKwhj؝ubj)}(hhh]j])}(h.Expected input size, or ~0 if variable length.h]h.Expected input size, or ~0 if variable length.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKwhjubah}(h]h ]h"]h$]h&]uh1jhj؝ubeh}(h]h ]h"]h$]h&]uh1jshjhKwhj&ubjt)}(h<``size_out`` Expected output size, or ~0 if variable length.h](jz)}(h ``size_out``h]j)}(hjh]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKwhjubj)}(hhh]j])}(h/Expected output size, or ~0 if variable length.h]h/Expected output size, or ~0 if variable length.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKxhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj,hKwhj&ubeh}(h]h ]h"]h$]h&]uh1jnhjޜubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjFhhhjthNubj])}(h**Description**h]j)}(hjZh]h Description}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhK{hjFhhubj])}(hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.h]hRepresents a single command that is supported by both the driver and the hardware. This is returned as part of an array from the query ioctl. The following would be a command that takes a variable length input and returns 0 bytes of output.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKyhjFhhubjb)}(h_- **id** = 10 - **flags** = CXL_MEM_COMMAND_FLAG_ENABLED - **size_in** = ~0 - **size_out** = 0 h]j)}(hhh](j)}(h **id** = 10h]j])}(hjh](j)}(h**id**h]hid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 10}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhK~hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h(**flags** = CXL_MEM_COMMAND_FLAG_ENABLEDh]j])}(hjh](j)}(h **flags**h]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = CXL_MEM_COMMAND_FLAG_ENABLED}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**size_in** = ~0h]j])}(hjԞh](j)}(h **size_in**h]hsize_in}(hjٞhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj֞ubh = ~0}(hj֞hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjҞubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**size_out** = 0 h]j])}(h**size_out** = 0h](j)}(h **size_out**h]hsize_out}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh = 0}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhjhK~hjubah}(h]h ]h"]h$]h&]uh1jahjhK~hjFhhubj])}(h"See struct cxl_mem_query_commands.h]h"See struct cxl_mem_query_commands.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjFhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!cxl_mem_query_commands (C struct)c.cxl_mem_query_commandshNtauh1jhjFhhhjthNubj")}(hhh](j')}(hcxl_mem_query_commandsh]j-)}(hstruct cxl_mem_query_commandsh](j)}(hjh]hstruct}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKubjE)}(h h]h }(hjahhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjOhhhj`hKubjV)}(hcxl_mem_query_commandsh]j\)}(hjMh]hcxl_mem_query_commands}(hjshhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjoubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjOhhhj`hKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjKhhhj`hKubah}(h]jFah ](jjeh"]h$]h&]jj)jhuh1j&hj`hKhjHhhubj)}(hhh]j])}(hQuery supported commands.h]hQuery supported commands.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjhhubah}(h]h ]h"]h$]h&]uh1jhjHhhhj`hKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j!hhhjFhjthNubj)}(hX5**Definition**:: struct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; }; **Members** ``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. ``rsvd`` Reserved for future use. ``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };h]hwstruct cxl_mem_query_commands { __u32 n_commands; __u32 rsvd; struct cxl_command_info __user commands[]; };}hjҟsbah}(h]h ]h"]h$]h&]hhuh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj])}(h **Members**h]j)}(hjh]hMembers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubjo)}(hhh](jt)}(h``n_commands`` In/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands. h](jz)}(h``n_commands``h]j)}(hjh]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hIn/out parameter. When **n_commands** is > 0, the driver will return min(num_support_commands, n_commands). When **n_commands** is 0, driver will return the number of total supported commands.h](hIn/out parameter. When }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhL is > 0, the driver will return min(num_support_commands, n_commands). When }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhA is 0, driver will return the number of total supported commands.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubjt)}(h"``rsvd`` Reserved for future use. h](jz)}(h``rsvd``h]j)}(hj`h]hrsvd}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjZubj)}(hhh]j])}(hReserved for future use.h]hReserved for future use.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjuhKhjvubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jshjuhKhjubjt)}(h``commands`` Output array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](jz)}(h ``commands``h]j)}(hjh]hcommands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, **n_commands**)h](hwOutput array of supported commands. This array must be allocated by userspace to be at least min(num_support_commands, }(hjhhhNhNubj)}(h**n_commands**h]h n_commands}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjFhhhjthNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjFhhubj])}(hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren't supported by either the driver, or the hardware are not returned in the query.h]hAllow userspace to query the available commands supported by both the driver, and the hardware. Commands that aren’t supported by either the driver, or the hardware are not returned in the query.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjFhhubj])}(h **Examples**h]j)}(hjh]hExamples}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjFhhubjb)}(h- { .n_commands = 0 } // Get number of supported commands - { .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands See struct cxl_command_info. h](j)}(hhh](j)}(h7{ .n_commands = 0 } // Get number of supported commandsh]j])}(hj3h]h7{ .n_commands = 0 } // Get number of supported commands}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hV{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands h]j])}(hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commandsh]hU{ .n_commands = 15, .commands = buf } // Return first 15 (or less) supported commands}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjIubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]jjuh1jhjBhKhj*ubj])}(hSee struct cxl_command_info.h]hSee struct cxl_command_info.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj*ubeh}(h]h ]h"]h$]h&]uh1jahjBhKhjFhhubj)}(hhh]h}(h]h ]h"]h$]h&]entries](jcxl_send_command (C struct)c.cxl_send_commandhNtauh1jhjFhhhjthNubj")}(hhh](j')}(hcxl_send_commandh]j-)}(hstruct cxl_send_commandh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKubjE)}(h h]h }(hjhhhNhNubah}(h]h ]jQah"]h$]h&]uh1jDhjhhhjhKubjV)}(hcxl_send_commandh]j\)}(hjh]hcxl_send_command}(hjhhhNhNubah}(h]h ]jhah"]h$]h&]uh1j[hjubah}(h]h ](jojpeh"]h$]h&]hhuh1jUhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj{uh1j,j|j}hjhhhjhKubah}(h]jah ](jjeh"]h$]h&]jj)jhuh1j&hjhKhjhhubj)}(hhh]j])}(h"Send a command to a memory device.h]h"Send a command to a memory device.}(hjءhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjաhhubah}(h]h ]h"]h$]h&]uh1jhjhhhjhKubeh}(h]h ](jstructeh"]h$]h&]jjjjjjjjjuh1j!hhhjFhjthNubj)}(hX **Definition**:: struct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; }; **Members** ``id`` The command to send to the memory device. This must be one of the commands returned by the query command. ``flags`` Flags for the command (input). ``{unnamed_union}`` anonymous ``raw`` Special fields for raw commands ``raw.opcode`` Opcode passed to hardware when using the RAW command. ``raw.rsvd`` Must be zero. ``rsvd`` Must be zero. ``retval`` Return value from the memory device (output). ``in`` Parameters associated with input payload. ``in.size`` Size of the payload to provide to the device (input). ``in.rsvd`` Must be zero. ``in.payload`` Pointer to memory for payload input, payload is little endian. ``out`` Parameters associated with output payload. ``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. ``out.rsvd`` Must be zero. ``out.payload`` Pointer to memory for payload output, payload is little endian.h](j])}(h**Definition**::h](j)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };h]hXsstruct cxl_send_command { __u32 id; __u32 flags; union { struct { __u16 opcode; __u16 rsvd; } raw; __u32 rsvd; }; __u32 retval; struct { __u32 size; __u32 rsvd; __u64 payload; } in; struct { __u32 size; __u32 rsvd; __u64 payload; } out; };}hjsbah}(h]h ]h"]h$]h&]hhuh1jhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj])}(h **Members**h]j)}(hj&h]hMembers}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubjo)}(hhh](jt)}(hq``id`` The command to send to the memory device. This must be one of the commands returned by the query command. h](jz)}(h``id``h]j)}(hjEh]hid}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj?ubj)}(hhh]j])}(hiThe command to send to the memory device. This must be one of the commands returned by the query command.h]hiThe command to send to the memory device. This must be one of the commands returned by the query command.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jshjZhKhj<ubjt)}(h)``flags`` Flags for the command (input). h](jz)}(h ``flags``h]j)}(hjh]hflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjyubj)}(hhh]j])}(hFlags for the command (input).h]hFlags for the command (input).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(h``{unnamed_union}`` anonymous h](jz)}(h``{unnamed_union}``h]j)}(hjh]h{unnamed_union}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h anonymoush]h anonymous}(hjѢhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj͢hKhj΢ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj͢hKhj<ubjt)}(h(``raw`` Special fields for raw commands h](jz)}(h``raw``h]j)}(hjh]hraw}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(hSpecial fields for raw commandsh]hSpecial fields for raw commands}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(hE``raw.opcode`` Opcode passed to hardware when using the RAW command. h](jz)}(h``raw.opcode``h]j)}(hj*h]h raw.opcode}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj$ubj)}(hhh]j])}(h5Opcode passed to hardware when using the RAW command.h]h5Opcode passed to hardware when using the RAW command.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj?hKhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jshj?hKhj<ubjt)}(h``raw.rsvd`` Must be zero. h](jz)}(h ``raw.rsvd``h]j)}(hjch]hraw.rsvd}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj]ubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjxhKhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jshjxhKhj<ubjt)}(h``rsvd`` Must be zero. h](jz)}(h``rsvd``h]j)}(hjh]hrsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(h9``retval`` Return value from the memory device (output). h](jz)}(h ``retval``h]j)}(hjգh]hretval}(hjףhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjӣubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjϣubj)}(hhh]j])}(h-Return value from the memory device (output).h]h-Return value from the memory device (output).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjϣubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(h1``in`` Parameters associated with input payload. h](jz)}(h``in``h]j)}(hjh]hin}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h)Parameters associated with input payload.h]h)Parameters associated with input payload.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj#hKhj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshj#hKhj<ubjt)}(hB``in.size`` Size of the payload to provide to the device (input). h](jz)}(h ``in.size``h]j)}(hjGh]hin.size}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjAubj)}(hhh]j])}(h5Size of the payload to provide to the device (input).h]h5Size of the payload to provide to the device (input).}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hj\hKhj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jshj\hKhj<ubjt)}(h``in.rsvd`` Must be zero. h](jz)}(h ``in.rsvd``h]j)}(hjh]hin.rsvd}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjzubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(hN``in.payload`` Pointer to memory for payload input, payload is little endian. h](jz)}(h``in.payload``h]j)}(hjh]h in.payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h>Pointer to memory for payload input, payload is little endian.h]h>Pointer to memory for payload input, payload is little endian.}(hjҤhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjΤhKhjϤubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjΤhKhj<ubjt)}(h3``out`` Parameters associated with output payload. h](jz)}(h``out``h]j)}(hjh]hout}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h*Parameters associated with output payload.h]h*Parameters associated with output payload.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubjt)}(hX``out.size`` Size of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was. h](jz)}(h ``out.size``h]j)}(hj+h]hout.size}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj%ubj)}(hhh]j])}(hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.h]hXSize of the payload received from the device (input/output). This field is filled in by userspace to let the driver know how much space was allocated for output. It is populated by the driver to let userspace know how large the output payload actually was.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjAubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jshj@hKhj<ubjt)}(h``out.rsvd`` Must be zero. h](jz)}(h ``out.rsvd``h]j)}(hjeh]hout.rsvd}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhj_ubj)}(hhh]j])}(h Must be zero.h]h Must be zero.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hjzhKhj{ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jshjzhKhj<ubjt)}(hO``out.payload`` Pointer to memory for payload output, payload is little endian.h](jz)}(h``out.payload``h]j)}(hjh]h out.payload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jyhk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubj)}(hhh]j])}(h?Pointer to memory for payload output, payload is little endian.h]h?Pointer to memory for payload output, payload is little endian.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jshjhKhj<ubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhjFhhhjthNubj])}(h**Description**h]j)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjߥubah}(h]h ]h"]h$]h&]uh1j\hk/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/memory-devices:483: ./include/uapi/linux/cxl_mem.hhKhjFhhubj])}(hX/Mechanism for userspace to send a command to the hardware for processing. The driver will do basic validation on the command sizes. In some cases even the payload may be introspected. Userspace is required to allocate large enough buffers for size_out which can be variable length in certain situations.h]hX/Mechanism for userspace to send a command to the hardware for processing. The driver will do basic validation on the command sizes. In some cases even the payload may be introspected. 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