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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h+Compute Express Link Subsystem Maturity Maph]h+Compute Express Link Subsystem Maturity Map}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh paragraph)}(hX/The Linux CXL subsystem tracks the dynamic `CXL specification `_ that continues to respond to new use cases with new features, capability updates and fixes. At any given point some aspects of the subsystem are more mature than others. While the periodic pull requests summarize the `work being incorporated each merge window `_, those do not always convey progress relative to a starting point and a future end goal.h](h+The Linux CXL subsystem tracks the dynamic }(hj^hhhNhNubh reference)}(hT`CXL specification `_h]hCXL specification}(hjhhhhNhNubah}(h]h ]h"]h$]h&]nameCXL specificationrefuri=https://computeexpresslink.org/cxl-specification-landing-pageuh1jfhj^ubhtarget)}(h@ h]h}(h]cxl-specificationah ]h"]cxl specificationah$]h&]refurijyuh1jz referencedKhj^ubh that continues to respond to new use cases with new features, capability updates and fixes. At any given point some aspects of the subsystem are more mature than others. While the periodic pull requests summarize the }(hj^hhhNhNubjg)}(h}`work being incorporated each merge window `_h]h)work being incorporated each merge window}(hjhhhNhNubah}(h]h ]h"]h$]h&]name)work being incorporated each merge windowjxNhttps://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3AReuh1jfhj^ubj{)}(hQ h]h}(h])work-being-incorporated-each-merge-windowah ]h"])work being incorporated each merge windowah$]h&]refurijuh1jzjKhj^ubhY, those do not always convey progress relative to a starting point and a future end goal.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1j\hhhKhjIhhubj])}(hWhat follows is a coarse breakdown of the subsystem's major responsibilities along with a maturity score. The expectation is that the change-history of this document provides an overview summary of the subsystem maturation over time.h]hWhat follows is a coarse breakdown of the subsystem’s major responsibilities along with a maturity score. The expectation is that the change-history of this document provides an overview summary of the subsystem maturation over time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjIhhubj])}(hThe maturity scores are:h]hThe maturity scores are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjIhhubh bullet_list)}(hhh](h list_item)}(h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports. h]j])}(h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports.h]h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress. h]j])}(h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress.h]h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs. h]j])}(h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs.h]h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK hj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX [0] Known gap: Feature is on a medium to long term horizon to implement. If the specification has a feature that does not even have a '0' score in this document, there is a good chance that no one in the linux-cxl@vger.kernel.org community has started to look at it. h]j])}(hX [0] Known gap: Feature is on a medium to long term horizon to implement. If the specification has a feature that does not even have a '0' score in this document, there is a good chance that no one in the linux-cxl@vger.kernel.org community has started to look at it.h](h[0] Known gap: Feature is on a medium to long term horizon to implement. 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Low Memory-holeh]j])}(hjh]h[0] Low Memory-hole}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[0] Hetero-interleave h]j])}(h[0] Hetero-interleaveh]h[0] Hetero-interleave}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jk*uh1jhhhK6hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(hJ[2] Switch Enumeration * [0] CXL register enumeration link-up dependency h](j])}(h[2] Switch Enumerationh]h[2] Switch Enumeration}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK:hj-ubj)}(hhh]j)}(h0[0] CXL register enumeration link-up dependency h]j])}(h/[0] CXL register enumeration link-up dependencyh]h/[0] CXL register enumeration link-up dependency}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjfubj)}(hhh]j)}(h/[0] Decoder target and granularity constraints h]j])}(h.[0] Decoder target and granularity constraintsh]h.[0] Decoder target and granularity constraints}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK@hj{ubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]jkj&uh1jhhhK@hjfubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(h[2] Performance enumeration * [3] Endpoint CDAT * [3] Switch CDAT * [1] CDAT to Core-mm integration * [1] x86 * [0] Arm64 * [0] All other arch. * [0] Shared link h](j])}(h[2] Performance enumerationh]h[2] Performance enumeration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKBhjubj)}(hhh](j)}(h[3] Endpoint CDATh]j])}(hjh]h[3] Endpoint CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[3] Switch CDATh]j])}(hjh]h[3] Switch CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hM[1] CDAT to Core-mm integration * [1] x86 * [0] Arm64 * [0] All other arch. h](j])}(h[1] CDAT to Core-mm integrationh]h[1] CDAT to Core-mm integration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKFhjubj)}(hhh](j)}(h[1] x86h]j])}(hjh]h[1] x86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h [0] Arm64h]j])}(hjh]h [0] Arm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[0] All other arch. h]j])}(h[0] All other arch.h]h[0] All other arch.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKJhj%ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKHhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h[0] Shared link h]j])}(h[0] Shared linkh]h[0] Shared link}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKLhjIubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKDhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(hO[2] Hotplug (see CXL Window Enumeration) * [0] Handle Soft Reserved conflicts h](j])}(h([2] Hotplug (see CXL Window Enumeration)h]h([2] Hotplug (see CXL Window Enumeration)}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKNhjmubj)}(hhh]j)}(h#[0] Handle Soft Reserved conflicts h]j])}(h"[0] Handle Soft Reserved conflictsh]h"[0] Handle Soft Reserved conflicts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jkj&uh1jhhhKQhjmubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(h,[0] :ref:`RCH link status `h]j])}(hjh](h[0] }(hjhhhNhNubh)}(h(:ref:`RCH link status `h]j)}(hjh]hRCH link status}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjrch-link-statusuh1hhhhKShjubeh}(h]h ]h"]h$]h&]uh1j\hhhKShjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[0] Fabrics / G-FAM (chapter 7)h]j])}(hjh]h[0] Fabrics / G-FAM (chapter 7)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKThjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[0] Global Access Endpoint h]j])}(h[0] Global Access Endpointh]h[0] Global Access Endpoint}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKUhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhK4hj~hhubeh}(h]enumeration-provisioningah ]h"]enumeration / provisioningah$]h&]uh1jGhjmhhhhhK/ubjH)}(hhh](jM)}(hRASh]hRAS}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKYubj])}(hIn many ways CXL can be seen as a standardization of what would normally be handled by custom EDAC drivers. The open development here is mainly caused by the enumeration corner cases above.h]hIn many ways CXL can be seen as a standardization of what would normally be handled by custom EDAC drivers. The open development here is mainly caused by the enumeration corner cases above.}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKZhj hhubj)}(hhh](j)}(h[3] Component events (OS)h]j])}(hj> h]h[3] Component events (OS)}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK^hj< ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[2] Component events (FFM)h]j])}(hjU h]h[2] Component events (FFM)}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK_hjS ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h![1] Endpoint protocol errors (OS)h]j])}(hjl h]h![1] Endpoint protocol errors (OS)}(hjn hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK`hjj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h"[1] Endpoint protocol errors (FFM)h]j])}(hj h]h"[1] Endpoint protocol errors (FFM)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKahj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[0] Switch protocol errors (OS)h]j])}(hj h]h[0] Switch protocol errors (OS)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKbhj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h [1] Switch protocol errors (FFM)h]j])}(hj h]h [1] Switch protocol errors (FFM)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKchj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(hf[2] DPA->HPA Address translation * [1] XOR Interleave translation (see CXL Window Enumeration) h](j])}(h [2] DPA->HPA Address translationh]h [2] DPA->HPA Address translation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKdhj ubh block_quote)}(h@* [1] XOR Interleave translation (see CXL Window Enumeration) h]j)}(hhh]j)}(h<[1] XOR Interleave translation (see CXL Window Enumeration) h]j])}(h;[1] XOR Interleave translation (see CXL Window Enumeration)h]h;[1] XOR Interleave translation (see CXL Window Enumeration)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKfhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]jkj&uh1jhhhKfhj ubah}(h]h ]h"]h$]h&]uh1j hhhKfhj ubeh}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[1] Memory Failure coordinationh]j])}(hj h]h[1] Memory Failure coordination}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKihj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[0] Scrub controlh]j])}(hj$ h]h[0] Scrub control}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKjhj" ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(hB[2] ACPI error injection EINJ * [0] EINJ v2 * [X] Compliance DOE h](j])}(h[2] ACPI error injection EINJh]h[2] ACPI error injection EINJ}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKkhj9 ubj)}(hhh](j)}(h [0] EINJ v2h]j])}(hjP h]h [0] EINJ v2}(hjR hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKmhjN ubah}(h]h ]h"]h$]h&]uh1jhjK ubj)}(h[X] Compliance DOE h]j])}(h[X] Compliance DOEh]h[X] Compliance DOE}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKnhje ubah}(h]h ]h"]h$]h&]uh1jhjK ubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKmhj9 ubeh}(h]h ]h"]h$]h&]uh1jhj9 hhhNhNubj)}(h[2] Native error injectionh]j])}(hj h]h[2] Native error injection}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKphj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[3] RCH error handlingh]j])}(hj h]h[3] RCH error handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKqhj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[1] VH error handlingh]j])}(hj h]h[1] VH error handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKrhj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[0] PPRh]j])}(hj h]h[0] PPR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKshj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h [0] Sparingh]j])}(hj h]h [0] Sparing}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKthj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubj)}(h[0] Device built in test h]j])}(h[0] Device built in testh]h[0] Device built in test}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKuhj ubah}(h]h ]h"]h$]h&]uh1jhj9 hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhK^hj hhubeh}(h]rasah ]h"]rasah$]h&]uh1jGhjmhhhhhKYubjH)}(hhh](jM)}(hMailbox commandsh]hMailbox commands}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj" hhhhhKyubj)}(hhh](j)}(h[3] Firmware updateh]j])}(hj8 h]h[3] Firmware update}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK{hj6 ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[3] Health / Alertsh]j])}(hjO h]h[3] Health / Alerts}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK|hjM ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h4[1] :ref:`Background commands `h]j])}(hjf h](h[1] }(hjh hhhNhNubh)}(h0:ref:`Background commands `h]j)}(hjq h]hBackground commands}(hjs hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjo ubah}(h]h ]h"]h$]h&]refdocj refdomainj} reftyperef refexplicitrefwarnjbackground-commandsuh1hhhhK}hjh ubeh}(h]h ]h"]h$]h&]uh1j\hhhK}hjd ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[3] Sanitizationh]j])}(hj h]h[3] Sanitization}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhK~hj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[3] Security commandsh]j])}(hj h]h[3] Security commands}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h![3] RAW Command Debug Passthroughh]j])}(hj h]h![3] RAW Command Debug Passthrough}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h#[0] CEL-only-validation Passthroughh]j])}(hj h]h#[0] CEL-only-validation Passthrough}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[0] Switch CCIh]j])}(hj h]h[0] Switch CCI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h [3] Timestamph]j])}(hj h]h [3] Timestamp}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[1] PMEM labelsh]j])}(hj' h]h[1] PMEM labels}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj% ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[3] PMEM GPF / Dirty Shutdownh]j])}(hj> h]h[3] PMEM GPF / Dirty Shutdown}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj< ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubj)}(h[0] Scan Media h]j])}(h[0] Scan Mediah]h[0] Scan Media}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjS ubah}(h]h ]h"]h$]h&]uh1jhj3 hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhK{hj" hhubeh}(h]mailbox-commandsah ]h"]mailbox commandsah$]h&]uh1jGhjmhhhhhKyubjH)}(hhh](jM)}(hPMUh]hPMU}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjy hhhhhKubj)}(hhh](j)}(h[1] Type 3 PMUh]j])}(hj h]h[1] Type 3 PMU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h[0] Switch USP/ DSP, Root Port h]j])}(h[0] Switch USP/ DSP, Root Porth]h[0] Switch USP/ DSP, Root Port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKhjy hhubeh}(h]pmuah ]h"]pmuah$]h&]uh1jGhjmhhhhhKubjH)}(hhh](jM)}(hSecurityh]hSecurity}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj)}(hhh](j)}(h=[X] CXL Trusted Execution Environment Security Protocol (TSP)h]j])}(hj h]h=[X] CXL Trusted Execution Environment Security Protocol (TSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h[X] CXL IDE (subsumed by TSP) h]j])}(h[X] CXL IDE (subsumed by TSP)h]h[X] CXL IDE (subsumed by TSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKhj hhubeh}(h]securityah ]h"]securityah$]h&]uh1jGhjmhhhhhKubjH)}(hhh](jM)}(hMemory-poolingh]hMemory-pooling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj)}(hhh](j)}(h$[1] Hotplug of LDs (via PCI hotplug)h]j])}(hj1 h]h$[1] Hotplug of LDs (via PCI hotplug)}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj/ ubah}(h]h ]h"]h$]h&]uh1jhj, hhhhhNubj)}(h*[0] Dynamic Capacity Device (DCD) Support h]j])}(h)[0] Dynamic Capacity Device (DCD) Supporth]h)[0] Dynamic Capacity Device (DCD) Support}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhjF ubah}(h]h ]h"]h$]h&]uh1jhj, hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKhj hhubeh}(h]memory-poolingah ]h"]memory-poolingah$]h&]uh1jGhjmhhhhhKubjH)}(hhh](jM)}(hMulti-host sharingh]hMulti-host sharing}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjl hhhhhKubj)}(hhh](j)}(h#[0] Hardware coherent shared memoryh]j])}(hj h]h#[0] Hardware coherent shared memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj} hhhhhNubj)}(h-[0] Software managed coherency shared memory h]j])}(h,[0] Software managed coherency shared memoryh]h,[0] Software managed coherency shared memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj} hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKhjl hhubeh}(h]multi-host-sharingah ]h"]multi-host sharingah$]h&]uh1jGhjmhhhhhKubjH)}(hhh](jM)}(hMulti-host memoryh]hMulti-host memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj)}(hhh](j)}(h#[0] Dynamic Capacity Device Supporth]j])}(hj h]h#[0] Dynamic Capacity Device Support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h [0] Sharing h]j])}(h [0] Sharingh]h [0] Sharing}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jkj&uh1jhhhKhj hhubeh}(h]multi-host-memoryah ]h"]multi-host memoryah$]h&]uh1jGhjmhhhhhKubjH)}(hhh](jM)}(h Acceleratorh]h Accelerator}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj)}(hhh](j)}(h=[0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)h]j])}(hj$h]h=[0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j\hhhKhj"ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h:[0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)h]j])}(hj;h]h:[0] Accelerator memory enumeration HDM-DB (CXL 3.0 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flow supportah$]h&]uh1jGhjmhhhhhKubeh}(h]feature-and-capabilitiesah ]h"]feature and capabilitiesah$]h&]uh1jGhjIhhhhhK,ubjH)}(hhh](jM)}(hDetailsh]hDetails}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj{)}(h.. _extended-linear:h]h}(h]h ]h"]h$]h&]refidextended-linearuh1jzhM hjhhhhubj)}(hhh]j)}(hX3**Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. `See the ECN `_ for more details: h]j])}(hX2**Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. `See the ECN `_ for more details:h](hstrong)}(h%**Extended-linear memory-side cache**h]h!Extended-linear memory-side cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. }(hjhhhNhNubjg)}(hu`See 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