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YEN SIGN h]h¥}hjLsbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h+Compute Express Link Subsystem Maturity Maph]h+Compute Express Link Subsystem Maturity Map}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj]hhhhhKubh paragraph)}(hX/The Linux CXL subsystem tracks the dynamic `CXL specification `_ that continues to respond to new use cases with new features, capability updates and fixes. At any given point some aspects of the subsystem are more mature than others. While the periodic pull requests summarize the `work being incorporated each merge window `_, those do not always convey progress relative to a starting point and a future end goal.h](h+The Linux CXL subsystem tracks the dynamic }(hjrhhhNhNubh reference)}(hT`CXL specification `_h]hCXL specification}(hj|hhhNhNubah}(h]h ]h"]h$]h&]nameCXL specificationrefuri=https://computeexpresslink.org/cxl-specification-landing-pageuh1jzhjrubhtarget)}(h@ h]h}(h]cxl-specificationah ]h"]cxl specificationah$]h&]refurijuh1j referencedKhjrubh that continues to respond to new use cases with new features, capability updates and fixes. At any given point some aspects of the subsystem are more mature than others. While the periodic pull requests summarize the }(hjrhhhNhNubj{)}(h}`work being incorporated each merge window `_h]h)work being incorporated each merge window}(hjhhhNhNubah}(h]h ]h"]h$]h&]name)work being incorporated each merge windowjNhttps://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3AReuh1jzhjrubj)}(hQ h]h}(h])work-being-incorporated-each-merge-windowah ]h"])work being incorporated each merge windowah$]h&]refurijuh1jjKhjrubhY, those do not always convey progress relative to a starting point and a future end goal.}(hjrhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhj]hhubjq)}(hWhat follows is a coarse breakdown of the subsystem's major responsibilities along with a maturity score. The expectation is that the change-history of this document provides an overview summary of the subsystem maturation over time.h]hWhat follows is a coarse breakdown of the subsystem’s major responsibilities along with a maturity score. The expectation is that the change-history of this document provides an overview summary of the subsystem maturation over time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj]hhubjq)}(hThe maturity scores are:h]hThe maturity scores are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj]hhubh bullet_list)}(hhh](h list_item)}(h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports. h]jq)}(h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports.h]h[3] Mature: Work in this area is complete and no changes on the horizon. Note that this score can regress from one kernel release to the next based on new test results or end user reports.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress. h]jq)}(h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress.h]h[2] Stabilizing: Major functionality operational, common cases are mature, but known corner cases are still a work in progress.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs. h]jq)}(h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs.h]h[1] Initial: Capability that has exited the Proof of Concept phase, but may still have significant gaps to close and fixes to apply as real world testing occurs.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX [0] Known gap: Feature is on a medium to long term horizon to implement. If the specification has a feature that does not even have a '0' score in this document, there is a good chance that no one in the linux-cxl@vger.kernel.org community has started to look at it. h]jq)}(hX [0] Known gap: Feature is on a medium to long term horizon to implement. If the specification has a feature that does not even have a '0' score in this document, there is a good chance that no one in the linux-cxl@vger.kernel.org community has started to look at it.h](h[0] Known gap: Feature is on a medium to long term horizon to implement. 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Memory-holeh]jq)}(hjh]h[0] Low Memory-hole}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[X] Hetero-interleave h]jq)}(h[X] Hetero-interleaveh]h[X] Hetero-interleave}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK8hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j*uh1jhhhK6hjubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(hJ[2] Switch Enumeration * [0] CXL register enumeration link-up dependency h](jq)}(h[2] Switch Enumerationh]h[2] Switch Enumeration}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK:hjAubj)}(hhh]j)}(h0[0] CXL register enumeration link-up dependency h]jq)}(h/[0] CXL register enumeration link-up dependencyh]h/[0] CXL register enumeration link-up dependency}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjzubj)}(hhh]j)}(h/[0] Decoder target and granularity constraints h]jq)}(h.[0] Decoder target and granularity constraintsh]h.[0] Decoder target and granularity constraints}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK@hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jj:uh1jhhhK@hjzubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(h[2] Performance enumeration * [3] Endpoint CDAT * [3] Switch CDAT * [1] CDAT to Core-mm integration * [1] x86 * [0] Arm64 * [0] All other arch. * [0] Shared link h](jq)}(h[2] Performance enumerationh]h[2] Performance enumeration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKBhjubj)}(hhh](j)}(h[3] Endpoint CDATh]jq)}(hjh]h[3] Endpoint CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKDhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[3] Switch CDATh]jq)}(hjh]h[3] Switch CDAT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hM[1] CDAT to Core-mm integration * [1] x86 * [0] Arm64 * [0] All other arch. h](jq)}(h[1] CDAT to Core-mm integrationh]h[1] CDAT to Core-mm integration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKFhjubj)}(hhh](j)}(h[1] x86h]jq)}(hj h]h[1] x86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKHhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h [0] Arm64h]jq)}(hj$h]h [0] Arm64}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKIhj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h[0] All other arch. h]jq)}(h[0] All other arch.h]h[0] All other arch.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKJhj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKHhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h[0] Shared link h]jq)}(h[0] Shared linkh]h[0] Shared link}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKLhj]ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKDhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(hO[2] Hotplug (see CXL Window Enumeration) * [0] Handle Soft Reserved conflicts h](jq)}(h([2] Hotplug (see CXL Window Enumeration)h]h([2] Hotplug (see CXL Window Enumeration)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKNhjubj)}(hhh]j)}(h#[0] Handle Soft Reserved conflicts h]jq)}(h"[0] Handle Soft Reserved conflictsh]h"[0] Handle Soft Reserved conflicts}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jj:uh1jhhhKQhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhNhNubj)}(h,[0] :ref:`RCH link status `h]jq)}(hjh](h[0] }(hjhhhNhNubh)}(h(:ref:`RCH link status `h]j)}(hjh]hRCH link status}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjrch-link-statusuh1hhhhKShjubeh}(h]h ]h"]h$]h&]uh1jphhhKShjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[0] Fabrics / G-FAM (chapter 7)h]jq)}(hjh]h[0] Fabrics / G-FAM (chapter 7)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKThjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h[0] Global Access Endpoint h]jq)}(h[0] Global Access Endpointh]h[0] Global Access Endpoint}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKUhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhK4hjhhubeh}(h]enumeration-provisioningah ]h"]enumeration / provisioningah$]h&]uh1j[hjhhhhhK/ubj\)}(hhh](ja)}(hRASh]hRAS}(hj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj. hhhhhKYubjq)}(hIn many ways CXL can be seen as a standardization of what would normally be handled by custom EDAC drivers. The open development here is mainly caused by the enumeration corner cases above.h]hIn many ways CXL can be seen as a standardization of what would normally be handled by custom EDAC drivers. The open development here is mainly caused by the enumeration corner cases above.}(hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKZhj. hhubj)}(hhh](j)}(h[3] Component events (OS)h]jq)}(hjR h]h[3] Component events (OS)}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK^hjP ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[2] Component events (FFM)h]jq)}(hji h]h[2] Component events (FFM)}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK_hjg ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h![1] Endpoint protocol errors (OS)h]jq)}(hj h]h![1] Endpoint protocol errors (OS)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK`hj~ ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h"[1] Endpoint protocol errors (FFM)h]jq)}(hj h]h"[1] Endpoint protocol errors (FFM)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKahj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[0] Switch protocol errors (OS)h]jq)}(hj h]h[0] Switch protocol errors (OS)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKbhj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h [1] Switch protocol errors (FFM)h]jq)}(hj h]h [1] Switch protocol errors (FFM)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKchj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(hf[2] DPA->HPA Address translation * [1] XOR Interleave translation (see CXL Window Enumeration) h](jq)}(h [2] DPA->HPA Address translationh]h [2] DPA->HPA Address translation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKdhj ubh block_quote)}(h@* [1] XOR Interleave translation (see CXL Window Enumeration) h]j)}(hhh]j)}(h<[1] XOR Interleave translation (see CXL Window Enumeration) h]jq)}(h;[1] XOR Interleave translation (see CXL Window Enumeration)h]h;[1] XOR Interleave translation (see CXL Window Enumeration)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKfhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]jj:uh1jhhhKfhj ubah}(h]h ]h"]h$]h&]uh1j hhhKfhj ubeh}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[1] Memory Failure coordinationh]jq)}(hj! h]h[1] Memory Failure coordination}(hj# hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKihj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[0] Scrub controlh]jq)}(hj8 h]h[0] Scrub control}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKjhj6 ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(hB[2] ACPI error injection EINJ * [0] EINJ v2 * [X] Compliance DOE h](jq)}(h[2] ACPI error injection EINJh]h[2] ACPI error injection EINJ}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKkhjM ubj)}(hhh](j)}(h [0] EINJ v2h]jq)}(hjd h]h [0] EINJ v2}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKmhjb ubah}(h]h ]h"]h$]h&]uh1jhj_ ubj)}(h[X] Compliance DOE h]jq)}(h[X] Compliance DOEh]h[X] Compliance DOE}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKnhjy ubah}(h]h ]h"]h$]h&]uh1jhj_ ubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKmhjM ubeh}(h]h ]h"]h$]h&]uh1jhjM hhhNhNubj)}(h[2] Native error injectionh]jq)}(hj h]h[2] Native error injection}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKphj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[3] RCH error handlingh]jq)}(hj h]h[3] RCH error handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKqhj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[1] VH error handlingh]jq)}(hj h]h[1] VH error handling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKrhj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[0] PPRh]jq)}(hj h]h[0] PPR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKshj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h [0] Sparingh]jq)}(hj h]h [0] Sparing}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKthj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubj)}(h[0] Device built in test h]jq)}(h[0] Device built in testh]h[0] Device built in test}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKuhj ubah}(h]h ]h"]h$]h&]uh1jhjM hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhK^hj. hhubeh}(h]rasah ]h"]rasah$]h&]uh1j[hjhhhhhKYubj\)}(hhh](ja)}(hMailbox commandsh]hMailbox commands}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj6 hhhhhKyubj)}(hhh](j)}(h[3] Firmware updateh]jq)}(hjL h]h[3] Firmware update}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK{hjJ ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[3] Health / Alertsh]jq)}(hjc h]h[3] Health / Alerts}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK|hja ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h4[1] :ref:`Background commands `h]jq)}(hjz h](h[1] }(hj| hhhNhNubh)}(h0:ref:`Background commands `h]j)}(hj h]hBackground commands}(hj hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainj reftyperef refexplicitrefwarnjbackground-commandsuh1hhhhK}hj| ubeh}(h]h ]h"]h$]h&]uh1jphhhK}hjx ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[3] Sanitizationh]jq)}(hj h]h[3] Sanitization}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhK~hj ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[3] Security commandsh]jq)}(hj h]h[3] Security commands}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h![3] RAW Command Debug Passthroughh]jq)}(hj h]h![3] RAW Command Debug Passthrough}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h#[0] CEL-only-validation Passthroughh]jq)}(hj h]h#[0] CEL-only-validation Passthrough}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[0] Switch CCIh]jq)}(hj h]h[0] Switch CCI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h [3] Timestamph]jq)}(hj$ h]h [3] Timestamp}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj" ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[1] PMEM labelsh]jq)}(hj; h]h[1] PMEM labels}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj9 ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[3] PMEM GPF / Dirty Shutdownh]jq)}(hjR h]h[3] PMEM GPF / Dirty Shutdown}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjP ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubj)}(h[0] Scan Media h]jq)}(h[0] Scan Mediah]h[0] Scan Media}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjg ubah}(h]h ]h"]h$]h&]uh1jhjG hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhK{hj6 hhubeh}(h]mailbox-commandsah ]h"]mailbox commandsah$]h&]uh1j[hjhhhhhKyubj\)}(hhh](ja)}(hPMUh]hPMU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hhh](j)}(h[1] Type 3 PMUh]jq)}(hj h]h[1] Type 3 PMU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h[0] Switch USP/ DSP, Root Port h]jq)}(h[0] Switch USP/ DSP, Root Porth]h[0] Switch USP/ DSP, Root Port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj hhubeh}(h]pmuah ]h"]pmuah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(hSecurityh]hSecurity}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hhh](j)}(h=[X] CXL Trusted Execution Environment Security Protocol (TSP)h]jq)}(hj h]h=[X] CXL Trusted Execution Environment Security Protocol (TSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h[X] CXL IDE (subsumed by TSP) h]jq)}(h[X] CXL IDE (subsumed by TSP)h]h[X] CXL IDE (subsumed by TSP)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj hhubeh}(h]securityah ]h"]securityah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(hMemory-poolingh]hMemory-pooling}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj/ hhhhhKubj)}(hhh](j)}(h$[1] Hotplug of LDs (via PCI hotplug)h]jq)}(hjE h]h$[1] Hotplug of LDs (via PCI hotplug)}(hjG hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjC ubah}(h]h ]h"]h$]h&]uh1jhj@ hhhhhNubj)}(h*[0] Dynamic Capacity Device (DCD) Support h]jq)}(h)[0] Dynamic Capacity Device (DCD) Supporth]h)[0] Dynamic Capacity Device (DCD) Support}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjZ ubah}(h]h ]h"]h$]h&]uh1jhj@ hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj/ hhubeh}(h]memory-poolingah ]h"]memory-poolingah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(hMulti-host sharingh]hMulti-host sharing}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hhh](j)}(h#[0] Hardware coherent shared memoryh]jq)}(hj h]h#[0] Hardware coherent shared memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h-[0] Software managed coherency shared memory h]jq)}(h,[0] Software managed coherency shared memoryh]h,[0] Software managed coherency shared memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj hhubeh}(h]multi-host-sharingah ]h"]multi-host sharingah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(hMulti-host memoryh]hMulti-host memory}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj hhhhhKubj)}(hhh](j)}(h#[0] Dynamic Capacity Device Supporth]jq)}(hj h]h#[0] Dynamic Capacity Device Support}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h [0] Sharing h]jq)}(h [0] Sharingh]h [0] Sharing}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj hhubeh}(h]multi-host-memoryah ]h"]multi-host memoryah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(h Acceleratorh]h Accelerator}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j`hj"hhhhhKubj)}(hhh](j)}(h=[0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)h]jq)}(hj8h]h=[0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhj3hhhhhNubj)}(h:[0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)h]jq)}(hjOh]h:[0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjMubah}(h]h ]h"]h$]h&]uh1jhj3hhhhhNubj)}(h[0] CXL.cache 68b (CXL 2.0)h]jq)}(hjfh]h[0] CXL.cache 68b (CXL 2.0)}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjdubah}(h]h ]h"]h$]h&]uh1jhj3hhhhhNubj)}(h'[0] CXL.cache 256b Cache IDs (CXL 3.0) h]jq)}(h&[0] CXL.cache 256b Cache IDs (CXL 3.0)h]h&[0] CXL.cache 256b Cache IDs (CXL 3.0)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhj{ubah}(h]h ]h"]h$]h&]uh1jhj3hhhhhNubeh}(h]h ]h"]h$]h&]jj:uh1jhhhKhj"hhubeh}(h] acceleratorah ]h"] acceleratorah$]h&]uh1j[hjhhhhhKubj\)}(hhh](ja)}(hUser Flow Supporth]hUser Flow Support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhKubj)}(hhh]j)}(h+[2] Inject & clear poison by region offset h]jq)}(h*[2] Inject & clear poison by region offseth]h*[2] Inject & clear poison by region offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubah}(h]h ]h"]h$]h&]jj:uh1jhhhKhjhhubeh}(h]user-flow-supportah ]h"]user flow supportah$]h&]uh1j[hjhhhhhKubeh}(h]feature-and-capabilitiesah ]h"]feature and capabilitiesah$]h&]uh1j[hj]hhhhhK,ubj\)}(hhh](ja)}(hDetailsh]hDetails}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j`hjhhhhhKubj)}(h.. _extended-linear:h]h}(h]h ]h"]h$]h&]refidextended-linearuh1jhM hjhhhhubj)}(hhh]j)}(hX3**Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. `See the ECN `_ for more details: h]jq)}(hX2**Extended-linear memory-side cache**: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. `See the ECN `_ for more details:h](hstrong)}(h%**Extended-linear memory-side cache**h]h!Extended-linear memory-side cache}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjubh: An HMAT proposal to enumerate the presence of a memory-side cache where the cache capacity extends the SRAT address range capacity. }(hjhhhNhNubj{)}(hu`See the ECN `_h]h See the ECN}(hjhhhNhNubah}(h]h ]h"]h$]h&]name See the ECNjdhttps://lore.kernel.org/linux-cxl/6650e4f835a0e_195e294a8@dwillia2-mobl3.amr.corp.intel.com.notmuch/uh1jzhjubj)}(hg h]h}(h] see-the-ecnah ]h"] see the ecnah$]h&]refurij/uh1jjKhjubh for more details:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jphhhKhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubah}(h]jah ]h"]extended-linearah$]h&]jj:uh1jhhhKhjhhexpect_referenced_by_name}jQjsexpect_referenced_by_id}jjsubj)}(h.. _rch-link-status:h]h}(h]h ]h"]h$]h&]jrch-link-statusuh1jhMhjhhhhubj)}(hhh]j)}(h**RCH Link Status**: RCH (Restricted CXL Host) topologies, end up hiding some standard registers like PCIe Link Status / Capabilities in the CXL RCRB (Root Complex Register Block). h]jq)}(h**RCH Link Status**: RCH (Restricted CXL Host) topologies, end up hiding some standard registers like PCIe Link Status / Capabilities in the CXL RCRB (Root Complex Register Block).h](j )}(h**RCH Link Status**h]hRCH Link Status}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjjubh: RCH (Restricted CXL Host) topologies, end up hiding some standard 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