€•_†Œsphinx.addnodes”Œdocument”“”)�”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)�”}”(hhh]”(hŒ pending_xref”“”)�”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…”�”}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”ŒP/translations/zh_CN/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)�”}”(hhh]”hŒChinese (Traditional)”…”�”}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/zh_TW/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒItalian”…”�”}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/it_IT/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒJapanese”…”�”}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/ja_JP/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒKorean”…”�”}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/ko_KR/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒPortuguese (Brazilian)”…”�”}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/pt_BR/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)�”}”(hhh]”hŒSpanish”…”�”}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒP/translations/sp_SP/driver-api/cxl/linux/example-configurations/multi-interleave”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)�”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…”�”}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œj/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/linux/example-configurations/multi-interleave.rst”h´KubhŒsection”“”)�”}”(hhh]”(hŒtitle”“”)�”}”(hŒMulti-Level Interleave”h]”hŒMulti-Level Interleave”…”�”}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)�”}”(hŒGThis cxl-cli configuration dump shows the following host configuration:”h]”hŒGThis cxl-cli configuration dump shows the following host configuration:”…”�”}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒ bullet_list”“”)�”}”(hhh]”(hŒ list_item”“”)�”}”(hŒ(A single socket system with one CXL root”h]”hÞ)�”}”(hhöh]”hŒ(A single socket system with one CXL root”…”�”}”(hhøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhôubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)�”}”(hŒ&CXL Root has Four (4) CXL Host Bridges”h]”hÞ)�”}”(hj h]”hŒ&CXL Root has Four (4) CXL Host Bridges”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)�”}”(hŒCTwo CXL Host Bridges have a two CXL Memory Expanders Attached each.”h]”hÞ)�”}”(hj$h]”hŒCTwo CXL Host Bridges have a two CXL Memory Expanders Attached each.”…”�”}”(hj&h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hj"ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)�”}”(hŒEThe CXL root is configured to interleave across the two host bridges.”h]”hÞ)�”}”(hj;h]”hŒEThe CXL root is configured to interleave across the two host bridges.”…”�”}”(hj=h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hj9ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)�”}”(hŒBEach host bridge with expanders interleaves across two endpoints. ”h]”hÞ)�”}”(hŒAEach host bridge with expanders interleaves across two endpoints.”h]”hŒAEach host bridge with expanders interleaves across two endpoints.”…”�”}”(hjTh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjPubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1híh³hÇh´KhhÊh²hubhÞ)�”}”(hŒ‰This output is generated by :code:`cxl list -v` and describes the relationships between objects exposed in :code:`/sys/bus/cxl/devices/`.”h]”(hŒThis output is generated by ”…”�”}”(hjph²hh³Nh´NubhŒliteral”“”)�”}”(hŒ:code:`cxl list -v`”h]”hŒ cxl list -v”…”�”}”(hjzh²hh³Nh´Nubah}”(h]”h ]”Œcode”ah"]”h$]”h&]”Œlanguage”huh1jxhjpubhŒ< and describes the relationships between objects exposed in ”…”�”}”(hjph²hh³Nh´Nubjy)�”}”(hŒ:code:`/sys/bus/cxl/devices/`”h]”hŒ/sys/bus/cxl/devices/”…”�”}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjpubhŒ.”…”�”}”(hjph²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒ literal_block”“”)�”}”(hXA[ { "bus":"root0", "provider":"ACPI.CXL", "nr_dports":4, "dports":[ { "dport":"pci0000:00", "alias":"ACPI0016:01", "id":0 }, { "dport":"pci0000:a8", "alias":"ACPI0016:02", "id":4 }, { "dport":"pci0000:2a", "alias":"ACPI0016:03", "id":1 }, { "dport":"pci0000:d2", "alias":"ACPI0016:00", "id":5 } ],”h]”hXA[ { "bus":"root0", "provider":"ACPI.CXL", "nr_dports":4, "dports":[ { "dport":"pci0000:00", "alias":"ACPI0016:01", "id":0 }, { "dport":"pci0000:a8", "alias":"ACPI0016:02", "id":4 }, { "dport":"pci0000:2a", "alias":"ACPI0016:03", "id":1 }, { "dport":"pci0000:d2", "alias":"ACPI0016:00", "id":5 } ],”…”�”}”hj©sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´KhhÊh²hubhÞ)�”}”(hŒçThis chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL Host Bridges. The `Root` can be considered the singular upstream port attached to the platform's memory controller - which routes memory requests to it.”h]”(hŒeThis chunk shows the CXL “busâ€� (root0) has 4 downstream ports attached to CXL Host Bridges. The ”…”�”}”(hj·h²hh³Nh´NubhŒtitle_reference”“”)�”}”(hŒ`Root`”h]”hŒRoot”…”�”}”(hjÁh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¿hj·ubhŒ‚ can be considered the singular upstream port attached to the platform’s memory controller - which routes memory requests to it.”…”�”}”(hj·h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K/hhÊh²hubhÞ)�”}”(hŒ”The `ports:root0` section lays out how each of these downstream ports are configured. If a port is not configured (id's 0 and 1), they are omitted.”h]”(hŒThe ”…”�”}”(hjÙh²hh³Nh´NubjÀ)�”}”(hŒ `ports:root0`”h]”hŒ ports:root0”…”�”}”(hjáh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¿hjÙubhŒ… section lays out how each of these downstream ports are configured. If a port is not configured (id’s 0 and 1), they are omitted.”…”�”}”(hjÙh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K3hhÊh²hubj¨)�”}”(hX"ports:root0":[ { "port":"port1", "host":"pci0000:d2", "depth":1, "nr_dports":3, "dports":[ { "dport":"0000:d2:01.1", "alias":"device:02", "id":0 }, { "dport":"0000:d2:01.3", "alias":"device:05", "id":2 }, { "dport":"0000:d2:07.1", "alias":"device:0d", "id":113 } ],”h]”hX"ports:root0":[ { "port":"port1", "host":"pci0000:d2", "depth":1, "nr_dports":3, "dports":[ { "dport":"0000:d2:01.1", "alias":"device:02", "id":0 }, { "dport":"0000:d2:01.3", "alias":"device:05", "id":2 }, { "dport":"0000:d2:07.1", "alias":"device:0d", "id":113 } ],”…”�”}”hjùsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´K8hhÊh²hubhÞ)�”}”(hŒ×This chunk shows the available downstream ports associated with the CXL Host Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream ports: :code:`dport0`, :code:`dport2`, and :code:`dport113`.”h]”(hŒTThis chunk shows the available downstream ports associated with the CXL Host Bridge ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ :code:`port1`”h]”hŒport1”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ. In this case, ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ :code:`port1`”h]”hŒport1”…”�”}”(hj"h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ# has 3 available downstream ports: ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ:code:`dport0`”h]”hŒdport0”…”�”}”(hj5h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ, ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ:code:`dport2`”h]”hŒdport2”…”�”}”(hjHh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ, and ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ:code:`dport113`”h]”hŒdport113”…”�”}”(hj[h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ.”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KPhhÊh²hubj¨)�”}”(hX¯"endpoints:port1":[ { "endpoint":"endpoint5", "host":"mem0", "parent_dport":"0000:d2:01.1", "depth":2, "memdev":{ "memdev":"mem0", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:d3:00.0" }, "decoders:endpoint5":[ { "decoder":"decoder5.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] }, { "endpoint":"endpoint6", "host":"mem1", "parent_dport":"0000:d2:01.3", "depth":2, "memdev":{ "memdev":"mem1", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:d3:00.0" }, "decoders:endpoint6":[ { "decoder":"decoder6.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] } ],”h]”hX¯"endpoints:port1":[ { "endpoint":"endpoint5", "host":"mem0", "parent_dport":"0000:d2:01.1", "depth":2, "memdev":{ "memdev":"mem0", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:d3:00.0" }, "decoders:endpoint5":[ { "decoder":"decoder5.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] }, { "endpoint":"endpoint6", "host":"mem1", "parent_dport":"0000:d2:01.3", "depth":2, "memdev":{ "memdev":"mem1", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:d3:00.0" }, "decoders:endpoint6":[ { "decoder":"decoder6.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] } ],”…”�”}”hjtsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´KVhhÊh²hubhÞ)�”}”(hŒIThis chunk shows the endpoints attached to the host bridge :code:`port1`.”h]”(hŒ;This chunk shows the endpoints attached to the host bridge ”…”�”}”(hj‚h²hh³Nh´Nubjy)�”}”(hŒ :code:`port1`”h]”hŒport1”…”�”}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj‚ubhŒ.”…”�”}”(hj‚h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K�hhÊh²hubhÞ)�”}”(hŒ—:code:`endpoint5` contains a single configured decoder :code:`decoder5.0` which has the same interleave configuration as :code:`region0` (shown later).”h]”(jy)�”}”(hŒ:code:`endpoint5`”h]”hŒ endpoint5”…”�”}”(hj§h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj£ubhŒ& contains a single configured decoder ”…”�”}”(hj£h²hh³Nh´Nubjy)�”}”(hŒ:code:`decoder5.0`”h]”hŒ decoder5.0”…”�”}”(hjºh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj£ubhŒ0 which has the same interleave configuration as ”…”�”}”(hj£h²hh³Nh´Nubjy)�”}”(hŒ:code:`region0`”h]”hŒregion0”…”�”}”(hjÍh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj£ubhŒ (shown later).”…”�”}”(hj£h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K�hhÊh²hubhÞ)�”}”(hŒ—:code:`endpoint6` contains a single configured decoder :code:`decoder5.0` which has the same interleave configuration as :code:`region0` (shown later).”h]”(jy)�”}”(hŒ:code:`endpoint6`”h]”hŒ endpoint6”…”�”}”(hjêh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjæubhŒ& contains a single configured decoder ”…”�”}”(hjæh²hh³Nh´Nubjy)�”}”(hŒ:code:`decoder5.0`”h]”hŒ decoder5.0”…”�”}”(hjýh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjæubhŒ0 which has the same interleave configuration as ”…”�”}”(hjæh²hh³Nh´Nubjy)�”}”(hŒ:code:`region0`”h]”hŒregion0”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjæubhŒ (shown later).”…”�”}”(hjæh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K’hhÊh²hubhÞ)�”}”(hŒ7Next we have the decoders belonging to the host bridge:”h]”hŒ7Next we have the decoders belonging to the host bridge:”…”�”}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K•hhÊh²hubj¨)�”}”(hX¹ "decoders:port1":[ { "decoder":"decoder1.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":512, "region":"region0", "nr_targets":2, "targets":[ { "target":"0000:d2:01.1", "alias":"device:02", "position":0, "id":0 }, { "target":"0000:d2:01.3", "alias":"device:05", "position":2, "id":0 } ] } ] },”h]”hX¹ "decoders:port1":[ { "decoder":"decoder1.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":512, "region":"region0", "nr_targets":2, "targets":[ { "target":"0000:d2:01.1", "alias":"device:02", "position":0, "id":0 }, { "target":"0000:d2:01.3", "alias":"device:05", "position":2, "id":0 } ] } ] },”…”�”}”hj7sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´K™hhÊh²hubhÞ)�”}”(hŒÆHost Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose targets are :code:`dport0` and :code:`dport2` - which are attached to :code:`endpoint5` and :code:`endpoint6` respectively.”h]”(hŒ Host Bridge ”…”�”}”(hjEh²hh³Nh´Nubjy)�”}”(hŒ :code:`port1`”h]”hŒport1”…”�”}”(hjMh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ has a single decoder (”…”�”}”(hjEh²hh³Nh´Nubjy)�”}”(hŒ:code:`decoder1.0`”h]”hŒ decoder1.0”…”�”}”(hj`h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ), whose targets are ”…”�”}”(hjEh²hh³Nh´Nubjy)�”}”(hŒ:code:`dport0`”h]”hŒdport0”…”�”}”(hjsh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ and ”…”�”}”(hjEh²hh³Nh´Nubjy)�”}”(hŒ:code:`dport2`”h]”hŒdport2”…”�”}”(hj†h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ - which are attached to ”…”�”}”(hjEh²hh³Nh´Nubjy)�”}”(hŒ:code:`endpoint5`”h]”hŒ endpoint5”…”�”}”(hj™h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ and ”…”�”}”hjEsbjy)�”}”(hŒ:code:`endpoint6`”h]”hŒ endpoint6”…”�”}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjEubhŒ respectively.”…”�”}”(hjEh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K´hhÊh²hubhÞ)�”}”(hŒ†The following chunk shows a similar configuration for Host Bridge :code:`port3`, the second host bridge with a memory device attached.”h]”(hŒBThe following chunk shows a similar configuration for Host Bridge ”…”�”}”(hjÅh²hh³Nh´Nubjy)�”}”(hŒ :code:`port3`”h]”hŒport3”…”�”}”(hjÍh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjÅubhŒ7, the second host bridge with a memory device attached.”…”�”}”(hjÅh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K¸hhÊh²hubj¨)�”}”(hX� { "port":"port3", "host":"pci0000:a8", "depth":1, "nr_dports":1, "dports":[ { "dport":"0000:a8:01.1", "alias":"device:c3", "id":0 }, { "dport":"0000:a8:01.3", "alias":"device:c5", "id":0 } ], "endpoints:port3":[ { "endpoint":"endpoint7", "host":"mem2", "parent_dport":"0000:a8:01.1", "depth":2, "memdev":{ "memdev":"mem2", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:a9:00.0" }, "decoders:endpoint7":[ { "decoder":"decoder7.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] }, { "endpoint":"endpoint8", "host":"mem3", "parent_dport":"0000:a8:01.3", "depth":2, "memdev":{ "memdev":"mem3", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:a9:00.0" }, "decoders:endpoint8":[ { "decoder":"decoder8.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] } ], "decoders:port3":[ { "decoder":"decoder3.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":512, "region":"region0", "nr_targets":1, "targets":[ { "target":"0000:a8:01.1", "alias":"device:c3", "position":1, "id":0 }, { "target":"0000:a8:01.3", "alias":"device:c5", "position":3, "id":0 } ] } ] },”h]”hX� { "port":"port3", "host":"pci0000:a8", "depth":1, "nr_dports":1, "dports":[ { "dport":"0000:a8:01.1", "alias":"device:c3", "id":0 }, { "dport":"0000:a8:01.3", "alias":"device:c5", "id":0 } ], "endpoints:port3":[ { "endpoint":"endpoint7", "host":"mem2", "parent_dport":"0000:a8:01.1", "depth":2, "memdev":{ "memdev":"mem2", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:a9:00.0" }, "decoders:endpoint7":[ { "decoder":"decoder7.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] }, { "endpoint":"endpoint8", "host":"mem3", "parent_dport":"0000:a8:01.3", "depth":2, "memdev":{ "memdev":"mem3", "ram_size":137438953472, "serial":0, "numa_node":0, "host":"0000:a9:00.0" }, "decoders:endpoint8":[ { "decoder":"decoder8.0", "resource":825975898112, "size":549755813888, "interleave_ways":4, "interleave_granularity":256, "region":"region0", "dpa_resource":0, "dpa_size":137438953472, "mode":"ram" } ] } ], "decoders:port3":[ { "decoder":"decoder3.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":512, "region":"region0", "nr_targets":1, "targets":[ { "target":"0000:a8:01.1", "alias":"device:c3", "position":1, "id":0 }, { "target":"0000:a8:01.3", "alias":"device:c5", "position":3, "id":0 } ] } ] },”…”�”}”hjæsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´K½hhÊh²hubhÞ)�”}”(hŒIThe next chunk shows the two CXL host bridges without attached endpoints.”h]”hŒIThe next chunk shows the two CXL host bridges without attached endpoints.”…”�”}”(hjôh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´M hhÊh²hubj¨)�”}”(hX– { "port":"port2", "host":"pci0000:00", "depth":1, "nr_dports":2, "dports":[ { "dport":"0000:00:01.3", "alias":"device:55", "id":2 }, { "dport":"0000:00:07.1", "alias":"device:5d", "id":113 } ] }, { "port":"port4", "host":"pci0000:2a", "depth":1, "nr_dports":1, "dports":[ { "dport":"0000:2a:01.1", "alias":"device:d0", "id":0 } ] } ],”h]”hX– { "port":"port2", "host":"pci0000:00", "depth":1, "nr_dports":2, "dports":[ { "dport":"0000:00:01.3", "alias":"device:55", "id":2 }, { "dport":"0000:00:07.1", "alias":"device:5d", "id":113 } ] }, { "port":"port4", "host":"pci0000:2a", "depth":1, "nr_dports":1, "dports":[ { "dport":"0000:2a:01.1", "alias":"device:d0", "id":0 } ] } ],”…”�”}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´M$hhÊh²hubhÞ)�”}”(hŒÅNext we have the `Root Decoders` belonging to :code:`root0`. This root decoder applies the interleave across the downstream ports :code:`port1` and :code:`port3` - with a granularity of 256 bytes.”h]”(hŒNext we have the ”…”�”}”(hjh²hh³Nh´NubjÀ)�”}”(hŒ`Root Decoders`”h]”hŒ Root Decoders”…”�”}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¿hjubhŒ belonging to ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ :code:`root0`”h]”hŒroot0”…”�”}”(hj*h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒH. This root decoder applies the interleave across the downstream ports ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ :code:`port1`”h]”hŒport1”…”�”}”(hj=h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ and ”…”�”}”(hjh²hh³Nh´Nubjy)�”}”(hŒ :code:`port3`”h]”hŒport3”…”�”}”(hjPh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhjubhŒ# - with a granularity of 256 bytes.”…”�”}”(hjh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´MEhhÊh²hubhÞ)�”}”(hŒLThis information is generated by the CXL driver reading the ACPI CEDT CMFWS.”h]”hŒLThis information is generated by the CXL driver reading the ACPI CEDT CMFWS.”…”�”}”(hjih²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´MIhhÊh²hubj¨)�”}”(hXr"decoders:root0":[ { "decoder":"decoder0.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":256, "max_available_extent":0, "volatile_capable":true, "nr_targets":2, "targets":[ { "target":"pci0000:a8", "alias":"ACPI0016:02", "position":1, "id":4 }, { "target":"pci0000:d2", "alias":"ACPI0016:00", "position":0, "id":5 } ],”h]”hXr"decoders:root0":[ { "decoder":"decoder0.0", "resource":825975898112, "size":549755813888, "interleave_ways":2, "interleave_granularity":256, "max_available_extent":0, "volatile_capable":true, "nr_targets":2, "targets":[ { "target":"pci0000:a8", "alias":"ACPI0016:02", "position":1, "id":4 }, { "target":"pci0000:d2", "alias":"ACPI0016:00", "position":0, "id":5 } ],”…”�”}”hjwsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´MMhhÊh²hubhÞ)�”}”(hXFinally we have the `Memory Region` associated with the `Root Decoder` :code:`decoder0.0`. This region describes the overall interleave configuration of the interleave set. So we see there are a total of :code:`4` interleave targets across 4 endpoint decoders.”h]”(hŒFinally we have the ”…”�”}”(hj…h²hh³Nh´NubjÀ)�”}”(hŒ`Memory Region`”h]”hŒ Memory Region”…”�”}”(hj�h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¿hj…ubhŒ associated with the ”…”�”}”(hj…h²hh³Nh´NubjÀ)�”}”(hŒ`Root Decoder`”h]”hŒ Root Decoder”…”�”}”(hjŸh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¿hj…ubhŒ ”…”�”}”(hj…h²hh³Nh´Nubjy)�”}”(hŒ:code:`decoder0.0`”h]”hŒ decoder0.0”…”�”}”(hj±h²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj…ubhŒu. This region describes the overall interleave configuration of the interleave set. So we see there are a total of ”…”�”}”(hj…h²hh³Nh´Nubjy)�”}”(hŒ :code:`4`”h]”hŒ4”…”�”}”(hjÄh²hh³Nh´Nubah}”(h]”h ]”j…ah"]”h$]”h&]”Œlanguage”huh1jxhj…ubhŒ/ interleave targets across 4 endpoint decoders.”…”�”}”(hj…h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´MfhhÊh²hubj¨)�”}”(hX  "regions:decoder0.0":[ { "region":"region0", "resource":825975898112, "size":549755813888, "type":"ram", "interleave_ways":4, "interleave_granularity":256, "decode_state":"commit", "mappings":[ { "position":3, "memdev":"mem3", "decoder":"decoder8.0" }, { "position":2, "memdev":"mem1", "decoder":"decoder6.0" } { "position":1, "memdev":"mem2", "decoder":"decoder7.0" }, { "position":0, "memdev":"mem0", "decoder":"decoder5.0" } ] } ] } ] } ]”h]”hX  "regions:decoder0.0":[ { "region":"region0", "resource":825975898112, "size":549755813888, "type":"ram", "interleave_ways":4, "interleave_granularity":256, "decode_state":"commit", "mappings":[ { "position":3, "memdev":"mem3", "decoder":"decoder8.0" }, { "position":2, "memdev":"mem1", "decoder":"decoder6.0" } { "position":1, "memdev":"mem2", "decoder":"decoder7.0" }, { "position":0, "memdev":"mem0", "decoder":"decoder5.0" } ] } ] } ] } ]”…”�”}”hjÝsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j§h³hÇh´MmhhÊh²hubeh}”(h]”Œmulti-level-interleave”ah ]”h"]”Œmulti-level interleave”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)�”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”jðjísŒ nametypes”}”jð‰sh}”jíhÊsŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.