€•Ÿk      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”ŒM/translations/zh_CN/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/zh_TW/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/it_IT/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/ja_JP/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/ko_KR/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/pt_BR/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”ŒM/translations/sp_SP/driver-api/cxl/linux/example-configurations/hb-interleave”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³Œg/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/linux/example-configurations/hb-interleave.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒInter-Host-Bridge Interleave”h]”hŒInter-Host-Bridge Interleave”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒGThis cxl-cli configuration dump shows the following host configuration:”h]”hŒGThis cxl-cli configuration dump shows the following host configuration:”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ(A single socket system with one CXL root”h]”hÞ)”}”(hhöh]”hŒ(A single socket system with one CXL root”…””}”(hhøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khhôubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hŒ&CXL Root has Four (4) CXL Host Bridges”h]”hÞ)”}”(hj  h]”hŒ&CXL Root has Four (4) CXL Host Bridges”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K	hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hŒ?Two CXL Host Bridges have a single CXL Memory Expander Attached”h]”hÞ)”}”(hj$  h]”hŒ?Two CXL Host Bridges have a single CXL Memory Expander Attached”…””}”(hj&  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K
hj"  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubhó)”}”(hŒFThe CXL root is configured to interleave across the two host bridges.
”h]”hÞ)”}”(hŒEThe CXL root is configured to interleave across the two host bridges.”h]”hŒEThe CXL root is configured to interleave across the two host bridges.”…””}”(hj=  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj9  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hòhhïh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1híh³hÇh´KhhÊh²hubhÞ)”}”(hŒ‰This output is generated by :code:`cxl list -v` and describes the relationships
between objects exposed in :code:`/sys/bus/cxl/devices/`.”h]”(hŒThis output is generated by ”…””}”(hjY  h²hh³Nh´NubhŒliteral”“”)”}”(hŒ:code:`cxl list -v`”h]”hŒcxl list -v”…””}”(hjc  h²hh³Nh´Nubah}”(h]”h ]”Œcode”ah"]”h$]”h&]”Œlanguage”huh1ja  hjY  ubhŒ< and describes the relationships
between objects exposed in ”…””}”(hjY  h²hh³Nh´Nubjb  )”}”(hŒ:code:`/sys/bus/cxl/devices/`”h]”hŒ/sys/bus/cxl/devices/”…””}”(hjw  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjY  ubhŒ.”…””}”(hjY  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒliteral_block”“”)”}”(hXA  [
  {
      "bus":"root0",
      "provider":"ACPI.CXL",
      "nr_dports":4,
      "dports":[
          {
              "dport":"pci0000:00",
              "alias":"ACPI0016:01",
              "id":0
          },
          {
              "dport":"pci0000:a8",
              "alias":"ACPI0016:02",
              "id":4
          },
          {
              "dport":"pci0000:2a",
              "alias":"ACPI0016:03",
              "id":1
          },
          {
              "dport":"pci0000:d2",
              "alias":"ACPI0016:00",
              "id":5
          }
      ],”h]”hXA  [
  {
      "bus":"root0",
      "provider":"ACPI.CXL",
      "nr_dports":4,
      "dports":[
          {
              "dport":"pci0000:00",
              "alias":"ACPI0016:01",
              "id":0
          },
          {
              "dport":"pci0000:a8",
              "alias":"ACPI0016:02",
              "id":4
          },
          {
              "dport":"pci0000:2a",
              "alias":"ACPI0016:03",
              "id":1
          },
          {
              "dport":"pci0000:d2",
              "alias":"ACPI0016:00",
              "id":5
          }
      ],”…””}”hj’  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´KhhÊh²hubhÞ)”}”(hŒçThis chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
Host Bridges.  The `Root` can be considered the singular upstream port attached
to the platform's memory controller - which routes memory requests to it.”h]”(hŒeThis chunk shows the CXL â€œbusâ€ (root0) has 4 downstream ports attached to CXL
Host Bridges.  The ”…””}”(hj   h²hh³Nh´NubhŒtitle_reference”“”)”}”(hŒ`Root`”h]”hŒRoot”…””}”(hjª  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¨  hj   ubhŒ‚ can be considered the singular upstream port attached
to the platformâ€™s memory controller - which routes memory requests to it.”…””}”(hj   h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K.hhÊh²hubhÞ)”}”(hŒ”The `ports:root0` section lays out how each of these downstream ports are
configured.  If a port is not configured (id's 0 and 1), they are omitted.”h]”(hŒThe ”…””}”(hjÂ  h²hh³Nh´Nubj©  )”}”(hŒ`ports:root0`”h]”hŒports:root0”…””}”(hjÊ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¨  hjÂ  ubhŒ… section lays out how each of these downstream ports are
configured.  If a port is not configured (idâ€™s 0 and 1), they are omitted.”…””}”(hjÂ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K2hhÊh²hubj‘  )”}”(hX  "ports:root0":[
    {
        "port":"port1",
        "host":"pci0000:d2",
        "depth":1,
        "nr_dports":3,
        "dports":[
            {
                "dport":"0000:d2:01.1",
                "alias":"device:02",
                "id":0
            },
            {
                "dport":"0000:d2:01.3",
                "alias":"device:05",
                "id":2
            },
            {
                "dport":"0000:d2:07.1",
                "alias":"device:0d",
                "id":113
            }
        ],”h]”hX  "ports:root0":[
    {
        "port":"port1",
        "host":"pci0000:d2",
        "depth":1,
        "nr_dports":3,
        "dports":[
            {
                "dport":"0000:d2:01.1",
                "alias":"device:02",
                "id":0
            },
            {
                "dport":"0000:d2:01.3",
                "alias":"device:05",
                "id":2
            },
            {
                "dport":"0000:d2:07.1",
                "alias":"device:0d",
                "id":113
            }
        ],”…””}”hjâ  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´K7hhÊh²hubhÞ)”}”(hŒØThis chunk shows the available downstream ports associated with the CXL Host
Bridge :code:`port1`.  In this case, :code:`port1` has 3 available downstream
ports: :code:`dport1`, :code:`dport2`, and :code:`dport113`..”h]”(hŒTThis chunk shows the available downstream ports associated with the CXL Host
Bridge ”…””}”(hjð  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port1`”h]”hŒport1”…””}”(hjø  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjð  ubhŒ.  In this case, ”…””}”(hjð  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port1`”h]”hŒport1”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjð  ubhŒ# has 3 available downstream
ports: ”…””}”(hjð  h²hh³Nh´Nubjb  )”}”(hŒ:code:`dport1`”h]”hŒdport1”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjð  ubhŒ, ”…””}”(hjð  h²hh³Nh´Nubjb  )”}”(hŒ:code:`dport2`”h]”hŒdport2”…””}”(hj1  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjð  ubhŒ, and ”…””}”(hjð  h²hh³Nh´Nubjb  )”}”(hŒ:code:`dport113`”h]”hŒdport113”…””}”(hjD  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjð  ubhŒ..”…””}”(hjð  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KOhhÊh²hubj‘  )”}”(hXâ  "endpoints:port1":[
    {
        "endpoint":"endpoint5",
        "host":"mem0",
        "parent_dport":"0000:d2:01.1",
        "depth":2,
        "memdev":{
            "memdev":"mem0",
            "ram_size":137438953472,
            "serial":0,
            "numa_node":0,
            "host":"0000:d3:00.0"
        },
        "decoders:endpoint5":[
            {
                "decoder":"decoder5.0",
                "resource":825975898112,
                "size":274877906944,
                "interleave_ways":2,
                "interleave_granularity":256,
                "region":"region0",
                "dpa_resource":0,
                "dpa_size":137438953472,
                "mode":"ram"
            }
        ]
    }
],”h]”hXâ  "endpoints:port1":[
    {
        "endpoint":"endpoint5",
        "host":"mem0",
        "parent_dport":"0000:d2:01.1",
        "depth":2,
        "memdev":{
            "memdev":"mem0",
            "ram_size":137438953472,
            "serial":0,
            "numa_node":0,
            "host":"0000:d3:00.0"
        },
        "decoders:endpoint5":[
            {
                "decoder":"decoder5.0",
                "resource":825975898112,
                "size":274877906944,
                "interleave_ways":2,
                "interleave_granularity":256,
                "region":"region0",
                "dpa_resource":0,
                "dpa_size":137438953472,
                "mode":"ram"
            }
        ]
    }
],”…””}”hj]  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´KUhhÊh²hubhÞ)”}”(hŒIThis chunk shows the endpoints attached to the host bridge :code:`port1`.”h]”(hŒ;This chunk shows the endpoints attached to the host bridge ”…””}”(hjk  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port1`”h]”hŒport1”…””}”(hjs  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjk  ubhŒ.”…””}”(hjk  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KrhhÊh²hubhÞ)”}”(hŒ—:code:`endpoint5` contains a single configured decoder :code:`decoder5.0`
which has the same interleave configuration as :code:`region0` (shown later).”h]”(jb  )”}”(hŒ:code:`endpoint5`”h]”hŒ	endpoint5”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjŒ  ubhŒ& contains a single configured decoder ”…””}”(hjŒ  h²hh³Nh´Nubjb  )”}”(hŒ:code:`decoder5.0`”h]”hŒ
decoder5.0”…””}”(hj£  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjŒ  ubhŒ0
which has the same interleave configuration as ”…””}”(hjŒ  h²hh³Nh´Nubjb  )”}”(hŒ:code:`region0`”h]”hŒregion0”…””}”(hj¶  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjŒ  ubhŒ (shown later).”…””}”(hjŒ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KthhÊh²hubhÞ)”}”(hŒ7Next we have the decodesr belonging to the host bridge:”h]”hŒ7Next we have the decodesr belonging to the host bridge:”…””}”(hjÏ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KwhhÊh²hubj‘  )”}”(hX×      "decoders:port1":[
        {
            "decoder":"decoder1.0",
            "resource":825975898112,
            "size":274877906944,
            "interleave_ways":1,
            "region":"region0",
            "nr_targets":1,
            "targets":[
                {
                    "target":"0000:d2:01.1",
                    "alias":"device:02",
                    "position":0,
                    "id":0
                }
            ]
        }
    ]
},”h]”hX×      "decoders:port1":[
        {
            "decoder":"decoder1.0",
            "resource":825975898112,
            "size":274877906944,
            "interleave_ways":1,
            "region":"region0",
            "nr_targets":1,
            "targets":[
                {
                    "target":"0000:d2:01.1",
                    "alias":"device:02",
                    "position":0,
                    "id":0
                }
            ]
        }
    ]
},”…””}”hjÝ  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´K{hhÊh²hubhÞ)”}”(hŒ’Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose only
target is :code:`dport1` - which is attached to :code:`endpoint5`.”h]”(hŒHost Bridge ”…””}”(hjë  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port1`”h]”hŒport1”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjë  ubhŒ has a single decoder (”…””}”(hjë  h²hh³Nh´Nubjb  )”}”(hŒ:code:`decoder1.0`”h]”hŒ
decoder1.0”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjë  ubhŒ), whose only
target is ”…””}”(hjë  h²hh³Nh´Nubjb  )”}”(hŒ:code:`dport1`”h]”hŒdport1”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjë  ubhŒ - which is attached to ”…””}”(hjë  h²hh³Nh´Nubjb  )”}”(hŒ:code:`endpoint5`”h]”hŒ	endpoint5”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjë  ubhŒ.”…””}”(hjë  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hŒ†The following chunk shows a similar configuration for Host Bridge :code:`port3`,
the second host bridge with a memory device attached.”h]”(hŒBThe following chunk shows a similar configuration for Host Bridge ”…””}”(hjE  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port3`”h]”hŒport3”…””}”(hjM  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hjE  ubhŒ7,
the second host bridge with a memory device attached.”…””}”(hjE  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K’hhÊh²hubj‘  )”}”(hXý  {
    "port":"port3",
    "host":"pci0000:a8",
    "depth":1,
    "nr_dports":1,
    "dports":[
        {
            "dport":"0000:a8:01.1",
            "alias":"device:c3",
            "id":0
        }
    ],
    "endpoints:port3":[
        {
            "endpoint":"endpoint6",
            "host":"mem1",
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                "serial":0,
                "numa_node":0,
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                    "target":"0000:a8:01.1",
                    "alias":"device:c3",
                    "position":0,
                    "id":0
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},”h]”hXý  {
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    "depth":1,
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    "dports":[
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            "memdev":{
                "memdev":"mem1",
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                "serial":0,
                "numa_node":0,
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            "decoders:endpoint6":[
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                    "mode":"ram"
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    "decoders:port3":[
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            "interleave_ways":1,
            "region":"region0",
            "nr_targets":1,
            "targets":[
                {
                    "target":"0000:a8:01.1",
                    "alias":"device:c3",
                    "position":0,
                    "id":0
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},”…””}”hjf  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´K—hhÊh²hubhÞ)”}”(hŒIThe next chunk shows the two CXL host bridges without attached endpoints.”h]”hŒIThe next chunk shows the two CXL host bridges without attached endpoints.”…””}”(hjt  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÔhhÊh²hubj‘  )”}”(hX–      {
        "port":"port2",
        "host":"pci0000:00",
        "depth":1,
        "nr_dports":2,
        "dports":[
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                "id":113
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    {
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        "depth":1,
        "nr_dports":1,
        "dports":[
            {
                "dport":"0000:2a:01.1",
                "alias":"device:d0",
                "id":0
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        ]
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],”h]”hX–      {
        "port":"port2",
        "host":"pci0000:00",
        "depth":1,
        "nr_dports":2,
        "dports":[
            {
                "dport":"0000:00:01.3",
                "alias":"device:55",
                "id":2
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            {
                "dport":"0000:00:07.1",
                "alias":"device:5d",
                "id":113
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        ]
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    {
        "port":"port4",
        "host":"pci0000:2a",
        "depth":1,
        "nr_dports":1,
        "dports":[
            {
                "dport":"0000:2a:01.1",
                "alias":"device:d0",
                "id":0
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        ]
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],”…””}”hj‚  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´KØhhÊh²hubhÞ)”}”(hŒÅNext we have the `Root Decoders` belonging to :code:`root0`.  This root decoder
applies the interleave across the downstream ports :code:`port1` and
:code:`port3` - with a granularity of 256 bytes.”h]”(hŒNext we have the ”…””}”(hj  h²hh³Nh´Nubj©  )”}”(hŒ`Root Decoders`”h]”hŒRoot Decoders”…””}”(hj˜  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¨  hj  ubhŒ belonging to ”…””}”(hj  h²hh³Nh´Nubjb  )”}”(hŒ:code:`root0`”h]”hŒroot0”…””}”(hjª  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hj  ubhŒH.  This root decoder
applies the interleave across the downstream ports ”…””}”(hj  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port1`”h]”hŒport1”…””}”(hj½  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hj  ubhŒ and
”…””}”(hj  h²hh³Nh´Nubjb  )”}”(hŒ:code:`port3`”h]”hŒport3”…””}”(hjÐ  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hj  ubhŒ# - with a granularity of 256 bytes.”…””}”(hj  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KùhhÊh²hubhÞ)”}”(hŒLThis information is generated by the CXL driver reading the ACPI CEDT CMFWS.”h]”hŒLThis information is generated by the CXL driver reading the ACPI CEDT CMFWS.”…””}”(hjé  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KýhhÊh²hubj‘  )”}”(hXr  "decoders:root0":[
    {
        "decoder":"decoder0.0",
        "resource":825975898112,
        "size":274877906944,
        "interleave_ways":2,
        "interleave_granularity":256,
        "max_available_extent":0,
        "volatile_capable":true,
        "nr_targets":2,
        "targets":[
            {
                "target":"pci0000:a8",
                "alias":"ACPI0016:02",
                "position":1,
                "id":4
            },
            {
                "target":"pci0000:d2",
                "alias":"ACPI0016:00",
                "position":0,
                "id":5
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        ],”h]”hXr  "decoders:root0":[
    {
        "decoder":"decoder0.0",
        "resource":825975898112,
        "size":274877906944,
        "interleave_ways":2,
        "interleave_granularity":256,
        "max_available_extent":0,
        "volatile_capable":true,
        "nr_targets":2,
        "targets":[
            {
                "target":"pci0000:a8",
                "alias":"ACPI0016:02",
                "position":1,
                "id":4
            },
            {
                "target":"pci0000:d2",
                "alias":"ACPI0016:00",
                "position":0,
                "id":5
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        ],”…””}”hj÷  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´MhhÊh²hubhÞ)”}”(hŒ­Finally we have the `Memory Region` associated with the `Root Decoder`
:code:`decoder0.0`.  This region describes the overall interleave configuration
of the interleave set.”h]”(hŒFinally we have the ”…””}”(hj  h²hh³Nh´Nubj©  )”}”(hŒ`Memory Region`”h]”hŒMemory Region”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¨  hj  ubhŒ associated with the ”…””}”(hj  h²hh³Nh´Nubj©  )”}”(hŒ`Root Decoder`”h]”hŒRoot Decoder”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j¨  hj  ubhŒ
”…””}”(hj  h²hh³Nh´Nubjb  )”}”(hŒ:code:`decoder0.0`”h]”hŒ
decoder0.0”…””}”(hj1  h²hh³Nh´Nubah}”(h]”h ]”jn  ah"]”h$]”h&]”Œlanguage”huh1ja  hj  ubhŒT.  This region describes the overall interleave configuration
of the interleave set.”…””}”(hj  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´MhhÊh²hubj‘  )”}”(hXx                "regions:decoder0.0":[
                  {
                      "region":"region0",
                      "resource":825975898112,
                      "size":274877906944,
                      "type":"ram",
                      "interleave_ways":2,
                      "interleave_granularity":256,
                      "decode_state":"commit",
                      "mappings":[
                          {
                              "position":1,
                              "memdev":"mem1",
                              "decoder":"decoder6.0"
                          },
                          {
                              "position":0,
                              "memdev":"mem0",
                              "decoder":"decoder5.0"
                          }
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              ]
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]”h]”hXx                "regions:decoder0.0":[
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                      "region":"region0",
                      "resource":825975898112,
                      "size":274877906944,
                      "type":"ram",
                      "interleave_ways":2,
                      "interleave_granularity":256,
                      "decode_state":"commit",
                      "mappings":[
                          {
                              "position":1,
                              "memdev":"mem1",
                              "decoder":"decoder6.0"
                          },
                          {
                              "position":0,
                              "memdev":"mem0",
                              "decoder":"decoder5.0"
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