~]sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget7/translations/zh_CN/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/zh_TW/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/it_IT/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/ja_JP/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/ko_KR/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget7/translations/sp_SP/driver-api/cxl/devices/device-typesmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhQ/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/devices/device-types.rsthKubhsection)}(hhh](htitle)}(hDevices and Protocolsh]hDevices and Protocols}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe type of CXL device (Memory, Accelerator, etc) dictates many configuration steps. This section covers some basic background on device types and on-device resources used by the platform and OS which impact configuration.h]hThe type of CXL device (Memory, Accelerator, etc) dictates many configuration steps. This section covers some basic background on device types and on-device resources used by the platform and OS which impact configuration.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h Protocolsh]h Protocols}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhK ubh)}(hThere are three core protocols to CXL. For the purpose of this documentation, we will only discuss very high level definitions as the specific hardware details are largely abstracted away from Linux. See the CXL specification for more details.h]hThere are three core protocols to CXL. For the purpose of this documentation, we will only discuss very high level definitions as the specific hardware details are largely abstracted away from Linux. See the CXL specification for more details.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hCXL.ioh]hCXL.io}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hThe basic interaction protocol, similar to PCIe configuration mechanisms. Typically used for initialization, configuration, and I/O access for anything other than memory (CXL.mem) or cache (CXL.cache) operations.h]hThe basic interaction protocol, similar to PCIe configuration mechanisms. Typically used for initialization, configuration, and I/O access for anything other than memory (CXL.mem) or cache (CXL.cache) operations.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe Linux CXL driver exposes access to .io functionalty via the various sysfs interfaces and /dev/cxl/ devices (which exposes direct access to device mailboxes).h]hThe Linux CXL driver exposes access to .io functionalty via the various sysfs interfaces and /dev/cxl/ devices (which exposes direct access to device mailboxes).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h]cxl-ioah ]h"]cxl.ioah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h CXL.cacheh]h CXL.cache}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhhhKubh)}(hLThe mechanism by which a device may coherently access and cache host memory.h]hLThe mechanism by which a device may coherently access and cache host memory.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj-hhubh)}(h-Largely transparent to Linux once configured.h]h-Largely transparent to Linux once configured.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hj-hhubeh}(h] cxl-cacheah ]h"] cxl.cacheah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hCXL.memh]hCXL.mem}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhhhhhK$ubh)}(hMThe mechanism by which the CPU may coherently access and cache device memory.h]hMThe mechanism by which the CPU may coherently access and cache device memory.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjbhhubh)}(h-Largely transparent to Linux once configured.h]h-Largely transparent to Linux once configured.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjbhhubeh}(h]cxl-memah ]h"]cxl.memah$]h&]uh1hhhhhhhhK$ubeh}(h] protocolsah ]h"] protocolsah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(h Device Typesh]h Device Types}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK+ubh)}(hhh](h)}(hType-1h]hType-1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK.ubh)}(hA Type-1 CXL device:h]hA Type-1 CXL device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjhhubh bullet_list)}(hhh](h list_item)}(h'Supports cxl.io and cxl.cache protocolsh]h)}(hjh]h'Supports cxl.io and cxl.cache protocols}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h!Implements a fully coherent cacheh]h)}(hjh]h!Implements a fully coherent cache}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h:Allows Device-to-Host coherence and Host-to-Device snoops.h]h)}(hjh]h:Allows Device-to-Host coherence and Host-to-Device snoops.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h/Does NOT have host-managed device memory (HDM) h]h)}(h.Does NOT have host-managed device memory (HDM)h]h.Does NOT have host-managed device memory (HDM)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet*uh1jhhhK2hjhhubh)}(hTypical examples of type-1 devices is a Smart NIC - which may want to directly operate on host-memory (DMA) to store incoming packets. These devices largely rely on CPU-attached memory.h]hTypical examples of type-1 devices is a Smart NIC - which may want to directly operate on host-memory (DMA) to store incoming packets. These devices largely rely on CPU-attached memory.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjhhubeh}(h]type-1ah ]h"]type-1ah$]h&]uh1hhjhhhhhK.ubh)}(hhh](h)}(hType-2h]hType-2}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhKhjQhhubj)}(hhh](j)}(h1Supports cxl.io, cxl.cache, and cxl.mem protocolsh]h)}(hjuh]h1Supports cxl.io, cxl.cache, and cxl.mem protocols}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjsubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(hCOptionally implements coherent cache and Host-Managed Device Memoryh]h)}(hjh]hCOptionally implements coherent cache and Host-Managed Device Memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(h=Is typically an accelerator device w/ high bandwidth memory. h]h)}(h`.h](hX(A Multi-Headed Single-Logical Device (MHSLD) exposes a single logical device to multiple heads which may be connected to one or more discrete hosts. An example of this would be a simple memory-pool which may be statically configured (prior to boot) to expose portions of its memory to Linux via }(hjhhhNhNubh)}(h#:doc:`CEDT <../platform/acpi/cedt>`h]hinline)}(hjh]hCEDT}(hjhhhNhNubah}(h]h ](xrefstdstd-doceh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc#driver-api/cxl/devices/device-types refdomainjreftypedoc refexplicitrefwarn reftarget../platform/acpi/cedtuh1hhhhKrhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKrhjhhubeh}(h]mhsldah ]h"]mhsldah$]h&]uh1hhjhhhhhKqubh)}(hhh](h)}(hMHMLDh]hMHMLD}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhKyubh)}(hXA Multi-Headed Multi-Logical Device (MHMLD) exposes multiple logical devices to multiple heads which may be connected to one or more discrete hosts. An example of this would be a Dynamic Capacity Device or which may be configured at runtime to expose portions of its memory to Linux.h]hXA Multi-Headed Multi-Logical Device (MHMLD) exposes multiple logical devices to multiple heads which may be connected to one or more discrete hosts. An example of this would be a Dynamic Capacity Device or which may be configured at runtime to expose portions of its memory to Linux.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhj5hhubeh}(h]mhmldah ]h"]mhmldah$]h&]uh1hhjhhhhhKyubeh}(h]logical-devices-and-headsah ]h"]logical devices and headsah$]h&]uh1hhjhhhhhKaubeh}(h] device-typesah ]h"] device typesah$]h&]uh1hhhhhhhhK+ubh)}(hhh](h)}(hExample Devicesh]hExample Devices}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhhhhhKubh)}(hhh](h)}(hMemory Expanderh]hMemory Expander}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}hhhhhKubh)}(hThe simplest form of Type-3 device is a memory expander. A memory expander exposes Host-Managed Device Memory (HDM) to Linux. This memory may be Volatile or Non-Volatile (Persistent).h]hThe simplest form of Type-3 device is a memory expander. A memory expander exposes Host-Managed Device Memory (HDM) to Linux. This memory may be Volatile or Non-Volatile (Persistent).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubh)}(hMemory Expanders will typically be considered a form of Single-Headed, Single-Logical Device - as its form factor will typically be an add-in-card (AIC) or some other similar form-factor.h]hMemory Expanders will typically be considered a form of Single-Headed, Single-Logical Device - as its form factor will typically be an add-in-card (AIC) or some other similar form-factor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubh)}(hXThe Linux CXL driver provides support for static or dynamic configuration of basic memory expanders. The platform may program decoders prior to OS init (e.g. auto-decoders), or the user may program the fabric if the platform defers these operations to the OS.h]hXThe Linux CXL driver provides support for static or dynamic configuration of basic memory expanders. The platform may program decoders prior to OS init (e.g. auto-decoders), or the user may program the fabric if the platform defers these operations to the OS.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubh)}(hXMultiple Memory Expanders may be added to an external chassis and exposed to a host via a head attached to a CXL switch. This is a "memory pool", and would be considered an MHSLD or MHMLD depending on the management capabilities provided by the switch platform.h]hX Multiple Memory Expanders may be added to an external chassis and exposed to a host via a head attached to a CXL switch. This is a “memory pool”, and would be considered an MHSLD or MHMLD depending on the management capabilities provided by the switch platform.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubh)}(hdAs of v6.14, Linux does not provide a formalized interface to manage non-DCD MHSLD or MHMLD devices.h]hdAs of v6.14, Linux does not provide a formalized interface to manage non-DCD MHSLD or MHMLD devices.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}hhubeh}(h]memory-expanderah ]h"]memory expanderah$]h&]uh1hhjlhhhhhKubh)}(hhh](h)}(hDynamic Capacity Device (DCD)h]hDynamic Capacity Device (DCD)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX0A Dynamic Capacity Device is a Type-3 device which provides dynamic management of memory capacity. The basic premise of a DCD to provide an allocator-like interface for physical memory capacity to a "Fabric Manager" (an external, privileged host with privileges to change configurations for other hosts).h]hX4A Dynamic Capacity Device is a Type-3 device which provides dynamic management of memory capacity. The basic premise of a DCD to provide an allocator-like interface for physical memory capacity to a “Fabric Manager” (an external, privileged host with privileges to change configurations for other hosts).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hA DCD manages "Memory Extents", which may be volatile or persistent. Extents may also be exclusive to a single host or shared across multiple hosts.h]hA DCD manages “Memory Extents”, which may be volatile or persistent. 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