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De Francesco, Intel”h]”hï)”}”(hjGh]”hŒFabio M. De Francesco, Intel”…””}”(hjIh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhjEubah}”(h]”h ]”h"]”h$]”h&]”uh1jChj@h²hh³hÇh´NubjD)”}”(hŒDan J. Williams, Intel”h]”hï)”}”(hj^h]”hŒDan J. Williams, Intel”…””}”(hj`h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khj\ubah}”(h]”h ]”h"]”h$]”h&]”uh1jChj@h²hh³hÇh´NubjD)”}”(hŒMahesh Natu, Intel ”h]”hï)”}”(hŒMahesh Natu, Intel”h]”hŒMahesh Natu, Intel”…””}”(hjwh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khjsubah}”(h]”h ]”h"]”h$]”h&]”uh1jChj@h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j>h³hÇh´Khj-h²hubeh}”(h]”Œcreator-contributors”ah ]”h"]”Œcreator/contributors”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒSummary of the Change”h]”hŒSummary of the Change”…””}”(hjžh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj›h²hh³hÇh´Kubhï)”}”(hX4According to the current Compute Express Link (CXL) Specifications (Revision 3.2, Version 1.0), the CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host Physical Address (HPA) windows associated with each CXL Host Bridge. Each window represents a contiguous HPA range that may be interleaved across one or more targets, including CXL Host Bridges. Each window has a set of restrictions that govern its usage. It is the Operating System-directed configuration and Power Management (OSPM) responsibility to utilize each window for the specified use.”h]”hX4According to the current Compute Express Link (CXL) Specifications (Revision 3.2, Version 1.0), the CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host Physical Address (HPA) windows associated with each CXL Host Bridge. Each window represents a contiguous HPA range that may be interleaved across one or more targets, including CXL Host Bridges. Each window has a set of restrictions that govern its usage. It is the Operating System-directed configuration and Power Management (OSPM) responsibility to utilize each window for the specified use.”…””}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khj›h²hubhï)”}”(hŒêTable 9-22 of the current CXL Specifications states that the Window Size field contains the total number of consecutive bytes of HPA this window describes. This value must be a multiple of the Number of Interleave Ways (NIW) * 256 MB.”h]”hŒêTable 9-22 of the current CXL Specifications states that the Window Size field contains the total number of consecutive bytes of HPA this window describes. This value must be a multiple of the Number of Interleave Ways (NIW) * 256 MB.”…””}”(hjºh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K#hj›h²hubhï)”}”(hŒÙPlatform Firmware (BIOS) might reserve physical addresses below 4 GB where a memory gap such as the Low Memory Hole for PCIe MMIO may exist. In such cases, the CFMWS Range Size may not adhere to the NIW * 256 MB rule.”h]”hŒÙPlatform Firmware (BIOS) might reserve physical addresses below 4 GB where a memory gap such as the Low Memory Hole for PCIe MMIO may exist. In such cases, the CFMWS Range Size may not adhere to the NIW * 256 MB rule.”…””}”(hjÈh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K'hj›h²hubhï)”}”(hX*The HPA represents the actual physical memory address space that the CXL devices can decode and respond to, while the System Physical Address (SPA), a related but distinct concept, represents the system-visible address space that users can direct transaction to and so it excludes reserved regions.”h]”hX*The HPA represents the actual physical memory address space that the CXL devices can decode and respond to, while the System Physical Address (SPA), a related but distinct concept, represents the system-visible address space that users can direct transaction to and so it excludes reserved regions.”…””}”(hjÖh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K+hj›h²hubhï)”}”(hXBIOS publishes CFMWS to communicate the active SPA ranges that, on platforms with LMH's, map to a strict subset of the HPA. The SPA range trims out the hole, resulting in lost capacity in the Endpoints with no SPA to map to that part of the HPA range that intersects the hole.”h]”hXBIOS publishes CFMWS to communicate the active SPA ranges that, on platforms with LMH’s, map to a strict subset of the HPA. The SPA range trims out the hole, resulting in lost capacity in the Endpoints with no SPA to map to that part of the HPA range that intersects the hole.”…””}”(hjäh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K0hj›h²hubhï)”}”(hŒ@E.g, an x86 platform with two CFMWS and an LMH starting at 2 GB:”h]”hŒ@E.g, an x86 platform with two CFMWS and an LMH starting at 2 GB:”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K5hj›h²hubhŒ block_quote”“”)”}”(hXz+--------+------------+-------------------+------------------+-------------------+------+ | Window | CFMWS Base | CFMWS Size | HDM Decoder Base | HDM Decoder Size | Ways | +========+============+===================+==================+===================+======+ | â€0 | 0 GB | 2 GB | 0 GB | 3 GB | 12 | +--------+------------+-------------------+------------------+-------------------+------+ | â€1 | 4 GB | NIW*256MB Aligned | 4 GB | NIW*256MB Aligned | 12 | +--------+------------+-------------------+------------------+-------------------+------+ ”h]”hŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K uh1jhj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jhj ubhŒthead”“”)”}”(hhh]”hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hï)”}”(hŒWindow”h]”hŒWindow”…””}”(hj]h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hjZubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubjY)”}”(hhh]”hï)”}”(hŒ CFMWS Base”h]”hŒ CFMWS Base”…””}”(hjth²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hjqubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubjY)”}”(hhh]”hï)”}”(hŒ CFMWS Size”h]”hŒ CFMWS Size”…””}”(hj‹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hjˆubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubjY)”}”(hhh]”hï)”}”(hŒHDM Decoder Base”h]”hŒHDM Decoder Base”…””}”(hj¢h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hjŸubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubjY)”}”(hhh]”hï)”}”(hŒHDM Decoder Size”h]”hŒHDM Decoder Size”…””}”(hj¹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hj¶ubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubjY)”}”(hhh]”hï)”}”(hŒWays”h]”hŒWays”…””}”(hjÐh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K8hjÍubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjUubeh}”(h]”h ]”h"]”h$]”h&]”uh1jShjPubah}”(h]”h ]”h"]”h$]”h&]”uh1jNhj ubhŒtbody”“”)”}”(hhh]”(jT)”}”(hhh]”(jY)”}”(hhh]”hï)”}”(hŒ0”h]”hŒ0”…””}”(hjûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hjøubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubjY)”}”(hhh]”hï)”}”(hŒ0 GB”h]”hŒ0 GB”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubjY)”}”(hhh]”hï)”}”(hŒ2 GB”h]”hŒ2 GB”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hj&ubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubjY)”}”(hhh]”hï)”}”(hŒ0 GB”h]”hŒ0 GB”…””}”(hj@h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hj=ubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubjY)”}”(hhh]”hï)”}”(hŒ3 GB”h]”hŒ3 GB”…””}”(hjWh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hjTubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubjY)”}”(hhh]”hï)”}”(hŒ12”h]”hŒ12”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K:hjkubah}”(h]”h ]”h"]”h$]”h&]”uh1jXhjõubeh}”(h]”h ]”h"]”h$]”h&]”uh1jShjòubjT)”}”(hhh]”(jY)”}”(hhh]”hï)”}”(hŒ1”h]”hŒ1”…””}”(hjŽh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K”h]”(hŒ>Compute Express Link Specification Revision 3.2, Version 1.0 <”…””}”(hj2h²hh³Nh´NubhŒ reference”“”)”}”(hŒ#https://www.computeexpresslink.org/”h]”hŒ#https://www.computeexpresslink.org/”…””}”(hj<h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j>uh1j:hj2ubhŒ>”…””}”(hj2h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kthj!h²hubeh}”(h]”Œ references”ah ]”h"]”Œ references”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KrubhÉ)”}”(hhh]”(hÎ)”}”(hŒ"Detailed Description of the Change”h]”hŒ"Detailed Description of the Change”…””}”(hj`h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj]h²hh³hÇh´Kxubhï)”}”(hŒÖThe description of the Window Size field in table 9-22 needs to account for platforms with Low Memory Holes, where SPA ranges might be subsets of the endpoints HPA. Therefore, it has to be changed to the following:”h]”hŒÖThe description of the Window Size field in table 9-22 needs to account for platforms with Low Memory Holes, where SPA ranges might be subsets of the endpoints HPA. Therefore, it has to be changed to the following:”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kzhj]h²hubhï)”}”(hŒu"The total number of consecutive bytes of HPA this window represents. This value shall be a multiple of NIW * 256 MB.”h]”hŒw“The total number of consecutive bytes of HPA this window represents. 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