Jsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget6/translations/zh_CN/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/zh_TW/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/it_IT/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ja_JP/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/ko_KR/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/pt_BR/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget6/translations/sp_SP/driver-api/cxl/conventions/cxl-atlmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhP/var/lib/git/docbuild/linux/Documentation/driver-api/cxl/conventions/cxl-atl.rsthKubhsection)}(hhh](htitle)}(h ACPI PRM CXL Address Translationh]h ACPI PRM CXL Address Translation}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDocumenth]hDocument}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hCXL Revision 3.2, Version 1.0h]hCXL Revision 3.2, Version 1.0}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]documentah ]h"]documentah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hLicenseh]hLicense}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(h"SPDX-License Identifier: CC-BY-4.0h]h"SPDX-License Identifier: CC-BY-4.0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]licenseah ]h"]licenseah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hCreator/Contributorsh]hCreator/Contributors}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhhhKubh bullet_list)}(hhh]h list_item)}(hRobert Richter, AMD et al. h]h)}(hRobert Richter, AMD et al.h]hRobert Richter, AMD et al.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjEubah}(h]h ]h"]h$]h&]uh1jChj@hhhhhNubah}(h]h ]h"]h$]h&]bullet-uh1j>hhhKhj-hhubeh}(h]creator-contributorsah ]h"]creator/contributorsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSummary of the Changeh]hSummary of the Change}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjmhhhhhKubh)}(hXdThe CXL Fixed Memory Window Structures (CFMWS) describe zero or more Host Physical Address (HPA) windows associated with one or more CXL Host Bridges. Each HPA range of a CXL Host Bridge is represented by a CFMWS entry. An HPA range may include addresses currently assigned to CXL.mem devices, or an OS may assign ranges from an address window to a device.h]hXdThe CXL Fixed Memory Window Structures (CFMWS) describe zero or more Host Physical Address (HPA) windows associated with one or more CXL Host Bridges. Each HPA range of a CXL Host Bridge is represented by a CFMWS entry. An HPA range may include addresses currently assigned to CXL.mem devices, or an OS may assign ranges from an address window to a device.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubh)}(hXjHost-managed Device Memory is Device-attached memory that is mapped to system coherent address space and accessible to the Host using standard write-back semantics. The managed address range is configured in the CXL HDM Decoder registers of the device. An HDM Decoder in a device is responsible for converting HPA into DPA by stripping off specific address bits.h]hXjHost-managed Device Memory is Device-attached memory that is mapped to system coherent address space and accessible to the Host using standard write-back semantics. The managed address range is configured in the CXL HDM Decoder registers of the device. An HDM Decoder in a device is responsible for converting HPA into DPA by stripping off specific address bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubh)}(hCXL devices and CXL bridges use the same HPA space. It is common across all components that belong to the same host domain. The view of the address region must be consistent on the CXL.mem path between the Host and the Device.h]hCXL devices and CXL bridges use the same HPA space. It is common across all components that belong to the same host domain. The view of the address region must be consistent on the CXL.mem path between the Host and the Device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjmhhubh)}(hqThis is described in the *CXL 3.2 specification* (Table 1-1, 3.3.1, 8.2.4.20, 9.13.1, 9.18.1.3). [#cxl-spec-3.2]_h](hThis is described in the }(hjhhhNhNubhemphasis)}(h*CXL 3.2 specification*h]hCXL 3.2 specification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh1 (Table 1-1, 3.3.1, 8.2.4.20, 9.13.1, 9.18.1.3). }(hjhhhNhNubhfootnote_reference)}(h[#cxl-spec-3.2]_h]h1}(hjhhhNhNubah}(h]id1ah ]h"]h$]h&]autoKrefid cxl-spec-3-2docname"driver-api/cxl/conventions/cxl-atluh1jhjresolvedKubeh}(h]h ]h"]h$]h&]uh1hhhhK(hjmhhubh)}(hXTDepending on the interconnect architecture of the platform, components attached to a host may not share the same host physical address space. Those platforms need address translation to convert an HPA between the host and the attached component, such as a CXL device. The translation mechanism is host-specific and implementation dependent.h]hXTDepending on the interconnect architecture of the platform, components attached to a host may not share the same host physical address space. Those platforms need address translation to convert an HPA between the host and the attached component, such as a CXL device. The translation mechanism is host-specific and implementation dependent.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjmhhubh)}(hX`For example, x86 AMD platforms use a Data Fabric that manages access to physical memory. Devices have their own memory space and can be configured to use 'Normalized addresses' different from System Physical Addresses (SPA). Address translation is then needed. For details, see :doc:`x86 AMD Address Translation `.h](hXFor example, x86 AMD platforms use a Data Fabric that manages access to physical memory. Devices have their own memory space and can be configured to use ‘Normalized addresses’ different from System Physical Addresses (SPA). Address translation is then needed. For details, see }(hjhhhNhNubh)}(hI:doc:`x86 AMD Address Translation `h]hinline)}(hjh]hx86 AMD Address Translation}(hjhhhNhNubah}(h]h ](xrefstdstd-doceh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftypedoc refexplicitrefwarn reftarget$/admin-guide/RAS/address-translationuh1hhhhK1hjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjmhhubh)}(hXThose AMD platforms provide PRM [#prm-spec]_ handlers in firmware to perform various types of address translation, including for CXL endpoints. AMD Zen5 systems implement the ACPI PRM CXL Address Translation firmware call. The ACPI PRM handler has a specific GUID to uniquely identify platforms with support for Normalized addressing. This is documented in the *ACPI v6.5 Porting Guide* (Address Translation - CXL DPA to System Physical Address). [#amd-ppr-58088]_h](h Those AMD platforms provide PRM }(hj%hhhNhNubj)}(h [#prm-spec]_h]h3}(hj-hhhNhNubah}(h]id2ah ]h"]h$]h&]jKjprm-specjjuh1jhj%jKubhX= handlers in firmware to perform various types of address translation, including for CXL endpoints. AMD Zen5 systems implement the ACPI PRM CXL Address Translation firmware call. The ACPI PRM handler has a specific GUID to uniquely identify platforms with support for Normalized addressing. This is documented in the }(hj%hhhNhNubj)}(h*ACPI v6.5 Porting Guide*h]hACPI v6.5 Porting Guide}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh= (Address Translation - CXL DPA to System Physical Address). }(hj%hhhNhNubj)}(h[#amd-ppr-58088]_h]h2}(hjShhhNhNubah}(h]id3ah ]h"]h$]h&]jKj amd-ppr-58088jjuh1jhj%jKubeh}(h]h ]h"]h$]h&]uh1hhhhK7hjmhhubh)}(hXWhen in Normalized address mode, HDM decoder address ranges must be configured and handled differently. Hardware addresses used in the HDM decoder configurations of an endpoint are not SPA and need to be translated from the address range of the endpoint to that of the CXL host bridge. This is especially important for finding an endpoint's associated CXL Host Bridge and HPA window described in the CFMWS. Additionally, the interleave decoding is done by the Data Fabric and the endpoint does not perform decoding when converting HPA to DPA. Instead, interleaving is switched off for the endpoint (1-way). Finally, address translation might also be needed to inspect the endpoint's hardware addresses, such as during profiling, tracing, or error handling.h]hXWhen in Normalized address mode, HDM decoder address ranges must be configured and handled differently. Hardware addresses used in the HDM decoder configurations of an endpoint are not SPA and need to be translated from the address range of the endpoint to that of the CXL host bridge. This is especially important for finding an endpoint’s associated CXL Host Bridge and HPA window described in the CFMWS. Additionally, the interleave decoding is done by the Data Fabric and the endpoint does not perform decoding when converting HPA to DPA. Instead, interleaving is switched off for the endpoint (1-way). Finally, address translation might also be needed to inspect the endpoint’s hardware addresses, such as during profiling, tracing, or error handling.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjmhhubh)}(hPFor example, with Normalized addressing the HDM decoders could look as follows::h]hOFor example, with Normalized addressing the HDM decoders could look as follows:}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjmhhubh literal_block)}(hX ------------------------------- | Root Decoder (CFMWS) | | SPA Range: 0x850000000 | | Size: 0x8000000000 (512 GB) | | Interleave Ways: 1 | ------------------------------- | v ------------------------------- | Host Bridge Decoder (HDM) | | SPA Range: 0x850000000 | | Size: 0x8000000000 (512 GB) | | Interleave Ways: 4 | | Targets: endpoint5,8,11,13 | | Granularity: 256 | ------------------------------- | -----------------------------+------------------------------ | | | | v v v v ------------------- ------------------- ------------------- ------------------- | endpoint5 | | endpoint8 | | endpoint11 | | endpoint13 | | decoder5.0 | | decoder8.0 | | decoder11.0 | | decoder13.0 | | PCIe: | | PCIe: | | PCIe: | | PCIe: | | 0000:e2:00.0 | | 0000:e3:00.0 | | 0000:e4:00.0 | | 0000:e1:00.0 | | DPA: | | DPA: | | DPA: | | DPA: | | Start: 0x0 | | Start: 0x0 | | Start: 0x0 | | Start: 0x0 | | Size: | | Size: | | Size: | | Size: | | 0x2000000000 | | 0x2000000000 | | 0x2000000000 | | 0x2000000000 | | (128 GB) | | (128 GB) | | (128 GB) | | (128 GB) | | Interleaving: | | Interleaving: | | Interleaving: | | Interleaving: | | Ways: 1 | | Ways: 1 | | Ways: 1 | | Ways: 1 | | Gran: 256 | | Gran: 256 | | Gran: 256 | | Gran: 256 | ------------------- ------------------- ------------------- ------------------- | | | | v v v v DPA DPA DPA DPAh]hX ------------------------------- | Root Decoder (CFMWS) | | SPA Range: 0x850000000 | | Size: 0x8000000000 (512 GB) | | Interleave Ways: 1 | ------------------------------- | v ------------------------------- | Host Bridge Decoder (HDM) | | SPA Range: 0x850000000 | | Size: 0x8000000000 (512 GB) | | Interleave Ways: 4 | | Targets: endpoint5,8,11,13 | | Granularity: 256 | ------------------------------- | -----------------------------+------------------------------ | | | | v v v v ------------------- ------------------- ------------------- ------------------- | endpoint5 | | endpoint8 | | endpoint11 | | endpoint13 | | decoder5.0 | | decoder8.0 | | decoder11.0 | | decoder13.0 | | PCIe: | | PCIe: | | PCIe: | | PCIe: | | 0000:e2:00.0 | | 0000:e3:00.0 | | 0000:e4:00.0 | | 0000:e1:00.0 | | DPA: | | DPA: | | DPA: | | DPA: | | Start: 0x0 | | Start: 0x0 | | Start: 0x0 | | Start: 0x0 | | Size: | | Size: | | Size: | | Size: | | 0x2000000000 | | 0x2000000000 | | 0x2000000000 | | 0x2000000000 | | (128 GB) | | (128 GB) | | (128 GB) | | (128 GB) | | Interleaving: | | Interleaving: | | Interleaving: | | Interleaving: | | Ways: 1 | | Ways: 1 | | Ways: 1 | | Ways: 1 | | Gran: 256 | | Gran: 256 | | Gran: 256 | | Gran: 256 | ------------------- ------------------- ------------------- ------------------- | | | | v v v v DPA DPA DPA DPA}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKKhjmhhubh)}(h'This shows the representation in sysfs:h]h'This shows the representation in sysfs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjmhhubj)}(hX/sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint5/decoder5.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint5/decoder5.0/start:0x0 /sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint8/decoder8.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint8/decoder8.0/start:0x0 /sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint11/decoder11.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint11/decoder11.0/start:0x0 /sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint13/decoder13.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint13/decoder13.0/start:0x0h]hX/sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint5/decoder5.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint5/decoder5.0/start:0x0 /sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint8/decoder8.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint8/decoder8.0/start:0x0 /sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint11/decoder11.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint11/decoder11.0/start:0x0 /sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_granularity:256 /sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_ways:1 /sys/bus/cxl/devices/endpoint13/decoder13.0/size:0x2000000000 /sys/bus/cxl/devices/endpoint13/decoder13.0/start:0x0}hjsbah}(h]h ]h"]h$]h&]hhƌforcelanguagenonehighlight_args}uh1jhhhKshjmhhubh)}(hNNote that the endpoint interleaving configurations use direct mapping (1-way).h]hNNote that the endpoint interleaving configurations use direct mapping (1-way).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubh)}(h@With PRM calls, the kernel can determine the following mappings:h]h@With PRM calls, the kernel can determine the following mappings:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubj)}(hX-cxl decoder5.0: address mapping found for 0000:e2:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder8.0: address mapping found for 0000:e3:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder11.0: address mapping found for 0000:e4:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder13.0: address mapping found for 0000:e1:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256h]hX-cxl decoder5.0: address mapping found for 0000:e2:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder8.0: address mapping found for 0000:e3:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder11.0: address mapping found for 0000:e4:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256 cxl decoder13.0: address mapping found for 0000:e1:00.0 (hpa -> spa): 0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256}hjsbah}(h]h ]h"]h$]h&]hhjjnonej}uh1jhhhKhjmhhubh)}(hwThe corresponding CXL host bridge (HDM) decoders and root decoder (CFMWS) match the calculated endpoint mappings shown:h]hwThe corresponding CXL host bridge (HDM) decoders and root decoder (CFMWS) match the calculated endpoint mappings shown:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubj)}(hXz/sys/bus/cxl/devices/port1/decoder1.0/interleave_granularity:256 /sys/bus/cxl/devices/port1/decoder1.0/interleave_ways:4 /sys/bus/cxl/devices/port1/decoder1.0/size:0x8000000000 /sys/bus/cxl/devices/port1/decoder1.0/start:0x850000000 /sys/bus/cxl/devices/port1/decoder1.0/target_list:0,1,2,3 /sys/bus/cxl/devices/port1/decoder1.0/target_type:expander /sys/bus/cxl/devices/root0/decoder0.0/interleave_granularity:256 /sys/bus/cxl/devices/root0/decoder0.0/interleave_ways:1 /sys/bus/cxl/devices/root0/decoder0.0/size:0x8000000000 /sys/bus/cxl/devices/root0/decoder0.0/start:0x850000000 /sys/bus/cxl/devices/root0/decoder0.0/target_list:7h]hXz/sys/bus/cxl/devices/port1/decoder1.0/interleave_granularity:256 /sys/bus/cxl/devices/port1/decoder1.0/interleave_ways:4 /sys/bus/cxl/devices/port1/decoder1.0/size:0x8000000000 /sys/bus/cxl/devices/port1/decoder1.0/start:0x850000000 /sys/bus/cxl/devices/port1/decoder1.0/target_list:0,1,2,3 /sys/bus/cxl/devices/port1/decoder1.0/target_type:expander /sys/bus/cxl/devices/root0/decoder0.0/interleave_granularity:256 /sys/bus/cxl/devices/root0/decoder0.0/interleave_ways:1 /sys/bus/cxl/devices/root0/decoder0.0/size:0x8000000000 /sys/bus/cxl/devices/root0/decoder0.0/start:0x850000000 /sys/bus/cxl/devices/root0/decoder0.0/target_list:7}hjsbah}(h]h ]h"]h$]h&]hhjjnonej}uh1jhhhKhjmhhubh)}(h6The following changes to the specification are needed:h]h6The following changes to the specification are needed:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmhhubj?)}(hhh](jD)}(hNAllow a CXL device to be in an HPA space other than the host's address space. h]h)}(hMAllow a CXL device to be in an HPA space other than the host's address space.h]hOAllow a CXL device to be in an HPA space other than the host’s address space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jChjhhhhhNubjD)}(hAllow the platform to use implementation-specific address translation when crossing memory domains on the CXL.mem path between the host and the device. h]h)}(hAllow the platform to use implementation-specific address translation when crossing memory domains on the CXL.mem path between the host and the device.h]hAllow the platform to use implementation-specific address translation when crossing memory domains on the CXL.mem path between the host and the device.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)ubah}(h]h ]h"]h$]h&]uh1jChjhhhhhNubjD)}(hEDefine a PRM handler method for converting device addresses to SPAs. h]h)}(hDDefine a PRM handler method for converting device addresses to SPAs.h]hDDefine a PRM handler method for converting device addresses to SPAs.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjAubah}(h]h ]h"]h$]h&]uh1jChjhhhhhNubjD)}(hSpecify that the platform shall provide the PRM handler method to the Operating System to detect Normalized addressing and for determining Endpoint SPA ranges and interleaving configurations. h]h)}(hSpecify that the platform shall provide the PRM handler method to the Operating System to detect Normalized addressing and for determining Endpoint SPA ranges and interleaving configurations.h]hSpecify that the platform shall provide the PRM handler method to the Operating System to detect Normalized addressing and for determining Endpoint SPA ranges and interleaving configurations.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubah}(h]h ]h"]h$]h&]uh1jChjhhhhhNubjD)}(hAdd reference to: | Platform Runtime Mechanism Specification, Version 1.1 – November 2020 | https://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf h](h)}(hAdd reference to:h]hAdd reference to:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubh line_block)}(hhh](hh)}(hGPlatform Runtime Mechanism Specification, Version 1.1 – November 2020h]hGPlatform Runtime Mechanism Specification, Version 1.1 – November 2020}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hindentKhjhhhKubj)}(hghttps://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdfh]h reference)}(hjh]hghttps://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubah}(h]h ]h"]h$]h&]uh1hjKhjhhhKubeh}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jChjhhhhhNubeh}(h]h ]h"]h$]h&]jc*uh1j>hhhKhjmhhubeh}(h]summary-of-the-changeah ]h"]summary of the changeah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hBenefits of the Changeh]hBenefits of the Change}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX Without the change, the Operating System may be unable to determine the memory region and Root Decoder for an Endpoint and its corresponding HDM decoder. Region creation would fail. Platforms with a different interconnect architecture would fail to set up and use CXL.h]hX Without the change, the Operating System may be unable to determine the memory region and Root Decoder for an Endpoint and its corresponding HDM decoder. Region creation would fail. Platforms with a different interconnect architecture would fail to set up and use CXL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]benefits-of-the-changeah ]h"]benefits of the changeah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Referencesh]h References}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubhfootnote)}(hcCompute Express Link Specification, Revision 3.2, Version 1.0, https://www.computeexpresslink.org/ h](hlabel)}(hhh]h1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(hbCompute Express Link Specification, Revision 3.2, Version 1.0, https://www.computeexpresslink.org/h](h?Compute Express Link Specification, Revision 3.2, Version 1.0, }(hjhhhNhNubj)}(h#https://www.computeexpresslink.org/h]h#https://www.computeexpresslink.org/}(hj"hhhNhNubah}(h]h ]h"]h$]h&]refurij$uh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]jah ]h"] cxl-spec-3.2ah$]h&](jid4ejKjjuh1jhhhKhjhhubj)}(hAMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh, ACPI v6.5 Porting Guide, Publication # 58088, https://www.amd.com/en/search/documentation/hub.html h](j )}(hhh]h2}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j hj?hhhNhNubh)}(hAMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh, ACPI v6.5 Porting Guide, Publication # 58088, https://www.amd.com/en/search/documentation/hub.htmlh](hdAMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh, ACPI v6.5 Porting Guide, Publication # 58088, }(hjPhhhNhNubj)}(h4https://www.amd.com/en/search/documentation/hub.htmlh]h4https://www.amd.com/en/search/documentation/hub.html}(hjXhhhNhNubah}(h]h ]h"]h$]h&]refurijZuh1jhjPubeh}(h]h ]h"]h$]h&]uh1hhhhKhj?ubeh}(h]jbah ]h"] amd-ppr-58088ah$]h&]j]ajKjjuh1jhhhKhjhhubj)}(hPlatform Runtime Mechanism, Version: 1.1, https://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf h](j )}(hhh]h3}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j hjthhhNhNubh)}(hPlatform Runtime Mechanism, Version: 1.1, https://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdfh](h*Platform Runtime Mechanism, Version: 1.1, }(hjhhhNhNubj)}(hghttps://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdfh]hghttps://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjtubeh}(h]j<ah ]h"]prm-specah$]h&]j7ajKjjuh1jhhhKhjhhubeh}(h] referencesah ]h"] referencesah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h"Detailed Description of the Changeh]h"Detailed Description of the Change}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h^The following describes the necessary changes to the *CXL 3.2 specification* [#cxl-spec-3.2]_:h](h5The following describes the necessary changes to the }(hjhhhNhNubj)}(h*CXL 3.2 specification*h]hCXL 3.2 specification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh }(hjhhhNhNubj)}(h[#cxl-spec-3.2]_h]h1}(hjhhhNhNubah}(h]j>ah ]h"]h$]h&]jKjjjjuh1jhjjKubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h)Add the following reference to the table:h]h)Add the following reference to the table:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTable 1-2. Reference Documentsh]hTable 1-2. Reference Documents}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hDocumenth]hDocument}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjFubah}(h]h ]h"]h$]h&]uh1jDhjAubjE)}(hhh]h)}(hChapter Referenceh]hChapter Reference}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj]ubah}(h]h ]h"]h$]h&]uh1jDhjAubjE)}(hhh]h)}(hDocument No./Locationh]hDocument No./Location}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjtubah}(h]h ]h"]h$]h&]uh1jDhjAubeh}(h]h ]h"]h$]h&]uh1j?hj<ubah}(h]h ]h"]h$]h&]uh1j:hjubhtbody)}(hhh]j@)}(hhh](jE)}(hhh]h)}(h'Platform Runtime Mechanism Version: 1.1h]h'Platform Runtime Mechanism Version: 1.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh]h)}(h Chapter 8, 9h]h Chapter 8, 9}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh]h)}(hhttps://www.uefi.org/acpih]j)}(hjh]hhttps://www.uefi.org/acpi}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]uh1j?hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(h7Add the following paragraphs to the end of the section:h]h7Add the following paragraphs to the end of the section:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h1**8.2.4.20 CXL HDM Decoder Capability Structure**h]hstrong)}(hjh]h-8.2.4.20 CXL HDM Decoder Capability Structure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX"A device may use an HPA space that is not common to other components of the host domain. The platform is responsible for address translation when crossing HPA spaces. The Operating System must determine the interleaving configuration and perform address translation to the HPA ranges of the HDM decoders as needed. The translation mechanism is host-specific and implementation dependent.h]hX“A device may use an HPA space that is not common to other components of the host domain. The platform is responsible for address translation when crossing HPA spaces. The Operating System must determine the interleaving configuration and perform address translation to the HPA ranges of the HDM decoders as needed. The translation mechanism is host-specific and implementation dependent.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXkThe platform indicates support of independent HPA spaces and the need for address translation by providing a Platform Runtime Mechanism (PRM) handler. The OS shall use that handler to perform the necessary translations from the DPA space to the HPA space. The handler is defined in Section 9.18.4 *PRM Handler for CXL DPA to System Physical Address Translation*."h](hX)The platform indicates support of independent HPA spaces and the need for address translation by providing a Platform Runtime Mechanism (PRM) handler. The OS shall use that handler to perform the necessary translations from the DPA space to the HPA space. The handler is defined in Section 9.18.4 }(hj<hhhNhNubj)}(h@*PRM Handler for CXL DPA to System Physical Address Translation*h]h>PRM Handler for CXL DPA to System Physical Address Translation}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh.”}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h;Add the following section and sub-section including tables:h]h;Add the following section and sub-section including tables:}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hI**9.18.4 PRM Handler for CXL DPA to System Physical Address Translation**h]j)}(hjlh]hE9.18.4 PRM Handler for CXL DPA to System Physical Address Translation}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX"A platform may be configured to use 'Normalized addresses'. Host physical address (HPA) spaces are component-specific and differ from system physical addresses (SPAs). The endpoint has its own physical address space. All requests presented to the device already use Device Physical Addresses (DPAs). The CXL endpoint decoders have interleaving disabled (1-way interleaving) and the device does not perform HPA decoding to determine a DPA.h]hX“A platform may be configured to use ‘Normalized addresses’. Host physical address (HPA) spaces are component-specific and differ from system physical addresses (SPAs). The endpoint has its own physical address space. All requests presented to the device already use Device Physical Addresses (DPAs). The CXL endpoint decoders have interleaving disabled (1-way interleaving) and the device does not perform HPA decoding to determine a DPA.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe platform provides a PRM handler for CXL DPA to System Physical Address Translation. The PRM handler translates a Device Physical Address (DPA) to a System Physical Address (SPA) for a specified CXL endpoint. In the address space of the host, SPA and HPA are equivalent, and the OS shall use this handler to determine the HPA that corresponds to a device address, for example when configuring HDM decoders on platforms with Normalized addressing. The GUID and the parameter buffer format of the handler are specified in section 9.18.4.1. If the OS identifies the PRM handler, the platform supports Normalized addressing and the OS must perform DPA address translation as needed."h]hXThe platform provides a PRM handler for CXL DPA to System Physical Address Translation. The PRM handler translates a Device Physical Address (DPA) to a System Physical Address (SPA) for a specified CXL endpoint. In the address space of the host, SPA and HPA are equivalent, and the OS shall use this handler to determine the HPA that corresponds to a device address, for example when configuring HDM decoders on platforms with Normalized addressing. The GUID and the parameter buffer format of the handler are specified in section 9.18.4.1. If the OS identifies the PRM handler, the platform supports Normalized addressing and the OS must perform DPA address translation as needed.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(h#**9.18.4.1 PRM Handler Invocation**h]j)}(hjh]h9.18.4.1 PRM Handler Invocation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h"The OS calls the PRM handler for CXL DPA to System Physical Address Translation using the direct invocation mechanism. Details of calling a PRM handler are described in the Platform Runtime Mechanism (PRM) specification.h]h“The OS calls the PRM handler for CXL DPA to System Physical Address Translation using the direct invocation mechanism. Details of calling a PRM handler are described in the Platform Runtime Mechanism (PRM) specification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h4The PRM handler is identified by the following GUID:h]h4The PRM handler is identified by the following GUID:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh block_quote)}(h%EE41B397-25D4-452C-AD54-48C6E3480B94 h]h)}(h$EE41B397-25D4-452C-AD54-48C6E3480B94h]h$EE41B397-25D4-452C-AD54-48C6E3480B94}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhhhM hjhhubh)}(hThe caller allocates and prepares a Parameter Buffer, then passes the PRM handler GUID and a pointer to the Parameter Buffer to invoke the handler. The Parameter Buffer is described in Table 9-32."h]hThe caller allocates and prepares a Parameter Buffer, then passes the PRM handler GUID and a pointer to the Parameter Buffer to invoke the handler. The Parameter Buffer is described in Table 9-32.”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h\**Table 9-32. PRM Parameter Buffer used for CXL DPA to System Physical Address Translation**h]j)}(hjh]hXTable 9-32. PRM Parameter Buffer used for CXL DPA to System Physical Address Translation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKHuh1jhjubj;)}(hhh]j@)}(hhh](jE)}(hhh]h)}(h Byte Offseth]h Byte Offset}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jDhj6ubjE)}(hhh]hdefinition_list)}(hhh]hdefinition_list_item)}(hLength in Bytesh](hterm)}(h Length inh]h Length in}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1j^hhhMhjZubh definition)}(hhh]h)}(hBytesh]hBytes}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1jnhjZubeh}(h]h ]h"]h$]h&]uh1jXhhhMhjUubah}(h]h ]h"]h$]h&]uh1jShjPubah}(h]h ]h"]h$]h&]uh1jDhj6ubjE)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jDhj6ubeh}(h]h ]h"]h$]h&]uh1j?hj3ubah}(h]h ]h"]h$]h&]uh1j:hjubj)}(hhh](j@)}(hhh](jE)}(hhh]h)}(h00hh]h00h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh]h)}(h8h]h8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh]h)}(hS**CXL Device Physical Address (DPA)**: CXL DPA (e.g., from CXL Component Event Log)h](j)}(h%**CXL Device Physical Address (DPA)**h]h!CXL Device Physical Address (DPA)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh.: CXL DPA (e.g., from CXL Component Event Log)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]uh1j?hjubj@)}(hhh](jE)}(hhh]h)}(h08hh]h08h}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh]h)}(h4h]h4}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jDhjubjE)}(hhh](h)}(h**CXL Endpoint SBDF**:h](j)}(h**CXL Endpoint SBDF**h]hCXL Endpoint SBDF}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubh:}(hjOhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjLubj?)}(hhh](jD)}(hByte 3 - PCIe Segmenth]h)}(hjph]hByte 3 - PCIe Segment}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1jChjkubjD)}(hByte 2 - Bus Numberh]h)}(hjh]hByte 2 - Bus Number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jChjkubjD)}(hKByte 1: - Device Number Bits[7:3] - Function Number Bits[2:0]h]jT)}(hhh]jY)}(h=Byte 1: - Device Number Bits[7:3] - Function Number Bits[2:0]h](j_)}(hByte 1:h]hByte 1:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j^hhhMhjubjo)}(hhh]j?)}(hhh](jD)}(hDevice Number Bits[7:3]h]h)}(hjh]hDevice Number Bits[7:3]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jChjubjD)}(hFunction Number Bits[2:0]h]h)}(hjh]hFunction Number Bits[2:0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jChjubeh}(h]h ]h"]h$]h&]jcjduh1j>hhhMhjubah}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ]h"]h$]h&]uh1jXhhhMhjubah}(h]h ]h"]h$]h&]uh1jShjubah}(h]h ]h"]h$]h&]uh1jChjkubjD)}(hByte 0 - RESERVED (MBZ) h]h)}(hByte 0 - RESERVED (MBZ)h]hByte 0 - RESERVED (MBZ)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj ubah}(h]h ]h"]h$]h&]uh1jChjkubeh}(h]h ]h"]h$]h&]jcjduh1j>hhhMhjLubeh}(h]h ]h"]h$]h&]uh1jDhjubeh}(h]h ]h"]h$]h&]uh1j?hjubj@)}(hhh](jE)}(hhh]h)}(h0Chh]h0Ch}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj4 ubah}(h]h ]h"]h$]h&]uh1jDhj1 ubjE)}(hhh]h)}(hjh]h8}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjK ubah}(h]h ]h"]h$]h&]uh1jDhj1 ubjE)}(hhh]h)}(hS**Output Buffer**: Virtual Address Pointer to the buffer, as defined in Table 9-33.h](j)}(h**Output Buffer**h]h Output Buffer}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd ubhB: Virtual Address Pointer to the buffer, as defined in Table 9-33.}(hjd hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM$hja ubah}(h]h ]h"]h$]h&]uh1jDhj1 ubeh}(h]h ]h"]h$]h&]uh1j?hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(hY**Table 9-33. PRM Output Buffer used for CXL DPA to System Physical Address Translation**h]j)}(hj h]hUTable 9-33. PRM Output Buffer used for CXL DPA to System Physical Address Translation}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhM(hjhhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKHuh1jhj ubj;)}(hhh]j@)}(hhh](jE)}(hhh]h)}(h Byte Offseth]h Byte Offset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj ubah}(h]h ]h"]h$]h&]uh1jDhj ubjE)}(hhh]jT)}(hhh]jY)}(hLength in Bytesh](j_)}(h Length inh]h Length in}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j^hhhM+hj ubjo)}(hhh]h)}(hBytesh]hBytes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj ubah}(h]h ]h"]h$]h&]uh1jnhj ubeh}(h]h ]h"]h$]h&]uh1jXhhhM+hj ubah}(h]h ]h"]h$]h&]uh1jShj ubah}(h]h ]h"]h$]h&]uh1jDhj ubjE)}(hhh]h)}(h Descriptionh]h Description}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj8 ubah}(h]h ]h"]h$]h&]uh1jDhj ubeh}(h]h ]h"]h$]h&]uh1j?hj ubah}(h]h ]h"]h$]h&]uh1j:hj ubj)}(hhh]j@)}(hhh](jE)}(hhh]h)}(h00hh]h00h}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hja ubah}(h]h ]h"]h$]h&]uh1jDhj^ ubjE)}(hhh]h)}(hjh]h8}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjx ubah}(h]h ]h"]h$]h&]uh1jDhj^ ubjE)}(hhh]h)}(hF**System Physical Address (SPA)**: The SPA converted from the CXL DPA.h](j)}(h!**System Physical Address (SPA)**h]hSystem Physical Address (SPA)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh%: The SPA converted from the CXL DPA.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM.hj ubah}(h]h ]h"]h$]h&]uh1jDhj^ ubeh}(h]h ]h"]h$]h&]uh1j?hj[ ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]"detailed-description-of-the-changeah ]h"]"detailed description of the changeah$]h&]uh1hhhhhhhhKubeh}(h] acpi-prm-cxl-address-translationah ]h"] acpi prm cxl address translationah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjDfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}( cxl-spec-3.2](jjeprm-spec]j-a amd-ppr-58088]jSaurefids}(j](jjejb]jSaj<]j-aunameids}(j j jjj*j'jjjgjjjjjjj;jjqjbjj<j j u nametypes}(j jj*jjjjjj;jqjj uh}(j hjhj'jjgj-jjmjjj7j-j]jSjjjjjjjbj?j<jtj jj>ju footnote_refs}(j> ](jjej@ ]j-ajB ]jSau citation_refs} autofootnotes](jj?jteautofootnote_refs](jj-jSjesymbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}j KsRparse_messages]transform_messages] transformerN include_log] decorationNhhub.