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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h"CXL Access Coordinates Computationh]h"CXL Access Coordinates Computation}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubjH)}(hhh](jM)}(h Shared Upstream Link Calculationh]h Shared Upstream Link Calculation}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj\hhhhhK ubh paragraph)}(hXFor certain CXL region construction with endpoints behind CXL switches (SW) or Root Ports (RP), there is the possibility of the total bandwidth for all the endpoints behind a switch being more than the switch upstream link. A similar situation can occur within the host, upstream of the root ports. The CXL driver performs an additional pass after all the targets have arrived for a region in order to recalculate the bandwidths with possible upstream link being a limiting factor in mind.h]hXFor certain CXL region construction with endpoints behind CXL switches (SW) or Root Ports (RP), there is the possibility of the total bandwidth for all the endpoints behind a switch being more than the switch upstream link. A similar situation can occur within the host, upstream of the root ports. The CXL driver performs an additional pass after all the targets have arrived for a region in order to recalculate the bandwidths with possible upstream link being a limiting factor in mind.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK hj\hhubjn)}(hXThe algorithm assumes the configuration is a symmetric topology as that maximizes performance. When asymmetric topology is detected, the calculation is aborted. An asymmetric topology is detected during topology walk where the number of RPs detected as a grandparent is not equal to the number of devices iterated in the same iteration loop. The assumption is made that subtle asymmetry in properties does not happen and all paths to EPs are equal.h]hXThe algorithm assumes the configuration is a symmetric topology as that maximizes performance. When asymmetric topology is detected, the calculation is aborted. An asymmetric topology is detected during topology walk where the number of RPs detected as a grandparent is not equal to the number of devices iterated in the same iteration loop. The assumption is made that subtle asymmetry in properties does not happen and all paths to EPs are equal.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj\hhubjn)}(hThere can be multiple switches under an RP. There can be multiple RPs under a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory Window Structure (CFMWS).h]hThere can be multiple switches under an RP. There can be multiple RPs under a CXL Host Bridge (HB). There can be multiple HBs under a CXL Fixed Memory Window Structure (CFMWS).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj\hhubjn)}(hAn example hierarchy:h]hAn example hierarchy:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj\hhubjn)}(hX> CFMWS 0 > | > _________|_________ > | | > ACPI0017-0 ACPI0017-1 > GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1 > | | | | > RP0 RP1 RP2 RP3 > | | | | > SW 0 SW 1 SW 2 SW 3 > | | | | | | | | > EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7h]hX> CFMWS 0 > | > _________|_________ > | | > ACPI0017-0 ACPI0017-1 > GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1 > | | | | > RP0 RP1 RP2 RP3 > | | | | > SW 0 SW 1 SW 2 SW 3 > | | | | | | | | > EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj\hhubjn)}(h&Computation for the example hierarchy:h]h&Computation for the example hierarchy:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK,hj\hhubhdefinition_list)}(hhh](hdefinition_list_item)}(hXrMin (GP0 to CPU BW, Min(SW 0 Upstream Link to RP0 BW, Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) + Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) + Min(SW 1 Upstream Link to RP1 BW, Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) + Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +h](hterm)}(hMin (GP0 to CPU BW,h]hMin (GP0 to CPU BW,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK3hjubh definition)}(hhh]j)}(hhh](j)}(hMin(SW 0 Upstream Link to RP0 BW, Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) + Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +h](j)}(h!Min(SW 0 Upstream Link to RP0 BW,h]h!Min(SW 0 Upstream Link to RP0 BW,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK0hjubj)}(hhh]jn)}(hMin(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) + Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +h]hMin(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) + Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK0hjubj)}(hMin(SW 1 Upstream Link to RP1 BW, Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) + Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +h](j)}(h!Min(SW 1 Upstream Link to RP1 BW,h]h!Min(SW 1 Upstream Link to RP1 BW,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK3hjubj)}(hhh]jn)}(hMin(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) + Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +h]hMin(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) + Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK3hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK3hjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK3hjubj)}(hXrMin (GP1 to CPU BW, Min(SW 2 Upstream Link to RP2 BW, Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) + Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) + Min(SW 3 Upstream Link to RP3 BW, Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) + Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link)))) h](j)}(hMin (GP1 to CPU BW,h]hMin (GP1 to CPU BW,}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK;hjVubj)}(hhh]j)}(hhh](j)}(hMin(SW 2 Upstream Link to RP2 BW, Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) + Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +h](j)}(h!Min(SW 2 Upstream Link to RP2 BW,h]h!Min(SW 2 Upstream Link to RP2 BW,}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK7hjnubj)}(hhh]jn)}(hMin(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) + Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +h]hMin(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) + Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhhhK7hjkubj)}(hMin(SW 3 Upstream Link to RP3 BW, Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) + Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link)))) h](j)}(h!Min(SW 3 Upstream Link to RP3 BW,h]h!Min(SW 3 Upstream Link to RP3 BW,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK;hjubj)}(hhh]jn)}(hMin(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) + Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))h]hMin(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) + Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhK;hjkubeh}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhhhK;hjhhubeh}(h]h ]h"]h$]h&]uh1jhj\hhhNhNubjn)}(hXThe calculation starts at cxl_region_shared_upstream_perf_update(). A xarray is created to collect all the endpoint bandwidths via the cxl_endpoint_gather_bandwidth() function. The min() of bandwidth from the endpoint CDAT and the upstream link bandwidth is calculated. If the endpoint has a CXL switch as a parent, then min() of calculated bandwidth and the bandwidth from the SSLBIS for the switch downstream port that is associated with the endpoint is calculated. The final bandwidth is stored in a 'struct cxl_perf_ctx' in the xarray indexed by a device pointer. If the endpoint is direct attached to a root port (RP), the device pointer would be an RP device. If the endpoint is behind a switch, the device pointer would be the upstream device of the parent switch.h]hXThe calculation starts at cxl_region_shared_upstream_perf_update(). A xarray is created to collect all the endpoint bandwidths via the cxl_endpoint_gather_bandwidth() function. The min() of bandwidth from the endpoint CDAT and the upstream link bandwidth is calculated. If the endpoint has a CXL switch as a parent, then min() of calculated bandwidth and the bandwidth from the SSLBIS for the switch downstream port that is associated with the endpoint is calculated. The final bandwidth is stored in a ‘struct cxl_perf_ctx’ in the xarray indexed by a device pointer. If the endpoint is direct attached to a root port (RP), the device pointer would be an RP device. If the endpoint is behind a switch, the device pointer would be the upstream device of the parent switch.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK=hj\hhubjn)}(hXbAt the next stage, the code walks through one or more switches if they exist in the topology. For endpoints directly attached to RPs, this step is skipped. If there is another switch upstream, the code takes the min() of the current gathered bandwidth and the upstream link bandwidth. If there's a switch upstream, then the SSLBIS of the upstream switch.h]hXdAt the next stage, the code walks through one or more switches if they exist in the topology. For endpoints directly attached to RPs, this step is skipped. If there is another switch upstream, the code takes the min() of the current gathered bandwidth and the upstream link bandwidth. If there’s a switch upstream, then the SSLBIS of the upstream switch.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKIhj\hhubjn)}(hX Once the topology walk reaches the RP, whether it's direct attached endpoints or walking through the switch(es), cxl_rp_gather_bandwidth() is called. At this point all the bandwidths are aggregated per each host bridge, which is also the index for the resulting xarray.h]hXOnce the topology walk reaches the RP, whether it’s direct attached endpoints or walking through the switch(es), cxl_rp_gather_bandwidth() is called. At this point all the bandwidths are aggregated per each host bridge, which is also the index for the resulting xarray.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKOhj\hhubjn)}(hX The next step is to take the min() of the per host bridge bandwidth and the bandwidth from the Generic Port (GP). The bandwidths for the GP is retrieved via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same ACPI0017 device to form a new xarray.h]hX The next step is to take the min() of the per host bridge bandwidth and the bandwidth from the Generic Port (GP). The bandwidths for the GP is retrieved via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same ACPI0017 device to form a new xarray.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKThj\hhubjn)}(hFinally, the cxl_region_update_bandwidth() is called and the aggregated bandwidth from all the members of the last xarray is updated for the access coordinates residing in the cxl region (cxlr) context.h]hFinally, the cxl_region_update_bandwidth() is called and the aggregated bandwidth from all the members of the last xarray is updated for the access coordinates residing in the cxl region (cxlr) context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKYhj\hhubeh}(h] shared-upstream-link-calculationah ]h"] shared upstream link calculationah$]h&]uh1jGhjIhhhhhK ubeh}(h]"cxl-access-coordinates-computationah ]h"]"cxl access coordinates computationah$]h&]uh1jGhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jLN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj]error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}(hhhhhhj jjjj*jj9j-jHj<jWjKjfjZjujijjxjjjjjjjjjjjjjjjjj jjjj)jj8j,jGj;jVjJjejYjtjhjjwjjjjjjjjjjjjjjjjj jjj j(jj7j+jFj:jUjIjdjXjsjgjjvjjjjjjjjjjjjjjjjj jjj j'jj6j*jEj9jTjHjcjWjrjfjjujjjjjjjjjjjjjjjjjjjj j&jj5j)jDj8usubstitution_names}(amphߌaposhasthbrvbarj bsoljcentj*colonj9commajHcommatjWcopyjfcurrenjudarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34j frac38jfrac58j)frac78j8gtjGhalfjVhorbarjehyphenjtiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquoj ltjmicroj(middotj7nbspjFnotjUnumjdohmjsordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotj raquojrarrj'rcubj6rdquojEregjTrparjcrsqbjrrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesjtradejuarrj&verbarj5yenjDurefnames}refids}nameids}(j7j4j/j,u nametypes}(j7j/uh}(j4jIj,j\u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log]3Documentation/driver-api/cxl/access-coordinates.rst(NNNNta decorationNhhub.