Lsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}(hhparenthuba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget"/translations/zh_CN/driver-api/clkmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}(hhhh2ubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/zh_TW/driver-api/clkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}(hhhhFubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/it_IT/driver-api/clkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}(hhhhZubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ja_JP/driver-api/clkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}(hhhhnubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/ko_KR/driver-api/clkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}(hhhhubah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget"/translations/sp_SP/driver-api/clkmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hThe Common Clk Frameworkh]hThe Common Clk Framework}(hhhhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh h]h paragraph)}(h"Mike Turquette h](hMike Turquette <}(hMike Turquette }(h>hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hThis document endeavours to explain the common clk framework details, and how to port a platform over to this framework. It is not yet a detailed explanation of the clock api in include/linux/clk.h, but perhaps someday it will include that information.h]hThis document endeavours to explain the common clk framework details, and how to port a platform over to this framework. It is not yet a detailed explanation of the clock api in include/linux/clk.h, but perhaps someday it will include that information.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h Introduction and interface splith]h Introduction and interface split}(hj$hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(hThe common clk framework is an interface to control the clock nodes available on various devices today. This may come in the form of clock gating, rate adjustment, muxing or other operations. This framework is enabled with the CONFIG_COMMON_CLK option.h]hThe common clk framework is an interface to control the clock nodes available on various devices today. This may come in the form of clock gating, rate adjustment, muxing or other operations. This framework is enabled with the CONFIG_COMMON_CLK option.}(hj2hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe interface itself is divided into two halves, each shielded from the details of its counterpart. First is the common definition of struct clk which unifies the framework-level accounting and infrastructure that has traditionally been duplicated across a variety of platforms. Second is a common implementation of the clk.h api, defined in drivers/clk/clk.c. Finally there is struct clk_ops, whose operations are invoked by the clk api implementation.h]hXThe interface itself is divided into two halves, each shielded from the details of its counterpart. First is the common definition of struct clk which unifies the framework-level accounting and infrastructure that has traditionally been duplicated across a variety of platforms. Second is a common implementation of the clk.h api, defined in drivers/clk/clk.c. Finally there is struct clk_ops, whose operations are invoked by the clk api implementation.}(hj@hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe second half of the interface is comprised of the hardware-specific callbacks registered with struct clk_ops and the corresponding hardware-specific structures needed to model a particular clock. For the remainder of this document any reference to a callback in struct clk_ops, such as .enable or .set_rate, implies the hardware-specific implementation of that code. Likewise, references to struct clk_foo serve as a convenient shorthand for the implementation of the hardware-specific bits for the hypothetical "foo" hardware.h]hXThe second half of the interface is comprised of the hardware-specific callbacks registered with struct clk_ops and the corresponding hardware-specific structures needed to model a particular clock. For the remainder of this document any reference to a callback in struct clk_ops, such as .enable or .set_rate, implies the hardware-specific implementation of that code. Likewise, references to struct clk_foo serve as a convenient shorthand for the implementation of the hardware-specific bits for the hypothetical “foo” hardware.}(hjNhjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTying the two halves of this interface together is struct clk_hw, which is defined in struct clk_foo and pointed to within struct clk_core. This allows for easy navigation between the two discrete halves of the common clock interface.h]hTying the two halves of this interface together is struct clk_hw, which is defined in struct clk_foo and pointed to within struct clk_core. This allows for easy navigation between the two discrete halves of the common clock interface.}(hj\hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjhhubeh}(h] introduction-and-interface-splitah ]h"] introduction and interface splitah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hCommon data structures and apih]hCommon data structures and api}(hjuhjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhK+ubh)}(h]Below is the common struct clk_core definition from drivers/clk/clk.c, modified for brevity::h]h\Below is the common struct clk_core definition from drivers/clk/clk.c, modified for brevity:}(h\Below is the common struct clk_core definition from drivers/clk/clk.c, modified for brevity:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjphhubh literal_block)}(hXstruct clk_core { const char *name; const struct clk_ops *ops; struct clk_hw *hw; struct module *owner; struct clk_core *parent; const char **parent_names; struct clk_core **parents; u8 num_parents; u8 new_parent_index; ... };h]hXstruct clk_core { const char *name; const struct clk_ops *ops; struct clk_hw *hw; struct module *owner; struct clk_core *parent; const char **parent_names; struct clk_core **parents; u8 num_parents; u8 new_parent_index; ... };}(hhhjubah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhK0hjphhubh)}(hThe members above make up the core of the clk tree topology. The clk api itself defines several driver-facing functions which operate on struct clk. That api is documented in include/linux/clk.h.h]hThe members above make up the core of the clk tree topology. The clk api itself defines several driver-facing functions which operate on struct clk. That api is documented in include/linux/clk.h.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjphhubh)}(hPlatforms and devices utilizing the common struct clk_core use the struct clk_ops pointer in struct clk_core to perform the hardware-specific parts of the operations defined in clk-provider.h::h]hPlatforms and devices utilizing the common struct clk_core use the struct clk_ops pointer in struct clk_core to perform the hardware-specific parts of the operations defined in clk-provider.h:}(hPlatforms and devices utilizing the common struct clk_core use the struct clk_ops pointer in struct clk_core to perform the hardware-specific parts of the operations defined in clk-provider.h:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjphhubj)}(hXfstruct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); int (*is_prepared)(struct clk_hw *hw); void (*unprepare_unused)(struct clk_hw *hw); int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); int (*get_phase)(struct clk_hw *hw); int (*set_phase)(struct clk_hw *hw, int degrees); void (*init)(struct clk_hw *hw); void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); };h]hXfstruct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); int (*is_prepared)(struct clk_hw *hw); void (*unprepare_unused)(struct clk_hw *hw); int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); int (*get_phase)(struct clk_hw *hw); int (*set_phase)(struct clk_hw *hw, int degrees); void (*init)(struct clk_hw *hw); void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); };}(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKEhjphhubeh}(h]common-data-structures-and-apiah ]h"]common data structures and apiah$]h&]uh1hhhhhhhhK+ubh)}(hhh](h)}(hHardware clk implementationsh]hHardware clk implementations}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKhubh)}(hXThe strength of the common struct clk_core comes from its .ops and .hw pointers which abstract the details of struct clk from the hardware-specific bits, and vice versa. To illustrate consider the simple gateable clk implementation in drivers/clk/clk-gate.c::h]hXThe strength of the common struct clk_core comes from its .ops and .hw pointers which abstract the details of struct clk from the hardware-specific bits, and vice versa. To illustrate consider the simple gateable clk implementation in drivers/clk/clk-gate.c:}(hXThe strength of the common struct clk_core comes from its .ops and .hw pointers which abstract the details of struct clk from the hardware-specific bits, and vice versa. To illustrate consider the simple gateable clk implementation in drivers/clk/clk-gate.c:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjhhubj)}(h{struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; ... };h]h{struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; ... };}(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKohjhhubh)}(hX4struct clk_gate contains struct clk_hw hw as well as hardware-specific knowledge about which register and bit controls this clk's gating. Nothing about clock topology or accounting, such as enable_count or notifier_count, is needed here. That is all handled by the common framework code and struct clk_core.h]hX6struct clk_gate contains struct clk_hw hw as well as hardware-specific knowledge about which register and bit controls this clk’s gating. Nothing about clock topology or accounting, such as enable_count or notifier_count, is needed here. That is all handled by the common framework code and struct clk_core.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjhhubh)}(h7Let's walk through enabling this clk from driver code::h]h8Let’s walk through enabling this clk from driver code:}(h6Let's walk through enabling this clk from driver code:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjhhubj)}(h\struct clk *clk; clk = clk_get(NULL, "my_gateable_clk"); clk_prepare(clk); clk_enable(clk);h]h\struct clk *clk; clk = clk_get(NULL, "my_gateable_clk"); clk_prepare(clk); clk_enable(clk);}(hhhj ubah}(h]h ]h"]h$]h&]jjuh1jhhhK~hjhhubh)}(h.The call graph for clk_enable is very simple::h]h-The call graph for clk_enable is very simple:}(h-The call graph for clk_enable is very simple:hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hclk_enable(clk); clk->ops->enable(clk->hw); [resolves to...] clk_gate_enable(hw); [resolves struct clk gate with to_clk_gate(hw)] clk_gate_set_bit(gate);h]hclk_enable(clk); clk->ops->enable(clk->hw); [resolves to...] clk_gate_enable(hw); [resolves struct clk gate with to_clk_gate(hw)] clk_gate_set_bit(gate);}(hhhj=ubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h(And the definition of clk_gate_set_bit::h]h'And the definition of clk_gate_set_bit:}(h'And the definition of clk_gate_set_bit:hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hstatic void clk_gate_set_bit(struct clk_gate *gate) { u32 reg; reg = __raw_readl(gate->reg); reg |= BIT(gate->bit_idx); writel(reg, gate->reg); }h]hstatic void clk_gate_set_bit(struct clk_gate *gate) { u32 reg; reg = __raw_readl(gate->reg); reg |= BIT(gate->bit_idx); writel(reg, gate->reg); }}(hhhjZubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h%Note that to_clk_gate is defined as::h]h$Note that to_clk_gate is defined as:}(h$Note that to_clk_gate is defined as:hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h?#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)h]h?#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)}(hhhjwubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hLThis pattern of abstraction is used for every clock hardware representation.h]hLThis pattern of abstraction is used for every clock hardware representation.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]hardware-clk-implementationsah ]h"]hardware clk implementationsah$]h&]uh1hhhhhhhhKhubh)}(hhh](h)}(h Supporting your own clk hardwareh]h Supporting your own clk hardware}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hhWhen implementing support for a new type of clock it is only necessary to include the following header::h]hgWhen implementing support for a new type of clock it is only necessary to include the following header:}(hgWhen implementing support for a new type of clock it is only necessary to include the following header:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h#include h]h#include }(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hWTo construct a clk hardware structure for your platform you must define the following::h]hVTo construct a clk hardware structure for your platform you must define the following:}(hVTo construct a clk hardware structure for your platform you must define the following:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h^struct clk_foo { struct clk_hw hw; ... hardware specific data goes here ... };h]h^struct clk_foo { struct clk_hw hw; ... hardware specific data goes here ... };}(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hUTo take advantage of your data you'll need to support valid operations for your clk::h]hVTo take advantage of your data you’ll need to support valid operations for your clk:}(hTTo take advantage of your data you'll need to support valid operations for your clk:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hxstruct clk_ops clk_foo_ops = { .enable = &clk_foo_enable, .disable = &clk_foo_disable, };h]hxstruct clk_ops clk_foo_ops = { .enable = &clk_foo_enable, .disable = &clk_foo_disable, };}(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h2Implement the above functions using container_of::h]h1Implement the above functions using container_of:}(h1Implement the above functions using container_of:hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw) int clk_foo_enable(struct clk_hw *hw) { struct clk_foo *foo; foo = to_clk_foo(hw); ... perform magic on foo ... return 0; };h]h#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw) int clk_foo_enable(struct clk_hw *hw) { struct clk_foo *foo; foo = to_clk_foo(hw); ... perform magic on foo ... return 0; };}(hhhjubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hXGBelow is a matrix detailing which clk_ops are mandatory based upon the hardware capabilities of that clock. A cell marked as "y" means mandatory, a cell marked as "n" implies that either including that callback is invalid or otherwise unnecessary. Empty cells are either optional or must be evaluated on a case-by-case basis.h]hXOBelow is a matrix detailing which clk_ops are mandatory based upon the hardware capabilities of that clock. A cell marked as “y” means mandatory, a cell marked as “n” implies that either including that callback is invalid or otherwise unnecessary. Empty cells are either optional or must be evaluated on a case-by-case basis.}(hj"hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhtable)}(hhh](h)}(hclock hardware characteristicsh]hclock hardware characteristics}(hj5hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj0ubhtgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jFhjCubjG)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jFhjCubjG)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jFhjCubjG)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jFhjCubjG)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jFhjCubjG)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jFhjCubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hgateh]hgate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h change rateh]h change rate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h single parenth]h single parent}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h multiplexerh]h multiplexer}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hrooth]hroot}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjCubhtbody)}(hhh](j)}(hhh](j)}(hhh]h)}(h.prepareh]h.prepare}(hj%hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h .unprepareh]h .unprepare}(hjrhjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmubah}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h.enableh]h.enable}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hyh]hy}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h.disableh]h.disable}(hjYhjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hjh]hy}(hjhjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h .is_enabledh]h .is_enabled}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hy}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h 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hjhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hhhjhhhNhNubah}(h]id1ah ]h"]h$]h&]refidid3docnamedriver-api/clkuh1jhjresolvedKubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h.determine_rateh]h.determine_rate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hy [1]_h](hy }(hy hj6hhhNhNubj)}(h[1]_h]h1}(hhhj?hhhNhNubah}(h]id2ah ]h"]h$]h&]jjjjuh1jhj6jKubeh}(h]h ]h"]h$]h&]uh1hhhhKhj3ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h .set_rateh]h .set_rate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj~ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(hjh]hy}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h 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]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjEh]hn}(hjEhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjh]hy}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hjEh]hn}(hjEhjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h.recalc_accuracyh]h.recalc_accuracy}(hjD hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj? ubah}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj< ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h.inith]h.init}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]colsKuh1jAhj0ubeh}(h]id4ah ]h"]h$]h&]uh1j.hjhhhhhNubhfootnote)}(h8either one of round_rate or determine_rate is required. h](hlabel)}(h1h]h1}(hhhj1 hhhNhNubah}(h]h ]h"]h$]h&]uh1j/ hj+ ubh)}(h7either one of round_rate or determine_rate is required.h]h7either one of round_rate or determine_rate is required.}(hjA hj? hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ ubeh}(h]jah ]h"]1ah$]h&](jjIejjuh1j) hhhKhjhhjKubh)}(hFinally, register your clock at run-time with a hardware-specific registration function. This function simply populates struct clk_foo's data and then passes the common struct clk parameters to the framework with a call to::h]hFinally, register your clock at run-time with a hardware-specific registration function. This function simply populates struct clk_foo’s data and then passes the common struct clk parameters to the framework with a call to:}(hFinally, register your clock at run-time with a hardware-specific registration function. This function simply populates struct clk_foo's data and then passes the common struct clk parameters to the framework with a call to:hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hclk_register(...)h]hclk_register(...)}(hhhjc ubah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hBSee the basic clock types in ``drivers/clk/clk-*.c`` for examples.h](hSee the basic clock types in }(hSee the basic clock types in hjq hhhNhNubhliteral)}(h``drivers/clk/clk-*.c``h]hdrivers/clk/clk-*.c}(hhhj| hhhNhNubah}(h]h ]h"]h$]h&]uh1jz hjq ubh for examples.}(h for examples.hjq hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] supporting-your-own-clk-hardwareah ]h"] supporting your own clk hardwareah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h'Disabling clock gating of unused clocksh]h'Disabling clock gating of unused clocks}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hX7Sometimes during development it can be useful to be able to bypass the default disabling of unused clocks. For example, if drivers aren't enabling clocks properly but rely on them being on from the bootloader, bypassing the disabling means that the driver will remain functional while the issues are sorted out.h]hX9Sometimes during development it can be useful to be able to bypass the default disabling of unused clocks. For example, if drivers aren’t enabling clocks properly but rely on them being on from the bootloader, bypassing the disabling means that the driver will remain functional while the issues are sorted out.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hZYou can see which clocks have been disabled by booting your kernel with these parameters::h]hYYou can see which clocks have been disabled by booting your kernel with these parameters:}(hYYou can see which clocks have been disabled by booting your kernel with these parameters:hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(h%tp_printk trace_event=clk:clk_disableh]h%tp_printk trace_event=clk:clk_disable}(hhhj ubah}(h]h ]h"]h$]h&]jjuh1jhhhMhj hhubh)}(hTTo bypass this disabling, include "clk_ignore_unused" in the bootargs to the kernel.h]hXTo bypass this disabling, include “clk_ignore_unused” in the bootargs to the kernel.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubeh}(h]'disabling-clock-gating-of-unused-clocksah ]h"]'disabling clock gating of unused clocksah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hLockingh]hLocking}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hWThe common clock framework uses two global locks, the prepare lock and the enable lock.h]hWThe common clock framework uses two global locks, the prepare lock and the enable lock.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hThe enable lock is a spinlock and is held across calls to the .enable, .disable operations. Those operations are thus not allowed to sleep, and calls to the clk_enable(), clk_disable() API functions are allowed in atomic context.h]hThe enable lock is a spinlock and is held across calls to the .enable, .disable operations. Those operations are thus not allowed to sleep, and calls to the clk_enable(), clk_disable() API functions are allowed in atomic context.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hXfFor clk_is_enabled() API, it is also designed to be allowed to be used in atomic context. However, it doesn't really make any sense to hold the enable lock in core, unless you want to do something else with the information of the enable state with that lock held. Otherwise, seeing if a clk is enabled is a one-shot read of the enabled state, which could just as easily change after the function returns because the lock is released. Thus the user of this API needs to handle synchronizing the read of the state with whatever they're using it for to make sure that the enable state doesn't change during that time.h]hXlFor clk_is_enabled() API, it is also designed to be allowed to be used in atomic context. However, it doesn’t really make any sense to hold the enable lock in core, unless you want to do something else with the information of the enable state with that lock held. Otherwise, seeing if a clk is enabled is a one-shot read of the enabled state, which could just as easily change after the function returns because the lock is released. Thus the user of this API needs to handle synchronizing the read of the state with whatever they’re using it for to make sure that the enable state doesn’t change during that time.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hThe prepare lock is a mutex and is held across calls to all other operations. All those operations are allowed to sleep, and calls to the corresponding API functions are not allowed in atomic context.h]hThe prepare lock is a mutex and is held across calls to all other operations. All those operations are allowed to sleep, and calls to the corresponding API functions are not allowed in atomic context.}(hj, hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(hMThis effectively divides operations in two groups from a locking perspective.h]hMThis effectively divides operations in two groups from a locking perspective.}(hj: hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hj hhubh)}(hXDrivers don't need to manually protect resources shared between the operations of one group, regardless of whether those resources are shared by multiple clocks or not. However, access to resources that are shared between operations of the two groups needs to be protected by the drivers. An example of such a resource would be a register that controls both the clock rate and the clock enable/disable state.h]hXDrivers don’t need to manually protect resources shared between the operations of one group, regardless of whether those resources are shared by multiple clocks or not. However, access to resources that are shared between operations of the two groups needs to be protected by the drivers. An example of such a resource would be a register that controls both the clock rate and the clock enable/disable state.}(hjH hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj hhubh)}(hXThe clock framework is reentrant, in that a driver is allowed to call clock framework functions from within its implementation of clock operations. This can for instance cause a .set_rate operation of one clock being called from within the .set_rate operation of another clock. This case must be considered in the driver implementations, but the code flow is usually controlled by the driver in that case.h]hXThe clock framework is reentrant, in that a driver is allowed to call clock framework functions from within its implementation of clock operations. This can for instance cause a .set_rate operation of one clock being called from within the .set_rate operation of another clock. This case must be considered in the driver implementations, but the code flow is usually controlled by the driver in that case.}(hjV hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj hhubh)}(hNote that locking must also be considered when code outside of the common clock framework needs to access resources used by the clock operations. This is considered out of scope of this document.h]hNote that locking must also be considered when code outside of the common clock framework needs to access resources used by the clock operations. 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