csphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget'/translations/zh_CN/crypto/async-tx-apimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/zh_TW/crypto/async-tx-apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/it_IT/crypto/async-tx-apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ja_JP/crypto/async-tx-apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ko_KR/crypto/async-tx-apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/sp_SP/crypto/async-tx-apimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhA/var/lib/git/docbuild/linux/Documentation/crypto/async-tx-api.rsthKubhsection)}(hhh](htitle)}(h%Asynchronous Transfers/Transforms APIh]h%Asynchronous Transfers/Transforms API}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hXnContents 1. INTRODUCTION 2 GENEALOGY 3 USAGE 3.1 General format of the API 3.2 Supported operations 3.3 Descriptor management 3.4 When does the operation execute? 3.5 When does the operation complete? 3.6 Constraints 3.7 Example 4 DMAENGINE DRIVER DEVELOPER NOTES 4.1 Conformance points 4.2 "My application needs exclusive control of hardware channels" 5 SOURCEh]hXnContents 1. INTRODUCTION 2 GENEALOGY 3 USAGE 3.1 General format of the API 3.2 Supported operations 3.3 Descriptor management 3.4 When does the operation execute? 3.5 When does the operation complete? 3.6 Constraints 3.7 Example 4 DMAENGINE DRIVER DEVELOPER NOTES 4.1 Conformance points 4.2 "My application needs exclusive control of hardware channels" 5 SOURCE}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubh)}(hhh](h)}(h1. Introductionh]h1. Introduction}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe async_tx API provides methods for describing a chain of asynchronous bulk memory transfers/transforms with support for inter-transactional dependencies. It is implemented as a dmaengine client that smooths over the details of different hardware offload engine implementations. Code that is written to the API can optimize for asynchronous operation and the API will fit the chain of operations to the available offload resources.h]hXThe async_tx API provides methods for describing a chain of asynchronous bulk memory transfers/transforms with support for inter-transactional dependencies. It is implemented as a dmaengine client that smooths over the details of different hardware offload engine implementations. Code that is written to the API can optimize for asynchronous operation and the API will fit the chain of operations to the available offload resources.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h] introductionah ]h"]1. introductionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h 2.Genealogyh]h 2.Genealogy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK(ubh)}(hXvThe API was initially designed to offload the memory copy and xor-parity-calculations of the md-raid5 driver using the offload engines present in the Intel(R) Xscale series of I/O processors. It also built on the 'dmaengine' layer developed for offloading memory copies in the network stack using Intel(R) I/OAT engines. The following design features surfaced as a result:h]hXzThe API was initially designed to offload the memory copy and xor-parity-calculations of the md-raid5 driver using the offload engines present in the Intel(R) Xscale series of I/O processors. It also built on the ‘dmaengine’ layer developed for offloading memory copies in the network stack using Intel(R) I/OAT engines. The following design features surfaced as a result:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjhhubhenumerated_list)}(hhh](h list_item)}(himplicit synchronous path: users of the API do not need to know if the platform they are running on has offload capabilities. The operation will be offloaded when an engine is available and carried out in software otherwise.h]h)}(himplicit synchronous path: users of the API do not need to know if the platform they are running on has offload capabilities. The operation will be offloaded when an engine is available and carried out in software otherwise.h]himplicit synchronous path: users of the API do not need to know if the platform they are running on has offload capabilities. The operation will be offloaded when an engine is available and carried out in software otherwise.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj&ubah}(h]h ]h"]h$]h&]uh1j$hj!hhhhhNubj%)}(hXcross channel dependency chains: the API allows a chain of dependent operations to be submitted, like xor->copy->xor in the raid5 case. The API automatically handles cases where the transition from one operation to another implies a hardware channel switch.h]h)}(hXcross channel dependency chains: the API allows a chain of dependent operations to be submitted, like xor->copy->xor in the raid5 case. The API automatically handles cases where the transition from one operation to another implies a hardware channel switch.h]hXcross channel dependency chains: the API allows a chain of dependent operations to be submitted, like xor->copy->xor in the raid5 case. The API automatically handles cases where the transition from one operation to another implies a hardware channel switch.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hj>ubah}(h]h ]h"]h$]h&]uh1j$hj!hhhhhNubj%)}(hUdmaengine extensions to support multiple clients and operation types beyond 'memcpy' h]h)}(hTdmaengine extensions to support multiple clients and operation types beyond 'memcpy'h]hXdmaengine extensions to support multiple clients and operation types beyond ‘memcpy’}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjVubah}(h]h ]h"]h$]h&]uh1j$hj!hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjhhhhhK1ubeh}(h] genealogyah ]h"] 2.genealogyah$]h&]uh1hhhhhhhhK(ubh)}(hhh](h)}(h3. Usageh]h3. Usage}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK=ubh)}(hhh](h)}(h3.1 General format of the APIh]h3.1 General format of the API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK@ubh literal_block)}(hmstruct dma_async_tx_descriptor * async_(, struct async_submit_ctl *submit)h]hmstruct dma_async_tx_descriptor * async_(, struct async_submit_ctl *submit)}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKDhjhhubeh}(h]general-format-of-the-apiah ]h"]3.1 general format of the apiah$]h&]uh1hhjhhhhhK@ubh)}(hhh](h)}(h3.2 Supported operationsh]h3.2 Supported operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKHubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKDuh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hmemcpyh]hmemcpy}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h5memory copy between a source and a destination bufferh]h5memory copy between a source and a destination buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hmemseth]hmemset}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj/ubah}(h]h ]h"]h$]h&]uh1jhj,ubj)}(hhh]h)}(h+fill a destination buffer with a byte valueh]h+fill a destination buffer with a byte value}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhjFubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hxorh]hxor}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjfubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]h)}(hKxor a series of source buffers and write the result to a destination bufferh]hKxor a series of source buffers and write the result to a destination buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj}ubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hxor_valh]hxor_val}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h}xor a series of source buffers and set a flag if the result is zero. The implementation attempts to prevent writes to memoryh]h}xor a series of source buffers and set a flag if the result is zero. The implementation attempts to prevent writes to memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hpqh]hpq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAgenerate the p+q (raid6 syndrome) from a series of source buffersh]hAgenerate the p+q (raid6 syndrome) from a series of source buffers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hpq_valh]hpq_val}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hLvalidate that a p and or q buffer are in sync with a given series of sourcesh]hLvalidate that a p and or q buffer are in sync with a given series of sources}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(hdataph]hdatap}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(hU(raid6_datap_recov) recover a raid6 data block and the p block from the given sourcesh]hU(raid6_datap_recov) recover a raid6 data block and the p block from the given sources}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjYubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h2datah]h2data}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjyubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh]h)}(hF(raid6_2data_recov) recover 2 raid6 data blocks from the given sourcesh]hF(raid6_2data_recov) recover 2 raid6 data blocks from the given sources}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]supported-operationsah ]h"]3.2 supported operationsah$]h&]uh1hhjhhhhhKHubh)}(hhh](h)}(h3.3 Descriptor managementh]h3.3 Descriptor management}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK\ubh)}(hXdThe return value is non-NULL and points to a 'descriptor' when the operation has been queued to execute asynchronously. Descriptors are recycled resources, under control of the offload engine driver, to be reused as operations complete. When an application needs to submit a chain of operations it must guarantee that the descriptor is not automatically recycled before the dependency is submitted. This requires that all descriptors be acknowledged by the application before the offload engine driver is allowed to recycle (or free) the descriptor. A descriptor can be acked by one of the following methods:h]hXhThe return value is non-NULL and points to a ‘descriptor’ when the operation has been queued to execute asynchronously. Descriptors are recycled resources, under control of the offload engine driver, to be reused as operations complete. When an application needs to submit a chain of operations it must guarantee that the descriptor is not automatically recycled before the dependency is submitted. This requires that all descriptors be acknowledged by the application before the offload engine driver is allowed to recycle (or free) the descriptor. A descriptor can be acked by one of the following methods:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubj )}(hhh](j%)}(hHsetting the ASYNC_TX_ACK flag if no child operations are to be submittedh]h)}(hjh]hHsetting the ASYNC_TX_ACK flag if no child operations are to be submitted}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(h|submitting an unacknowledged descriptor as a dependency to another async_tx call will implicitly set the acknowledged state.h]h)}(h|submitting an unacknowledged descriptor as a dependency to another async_tx call will implicitly set the acknowledged state.h]h|submitting an unacknowledged descriptor as a dependency to another async_tx call will implicitly set the acknowledged state.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(h*calling async_tx_ack() on the descriptor. h]h)}(h)calling async_tx_ack() on the descriptor.h]h)calling async_tx_ack() on the descriptor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubeh}(h]h ]h"]h$]h&]jtjujvhjwjxuh1jhjhhhhhKhubeh}(h]descriptor-managementah ]h"]3.3 descriptor managementah$]h&]uh1hhjhhhhhK\ubh)}(hhh](h)}(h$3.4 When does the operation execute?h]h$3.4 When does the operation execute?}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhKnubh)}(hXOperations do not immediately issue after return from the async_ call. Offload engine drivers batch operations to improve performance by reducing the number of mmio cycles needed to manage the channel. Once a driver-specific threshold is met the driver automatically issues pending operations. An application can force this event by calling async_tx_issue_pending_all(). This operates on all channels since the application has no knowledge of channel to operation mapping.h]hXOperations do not immediately issue after return from the async_ call. Offload engine drivers batch operations to improve performance by reducing the number of mmio cycles needed to manage the channel. Once a driver-specific threshold is met the driver automatically issues pending operations. An application can force this event by calling async_tx_issue_pending_all(). This operates on all channels since the application has no knowledge of channel to operation mapping.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphj?hhubeh}(h]when-does-the-operation-executeah ]h"]$3.4 when does the operation execute?ah$]h&]uh1hhjhhhhhKnubh)}(hhh](h)}(h%3.5 When does the operation complete?h]h%3.5 When does the operation complete?}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhKzubh)}(hWThere are two methods for an application to learn about the completion of an operation.h]hWThere are two methods for an application to learn about the completion of an operation.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjfhhubj )}(hhh](j%)}(hCall dma_wait_for_async_tx(). This call causes the CPU to spin while it polls for the completion of the operation. It handles dependency chains and issuing pending operations.h]h)}(hCall dma_wait_for_async_tx(). This call causes the CPU to spin while it polls for the completion of the operation. It handles dependency chains and issuing pending operations.h]hCall dma_wait_for_async_tx(). This call causes the CPU to spin while it polls for the completion of the operation. It handles dependency chains and issuing pending operations.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(hXSpecify a completion callback. The callback routine runs in tasklet context if the offload engine driver supports interrupts, or it is called in application context if the operation is carried out synchronously in software. The callback can be set in the call to async_, or when the application needs to submit a chain of unknown length it can use the async_trigger_callback() routine to set a completion interrupt/callback at the end of the chain. h]h)}(hXSpecify a completion callback. The callback routine runs in tasklet context if the offload engine driver supports interrupts, or it is called in application context if the operation is carried out synchronously in software. The callback can be set in the call to async_, or when the application needs to submit a chain of unknown length it can use the async_trigger_callback() routine to set a completion interrupt/callback at the end of the chain.h]hXSpecify a completion callback. The callback routine runs in tasklet context if the offload engine driver supports interrupts, or it is called in application context if the operation is carried out synchronously in software. The callback can be set in the call to async_, or when the application needs to submit a chain of unknown length it can use the async_trigger_callback() routine to set a completion interrupt/callback at the end of the chain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubeh}(h]h ]h"]h$]h&]jtjujvhjwjxuh1jhjfhhhhhKubeh}(h] when-does-the-operation-completeah ]h"]%3.5 when does the operation complete?ah$]h&]uh1hhjhhhhhKzubh)}(hhh](h)}(h3.6 Constraintsh]h3.6 Constraints}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(hhh](j%)}(hCalls to async_ are not permitted in IRQ context. Other contexts are permitted provided constraint #2 is not violated.h]h)}(hCalls to async_ are not permitted in IRQ context. Other contexts are permitted provided constraint #2 is not violated.h]hCalls to async_ are not permitted in IRQ context. Other contexts are permitted provided constraint #2 is not violated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(hCompletion callback routines cannot submit new operations. This results in recursion in the synchronous case and spin_locks being acquired twice in the asynchronous case. h]h)}(hCompletion callback routines cannot submit new operations. This results in recursion in the synchronous case and spin_locks being acquired twice in the asynchronous case.h]hCompletion callback routines cannot submit new operations. This results in recursion in the synchronous case and spin_locks being acquired twice in the asynchronous case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubeh}(h]h ]h"]h$]h&]jtjujvhjwjxuh1jhjhhhhhKubeh}(h] constraintsah ]h"]3.6 constraintsah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h 3.7 Exampleh]h 3.7 Example}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hkPerform a xor->copy->xor operation where each operation depends on the result from the previous operation::h]hjPerform a xor->copy->xor operation where each operation depends on the result from the previous operation:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX#include static void callback(void *param) { complete(param); } #define NDISKS 2 static void run_xor_copy_xor(struct page **xor_srcs, struct page *xor_dest, size_t xor_len, struct page *copy_src, struct page *copy_dest, size_t copy_len) { struct dma_async_tx_descriptor *tx; struct async_submit_ctl submit; addr_conv_t addr_conv[NDISKS]; struct completion cmp; init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL, addr_conv); tx = async_xor(xor_dest, xor_srcs, 0, NDISKS, xor_len, &submit); submit.depend_tx = tx; tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit); init_completion(&cmp); init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx, callback, &cmp, addr_conv); tx = async_xor(xor_dest, xor_srcs, 0, NDISKS, xor_len, &submit); async_tx_issue_pending_all(); wait_for_completion(&cmp); }h]hX#include static void callback(void *param) { complete(param); } #define NDISKS 2 static void run_xor_copy_xor(struct page **xor_srcs, struct page *xor_dest, size_t xor_len, struct page *copy_src, struct page *copy_dest, size_t copy_len) { struct dma_async_tx_descriptor *tx; struct async_submit_ctl submit; addr_conv_t addr_conv[NDISKS]; struct completion cmp; init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL, addr_conv); tx = async_xor(xor_dest, xor_srcs, 0, NDISKS, xor_len, &submit); submit.depend_tx = tx; tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit); init_completion(&cmp); init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx, callback, &cmp, addr_conv); tx = async_xor(xor_dest, xor_srcs, 0, NDISKS, xor_len, &submit); async_tx_issue_pending_all(); wait_for_completion(&cmp); }}hj7sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubh)}(hSee include/linux/async_tx.h for more information on the flags. See the ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more implementation examples.h]hSee include/linux/async_tx.h for more information on the flags. See the ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more implementation examples.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]exampleah ]h"] 3.7 exampleah$]h&]uh1hhjhhhhhKubeh}(h]usageah ]h"]3. usageah$]h&]uh1hhhhhhhhK=ubh)}(hhh](h)}(h4. Driver Development Notesh]h4. Driver Development Notes}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchhhhhKubh)}(hhh](h)}(h4.1 Conformance pointsh]h4.1 Conformance points}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjthhhhhKubh)}(hThere are a few conformance points required in dmaengine drivers to accommodate assumptions made by applications using the async_tx API:h]hThere are a few conformance points required in dmaengine drivers to accommodate assumptions made by applications using the async_tx API:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjthhubj )}(hhh](j%)}(h>Completion callbacks are expected to happen in tasklet contexth]h)}(hjh]h>Completion callbacks are expected to happen in tasklet context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(hCdma_async_tx_descriptor fields are never manipulated in IRQ contexth]h)}(hjh]hCdma_async_tx_descriptor fields are never manipulated in IRQ context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubj%)}(hmUse async_tx_run_dependencies() in the descriptor clean up path to handle submission of dependent operations h]h)}(hlUse async_tx_run_dependencies() in the descriptor clean up path to handle submission of dependent operationsh]hlUse async_tx_run_dependencies() in the descriptor clean up path to handle submission of dependent operations}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjhhhhhNubeh}(h]h ]h"]h$]h&]jtjujvhjwjxuh1jhjthhhhhKubeh}(h]conformance-pointsah ]h"]4.1 conformance pointsah$]h&]uh1hhjchhhhhKubh)}(hhh](h)}(hA4.2 "My application needs exclusive control of hardware channels"h]hE4.2 “My application needs exclusive control of hardware channels”}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX$Primarily this requirement arises from cases where a DMA engine driver is being used to support device-to-memory operations. A channel that is performing these operations cannot, for many platform specific reasons, be shared. For these cases the dma_request_channel() interface is provided.h]hX$Primarily this requirement arises from cases where a DMA engine driver is being used to support device-to-memory operations. A channel that is performing these operations cannot, for many platform specific reasons, be shared. For these cases the dma_request_channel() interface is provided.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThe interface is::h]hThe interface is:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hstruct dma_chan *dma_request_channel(dma_cap_mask_t mask, dma_filter_fn filter_fn, void *filter_param);h]hstruct dma_chan *dma_request_channel(dma_cap_mask_t mask, dma_filter_fn filter_fn, void *filter_param);}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubh)}(h#Where dma_filter_fn is defined as::h]h"Where dma_filter_fn is defined as:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hItypedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);h]hItypedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);}hj3sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubh)}(hXyWhen the optional 'filter_fn' parameter is set to NULL dma_request_channel simply returns the first channel that satisfies the capability mask. Otherwise, when the mask parameter is insufficient for specifying the necessary channel, the filter_fn routine can be used to disposition the available channels in the system. The filter_fn routine is called once for each free channel in the system. Upon seeing a suitable channel filter_fn returns DMA_ACK which flags that channel to be the return value from dma_request_channel. A channel allocated via this interface is exclusive to the caller, until dma_release_channel() is called.h]hX}When the optional ‘filter_fn’ parameter is set to NULL dma_request_channel simply returns the first channel that satisfies the capability mask. Otherwise, when the mask parameter is insufficient for specifying the necessary channel, the filter_fn routine can be used to disposition the available channels in the system. The filter_fn routine is called once for each free channel in the system. Upon seeing a suitable channel filter_fn returns DMA_ACK which flags that channel to be the return value from dma_request_channel. A channel allocated via this interface is exclusive to the caller, until dma_release_channel() is called.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX'The DMA_PRIVATE capability flag is used to tag dma devices that should not be used by the general-purpose allocator. It can be set at initialization time if it is known that a channel will always be private. Alternatively, it is set when dma_request_channel() finds an unused "public" channel.h]hX+The DMA_PRIVATE capability flag is used to tag dma devices that should not be used by the general-purpose allocator. It can be set at initialization time if it is known that a channel will always be private. Alternatively, it is set when dma_request_channel() finds an unused “public” channel.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hAA couple caveats to note when implementing a driver and consumer:h]hAA couple caveats to note when implementing a driver and consumer:}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj )}(hhh](j%)}(hOnce a channel has been privately allocated it will no longer be considered by the general-purpose allocator even after a call to dma_release_channel().h]h)}(hOnce a channel has been privately allocated it will no longer be considered by the general-purpose allocator even after a call to dma_release_channel().h]hOnce a channel has been privately allocated it will no longer be considered by the general-purpose allocator even after a call to dma_release_channel().}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnubah}(h]h ]h"]h$]h&]uh1j$hjkhhhhhNubj%)}(hSince capabilities are specified at the device level a dma_device with multiple channels will either have all channels public, or all channels private. h]h)}(hSince capabilities are specified at the device level a dma_device with multiple channels will either have all channels public, or all channels private.h]hSince capabilities are specified at the device level a dma_device with multiple channels will either have all channels public, or all channels private.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j$hjkhhhhhNubeh}(h]h ]h"]h$]h&]jtjujvhjwjxuh1jhjhhhhhKubeh}(h];my-application-needs-exclusive-control-of-hardware-channelsah ]h"]A4.2 "my application needs exclusive control of hardware channels"ah$]h&]uh1hhjchhhhhKubh)}(hhh](h)}(h 5. Sourceh]h 5. Source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubhdefinition_list)}(hhh](hdefinition_list_item)}(hIinclude/linux/dmaengine.h: core header file for DMA drivers and api usersh](hterm)}(hinclude/linux/dmaengine.h:h]hinclude/linux/dmaengine.h:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubh definition)}(hhh]h)}(h.core header file for DMA drivers and api usersh]h.core header file for DMA drivers and api users}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hCdrivers/dma/dmaengine.c: offload engine channel management routinesh](j)}(hdrivers/dma/dmaengine.c:h]hdrivers/dma/dmaengine.c:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(h*offload engine channel management routinesh]h*offload engine channel management routines}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(h1drivers/dma/: location for offload engine driversh](j)}(h drivers/dma/:h]h drivers/dma/:}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj&ubj)}(hhh]h)}(h#location for offload engine driversh]h#location for offload engine drivers}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(h?include/linux/async_tx.h: core header file for the async_tx apih](j)}(hinclude/linux/async_tx.h:h]hinclude/linux/async_tx.h:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjUubj)}(hhh]h)}(h%core header file for the async_tx apih]h%core header file for the async_tx api}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjgubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhhhMhjhhubj)}(hKcrypto/async_tx/async_tx.c: async_tx interface to dmaengine and common codeh](j)}(hcrypto/async_tx/async_tx.c:h]hcrypto/async_tx/async_tx.c:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj)}(hhh]h)}(h/async_tx interface to dmaengine and common codeh]h/async_tx interface to dmaengine and common code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(h,crypto/async_tx/async_memcpy.c: copy offloadh](j)}(hcrypto/async_tx/async_memcpy.c:h]hcrypto/async_tx/async_memcpy.c:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj)}(hhh]h)}(h copy offloadh]h copy offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(h9crypto/async_tx/async_xor.c: xor and xor zero sum offloadh](j)}(hcrypto/async_tx/async_xor.c:h]hcrypto/async_tx/async_xor.c:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj)}(hhh]h)}(hxor and xor zero sum offloadh]hxor and xor zero sum offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]sourceah ]h"] 5. sourceah$]h&]uh1hhjchhhhhKubeh}(h]driver-development-notesah ]h"]4. driver development notesah$]h&]uh1hhhhhhhhKubeh}(h]%asynchronous-transfers-transforms-apiah ]h"]%asynchronous transfers/transforms apiah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjQerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j,j)hhj~j{j`j]jjjjj<j9jcj`jjjjjXjUj$j!jjjjjju nametypes}(j,hj~j`jjj<jcjjjXj$jjjuh}(j)hhhj{jj]jjjjjj9jj`j?jjfjjjUjj!jcjjtjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.