€•hK      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ,/translations/zh_CN/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/zh_TW/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/it_IT/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/ja_JP/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/ko_KR/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/pt_BR/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ,/translations/sp_SP/core-api/irq/managed_irq”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³ŒF/var/lib/git/docbuild/linux/Documentation/core-api/irq/managed_irq.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒAffinity managed interrupts”h]”hŒAffinity managed interrupts”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒõThe IRQ core provides support for managing interrupts according to a specified
CPU affinity. Under normal operation, an interrupt is associated with a
particular CPU. If that CPU is taken offline, the interrupt is migrated to
another online CPU.”h]”hŒõThe IRQ core provides support for managing interrupts according to a specified
CPU affinity. Under normal operation, an interrupt is associated with a
particular CPU. If that CPU is taken offline, the interrupt is migrated to
another online CPU.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hXY  Devices with large numbers of interrupt vectors can stress the available vector
space. For example, an NVMe device with 128 I/O queues typically requests one
interrupt per queue on systems with at least 128 CPUs. Two such devices
therefore request 256 interrupts. On x86, the interrupt vector space is
notoriously low, providing only 256 vectors per CPU, and the kernel reserves a
subset of these, further reducing the number available for device interrupts.
In practice this is not an issue because the interrupts are distributed across
many CPUs, so each CPU only receives a small number of vectors.”h]”hXY  Devices with large numbers of interrupt vectors can stress the available vector
space. For example, an NVMe device with 128 I/O queues typically requests one
interrupt per queue on systems with at least 128 CPUs. Two such devices
therefore request 256 interrupts. On x86, the interrupt vector space is
notoriously low, providing only 256 vectors per CPU, and the kernel reserves a
subset of these, further reducing the number available for device interrupts.
In practice this is not an issue because the interrupts are distributed across
many CPUs, so each CPU only receives a small number of vectors.”…””}”(hhíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hŒñDuring system suspend, however, all secondary CPUs are taken offline and all
interrupts are migrated to the single CPU that remains online. This can exhaust
the available interrupt vectors on that CPU and cause the suspend operation to
fail.”h]”hŒñDuring system suspend, however, all secondary CPUs are taken offline and all
interrupts are migrated to the single CPU that remains online. This can exhaust
the available interrupt vectors on that CPU and cause the suspend operation to
fail.”…””}”(hhûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hXI  Affinityâ€‘managed interrupts address this limitation. Each interrupt is assigned
a CPU affinity mask that specifies the set of CPUs on which the interrupt may
be targeted. When a CPU in the mask goes offline, the interrupt is moved to the
next CPU in the mask. If the last CPU in the mask goes offline, the interrupt
is shut down. Drivers using affinityâ€‘managed interrupts must ensure that the
associated queue is quiesced before the interrupt is disabled so that no
further interrupts are generated. When a CPU in the affinity mask comes back
online, the interrupt is reâ€‘enabled.”h]”hXI  Affinityâ€‘managed interrupts address this limitation. Each interrupt is assigned
a CPU affinity mask that specifies the set of CPUs on which the interrupt may
be targeted. When a CPU in the mask goes offline, the interrupt is moved to the
next CPU in the mask. If the last CPU in the mask goes offline, the interrupt
is shut down. Drivers using affinityâ€‘managed interrupts must ensure that the
associated queue is quiesced before the interrupt is disabled so that no
further interrupts are generated. When a CPU in the affinity mask comes back
online, the interrupt is reâ€‘enabled.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒImplementation”h]”hŒImplementation”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj  h²hh³hÇh´K$ubhÞ)”}”(hXD  Devices must provide perâ€‘instance interrupts, such as perâ€‘I/Oâ€‘queue interrupts
for storage devices like NVMe. The driver allocates interrupt vectors with the
required affinity settings using struct irq_affinity. For MSIâ€‘X devices, this
is done via pci_alloc_irq_vectors_affinity() with the PCI_IRQ_AFFINITY flag
set.”h]”hXD  Devices must provide perâ€‘instance interrupts, such as perâ€‘I/Oâ€‘queue interrupts
for storage devices like NVMe. The driver allocates interrupt vectors with the
required affinity settings using struct irq_affinity. For MSIâ€‘X devices, this
is done via pci_alloc_irq_vectors_affinity() with the PCI_IRQ_AFFINITY flag
set.”…””}”(hj(  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K&hj  h²hubhÞ)”}”(hŒúBased on the provided affinity information, the IRQ core attempts to spread the
interrupts evenly across the system. The affinity masks are computed during
this allocation step, but the final IRQ assignment is performed when
request_irq() is invoked.”h]”hŒúBased on the provided affinity information, the IRQ core attempts to spread the
interrupts evenly across the system. The affinity masks are computed during
this allocation step, but the final IRQ assignment is performed when
request_irq() is invoked.”…””}”(hj6  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K,hj  h²hubeh}”(h]”Œimplementation”ah ]”h"]”Œimplementation”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K$ubhÉ)”}”(hhh]”(hÎ)”}”(hŒIsolated CPUs”h]”hŒIsolated CPUs”…””}”(hjO  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjL  h²hh³hÇh´K2ubhÞ)”}”(hXë  The affinity of managed interrupts is handled entirely in the kernel and cannot
be modified from user space through the /proc interfaces. The managed_irq
subâ€‘parameter of the isolcpus boot option specifies a CPU mask that managed
interrupts should attempt to avoid. This isolation is bestâ€‘effort and only
applies if the automatically assigned interrupt mask also contains online CPUs
outside the avoided mask. If the requested mask contains only isolated CPUs,
the setting has no effect.”h]”hXë  The affinity of managed interrupts is handled entirely in the kernel and cannot
be modified from user space through the /proc interfaces. The managed_irq
subâ€‘parameter of the isolcpus boot option specifies a CPU mask that managed
interrupts should attempt to avoid. This isolation is bestâ€‘effort and only
applies if the automatically assigned interrupt mask also contains online CPUs
outside the avoided mask. If the requested mask contains only isolated CPUs,
the setting has no effect.”…””}”(hj]  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K4hjL  h²hubhÞ)”}”(hŒäCPUs listed in the avoided mask remain part of the interruptâ€™s affinity mask.
This means that if all nonâ€‘isolated CPUs go offline while isolated CPUs remain
online, the interrupt will be assigned to one of the isolated CPUs.”h]”hŒäCPUs listed in the avoided mask remain part of the interruptâ€™s affinity mask.
This means that if all nonâ€‘isolated CPUs go offline while isolated CPUs remain
online, the interrupt will be assigned to one of the isolated CPUs.”…””}”(hjk  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K<hjL  h²hubhÞ)”}”(hŒ3The following examples assume a system with 8 CPUs.”h]”hŒ3The following examples assume a system with 8 CPUs.”…””}”(hjy  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K@hjL  h²hubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX:  A QEMU instance is booted with "-device virtio-scsi-pci".
The MSIâ€‘X device exposes 11 interrupts: 3 "management" interrupts and 8
"queue" interrupts. The driver requests the 8 queue interrupts, each of which
is affine to exactly one CPU. If that CPU goes offline, the interrupt is shut
down.

Assuming interrupt 48 is one of the queue interrupts, the following appears::

  /proc/irq/48/effective_affinity_list:7
  /proc/irq/48/smp_affinity_list:7

This indicates that the interrupt is served only by CPU7. Shutting down CPU7
does not migrate the interrupt to another CPU::

  /proc/irq/48/effective_affinity_list:0
  /proc/irq/48/smp_affinity_list:7

This can be verified via the debugfs interface
(/sys/kernel/debug/irq/irqs/48). The dstate field will include
IRQD_IRQ_DISABLED, IRQD_IRQ_MASKED and IRQD_MANAGED_SHUTDOWN.
”h]”(hÞ)”}”(hX%  A QEMU instance is booted with "-device virtio-scsi-pci".
The MSIâ€‘X device exposes 11 interrupts: 3 "management" interrupts and 8
"queue" interrupts. The driver requests the 8 queue interrupts, each of which
is affine to exactly one CPU. If that CPU goes offline, the interrupt is shut
down.”h]”hX1  A QEMU instance is booted with â€œ-device virtio-scsi-pciâ€.
The MSIâ€‘X device exposes 11 interrupts: 3 â€œmanagementâ€ interrupts and 8
â€œqueueâ€ interrupts. The driver requests the 8 queue interrupts, each of which
is affine to exactly one CPU. If that CPU goes offline, the interrupt is shut
down.”…””}”(hj’  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KBhjŽ  ubhÞ)”}”(hŒMAssuming interrupt 48 is one of the queue interrupts, the following appears::”h]”hŒLAssuming interrupt 48 is one of the queue interrupts, the following appears:”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KHhjŽ  ubhŒliteral_block”“”)”}”(hŒG/proc/irq/48/effective_affinity_list:7
/proc/irq/48/smp_affinity_list:7”h]”hŒG/proc/irq/48/effective_affinity_list:7
/proc/irq/48/smp_affinity_list:7”…””}”hj°  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j®  h³hÇh´KJhjŽ  ubhÞ)”}”(hŒ|This indicates that the interrupt is served only by CPU7. Shutting down CPU7
does not migrate the interrupt to another CPU::”h]”hŒ{This indicates that the interrupt is served only by CPU7. Shutting down CPU7
does not migrate the interrupt to another CPU:”…””}”(hj¾  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KMhjŽ  ubj¯  )”}”(hŒG/proc/irq/48/effective_affinity_list:0
/proc/irq/48/smp_affinity_list:7”h]”hŒG/proc/irq/48/effective_affinity_list:0
/proc/irq/48/smp_affinity_list:7”…””}”hjÌ  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j®  h³hÇh´KPhjŽ  ubhÞ)”}”(hŒ«This can be verified via the debugfs interface
(/sys/kernel/debug/irq/irqs/48). The dstate field will include
IRQD_IRQ_DISABLED, IRQD_IRQ_MASKED and IRQD_MANAGED_SHUTDOWN.”h]”hŒ«This can be verified via the debugfs interface
(/sys/kernel/debug/irq/irqs/48). The dstate field will include
IRQD_IRQ_DISABLED, IRQD_IRQ_MASKED and IRQD_MANAGED_SHUTDOWN.”…””}”(hjÚ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KShjŽ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jŒ  hj‰  h²hh³hÇh´Nubj  )”}”(hX“  A QEMU instance is booted with "-device virtio-scsi-pci,num_queues=2"
and the kernel command line includes:
"irqaffinity=0,1 isolcpus=domain,2-7 isolcpus=managed_irq,1-3,5-7".
The MSIâ€‘X device exposes 5 interrupts: 3 management interrupts and 2 queue
interrupts. The management interrupts follow the irqaffinity= setting. The
queue interrupts are spread across available CPUs::

  /proc/irq/47/effective_affinity_list:0
  /proc/irq/47/smp_affinity_list:0-3
  /proc/irq/48/effective_affinity_list:4
  /proc/irq/48/smp_affinity_list:4-7

The two queue interrupts are evenly distributed. Interrupt 48 is placed on CPU4
because the managed_irq mask avoids CPUs 5â€“7 when possible.

Replacing the managed_irq argument with "isolcpus=managed_irq,1-3,4-5,7"
results in::

  /proc/irq/48/effective_affinity_list:6
  /proc/irq/48/smp_affinity_list:4-7

Interrupt 48 is now served on CPU6 because the system avoids CPUs 4, 5 and
7. If CPU6 is taken offline, the interrupt migrates to one of the "isolated"
CPUs::

  /proc/irq/48/effective_affinity_list:7
  /proc/irq/48/smp_affinity_list:4-7

The interrupt is shut down once all CPUs listed in its smp_affinity mask are
offline.”h]”(hÞ)”}”(hX{  A QEMU instance is booted with "-device virtio-scsi-pci,num_queues=2"
and the kernel command line includes:
"irqaffinity=0,1 isolcpus=domain,2-7 isolcpus=managed_irq,1-3,5-7".
The MSIâ€‘X device exposes 5 interrupts: 3 management interrupts and 2 queue
interrupts. The management interrupts follow the irqaffinity= setting. The
queue interrupts are spread across available CPUs::”h]”hX‚  A QEMU instance is booted with â€œ-device virtio-scsi-pci,num_queues=2â€
and the kernel command line includes:
â€œirqaffinity=0,1 isolcpus=domain,2-7 isolcpus=managed_irq,1-3,5-7â€.
The MSIâ€‘X device exposes 5 interrupts: 3 management interrupts and 2 queue
interrupts. The management interrupts follow the irqaffinity= setting. The
queue interrupts are spread across available CPUs:”…””}”(hjò  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KWhjî  ubj¯  )”}”(hŒ“/proc/irq/47/effective_affinity_list:0
/proc/irq/47/smp_affinity_list:0-3
/proc/irq/48/effective_affinity_list:4
/proc/irq/48/smp_affinity_list:4-7”h]”hŒ“/proc/irq/47/effective_affinity_list:0
/proc/irq/47/smp_affinity_list:0-3
/proc/irq/48/effective_affinity_list:4
/proc/irq/48/smp_affinity_list:4-7”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j®  h³hÇh´K^hjî  ubhÞ)”}”(hŒThe two queue interrupts are evenly distributed. Interrupt 48 is placed on CPU4
because the managed_irq mask avoids CPUs 5â€“7 when possible.”h]”hŒThe two queue interrupts are evenly distributed. Interrupt 48 is placed on CPU4
because the managed_irq mask avoids CPUs 5â€“7 when possible.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kchjî  ubhÞ)”}”(hŒUReplacing the managed_irq argument with "isolcpus=managed_irq,1-3,4-5,7"
results in::”h]”hŒXReplacing the managed_irq argument with â€œisolcpus=managed_irq,1-3,4-5,7â€
results in:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kfhjî  ubj¯  )”}”(hŒI/proc/irq/48/effective_affinity_list:6
/proc/irq/48/smp_affinity_list:4-7”h]”hŒI/proc/irq/48/effective_affinity_list:6
/proc/irq/48/smp_affinity_list:4-7”…””}”hj*  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j®  h³hÇh´Kihjî  ubhÞ)”}”(hŒžInterrupt 48 is now served on CPU6 because the system avoids CPUs 4, 5 and
7. If CPU6 is taken offline, the interrupt migrates to one of the "isolated"
CPUs::”h]”hŒ¡Interrupt 48 is now served on CPU6 because the system avoids CPUs 4, 5 and
7. If CPU6 is taken offline, the interrupt migrates to one of the â€œisolatedâ€
CPUs:”…””}”(hj8  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Klhjî  ubj¯  )”}”(hŒI/proc/irq/48/effective_affinity_list:7
/proc/irq/48/smp_affinity_list:4-7”h]”hŒI/proc/irq/48/effective_affinity_list:7
/proc/irq/48/smp_affinity_list:4-7”…””}”hjF  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j®  h³hÇh´Kphjî  ubhÞ)”}”(hŒUThe interrupt is shut down once all CPUs listed in its smp_affinity mask are
offline.”h]”hŒUThe interrupt is shut down once all CPUs listed in its smp_affinity mask are
offline.”…””}”(hjT  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kshjî  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jŒ  hj‰  h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j‡  h³hÇh´KBhjL  h²hubeh}”(h]”Œisolated-cpus”ah ]”h"]”Œisolated cpus”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K2ubeh}”(h]”Œaffinity-managed-interrupts”ah ]”h"]”Œaffinity managed interrupts”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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