(sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget'/translations/zh_CN/core-api/genericirqmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/zh_TW/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/it_IT/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ja_JP/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/ko_KR/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/pt_BR/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget'/translations/sp_SP/core-api/genericirqmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .h]hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsubstitution_definition)}(h*.. |amp| unicode:: U+00026 .. AMPERSANDh]h&}hhsbah}(h]h ]h"]ampah$]h&]uh1hhhhKhhhhubh)}(h+.. |apos| unicode:: U+00027 .. APOSTROPHEh]h'}hhsbah}(h]h ]h"]aposah$]h&]uh1hhhhKhhhhubh)}(h).. |ast| unicode:: U+0002A .. ASTERISKh]h*}hhsbah}(h]h ]h"]astah$]h&]uh1hhhhK hhhhubh)}(h+.. |brvbar| unicode:: U+000A6 .. BROKEN BARh]h¦}hjsbah}(h]h ]h"]brvbarah$]h&]uh1hhhhK hhhhubh)}(h0.. |bsol| unicode:: U+0005C .. REVERSE SOLIDUSh]h\}hjsbah}(h]h ]h"]bsolah$]h&]uh1hhhhK hhhhubh)}(h*.. |cent| unicode:: U+000A2 .. CENT SIGNh]h¢}hj#sbah}(h]h ]h"]centah$]h&]uh1hhhhK hhhhubh)}(h&.. |colon| unicode:: U+0003A .. COLONh]h:}hj2sbah}(h]h ]h"]colonah$]h&]uh1hhhhK hhhhubh)}(h&.. |comma| unicode:: U+0002C .. COMMAh]h,}hjAsbah}(h]h ]h"]commaah$]h&]uh1hhhhKhhhhubh)}(h... |commat| unicode:: U+00040 .. COMMERCIAL ATh]h@}hjPsbah}(h]h ]h"]commatah$]h&]uh1hhhhKhhhhubh)}(h/.. |copy| unicode:: U+000A9 .. COPYRIGHT SIGNh]h©}hj_sbah}(h]h ]h"]copyah$]h&]uh1hhhhKhhhhubh)}(h... |curren| unicode:: U+000A4 .. CURRENCY SIGNh]h¤}hjnsbah}(h]h ]h"]currenah$]h&]uh1hhhhKhhhhubh)}(h0.. |darr| unicode:: U+02193 .. DOWNWARDS ARROWh]h↓}hj}sbah}(h]h ]h"]darrah$]h&]uh1hhhhKhhhhubh)}(h,.. |deg| unicode:: U+000B0 .. DEGREE SIGNh]h°}hjsbah}(h]h ]h"]degah$]h&]uh1hhhhKhhhhubh)}(h... |divide| unicode:: U+000F7 .. DIVISION SIGNh]h÷}hjsbah}(h]h ]h"]divideah$]h&]uh1hhhhKhhhhubh)}(h,.. |dollar| unicode:: U+00024 .. DOLLAR SIGNh]h$}hjsbah}(h]h ]h"]dollarah$]h&]uh1hhhhKhhhhubh)}(h,.. |equals| unicode:: U+0003D .. EQUALS SIGNh]h=}hjsbah}(h]h ]h"]equalsah$]h&]uh1hhhhKhhhhubh)}(h1.. |excl| unicode:: U+00021 .. EXCLAMATION MARKh]h!}hjsbah}(h]h ]h"]exclah$]h&]uh1hhhhKhhhhubh)}(h9.. |frac12| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjsbah}(h]h ]h"]frac12ah$]h&]uh1hhhhKhhhhubh)}(h<.. |frac14| unicode:: U+000BC .. VULGAR FRACTION ONE QUARTERh]h¼}hjsbah}(h]h ]h"]frac14ah$]h&]uh1hhhhKhhhhubh)}(h;.. |frac18| unicode:: U+0215B .. VULGAR FRACTION ONE EIGHTHh]h⅛}hjsbah}(h]h ]h"]frac18ah$]h&]uh1hhhhKhhhhubh)}(h?.. |frac34| unicode:: U+000BE .. VULGAR FRACTION THREE QUARTERSh]h¾}hjsbah}(h]h ]h"]frac34ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac38| unicode:: U+0215C .. VULGAR FRACTION THREE EIGHTHSh]h⅜}hjsbah}(h]h ]h"]frac38ah$]h&]uh1hhhhKhhhhubh)}(h=.. |frac58| unicode:: U+0215D .. VULGAR FRACTION FIVE EIGHTHSh]h⅝}hj"sbah}(h]h ]h"]frac58ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac78| unicode:: U+0215E .. VULGAR FRACTION SEVEN EIGHTHSh]h⅞}hj1sbah}(h]h ]h"]frac78ah$]h&]uh1hhhhKhhhhubh)}(h2.. |gt| unicode:: U+0003E .. GREATER-THAN SIGNh]h>}hj@sbah}(h]h ]h"]gtah$]h&]uh1hhhhKhhhhubh)}(h9.. |half| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjOsbah}(h]h ]h"]halfah$]h&]uh1hhhhK hhhhubh)}(h/.. |horbar| unicode:: U+02015 .. HORIZONTAL BARh]h―}hj^sbah}(h]h ]h"]horbarah$]h&]uh1hhhhK!hhhhubh)}(h'.. |hyphen| unicode:: U+02010 .. HYPHENh]h‐}hjmsbah}(h]h ]h"]hyphenah$]h&]uh1hhhhK"hhhhubh)}(h:.. |iexcl| unicode:: U+000A1 .. INVERTED EXCLAMATION MARKh]h¡}hj|sbah}(h]h ]h"]iexclah$]h&]uh1hhhhK#hhhhubh)}(h7.. |iquest| unicode:: U+000BF .. INVERTED QUESTION MARKh]h¿}hjsbah}(h]h ]h"]iquestah$]h&]uh1hhhhK$hhhhubh)}(hJ.. |laquo| unicode:: U+000AB .. LEFT-POINTING DOUBLE ANGLE QUOTATION MARKh]h«}hjsbah}(h]h ]h"]laquoah$]h&]uh1hhhhK%hhhhubh)}(h0.. |larr| unicode:: U+02190 .. LEFTWARDS ARROWh]h←}hjsbah}(h]h ]h"]larrah$]h&]uh1hhhhK&hhhhubh)}(h3.. |lcub| unicode:: U+0007B .. LEFT CURLY BRACKETh]h{}hjsbah}(h]h ]h"]lcubah$]h&]uh1hhhhK'hhhhubh)}(h;.. |ldquo| unicode:: U+0201C .. LEFT DOUBLE QUOTATION MARKh]h“}hjsbah}(h]h ]h"]ldquoah$]h&]uh1hhhhK(hhhhubh)}(h).. |lowbar| unicode:: U+0005F .. LOW LINEh]h_}hjsbah}(h]h ]h"]lowbarah$]h&]uh1hhhhK)hhhhubh)}(h1.. |lpar| unicode:: U+00028 .. LEFT PARENTHESISh]h(}hjsbah}(h]h ]h"]lparah$]h&]uh1hhhhK*hhhhubh)}(h4.. |lsqb| unicode:: U+0005B .. LEFT SQUARE BRACKETh]h[}hjsbah}(h]h ]h"]lsqbah$]h&]uh1hhhhK+hhhhubh)}(h;.. |lsquo| unicode:: U+02018 .. LEFT SINGLE QUOTATION MARKh]h‘}hjsbah}(h]h ]h"]lsquoah$]h&]uh1hhhhK,hhhhubh)}(h/.. |lt| unicode:: U+0003C .. LESS-THAN SIGNh]h<}hjsbah}(h]h ]h"]ltah$]h&]uh1hhhhK-hhhhubh)}(h+.. |micro| unicode:: U+000B5 .. MICRO SIGNh]hµ}hj!sbah}(h]h ]h"]microah$]h&]uh1hhhhK.hhhhubh)}(h+.. |middot| unicode:: U+000B7 .. MIDDLE DOTh]h·}hj0sbah}(h]h ]h"]middotah$]h&]uh1hhhhK/hhhhubh)}(h/.. |nbsp| unicode:: U+000A0 .. NO-BREAK SPACEh]h }hj?sbah}(h]h ]h"]nbspah$]h&]uh1hhhhK0hhhhubh)}(h).. |not| unicode:: U+000AC .. NOT SIGNh]h¬}hjNsbah}(h]h ]h"]notah$]h&]uh1hhhhK1hhhhubh)}(h,.. |num| unicode:: U+00023 .. NUMBER SIGNh]h#}hj]sbah}(h]h ]h"]numah$]h&]uh1hhhhK2hhhhubh)}(h).. |ohm| unicode:: U+02126 .. OHM SIGNh]hΩ}hjlsbah}(h]h ]h"]ohmah$]h&]uh1hhhhK3hhhhubh)}(h;.. |ordf| unicode:: U+000AA .. FEMININE ORDINAL INDICATORh]hª}hj{sbah}(h]h ]h"]ordfah$]h&]uh1hhhhK4hhhhubh)}(h<.. |ordm| unicode:: U+000BA .. MASCULINE ORDINAL INDICATORh]hº}hjsbah}(h]h ]h"]ordmah$]h&]uh1hhhhK5hhhhubh)}(h-.. |para| unicode:: U+000B6 .. PILCROW SIGNh]h¶}hjsbah}(h]h ]h"]paraah$]h&]uh1hhhhK6hhhhubh)}(h-.. |percnt| unicode:: U+00025 .. PERCENT SIGNh]h%}hjsbah}(h]h ]h"]percntah$]h&]uh1hhhhK7hhhhubh)}(h*.. |period| unicode:: U+0002E .. FULL STOPh]h.}hjsbah}(h]h ]h"]periodah$]h&]uh1hhhhK8hhhhubh)}(h*.. |plus| unicode:: U+0002B .. PLUS SIGNh]h+}hjsbah}(h]h ]h"]plusah$]h&]uh1hhhhK9hhhhubh)}(h0.. |plusmn| unicode:: U+000B1 .. PLUS-MINUS SIGNh]h±}hjsbah}(h]h ]h"]plusmnah$]h&]uh1hhhhK:hhhhubh)}(h+.. |pound| unicode:: U+000A3 .. POUND SIGNh]h£}hjsbah}(h]h ]h"]poundah$]h&]uh1hhhhK;hhhhubh)}(h... |quest| unicode:: U+0003F .. QUESTION MARKh]h?}hjsbah}(h]h ]h"]questah$]h&]uh1hhhhKhhhhubh)}(h1.. |rarr| unicode:: U+02192 .. RIGHTWARDS ARROWh]h→}hj sbah}(h]h ]h"]rarrah$]h&]uh1hhhhK?hhhhubh)}(h4.. |rcub| unicode:: U+0007D .. RIGHT CURLY BRACKETh]h}}hj/sbah}(h]h ]h"]rcubah$]h&]uh1hhhhK@hhhhubh)}(h<.. |rdquo| unicode:: U+0201D .. RIGHT DOUBLE QUOTATION MARKh]h”}hj>sbah}(h]h ]h"]rdquoah$]h&]uh1hhhhKAhhhhubh)}(h0.. |reg| unicode:: U+000AE .. REGISTERED SIGNh]h®}hjMsbah}(h]h ]h"]regah$]h&]uh1hhhhKBhhhhubh)}(h2.. |rpar| unicode:: U+00029 .. RIGHT PARENTHESISh]h)}hj\sbah}(h]h ]h"]rparah$]h&]uh1hhhhKChhhhubh)}(h5.. |rsqb| unicode:: U+0005D .. RIGHT SQUARE BRACKETh]h]}hjksbah}(h]h ]h"]rsqbah$]h&]uh1hhhhKDhhhhubh)}(h<.. |rsquo| unicode:: U+02019 .. RIGHT SINGLE QUOTATION MARKh]h’}hjzsbah}(h]h ]h"]rsquoah$]h&]uh1hhhhKEhhhhubh)}(h-.. |sect| unicode:: U+000A7 .. SECTION SIGNh]h§}hjsbah}(h]h ]h"]sectah$]h&]uh1hhhhKFhhhhubh)}(h*.. |semi| unicode:: U+0003B .. SEMICOLONh]h;}hjsbah}(h]h ]h"]semiah$]h&]uh1hhhhKGhhhhubh)}(h,.. |shy| unicode:: U+000AD .. SOFT HYPHENh]h­}hjsbah}(h]h ]h"]shyah$]h&]uh1hhhhKHhhhhubh)}(h(.. |sol| unicode:: U+0002F .. SOLIDUSh]h/}hjsbah}(h]h ]h"]solah$]h&]uh1hhhhKIhhhhubh)}(h,.. |sung| unicode:: U+0266A .. EIGHTH NOTEh]h♪}hjsbah}(h]h ]h"]sungah$]h&]uh1hhhhKJhhhhubh)}(h0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONEh]h¹}hjsbah}(h]h ]h"]sup1ah$]h&]uh1hhhhKKhhhhubh)}(h0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWOh]h²}hjsbah}(h]h ]h"]sup2ah$]h&]uh1hhhhKLhhhhubh)}(h2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREEh]h³}hjsbah}(h]h ]h"]sup3ah$]h&]uh1hhhhKMhhhhubh)}(h4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGNh]h×}hjsbah}(h]h ]h"]timesah$]h&]uh1hhhhKNhhhhubh)}(h0.. |trade| unicode:: U+02122 .. TRADE MARK SIGNh]h™}hjsbah}(h]h ]h"]tradeah$]h&]uh1hhhhKOhhhhubh)}(h... |uarr| unicode:: U+02191 .. UPWARDS ARROWh]h↑}hjsbah}(h]h ]h"]uarrah$]h&]uh1hhhhKPhhhhubh)}(h... |verbar| unicode:: U+0007C .. VERTICAL LINEh]h|}hj.sbah}(h]h ]h"]verbarah$]h&]uh1hhhhKQhhhhubh)}(h*.. |yen| unicode:: U+000A5 .. YEN SIGN h]h¥}hj=sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(hLinux generic IRQ handlingh]hLinux generic IRQ handling}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjNhhhA/var/lib/git/docbuild/linux/Documentation/core-api/genericirq.rsthKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jlhjihjahKubh field_body)}(h!|copy| 2005-2010: Thomas Gleixnerh]h paragraph)}(hjh](h©}(hjhhhNhNubh 2005-2010: Thomas Gleixner}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahKhj~ubah}(h]h ]h"]h$]h&]uh1j|hjiubeh}(h]h ]h"]h$]h&]uh1jghjahKhjdhhubjh)}(hhh](jm)}(h Copyrighth]h Copyright}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jlhjhjahKubj})}(h|copy| 2005-2006: Ingo Molnar h]j)}(h|copy| 2005-2006: Ingo Molnarh](h©}(hjhhhNhNubh 2005-2006: Ingo Molnar}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1j|hjubeh}(h]h ]h"]h$]h&]uh1jghjahKhjdhhubeh}(h]h ]h"]h$]h&]uh1jbhjNhhhjahKubjM)}(hhh](jR)}(h Introductionh]h Introduction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahK ubj)}(hXThe generic interrupt handling layer is designed to provide a complete abstraction of interrupt handling for device drivers. It is able to handle all the different types of interrupt controller hardware. Device drivers use generic API functions to request, enable, disable and free interrupts. The drivers do not have to know anything about interrupt hardware details, so they can be used on different platforms without code changes.h]hXThe generic interrupt handling layer is designed to provide a complete abstraction of interrupt handling for device drivers. It is able to handle all the different types of interrupt controller hardware. Device drivers use generic API functions to request, enable, disable and free interrupts. The drivers do not have to know anything about interrupt hardware details, so they can be used on different platforms without code changes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK hjhhubj)}(hThis documentation is provided to developers who want to implement an interrupt subsystem based for their architecture, with the help of the generic IRQ handling layer.h]hThis documentation is provided to developers who want to implement an interrupt subsystem based for their architecture, with the help of the generic IRQ handling layer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1jLhjNhhhjahK ubjM)}(hhh](jR)}(h Rationaleh]h Rationale}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahKubj)}(hThe original implementation of interrupt handling in Linux uses the __do_IRQ() super-handler, which is able to deal with every type of interrupt logic.h]hThe original implementation of interrupt handling in Linux uses the __do_IRQ() super-handler, which is able to deal with every type of interrupt logic.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjhhubj)}(hOriginally, Russell King identified different types of handlers to build a quite universal set for the ARM interrupt handler implementation in Linux 2.5/2.6. He distinguished between:h]hOriginally, Russell King identified different types of handlers to build a quite universal set for the ARM interrupt handler implementation in Linux 2.5/2.6. He distinguished between:}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK hjhhubh bullet_list)}(hhh](h list_item)}(h Level type h]j)}(h Level typeh]h Level type}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK$hjCubah}(h]h ]h"]h$]h&]uh1jAhj>hhhjahNubjB)}(h Edge type h]j)}(h Edge typeh]h Edge type}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK&hj[ubah}(h]h ]h"]h$]h&]uh1jAhj>hhhjahNubjB)}(h Simple type h]j)}(h Simple typeh]h Simple type}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK(hjsubah}(h]h ]h"]h$]h&]uh1jAhj>hhhjahNubeh}(h]h ]h"]h$]h&]bullet-uh1j<hjahK$hjhhubj)}(h5During the implementation we identified another type:h]h5During the implementation we identified another type:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK*hjhhubj=)}(hhh]jB)}(hFast EOI type h]j)}(h Fast EOI typeh]h Fast EOI type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK,hjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubah}(h]h ]h"]h$]h&]jjuh1j<hjahK,hjhhubj)}(hMIn the SMP world of the __do_IRQ() super-handler another type was identified:h]hMIn the SMP world of the __do_IRQ() super-handler another type was identified:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK.hjhhubj=)}(hhh]jB)}(h Per CPU type h]j)}(h Per CPU typeh]h Per CPU type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK1hjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubah}(h]h ]h"]h$]h&]jjuh1j<hjahK1hjhhubj)}(hThis split implementation of high-level IRQ handlers allows us to optimize the flow of the interrupt handling for each specific interrupt type. This reduces complexity in that particular code path and allows the optimized handling of a given type.h]hThis split implementation of high-level IRQ handlers allows us to optimize the flow of the interrupt handling for each specific interrupt type. This reduces complexity in that particular code path and allows the optimized handling of a given type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK3hjhhubj)}(hXThe original general IRQ implementation used hw_interrupt_type structures and their ``->ack``, ``->end`` [etc.] callbacks to differentiate the flow control in the super-handler. This leads to a mix of flow logic and low-level hardware logic, and it also leads to unnecessary code duplication: for example in i386, there is an ``ioapic_level_irq`` and an ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but have different flow handling.h](hTThe original general IRQ implementation used hw_interrupt_type structures and their }(hjhhhNhNubhliteral)}(h ``->ack``h]h->ack}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(hjhhhNhNubj)}(h ``->end``h]h->end}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh [etc.] callbacks to differentiate the flow control in the super-handler. This leads to a mix of flow logic and low-level hardware logic, and it also leads to unnecessary code duplication: for example in i386, there is an }(hjhhhNhNubj)}(h``ioapic_level_irq``h]hioapic_level_irq}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and an }(hjhhhNhNubj)}(h``ioapic_edge_irq``h]hioapic_edge_irq}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhU IRQ-type which share many of the low-level details but have different flow handling.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahK8hjhhubj)}(h\A more natural abstraction is the clean separation of the 'irq flow' and the 'chip details'.h]hdA more natural abstraction is the clean separation of the ‘irq flow’ and the ‘chip details’.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK@hjhhubj)}(hX}Analysing a couple of architecture's IRQ subsystem implementations reveals that most of them can use a generic set of 'irq flow' methods and only need to add the chip-level specific code. The separation is also valuable for (sub)architectures which need specific quirks in the IRQ flow itself but not in the chip details - and thus provides a more transparent IRQ subsystem design.h]hXAnalysing a couple of architecture’s IRQ subsystem implementations reveals that most of them can use a generic set of ‘irq flow’ methods and only need to add the chip-level specific code. The separation is also valuable for (sub)architectures which need specific quirks in the IRQ flow itself but not in the chip details - and thus provides a more transparent IRQ subsystem design.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKChjhhubj)}(hX%Each interrupt descriptor is assigned its own high-level flow handler, which is normally one of the generic implementations. (This high-level flow handler implementation also makes it simple to provide demultiplexing handlers which can be found in embedded platforms on various architectures.)h]hX%Each interrupt descriptor is assigned its own high-level flow handler, which is normally one of the generic implementations. (This high-level flow handler implementation also makes it simple to provide demultiplexing handlers which can be found in embedded platforms on various architectures.)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKJhjhhubj)}(hXThe separation makes the generic interrupt handling layer more flexible and extensible. For example, an (sub)architecture can use a generic IRQ-flow implementation for 'level type' interrupts and add a (sub)architecture specific 'edge type' implementation.h]hXThe separation makes the generic interrupt handling layer more flexible and extensible. For example, an (sub)architecture can use a generic IRQ-flow implementation for ‘level type’ interrupts and add a (sub)architecture specific ‘edge type’ implementation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKPhjhhubj)}(hXTo make the transition to the new model easier and prevent the breakage of existing implementations, the __do_IRQ() super-handler is still available. This leads to a kind of duality for the time being. Over time the new model should be used in more and more architectures, as it enables smaller and cleaner IRQ subsystems. It's deprecated for three years now and about to be removed.h]hXTo make the transition to the new model easier and prevent the breakage of existing implementations, the __do_IRQ() super-handler is still available. This leads to a kind of duality for the time being. Over time the new model should be used in more and more architectures, as it enables smaller and cleaner IRQ subsystems. It’s deprecated for three years now and about to be removed.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKUhjhhubeh}(h] rationaleah ]h"] rationaleah$]h&]uh1jLhjNhhhjahKubjM)}(hhh](jR)}(hKnown Bugs And Assumptionsh]hKnown Bugs And Assumptions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahK]ubj)}(hNone (knock on wood).h]hNone (knock on wood).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK_hjhhubeh}(h]known-bugs-and-assumptionsah ]h"]known bugs and assumptionsah$]h&]uh1jLhjNhhhjahK]ubjM)}(hhh](jR)}(hAbstraction layersh]hAbstraction layers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahKbubj)}(hAThere are three main levels of abstraction in the interrupt code:h]hAThere are three main levels of abstraction in the interrupt code:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKdhjhhubhenumerated_list)}(hhh](jB)}(hHigh-level driver API h]j)}(hHigh-level driver APIh]hHigh-level driver API}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKfhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hHigh-level IRQ flow handlers h]j)}(hHigh-level IRQ flow handlersh]hHigh-level IRQ flow handlers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(h"Chip-level hardware encapsulation h]j)}(h!Chip-level hardware encapsulationh]h!Chip-level hardware encapsulation}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKjhj ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjhhhjahKfubjM)}(hhh](jR)}(hInterrupt control flowh]hInterrupt control flow}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjChhhjahKmubj)}(hXEach interrupt is described by an interrupt descriptor structure irq_desc. The interrupt is referenced by an 'unsigned int' numeric value which selects the corresponding interrupt description structure in the descriptor structures array. The descriptor structure contains status information and pointers to the interrupt flow method and the interrupt chip structure which are assigned to this interrupt.h]hXEach interrupt is described by an interrupt descriptor structure irq_desc. The interrupt is referenced by an ‘unsigned int’ numeric value which selects the corresponding interrupt description structure in the descriptor structures array. The descriptor structure contains status information and pointers to the interrupt flow method and the interrupt chip structure which are assigned to this interrupt.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKohjChhubj)}(hX Whenever an interrupt triggers, the low-level architecture code calls into the generic interrupt code by calling desc->handle_irq(). This high-level IRQ handling function only uses desc->irq_data.chip primitives referenced by the assigned chip descriptor structure.h]hX Whenever an interrupt triggers, the low-level architecture code calls into the generic interrupt code by calling desc->handle_irq(). This high-level IRQ handling function only uses desc->irq_data.chip primitives referenced by the assigned chip descriptor structure.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKvhjChhubeh}(h]interrupt-control-flowah ]h"]interrupt control flowah$]h&]uh1jLhjhhhjahKmubjM)}(hhh](jR)}(hHigh-level Driver APIh]hHigh-level Driver API}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjxhhhjahK|ubj)}(h:The high-level Driver API consists of following functions:h]h:The high-level Driver API consists of following functions:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahK~hjxhhubj=)}(hhh](jB)}(hrequest_irq() h]j)}(h request_irq()h]h request_irq()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hrequest_threaded_irq() h]j)}(hrequest_threaded_irq()h]hrequest_threaded_irq()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(h free_irq() h]j)}(h free_irq()h]h free_irq()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hdisable_irq() h]j)}(h disable_irq()h]h disable_irq()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(h enable_irq() h]j)}(h enable_irq()h]h enable_irq()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(h disable_irq_nosync() (SMP only) h]j)}(hdisable_irq_nosync() (SMP only)h]hdisable_irq_nosync() (SMP only)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hsynchronize_irq() (SMP only) h]j)}(hsynchronize_irq() (SMP only)h]hsynchronize_irq() (SMP only)}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj* ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hirq_set_irq_type() h]j)}(hirq_set_irq_type()h]hirq_set_irq_type()}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjB ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hirq_set_irq_wake() h]j)}(hirq_set_irq_wake()h]hirq_set_irq_wake()}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjZ ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hirq_set_handler_data() h]j)}(hirq_set_handler_data()h]hirq_set_handler_data()}(hjv hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjr ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hirq_set_chip() h]j)}(hirq_set_chip()h]hirq_set_chip()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hirq_set_chip_data() h]j)}(hirq_set_chip_data()h]hirq_set_chip_data()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubeh}(h]h ]h"]h$]h&]jjuh1j<hjahKhjxhhubj)}(h9See the autogenerated function documentation for details.h]h9See the autogenerated function documentation for details.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjxhhubeh}(h]high-level-driver-apiah ]h"]high-level driver apiah$]h&]uh1jLhjhhhjahK|ubjM)}(hhh](jR)}(hHigh-level IRQ flow handlersh]hHigh-level IRQ flow handlers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubj)}(hAThe generic layer provides a set of pre-defined irq-flow methods:h]hAThe generic layer provides a set of pre-defined irq-flow methods:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubj=)}(hhh](jB)}(hhandle_level_irq() h]j)}(hhandle_level_irq()h]hhandle_level_irq()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_edge_irq() h]j)}(hhandle_edge_irq()h]hhandle_edge_irq()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_fasteoi_irq() h]j)}(hhandle_fasteoi_irq()h]hhandle_fasteoi_irq()}(hj, hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj( ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_simple_irq() h]j)}(hhandle_simple_irq()h]hhandle_simple_irq()}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj@ ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_percpu_irq() h]j)}(hhandle_percpu_irq()h]hhandle_percpu_irq()}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjX ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_edge_eoi_irq() h]j)}(hhandle_edge_eoi_irq()h]hhandle_edge_eoi_irq()}(hjt hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjp ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubjB)}(hhandle_bad_irq() h]j)}(hhandle_bad_irq()h]hhandle_bad_irq()}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj ubah}(h]h ]h"]h$]h&]uh1jAhj hhhjahNubeh}(h]h ]h"]h$]h&]jjuh1j<hjahKhj hhubj)}(hThe interrupt flow handlers (either pre-defined or architecture specific) are assigned to specific interrupts by the architecture either during bootup or during device initialization.h]hThe interrupt flow handlers (either pre-defined or architecture specific) are assigned to specific interrupts by the architecture either during bootup or during device initialization.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubjM)}(hhh](jR)}(hDefault flow implementationsh]hDefault flow implementations}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubjM)}(hhh](jR)}(hHelper functionsh]hHelper functions}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubj)}(hThe helper functions call the chip primitives and are used by the default flow implementations. The following helper functions are implemented (simplified excerpt)::h]hThe helper functions call the chip primitives and are used by the default flow implementations. The following helper functions are implemented (simplified excerpt):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubh literal_block)}(hXdefault_enable(struct irq_data *data) { desc->irq_data.chip->irq_unmask(data); } default_disable(struct irq_data *data) { if (!delay_disable(data)) desc->irq_data.chip->irq_mask(data); } default_ack(struct irq_data *data) { chip->irq_ack(data); } default_mask_ack(struct irq_data *data) { if (chip->irq_mask_ack) { chip->irq_mask_ack(data); } else { chip->irq_mask(data); chip->irq_ack(data); } } noop(struct irq_data *data) { }h]hXdefault_enable(struct irq_data *data) { desc->irq_data.chip->irq_unmask(data); } default_disable(struct irq_data *data) { if (!delay_disable(data)) desc->irq_data.chip->irq_mask(data); } default_ack(struct irq_data *data) { chip->irq_ack(data); } default_mask_ack(struct irq_data *data) { if (chip->irq_mask_ack) { chip->irq_mask_ack(data); } else { chip->irq_mask(data); chip->irq_ack(data); } } noop(struct irq_data *data) { }}hj sbah}(h]h ]h"]h$]h&]hhuh1j hjahKhj hhubeh}(h]helper-functionsah ]h"]helper functionsah$]h&]uh1jLhj hhhjahKubeh}(h]default-flow-implementationsah ]h"]default flow implementationsah$]h&]uh1jLhj hhhjahKubjM)}(hhh](jR)}(h$Default flow handler implementationsh]h$Default flow handler implementations}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubjM)}(hhh](jR)}(hDefault Level IRQ flow handlerh]hDefault Level IRQ flow handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubj)}(hRhandle_level_irq provides a generic implementation for level-triggered interrupts.h]hRhandle_level_irq provides a generic implementation for level-triggered interrupts.}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubj)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubj )}(hgdesc->irq_data.chip->irq_mask_ack(); handle_irq_event(desc->action); desc->irq_data.chip->irq_unmask();h]hgdesc->irq_data.chip->irq_mask_ack(); handle_irq_event(desc->action); desc->irq_data.chip->irq_unmask();}hjB sbah}(h]h ]h"]h$]h&]hhuh1j hjahKhj hhubeh}(h]default-level-irq-flow-handlerah ]h"]default level irq flow handlerah$]h&]uh1jLhj hhhjahKubjM)}(hhh](jR)}(h!Default Fast EOI IRQ flow handlerh]h!Default Fast EOI IRQ flow handler}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjX hhhjahKubj)}(hvhandle_fasteoi_irq provides a generic implementation for interrupts, which only need an EOI at the end of the handler.h]hvhandle_fasteoi_irq provides a generic implementation for interrupts, which only need an EOI at the end of the handler.}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjX hhubj)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjX hhubj )}(h?handle_irq_event(desc->action); desc->irq_data.chip->irq_eoi();h]h?handle_irq_event(desc->action); desc->irq_data.chip->irq_eoi();}hj sbah}(h]h ]h"]h$]h&]hhuh1j hjahKhjX hhubeh}(h]!default-fast-eoi-irq-flow-handlerah ]h"]!default fast eoi irq flow handlerah$]h&]uh1jLhj hhhjahKubjM)}(hhh](jR)}(hDefault Edge IRQ flow handlerh]hDefault Edge IRQ flow handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahKubj)}(hPhandle_edge_irq provides a generic implementation for edge-triggered interrupts.h]hPhandle_edge_irq provides a generic implementation for edge-triggered interrupts.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubj)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhj hhubj )}(hXif (desc->status & running) { desc->irq_data.chip->irq_mask_ack(); desc->status |= pending | masked; return; } desc->irq_data.chip->irq_ack(); desc->status |= running; do { if (desc->status & masked) desc->irq_data.chip->irq_unmask(); desc->status &= ~pending; handle_irq_event(desc->action); } while (desc->status & pending); desc->status &= ~running;h]hXif (desc->status & running) { desc->irq_data.chip->irq_mask_ack(); desc->status |= pending | masked; return; } desc->irq_data.chip->irq_ack(); desc->status |= running; do { if (desc->status & masked) desc->irq_data.chip->irq_unmask(); desc->status &= ~pending; handle_irq_event(desc->action); } while (desc->status & pending); desc->status &= ~running;}hj sbah}(h]h ]h"]h$]h&]hhuh1j hjahKhj hhubeh}(h]default-edge-irq-flow-handlerah ]h"]default edge irq flow handlerah$]h&]uh1jLhj hhhjahKubjM)}(hhh](jR)}(hDefault simple IRQ flow handlerh]hDefault simple IRQ flow handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahMubj)}(hJhandle_simple_irq provides a generic implementation for simple interrupts.h]hJhandle_simple_irq provides a generic implementation for simple interrupts.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj hhubhnote)}(hBThe simple flow handler does not call any handler/chip primitives.h]j)}(hj h]hBThe simple flow handler does not call any handler/chip primitives.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj ubah}(h]h ]h"]h$]h&]uh1j hj hhhjahNubj)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj hhubj )}(hhandle_irq_event(desc->action);h]hhandle_irq_event(desc->action);}hj$ sbah}(h]h ]h"]h$]h&]hhuh1j hjahMhj hhubeh}(h]default-simple-irq-flow-handlerah ]h"]default simple irq flow handlerah$]h&]uh1jLhj hhhjahMubjM)}(hhh](jR)}(hDefault per CPU flow handlerh]hDefault per CPU flow handler}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj: hhhjahMubj)}(hKhandle_percpu_irq provides a generic implementation for per CPU interrupts.h]hKhandle_percpu_irq provides a generic implementation for per CPU interrupts.}(hjK hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM!hj: hhubj)}(hkPer CPU interrupts are only available on SMP and the handler provides a simplified version without locking.h]hkPer CPU interrupts are only available on SMP and the handler provides a simplified version without locking.}(hjY hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM$hj: hhubj)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM'hj: hhubj )}(hif (desc->irq_data.chip->irq_ack) desc->irq_data.chip->irq_ack(); handle_irq_event(desc->action); if (desc->irq_data.chip->irq_eoi) desc->irq_data.chip->irq_eoi();h]hif (desc->irq_data.chip->irq_ack) desc->irq_data.chip->irq_ack(); handle_irq_event(desc->action); if (desc->irq_data.chip->irq_eoi) desc->irq_data.chip->irq_eoi();}hju sbah}(h]h ]h"]h$]h&]hhuh1j hjahM)hj: hhubeh}(h]default-per-cpu-flow-handlerah ]h"]default per cpu flow handlerah$]h&]uh1jLhj hhhjahMubjM)}(hhh](jR)}(hEOI Edge IRQ flow handlerh]hEOI Edge IRQ flow handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahM1ubj)}(hhandle_edge_eoi_irq provides an abnomination of the edge handler which is solely used to tame a badly wreckaged irq controller on powerpc/cell.h]hhandle_edge_eoi_irq provides an abnomination of the edge handler which is solely used to tame a badly wreckaged irq controller on powerpc/cell.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM3hj hhubeh}(h]eoi-edge-irq-flow-handlerah ]h"]eoi edge irq flow handlerah$]h&]uh1jLhj hhhjahM1ubjM)}(hhh](jR)}(hBad IRQ flow handlerh]hBad IRQ flow handler}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahM8ubj)}(hThandle_bad_irq is used for spurious interrupts which have no real handler assigned..h]hThandle_bad_irq is used for spurious interrupts which have no real handler assigned..}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM:hj hhubeh}(h]bad-irq-flow-handlerah ]h"]bad irq flow handlerah$]h&]uh1jLhj hhhjahM8ubeh}(h]$default-flow-handler-implementationsah ]h"]$default flow handler implementationsah$]h&]uh1jLhj hhhjahKubjM)}(hhh](jR)}(hQuirks and optimizationsh]hQuirks and optimizations}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahM>ubj)}(hThe generic functions are intended for 'clean' architectures and chips, which have no platform-specific IRQ handling quirks. If an architecture needs to implement quirks on the 'flow' level then it can do so by overriding the high-level irq-flow handler.h]hXThe generic functions are intended for ‘clean’ architectures and chips, which have no platform-specific IRQ handling quirks. If an architecture needs to implement quirks on the ‘flow’ level then it can do so by overriding the high-level irq-flow handler.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahM@hj hhubeh}(h]quirks-and-optimizationsah ]h"]quirks and optimizationsah$]h&]uh1jLhj hhhjahM>ubjM)}(hhh](jR)}(hDelayed interrupt disableh]hDelayed interrupt disable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj hhhjahMFubj)}(hXThis per interrupt selectable feature, which was introduced by Russell King in the ARM interrupt implementation, does not mask an interrupt at the hardware level when disable_irq() is called. The interrupt is kept enabled and is masked in the flow handler when an interrupt event happens. This prevents losing edge interrupts on hardware which does not store an edge interrupt event while the interrupt is disabled at the hardware level. When an interrupt arrives while the IRQ_DISABLED flag is set, then the interrupt is masked at the hardware level and the IRQ_PENDING bit is set. When the interrupt is re-enabled by enable_irq() the pending bit is checked and if it is set, the interrupt is resent either via hardware or by a software resend mechanism. (It's necessary to enable CONFIG_HARDIRQS_SW_RESEND when you want to use the delayed interrupt disable feature and your hardware is not capable of retriggering an interrupt.) The delayed interrupt disable is not configurable.h]hXThis per interrupt selectable feature, which was introduced by Russell King in the ARM interrupt implementation, does not mask an interrupt at the hardware level when disable_irq() is called. The interrupt is kept enabled and is masked in the flow handler when an interrupt event happens. This prevents losing edge interrupts on hardware which does not store an edge interrupt event while the interrupt is disabled at the hardware level. When an interrupt arrives while the IRQ_DISABLED flag is set, then the interrupt is masked at the hardware level and the IRQ_PENDING bit is set. When the interrupt is re-enabled by enable_irq() the pending bit is checked and if it is set, the interrupt is resent either via hardware or by a software resend mechanism. (It’s necessary to enable CONFIG_HARDIRQS_SW_RESEND when you want to use the delayed interrupt disable feature and your hardware is not capable of retriggering an interrupt.) The delayed interrupt disable is not configurable.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMHhj hhubeh}(h]delayed-interrupt-disableah ]h"]delayed interrupt disableah$]h&]uh1jLhj hhhjahMFubeh}(h]high-level-irq-flow-handlersah ]h"]high-level irq flow handlersah$]h&]uh1jLhjhhhjahKubjM)}(hhh](jR)}(h!Chip-level hardware encapsulationh]h!Chip-level hardware encapsulation}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj7 hhhjahMYubj)}(hThe chip-level hardware descriptor structure :c:type:`irq_chip` contains all the direct chip relevant functions, which can be utilized by the irq flow implementations.h](h-The chip-level hardware descriptor structure }(hjH hhhNhNubh)}(h:c:type:`irq_chip`h]j)}(hjR h]hirq_chip}(hjT hhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jhjP ubah}(h]h ]h"]h$]h&]refdoccore-api/genericirq refdomainj_ reftypetype refexplicitrefwarn reftargetirq_chipuh1hhjahM[hjH ubhh contains all the direct chip relevant functions, which can be utilized by the irq flow implementations.}(hjH hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahM[hj7 hhubj=)}(hhh](jB)}(h ``irq_ack`` h]j)}(h ``irq_ack``h]j)}(hj h]hirq_ack}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjahM_hj ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h9``irq_mask_ack`` - Optional, recommended for performance h]j)}(h8``irq_mask_ack`` - Optional, recommended for performanceh](j)}(h``irq_mask_ack``h]h irq_mask_ack}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh( - Optional, recommended for performance}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahMahj ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h ``irq_mask`` h]j)}(h ``irq_mask``h]j)}(hj h]hirq_mask}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjahMchj ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h``irq_unmask`` h]j)}(h``irq_unmask``h]j)}(hj h]h irq_unmask}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjahMehj ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h7``irq_eoi`` - Optional, required for EOI flow handlers h]j)}(h6``irq_eoi`` - Optional, required for EOI flow handlersh](j)}(h ``irq_eoi``h]hirq_eoi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh+ - Optional, required for EOI flow handlers}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahMghj ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h``irq_retrigger`` - Optional h]j)}(h``irq_retrigger`` - Optionalh](j)}(h``irq_retrigger``h]h irq_retrigger}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh - Optional}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahMihj/ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h``irq_set_type`` - Optional h]j)}(h``irq_set_type`` - Optionalh](j)}(h``irq_set_type``h]h irq_set_type}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh - Optional}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahMkhjUubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubjB)}(h``irq_set_wake`` - Optional h]j)}(h``irq_set_wake`` - Optionalh](j)}(h``irq_set_wake``h]h irq_set_wake}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh - Optional}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjahMmhj{ubah}(h]h ]h"]h$]h&]uh1jAhj} hhhjahNubeh}(h]h ]h"]h$]h&]jjuh1j<hjahM_hj7 hhubj)}(hThese primitives are strictly intended to mean what they say: ack means ACK, masking means masking of an IRQ line, etc. It is up to the flow handler(s) to use these basic units of low-level functionality.h]hThese primitives are strictly intended to mean what they say: ack means ACK, masking means masking of an IRQ line, etc. It is up to the flow handler(s) to use these basic units of low-level functionality.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMohj7 hhubeh}(h]!chip-level-hardware-encapsulationah ]h"]!chip-level hardware encapsulationah$]h&]uh1jLhjhhhjahMYubeh}(h]abstraction-layersah ]h"]abstraction layersah$]h&]uh1jLhjNhhhjahKbubjM)}(hhh](jR)}(h__do_IRQ entry pointh]h__do_IRQ entry point}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahMtubj)}(hwThe original implementation __do_IRQ() was an alternative entry point for all types of interrupts. It no longer exists.h]hwThe original implementation __do_IRQ() was an alternative entry point for all types of interrupts. It no longer exists.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMvhjhhubj)}(hThis handler turned out to be not suitable for all interrupt hardware and was therefore reimplemented with split functionality for edge/level/simple/percpu interrupts. This is not only a functional optimization. It also shortens code paths for interrupts.h]hThis handler turned out to be not suitable for all interrupt hardware and was therefore reimplemented with split functionality for edge/level/simple/percpu interrupts. This is not only a functional optimization. It also shortens code paths for interrupts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMyhjhhubeh}(h]do-irq-entry-pointah ]h"]__do_irq entry pointah$]h&]uh1jLhjNhhhjahMtubjM)}(hhh](jR)}(hLocking on SMPh]hLocking on SMP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahMubj)}(hThe locking of chip registers is up to the architecture that defines the chip primitives. The per-irq structure is protected via desc->lock, by the generic layer.h]hThe locking of chip registers is up to the architecture that defines the chip primitives. The per-irq structure is protected via desc->lock, by the generic layer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhjhhubeh}(h]locking-on-smpah ]h"]locking on smpah$]h&]uh1jLhjNhhhjahMubjM)}(hhh](jR)}(hGeneric interrupt chiph]hGeneric interrupt chip}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj!hhhjahMubj)}(hXTo avoid copies of identical implementations of IRQ chips the core provides a configurable generic interrupt chip implementation. Developers should check carefully whether the generic chip fits their needs before implementing the same functionality slightly differently themselves.h]hXTo avoid copies of identical implementations of IRQ chips the core provides a configurable generic interrupt chip implementation. Developers should check carefully whether the generic chip fits their needs before implementing the same functionality slightly differently themselves.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj!hhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleirq_gc_noop (C function) c.irq_gc_noophNtauh1j@hj!hhhNhNubhdesc)}(hhh](hdesc_signature)}(h%void irq_gc_noop (struct irq_data *d)h]hdesc_signature_line)}(h$void irq_gc_noop(struct irq_data *d)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjdhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jbhj^hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKubhdesc_sig_space)}(h h]h }(hjvhhhNhNubah}(h]h ]wah"]h$]h&]uh1jthj^hhhjshKubh desc_name)}(h irq_gc_nooph]h desc_sig_name)}(h irq_gc_nooph]h irq_gc_noop}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhj^hhhjshKubhdesc_parameterlist)}(h(struct irq_data *d)h]hdesc_parameter)}(hstruct irq_data *dh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjsb c.irq_gc_noopasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubhdesc_sig_punctuation)}(h*h]h*}(hj hhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubj)}(hdh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj^hhhjshKubeh}(h]h ]h"]h$]h&]hhƌ add_permalinkuh1j\sphinx_line_type declaratorhjXhhhjshKubah}(h]jOah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jVhjshKhjShhubh desc_content)}(hhh]j)}(h NOOP functionh]h NOOP function}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjJhhubah}(h]h ]h"]h$]h&]uh1jHhjShhhjshKubeh}(h]h ](j_ functioneh"]h$]h&]domainj_ objtypejedesctypejenoindex noindexentrynocontentsentryuh1jQhhhj!hNhNubh container)}(h1**Parameters** ``struct irq_data *d`` irq_datah](j)}(h**Parameters**h]hstrong)}(hjwh]h Parameters}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjuubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjqubhdefinition_list)}(hhh]hdefinition_list_item)}(h``struct irq_data *d`` irq_datah](hterm)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubh definition)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_gc_mask_disable_reg (C function)c.irq_gc_mask_disable_reghNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h1void irq_gc_mask_disable_reg (struct irq_data *d)h]j])}(h0void irq_gc_mask_disable_reg(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubj)}(hirq_gc_mask_disable_regh]j)}(hirq_gc_mask_disable_regh]hirq_gc_mask_disable_reg}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubju)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjWmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_mask_disable_regasbuh1hhj3ubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj/ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKhjhhubjI)}(hhh]j)}(hMask chip via disable registerh]hMask chip via disable register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has separate enable/disable registers instead of a single mask register.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK#hjubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK hjubj)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj5h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK"hjubj)}(hMChip has separate enable/disable registers instead of a single mask register.h]hMChip has separate enable/disable registers instead of a single mask register.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK!hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM irq_gc_mask_set_bit (C function)c.irq_gc_mask_set_bithNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h-void irq_gc_mask_set_bit (struct irq_data *d)h]j])}(h,void irq_gc_mask_set_bit(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjzhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.c hK2ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvhhhjhK2ubj)}(hirq_gc_mask_set_bith]j)}(hirq_gc_mask_set_bith]hirq_gc_mask_set_bit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjvhhhjhK2ubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_mask_set_bitasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjvhhhjhK2ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjrhhhjhK2ubah}(h]jmah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhK2hjohhubjI)}(hhh]j)}(h*Mask chip via setting bit in mask registerh]h*Mask chip via setting bit in mask register}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK2hj6hhubah}(h]h ]h"]h$]h&]uh1jHhjohhhjhK2ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjQjkjQjljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has a single mask register. Values of this register are cached and protected by gc->lockh](j)}(h**Parameters**h]jz)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK6hjUubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjzh]hstruct irq_data *d}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK3hjtubj)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhK3hjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhK3hjqubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK5hjUubj)}(h]Chip has a single mask register. Values of this register are cached and protected by gc->lockh]h]Chip has a single mask register. Values of this register are cached and protected by gc->lock}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK4hjUubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM irq_gc_mask_clr_bit (C function)c.irq_gc_mask_clr_bithNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h-void irq_gc_mask_clr_bit (struct irq_data *d)h]j])}(h,void irq_gc_mask_clr_bit(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKEubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKEubj)}(hirq_gc_mask_clr_bith]j)}(hirq_gc_mask_clr_bith]hirq_gc_mask_clr_bit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKEubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubju)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjWmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_mask_clr_bitasbuh1hhj3ubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj/ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKEubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKEubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKEhjhhubjI)}(hhh]j)}(h+Mask chip via clearing bit in mask registerh]h+Mask chip via clearing bit in mask register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKEhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKEubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has a single mask register. Values of this register are cached and protected by gc->lockh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKIhjubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKFhjubj)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKFhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKFhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj5h]h Description}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKHhjubj)}(h]Chip has a single mask register. Values of this register are cached and protected by gc->lockh]h]Chip has a single mask register. Values of this register are cached and protected by gc->lock}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKGhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_gc_unmask_enable_reg (C function)c.irq_gc_unmask_enable_reghNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h2void irq_gc_unmask_enable_reg (struct irq_data *d)h]j])}(h1void irq_gc_unmask_enable_reg(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjzhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKXubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvhhhjhKXubj)}(hirq_gc_unmask_enable_regh]j)}(hirq_gc_unmask_enable_regh]hirq_gc_unmask_enable_reg}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjvhhhjhKXubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_unmask_enable_regasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjvhhhjhKXubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjrhhhjhKXubah}(h]jmah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKXhjohhubjI)}(hhh]j)}(hUnmask chip via enable registerh]hUnmask chip via enable register}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKXhj6hhubah}(h]h ]h"]h$]h&]uh1jHhjohhhjhKXubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjQjkjQjljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has separate enable/disable registers instead of a single mask register.h](j)}(h**Parameters**h]jz)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjYubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK\hjUubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjzh]hstruct irq_data *d}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKYhjtubj)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKYhjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhKYhjqubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chK[hjUubj)}(hMChip has separate enable/disable registers instead of a single mask register.h]hMChip has separate enable/disable registers instead of a single mask register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKZhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_gc_ack_set_bit (C function)c.irq_gc_ack_set_bithNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h,void irq_gc_ack_set_bit (struct irq_data *d)h]j])}(h+void irq_gc_ack_set_bit(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKkubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKkubj)}(hirq_gc_ack_set_bith]j)}(hirq_gc_ack_set_bith]hirq_gc_ack_set_bit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKkubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubju)}(h h]h }(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjWmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_ack_set_bitasbuh1hhj3ubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj/ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKkubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKkubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKkhjhhubjI)}(hhh]j)}(h%Ack pending interrupt via setting bith]h%Ack pending interrupt via setting bit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKkhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKkubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj!hNhNubjp)}(h1**Parameters** ``struct irq_data *d`` irq_datah](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKohjubj)}(hhh]j)}(h``struct irq_data *d`` irq_datah](j)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKqhjubj)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKqhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM,irq_gc_mask_disable_and_ack_set (C function)!c.irq_gc_mask_disable_and_ack_sethNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h9void irq_gc_mask_disable_and_ack_set (struct irq_data *d)h]j])}(h8void irq_gc_mask_disable_and_ack_set(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hjThhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjPhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPhhhjbhKubj)}(hirq_gc_mask_disable_and_ack_seth]j)}(hirq_gc_mask_disable_and_ack_seth]hirq_gc_mask_disable_and_ack_set}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ](jjeh"]h$]h&]hhuh1jhjPhhhjbhKubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjwsb!c.irq_gc_mask_disable_and_ack_setasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjPhhhjbhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjLhhhjbhKubah}(h]jGah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjbhKhjIhhubjI)}(hhh]j)}(hMask and ack pending interrupth]hMask and ack pending interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjhhubah}(h]h ]h"]h$]h&]uh1jHhjIhhhjbhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj+jkj+jljmjnuh1jQhhhj!hNhNubjp)}(hX**Parameters** ``struct irq_data *d`` irq_data **Description** This generic implementation of the irq_mask_ack method is for chips with separate enable/disable registers instead of a single mask register and where a pending interrupt is acknowledged by setting a bit. **Note** This is the only permutation currently used. Similar generic functions should be added here if other permutations are required.h](j)}(h**Parameters**h]jz)}(hj5h]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjTh]hstruct irq_data *d}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjNubj)}(hhh]j)}(hirq_datah]hirq_data}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjihKhjjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjihKhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubj)}(hThis generic implementation of the irq_mask_ack method is for chips with separate enable/disable registers instead of a single mask register and where a pending interrupt is acknowledged by setting a bit.h]hThis generic implementation of the irq_mask_ack method is for chips with separate enable/disable registers instead of a single mask register and where a pending interrupt is acknowledged by setting a bit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubj)}(h**Note**h]jz)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubj)}(hThis is the only permutation currently used. Similar generic functions should be added here if other permutations are required.h]hThis is the only permutation currently used. Similar generic functions should be added here if other permutations are required.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_gc_set_wake (C function)c.irq_gc_set_wakehNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h9int irq_gc_set_wake (struct irq_data *d, unsigned int on)h]j])}(h8int irq_gc_set_wake(struct irq_data *d, unsigned int on)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj hKubj)}(hirq_gc_set_wakeh]j)}(hirq_gc_set_wakeh]hirq_gc_set_wake}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj hKubj)}(h%(struct irq_data *d, unsigned int on)h](j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubju)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj4ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjXmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_set_wakeasbuh1hhj4ubju)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj4ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubj)}(hjh]hd}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0ubj)}(hunsigned int onh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(honh]hon}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj hKubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj hKhjhhubjI)}(hhh]j)}(h!Set/clr wake bit for an interrupth]h!Set/clr wake bit for an interrupt}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj hKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj#jkj#jljmjnuh1jQhhhj!hNhNubjp)}(hX(**Parameters** ``struct irq_data *d`` irq_data ``unsigned int on`` Indicates whether the wake bit should be set or cleared **Description** For chips where the wake from suspend functionality is not configured in a separate register and the wakeup active state is just stored in a bitmask.h](j)}(h**Parameters**h]jz)}(hj-h]h Parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj+ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj'ubj)}(hhh](j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjLh]hstruct irq_data *d}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjFubj)}(hhh]j)}(hirq_datah]hirq_data}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahKhjbubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jhjahKhjCubj)}(hL``unsigned int on`` Indicates whether the wake bit should be set or cleared h](j)}(h``unsigned int on``h]j)}(hjh]hunsigned int on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubj)}(hhh]j)}(h7Indicates whether the wake bit should be set or clearedh]h7Indicates whether the wake bit should be set or cleared}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjCubeh}(h]h ]h"]h$]h&]uh1jhj'ubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj'ubj)}(hFor chips where the wake from suspend functionality is not configured in a separate register and the wakeup active state is just stored in a bitmask.h]hFor chips where the wake from suspend functionality is not configured in a separate register and the wakeup active state is just stored in a bitmask.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#irq_alloc_generic_chip (C function)c.irq_alloc_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hstruct irq_chip_generic * irq_alloc_generic_chip (const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h]j])}(hstruct irq_chip_generic *irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj&modnameN classnameNjj)}j]j)}jirq_alloc_generic_chipsbc.irq_alloc_generic_chipasbuh1hhjhhhjhKubju)}(h h]h }(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubj )}(hj h]h*}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhhhjhKubj)}(hirq_alloc_generic_chiph]j)}(hjBh]hirq_alloc_generic_chip}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubj)}(hi(const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h](j)}(hconst char *nameh](j)}(hconsth]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj{ubjc)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj{ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj{ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubj)}(hnameh]hname}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(h int num_cth](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hnum_cth]hnum_ct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(hunsigned int irq_baseh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj.hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirq_baseh]hirq_base}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(hvoid __iomem *reg_baseh](jc)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_ubju)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubh__iomem}(hj_hhhNhNubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(hreg_baseh]hreg_base}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubj)}(hirq_flow_handler_t handlerh](h)}(hhh]j)}(hirq_flow_handler_th]hirq_flow_handler_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j@c.irq_alloc_generic_chipasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjwubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKhjhhubjI)}(hhh]j)}(h)Allocate a generic chip and initialize ith]h)Allocate a generic chip and initialize it}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj(jkj(jljmjnuh1jQhhhj!hNhNubjp)}(hX**Parameters** ``const char *name`` Name of the irq chip ``int num_ct`` Number of irq_chip_type instances associated with this ``unsigned int irq_base`` Interrupt base nr for this chip ``void __iomem *reg_base`` Register base address (virtual) ``irq_flow_handler_t handler`` Default flow handler associated with this chip **Description** Returns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and **handler**h](j)}(h**Parameters**h]jz)}(hj2h]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj0ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj,ubj)}(hhh](j)}(h*``const char *name`` Name of the irq chip h](j)}(h``const char *name``h]j)}(hjQh]hconst char *name}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjKubj)}(hhh]j)}(hName of the irq chiph]hName of the irq chip}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfhKhjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjfhKhjHubj)}(hF``int num_ct`` Number of irq_chip_type instances associated with this h](j)}(h``int num_ct``h]j)}(hjh]h int num_ct}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubj)}(hhh]j)}(h6Number of irq_chip_type instances associated with thish]h6Number of irq_chip_type instances associated with this}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjHubj)}(h:``unsigned int irq_base`` Interrupt base nr for this chip h](j)}(h``unsigned int irq_base``h]j)}(hjh]hunsigned int irq_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubj)}(hhh]j)}(hInterrupt base nr for this chiph]hInterrupt base nr for this chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjHubj)}(h;``void __iomem *reg_base`` Register base address (virtual) h](j)}(h``void __iomem *reg_base``h]j)}(hjh]hvoid __iomem *reg_base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhjubj)}(hhh]j)}(hRegister base address (virtual)h]hRegister base address (virtual)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjHubj)}(hN``irq_flow_handler_t handler`` Default flow handler associated with this chip h](j)}(h``irq_flow_handler_t handler``h]j)}(hj5h]hirq_flow_handler_t handler}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj/ubj)}(hhh]j)}(h.Default flow handler associated with this chiph]h.Default flow handler associated with this chip}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJhKhjKubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhjJhKhjHubeh}(h]h ]h"]h$]h&]uh1jhj,ubj)}(h**Description**h]jz)}(hjph]h Description}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjnubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj,ubj)}(h{Returns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and **handler**h](hpReturns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and }(hjhhhNhNubjz)}(h **handler**h]hhandler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chKhj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM+irq_domain_alloc_generic_chips (C function) c.irq_domain_alloc_generic_chipshNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hjint irq_domain_alloc_generic_chips (struct irq_domain *d, const struct irq_domain_chip_generic_info *info)h]j])}(hiint irq_domain_alloc_generic_chips(struct irq_domain *d, const struct irq_domain_chip_generic_info *info)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_domain_alloc_generic_chipsh]j)}(hirq_domain_alloc_generic_chipsh]hirq_domain_alloc_generic_chips}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(hG(struct irq_domain *d, const struct irq_domain_chip_generic_info *info)h](j)}(hstruct irq_domain *dh](j)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj modnameN classnameNjj)}j]j)}jjsb c.irq_domain_alloc_generic_chipsasbuh1hhjubju)}(h h]h }(hj> hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjL hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hjY hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h/const struct irq_domain_chip_generic_info *infoh](j)}(hjh]hconst}(hjq hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm ubju)}(h h]h }(hj~ hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjm ubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm ubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjm ubh)}(hhh]j)}(hirq_domain_chip_generic_infoh]hirq_domain_chip_generic_info}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj modnameN classnameNjj)}j]j: c.irq_domain_alloc_generic_chipsasbuh1hhjm ubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjm ubj )}(hj h]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm ubj)}(hinfoh]hinfo}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjm ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h(Allocate generic chips for an irq domainh]h(Allocate generic chips for an irq domain}(hj !hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj !hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj%!jkj%!jljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_domain *d`` irq domain for which to allocate chips ``const struct irq_domain_chip_generic_info *info`` Generic chip information **Return** 0 on success, negative error code on failureh](j)}(h**Parameters**h]jz)}(hj/!h]h Parameters}(hj1!hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj-!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)!ubj)}(hhh](j)}(h@``struct irq_domain *d`` irq domain for which to allocate chips h](j)}(h``struct irq_domain *d``h]j)}(hjN!h]hstruct irq_domain *d}(hjP!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhjH!ubj)}(hhh]j)}(h&irq domain for which to allocate chipsh]h&irq domain for which to allocate chips}(hjg!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc!hMhjd!ubah}(h]h ]h"]h$]h&]uh1jhjH!ubeh}(h]h ]h"]h$]h&]uh1jhjc!hMhjE!ubj)}(hM``const struct irq_domain_chip_generic_info *info`` Generic chip information h](j)}(h3``const struct irq_domain_chip_generic_info *info``h]j)}(hj!h]h/const struct irq_domain_chip_generic_info *info}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj!ubj)}(hhh]j)}(hGeneric chip informationh]hGeneric chip information}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMhjE!ubeh}(h]h ]h"]h$]h&]uh1jhj)!ubj)}(h **Return**h]jz)}(hj!h]hReturn}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)!ubj)}(h,0 on success, negative error code on failureh]h,0 on success, negative error code on failure}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)!ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM,irq_domain_remove_generic_chips (C function)!c.irq_domain_remove_generic_chipshNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h;void irq_domain_remove_generic_chips (struct irq_domain *d)h]j])}(h:void irq_domain_remove_generic_chips(struct irq_domain *d)h](jc)}(hvoidh]hvoid}(hj"hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj"hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMaubju)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj"hhhj"hMaubj)}(hirq_domain_remove_generic_chipsh]j)}(hirq_domain_remove_generic_chipsh]hirq_domain_remove_generic_chips}(hj("hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$"ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj"hhhj"hMaubj)}(h(struct irq_domain *d)h]j)}(hstruct irq_domain *dh](j)}(hjh]hstruct}(hjD"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@"ubju)}(h h]h }(hjQ"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@"ubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hjb"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_"ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjd"modnameN classnameNjj)}j]j)}jj*"sb!c.irq_domain_remove_generic_chipsasbuh1hhj@"ubju)}(h h]h }(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@"ubj )}(hj h]h*}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@"ubj)}(hjh]hd}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@"ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj<"ubah}(h]h ]h"]h$]h&]hhuh1jhj"hhhj"hMaubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj!hhhj"hMaubah}(h]j!ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj"hMahj!hhubjI)}(hhh]j)}(h'Remove generic chips from an irq domainh]h'Remove generic chips from an irq domain}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMahj"hhubah}(h]h ]h"]h$]h&]uh1jHhj!hhhj"hMaubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj"jkj"jljmjnuh1jQhhhj!hNhNubjp)}(h_**Parameters** ``struct irq_domain *d`` irq domain for which generic chips are to be removedh](j)}(h**Parameters**h]jz)}(hj"h]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMehj"ubj)}(hhh]j)}(hM``struct irq_domain *d`` irq domain for which generic chips are to be removedh](j)}(h``struct irq_domain *d``h]j)}(hj#h]hstruct irq_domain *d}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMghj#ubj)}(hhh]j)}(h4irq domain for which generic chips are to be removedh]h4irq domain for which generic chips are to be removed}(hj #hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMbhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhj#hMghj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM-__irq_alloc_domain_generic_chips (C function)"c.__irq_alloc_domain_generic_chipshNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hint __irq_alloc_domain_generic_chips (struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h]j])}(hint __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h](jc)}(hinth]hint}(hja#hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj]#hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMwubju)}(h h]h }(hjp#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]#hhhjo#hMwubj)}(h __irq_alloc_domain_generic_chipsh]j)}(h __irq_alloc_domain_generic_chipsh]h __irq_alloc_domain_generic_chips}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~#ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]#hhhjo#hMwubj)}(h(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h](j)}(hstruct irq_domain *dh](j)}(hjh]hstruct}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubju)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj#modnameN classnameNjj)}j]j)}jj#sb"c.__irq_alloc_domain_generic_chipsasbuh1hhj#ubju)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubj )}(hj h]h*}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]hd}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hint irqs_per_chiph](jc)}(hinth]hint}(hj$hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj $ubju)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj $ubj)}(h irqs_per_chiph]h irqs_per_chip}(hj+$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj $ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(h int num_cth](jc)}(hinth]hint}(hjD$hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj@$ubju)}(h h]h }(hjR$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@$ubj)}(hnum_cth]hnum_ct}(hj`$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hconst char *nameh](j)}(hjh]hconst}(hjy$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju$ubju)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthju$ubjc)}(hcharh]hchar}(hj$hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhju$ubju)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthju$ubj )}(hj h]h*}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju$ubj)}(hnameh]hname}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hirq_flow_handler_t handlerh](h)}(hhh]j)}(hirq_flow_handler_th]hirq_flow_handler_t}(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj$modnameN classnameNjj)}j]j#"c.__irq_alloc_domain_generic_chipsasbuh1hhj$ubju)}(h h]h }(hj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$ubj)}(hhandlerh]hhandler}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hj%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj%ubju)}(h h]h }(hj,%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubjc)}(hinth]hint}(hj:%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj%ubju)}(h h]h }(hjH%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubj)}(hclrh]hclr}(hjV%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hjo%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjk%ubju)}(h h]h }(hj}%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjk%ubjc)}(hinth]hint}(hj%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjk%ubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjk%ubj)}(hseth]hset}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjk%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(henum irq_gc_flags gcflagsh](j)}(henumh]henum}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubh)}(hhh]j)}(h irq_gc_flagsh]h irq_gc_flags}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj%modnameN classnameNjj)}j]j#"c.__irq_alloc_domain_generic_chipsasbuh1hhj%ubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubj)}(hgcflagsh]hgcflags}(hj &hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubeh}(h]h ]h"]h$]h&]hhuh1jhj]#hhhjo#hMwubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjY#hhhjo#hMwubah}(h]jT#ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjo#hMwhjV#hhubjI)}(hhh]j)}(h(Allocate generic chips for an irq domainh]h(Allocate generic chips for an irq domain}(hj5&hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMwhj2&hhubah}(h]h ]h"]h$]h&]uh1jHhjV#hhhjo#hMwubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjM&jkjM&jljmjnuh1jQhhhj!hNhNubjp)}(hX,**Parameters** ``struct irq_domain *d`` irq domain for which to allocate chips ``int irqs_per_chip`` Number of interrupts each chip handles (max 32) ``int num_ct`` Number of irq_chip_type instances associated with this ``const char *name`` Name of the irq chip ``irq_flow_handler_t handler`` Default flow handler associated with these chips ``unsigned int clr`` IRQ_* bits to clear in the mapping function ``unsigned int set`` IRQ_* bits to set in the mapping function ``enum irq_gc_flags gcflags`` Generic chip specific setup flagsh](j)}(h**Parameters**h]jz)}(hjW&h]h Parameters}(hjY&hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjU&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM{hjQ&ubj)}(hhh](j)}(h@``struct irq_domain *d`` irq domain for which to allocate chips h](j)}(h``struct irq_domain *d``h]j)}(hjv&h]hstruct irq_domain *d}(hjx&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjt&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMxhjp&ubj)}(hhh]j)}(h&irq domain for which to allocate chipsh]h&irq domain for which to allocate chips}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&hMxhj&ubah}(h]h ]h"]h$]h&]uh1jhjp&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMxhjm&ubj)}(hF``int irqs_per_chip`` Number of interrupts each chip handles (max 32) h](j)}(h``int irqs_per_chip``h]j)}(hj&h]hint irqs_per_chip}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMyhj&ubj)}(hhh]j)}(h/Number of interrupts each chip handles (max 32)h]h/Number of interrupts each chip handles (max 32)}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&hMyhj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMyhjm&ubj)}(hF``int num_ct`` Number of irq_chip_type instances associated with this h](j)}(h``int num_ct``h]j)}(hj&h]h int num_ct}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMzhj&ubj)}(hhh]j)}(h6Number of irq_chip_type instances associated with thish]h6Number of irq_chip_type instances associated with this}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&hMzhj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhj&hMzhjm&ubj)}(h*``const char *name`` Name of the irq chip h](j)}(h``const char *name``h]j)}(hj!'h]hconst char *name}(hj#'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM{hj'ubj)}(hhh]j)}(hName of the irq chiph]hName of the irq chip}(hj:'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6'hM{hj7'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj6'hM{hjm&ubj)}(hP``irq_flow_handler_t handler`` Default flow handler associated with these chips h](j)}(h``irq_flow_handler_t handler``h]j)}(hjZ'h]hirq_flow_handler_t handler}(hj\'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM|hjT'ubj)}(hhh]j)}(h0Default flow handler associated with these chipsh]h0Default flow handler associated with these chips}(hjs'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjo'hM|hjp'ubah}(h]h ]h"]h$]h&]uh1jhjT'ubeh}(h]h ]h"]h$]h&]uh1jhjo'hM|hjm&ubj)}(hA``unsigned int clr`` IRQ_* bits to clear in the mapping function h](j)}(h``unsigned int clr``h]j)}(hj'h]hunsigned int clr}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM}hj'ubj)}(hhh]j)}(h+IRQ_* bits to clear in the mapping functionh]h+IRQ_* bits to clear in the mapping function}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'hM}hj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM}hjm&ubj)}(h?``unsigned int set`` IRQ_* bits to set in the mapping function h](j)}(h``unsigned int set``h]j)}(hj'h]hunsigned int set}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM~hj'ubj)}(hhh]j)}(h)IRQ_* bits to set in the mapping functionh]h)IRQ_* bits to set in the mapping function}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'hM~hj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hM~hjm&ubj)}(h?``enum irq_gc_flags gcflags`` Generic chip specific setup flagsh](j)}(h``enum irq_gc_flags gcflags``h]j)}(hj(h]henum irq_gc_flags gcflags}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj'ubj)}(hhh]j)}(h!Generic chip specific setup flagsh]h!Generic chip specific setup flags}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj(ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhjm&ubeh}(h]h ]h"]h$]h&]uh1jhjQ&ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM(irq_get_domain_generic_chip (C function)c.irq_get_domain_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hastruct irq_chip_generic * irq_get_domain_generic_chip (struct irq_domain *d, unsigned int hw_irq)h]j])}(h_struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)h](j)}(hjh]hstruct}(hj_(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[(hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hjm(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[(hhhjl(hMubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hj~(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{(ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj(modnameN classnameNjj)}j]j)}jirq_get_domain_generic_chipsbc.irq_get_domain_generic_chipasbuh1hhj[(hhhjl(hMubju)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[(hhhjl(hMubj )}(hj h]h*}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[(hhhjl(hMubj)}(hirq_get_domain_generic_chiph]j)}(hj(h]hirq_get_domain_generic_chip}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj[(hhhjl(hMubj)}(h+(struct irq_domain *d, unsigned int hw_irq)h](j)}(hstruct irq_domain *d h](j)}(hjh]hstruct}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubju)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj(ubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj(modnameN classnameNjj)}j]j(c.irq_get_domain_generic_chipasbuh1hhj(ubju)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj(ubj )}(hj h]h*}(hj#)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubj)}(hjh]hd}(hj0)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj(ubj)}(hunsigned int hw_irqh](jc)}(hunsignedh]hunsigned}(hjH)hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjD)ubju)}(h h]h }(hjV)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjD)ubjc)}(hinth]hint}(hjd)hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjD)ubju)}(h h]h }(hjr)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjD)ubj)}(hhw_irqh]hhw_irq}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjD)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj(ubeh}(h]h ]h"]h$]h&]hhuh1jhj[(hhhjl(hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjW(hhhjl(hMubah}(h]jR(ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjl(hMhjT(hhubjI)}(hhh]j)}(h-Get a pointer to the generic chip of a hw_irqh]h-Get a pointer to the generic chip of a hw_irq}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)hhubah}(h]h ]h"]h$]h&]uh1jHhjT(hhhjl(hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj)jkj)jljmjnuh1jQhhhj!hNhNubjp)}(hr**Parameters** ``struct irq_domain *d`` irq domain pointer ``unsigned int hw_irq`` Hardware interrupt numberh](j)}(h**Parameters**h]jz)}(hj)h]h Parameters}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj)ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)ubj)}(hhh](j)}(h,``struct irq_domain *d`` irq domain pointer h](j)}(h``struct irq_domain *d``h]j)}(hj)h]hstruct irq_domain *d}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj)ubj)}(hhh]j)}(hirq domain pointerh]hirq domain pointer}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhj)ubj)}(h1``unsigned int hw_irq`` Hardware interrupt numberh](j)}(h``unsigned int hw_irq``h]j)}(hj$*h]hunsigned int hw_irq}(hj&*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj*ubj)}(hhh]j)}(hHardware interrupt numberh]hHardware interrupt number}(hj=*hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj:*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhj9*hMhj)ubeh}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#irq_setup_generic_chip (C function)c.irq_setup_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hvoid irq_setup_generic_chip (struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h]j])}(h~void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h](jc)}(hvoidh]hvoid}(hj~*hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjz*hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjz*hhhj*hMubj)}(hirq_setup_generic_chiph]j)}(hirq_setup_generic_chiph]hirq_setup_generic_chip}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjz*hhhj*hMubj)}(hc(struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h](j)}(hstruct irq_chip_generic *gch](j)}(hjh]hstruct}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubju)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj*ubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj*modnameN classnameNjj)}j]j)}jj*sbc.irq_setup_generic_chipasbuh1hhj*ubju)}(h h]h }(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj*ubj )}(hj h]h*}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubj)}(hgch]hgc}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(hu32 mskh](h)}(hhh]j)}(hu32h]hu32}(hj0+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-+ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj2+modnameN classnameNjj)}j]j*c.irq_setup_generic_chipasbuh1hhj)+ubju)}(h h]h }(hjN+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)+ubj)}(hmskh]hmsk}(hj\+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(henum irq_gc_flags flagsh](j)}(hj%h]henum}(hju+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq+ubju)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjq+ubh)}(hhh]j)}(h irq_gc_flagsh]h irq_gc_flags}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj+modnameN classnameNjj)}j]j*c.irq_setup_generic_chipasbuh1hhjq+ubju)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjq+ubj)}(hflagsh]hflags}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hj+hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ubju)}(h h]h }(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ubjc)}(hinth]hint}(hj+hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ubju)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ubj)}(hclrh]hclr}(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hj),hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj%,ubju)}(h h]h }(hj7,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%,ubjc)}(hinth]hint}(hjE,hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj%,ubju)}(h h]h }(hjS,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%,ubj)}(hseth]hset}(hja,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%,ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj*ubeh}(h]h ]h"]h$]h&]hhuh1jhjz*hhhj*hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjv*hhhj*hMubah}(h]jq*ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj*hMhjs*hhubjI)}(hhh]j)}(h/Setup a range of interrupts with a generic chiph]h/Setup a range of interrupts with a generic chip}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj,hhubah}(h]h ]h"]h$]h&]uh1jHhjs*hhhj*hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj,jkj,jljmjnuh1jQhhhj!hNhNubjp)}(hX**Parameters** ``struct irq_chip_generic *gc`` Generic irq chip holding all data ``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base ``enum irq_gc_flags flags`` Flags for initialization ``unsigned int clr`` IRQ_* bits to clear ``unsigned int set`` IRQ_* bits to set **Description** Set up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.h](j)}(h**Parameters**h]jz)}(hj,h]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hj,ubj)}(hhh](j)}(hB``struct irq_chip_generic *gc`` Generic irq chip holding all data h](j)}(h``struct irq_chip_generic *gc``h]j)}(hj,h]hstruct irq_chip_generic *gc}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj,ubj)}(hhh]j)}(h!Generic irq chip holding all datah]h!Generic irq chip holding all data}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,hMhj,ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhj,ubj)}(hL``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base h](j)}(h ``u32 msk``h]j)}(hj-h]hu32 msk}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hj,ubj)}(hhh]j)}(h?Bitmask holding the irqs to initialize relative to gc->irq_baseh]h?Bitmask holding the irqs to initialize relative to gc->irq_base}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj,ubj)}(h5``enum irq_gc_flags flags`` Flags for initialization h](j)}(h``enum irq_gc_flags flags``h]j)}(hj>-h]henum irq_gc_flags flags}(hj@-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hj8-ubj)}(hhh]j)}(hFlags for initializationh]hFlags for initialization}(hjW-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjS-hM hjT-ubah}(h]h ]h"]h$]h&]uh1jhj8-ubeh}(h]h ]h"]h$]h&]uh1jhjS-hM hj,ubj)}(h)``unsigned int clr`` IRQ_* bits to clear h](j)}(h``unsigned int clr``h]j)}(hjw-h]hunsigned int clr}(hjy-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hjq-ubj)}(hhh]j)}(hIRQ_* bits to clearh]hIRQ_* bits to clear}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1jhjq-ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj,ubj)}(h'``unsigned int set`` IRQ_* bits to set h](j)}(h``unsigned int set``h]j)}(hj-h]hunsigned int set}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hj-ubj)}(hhh]j)}(hIRQ_* bits to seth]hIRQ_* bits to set}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj,ubeh}(h]h ]h"]h$]h&]uh1jhj,ubj)}(h**Description**h]jz)}(hj-h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMhj,ubj)}(hSet up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.h]hSet up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_setup_alt_chip (C function)c.irq_setup_alt_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h>int irq_setup_alt_chip (struct irq_data *d, unsigned int type)h]j])}(h=int irq_setup_alt_chip(struct irq_data *d, unsigned int type)h](jc)}(hinth]hint}(hj0.hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj,.hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM8ubju)}(h h]h }(hj?.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj,.hhhj>.hM8ubj)}(hirq_setup_alt_chiph]j)}(hirq_setup_alt_chiph]hirq_setup_alt_chip}(hjQ.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjM.ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj,.hhhj>.hM8ubj)}(h'(struct irq_data *d, unsigned int type)h](j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hjm.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhji.ubju)}(h h]h }(hjz.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthji.ubh)}(hhh]j)}(hirq_datah]hirq_data}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj.modnameN classnameNjj)}j]j)}jjS.sbc.irq_setup_alt_chipasbuh1hhji.ubju)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthji.ubj )}(hj h]h*}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhji.ubj)}(hjh]hd}(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhji.ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhje.ubj)}(hunsigned int typeh](jc)}(hunsignedh]hunsigned}(hj.hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj.ubju)}(h h]h }(hj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj.ubjc)}(hinth]hint}(hj.hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj.ubju)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj.ubj)}(htypeh]htype}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhje.ubeh}(h]h ]h"]h$]h&]hhuh1jhj,.hhhj>.hM8ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj(.hhhj>.hM8ubah}(h]j#.ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj>.hM8hj%.hhubjI)}(hhh]j)}(hSwitch to alternative chiph]hSwitch to alternative chip}(hj@/hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM8hj=/hhubah}(h]h ]h"]h$]h&]uh1jHhj%.hhhj>.hM8ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjX/jkjX/jljmjnuh1jQhhhj!hNhNubjp)}(h**Parameters** ``struct irq_data *d`` irq_data for this interrupt ``unsigned int type`` Flow type to be initialized **Description** Only to be called from chip->irq_set_type() callbacks.h](j)}(h**Parameters**h]jz)}(hjb/h]h Parameters}(hjd/hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj`/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM<hj\/ubj)}(hhh](j)}(h3``struct irq_data *d`` irq_data for this interrupt h](j)}(h``struct irq_data *d``h]j)}(hj/h]hstruct irq_data *d}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM9hj{/ubj)}(hhh]j)}(hirq_data for this interrupth]hirq_data for this interrupt}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/hM9hj/ubah}(h]h ]h"]h$]h&]uh1jhj{/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM9hjx/ubj)}(h2``unsigned int type`` Flow type to be initialized h](j)}(h``unsigned int type``h]j)}(hj/h]hunsigned int type}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM:hj/ubj)}(hhh]j)}(hFlow type to be initializedh]hFlow type to be initialized}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/hM:hj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jhj/hM:hjx/ubeh}(h]h ]h"]h$]h&]uh1jhj\/ubj)}(h**Description**h]jz)}(hj/h]h Description}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj/ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM<hj\/ubj)}(h6Only to be called from chip->irq_set_type() callbacks.h]h6Only to be called from chip->irq_set_type() callbacks.}(hj 0hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chM;hj\/ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_remove_generic_chip (C function)c.irq_remove_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hgvoid irq_remove_generic_chip (struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h]j])}(hfvoid irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h](jc)}(hvoidh]hvoid}(hj:0hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj60hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMPubju)}(h h]h }(hjI0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj60hhhjH0hMPubj)}(hirq_remove_generic_chiph]j)}(hirq_remove_generic_chiph]hirq_remove_generic_chip}(hj[0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjW0ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj60hhhjH0hMPubj)}(hJ(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h](j)}(hstruct irq_chip_generic *gch](j)}(hjh]hstruct}(hjw0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs0ubju)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjs0ubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj0modnameN classnameNjj)}j]j)}jj]0sbc.irq_remove_generic_chipasbuh1hhjs0ubju)}(h h]h }(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjs0ubj )}(hj h]h*}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs0ubj)}(hgch]hgc}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs0ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjo0ubj)}(hu32 mskh](h)}(hhh]j)}(hu32h]hu32}(hj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj0modnameN classnameNjj)}j]j0c.irq_remove_generic_chipasbuh1hhj0ubju)}(h h]h }(hj 1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj0ubj)}(hmskh]hmsk}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjo0ubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hj11hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj-1ubju)}(h h]h }(hj?1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj-1ubjc)}(hinth]hint}(hjM1hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj-1ubju)}(h h]h }(hj[1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj-1ubj)}(hclrh]hclr}(hji1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-1ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjo0ubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hj1hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj~1ubju)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~1ubjc)}(hinth]hint}(hj1hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj~1ubju)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~1ubj)}(hseth]hset}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~1ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjo0ubeh}(h]h ]h"]h$]h&]hhuh1jhj60hhhjH0hMPubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj20hhhjH0hMPubah}(h]j-0ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjH0hMPhj/0hhubjI)}(hhh]j)}(h Remove a chiph]h Remove a chip}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMPhj1hhubah}(h]h ]h"]h$]h&]uh1jHhj/0hhhjH0hMPubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj1jkj1jljmjnuh1jQhhhj!hNhNubjp)}(hXA**Parameters** ``struct irq_chip_generic *gc`` Generic irq chip holding all data ``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base ``unsigned int clr`` IRQ_* bits to clear ``unsigned int set`` IRQ_* bits to set **Description** Remove up to 32 interrupts starting from gc->irq_base.h](j)}(h**Parameters**h]jz)}(hj2h]h Parameters}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMThj2ubj)}(hhh](j)}(hB``struct irq_chip_generic *gc`` Generic irq chip holding all data h](j)}(h``struct irq_chip_generic *gc``h]j)}(hj%2h]hstruct irq_chip_generic *gc}(hj'2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMQhj2ubj)}(hhh]j)}(h!Generic irq chip holding all datah]h!Generic irq chip holding all data}(hj>2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:2hMQhj;2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj:2hMQhj2ubj)}(hL``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base h](j)}(h ``u32 msk``h]j)}(hj^2h]hu32 msk}(hj`2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMRhjX2ubj)}(hhh]j)}(h?Bitmask holding the irqs to initialize relative to gc->irq_baseh]h?Bitmask holding the irqs to initialize relative to gc->irq_base}(hjw2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjs2hMRhjt2ubah}(h]h ]h"]h$]h&]uh1jhjX2ubeh}(h]h ]h"]h$]h&]uh1jhjs2hMRhj2ubj)}(h)``unsigned int clr`` IRQ_* bits to clear h](j)}(h``unsigned int clr``h]j)}(hj2h]hunsigned int clr}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMShj2ubj)}(hhh]j)}(hIRQ_* bits to clearh]hIRQ_* bits to clear}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2hMShj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMShj2ubj)}(h'``unsigned int set`` IRQ_* bits to set h](j)}(h``unsigned int set``h]j)}(hj2h]hunsigned int set}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMThj2ubj)}(hhh]j)}(hIRQ_* bits to seth]hIRQ_* bits to set}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2hMThj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hMThj2ubeh}(h]h ]h"]h$]h&]uh1jhj2ubj)}(h**Description**h]jz)}(hj 3h]h Description}(hj 3hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj 3ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMVhj2ubj)}(h6Remove up to 32 interrupts starting from gc->irq_base.h]h6Remove up to 32 interrupts starting from gc->irq_base.}(hj!3hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:484: ./kernel/irq/generic-chip.chMUhj2ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj!hhhNhNubeh}(h]generic-interrupt-chipah ]h"]generic interrupt chipah$]h&]uh1jLhjNhhhjahMubjM)}(hhh](jR)}(h Structuresh]h Structures}(hjB3hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj?3hhhjahMubj)}(hpThis chapter contains the autogenerated documentation of the structures which are used in the generic IRQ layer.h]hpThis chapter contains the autogenerated documentation of the structures which are used in the generic IRQ layer.}(hjP3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj?3hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_common_data (C struct)c.irq_common_datahNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_common_datah]j])}(hstruct irq_common_datah](j)}(hjh]hstruct}(hjw3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjs3hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKubju)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjs3hhhj3hKubj)}(hirq_common_datah]j)}(hjq3h]hirq_common_data}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjs3hhhj3hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjo3hhhj3hKubah}(h]jj3ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj3hKhjl3hhubjI)}(hhh]j)}(h#per irq data shared by all irqchipsh]h#per irq data shared by all irqchips}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj3hhubah}(h]h ]h"]h$]h&]uh1jHhjl3hhhj3hKubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjj3jkj3jljmjnuh1jQhhhj?3hNhNubjp)}(hXD**Definition**:: struct irq_common_data { unsigned int state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; }; **Members** ``state_use_accessors`` status information for irq chip functions. Use accessor functions to deal with it ``node`` node index useful for balancing ``handler_data`` per-IRQ data for the irq_chip methods ``msi_desc`` MSI descriptor ``affinity`` IRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent. ``effective_affinity`` The effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of **affinity**. ``ipi_offset`` Offset of first IPI target cpu in **affinity**. Optional.h](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj3ubh:}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj3ubj )}(hXstruct irq_common_data { unsigned int state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; };h]hXstruct irq_common_data { unsigned int state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; };}hj3sbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj3ubj)}(h **Members**h]jz)}(hj4h]hMembers}(hj 4hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj3ubj)}(hhh](j)}(hj``state_use_accessors`` status information for irq chip functions. Use accessor functions to deal with it h](j)}(h``state_use_accessors``h]j)}(hj&4h]hstate_use_accessors}(hj(4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj 4ubj)}(hhh]j)}(hQstatus information for irq chip functions. Use accessor functions to deal with ith]hQstatus information for irq chip functions. Use accessor functions to deal with it}(hj?4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj<4ubah}(h]h ]h"]h$]h&]uh1jhj 4ubeh}(h]h ]h"]h$]h&]uh1jhj;4hKhj4ubj)}(h)``node`` node index useful for balancing h](j)}(h``node``h]j)}(hj`4h]hnode}(hjb4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhjZ4ubj)}(hhh]j)}(hnode index useful for balancingh]hnode index useful for balancing}(hjy4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju4hKhjv4ubah}(h]h ]h"]h$]h&]uh1jhjZ4ubeh}(h]h ]h"]h$]h&]uh1jhju4hKhj4ubj)}(h7``handler_data`` per-IRQ data for the irq_chip methods h](j)}(h``handler_data``h]j)}(hj4h]h handler_data}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj4ubj)}(hhh]j)}(h%per-IRQ data for the irq_chip methodsh]h%per-IRQ data for the irq_chip methods}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hKhj4ubj)}(h``msi_desc`` MSI descriptor h](j)}(h ``msi_desc``h]j)}(hj4h]hmsi_desc}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj4ubj)}(hhh]j)}(hMSI descriptorh]hMSI descriptor}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4hKhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hKhj4ubj)}(h``affinity`` IRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent. h](j)}(h ``affinity``h]j)}(hj 5h]haffinity}(hj 5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj5ubj)}(hhh]j)}(hrIRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent.h]hrIRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent.}(hj$5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj!5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj 5hKhj4ubj)}(h``effective_affinity`` The effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of **affinity**. h](j)}(h``effective_affinity``h]j)}(hjE5h]heffective_affinity}(hjG5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj?5ubj)}(hhh]j)}(hrThe effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of **affinity**.h](heThe effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of }(hj^5hhhNhNubjz)}(h **affinity**h]haffinity}(hjf5hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj^5ubh.}(hj^5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj[5ubah}(h]h ]h"]h$]h&]uh1jhj?5ubeh}(h]h ]h"]h$]h&]uh1jhjZ5hKhj4ubj)}(hH``ipi_offset`` Offset of first IPI target cpu in **affinity**. Optional.h](j)}(h``ipi_offset``h]j)}(hj5h]h ipi_offset}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj5ubj)}(hhh]j)}(h9Offset of first IPI target cpu in **affinity**. Optional.h](h"Offset of first IPI target cpu in }(hj5hhhNhNubjz)}(h **affinity**h]haffinity}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj5ubh . Optional.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hKhj4ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_data (C struct) c.irq_datahNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_datah]j])}(hstruct irq_datah](j)}(hjh]hstruct}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKubju)}(h h]h }(hj 6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5hhhj 6hKubj)}(hirq_datah]j)}(hj5h]hirq_data}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj5hhhj 6hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj5hhhj 6hKubah}(h]j5ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj 6hKhj5hhubjI)}(hhh]j)}(h/per irq chip data passed down to chip functionsh]h/per irq chip data passed down to chip functions}(hj?6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj<6hhubah}(h]h ]h"]h$]h&]uh1jHhj5hhhj 6hKubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjjW6jkjW6jljmjnuh1jQhhhj?3hNhNubjp)}(hX**Definition**:: struct irq_data { u32 mask; unsigned int irq; irq_hw_number_t hwirq; struct irq_common_data *common; struct irq_chip *chip; struct irq_domain *domain; #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY; struct irq_data *parent_data; #endif; void *chip_data; }; **Members** ``mask`` precomputed bitmask for accessing the chip registers ``irq`` interrupt number ``hwirq`` hardware interrupt number, local to the interrupt domain ``common`` point to data shared by all irqchips ``chip`` low level interrupt hardware access ``domain`` Interrupt translation domain; responsible for mapping between hwirq number and linux irq number. ``parent_data`` pointer to parent struct irq_data to support hierarchy irq_domain ``chip_data`` platform-specific per-chip private data for the chip methods, to allow shared chip implementationsh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hjc6hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj_6ubh:}(hj_6hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj[6ubj )}(hX6struct irq_data { u32 mask; unsigned int irq; irq_hw_number_t hwirq; struct irq_common_data *common; struct irq_chip *chip; struct irq_domain *domain; #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY; struct irq_data *parent_data; #endif; void *chip_data; };h]hX6struct irq_data { u32 mask; unsigned int irq; irq_hw_number_t hwirq; struct irq_common_data *common; struct irq_chip *chip; struct irq_domain *domain; #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY; struct irq_data *parent_data; #endif; void *chip_data; };}hj|6sbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj[6ubj)}(h **Members**h]jz)}(hj6h]hMembers}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj[6ubj)}(hhh](j)}(h>``mask`` precomputed bitmask for accessing the chip registers h](j)}(h``mask``h]j)}(hj6h]hmask}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj6ubj)}(hhh]j)}(h4precomputed bitmask for accessing the chip registersh]h4precomputed bitmask for accessing the chip registers}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6hKhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hKhj6ubj)}(h``irq`` interrupt number h](j)}(h``irq``h]j)}(hj6h]hirq}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj6ubj)}(hhh]j)}(hinterrupt numberh]hinterrupt number}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6hKhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hKhj6ubj)}(hC``hwirq`` hardware interrupt number, local to the interrupt domain h](j)}(h ``hwirq``h]j)}(hj7h]hhwirq}(hj 7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj7ubj)}(hhh]j)}(h8hardware interrupt number, local to the interrupt domainh]h8hardware interrupt number, local to the interrupt domain}(hj77hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj37hKhj47ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj37hKhj6ubj)}(h0``common`` point to data shared by all irqchips h](j)}(h ``common``h]j)}(hjW7h]hcommon}(hjY7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhjQ7ubj)}(hhh]j)}(h$point to data shared by all irqchipsh]h$point to data shared by all irqchips}(hjp7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjl7hKhjm7ubah}(h]h ]h"]h$]h&]uh1jhjQ7ubeh}(h]h ]h"]h$]h&]uh1jhjl7hKhj6ubj)}(h-``chip`` low level interrupt hardware access h](j)}(h``chip``h]j)}(hj7h]hchip}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj7ubj)}(hhh]j)}(h#low level interrupt hardware accessh]h#low level interrupt hardware access}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7hKhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hKhj6ubj)}(hl``domain`` Interrupt translation domain; responsible for mapping between hwirq number and linux irq number. h](j)}(h ``domain``h]j)}(hj7h]hdomain}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj7ubj)}(hhh]j)}(h`Interrupt translation domain; responsible for mapping between hwirq number and linux irq number.h]h`Interrupt translation domain; responsible for mapping between hwirq number and linux irq number.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hKhj6ubj)}(hR``parent_data`` pointer to parent struct irq_data to support hierarchy irq_domain h](j)}(h``parent_data``h]j)}(hj8h]h parent_data}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj7ubj)}(hhh]j)}(hApointer to parent struct irq_data to support hierarchy irq_domainh]hApointer to parent struct irq_data to support hierarchy irq_domain}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj8ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj8hKhj6ubj)}(hp``chip_data`` platform-specific per-chip private data for the chip methods, to allow shared chip implementationsh](j)}(h ``chip_data``h]j)}(hj=8h]h chip_data}(hj?8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKhj78ubj)}(hhh]j)}(hbplatform-specific per-chip private data for the chip methods, to allow shared chip implementationsh]hbplatform-specific per-chip private data for the chip methods, to allow shared chip implementations}(hjV8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR8hKhjS8ubah}(h]h ]h"]h$]h&]uh1jhj78ubeh}(h]h ]h"]h$]h&]uh1jhjR8hKhj6ubeh}(h]h ]h"]h$]h&]uh1jhj[6ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip (C struct) c.irq_chiphNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_chiph]j])}(hstruct irq_chiph](j)}(hjh]hstruct}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhKubju)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8hhhj8hKubj)}(hirq_chiph]j)}(hj8h]hirq_chip}(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj8hhhj8hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj8hhhj8hKubah}(h]j8ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj8hKhj8hhubjI)}(hhh]j)}(h"hardware interrupt chip descriptorh]h"hardware interrupt chip descriptor}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj8hhubah}(h]h ]h"]h$]h&]uh1jHhj8hhhj8hKubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjj8jkj8jljmjnuh1jQhhhj?3hNhNubjp)}(hXY**Definition**:: struct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); void (*irq_pre_redirect)(struct irq_data *data); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); void (*irq_force_complete_move)(struct irq_data *data); unsigned long flags; }; **Members** ``name`` name for /proc/interrupts ``irq_startup`` start up the interrupt (defaults to ->enable if NULL) ``irq_shutdown`` shut down the interrupt (defaults to ->disable if NULL) ``irq_enable`` enable the interrupt (defaults to chip->unmask if NULL) ``irq_disable`` disable the interrupt ``irq_ack`` start of a new interrupt ``irq_mask`` mask an interrupt source ``irq_mask_ack`` ack and mask an interrupt source ``irq_unmask`` unmask an interrupt source ``irq_eoi`` end of interrupt ``irq_set_affinity`` Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask. ``irq_pre_redirect`` Optional function to be invoked before redirecting an interrupt via irq_work. Called only on CONFIG_SMP. ``irq_retrigger`` resend an IRQ to the CPU ``irq_set_type`` set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ ``irq_set_wake`` enable/disable power-management wake-on of an IRQ ``irq_bus_lock`` function to lock access to slow bus (i2c) chips ``irq_bus_sync_unlock`` function to sync and unlock slow bus (i2c) chips ``irq_cpu_online`` configure an interrupt source for a secondary CPU ``irq_cpu_offline`` un-configure an interrupt source for a secondary CPU ``irq_suspend`` function called from core code on suspend once per chip, when one or more interrupts are installed ``irq_resume`` function called from core code on resume once per chip, when one ore more interrupts are installed ``irq_pm_shutdown`` function called from core code on shutdown once per chip ``irq_calc_mask`` Optional function to set irq_data.mask for special cases ``irq_print_chip`` optional to print special chip info in show_interrupts ``irq_request_resources`` optional to request resources before calling any other callback related to this irq ``irq_release_resources`` optional to release resources acquired with irq_request_resources ``irq_compose_msi_msg`` optional to compose message content for MSI ``irq_write_msi_msg`` optional to write message content for MSI ``irq_get_irqchip_state`` return the internal state of an interrupt ``irq_set_irqchip_state`` set the internal state of a interrupt ``irq_set_vcpu_affinity`` optional to target a vCPU in a virtual machine ``ipi_send_single`` send a single IPI to destination cpus ``ipi_send_mask`` send an IPI to destination cpus in cpumask ``irq_nmi_setup`` function called from core code before enabling an NMI ``irq_nmi_teardown`` function called from core code after disabling an NMI ``irq_force_complete_move`` optional function to force complete pending irq move ``flags`` chip specific flagsh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj8ubh:}(hj8hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj8ubj )}(hXstruct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); void (*irq_pre_redirect)(struct irq_data *data); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); void (*irq_force_complete_move)(struct irq_data *data); unsigned long flags; };h]hXstruct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); void (*irq_pre_redirect)(struct irq_data *data); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); void (*irq_force_complete_move)(struct irq_data *data); unsigned long flags; };}hj9sbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj8ubj)}(h **Members**h]jz)}(hj&9h]hMembers}(hj(9hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj$9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj8ubj)}(hhh](j)}(h#``name`` name for /proc/interrupts h](j)}(h``name``h]j)}(hjE9h]hname}(hjG9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?9ubj)}(hhh]j)}(hname for /proc/interruptsh]hname for /proc/interrupts}(hj^9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ9hMhj[9ubah}(h]h ]h"]h$]h&]uh1jhj?9ubeh}(h]h ]h"]h$]h&]uh1jhjZ9hMhj<9ubj)}(hF``irq_startup`` start up the interrupt (defaults to ->enable if NULL) h](j)}(h``irq_startup``h]j)}(hj~9h]h irq_startup}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjx9ubj)}(hhh]j)}(h5start up the interrupt (defaults to ->enable if NULL)h]h5start up the interrupt (defaults to ->enable if NULL)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhjx9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj<9ubj)}(hI``irq_shutdown`` shut down the interrupt (defaults to ->disable if NULL) h](j)}(h``irq_shutdown``h]j)}(hj9h]h irq_shutdown}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj9ubj)}(hhh]j)}(h7shut down the interrupt (defaults to ->disable if NULL)h]h7shut down the interrupt (defaults to ->disable if NULL)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj<9ubj)}(hG``irq_enable`` enable the interrupt (defaults to chip->unmask if NULL) h](j)}(h``irq_enable``h]j)}(hj9h]h irq_enable}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj9ubj)}(hhh]j)}(h7enable the interrupt (defaults to chip->unmask if NULL)h]h7enable the interrupt (defaults to chip->unmask if NULL)}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj<9ubj)}(h&``irq_disable`` disable the interrupt h](j)}(h``irq_disable``h]j)}(hj):h]h irq_disable}(hj+:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj':ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj#:ubj)}(hhh]j)}(hdisable the interrupth]hdisable the interrupt}(hjB:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>:hMhj?:ubah}(h]h ]h"]h$]h&]uh1jhj#:ubeh}(h]h ]h"]h$]h&]uh1jhj>:hMhj<9ubj)}(h%``irq_ack`` start of a new interrupt h](j)}(h ``irq_ack``h]j)}(hjb:h]hirq_ack}(hjd:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj\:ubj)}(hhh]j)}(hstart of a new interrupth]hstart of a new interrupt}(hj{:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjw:hMhjx:ubah}(h]h ]h"]h$]h&]uh1jhj\:ubeh}(h]h ]h"]h$]h&]uh1jhjw:hMhj<9ubj)}(h&``irq_mask`` mask an interrupt source h](j)}(h ``irq_mask``h]j)}(hj:h]hirq_mask}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj:ubj)}(hhh]j)}(hmask an interrupt sourceh]hmask an interrupt source}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj<9ubj)}(h2``irq_mask_ack`` ack and mask an interrupt source h](j)}(h``irq_mask_ack``h]j)}(hj:h]h irq_mask_ack}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj:ubj)}(hhh]j)}(h ack and mask an interrupt sourceh]h ack and mask an interrupt source}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj<9ubj)}(h*``irq_unmask`` unmask an interrupt source h](j)}(h``irq_unmask``h]j)}(hj ;h]h irq_unmask}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj;ubj)}(hhh]j)}(hunmask an interrupt sourceh]hunmask an interrupt source}(hj&;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj";hMhj#;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj";hMhj<9ubj)}(h``irq_eoi`` end of interrupt h](j)}(h ``irq_eoi``h]j)}(hjF;h]hirq_eoi}(hjH;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj@;ubj)}(hhh]j)}(hend of interrupth]hend of interrupt}(hj_;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[;hMhj\;ubah}(h]h ]h"]h$]h&]uh1jhj@;ubeh}(h]h ]h"]h$]h&]uh1jhj[;hMhj<9ubj)}(hX9``irq_set_affinity`` Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask. h](j)}(h``irq_set_affinity``h]j)}(hj;h]hirq_set_affinity}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj};ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjy;ubj)}(hhh]j)}(hX#Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask.h]hX#Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj;ubah}(h]h ]h"]h$]h&]uh1jhjy;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj<9ubj)}(h~``irq_pre_redirect`` Optional function to be invoked before redirecting an interrupt via irq_work. Called only on CONFIG_SMP. h](j)}(h``irq_pre_redirect``h]j)}(hj;h]hirq_pre_redirect}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj;ubj)}(hhh]j)}(hhOptional function to be invoked before redirecting an interrupt via irq_work. Called only on CONFIG_SMP.h]hhOptional function to be invoked before redirecting an interrupt via irq_work. Called only on CONFIG_SMP.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj<9ubj)}(h+``irq_retrigger`` resend an IRQ to the CPU h](j)}(h``irq_retrigger``h]j)}(hj;h]h irq_retrigger}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj;ubj)}(hhh]j)}(hresend an IRQ to the CPUh]hresend an IRQ to the CPU}(hj <hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<hMhj <ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj<9ubj)}(hC``irq_set_type`` set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ h](j)}(h``irq_set_type``h]j)}(hj,<h]h irq_set_type}(hj.<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj&<ubj)}(hhh]j)}(h1set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQh]h1set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ}(hjE<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA<hMhjB<ubah}(h]h ]h"]h$]h&]uh1jhj&<ubeh}(h]h ]h"]h$]h&]uh1jhjA<hMhj<9ubj)}(hC``irq_set_wake`` enable/disable power-management wake-on of an IRQ h](j)}(h``irq_set_wake``h]j)}(hje<h]h irq_set_wake}(hjg<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj_<ubj)}(hhh]j)}(h1enable/disable power-management wake-on of an IRQh]h1enable/disable power-management wake-on of an IRQ}(hj~<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz<hMhj{<ubah}(h]h ]h"]h$]h&]uh1jhj_<ubeh}(h]h ]h"]h$]h&]uh1jhjz<hMhj<9ubj)}(hA``irq_bus_lock`` function to lock access to slow bus (i2c) chips h](j)}(h``irq_bus_lock``h]j)}(hj<h]h irq_bus_lock}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj<ubj)}(hhh]j)}(h/function to lock access to slow bus (i2c) chipsh]h/function to lock access to slow bus (i2c) chips}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj<9ubj)}(hI``irq_bus_sync_unlock`` function to sync and unlock slow bus (i2c) chips h](j)}(h``irq_bus_sync_unlock``h]j)}(hj<h]hirq_bus_sync_unlock}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj<ubj)}(hhh]j)}(h0function to sync and unlock slow bus (i2c) chipsh]h0function to sync and unlock slow bus (i2c) chips}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj<9ubj)}(hE``irq_cpu_online`` configure an interrupt source for a secondary CPU h](j)}(h``irq_cpu_online``h]j)}(hj=h]hirq_cpu_online}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj =ubj)}(hhh]j)}(h1configure an interrupt source for a secondary CPUh]h1configure an interrupt source for a secondary CPU}(hj)=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%=hMhj&=ubah}(h]h ]h"]h$]h&]uh1jhj =ubeh}(h]h ]h"]h$]h&]uh1jhj%=hMhj<9ubj)}(hI``irq_cpu_offline`` un-configure an interrupt source for a secondary CPU h](j)}(h``irq_cpu_offline``h]j)}(hjI=h]hirq_cpu_offline}(hjK=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjC=ubj)}(hhh]j)}(h4un-configure an interrupt source for a secondary CPUh]h4un-configure an interrupt source for a secondary CPU}(hjb=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^=hMhj_=ubah}(h]h ]h"]h$]h&]uh1jhjC=ubeh}(h]h ]h"]h$]h&]uh1jhj^=hMhj<9ubj)}(hs``irq_suspend`` function called from core code on suspend once per chip, when one or more interrupts are installed h](j)}(h``irq_suspend``h]j)}(hj=h]h irq_suspend}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj|=ubj)}(hhh]j)}(hbfunction called from core code on suspend once per chip, when one or more interrupts are installedh]hbfunction called from core code on suspend once per chip, when one or more interrupts are installed}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj=ubah}(h]h ]h"]h$]h&]uh1jhj|=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<9ubj)}(hr``irq_resume`` function called from core code on resume once per chip, when one ore more interrupts are installed h](j)}(h``irq_resume``h]j)}(hj=h]h irq_resume}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj=ubj)}(hhh]j)}(hbfunction called from core code on resume once per chip, when one ore more interrupts are installedh]hbfunction called from core code on resume once per chip, when one ore more interrupts are installed}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<9ubj)}(hM``irq_pm_shutdown`` function called from core code on shutdown once per chip h](j)}(h``irq_pm_shutdown``h]j)}(hj=h]hirq_pm_shutdown}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj=ubj)}(hhh]j)}(h8function called from core code on shutdown once per chiph]h8function called from core code on shutdown once per chip}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj >hMhj >ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj >hMhj<9ubj)}(hK``irq_calc_mask`` Optional function to set irq_data.mask for special cases h](j)}(h``irq_calc_mask``h]j)}(hj/>h]h irq_calc_mask}(hj1>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj->ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj)>ubj)}(hhh]j)}(h8Optional function to set irq_data.mask for special casesh]h8Optional function to set irq_data.mask for special cases}(hjH>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD>hMhjE>ubah}(h]h ]h"]h$]h&]uh1jhj)>ubeh}(h]h ]h"]h$]h&]uh1jhjD>hMhj<9ubj)}(hJ``irq_print_chip`` optional to print special chip info in show_interrupts h](j)}(h``irq_print_chip``h]j)}(hjh>h]hirq_print_chip}(hjj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjf>ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjb>ubj)}(hhh]j)}(h6optional to print special chip info in show_interruptsh]h6optional to print special chip info in show_interrupts}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}>hMhj~>ubah}(h]h ]h"]h$]h&]uh1jhjb>ubeh}(h]h ]h"]h$]h&]uh1jhj}>hMhj<9ubj)}(hn``irq_request_resources`` optional to request resources before calling any other callback related to this irq h](j)}(h``irq_request_resources``h]j)}(hj>h]hirq_request_resources}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj>ubj)}(hhh]j)}(hSoptional to request resources before calling any other callback related to this irqh]hSoptional to request resources before calling any other callback related to this irq}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj<9ubj)}(h\``irq_release_resources`` optional to release resources acquired with irq_request_resources h](j)}(h``irq_release_resources``h]j)}(hj>h]hirq_release_resources}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj>ubj)}(hhh]j)}(hAoptional to release resources acquired with irq_request_resourcesh]hAoptional to release resources acquired with irq_request_resources}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj<9ubj)}(hD``irq_compose_msi_msg`` optional to compose message content for MSI h](j)}(h``irq_compose_msi_msg``h]j)}(hj?h]hirq_compose_msi_msg}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?ubj)}(hhh]j)}(h+optional to compose message content for MSIh]h+optional to compose message content for MSI}(hj.?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*?hMhj+?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj*?hMhj<9ubj)}(h@``irq_write_msi_msg`` optional to write message content for MSI h](j)}(h``irq_write_msi_msg``h]j)}(hjN?h]hirq_write_msi_msg}(hjP?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjH?ubj)}(hhh]j)}(h)optional to write message content for MSIh]h)optional to write message content for MSI}(hjg?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjc?hMhjd?ubah}(h]h ]h"]h$]h&]uh1jhjH?ubeh}(h]h ]h"]h$]h&]uh1jhjc?hMhj<9ubj)}(hD``irq_get_irqchip_state`` return the internal state of an interrupt h](j)}(h``irq_get_irqchip_state``h]j)}(hj?h]hirq_get_irqchip_state}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?ubj)}(hhh]j)}(h)return the internal state of an interrupth]h)return the internal state of an interrupt}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj<9ubj)}(h@``irq_set_irqchip_state`` set the internal state of a interrupt h](j)}(h``irq_set_irqchip_state``h]j)}(hj?h]hirq_set_irqchip_state}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?ubj)}(hhh]j)}(h%set the internal state of a interrupth]h%set the internal state of a interrupt}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj<9ubj)}(hI``irq_set_vcpu_affinity`` optional to target a vCPU in a virtual machine h](j)}(h``irq_set_vcpu_affinity``h]j)}(hj?h]hirq_set_vcpu_affinity}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?ubj)}(hhh]j)}(h.optional to target a vCPU in a virtual machineh]h.optional to target a vCPU in a virtual machine}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj<9ubj)}(h:``ipi_send_single`` send a single IPI to destination cpus h](j)}(h``ipi_send_single``h]j)}(hj2@h]hipi_send_single}(hj4@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj,@ubj)}(hhh]j)}(h%send a single IPI to destination cpush]h%send a single IPI to destination cpus}(hjK@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG@hMhjH@ubah}(h]h ]h"]h$]h&]uh1jhj,@ubeh}(h]h ]h"]h$]h&]uh1jhjG@hMhj<9ubj)}(h=``ipi_send_mask`` send an IPI to destination cpus in cpumask h](j)}(h``ipi_send_mask``h]j)}(hjk@h]h ipi_send_mask}(hjm@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhje@ubj)}(hhh]j)}(h*send an IPI to destination cpus in cpumaskh]h*send an IPI to destination cpus in cpumask}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhje@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj<9ubj)}(hH``irq_nmi_setup`` function called from core code before enabling an NMI h](j)}(h``irq_nmi_setup``h]j)}(hj@h]h irq_nmi_setup}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj@ubj)}(hhh]j)}(h5function called from core code before enabling an NMIh]h5function called from core code before enabling an NMI}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj<9ubj)}(hK``irq_nmi_teardown`` function called from core code after disabling an NMI h](j)}(h``irq_nmi_teardown``h]j)}(hj@h]hirq_nmi_teardown}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj@ubj)}(hhh]j)}(h5function called from core code after disabling an NMIh]h5function called from core code after disabling an NMI}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhj@hMhj<9ubj)}(hQ``irq_force_complete_move`` optional function to force complete pending irq move h](j)}(h``irq_force_complete_move``h]j)}(hjAh]hirq_force_complete_move}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjAubj)}(hhh]j)}(h4optional function to force complete pending irq moveh]h4optional function to force complete pending irq move}(hj/AhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+AhMhj,Aubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj+AhMhj<9ubj)}(h``flags`` chip specific flagsh](j)}(h ``flags``h]j)}(hjOAh]hflags}(hjQAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMAubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjIAubj)}(hhh]j)}(hchip specific flagsh]hchip specific flags}(hjhAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjeAubah}(h]h ]h"]h$]h&]uh1jhjIAubeh}(h]h ]h"]h$]h&]uh1jhjdAhMhj<9ubeh}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_regs (C struct)c.irq_chip_regshNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(h irq_chip_regsh]j])}(hstruct irq_chip_regsh](j)}(hjh]hstruct}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMubju)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjAhhhjAhMubj)}(h irq_chip_regsh]j)}(hjAh]h irq_chip_regs}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ](jjeh"]h$]h&]hhuh1jhjAhhhjAhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjAhhhjAhMubah}(h]jAah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjAhMhjAhhubjI)}(hhh]j)}(h#register offsets for struct irq_gcih]h#register offsets for struct irq_gci}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjAhhubah}(h]h ]h"]h$]h&]uh1jHhjAhhhjAhMubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjjBjkjBjljmjnuh1jQhhhj?3hNhNubjp)}(hX9**Definition**:: struct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; }; **Members** ``enable`` Enable register offset to reg_base ``disable`` Disable register offset to reg_base ``mask`` Mask register offset to reg_base ``ack`` Ack register offset to reg_base ``eoi`` Eoi register offset to reg_base ``type`` Type configuration register offset to reg_baseh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj Bubh:}(hj BhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj )}(hstruct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; };h]hstruct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; };}hj(Bsbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj)}(h **Members**h]jz)}(hj9Bh]hMembers}(hj;BhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj7Bubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj)}(hhh](j)}(h.``enable`` Enable register offset to reg_base h](j)}(h ``enable``h]j)}(hjXBh]henable}(hjZBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjRBubj)}(hhh]j)}(h"Enable register offset to reg_baseh]h"Enable register offset to reg_base}(hjqBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmBhMhjnBubah}(h]h ]h"]h$]h&]uh1jhjRBubeh}(h]h ]h"]h$]h&]uh1jhjmBhMhjOBubj)}(h0``disable`` Disable register offset to reg_base h](j)}(h ``disable``h]j)}(hjBh]hdisable}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj)}(hhh]j)}(h#Disable register offset to reg_baseh]h#Disable register offset to reg_base}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjOBubj)}(h*``mask`` Mask register offset to reg_base h](j)}(h``mask``h]j)}(hjBh]hmask}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj)}(hhh]j)}(h Mask register offset to reg_baseh]h Mask register offset to reg_base}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjOBubj)}(h(``ack`` Ack register offset to reg_base h](j)}(h``ack``h]j)}(hjCh]hack}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjBubj)}(hhh]j)}(hAck register offset to reg_baseh]hAck register offset to reg_base}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjChMhjOBubj)}(h(``eoi`` Eoi register offset to reg_base h](j)}(h``eoi``h]j)}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:Cubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj6Cubj)}(hhh]j)}(hEoi register offset to reg_baseh]hEoi register offset to reg_base}(hjUChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQChMhjRCubah}(h]h ]h"]h$]h&]uh1jhj6Cubeh}(h]h ]h"]h$]h&]uh1jhjQChMhjOBubj)}(h7``type`` Type configuration register offset to reg_baseh](j)}(h``type``h]j)}(hjuCh]htype}(hjwChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsCubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjoCubj)}(hhh]j)}(h.Type configuration register offset to reg_baseh]h.Type configuration register offset to reg_base}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjCubah}(h]h ]h"]h$]h&]uh1jhjoCubeh}(h]h ]h"]h$]h&]uh1jhjChMhjOBubeh}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_type (C struct)c.irq_chip_typehNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(h irq_chip_typeh]j])}(hstruct irq_chip_typeh](j)}(hjh]hstruct}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjChhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMubju)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjChhhjChMubj)}(h irq_chip_typeh]j)}(hjCh]h irq_chip_type}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubah}(h]h ](jjeh"]h$]h&]hhuh1jhjChhhjChMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjChhhjChMubah}(h]jCah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjChMhjChhubjI)}(hhh]j)}(h/Generic interrupt chip instance for a flow typeh]h/Generic interrupt chip instance for a flow type}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjDhhubah}(h]h ]h"]h$]h&]uh1jHhjChhhjChMubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjj)Djkj)Djljmjnuh1jQhhhj?3hNhNubjp)}(hX.**Definition**:: struct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; }; **Members** ``chip`` The real interrupt chip which provides the callbacks ``regs`` Register offsets for this chip ``handler`` Flow handler associated with this chip ``type`` Chip can handle these flow types ``mask_cache_priv`` Cached mask register private to the chip type ``mask_cache`` Pointer to cached mask registerh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hj5DhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj1Dubh:}(hj1DhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj-Dubj )}(hstruct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; };h]hstruct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; };}hjNDsbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj-Dubj)}(h **Members**h]jz)}(hj_Dh]hMembers}(hjaDhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj]Dubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj-Dubj)}(hhh](j)}(h>``chip`` The real interrupt chip which provides the callbacks h](j)}(h``chip``h]j)}(hj~Dh]hchip}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|Dubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjxDubj)}(hhh]j)}(h4The real interrupt chip which provides the callbacksh]h4The real interrupt chip which provides the callbacks}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjxDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjuDubj)}(h(``regs`` Register offsets for this chip h](j)}(h``regs``h]j)}(hjDh]hregs}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjDubj)}(hhh]j)}(hRegister offsets for this chiph]hRegister offsets for this chip}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjuDubj)}(h3``handler`` Flow handler associated with this chip h](j)}(h ``handler``h]j)}(hjDh]hhandler}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjDubj)}(hhh]j)}(h&Flow handler associated with this chiph]h&Flow handler associated with this chip}(hj EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEhMhjEubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjuDubj)}(h*``type`` Chip can handle these flow types h](j)}(h``type``h]j)}(hj)Eh]htype}(hj+EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'Eubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj#Eubj)}(hhh]j)}(h Chip can handle these flow typesh]h Chip can handle these flow types}(hjBEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>EhMhj?Eubah}(h]h ]h"]h$]h&]uh1jhj#Eubeh}(h]h ]h"]h$]h&]uh1jhj>EhMhjuDubj)}(hB``mask_cache_priv`` Cached mask register private to the chip type h](j)}(h``mask_cache_priv``h]j)}(hjbEh]hmask_cache_priv}(hjdEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`Eubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj\Eubj)}(hhh]j)}(h-Cached mask register private to the chip typeh]h-Cached mask register private to the chip type}(hj{EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwEhMhjxEubah}(h]h ]h"]h$]h&]uh1jhj\Eubeh}(h]h ]h"]h$]h&]uh1jhjwEhMhjuDubj)}(h.``mask_cache`` Pointer to cached mask registerh](j)}(h``mask_cache``h]j)}(hjEh]h mask_cache}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjEubj)}(hhh]j)}(hPointer to cached mask registerh]hPointer to cached mask register}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjuDubeh}(h]h ]h"]h$]h&]uh1jhj-Dubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubj)}(h**Description**h]jz)}(hjEh]h Description}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjEubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?3hhubj)}(hA irq_generic_chip can have several instances of irq_chip_type when it requires different functions and register offsets for different flow types.h]hA irq_generic_chip can have several instances of irq_chip_type when it requires different functions and register offsets for different flow types.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?3hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_generic (C struct)c.irq_chip_generichNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_chip_generich]j])}(hstruct irq_chip_generich](j)}(hjh]hstruct}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMubju)}(h h]h }(hj*FhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjFhhhj)FhMubj)}(hirq_chip_generich]j)}(hjFh]hirq_chip_generic}(hjIubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj:Iubj)}(hhh]j)}(h7Number of available irq_chip_type instances (usually 1)h]h7Number of available irq_chip_type instances (usually 1)}(hjYIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUIhMhjVIubah}(h]h ]h"]h$]h&]uh1jhj:Iubeh}(h]h ]h"]h$]h&]uh1jhjUIhMhjFubj)}(h8``private`` Private data for non generic chip callbacks h](j)}(h ``private``h]j)}(hjyIh]hprivate}(hj{IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwIubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjsIubj)}(hhh]j)}(h+Private data for non generic chip callbacksh]h+Private data for non generic chip callbacks}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIhMhjIubah}(h]h ]h"]h$]h&]uh1jhjsIubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjFubj)}(h6``installed`` bitfield to denote installed interrupts h](j)}(h ``installed``h]j)}(hjIh]h installed}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjIubj)}(hhh]j)}(h'bitfield to denote installed interruptsh]h'bitfield to denote installed interrupts}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIhMhjIubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjIhMhjFubj)}(h0``unused`` bitfield to denote unused interrupts h](j)}(h ``unused``h]j)}(hjIh]hunused}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjIubj)}(hhh]j)}(h$bitfield to denote unused interruptsh]h$bitfield to denote unused interrupts}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJhMhjJubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjJhMhjFubj)}(h``domain`` irq domain pointer h](j)}(h ``domain``h]j)}(hj$Jh]hdomain}(hj&JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"Jubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjJubj)}(hhh]j)}(hirq domain pointerh]hirq domain pointer}(hj=JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9JhMhj:Jubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhj9JhMhjFubj)}(h2``list`` List head for keeping track of instances h](j)}(h``list``h]j)}(hj]Jh]hlist}(hj_JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[Jubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjWJubj)}(hhh]j)}(h(List head for keeping track of instancesh]h(List head for keeping track of instances}(hjvJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrJhMhjsJubah}(h]h ]h"]h$]h&]uh1jhjWJubeh}(h]h ]h"]h$]h&]uh1jhjrJhMhjFubj)}(h0``chip_types`` Array of interrupt irq_chip_typesh](j)}(h``chip_types``h]j)}(hjJh]h chip_types}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjJubj)}(hhh]j)}(h!Array of interrupt irq_chip_typesh]h!Array of interrupt irq_chip_types}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhMhjFubeh}(h]h ]h"]h$]h&]uh1jhjzFubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubj)}(h**Description**h]jz)}(hjJh]h Description}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjJubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?3hhubj)}(hX-Note, that irq_chip_generic can have multiple irq_chip_type implementations which can be associated to a particular irq line of an irq_chip_generic instance. That allows to share and protect state in an irq_chip_generic instance when we need to implement different flow mechanisms (level/edge) for it.h]hX-Note, that irq_chip_generic can have multiple irq_chip_type implementations which can be associated to a particular irq line of an irq_chip_generic instance. That allows to share and protect state in an irq_chip_generic instance when we need to implement different flow mechanisms (level/edge) for it.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhj?3hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_gc_flags (C enum)c.irq_gc_flagshNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(h irq_gc_flagsh]j])}(henum irq_gc_flagsh](j)}(hj%h]henum}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjKhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM$ubju)}(h h]h }(hj%KhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjKhhhj$KhM$ubj)}(h irq_gc_flagsh]j)}(hjKh]h irq_gc_flags}(hj7KhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3Kubah}(h]h ](jjeh"]h$]h&]hhuh1jhjKhhhj$KhM$ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjKhhhj$KhM$ubah}(h]j Kah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj$KhM$hj KhhubjI)}(hhh]j)}(h*Initialization flags for generic irq chipsh]h*Initialization flags for generic irq chips}(hjYKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM8hjVKhhubah}(h]h ]h"]h$]h&]uh1jHhj Khhhj$KhM$ubeh}(h]h ](j_ enumeh"]h$]h&]jij_ jjjqKjkjqKjljmjnuh1jQhhhj?3hNhNubjp)}(hX**Constants** ``IRQ_GC_INIT_MASK_CACHE`` Initialize the mask_cache by reading mask reg ``IRQ_GC_INIT_NESTED_LOCK`` Set the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. Usually GPIO implementations ``IRQ_GC_MASK_CACHE_PER_TYPE`` Mask cache is chip type private ``IRQ_GC_NO_MASK`` Do not calculate irq_data->mask ``IRQ_GC_BE_IO`` Use big-endian register accesses (default: LE)h](j)}(h **Constants**h]jz)}(hj{Kh]h Constants}(hj}KhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjyKubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM<hjuKubj)}(hhh](j)}(hI``IRQ_GC_INIT_MASK_CACHE`` Initialize the mask_cache by reading mask reg h](j)}(h``IRQ_GC_INIT_MASK_CACHE``h]j)}(hjKh]hIRQ_GC_INIT_MASK_CACHE}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM?hjKubj)}(hhh]j)}(h-Initialize the mask_cache by reading mask regh]h-Initialize the mask_cache by reading mask reg}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKhM?hjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjKhM?hjKubj)}(h``IRQ_GC_INIT_NESTED_LOCK`` Set the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. Usually GPIO implementations h](j)}(h``IRQ_GC_INIT_NESTED_LOCK``h]j)}(hjKh]hIRQ_GC_INIT_NESTED_LOCK}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMDhjKubj)}(hhh]j)}(hSet the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. Usually GPIO implementationsh]hSet the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. Usually GPIO implementations}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMBhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjKhMDhjKubj)}(h?``IRQ_GC_MASK_CACHE_PER_TYPE`` Mask cache is chip type private h](j)}(h``IRQ_GC_MASK_CACHE_PER_TYPE``h]j)}(hj Lh]hIRQ_GC_MASK_CACHE_PER_TYPE}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Lubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMGhjLubj)}(hhh]j)}(hMask cache is chip type privateh]hMask cache is chip type private}(hj&LhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"LhMGhj#Lubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jhj"LhMGhjKubj)}(h3``IRQ_GC_NO_MASK`` Do not calculate irq_data->mask h](j)}(h``IRQ_GC_NO_MASK``h]j)}(hjFLh]hIRQ_GC_NO_MASK}(hjHLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDLubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMJhj@Lubj)}(hhh]j)}(hDo not calculate irq_data->maskh]hDo not calculate irq_data->mask}(hj_LhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[LhMJhj\Lubah}(h]h ]h"]h$]h&]uh1jhj@Lubeh}(h]h ]h"]h$]h&]uh1jhj[LhMJhjKubj)}(h?``IRQ_GC_BE_IO`` Use big-endian register accesses (default: LE)h](j)}(h``IRQ_GC_BE_IO``h]j)}(hjLh]h IRQ_GC_BE_IO}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}Lubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMLhjyLubj)}(hhh]j)}(h.Use big-endian register accesses (default: LE)h]h.Use big-endian register accesses (default: LE)}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMMhjLubah}(h]h ]h"]h$]h&]uh1jhjyLubeh}(h]h ]h"]h$]h&]uh1jhjLhMLhjKubeh}(h]h ]h"]h$]h&]uh1jhjuKubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM'irq_domain_chip_generic_info (C struct)c.irq_domain_chip_generic_infohNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_domain_chip_generic_infoh]j])}(h#struct irq_domain_chip_generic_infoh](j)}(hjh]hstruct}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMRubju)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLhhhjLhMRubj)}(hirq_domain_chip_generic_infoh]j)}(hjLh]hirq_domain_chip_generic_info}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubah}(h]h ](jjeh"]h$]h&]hhuh1jhjLhhhjLhMRubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjLhhhjLhMRubah}(h]jLah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjLhMRhjLhhubjI)}(hhh]j)}(h"Generic chip information structureh]h"Generic chip information structure}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM^hjMhhubah}(h]h ]h"]h$]h&]uh1jHhjLhhhjLhMRubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjj3Mjkj3Mjljmjnuh1jQhhhj?3hNhNubjp)}(hXn**Definition**:: struct irq_domain_chip_generic_info { const char *name; irq_flow_handler_t handler; unsigned int irqs_per_chip; unsigned int num_ct; unsigned int irq_flags_to_clear; unsigned int irq_flags_to_set; enum irq_gc_flags gc_flags; int (*init)(struct irq_chip_generic *gc); void (*exit)(struct irq_chip_generic *gc); }; **Members** ``name`` Name of the generic interrupt chip ``handler`` Interrupt handler used by the generic interrupt chip ``irqs_per_chip`` Number of interrupts each chip handles (max 32) ``num_ct`` Number of irq_chip_type instances associated with each chip ``irq_flags_to_clear`` IRQ_* bits to clear in the mapping function ``irq_flags_to_set`` IRQ_* bits to set in the mapping function ``gc_flags`` Generic chip specific setup flags ``init`` Function called on each chip when they are created. Allow to do some additional chip initialisation. ``exit`` Function called on each chip when they are destroyed. Allow to do some chip cleanup operation.h](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hj?MhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj;Mubh:}(hj;MhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMbhj7Mubj )}(hXstruct irq_domain_chip_generic_info { const char *name; irq_flow_handler_t handler; unsigned int irqs_per_chip; unsigned int num_ct; unsigned int irq_flags_to_clear; unsigned int irq_flags_to_set; enum irq_gc_flags gc_flags; int (*init)(struct irq_chip_generic *gc); void (*exit)(struct irq_chip_generic *gc); };h]hXstruct irq_domain_chip_generic_info { const char *name; irq_flow_handler_t handler; unsigned int irqs_per_chip; unsigned int num_ct; unsigned int irq_flags_to_clear; unsigned int irq_flags_to_set; enum irq_gc_flags gc_flags; int (*init)(struct irq_chip_generic *gc); void (*exit)(struct irq_chip_generic *gc); };}hjXMsbah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMdhj7Mubj)}(h **Members**h]jz)}(hjiMh]hMembers}(hjkMhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjgMubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMphj7Mubj)}(hhh](j)}(h,``name`` Name of the generic interrupt chip h](j)}(h``name``h]j)}(hjMh]hname}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhM`hjMubj)}(hhh]j)}(h"Name of the generic interrupt chiph]h"Name of the generic interrupt chip}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMhM`hjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjMhM`hjMubj)}(hA``handler`` Interrupt handler used by the generic interrupt chip h](j)}(h ``handler``h]j)}(hjMh]hhandler}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMahjMubj)}(hhh]j)}(h4Interrupt handler used by the generic interrupt chiph]h4Interrupt handler used by the generic interrupt chip}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMhMahjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjMhMahjMubj)}(hB``irqs_per_chip`` Number of interrupts each chip handles (max 32) h](j)}(h``irqs_per_chip``h]j)}(hjMh]h irqs_per_chip}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMbhjMubj)}(hhh]j)}(h/Number of interrupts each chip handles (max 32)h]h/Number of interrupts each chip handles (max 32)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhMbhjNubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjNhMbhjMubj)}(hG``num_ct`` Number of irq_chip_type instances associated with each chip h](j)}(h ``num_ct``h]j)}(hj3Nh]hnum_ct}(hj5NhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1Nubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMdhj-Nubj)}(hhh]j)}(h;Number of irq_chip_type instances associated with each chiph]h;Number of irq_chip_type instances associated with each chip}(hjLNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMchjINubah}(h]h ]h"]h$]h&]uh1jhj-Nubeh}(h]h ]h"]h$]h&]uh1jhjHNhMdhjMubj)}(hC``irq_flags_to_clear`` IRQ_* bits to clear in the mapping function h](j)}(h``irq_flags_to_clear``h]j)}(hjmNh]hirq_flags_to_clear}(hjoNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMehjgNubj)}(hhh]j)}(h+IRQ_* bits to clear in the mapping functionh]h+IRQ_* bits to clear in the mapping function}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhMehjNubah}(h]h ]h"]h$]h&]uh1jhjgNubeh}(h]h ]h"]h$]h&]uh1jhjNhMehjMubj)}(h?``irq_flags_to_set`` IRQ_* bits to set in the mapping function h](j)}(h``irq_flags_to_set``h]j)}(hjNh]hirq_flags_to_set}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMfhjNubj)}(hhh]j)}(h)IRQ_* bits to set in the mapping functionh]h)IRQ_* bits to set in the mapping function}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhMfhjNubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjNhMfhjMubj)}(h/``gc_flags`` Generic chip specific setup flags h](j)}(h ``gc_flags``h]j)}(hjNh]hgc_flags}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMghjNubj)}(hhh]j)}(h!Generic chip specific setup flagsh]h!Generic chip specific setup flags}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhMghjNubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhjNhMghjMubj)}(hn``init`` Function called on each chip when they are created. Allow to do some additional chip initialisation. h](j)}(h``init``h]j)}(hjOh]hinit}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMihjOubj)}(hhh]j)}(hdFunction called on each chip when they are created. Allow to do some additional chip initialisation.h]hdFunction called on each chip when they are created. Allow to do some additional chip initialisation.}(hj1OhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMhhj.Oubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhj-OhMihjMubj)}(hg``exit`` Function called on each chip when they are destroyed. Allow to do some chip cleanup operation.h](j)}(h``exit``h]j)}(hjROh]hexit}(hjTOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPOubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:493: ./include/linux/irq.hhMjhjLOubj)}(hhh]j)}(h^Function called on each chip when they are destroyed. Allow to do some chip cleanup operation.h]h^Function called on each chip when they are destroyed. Allow to do some chip cleanup operation.}(hjkOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgOhMjhjhOubah}(h]h ]h"]h$]h&]uh1jhjLOubeh}(h]h ]h"]h$]h&]uh1jhjgOhMjhjMubeh}(h]h ]h"]h$]h&]uh1jhj7Mubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirqaction (C struct) c.irqactionhNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(h irqactionh]j])}(hstruct irqactionh](j)}(hjh]hstruct}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKubju)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjOhhhjOhKubj)}(h irqactionh]j)}(hjOh]h irqaction}(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ](jjeh"]h$]h&]hhuh1jhjOhhhjOhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjOhhhjOhKubah}(h]jOah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjOhKhjOhhubjI)}(hhh]j)}(hper interrupt action descriptorh]hper interrupt action descriptor}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKkhjOhhubah}(h]h ]h"]h$]h&]uh1jHhjOhhhjOhKubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjjPjkjPjljmjnuh1jQhhhj?3hNhNubjp)}(hX8**Definition**:: struct irqaction { irq_handler_t handler; union { void *dev_id; void __percpu *percpu_dev_id; }; const struct cpumask *affinity; struct irqaction *next; irq_handler_t thread_fn; struct task_struct *thread; struct irqaction *secondary; unsigned int irq; unsigned int flags; unsigned long thread_flags; unsigned long thread_mask; const char *name; struct proc_dir_entry *dir; }; **Members** ``handler`` interrupt handler function ``{unnamed_union}`` anonymous ``dev_id`` cookie to identify the device ``percpu_dev_id`` cookie to identify the device ``affinity`` CPUs this irqaction is allowed to run on ``next`` pointer to the next irqaction for shared interrupts ``thread_fn`` interrupt handler function for threaded interrupts ``thread`` thread pointer for threaded interrupts ``secondary`` pointer to secondary irqaction (force threading) ``irq`` interrupt number ``flags`` flags (see IRQF_* above) ``thread_flags`` flags related to **thread** ``thread_mask`` bitmask for keeping track of **thread** activity ``name`` name of the device ``dir`` pointer to the proc/irq/NN/name entryh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj Pubh:}(hj PhhhNhNubeh}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKohj Pubj )}(hXstruct irqaction { irq_handler_t handler; union { void *dev_id; void __percpu *percpu_dev_id; }; const struct cpumask *affinity; struct irqaction *next; irq_handler_t thread_fn; struct task_struct *thread; struct irqaction *secondary; unsigned int irq; unsigned int flags; unsigned long thread_flags; unsigned long thread_mask; const char *name; struct proc_dir_entry *dir; };h]hXstruct irqaction { irq_handler_t handler; union { void *dev_id; void __percpu *percpu_dev_id; }; const struct cpumask *affinity; struct irqaction *next; irq_handler_t thread_fn; struct task_struct *thread; struct irqaction *secondary; unsigned int irq; unsigned int flags; unsigned long thread_flags; unsigned long thread_mask; const char *name; struct proc_dir_entry *dir; };}hj*Psbah}(h]h ]h"]h$]h&]hhuh1j h^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKqhj Pubj)}(h **Members**h]jz)}(hj;Ph]hMembers}(hj=PhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj9Pubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKhj Pubj)}(hhh](j)}(h'``handler`` interrupt handler function h](j)}(h ``handler``h]j)}(hjZPh]hhandler}(hj\PhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXPubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKmhjTPubj)}(hhh]j)}(hinterrupt handler functionh]hinterrupt handler function}(hjsPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoPhKmhjpPubah}(h]h ]h"]h$]h&]uh1jhjTPubeh}(h]h ]h"]h$]h&]uh1jhjoPhKmhjQPubj)}(h``{unnamed_union}`` anonymous h](j)}(h``{unnamed_union}``h]j)}(hjPh]h{unnamed_union}}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKhjPubj)}(hhh]j)}(h anonymoush]h anonymous}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPhKhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjPhKhjQPubj)}(h)``dev_id`` cookie to identify the device h](j)}(h ``dev_id``h]j)}(hjPh]hdev_id}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKohjPubj)}(hhh]j)}(hcookie to identify the deviceh]hcookie to identify the device}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjPhKohjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjPhKohjQPubj)}(h0``percpu_dev_id`` cookie to identify the device h](j)}(h``percpu_dev_id``h]j)}(hjQh]h percpu_dev_id}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhKphjPubj)}(hhh]j)}(hcookie to identify the deviceh]hcookie to identify the device}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQhKphjQubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjQhKphjQPubj)}(h6``affinity`` CPUs this irqaction is allowed to run on h](j)}(h ``affinity``h]j)}(hj>Qh]haffinity}(hj@QhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCallback for calculating the number and size of interrupt setsh]h>Callback for calculating the number and size of interrupt sets}(hj2[hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM#hj/[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhj.[hM$hjZubj)}(hc``priv`` Private data for usage by **calc_sets**, usually a pointer to driver/device specific data.h](j)}(h``priv``h]j)}(hjS[h]hpriv}(hjU[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ[ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM%hjM[ubj)}(hhh]j)}(hZPrivate data for usage by **calc_sets**, usually a pointer to driver/device specific data.h](hPrivate data for usage by }(hjl[hhhNhNubjz)}(h **calc_sets**h]h calc_sets}(hjt[hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjl[ubh3, usually a pointer to driver/device specific data.}(hjl[hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhjh[hM%hji[ubah}(h]h ]h"]h$]h&]uh1jhjM[ubeh}(h]h ]h"]h$]h&]uh1jhjh[hM%hjZubeh}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_affinity_desc (C struct)c.irq_affinity_deschNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hirq_affinity_desch]j])}(hstruct irq_affinity_desch](j)}(hjh]hstruct}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM,ubju)}(h h]h }(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[hhhj[hM,ubj)}(hirq_affinity_desch]j)}(hj[h]hirq_affinity_desc}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj[hhhj[hM,ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj[hhhj[hM,ubah}(h]j[ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj[hM,hj[hhubjI)}(hhh]j)}(hInterrupt affinity descriptorh]hInterrupt affinity descriptor}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM1hj[hhubah}(h]h ]h"]h$]h&]uh1jHhj[hhhj[hM,ubeh}(h]h ](j_ structeh"]h$]h&]jij_ jjj\jkj\jljmjnuh1jQhhhj?3hNhNubjp)}(h**Definition**:: struct irq_affinity_desc { struct cpumask mask; unsigned int is_managed : 1; }; **Members** ``mask`` cpumask to hold the affinity assignment ``is_managed`` 1 if the interrupt is managed internallyh](j)}(h**Definition**::h](jz)}(h**Definition**h]h Definition}(hj$\hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj \ubh:}(hj \hhhNhNubeh}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM5hj\ubj )}(h[struct irq_affinity_desc { struct cpumask mask; unsigned int is_managed : 1; };h]h[struct irq_affinity_desc { struct cpumask mask; unsigned int is_managed : 1; };}hj=\sbah}(h]h ]h"]h$]h&]hhuh1j h^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM7hj\ubj)}(h **Members**h]jz)}(hjN\h]hMembers}(hjP\hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjL\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM<hj\ubj)}(hhh](j)}(h1``mask`` cpumask to hold the affinity assignment h](j)}(h``mask``h]j)}(hjm\h]hmask}(hjo\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM3hjg\ubj)}(hhh]j)}(h'cpumask to hold the affinity assignmenth]h'cpumask to hold the affinity assignment}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\hM3hj\ubah}(h]h ]h"]h$]h&]uh1jhjg\ubeh}(h]h ]h"]h$]h&]uh1jhj\hM3hjd\ubj)}(h7``is_managed`` 1 if the interrupt is managed internallyh](j)}(h``is_managed``h]j)}(hj\h]h is_managed}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM3hj\ubj)}(hhh]j)}(h(1 if the interrupt is managed internallyh]h(1 if the interrupt is managed internally}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhM4hj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jhj\hM3hjd\ubeh}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_update_affinity_hint (C function)c.irq_update_affinity_hinthNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hHint irq_update_affinity_hint (unsigned int irq, const struct cpumask *m)h]j])}(hGint irq_update_affinity_hint(unsigned int irq, const struct cpumask *m)h](jc)}(hinth]hint}(hj]hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMHubju)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\hhhj]hMHubj)}(hirq_update_affinity_hinth]j)}(hirq_update_affinity_hinth]hirq_update_affinity_hint}(hj!]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj\hhhj]hMHubj)}(h+(unsigned int irq, const struct cpumask *m)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hj=]hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj9]ubju)}(h h]h }(hjK]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj9]ubjc)}(hinth]hint}(hjY]hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj9]ubju)}(h h]h }(hjg]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj9]ubj)}(hirqh]hirq}(hju]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj9]ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj5]ubj)}(hconst struct cpumask *mh](j)}(hjh]hconst}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubju)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]ubj)}(hjh]hstruct}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubju)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]ubh)}(hhh]j)}(hcpumaskh]hcpumask}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj]modnameN classnameNjj)}j]j)}jj#]sbc.irq_update_affinity_hintasbuh1hhj]ubju)}(h h]h }(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]ubj )}(hj h]h*}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubj)}(hmh]hm}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj5]ubeh}(h]h ]h"]h$]h&]hhuh1jhj\hhhj]hMHubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj\hhhj]hMHubah}(h]j\ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj]hMHhj\hhubjI)}(hhh]j)}(hUpdate the affinity hinth]hUpdate the affinity hint}(hj,^hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMHhj)^hhubah}(h]h ]h"]h$]h&]uh1jHhj\hhhj]hMHubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjD^jkjD^jljmjnuh1jQhhhj?3hNhNubjp)}(h**Parameters** ``unsigned int irq`` Interrupt to update ``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) **Description** Updates the affinity hint, but does not change the affinity of the interrupt.h](j)}(h**Parameters**h]jz)}(hjN^h]h Parameters}(hjP^hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjL^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMLhjH^ubj)}(hhh](j)}(h)``unsigned int irq`` Interrupt to update h](j)}(h``unsigned int irq``h]j)}(hjm^h]hunsigned int irq}(hjo^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMIhjg^ubj)}(hhh]j)}(hInterrupt to updateh]hInterrupt to update}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^hMIhj^ubah}(h]h ]h"]h$]h&]uh1jhjg^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMIhjd^ubj)}(hE``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) h](j)}(h``const struct cpumask *m``h]j)}(hj^h]hconst struct cpumask *m}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMJhj^ubj)}(hhh]j)}(h(cpumask pointer (NULL to clear the hint)h]h(cpumask pointer (NULL to clear the hint)}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^hMJhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jhj^hMJhjd^ubeh}(h]h ]h"]h$]h&]uh1jhjH^ubj)}(h**Description**h]jz)}(hj^h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj^ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMLhjH^ubj)}(hMUpdates the affinity hint, but does not change the affinity of the interrupt.h]hMUpdates the affinity hint, but does not change the affinity of the interrupt.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMKhjH^ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&irq_set_affinity_and_hint (C function)c.irq_set_affinity_and_hinthNtauh1j@hj?3hhhNhNubjR)}(hhh](jW)}(hIint irq_set_affinity_and_hint (unsigned int irq, const struct cpumask *m)h]j])}(hHint irq_set_affinity_and_hint(unsigned int irq, const struct cpumask *m)h](jc)}(hinth]hint}(hj&_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj"_hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMUubju)}(h h]h }(hj5_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj"_hhhj4_hMUubj)}(hirq_set_affinity_and_hinth]j)}(hirq_set_affinity_and_hinth]hirq_set_affinity_and_hint}(hjG_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjC_ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj"_hhhj4_hMUubj)}(h+(unsigned int irq, const struct cpumask *m)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjc_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj__ubju)}(h h]h }(hjq_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj__ubjc)}(hinth]hint}(hj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj__ubju)}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj__ubj)}(hirqh]hirq}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj__ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj[_ubj)}(hconst struct cpumask *mh](j)}(hjh]hconst}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubju)}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubj)}(hjh]hstruct}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubju)}(h h]h }(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubh)}(hhh]j)}(hcpumaskh]hcpumask}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj_modnameN classnameNjj)}j]j)}jjI_sbc.irq_set_affinity_and_hintasbuh1hhj_ubju)}(h h]h }(hj `hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubj )}(hj h]h*}(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(hj^h]hm}(hj(`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj[_ubeh}(h]h ]h"]h$]h&]hhuh1jhj"_hhhj4_hMUubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj_hhhj4_hMUubah}(h]j_ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj4_hMUhj_hhubjI)}(hhh]j)}(hHUpdate the affinity hint and apply the provided cpumask to the interrupth]hHUpdate the affinity hint and apply the provided cpumask to the interrupt}(hjQ`hhhNhNubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMUhjN`hhubah}(h]h ]h"]h$]h&]uh1jHhj_hhhj4_hMUubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjji`jkji`jljmjnuh1jQhhhj?3hNhNubjp)}(h**Parameters** ``unsigned int irq`` Interrupt to update ``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) **Description** Updates the affinity hint and if **m** is not NULL it applies it as the affinity of that interrupt.h](j)}(h**Parameters**h]jz)}(hjs`h]h Parameters}(hju`hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjq`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMYhjm`ubj)}(hhh](j)}(h)``unsigned int irq`` Interrupt to update h](j)}(h``unsigned int irq``h]j)}(hj`h]hunsigned int irq}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMWhj`ubj)}(hhh]j)}(hInterrupt to updateh]hInterrupt to update}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`hMWhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMWhj`ubj)}(hE``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) h](j)}(h``const struct cpumask *m``h]j)}(hj`h]hconst struct cpumask *m}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMXhj`ubj)}(hhh]j)}(h(cpumask pointer (NULL to clear the hint)h]h(cpumask pointer (NULL to clear the hint)}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`hMXhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj`hMXhj`ubeh}(h]h ]h"]h$]h&]uh1jhjm`ubj)}(h**Description**h]jz)}(hjah]h Description}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjaubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMZhjm`ubj)}(hcUpdates the affinity hint and if **m** is not NULL it applies it as the affinity of that interrupt.h](h!Updates the affinity hint and if }(hjahhhNhNubjz)}(h**m**h]hm}(hj$ahhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjaubh= is not NULL it applies it as the affinity of that interrupt.}(hjahhhNhNubeh}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:496: ./include/linux/interrupt.hhMYhjm`ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj?3hhhNhNubeh}(h] structuresah ]h"] structuresah$]h&]uh1jLhjNhhhjahMubjM)}(hhh](jR)}(hPublic Functions Providedh]hPublic Functions Provided}(hjOahhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjLahhhjahMubj)}(heThis chapter contains the autogenerated documentation of the kernel API functions which are exported.h]heThis chapter contains the autogenerated documentation of the kernel API functions which are exported.}(hj]ahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhjLahhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM synchronize_hardirq (C function)c.synchronize_hardirqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h+bool synchronize_hardirq (unsigned int irq)h]j])}(h*bool synchronize_hardirq(unsigned int irq)h](jc)}(hboolh]hbool}(hjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjahhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKUubju)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjahhhjahKUubj)}(hsynchronize_hardirqh]j)}(hsynchronize_hardirqh]hsynchronize_hardirq}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubah}(h]h ](jjeh"]h$]h&]hhuh1jhjahhhjahKUubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjaubju)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubjc)}(hinth]hint}(hjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjaubju)}(h h]h }(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubj)}(hirqh]hirq}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjaubah}(h]h ]h"]h$]h&]hhuh1jhjahhhjahKUubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj|ahhhjahKUubah}(h]jwaah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjahKUhjyahhubjI)}(hhh]j)}(h2wait for pending hard IRQ handlers (on other CPUs)h]h2wait for pending hard IRQ handlers (on other CPUs)}(hj#bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKUhj bhhubah}(h]h ]h"]h$]h&]uh1jHhjyahhhjahKUubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj;bjkj;bjljmjnuh1jQhhhjLahNhNubjp)}(hX!**Parameters** ``unsigned int irq`` interrupt number to wait for **Description** This function waits for any pending hard IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. It does not take associated threaded handlers into account. Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed. This function may be called - with care - from IRQ context. It does not check whether there is an interrupt in flight at the hardware level, but not serviced yet, as this might deadlock when called with interrupts disabled and the target CPU of the interrupt is the current CPU. **Return** false if a threaded handler is active.h](j)}(h**Parameters**h]jz)}(hjEbh]h Parameters}(hjGbhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjCbubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKYhj?bubj)}(hhh]j)}(h2``unsigned int irq`` interrupt number to wait for h](j)}(h``unsigned int irq``h]j)}(hjdbh]hunsigned int irq}(hjfbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbbubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKVhj^bubj)}(hhh]j)}(hinterrupt number to wait forh]hinterrupt number to wait for}(hj}bhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjybhKVhjzbubah}(h]h ]h"]h$]h&]uh1jhj^bubeh}(h]h ]h"]h$]h&]uh1jhjybhKVhj[bubah}(h]h ]h"]h$]h&]uh1jhj?bubj)}(h**Description**h]jz)}(hjbh]h Description}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjbubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKXhj?bubj)}(hXThis function waits for any pending hard IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. It does not take associated threaded handlers into account.h]hXThis function waits for any pending hard IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. It does not take associated threaded handlers into account.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKWhj?bubj)}(h{Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed.h]h{Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chK\hj?bubj)}(h;This function may be called - with care - from IRQ context.h]h;This function may be called - with care - from IRQ context.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chK`hj?bubj)}(hIt does not check whether there is an interrupt in flight at the hardware level, but not serviced yet, as this might deadlock when called with interrupts disabled and the target CPU of the interrupt is the current CPU.h]hIt does not check whether there is an interrupt in flight at the hardware level, but not serviced yet, as this might deadlock when called with interrupts disabled and the target CPU of the interrupt is the current CPU.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKbhj?bubj)}(h **Return**h]jz)}(hjbh]hReturn}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjbubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKghj?bubj)}(h&false if a threaded handler is active.h]h&false if a threaded handler is active.}(hj chhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chK`hj?bubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMsynchronize_irq (C function)c.synchronize_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h'void synchronize_irq (unsigned int irq)h]j])}(h&void synchronize_irq(unsigned int irq)h](jc)}(hvoidh]hvoid}(hj8chhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj4chhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKubju)}(h h]h }(hjGchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj4chhhjFchKubj)}(hsynchronize_irqh]j)}(hsynchronize_irqh]hsynchronize_irq}(hjYchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUcubah}(h]h ](jjeh"]h$]h&]hhuh1jhj4chhhjFchKubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjuchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjqcubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjqcubjc)}(hinth]hint}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjqcubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjqcubj)}(hirqh]hirq}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqcubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjmcubah}(h]h ]h"]h$]h&]hhuh1jhj4chhhjFchKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj0chhhjFchKubah}(h]j+cah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjFchKhj-chhubjI)}(hhh]j)}(h-wait for pending IRQ handlers (on other CPUs)h]h-wait for pending IRQ handlers (on other CPUs)}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjchhubah}(h]h ]h"]h$]h&]uh1jHhj-chhhjFchKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjcjkjcjljmjnuh1jQhhhjLahNhNubjp)}(hX **Parameters** ``unsigned int irq`` interrupt number to wait for **Description** This function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. Can only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**. It optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.h](j)}(h**Parameters**h]jz)}(hjch]h Parameters}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjcubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjcubj)}(hhh]j)}(h2``unsigned int irq`` interrupt number to wait for h](j)}(h``unsigned int irq``h]j)}(hjdh]hunsigned int irq}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjdubj)}(hhh]j)}(hinterrupt number to wait forh]hinterrupt number to wait for}(hj1dhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-dhKhj.dubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhj-dhKhjdubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(h**Description**h]jz)}(hjSdh]h Description}(hjUdhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjQdubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjcubj)}(hThis function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock.h]hThis function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock.}(hjidhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjcubj)}(hmCan only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**.h](heCan only be called from preemptible code as it might sleep when an interrupt thread is associated to }(hjxdhhhNhNubjz)}(h**irq**h]hirq}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjxdubh.}(hjxdhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjcubj)}(hIt optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.h]hIt optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjcubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_can_set_affinity (C function)c.irq_can_set_affinityhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h+int irq_can_set_affinity (unsigned int irq)h]j])}(h*int irq_can_set_affinity(unsigned int irq)h](jc)}(hinth]hint}(hjdhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjdhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKubju)}(h h]h }(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdhhhjdhKubj)}(hirq_can_set_affinityh]j)}(hirq_can_set_affinityh]hirq_can_set_affinity}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjdhKubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjehhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjeubju)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjeubjc)}(hinth]hint}(hj!ehhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjeubju)}(h h]h }(hj/ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjeubj)}(hirqh]hirq}(hj=ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjdubah}(h]h ]h"]h$]h&]hhuh1jhjdhhhjdhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjdhhhjdhKubah}(h]jdah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjdhKhjdhhubjI)}(hhh]j)}(h/Check if the affinity of a given irq can be seth]h/Check if the affinity of a given irq can be set}(hjgehhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjdehhubah}(h]h ]h"]h$]h&]uh1jHhjdhhhjdhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjejkjejljmjnuh1jQhhhjLahNhNubjp)}(h9**Parameters** ``unsigned int irq`` Interrupt to checkh](j)}(h**Parameters**h]jz)}(hjeh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjeubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjeubj)}(hhh]j)}(h'``unsigned int irq`` Interrupt to checkh](j)}(h``unsigned int irq``h]j)}(hjeh]hunsigned int irq}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjeubj)}(hhh]j)}(hInterrupt to checkh]hInterrupt to check}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jhjehKhjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_can_set_affinity_usr (C function)c.irq_can_set_affinity_usrhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h0bool irq_can_set_affinity_usr (unsigned int irq)h]j])}(h/bool irq_can_set_affinity_usr(unsigned int irq)h](jc)}(hjah]hbool}(hjfhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjehhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKubju)}(h h]h }(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjehhhjfhKubj)}(hirq_can_set_affinity_usrh]j)}(hirq_can_set_affinity_usrh]hirq_can_set_affinity_usr}(hj"fhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubah}(h]h ](jjeh"]h$]h&]hhuh1jhjehhhjfhKubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hj>fhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj:fubju)}(h h]h }(hjLfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj:fubjc)}(hinth]hint}(hjZfhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj:fubju)}(h h]h }(hjhfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj:fubj)}(hirqh]hirq}(hjvfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:fubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj6fubah}(h]h ]h"]h$]h&]hhuh1jhjehhhjfhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjehhhjfhKubah}(h]jeah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjfhKhjehhubjI)}(hhh]j)}(h5Check if affinity of a irq can be set from user spaceh]h5Check if affinity of a irq can be set from user space}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjfhhubah}(h]h ]h"]h$]h&]uh1jHhjehhhjfhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjfjkjfjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``unsigned int irq`` Interrupt to check **Description** Like irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.h](j)}(h**Parameters**h]jz)}(hjfh]h Parameters}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjfubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjfubj)}(hhh]j)}(h(``unsigned int irq`` Interrupt to check h](j)}(h``unsigned int irq``h]j)}(hjfh]hunsigned int irq}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjfubj)}(hhh]j)}(hInterrupt to checkh]hInterrupt to check}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfhKhjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jhjfhKhjfubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(h**Description**h]jz)}(hjgh]h Description}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjgubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjfubj)}(hYLike irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.h]hYLike irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.}(hj2ghhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjfubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_set_thread_affinity (C function)c.irq_set_thread_affinityhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h4void irq_set_thread_affinity (struct irq_desc *desc)h]j])}(h3void irq_set_thread_affinity(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjaghhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj]ghhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKubju)}(h h]h }(hjpghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]ghhhjoghKubj)}(hirq_set_thread_affinityh]j)}(hirq_set_thread_affinityh]hirq_set_thread_affinity}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~gubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]ghhhjoghKubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubju)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjgubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjgmodnameN classnameNjj)}j]j)}jjgsbc.irq_set_thread_affinityasbuh1hhjgubju)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjgubj )}(hj h]h*}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubj)}(hdesch]hdesc}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjgubah}(h]h ]h"]h$]h&]hhuh1jhj]ghhhjoghKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjYghhhjoghKubah}(h]jTgah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjoghKhjVghhubjI)}(hhh]j)}(h%Notify irq threads to adjust affinityh]h%Notify irq threads to adjust affinity}(hj!hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhjhhhubah}(h]h ]h"]h$]h&]uh1jHhjVghhhjoghKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj9hjkj9hjljmjnuh1jQhhhjLahNhNubjp)}(hX<**Parameters** ``struct irq_desc *desc`` irq descriptor which has affinity changed **Description** Just set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.h](j)}(h**Parameters**h]jz)}(hjChh]h Parameters}(hjEhhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjAhubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhj=hubj)}(hhh]j)}(hD``struct irq_desc *desc`` irq descriptor which has affinity changed h](j)}(h``struct irq_desc *desc``h]j)}(hjbhh]hstruct irq_desc *desc}(hjdhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`hubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhj\hubj)}(hhh]j)}(h)irq descriptor which has affinity changedh]h)irq descriptor which has affinity changed}(hj{hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwhhKhjxhubah}(h]h ]h"]h$]h&]uh1jhj\hubeh}(h]h ]h"]h$]h&]uh1jhjwhhKhjYhubah}(h]h ]h"]h$]h&]uh1jhj=hubj)}(h**Description**h]jz)}(hjhh]h Description}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjhubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhj=hubj)}(hJust set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.h]hJust set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chKhj=hubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM.irq_affinity_schedule_notify_work (C function)#c.irq_affinity_schedule_notify_workhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h>void irq_affinity_schedule_notify_work (struct irq_desc *desc)h]j])}(h=void irq_affinity_schedule_notify_work(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMjubju)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhhjhhMjubj)}(h!irq_affinity_schedule_notify_workh]j)}(h!irq_affinity_schedule_notify_workh]h!irq_affinity_schedule_notify_work}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhjhhMjubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubju)}(h h]h }(hj,ihhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjiubh)}(hhh]j)}(hirq_desch]hirq_desc}(hj=ihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:iubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj?imodnameN classnameNjj)}j]j)}jjisb#c.irq_affinity_schedule_notify_workasbuh1hhjiubju)}(h h]h }(hj]ihhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjiubj )}(hj h]h*}(hjkihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubj)}(hdesch]hdesc}(hjxihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjiubah}(h]h ]h"]h$]h&]hhuh1jhjhhhhjhhMjubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhhjhhMjubah}(h]jhah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhhMjhjhhhubjI)}(hhh]j)}(h-Schedule work to notify about affinity changeh]h-Schedule work to notify about affinity change}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMjhjihhubah}(h]h ]h"]h$]h&]uh1jHhjhhhhjhhMjubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjijkjijljmjnuh1jQhhhjLahNhNubjp)}(hW**Parameters** ``struct irq_desc *desc`` Interrupt descriptor whose affinity changedh](j)}(h**Parameters**h]jz)}(hjih]h Parameters}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjiubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMnhjiubj)}(hhh]j)}(hE``struct irq_desc *desc`` Interrupt descriptor whose affinity changedh](j)}(h``struct irq_desc *desc``h]j)}(hjih]hstruct irq_desc *desc}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjiubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMphjiubj)}(hhh]j)}(h+Interrupt descriptor whose affinity changedh]h+Interrupt descriptor whose affinity changed}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMkhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjihMphjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_update_affinity_desc (C function)c.irq_update_affinity_deschNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hSint irq_update_affinity_desc (unsigned int irq, struct irq_affinity_desc *affinity)h]j])}(hRint irq_update_affinity_desc(unsigned int irq, struct irq_affinity_desc *affinity)h](jc)}(hinth]hint}(hj=jhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj9jhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjLjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj9jhhhjKjhMubj)}(hirq_update_affinity_desch]j)}(hirq_update_affinity_desch]hirq_update_affinity_desc}(hj^jhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj9jhhhjKjhMubj)}(h6(unsigned int irq, struct irq_affinity_desc *affinity)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjzjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvjubju)}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvjubjc)}(hinth]hint}(hjjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvjubju)}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvjubj)}(hirqh]hirq}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjrjubj)}(h"struct irq_affinity_desc *affinityh](j)}(hjh]hstruct}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubju)}(h h]h }(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjjubh)}(hhh]j)}(hirq_affinity_desch]hirq_affinity_desc}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjjmodnameN classnameNjj)}j]j)}jj`jsbc.irq_update_affinity_descasbuh1hhjjubju)}(h h]h }(hj khhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjjubj )}(hj h]h*}(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubj)}(haffinityh]haffinity}(hj$khhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjrjubeh}(h]h ]h"]h$]h&]hhuh1jhj9jhhhjKjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj5jhhhjKjhMubah}(h]j0jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjKjhMhj2jhhubjI)}(hhh]j)}(h+Update affinity management for an interrupth]h+Update affinity management for an interrupt}(hjNkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjKkhhubah}(h]h ]h"]h$]h&]uh1jHhj2jhhhjKjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjfkjkjfkjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` The interrupt number to update ``struct irq_affinity_desc *affinity`` Pointer to the affinity descriptor **Description** This interface can be used to configure the affinity management of interrupts which have been allocated already. There are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.h](j)}(h**Parameters**h]jz)}(hjpkh]h Parameters}(hjrkhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjnkubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjjkubj)}(hhh](j)}(h4``unsigned int irq`` The interrupt number to update h](j)}(h``unsigned int irq``h]j)}(hjkh]hunsigned int irq}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjkubj)}(hhh]j)}(hThe interrupt number to updateh]hThe interrupt number to update}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkhMhjkubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjkubj)}(hJ``struct irq_affinity_desc *affinity`` Pointer to the affinity descriptor h](j)}(h&``struct irq_affinity_desc *affinity``h]j)}(hjkh]h"struct irq_affinity_desc *affinity}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjkubj)}(hhh]j)}(h"Pointer to the affinity descriptorh]h"Pointer to the affinity descriptor}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkhMhjkubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjkubeh}(h]h ]h"]h$]h&]uh1jhjjkubj)}(h**Description**h]jz)}(hjlh]h Description}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjlubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjjkubj)}(hpThis interface can be used to configure the affinity management of interrupts which have been allocated already.h]hpThis interface can be used to configure the affinity management of interrupts which have been allocated already.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjjkubj)}(hXThere are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.h]hXThere are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.}(hj(lhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjjkubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_affinity (C function)c.irq_set_affinityhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hFint irq_set_affinity (unsigned int irq, const struct cpumask *cpumask)h]j])}(hEint irq_set_affinity(unsigned int irq, const struct cpumask *cpumask)h](jc)}(hinth]hint}(hjWlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjSlhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjflhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjSlhhhjelhMubj)}(hirq_set_affinityh]j)}(hirq_set_affinityh]hirq_set_affinity}(hjxlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtlubah}(h]h ](jjeh"]h$]h&]hhuh1jhjSlhhhjelhMubj)}(h1(unsigned int irq, const struct cpumask *cpumask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjlubju)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubjc)}(hinth]hint}(hjlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjlubju)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubj)}(hirqh]hirq}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjlubj)}(hconst struct cpumask *cpumaskh](j)}(hjh]hconst}(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubju)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubj)}(hjh]hstruct}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubju)}(h h]h }(hj mhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubh)}(hhh]j)}(hcpumaskh]hcpumask}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj mmodnameN classnameNjj)}j]j)}jjzlsbc.irq_set_affinityasbuh1hhjlubju)}(h h]h }(hj>mhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubj )}(hj h]h*}(hjLmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj)}(hcpumaskh]hcpumask}(hjYmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjlubeh}(h]h ]h"]h$]h&]hhuh1jhjSlhhhjelhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjOlhhhjelhMubah}(h]jJlah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjelhMhjLlhhubjI)}(hhh]j)}(h#Set the irq affinity of a given irqh]h#Set the irq affinity of a given irq}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmhhubah}(h]h ]h"]h$]h&]uh1jHhjLlhhhjelhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjmjkjmjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``unsigned int irq`` Interrupt to set affinity ``const struct cpumask *cpumask`` cpumask **Description** Fails if cpumask does not contain an online CPUh](j)}(h**Parameters**h]jz)}(hjmh]h Parameters}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjmubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubj)}(hhh](j)}(h/``unsigned int irq`` Interrupt to set affinity h](j)}(h``unsigned int irq``h]j)}(hjmh]hunsigned int irq}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubj)}(hhh]j)}(hInterrupt to set affinityh]hInterrupt to set affinity}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmhMhjmubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjmhMhjmubj)}(h*``const struct cpumask *cpumask`` cpumask h](j)}(h!``const struct cpumask *cpumask``h]j)}(hjmh]hconst struct cpumask *cpumask}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubj)}(hhh]j)}(hcpumaskh]hcpumask}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnhMhjnubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjnhMhjmubeh}(h]h ]h"]h$]h&]uh1jhjmubj)}(h**Description**h]jz)}(hj8nh]h Description}(hj:nhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj6nubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubj)}(h/Fails if cpumask does not contain an online CPUh]h/Fails if cpumask does not contain an online CPU}(hjNnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_force_affinity (C function)c.irq_force_affinityhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hHint irq_force_affinity (unsigned int irq, const struct cpumask *cpumask)h]j])}(hGint irq_force_affinity(unsigned int irq, const struct cpumask *cpumask)h](jc)}(hinth]hint}(hj}nhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjynhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjynhhhjnhMubj)}(hirq_force_affinityh]j)}(hirq_force_affinityh]hirq_force_affinity}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubah}(h]h ](jjeh"]h$]h&]hhuh1jhjynhhhjnhMubj)}(h1(unsigned int irq, const struct cpumask *cpumask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjnhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjnubju)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjnubjc)}(hinth]hint}(hjnhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjnubju)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjnubj)}(hirqh]hirq}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjnubj)}(hconst struct cpumask *cpumaskh](j)}(hjh]hconst}(hj ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubju)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjoubj)}(hjh]hstruct}(hj&ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubju)}(h h]h }(hj3ohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjoubh)}(hhh]j)}(hcpumaskh]hcpumask}(hjDohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAoubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjFomodnameN classnameNjj)}j]j)}jjnsbc.irq_force_affinityasbuh1hhjoubju)}(h h]h }(hjdohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjoubj )}(hj h]h*}(hjrohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubj)}(hcpumaskh]hcpumask}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjnubeh}(h]h ]h"]h$]h&]hhuh1jhjynhhhjnhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjunhhhjnhMubah}(h]jpnah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjnhMhjrnhhubjI)}(hhh]j)}(h%Force the irq affinity of a given irqh]h%Force the irq affinity of a given irq}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjohhubah}(h]h ]h"]h$]h&]uh1jHhjrnhhhjnhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjojkjojljmjnuh1jQhhhjLahNhNubjp)}(hXC**Parameters** ``unsigned int irq`` Interrupt to set affinity ``const struct cpumask *cpumask`` cpumask **Description** Same as irq_set_affinity, but without checking the mask against online cpus. Solely for low level cpu hotplug code, where we need to make per cpu interrupts affine before the cpu becomes online.h](j)}(h**Parameters**h]jz)}(hjoh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjoubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjoubj)}(hhh](j)}(h/``unsigned int irq`` Interrupt to set affinity h](j)}(h``unsigned int irq``h]j)}(hjoh]hunsigned int irq}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjoubj)}(hhh]j)}(hInterrupt to set affinityh]hInterrupt to set affinity}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjohMhjpubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjohMhjoubj)}(h*``const struct cpumask *cpumask`` cpumask h](j)}(h!``const struct cpumask *cpumask``h]j)}(hj#ph]hconst struct cpumask *cpumask}(hj%phhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!pubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjpubj)}(hhh]j)}(hcpumaskh]hcpumask}(hj IOMMU -> irq_set_vcpu_affinity().h](j)}(h**Parameters**h]jz)}(hjsh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjsubj)}(hhh](j)}(h6``unsigned int irq`` interrupt number to set affinity h](j)}(h``unsigned int irq``h]j)}(hjsh]hunsigned int irq}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjsubj)}(hhh]j)}(h interrupt number to set affinityh]h interrupt number to set affinity}(hj thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjthMhjtubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjthMhjsubj)}(hv``void *vcpu_info`` vCPU specific data or pointer to a percpu array of vCPU specific data for percpu_devid interrupts h](j)}(h``void *vcpu_info``h]j)}(hj+th]hvoid *vcpu_info}(hj-thhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)tubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj%tubj)}(hhh]j)}(havCPU specific data or pointer to a percpu array of vCPU specific data for percpu_devid interruptsh]havCPU specific data or pointer to a percpu array of vCPU specific data for percpu_devid interrupts}(hjDthhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjAtubah}(h]h ]h"]h$]h&]uh1jhj%tubeh}(h]h ]h"]h$]h&]uh1jhj@thMhjsubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(h**Description**h]jz)}(hjgth]h Description}(hjithhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjetubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjsubj)}(hThis function uses the vCPU specific data to set the vCPU affinity for an irq. The vCPU specific data is passed from outside, such as KVM. One example code path is as below: KVM -> IOMMU -> irq_set_vcpu_affinity().h]hThis function uses the vCPU specific data to set the vCPU affinity for an irq. The vCPU specific data is passed from outside, such as KVM. One example code path is as below: KVM -> IOMMU -> irq_set_vcpu_affinity().}(hj}thhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjsubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMdisable_irq_nosync (C function)c.disable_irq_nosynchNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h*void disable_irq_nosync (unsigned int irq)h]j])}(h)void disable_irq_nosync(unsigned int irq)h](jc)}(hvoidh]hvoid}(hjthhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjthhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjthhhjthMubj)}(hdisable_irq_nosynch]j)}(hdisable_irq_nosynch]hdisable_irq_nosync}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubah}(h]h ](jjeh"]h$]h&]hhuh1jhjthhhjthMubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjthhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjtubju)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjtubjc)}(hinth]hint}(hjuhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjtubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjtubj)}(hirqh]hirq}(hj!uhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubah}(h]h ]h"]h$]h&]hhuh1jhjthhhjthMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjthhhjthMubah}(h]jtah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjthMhjthhubjI)}(hhh]j)}(hdisable an irq without waitingh]hdisable an irq without waiting}(hjKuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjHuhhubah}(h]h ]h"]h$]h&]uh1jHhjthhhjthMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjcujkjcujljmjnuh1jQhhhjLahNhNubjp)}(hX>**Parameters** ``unsigned int irq`` Interrupt to disable **Description** Disable the selected interrupt line. Disables and Enables are nested. Unlike disable_irq(), this function does not ensure existing instances of the IRQ handler have completed before returning. This function may be called from IRQ context.h](j)}(h**Parameters**h]jz)}(hjmuh]h Parameters}(hjouhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjkuubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjguubj)}(hhh]j)}(h*``unsigned int irq`` Interrupt to disable h](j)}(h``unsigned int irq``h]j)}(hjuh]hunsigned int irq}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjuubj)}(hhh]j)}(hInterrupt to disableh]hInterrupt to disable}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjuhMhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjuhMhjuubah}(h]h ]h"]h$]h&]uh1jhjguubj)}(h**Description**h]jz)}(hjuh]h Description}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjuubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjguubj)}(hDisable the selected interrupt line. Disables and Enables are nested. Unlike disable_irq(), this function does not ensure existing instances of the IRQ handler have completed before returning.h]hDisable the selected interrupt line. Disables and Enables are nested. Unlike disable_irq(), this function does not ensure existing instances of the IRQ handler have completed before returning.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjguubj)}(h-This function may be called from IRQ context.h]h-This function may be called from IRQ context.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjguubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMdisable_irq (C function) c.disable_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h#void disable_irq (unsigned int irq)h]j])}(h"void disable_irq(unsigned int irq)h](jc)}(hvoidh]hvoid}(hjvhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hj*vhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvhhhj)vhMubj)}(h disable_irqh]j)}(h disable_irqh]h disable_irq}(hjzh]hunsigned int irq}(hj@zhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjirq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !h](j)}(h**Parameters**h]jz)}(hj{h]h Parameters}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM&hj{ubj)}(hhh]j)}(h)``unsigned int irq`` Interrupt to enable h](j)}(h``unsigned int irq``h]j)}(hj{h]hunsigned int irq}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM#hj{ubj)}(hhh]j)}(hInterrupt to enableh]hInterrupt to enable}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{hM#hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hM#hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(h**Description**h]jz)}(hj{h]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM%hj{ubj)}(hUndoes the effect of one call to disable_irq(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h]hUndoes the effect of one call to disable_irq(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM$hj{ubj)}(hThis function may be called from IRQ context only when desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !h]hThis function may be called from IRQ context only when desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !}(hj |hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM'hj{ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMenable_nmi (C function) c.enable_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h"void enable_nmi (unsigned int irq)h]j])}(h!void enable_nmi(unsigned int irq)h](jc)}(hvoidh]hvoid}(hj<|hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj8|hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM8ubju)}(h h]h }(hjK|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8|hhhjJ|hM8ubj)}(h enable_nmih]j)}(h enable_nmih]h enable_nmi}(hj]|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjY|ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj8|hhhjJ|hM8ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjy|hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhju|ubju)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthju|ubjc)}(hinth]hint}(hj|hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhju|ubju)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthju|ubj)}(hirqh]hirq}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhju|ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjq|ubah}(h]h ]h"]h$]h&]hhuh1jhj8|hhhjJ|hM8ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj4|hhhjJ|hM8ubah}(h]j/|ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjJ|hM8hj1|hhubjI)}(hhh]j)}(henable handling of an nmih]henable handling of an nmi}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM8hj|hhubah}(h]h ]h"]h$]h&]uh1jHhj1|hhhjJ|hM8ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj|jkj|jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt to enable **Description** The interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h](j)}(h**Parameters**h]jz)}(hj|h]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj|ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM<hj|ubj)}(hhh]j)}(h)``unsigned int irq`` Interrupt to enable h](j)}(h``unsigned int irq``h]j)}(hj}h]hunsigned int irq}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM9hj}ubj)}(hhh]j)}(hInterrupt to enableh]hInterrupt to enable}(hj5}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1}hM9hj2}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhj1}hM9hj}ubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(h**Description**h]jz)}(hjW}h]h Description}(hjY}hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjU}ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM;hj|ubj)}(hThe interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h]hThe interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.}(hjm}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM:hj|ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_irq_wake (C function)c.irq_set_irq_wakehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h8int irq_set_irq_wake (unsigned int irq, unsigned int on)h]j])}(h7int irq_set_irq_wake(unsigned int irq, unsigned int on)h](jc)}(hinth]hint}(hj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMSubju)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}hhhj}hMSubj)}(hirq_set_irq_wakeh]j)}(hirq_set_irq_wakeh]hirq_set_irq_wake}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj}hhhj}hMSubj)}(h#(unsigned int irq, unsigned int on)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}ubju)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubjc)}(hinth]hint}(hj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}ubju)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubj)}(hirqh]hirq}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubj)}(hunsigned int onh](jc)}(hunsignedh]hunsigned}(hj*~hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&~ubju)}(h h]h }(hj8~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&~ubjc)}(hinth]hint}(hjF~hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&~ubju)}(h h]h }(hjT~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&~ubj)}(honh]hon}(hjb~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubeh}(h]h ]h"]h$]h&]hhuh1jhj}hhhj}hMSubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj}hhhj}hMSubah}(h]j}ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj}hMShj}hhubjI)}(hhh]j)}(h#control irq power management wakeuph]h#control irq power management wakeup}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMShj~hhubah}(h]h ]h"]h$]h&]uh1jHhj}hhhj}hMSubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj~jkj~jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` interrupt to control ``unsigned int on`` enable/disable power management wakeup **Description** Enable/disable power management wakeup mode, which is disabled by default. Enables and disables must match, just as they match for non-wakeup mode support. Wakeup mode lets this IRQ wake the system from sleep states like "suspend to RAM". **Note** irq enable/disable state is completely orthogonal to the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. If this does not hold, then the underlying irq chip and the related driver need to be investigated.h](j)}(h**Parameters**h]jz)}(hj~h]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj~ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMWhj~ubj)}(hhh](j)}(h*``unsigned int irq`` interrupt to control h](j)}(h``unsigned int irq``h]j)}(hj~h]hunsigned int irq}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMThj~ubj)}(hhh]j)}(hinterrupt to controlh]hinterrupt to control}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~hMThj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~hMThj~ubj)}(h;``unsigned int on`` enable/disable power management wakeup h](j)}(h``unsigned int on``h]j)}(hjh]hunsigned int on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMUhjubj)}(hhh]j)}(h&enable/disable power management wakeuph]h&enable/disable power management wakeup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMUhj~ubeh}(h]h ]h"]h$]h&]uh1jhj~ubj)}(h**Description**h]jz)}(hjAh]h Description}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMWhj~ubj)}(hEnable/disable power management wakeup mode, which is disabled by default. Enables and disables must match, just as they match for non-wakeup mode support.h]hEnable/disable power management wakeup mode, which is disabled by default. Enables and disables must match, just as they match for non-wakeup mode support.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMVhj~ubj)}(hRWakeup mode lets this IRQ wake the system from sleep states like "suspend to RAM".h]hVWakeup mode lets this IRQ wake the system from sleep states like “suspend to RAM”.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMZhj~ubj)}(h**Note**h]jz)}(hjwh]hNote}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjuubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM]hj~ubj)}(hX'irq enable/disable state is completely orthogonal to the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. If this does not hold, then the underlying irq chip and the related driver need to be investigated.h]hX'irq enable/disable state is completely orthogonal to the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. If this does not hold, then the underlying irq chip and the related driver need to be investigated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM^hj~ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_wake_thread (C function)c.irq_wake_threadhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h5void irq_wake_thread (unsigned int irq, void *dev_id)h]j])}(h4void irq_wake_thread(unsigned int irq, void *dev_id)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hirq_wake_threadh]j)}(hirq_wake_threadh]hirq_wake_thread}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h (unsigned int irq, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hjJhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjFubju)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjFubj )}(hj h]h*}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubj)}(hdev_idh]hdev_id}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hjhhubjI)}(hhh]j)}(h7wake the irq thread for the action identified by dev_idh]h7wake the irq thread for the action identified by dev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h~**Parameters** ``unsigned int irq`` Interrupt line ``void *dev_id`` Device identity for which the thread should be wokenh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh](j)}(h$``unsigned int irq`` Interrupt line h](j)}(h``unsigned int irq``h]j)}(hjހh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj܀ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj؀ubj)}(hhh]j)}(hInterrupt lineh]hInterrupt line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhj؀ubeh}(h]h ]h"]h$]h&]uh1jhjhM hjՀubj)}(hE``void *dev_id`` Device identity for which the thread should be wokenh](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h4Device identity for which the thread should be wokenh]h4Device identity for which the thread should be woken}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj,hM hjՀubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMfree_irq (C function) c.free_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h6const void * free_irq (unsigned int irq, void *dev_id)h]j])}(h4const void *free_irq(unsigned int irq, void *dev_id)h](j)}(hjh]hconst}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjmhhhj~hMubjc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjmhhhj~hMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjmhhhj~hMubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjmhhhj~hMubj)}(hfree_irqh]j)}(hfree_irqh]hfree_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjmhhhj~hMubj)}(h (unsigned int irq, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjցhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjҁubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjҁubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjҁubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjҁubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjҁubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj΁ubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hj'hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj#ubju)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubj )}(hj h]h*}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hdev_idh]hdev_id}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj΁ubeh}(h]h ]h"]h$]h&]hhuh1jhjmhhhj~hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjihhhj~hMubah}(h]jdah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj~hMhjfhhubjI)}(hhh]j)}(h,free an interrupt allocated with request_irqh]h,free an interrupt allocated with request_irq}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjwhhubah}(h]h ]h"]h$]h&]uh1jHhjfhhhj~hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX9**Parameters** ``unsigned int irq`` Interrupt line to free ``void *dev_id`` Device identity to free **Description** Remove an interrupt handler. The handler is removed and if the interrupt line is no longer in use by any driver it is disabled. On a shared IRQ the caller must ensure the interrupt is disabled on the card it drives before calling this function. The function does not return until any executing interrupts for this IRQ have completed. This function must not be called from interrupt context. Returns the devname argument passed to request_irq.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh](j)}(h,``unsigned int irq`` Interrupt line to free h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(hInterrupt line to freeh]hInterrupt line to free}(hjԂhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЂhMhjтubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjЂhMhjubj)}(h)``void *dev_id`` Device identity to free h](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(hDevice identity to freeh]hDevice identity to free}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj/h]h Description}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj-ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hXNRemove an interrupt handler. The handler is removed and if the interrupt line is no longer in use by any driver it is disabled. On a shared IRQ the caller must ensure the interrupt is disabled on the card it drives before calling this function. The function does not return until any executing interrupts for this IRQ have completed.h]hXNRemove an interrupt handler. The handler is removed and if the interrupt line is no longer in use by any driver it is disabled. On a shared IRQ the caller must ensure the interrupt is disabled on the card it drives before calling this function. The function does not return until any executing interrupts for this IRQ have completed.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(h8This function must not be called from interrupt context.h]h8This function must not be called from interrupt context.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(h3Returns the devname argument passed to request_irq.h]h3Returns the devname argument passed to request_irq.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!request_threaded_irq (C function)c.request_threaded_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hint request_threaded_irq (unsigned int irq, irq_handler_t handler, irq_handler_t thread_fn, unsigned long irqflags, const char *devname, void *dev_id)h]j])}(hint request_threaded_irq(unsigned int irq, irq_handler_t handler, irq_handler_t thread_fn, unsigned long irqflags, const char *devname, void *dev_id)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hrequest_threaded_irqh]j)}(hrequest_threaded_irqh]hrequest_threaded_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h}(unsigned int irq, irq_handler_t handler, irq_handler_t thread_fn, unsigned long irqflags, const char *devname, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjσhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj˃ubju)}(h h]h }(hj݃hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj˃ubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj˃ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj˃ubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj˃ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj%modnameN classnameNjj)}j]j)}jjsbc.request_threaded_irqasbuh1hhjubju)}(h h]h }(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubj)}(hirq_handler_t thread_fnh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjomodnameN classnameNjj)}j]j?c.request_threaded_irqasbuh1hhjfubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjfubj)}(h thread_fnh]h thread_fn}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubj)}(hunsigned long irqflagsh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hlongh]hlong}(hj΄hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj܄hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqflagsh]hirqflags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubj)}(hconst char *devnameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdevnameh]hdevname}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubj )}(hj h]h*}(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubj)}(hdev_idh]hdev_id}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjǃubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(hallocate an interrupt lineh]hallocate an interrupt line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj˅jkj˅jljmjnuh1jQhhhjLahNhNubjp)}(hX.**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed. ``irq_handler_t thread_fn`` Function called from the irq handler thread If NULL, no irq thread is created ``unsigned long irqflags`` Interrupt type flags ``const char *devname`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function **Description** This call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order. If you want to set up a threaded irq handler for your device then you need to supply **handler** and **thread_fn**. **handler** is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run **thread_fn**. This split handler design is necessary to support shared interrupts. **dev_id** must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt. Flags: IRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh](j)}(h**Parameters**h]jz)}(hjՅh]h Parameters}(hjׅhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjӅubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjυubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h``irq_handler_t handler`` Function to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed. h](j)}(h``irq_handler_t handler``h]j)}(hj-h]hirq_handler_t handler}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM!hj'ubj)}(hhh]j)}(hFunction to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed.h]hFunction to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjCubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhjBhM!hjubj)}(hj``irq_handler_t thread_fn`` Function called from the irq handler thread If NULL, no irq thread is created h](j)}(h``irq_handler_t thread_fn``h]j)}(hjgh]hirq_handler_t thread_fn}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM#hjaubj)}(hhh]j)}(hMFunction called from the irq handler thread If NULL, no irq thread is createdh]hMFunction called from the irq handler thread If NULL, no irq thread is created}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM"hj}ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hM#hjubj)}(h0``unsigned long irqflags`` Interrupt type flags h](j)}(h``unsigned long irqflags``h]j)}(hjh]hunsigned long irqflags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM$hjubj)}(hhh]j)}(hInterrupt type flagsh]hInterrupt type flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM$hjubj)}(h>``const char *devname`` An ascii name for the claiming device h](j)}(h``const char *devname``h]j)}(hjچh]hconst char *devname}(hj܆hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj؆ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM%hjԆubj)}(hhh]j)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM%hjubah}(h]h ]h"]h$]h&]uh1jhjԆubeh}(h]h ]h"]h$]h&]uh1jhjhM%hjubj)}(h>``void *dev_id`` A cookie passed back to the handler function h](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM&hj ubj)}(hhh]j)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(hM&hj)ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj(hM&hjubeh}(h]h ]h"]h$]h&]uh1jhjυubj)}(h**Description**h]jz)}(hjNh]h Description}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjLubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM(hjυubj)}(hXRThis call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order.h]hXRThis call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM'hjυubj)}(hXIf you want to set up a threaded irq handler for your device then you need to supply **handler** and **thread_fn**. **handler** is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run **thread_fn**. This split handler design is necessary to support shared interrupts.h](hUIf you want to set up a threaded irq handler for your device then you need to supply }(hjshhhNhNubjz)}(h **handler**h]hhandler}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubh and }(hjshhhNhNubjz)}(h **thread_fn**h]h thread_fn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubh. }(hjshhhNhNubjz)}(h **handler**h]hhandler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubh is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run }(hjshhhNhNubjz)}(h **thread_fn**h]h thread_fn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubhF. This split handler design is necessary to support shared interrupts.}(hjshhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM-hjυubj)}(h**dev_id** must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.h](jz)}(h **dev_id**h]hdev_id}(hj·hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjʇubh must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.-}(hjʇhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM5hjυubj)}(hkIf your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt.h]hkIf your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM9hjυubj)}(hFlags:h]hFlags:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM<hjυubh block_quote)}(hIRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh]j)}(hIRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh]hIRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line masked}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM>hjubah}(h]h ]h"]h$]h&]uh1jhjhM>hjυubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$request_any_context_irq (C function)c.request_any_context_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hzint request_any_context_irq (unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h]j])}(hyint request_any_context_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h](jc)}(hinth]hint}(hj@hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj<hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<hhhjNhMubj)}(hrequest_any_context_irqh]j)}(hrequest_any_context_irqh]hrequest_any_context_irq}(hjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj<hhhjNhMubj)}(h^(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjyubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjyubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjyubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjyubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hjшhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjΈubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjӈmodnameN classnameNjj)}j]j)}jjcsbc.request_any_context_irqasbuh1hhjʈubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjʈubj)}(hhandlerh]hhandler}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʈubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(hunsigned long flagsh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hlongh]hlong}(hj4hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hflagsh]hflags}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(hconst char *nameh](j)}(hjh]hconst}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubju)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjeubjc)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjeubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjeubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubj)}(hnameh]hname}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hjƉhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj‰ubju)}(h h]h }(hjԉhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj‰ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj‰ubj)}(hdev_idh]hdev_id}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj‰ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjuubeh}(h]h ]h"]h$]h&]hhuh1jhj<hhhjNhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj8hhhjNhMubah}(h]j3ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjNhMhj5hhubjI)}(hhh]j)}(hallocate an interrupt lineh]hallocate an interrupt line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhj5hhhjNhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj1jkj1jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. ``unsigned long flags`` Interrupt type flags ``const char *name`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function **Description** This call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context. **Return** On failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.h](j)}(h**Parameters**h]jz)}(hj;h]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj5ubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjZh]hunsigned int irq}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjTubj)}(hhh]j)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjohMhjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjohMhjQubj)}(ho``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. h](j)}(h``irq_handler_t handler``h]j)}(hjh]hirq_handler_t handler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.h]hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjQubj)}(h-``unsigned long flags`` Interrupt type flags h](j)}(h``unsigned long flags``h]j)}(hj͊h]hunsigned long flags}(hjϊhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjˊubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjNJubj)}(hhh]j)}(hInterrupt type flagsh]hInterrupt type flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjNJubeh}(h]h ]h"]h$]h&]uh1jhjhMhjQubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjQubj)}(h>``void *dev_id`` A cookie passed back to the handler function h](j)}(h``void *dev_id``h]j)}(hj?h]h void *dev_id}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj9ubj)}(hhh]j)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjThMhjUubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhjThMhjQubeh}(h]h ]h"]h$]h&]uh1jhj5ubj)}(h**Description**h]jz)}(hjzh]h Description}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjxubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj5ubj)}(hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context.h]hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj5ubj)}(h **Return**h]jz)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj5ubj)}(hiOn failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.h]hiOn failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj5ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMrequest_nmi (C function) c.request_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hqint request_nmi (unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h]j])}(hpint request_nmi(unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(h request_nmih]j)}(h request_nmih]h request_nmi}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(ha(unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hj#hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj?hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjymodnameN classnameNjj)}j]j)}jj sb c.request_nmiasbuh1hhjpubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjpubj)}(hhandlerh]hhandler}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned long irqflagsh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hǰhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hlongh]hlong}(hjڌhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqflagsh]hirqflags}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hconst char *nameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubjc)}(hcharh]hchar}(hj*hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj ubju)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubj )}(hj h]h*}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hnameh]hname}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hjlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhubju)}(h h]h }(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubj)}(hdev_idh]hdev_id}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjދhhhjhMubah}(h]jًah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjۋhhubjI)}(hhh]j)}(h+allocate an interrupt line for NMI deliveryh]h+allocate an interrupt line for NMI delivery}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjۋhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj׍jkj׍jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. ``unsigned long irqflags`` Interrupt type flags ``const char *name`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function **Description** This call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI. An interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded. Interrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled. **dev_id** must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjߍubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(ho``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. h](j)}(h``irq_handler_t handler``h]j)}(hj9h]hirq_handler_t handler}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhj3ubj)}(hhh]j)}(hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.h]hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMhjubj)}(h0``unsigned long irqflags`` Interrupt type flags h](j)}(h``unsigned long irqflags``h]j)}(hjsh]hunsigned long irqflags}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjmubj)}(hhh]j)}(hInterrupt type flagsh]hInterrupt type flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjubj)}(hhh]j)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjŎhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjŽubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h>``void *dev_id`` A cookie passed back to the handler function h](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjߎubj)}(hhh]j)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjߎubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjۍubj)}(h**Description**h]jz)}(hj h]h Description}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI.h]hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(hWAn interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded.h]hWAn interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(huInterrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled.h]huInterrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(h**dev_id** must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.h](jz)}(h **dev_id**h]hdev_id}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjcubh must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubj)}(heIf the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.h]heIf the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMhjۍubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_percpu_is_enabled (C function)c.irq_percpu_is_enabledhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h-bool irq_percpu_is_enabled (unsigned int irq)h]j])}(h,bool irq_percpu_is_enabled(unsigned int irq)h](jc)}(hjah]hbool}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM> ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM> ubj)}(hirq_percpu_is_enabledh]j)}(hirq_percpu_is_enabledh]hirq_percpu_is_enabled}(hjϏhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjˏubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM> ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM> ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM> ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM> hjhhubjI)}(hhh]j)}(h(Check whether the per cpu irq is enabledh]h(Check whether the per cpu irq is enabled}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM> hjJhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM> ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjejkjejljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``unsigned int irq`` Linux irq number to check for **Description** Must be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.h](j)}(h**Parameters**h]jz)}(hjoh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjmubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMB hjiubj)}(hhh]j)}(h3``unsigned int irq`` Linux irq number to check for h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM? hjubj)}(hhh]j)}(hLinux irq number to check forh]hLinux irq number to check for}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM? hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM? hjubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(h**Description**h]jz)}(hjɐh]h Description}(hjːhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjǐubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMA hjiubj)}(hqMust be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.h]hqMust be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.}(hjߐhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM@ hjiubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMfree_percpu_irq (C function)c.free_percpu_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h>void free_percpu_irq (unsigned int irq, void __percpu *dev_id)h]j])}(h=void free_percpu_irq(unsigned int irq, void __percpu *dev_id)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj hhhjhM ubj)}(hfree_percpu_irqh]j)}(hfree_percpu_irqh]hfree_percpu_irq}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhjhM ubj)}(h)(unsigned int irq, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjKhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjGubju)}(h h]h }(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjGubjc)}(hinth]hint}(hjghhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjGubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjGubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjCubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__percpu}(hjhhhNhNubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjʑhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hjבhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjCubeh}(h]h ]h"]h$]h&]hhuh1jhj hhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hjhhubjI)}(hhh]j)}(h3free an interrupt allocated with request_percpu_irqh]h3free an interrupt allocated with request_percpu_irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to free ``void __percpu *dev_id`` Device identity to free **Description** Remove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed. This function must not be called from interrupt context.h](j)}(h**Parameters**h]jz)}(hj#h]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj!ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh](j)}(h,``unsigned int irq`` Interrupt line to free h](j)}(h``unsigned int irq``h]j)}(hjBh]hunsigned int irq}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj<ubj)}(hhh]j)}(hInterrupt line to freeh]hInterrupt line to free}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWhM hjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhM hj9ubj)}(h2``void __percpu *dev_id`` Device identity to free h](j)}(h``void __percpu *dev_id``h]j)}(hj{h]hvoid __percpu *dev_id}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjuubj)}(hhh]j)}(hDevice identity to freeh]hDevice identity to free}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhM hj9ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hRemove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed.h]hRemove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed.}(hj̒hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(h8This function must not be called from interrupt context.h]h8This function must not be called from interrupt context.}(hjےhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM(request_percpu_irq_affinity (C function)c.request_percpu_irq_affinityhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hint request_percpu_irq_affinity (unsigned int irq, irq_handler_t handler, const char *devname, const cpumask_t *affinity, void __percpu *dev_id)h]j])}(hint request_percpu_irq_affinity(unsigned int irq, irq_handler_t handler, const char *devname, const cpumask_t *affinity, void __percpu *dev_id)h](jc)}(hinth]hint}(hj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hrequest_percpu_irq_affinityh]j)}(hrequest_percpu_irq_affinityh]hrequest_percpu_irq_affinity}(hj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(hp(unsigned int irq, irq_handler_t handler, const char *devname, const cpumask_t *affinity, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjGhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjCubju)}(h h]h }(hjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjCubjc)}(hinth]hint}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjCubju)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjCubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jj-sbc.request_percpu_irq_affinityasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hjɓhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hconst char *devnameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޓubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjޓubjc)}(hcharh]hchar}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjޓubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjޓubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޓubj)}(hdevnameh]hdevname}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjޓubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hconst cpumask_t *affinityh](j)}(hjh]hconst}(hj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubju)}(h h]h }(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj;ubh)}(hhh]j)}(h cpumask_th]h cpumask_t}(hj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj_modnameN classnameNjj)}j]jc.request_percpu_irq_affinityasbuh1hhj;ubju)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj;ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubj)}(haffinityh]haffinity}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__percpu}(hjhhhNhNubju)}(h h]h }(hjϔhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjݔhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj?ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hjhhubjI)}(hhh]j)}(h allocate a percpu interrupt lineh]h allocate a percpu interrupt line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj,jkj,jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. ``const char *devname`` An ascii name for the claiming device ``const cpumask_t *affinity`` A cpumask describing the target CPUs for this interrupt ``void __percpu *dev_id`` A percpu cookie passed back to the handler function **Description** This call allocates interrupt resources, but doesn't enable the interrupt on any CPU, as all percpu-devid interrupts are flagged with IRQ_NOAUTOEN. It has to be done on each CPU using enable_percpu_irq(). **dev_id** must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h](j)}(h**Parameters**h]jz)}(hj6h]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj0ubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjUh]hunsigned int irq}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjOubj)}(hhh]j)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjhM hjkubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jhjjhM hjLubj)}(hE``irq_handler_t handler`` Function to be called when the IRQ occurs. h](j)}(h``irq_handler_t handler``h]j)}(hjh]hirq_handler_t handler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h*Function to be called when the IRQ occurs.h]h*Function to be called when the IRQ occurs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjLubj)}(h>``const char *devname`` An ascii name for the claiming device h](j)}(h``const char *devname``h]j)}(hjǕh]hconst char *devname}(hjɕhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjŕubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܕhM hjݕubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjܕhM hjLubj)}(hV``const cpumask_t *affinity`` A cpumask describing the target CPUs for this interrupt h](j)}(h``const cpumask_t *affinity``h]j)}(hjh]hconst cpumask_t *affinity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h7A cpumask describing the target CPUs for this interrupth]h7A cpumask describing the target CPUs for this interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjLubj)}(hN``void __percpu *dev_id`` A percpu cookie passed back to the handler function h](j)}(h``void __percpu *dev_id``h]j)}(hj9h]hvoid __percpu *dev_id}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj3ubj)}(hhh]j)}(h3A percpu cookie passed back to the handler functionh]h3A percpu cookie passed back to the handler function}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhM hjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhM hjLubeh}(h]h ]h"]h$]h&]uh1jhj0ubj)}(h**Description**h]jz)}(hjth]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjrubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj0ubj)}(hThis call allocates interrupt resources, but doesn't enable the interrupt on any CPU, as all percpu-devid interrupts are flagged with IRQ_NOAUTOEN. It has to be done on each CPU using enable_percpu_irq().h]hThis call allocates interrupt resources, but doesn’t enable the interrupt on any CPU, as all percpu-devid interrupts are flagged with IRQ_NOAUTOEN. It has to be done on each CPU using enable_percpu_irq().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj0ubj)}(h**dev_id** must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h](jz)}(h **dev_id**h]hdev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU’s instance of that variable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj0ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMrequest_percpu_nmi (C function)c.request_percpu_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hint request_percpu_nmi (unsigned int irq, irq_handler_t handler, const char *name, const struct cpumask *affinity, void __percpu *dev_id)h]j])}(hint request_percpu_nmi(unsigned int irq, irq_handler_t handler, const char *name, const struct cpumask *affinity, void __percpu *dev_id)h](jc)}(hinth]hint}(hj֖hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjҖhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjҖhhhjhM ubj)}(hrequest_percpu_nmih]j)}(hrequest_percpu_nmih]hrequest_percpu_nmi}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjҖhhhjhM ubj)}(hr(unsigned int irq, irq_handler_t handler, const char *name, const struct cpumask *affinity, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj/hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjimodnameN classnameNjj)}j]j)}jjsbc.request_percpu_nmiasbuh1hhj`ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj`ubj)}(hhandlerh]hhandler}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(hconst char *nameh](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hcharh]hchar}(hjɗhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjחhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hnameh]hname}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(hconst struct cpumask *affinityh](j)}(hjh]hconst}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hjh]hstruct}(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hcpumaskh]hcpumask}(hjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjFmodnameN classnameNjj)}j]jc.request_percpu_nmiasbuh1hhjubju)}(h h]h }(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(haffinityh]haffinity}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__percpu}(hjhhhNhNubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjĘhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hjјhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubeh}(h]h ]h"]h$]h&]hhuh1jhjҖhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjΖhhhjhM ubah}(h]jɖah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hj˖hhubjI)}(hhh]j)}(h1allocate a percpu interrupt line for NMI deliveryh]h1allocate a percpu interrupt line for NMI delivery}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhj˖hhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. ``const char *name`` An ascii name for the claiming device ``const struct cpumask *affinity`` A cpumask describing the target CPUs for this interrupt ``void __percpu *dev_id`` A percpu cookie passed back to the handler function **Description** This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi(). **dev_id** must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable. Interrupt lines requested for NMI delivering should have auto enabling setting disabled. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hj<h]hunsigned int irq}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj6ubj)}(hhh]j)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQhM hjRubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhjQhM hj3ubj)}(hE``irq_handler_t handler`` Function to be called when the IRQ occurs. h](j)}(h``irq_handler_t handler``h]j)}(hjuh]hirq_handler_t handler}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjoubj)}(hhh]j)}(h*Function to be called when the IRQ occurs.h]h*Function to be called when the IRQ occurs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjhM hj3ubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjǙhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjÙhM hjęubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjÙhM hj3ubj)}(h[``const struct cpumask *affinity`` A cpumask describing the target CPUs for this interrupt h](j)}(h"``const struct cpumask *affinity``h]j)}(hjh]hconst struct cpumask *affinity}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h7A cpumask describing the target CPUs for this interrupth]h7A cpumask describing the target CPUs for this interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hj3ubj)}(hN``void __percpu *dev_id`` A percpu cookie passed back to the handler function h](j)}(h``void __percpu *dev_id``h]j)}(hj h]hvoid __percpu *dev_id}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h3A percpu cookie passed back to the handler functionh]h3A percpu cookie passed back to the handler function}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5hM hj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hM hj3ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj[h]h Description}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjYubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hThis call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi().h]hThis call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi().}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(h**dev_id** must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h](jz)}(h **dev_id**h]hdev_id}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU’s instance of that variable.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hXInterrupt lines requested for NMI delivering should have auto enabling setting disabled.h]hXInterrupt lines requested for NMI delivering should have auto enabling setting disabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h]hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMprepare_percpu_nmi (C function)c.prepare_percpu_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h)int prepare_percpu_nmi (unsigned int irq)h]j])}(h(int prepare_percpu_nmi(unsigned int irq)h](jc)}(hinth]hint}(hjۚhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjךhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMI ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjךhhhjhMI ubj)}(hprepare_percpu_nmih]j)}(hprepare_percpu_nmih]hprepare_percpu_nmi}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjךhhhjhMI ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj4hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjךhhhjhMI ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjӚhhhjhMI ubah}(h]jΚah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMI hjКhhubjI)}(hhh]j)}(h)performs CPU local setup for NMI deliveryh]h)performs CPU local setup for NMI delivery}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMI hjwhhubah}(h]h ]h"]h$]h&]uh1jHhjКhhhjhMI ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line to prepare for NMI delivery **Description** This call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi(). As a CPU local operation, this should be called from non-preemptible context. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMM hjubj)}(hhh]j)}(h@``unsigned int irq`` Interrupt line to prepare for NMI delivery h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMJ hjubj)}(hhh]j)}(h*Interrupt line to prepare for NMI deliveryh]h*Interrupt line to prepare for NMI delivery}(hjԛhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЛhMJ hjћubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjЛhMJ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chML hjubj)}(hThis call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi().h]hThis call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi().}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMK hjubj)}(hMAs a CPU local operation, this should be called from non-preemptible context.h]hMAs a CPU local operation, this should be called from non-preemptible context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMN hjubj)}(hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h]hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.c?hMQ hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM teardown_percpu_nmi (C function)c.teardown_percpu_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h+void teardown_percpu_nmi (unsigned int irq)h]j])}(h*void teardown_percpu_nmi(unsigned int irq)h](jc)}(hvoidh]hvoid}(hjYhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjUhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMh ubju)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjUhhhjghMh ubj)}(hteardown_percpu_nmih]j)}(hteardown_percpu_nmih]hteardown_percpu_nmi}(hjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ](jjeh"]h$]h&]hhuh1jhjUhhhjghMh ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjΜhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjUhhhjghMh ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjQhhhjghMh ubah}(h]jLah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjghMh hjNhhubjI)}(hhh]j)}(hundoes NMI setup of IRQ lineh]hundoes NMI setup of IRQ line}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMh hjhhubah}(h]h ]h"]h$]h&]uh1jHhjNhhhjghMh ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX<**Parameters** ``unsigned int irq`` Interrupt line from which CPU local NMI configuration should be removed **Description** This call undoes the setup done by prepare_percpu_nmi(). IRQ line should not be enabled for the current CPU. As a CPU local operation, this should be called from non-preemptible context.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMl hjubj)}(hhh]j)}(h]``unsigned int irq`` Interrupt line from which CPU local NMI configuration should be removed h](j)}(h``unsigned int irq``h]j)}(hj9h]hunsigned int irq}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMi hj3ubj)}(hhh]j)}(hGInterrupt line from which CPU local NMI configuration should be removedh]hGInterrupt line from which CPU local NMI configuration should be removed}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNhMi hjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMi hj0ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjth]h Description}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjrubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMk hjubj)}(h8This call undoes the setup done by prepare_percpu_nmi().h]h8This call undoes the setup done by prepare_percpu_nmi().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMj hjubj)}(hIRQ line should not be enabled for the current CPU. As a CPU local operation, this should be called from non-preemptible context.h]hIRQ line should not be enabled for the current CPU. As a CPU local operation, this should be called from non-preemptible context.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chMl hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_get_irqchip_state (C function)c.irq_get_irqchip_statehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hWint irq_get_irqchip_state (unsigned int irq, enum irqchip_irq_state which, bool *state)h]j])}(hVint irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool *state)h](jc)}(hinth]hint}(hjȝhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjĝhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjםhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjĝhhhj֝hM ubj)}(hirq_get_irqchip_stateh]j)}(hirq_get_irqchip_stateh]hirq_get_irqchip_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjĝhhhj֝hM ubj)}(h=(unsigned int irq, enum irqchip_irq_state which, bool *state)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj!hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum irqchip_irq_state whichh](j)}(hj%h]henum}(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjRubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjqubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjvmodnameN classnameNjj)}j]j)}jjsbc.irq_get_irqchip_stateasbuh1hhjRubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjRubj)}(hwhichh]hwhich}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool *stateh](jc)}(hjah]hbool}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjȞhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj֞hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjĝhhhj֝hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj֝hM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj֝hM hjhhubjI)}(hhh]j)}(h)returns the irqchip state of a interrupt.h]h)returns the irqchip state of a interrupt.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj֝hM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj%jkj%jljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line that is forwarded to a VM ``enum irqchip_irq_state which`` One of IRQCHIP_STATE_* the caller wants to know about ``bool *state`` a pointer to a boolean where the state is to be stored **Description** This call snapshots the internal irqchip state of an interrupt, returning into **state** the bit corresponding to stage **which** This function should be called with preemption disabled if the interrupt controller has per-cpu registers.h](j)}(h**Parameters**h]jz)}(hj/h]h Parameters}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj-ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj)ubj)}(hhh](j)}(h>``unsigned int irq`` Interrupt line that is forwarded to a VM h](j)}(h``unsigned int irq``h]j)}(hjNh]hunsigned int irq}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjLubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjHubj)}(hhh]j)}(h(Interrupt line that is forwarded to a VMh]h(Interrupt line that is forwarded to a VM}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjchM hjdubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jhjchM hjEubj)}(hW``enum irqchip_irq_state which`` One of IRQCHIP_STATE_* the caller wants to know about h](j)}(h ``enum irqchip_irq_state which``h]j)}(hjh]henum irqchip_irq_state which}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h5One of IRQCHIP_STATE_* the caller wants to know abouth]h5One of IRQCHIP_STATE_* the caller wants to know about}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjEubj)}(hG``bool *state`` a pointer to a boolean where the state is to be stored h](j)}(h``bool *state``h]j)}(hjh]h bool *state}(hjŸhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h6a pointer to a boolean where the state is to be storedh]h6a pointer to a boolean where the state is to be stored}(hjٟhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj՟hM hj֟ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj՟hM hjEubeh}(h]h ]h"]h$]h&]uh1jhj)ubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj)ubj)}(hThis call snapshots the internal irqchip state of an interrupt, returning into **state** the bit corresponding to stage **which**h](hOThis call snapshots the internal irqchip state of an interrupt, returning into }(hjhhhNhNubjz)}(h **state**h]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh the bit corresponding to stage }(hjhhhNhNubjz)}(h **which**h]hwhich}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj)ubj)}(hjThis function should be called with preemption disabled if the interrupt controller has per-cpu registers.h]hjThis function should be called with preemption disabled if the interrupt controller has per-cpu registers.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj)ubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_set_irqchip_state (C function)c.irq_set_irqchip_statehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hTint irq_set_irqchip_state (unsigned int irq, enum irqchip_irq_state which, bool val)h]j])}(hSint irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool val)h](jc)}(hinth]hint}(hjohhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjkhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjkhhhj}hM ubj)}(hirq_set_irqchip_stateh]j)}(hirq_set_irqchip_stateh]hirq_set_irqchip_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjkhhhj}hM ubj)}(h:(unsigned int irq, enum irqchip_irq_state which, bool val)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjȠhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj֠hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum irqchip_irq_state whichh](j)}(hj%h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_set_irqchip_stateasbuh1hhjubju)}(h h]h }(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hwhichh]hwhich}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool valh](jc)}(hjah]hbool}(hjbhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj^ubju)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj^ubj)}(hvalh]hval}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjkhhhj}hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjghhhj}hM ubah}(h]jbah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj}hM hjdhhubjI)}(hhh]j)}(h'set the state of a forwarded interrupt.h]h'set the state of a forwarded interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhjdhhhj}hM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``unsigned int irq`` Interrupt line that is forwarded to a VM ``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) ``bool val`` Value corresponding to **which** **Description** This call sets the internal irqchip state of an interrupt, depending on the value of **which**. This function should be called with migration disabled if the interrupt controller has per-cpu registers.h](j)}(h**Parameters**h]jz)}(hjɡh]h Parameters}(hjˡhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjǡubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjáubj)}(hhh](j)}(h>``unsigned int irq`` Interrupt line that is forwarded to a VM h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h(Interrupt line that is forwarded to a VMh]h(Interrupt line that is forwarded to a VM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjߡubj)}(hO``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) h](j)}(h ``enum irqchip_irq_state which``h]j)}(hj!h]henum irqchip_irq_state which}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(h-State to be restored (one of IRQCHIP_STATE_*)h]h-State to be restored (one of IRQCHIP_STATE_*)}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6hM hj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj6hM hjߡubj)}(h.``bool val`` Value corresponding to **which** h](j)}(h ``bool val``h]j)}(hjZh]hbool val}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjTubj)}(hhh]j)}(h Value corresponding to **which**h](hValue corresponding to }(hjshhhNhNubjz)}(h **which**h]hwhich}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubeh}(h]h ]h"]h$]h&]uh1jhjohM hjpubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jhjohM hjߡubeh}(h]h ]h"]h$]h&]uh1jhjáubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjáubj)}(h_This call sets the internal irqchip state of an interrupt, depending on the value of **which**.h](hUThis call sets the internal irqchip state of an interrupt, depending on the value of }(hjhhhNhNubjz)}(h **which**h]hwhich}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjáubj)}(hiThis function should be called with migration disabled if the interrupt controller has per-cpu registers.h]hiThis function should be called with migration disabled if the interrupt controller has per-cpu registers.}(hjڢhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjáubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_has_action (C function)c.irq_has_actionhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h&bool irq_has_action (unsigned int irq)h]j])}(h%bool irq_has_action(unsigned int irq)h](jc)}(hjah]hbool}(hj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hirq_has_actionh]j)}(hirq_has_actionh]hirq_has_action}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjEhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjAubju)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjAubjc)}(hinth]hint}(hjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjAubju)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjAubj)}(hirqh]hirq}(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj=ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hjhhubjI)}(hhh]j)}(h'Check whether an interrupt is requestedh]h'Check whether an interrupt is requested}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hh**Parameters** ``unsigned int irq`` The linux irq number **Return** A snapshot of the current stateh](j)}(h**Parameters**h]jz)}(hjɣh]h Parameters}(hjˣhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjǣubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjãubj)}(hhh]j)}(h*``unsigned int irq`` The linux irq number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(hThe linux irq numberh]hThe linux irq number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjߣubah}(h]h ]h"]h$]h&]uh1jhjãubj)}(h **Return**h]jz)}(hj#h]hReturn}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj!ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjãubj)}(hA snapshot of the current stateh]hA snapshot of the current state}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjãubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_check_status_bit (C function)c.irq_check_status_bithNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hBbool irq_check_status_bit (unsigned int irq, unsigned int bitmask)h]j])}(hAbool irq_check_status_bit(unsigned int irq, unsigned int bitmask)h](jc)}(hjah]hbool}(hjhhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjdhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM ubju)}(h h]h }(hjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdhhhjuhM ubj)}(hirq_check_status_bith]j)}(hirq_check_status_bith]hirq_check_status_bit}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjuhM ubj)}(h((unsigned int irq, unsigned int bitmask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjΤhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjܤhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int bitmaskh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hbitmaskh]hbitmask}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjdhhhjuhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj`hhhjuhM ubah}(h]j[ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjuhM hj]hhubjI)}(hhh]j)}(h7Check whether bits in the irq descriptor status are seth]h7Check whether bits in the irq descriptor status are set}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjThhubah}(h]h ]h"]h$]h&]uh1jHhj]hhhjuhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjojkjojljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``unsigned int irq`` The linux irq number ``unsigned int bitmask`` The bitmask to evaluate **Return** True if one of the bits in **bitmask** is seth](j)}(h**Parameters**h]jz)}(hjyh]h Parameters}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjwubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjsubj)}(hhh](j)}(h*``unsigned int irq`` The linux irq number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjubj)}(hhh]j)}(hThe linux irq numberh]hThe linux irq number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(h1``unsigned int bitmask`` The bitmask to evaluate h](j)}(h``unsigned int bitmask``h]j)}(hjѥh]hunsigned int bitmask}(hjӥhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjϥubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hj˥ubj)}(hhh]j)}(hThe bitmask to evaluateh]hThe bitmask to evaluate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhj˥ubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(h **Return**h]jz)}(hj h]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjsubj)}(h-True if one of the bits in **bitmask** is seth](hTrue if one of the bits in }(hj"hhhNhNubjz)}(h **bitmask**h]hbitmask}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj"ubh is set}(hj"hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/manage.chM hjsubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_chip (C function)c.irq_set_chiphNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h@int irq_set_chip (unsigned int irq, const struct irq_chip *chip)h]j])}(h?int irq_set_chip(unsigned int irq, const struct irq_chip *chip)h](jc)}(hinth]hint}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK&ubju)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_hhhjqhK&ubj)}(h irq_set_chiph]j)}(h irq_set_chiph]h irq_set_chip}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_hhhjqhK&ubj)}(h/(unsigned int irq, const struct irq_chip *chip)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjʦhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjئhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hconst struct irq_chip *chiph](j)}(hjh]hconst}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hjh]hstruct}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_chiph]hirq_chip}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj,modnameN classnameNjj)}j]j)}jjsbc.irq_set_chipasbuh1hhjubju)}(h h]h }(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hchiph]hchip}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj_hhhjqhK&ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj[hhhjqhK&ubah}(h]jVah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjqhK&hjXhhubjI)}(hhh]j)}(hset the irq chip for an irqh]hset the irq chip for an irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK&hjhhubah}(h]h ]h"]h$]h&]uh1jHhjXhhhjqhK&ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h~**Parameters** ``unsigned int irq`` irq number ``const struct irq_chip *chip`` pointer to irq chip description structureh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK*hjubj)}(hhh](j)}(h ``unsigned int irq`` irq number h](j)}(h``unsigned int irq``h]j)}(hjЧh]hunsigned int irq}(hjҧhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjΧubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK'hjʧubj)}(hhh]j)}(h irq numberh]h irq number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhK'hjubah}(h]h ]h"]h$]h&]uh1jhjʧubeh}(h]h ]h"]h$]h&]uh1jhjhK'hjǧubj)}(hI``const struct irq_chip *chip`` pointer to irq chip description structureh](j)}(h``const struct irq_chip *chip``h]j)}(hj h]hconst struct irq_chip *chip}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK)hjubj)}(hhh]j)}(h)pointer to irq chip description structureh]h)pointer to irq chip description structure}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK)hjǧubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_irq_type (C function)c.irq_set_irq_typehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h:int irq_set_irq_type (unsigned int irq, unsigned int type)h]j])}(h9int irq_set_irq_type(unsigned int irq, unsigned int type)h](jc)}(hinth]hint}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK:ubju)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_hhhjqhK:ubj)}(hirq_set_irq_typeh]j)}(hirq_set_irq_typeh]hirq_set_irq_type}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_hhhjqhK:ubj)}(h%(unsigned int irq, unsigned int type)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjʨhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjبhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int typeh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(htypeh]htype}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj_hhhjqhK:ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj[hhhjqhK:ubah}(h]jVah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjqhK:hjXhhubjI)}(hhh]j)}(h#set the irq trigger type for an irqh]h#set the irq trigger type for an irq}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK:hjPhhubah}(h]h ]h"]h$]h&]uh1jHhjXhhhjqhK:ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjkjkjkjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``unsigned int irq`` irq number ``unsigned int type`` IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.hh](j)}(h**Parameters**h]jz)}(hjuh]h Parameters}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjsubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK>hjoubj)}(hhh](j)}(h ``unsigned int irq`` irq number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK;hjubj)}(hhh]j)}(h irq numberh]h irq number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhK;hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK;hjubj)}(hM``unsigned int type`` IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.hh](j)}(h``unsigned int type``h]j)}(hjͩh]hunsigned int type}(hjϩhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj˩ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chK=hjǩubj)}(hhh]j)}(h7IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.hh]h7IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chKh]hstruct irq_desc *desc}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMZhj8ubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjShMZhjTubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhjShMZhj5ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjyh]h Description}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjwubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM\hjubj)}(hSimple interrupts are either sent from a demultiplexing interrupt handler or come from hardware, where no interrupt hardware control is necessary.h]hSimple interrupts are either sent from a demultiplexing interrupt handler or come from hardware, where no interrupt hardware control is necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM[hjubj)}(h**Note**h]jz)}(hjh]hNote}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM_hjubj)}(hUThe caller is expected to handle the ack, clear, mask and unmask issues if necessary.h]hUThe caller is expected to handle the ack, clear, mask and unmask issues if necessary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM`hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!handle_untracked_irq (C function)c.handle_untracked_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h1void handle_untracked_irq (struct irq_desc *desc)h]j])}(h0void handle_untracked_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMvubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMvubj)}(hhandle_untracked_irqh]j)}(hhandle_untracked_irqh]hhandle_untracked_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMvubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjBmodnameN classnameNjj)}j]j)}jjsbc.handle_untracked_irqasbuh1hhjubju)}(h h]h }(hj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMvubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjݰhhhjhMvubah}(h]jذah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMvhjڰhhubjI)}(hhh]j)}(h!Simple and software-decoded IRQs.h]h!Simple and software-decoded IRQs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMvhjhhubah}(h]h ]h"]h$]h&]uh1jHhjڰhhhjhMvubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Untracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. IRQ's handled through here are not subjected to stats tracking, randomness, or spurious interrupt detection. **Note** Like handle_simple_irq, the caller is expected to handle the ack, clear, mask and unmask issues if necessary.h](j)}(h**Parameters**h]jz)}(hjDZh]h Parameters}(hjɱhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjűubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMzhjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMwhjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMwhjݱubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj!h]h Description}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMyhjubj)}(hXUntracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. IRQ's handled through here are not subjected to stats tracking, randomness, or spurious interrupt detection.h]hXUntracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. IRQ’s handled through here are not subjected to stats tracking, randomness, or spurious interrupt detection.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMxhjubj)}(h**Note**h]jz)}(hjHh]hNote}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjFubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM~hjubj)}(hmLike handle_simple_irq, the caller is expected to handle the ack, clear, mask and unmask issues if necessary.h]hmLike handle_simple_irq, the caller is expected to handle the ack, clear, mask and unmask issues if necessary.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_level_irq (C function)c.handle_level_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h-void handle_level_irq (struct irq_desc *desc)h]j])}(h,void handle_level_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hhandle_level_irqh]j)}(hhandle_level_irqh]hhandle_level_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjʲhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƲubju)}(h h]h }(hjײhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjƲubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_level_irqasbuh1hhjƲubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjƲubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƲubj)}(hdesch]hdesc}(hj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjƲubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj²ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(hLevel type irq handlerh]hLevel type irq handler}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjJhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjejkjejljmjnuh1jQhhhjLahNhNubjp)}(hX\**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Level type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.h](j)}(h**Parameters**h]jz)}(hjoh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjmubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjiubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(h**Description**h]jz)}(hjɳh]h Description}(hj˳hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjdzubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjiubj)}(hLevel type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.h]hLevel type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.}(hj߳hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjiubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_fasteoi_irq (C function)c.handle_fasteoi_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h/void handle_fasteoi_irq (struct irq_desc *desc)h]j])}(h.void handle_fasteoi_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj hhhjhMubj)}(hhandle_fasteoi_irqh]j)}(hhandle_fasteoi_irqh]hhandle_fasteoi_irq}(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj hhhjhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubju)}(h h]h }(hjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjGubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjkmodnameN classnameNjj)}j]j)}jj1sbc.handle_fasteoi_irqasbuh1hhjGubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjGubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjCubah}(h]h ]h"]h$]h&]hhuh1jhj hhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h'irq handler for transparent controllersh]h'irq handler for transparent controllers}(hjδhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj˴hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hXN**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Only a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj ubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$hMhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj$hMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjJh]h Description}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjHubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h]hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_fasteoi_nmi (C function)c.handle_fasteoi_nmihNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h/void handle_fasteoi_nmi (struct irq_desc *desc)h]j])}(h.void handle_fasteoi_nmi(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hhandle_fasteoi_nmih]j)}(hhandle_fasteoi_nmih]hhandle_fasteoi_nmi}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hj̵hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȵubju)}(h h]h }(hjٵhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjȵubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_fasteoi_nmiasbuh1hhjȵubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjȵubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȵubj)}(hdesch]hdesc}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjȵubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjĵubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM hjhhubjI)}(hhh]j)}(h#irq handler for NMI interrupt linesh]h#irq handler for NMI interrupt lines}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM hjLhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjgjkjgjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** A simple NMI-safe handler, considering the restrictions from request_nmi. Only a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](j)}(h**Parameters**h]jz)}(hjqh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjoubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjkubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM hjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjkubj)}(h**Description**h]jz)}(hj˶h]h Description}(hjͶhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjɶubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM hjkubj)}(hX*A simple NMI-safe handler, considering the restrictions from request_nmi. Only a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](j)}(hIA simple NMI-safe handler, considering the restrictions from request_nmi.h]hIA simple NMI-safe handler, considering the restrictions from request_nmi.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM hjubj)}(hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h]hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjkubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_edge_irq (C function)c.handle_edge_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h,void handle_edge_irq (struct irq_desc *desc)h]j])}(h+void handle_edge_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hj)hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj%hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM+ubju)}(h h]h }(hj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%hhhj7hM+ubj)}(hhandle_edge_irqh]j)}(hhandle_edge_irqh]hhandle_edge_irq}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ](jjeh"]h$]h&]hhuh1jhj%hhhj7hM+ubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjfhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubju)}(h h]h }(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjLsbc.handle_edge_irqasbuh1hhjbubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj^ubah}(h]h ]h"]h$]h&]hhuh1jhj%hhhj7hM+ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj!hhhj7hM+ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj7hM+hjhhubjI)}(hhh]j)}(hedge type IRQ handlerh]hedge type IRQ handler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM+hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj7hM+ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Interrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.h](j)}(h**Parameters**h]jz)}(hj h]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM/hjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hj*h]hstruct irq_desc *desc}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM,hj$ubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?hM,hj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hM,hj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjeh]h Description}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjcubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM.hjubj)}(hXbInterrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.h]hXbInterrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM-hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#handle_fasteoi_ack_irq (C function)c.handle_fasteoi_ack_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h3void handle_fasteoi_ack_irq (struct irq_desc *desc)h]j])}(h2void handle_fasteoi_ack_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMlubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMlubj)}(hhandle_fasteoi_ack_irqh]j)}(hhandle_fasteoi_ack_irqh]hhandle_fasteoi_ack_irq}(hj˸hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjǸubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMlubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jj͸sbc.handle_fasteoi_ack_irqasbuh1hhjubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj߸ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMlubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMlubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMlhjhhubjI)}(hhh]j)}(hAirq handler for edge hierarchy stacked on transparent controllersh]hAirq handler for edge hierarchy stacked on transparent controllers}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMlhjghhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMlubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMphjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMohjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjĹhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMohjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMohjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMqhjubj)}(h|Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.h]h|Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMphjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$handle_fasteoi_mask_irq (C function)c.handle_fasteoi_mask_irqhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h4void handle_fasteoi_mask_irq (struct irq_desc *desc)h]j])}(h3void handle_fasteoi_mask_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hj+hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj'hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj'hhhj9hMubj)}(hhandle_fasteoi_mask_irqh]j)}(hhandle_fasteoi_mask_irqh]hhandle_fasteoi_mask_irq}(hjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ](jjeh"]h$]h&]hhuh1jhj'hhhj9hMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubju)}(h h]h }(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjNsbc.handle_fasteoi_mask_irqasbuh1hhjdubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj`ubah}(h]h ]h"]h$]h&]hhuh1jhj'hhhj9hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj#hhhj9hMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj9hMhj hhubjI)}(hhh]j)}(hBirq handler for level hierarchy stacked on transparent controllersh]hBirq handler for level hierarchy stacked on transparent controllers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhj hhhj9hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.h](j)}(h**Parameters**h]jz)}(hj h]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hj,h]hstruct irq_desc *desc}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj&ubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAhMhjBubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhjAhMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjgh]h Description}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjeubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hLike handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.h]hLike handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&irq_chip_set_parent_state (C function)c.irq_chip_set_parent_statehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h]int irq_chip_set_parent_state (struct irq_data *data, enum irqchip_irq_state which, bool val)h]j])}(h\int irq_chip_set_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool val)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_set_parent_stateh]j)}(hirq_chip_set_parent_stateh]hirq_chip_set_parent_state}(hjͻhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjɻubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h?(struct irq_data *data, enum irqchip_irq_state which, bool val)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj modnameN classnameNjj)}j]j)}jjϻsbc.irq_chip_set_parent_stateasbuh1hhjubju)}(h h]h }(hj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum irqchip_irq_state whichh](j)}(hj%h]henum}(hj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubju)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj{modnameN classnameNjj)}j]j#c.irq_chip_set_parent_stateasbuh1hhjWubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubj)}(hwhichh]hwhich}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool valh](jc)}(hjah]hbool}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj˼hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hvalh]hval}(hjټhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h$set the state of a parent interrupt.h]h$set the state of a parent interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hX)**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) ``bool val`` Value corresponding to **which** **Description** Conditional success, if the underlying irqchip does not implement it.h](j)}(h**Parameters**h]jz)}(hj%h]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj#ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjDh]hstruct irq_data *data}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj>ubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYhMhjZubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhjYhMhj;ubj)}(hO``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) h](j)}(h ``enum irqchip_irq_state which``h]j)}(hj}h]henum irqchip_irq_state which}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjwubj)}(hhh]j)}(h-State to be restored (one of IRQCHIP_STATE_*)h]h-State to be restored (one of IRQCHIP_STATE_*)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjhMhj;ubj)}(h.``bool val`` Value corresponding to **which** h](j)}(h ``bool val``h]j)}(hjh]hbool val}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h Value corresponding to **which**h](hValue corresponding to }(hjϽhhhNhNubjz)}(h **which**h]hwhich}(hj׽hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjϽubeh}(h]h ]h"]h$]h&]uh1jhj˽hMhj̽ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj˽hMhj;ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hEConditional success, if the underlying irqchip does not implement it.h]hEConditional success, if the underlying irqchip does not implement it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&irq_chip_get_parent_state (C function)c.irq_chip_get_parent_statehNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h`int irq_chip_get_parent_state (struct irq_data *data, enum irqchip_irq_state which, bool *state)h]j])}(h_int irq_chip_get_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool *state)h](jc)}(hinth]hint}(hjDhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj@hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@hhhjRhMubj)}(hirq_chip_get_parent_stateh]j)}(hirq_chip_get_parent_stateh]hirq_chip_get_parent_state}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubah}(h]h ](jjeh"]h$]h&]hhuh1jhj@hhhjRhMubj)}(hB(struct irq_data *data, enum irqchip_irq_state which, bool *state)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjgsbc.irq_chip_get_parent_stateasbuh1hhj}ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubj )}(hj h]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubj)}(hdatah]hdata}(hjھhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjyubj)}(henum irqchip_irq_state whichh](j)}(hj%h]henum}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]jc.irq_chip_get_parent_stateasbuh1hhjubju)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hwhichh]hwhich}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjyubj)}(h bool *stateh](jc)}(hjah]hbool}(hjVhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjRubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjRubj )}(hj h]h*}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubj)}(hstateh]hstate}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjyubeh}(h]h ]h"]h$]h&]hhuh1jhj@hhhjRhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj<hhhjRhMubah}(h]j7ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjRhMhj9hhubjI)}(hhh]j)}(h$get the state of a parent interrupt.h]h$get the state of a parent interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhj9hhhjRhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hXD**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``enum irqchip_irq_state which`` one of IRQCHIP_STATE_* the caller wants to know ``bool *state`` a pointer to a boolean where the state is to be stored **Description** Conditional success, if the underlying irqchip does not implement it.h](j)}(h**Parameters**h]jz)}(hjʿh]h Parameters}(hj̿hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjȿubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjĿubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hQ``enum irqchip_irq_state which`` one of IRQCHIP_STATE_* the caller wants to know h](j)}(h ``enum irqchip_irq_state which``h]j)}(hj"h]henum irqchip_irq_state which}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h/one of IRQCHIP_STATE_* the caller wants to knowh]h/one of IRQCHIP_STATE_* the caller wants to know}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7hMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubj)}(hG``bool *state`` a pointer to a boolean where the state is to be stored h](j)}(h``bool *state``h]j)}(hj[h]h bool *state}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjUubj)}(hhh]j)}(h6a pointer to a boolean where the state is to be storedh]h6a pointer to a boolean where the state is to be stored}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjphMhjqubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjphMhjubeh}(h]h ]h"]h$]h&]uh1jhjĿubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjĿubj)}(hEConditional success, if the underlying irqchip does not implement it.h]hEConditional success, if the underlying irqchip does not implement it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjĿubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_shutdown_parent (C function)c.irq_chip_shutdown_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h5void irq_chip_shutdown_parent (struct irq_data *data)h]j])}(h4void irq_chip_shutdown_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_shutdown_parenth]j)}(hirq_chip_shutdown_parenth]hirq_chip_shutdown_parent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj8modnameN classnameNjj)}j]j)}jjsbc.irq_chip_shutdown_parentasbuh1hhjubju)}(h h]h }(hjVhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(hShutdown the parent interrupth]hShutdown the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data **Description** Invokes the irq_shutdown() callback of the parent if available or falls back to irq_chip_disable_parent().h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hjInvokes the irq_shutdown() callback of the parent if available or falls back to irq_chip_disable_parent().h]hjInvokes the irq_shutdown() callback of the parent if available or falls back to irq_chip_disable_parent().}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_chip_startup_parent (C function)c.irq_chip_startup_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hsbc.irq_chip_eoi_parentasbuh1hhjTubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjTubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjPubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj)hMUubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj)hMUubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj)hMUhjhhubjI)}(hhh]j)}(h"Invoke EOI on the parent interrupth]h"Invoke EOI on the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMUhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj)hMUubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMYhjubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM[hjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMVhj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj1hM[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM)irq_chip_set_affinity_parent (C function)c.irq_chip_set_affinity_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h`int irq_chip_set_affinity_parent (struct irq_data *data, const struct cpumask *dest, bool force)h]j])}(h_int irq_chip_set_affinity_parent(struct irq_data *data, const struct cpumask *dest, bool force)h](jc)}(hinth]hint}(hjvhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjrhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM`ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjrhhhjhM`ubj)}(hirq_chip_set_affinity_parenth]j)}(hirq_chip_set_affinity_parenth]hirq_chip_set_affinity_parent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjrhhhjhM`ubj)}(h?(struct irq_data *data, const struct cpumask *dest, bool force)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_set_affinity_parentasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hconst struct cpumask *desth](j)}(hjh]hconst}(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubju)}(h h]h }(hj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj!ubj)}(hjh]hstruct}(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubju)}(h h]h }(hjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj!ubh)}(hhh]j)}(hcpumaskh]hcpumask}(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj`modnameN classnameNjj)}j]jc.irq_chip_set_affinity_parentasbuh1hhj!ubju)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj!ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubj)}(hdesth]hdest}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h bool forceh](jc)}(hjah]hbool}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hforceh]hforce}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjrhhhjhM`ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjnhhhjhM`ubah}(h]jiah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM`hjkhhubjI)}(hhh]j)}(h$Set affinity on the parent interrupth]h$Set affinity on the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chM`hjhhubah}(h]h ]h"]h$]h&]uh1jHhjkhhhjhM`ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj jkj jljmjnuh1jQhhhjLahNhNubjp)}(hX **Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``const struct cpumask *dest`` The affinity mask to set ``bool force`` Flag to enforce setting (disable online checks) **Description** Conditional, as the underlying parent chip might not implement it.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMdhjubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hj6h]hstruct irq_data *data}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMahj0ubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKhMahjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhMahj-ubj)}(h8``const struct cpumask *dest`` The affinity mask to set h](j)}(h``const struct cpumask *dest``h]j)}(hjoh]hconst struct cpumask *dest}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMbhjiubj)}(hhh]j)}(hThe affinity mask to seth]hThe affinity mask to set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMbhjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjhMbhj-ubj)}(h?``bool force`` Flag to enforce setting (disable online checks) h](j)}(h``bool force``h]j)}(hjh]h bool force}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMchjubj)}(hhh]j)}(h/Flag to enforce setting (disable online checks)h]h/Flag to enforce setting (disable online checks)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMchjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMchj-ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMehjubj)}(hBConditional, as the underlying parent chip might not implement it.h]hBConditional, as the underlying parent chip might not implement it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMdhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_set_type_parent (C function)c.irq_chip_set_type_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hGint irq_chip_set_type_parent (struct irq_data *data, unsigned int type)h]j])}(hFint irq_chip_set_type_parent(struct irq_data *data, unsigned int type)h](jc)}(hinth]hint}(hj(hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj$hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMsubju)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$hhhj6hMsubj)}(hirq_chip_set_type_parenth]j)}(hirq_chip_set_type_parenth]hirq_chip_set_type_parent}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjEubah}(h]h ](jjeh"]h$]h&]hhuh1jhj$hhhj6hMsubj)}(h*(struct irq_data *data, unsigned int type)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubju)}(h h]h }(hjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjKsbc.irq_chip_set_type_parentasbuh1hhjaubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj]ubj)}(hunsigned int typeh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(htypeh]htype}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj]ubeh}(h]h ]h"]h$]h&]hhuh1jhj$hhhj6hMsubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj hhhj6hMsubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj6hMshjhhubjI)}(hhh]j)}(h$Set IRQ type on the parent interrupth]h$Set IRQ type on the parent interrupt}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMshj6hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj6hMsubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjQjkjQjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``unsigned int type`` IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h **Description** Conditional, as the underlying parent chip might not implement it.h](j)}(h**Parameters**h]jz)}(hj[h]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjYubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMwhjUubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjzh]hstruct irq_data *data}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMthjtubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMthjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhMthjqubj)}(hN``unsigned int type`` IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h h](j)}(h``unsigned int type``h]j)}(hjh]hunsigned int type}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMuhjubj)}(hhh]j)}(h7IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.hh]h7IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMuhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMuhjqubeh}(h]h ]h"]h$]h&]uh1jhjUubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMwhjUubj)}(hBConditional, as the underlying parent chip might not implement it.h]hBConditional, as the underlying parent chip might not implement it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMvhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM)irq_chip_retrigger_hierarchy (C function)c.irq_chip_retrigger_hierarchyhNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h8int irq_chip_retrigger_hierarchy (struct irq_data *data)h]j])}(h7int irq_chip_retrigger_hierarchy(struct irq_data *data)h](jc)}(hinth]hint}(hj3hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj/hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj/hhhjAhMubj)}(hirq_chip_retrigger_hierarchyh]j)}(hirq_chip_retrigger_hierarchyh]hirq_chip_retrigger_hierarchy}(hjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubah}(h]h ](jjeh"]h$]h&]hhuh1jhj/hhhjAhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubju)}(h h]h }(hj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjVsbc.irq_chip_retrigger_hierarchyasbuh1hhjlubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjlubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjhubah}(h]h ]h"]h$]h&]hhuh1jhj/hhhjAhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj+hhhjAhMubah}(h]j&ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjAhMhj(hhubjI)}(hhh]j)}(h"Retrigger an interrupt in hardwareh]h"Retrigger an interrupt in hardware}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhj(hhhjAhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj jkj jljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data **Description** Iterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hj4h]hstruct irq_data *data}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj.ubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIhMhjJubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhjIhMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjoh]h Description}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjmubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hzIterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.h]hzIterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM.irq_chip_set_vcpu_affinity_parent (C function)#c.irq_chip_set_vcpu_affinity_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hNint irq_chip_set_vcpu_affinity_parent (struct irq_data *data, void *vcpu_info)h]j])}(hMint irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(h!irq_chip_set_vcpu_affinity_parenth]j)}(h!irq_chip_set_vcpu_affinity_parenth]h!irq_chip_set_vcpu_affinity_parent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h((struct irq_data *data, void *vcpu_info)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb#c.irq_chip_set_vcpu_affinity_parentasbuh1hhjubju)}(h h]h }(hj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hvoid *vcpu_infoh](jc)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_ubju)}(h h]h }(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubj)}(h vcpu_infoh]h vcpu_info}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h)Set vcpu affinity on the parent interrupth]h)Set vcpu affinity on the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``void *vcpu_info`` The vcpu affinity informationh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubj)}(h1``void *vcpu_info`` The vcpu affinity informationh](j)}(h``void *vcpu_info``h]j)}(hj0h]hvoid *vcpu_info}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhj*ubj)}(hhh]j)}(hThe vcpu affinity informationh]hThe vcpu affinity information}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjFubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_set_wake_parent (C function)c.irq_chip_set_wake_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(hEint irq_chip_set_wake_parent (struct irq_data *data, unsigned int on)h]j])}(hDint irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_set_wake_parenth]j)}(hirq_chip_set_wake_parenth]hirq_chip_set_wake_parent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h((struct irq_data *data, unsigned int on)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_set_wake_parentasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int onh](jc)}(hunsignedh]hunsigned}(hj9hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj5ubju)}(h h]h }(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubjc)}(hinth]hint}(hjUhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj5ubju)}(h h]h }(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubj)}(honh]hon}(hjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]j}ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h)Set/reset wake-up on the parent interrupth]h)Set/reset wake-up on the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``unsigned int on`` Whether to set or reset the wake-up capability of this irq **Description** Conditional, as the underlying parent chip might not implement it.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hO``unsigned int on`` Whether to set or reset the wake-up capability of this irq h](j)}(h``unsigned int on``h]j)}(hjh]hunsigned int on}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h:Whether to set or reset the wake-up capability of this irqh]h:Whether to set or reset the wake-up capability of this irq}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*hMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj*hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjPh]h Description}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hBConditional, as the underlying parent chip might not implement it.h]hBConditional, as the underlying parent chip might not implement it.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM.irq_chip_request_resources_parent (C function)#c.irq_chip_request_resources_parenthNtauh1j@hjLahhhNhNubjR)}(hhh](jW)}(h=int irq_chip_request_resources_parent (struct irq_data *data)h]j])}(hvoid irq_chip_release_resources_parent (struct irq_data *data)h]j])}(h=void irq_chip_release_resources_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(h!irq_chip_release_resources_parenth]j)}(h!irq_chip_release_resources_parenth]h!irq_chip_release_resources_parent}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubju)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjHubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjMmodnameN classnameNjj)}j]j)}jjsb#c.irq_chip_release_resources_parentasbuh1hhj)ubju)}(h h]h }(hjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)ubj )}(hj h]h*}(hjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj%ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h)Release resources on the parent interrupth]h)Release resources on the parent interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhjLahNhNubjp)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:507: ./kernel/irq/chip.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johjLahhhNhNubeh}(h]public-functions-providedah ]h"]public functions providedah$]h&]uh1jLhjNhhhjahMubjM)}(hhh](jR)}(hInternal Functions Providedh]hInternal Functions Provided}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jQhj:hhhjahMubj)}(hPThis chapter contains the autogenerated documentation of the internal functions.h]hPThis chapter contains the autogenerated documentation of the internal functions.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhj:hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_get_nr_irqs (C function)c.irq_get_nr_irqshNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h#unsigned int irq_get_nr_irqs (void)h]j])}(h"unsigned int irq_get_nr_irqs(void)h](jc)}(hunsignedh]hunsigned}(hjrhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjnhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjnhhhjhKubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjnhhhjhKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjnhhhjhKubj)}(hirq_get_nr_irqsh]j)}(hirq_get_nr_irqsh]hirq_get_nr_irqs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjnhhhjhKubj)}(h(void)h]j)}(hvoidh]jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubah}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjnhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjjhhhjhKubah}(h]jeah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKhjghhubjI)}(hhh]j)}(h-Number of interrupts supported by the system.h]h-Number of interrupts supported by the system.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjhhubah}(h]h ]h"]h$]h&]uh1jHhjghhhjhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj jkj jljmjnuh1jQhhhj:hNhNubjp)}(h'**Parameters** ``void`` no argumentsh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjubj)}(hhh]j)}(h``void`` no argumentsh](j)}(h``void``h]j)}(hj6h]hvoid}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhj0ubj)}(hhh]j)}(h no argumentsh]h no arguments}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjLubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jhjKhKhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_nr_irqs (C function)c.irq_set_nr_irqshNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h.unsigned int irq_set_nr_irqs (unsigned int nr)h]j])}(h-unsigned int irq_set_nr_irqs(unsigned int nr)h](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhjhKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubj)}(hirq_set_nr_irqsh]j)}(hirq_set_nr_irqsh]hirq_set_nr_irqs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubj)}(h(unsigned int nr)h]j)}(hunsigned int nrh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hnrh]hnr}(hj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKhjhhubjI)}(hhh]j)}(h5Set the number of interrupts supported by the system.h]h5Set the number of interrupts supported by the system.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjHhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjcjkjcjljmjnuh1jQhhhj:hNhNubjp)}(hT**Parameters** ``unsigned int nr`` New number of interrupts. **Return** **nr**.h](j)}(h**Parameters**h]jz)}(hjmh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjkubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjgubj)}(hhh]j)}(h.``unsigned int nr`` New number of interrupts. h](j)}(h``unsigned int nr``h]j)}(hjh]hunsigned int nr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjubj)}(hhh]j)}(hNew number of interrupts.h]hNew number of interrupts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h **Return**h]jz)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjgubj)}(h**nr**.h](jz)}(h**nr**h]hnr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chKhjgubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMgeneric_handle_irq (C function)c.generic_handle_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h)int generic_handle_irq (unsigned int irq)h]j])}(h(int generic_handle_irq(unsigned int irq)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj(hMubj)}(hgeneric_handle_irqh]j)}(hgeneric_handle_irqh]hgeneric_handle_irq}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj(hMubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjWhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjSubju)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjSubjc)}(hinth]hint}(hjshhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjSubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjSubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjOubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj(hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj(hMubah}(h]j ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj(hMhjhhubjI)}(hhh]j)}(h'Invoke the handler for a particular irqh]h'Invoke the handler for a particular irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.c hMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj(hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``unsigned int irq`` The irq number to handle **Return** 0 on success, or -EINVAL if conversion has failed **Description** This function must be called from an IRQ context with irq regs initialized.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h.``unsigned int irq`` The irq number to handle h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(hThe irq number to handleh]hThe irq number to handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h **Return**h]jz)}(hj5h]hReturn}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj3ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(h**Description**h]jz)}(hj\h]h Description}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hKThis function must be called from an IRQ context with irq regs initialized.h]j)}(hKThis function must be called from an IRQ context with irq regs initialized.h]hKThis function must be called from an IRQ context with irq regs initialized.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjrubah}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$generic_handle_irq_safe (C function)c.generic_handle_irq_safehNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h.int generic_handle_irq_safe (unsigned int irq)h]j])}(h-int generic_handle_irq_safe(unsigned int irq)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hgeneric_handle_irq_safeh]j)}(hgeneric_handle_irq_safeh]hgeneric_handle_irq_safe}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(h9Invoke the handler for a particular irq from any context.h]h9Invoke the handler for a particular irq from any context.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjGhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjbjkjbjljmjnuh1jQhhhj:hNhNubjp)}(hX?**Parameters** ``unsigned int irq`` The irq number to handle **Return** 0 on success, a negative value on error. **Description** This function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.h](j)}(h**Parameters**h]jz)}(hjlh]h Parameters}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjfubj)}(hhh]j)}(h.``unsigned int irq`` The irq number to handle h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(hThe irq number to handleh]hThe irq number to handle}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(h **Return**h]jz)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjfubj)}(h(0 on success, a negative value on error.h]h(0 on success, a negative value on error.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjfubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjfubj)}(hThis function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.h]hThis function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjfubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&generic_handle_domain_irq (C function)c.generic_handle_domain_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hPint generic_handle_domain_irq (struct irq_domain *domain, irq_hw_number_t hwirq)h]j])}(hOint generic_handle_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)h](jc)}(hinth]hint}(hj2hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj.hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj.hhhj@hMubj)}(hgeneric_handle_domain_irqh]j)}(hgeneric_handle_domain_irqh]hgeneric_handle_domain_irq}(hjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ](jjeh"]h$]h&]hhuh1jhj.hhhj@hMubj)}(h2(struct irq_domain *domain, irq_hw_number_t hwirq)h](j)}(hstruct irq_domain *domainh](j)}(hjh]hstruct}(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubju)}(h h]h }(hj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjkubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjUsbc.generic_handle_domain_irqasbuh1hhjkubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjkubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubj)}(hdomainh]hdomain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjgubj)}(hirq_hw_number_t hwirqh](h)}(hhh]j)}(hirq_hw_number_th]hirq_hw_number_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]jc.generic_handle_domain_irqasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhwirqh]hhwirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjgubeh}(h]h ]h"]h$]h&]hhuh1jhj.hhhj@hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj*hhhj@hMubah}(h]j%ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj@hMhj'hhubjI)}(hhh]j)}(h6Invoke the handler for a HW irq belonging to a domain.h]h6Invoke the handler for a HW irq belonging to a domain.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj7hhubah}(h]h ]h"]h$]h&]uh1jHhj'hhhj@hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjRjkjRjljmjnuh1jQhhhj:hNhNubjp)}(hXX**Parameters** ``struct irq_domain *domain`` The domain where to perform the lookup ``irq_hw_number_t hwirq`` The HW irq number to convert to a logical one **Return** 0 on success, or -EINVAL if conversion has failed **Description** This function must be called from an IRQ context with irq regs initialized.h](j)}(h**Parameters**h]jz)}(hj\h]h Parameters}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjZubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjVubj)}(hhh](j)}(hE``struct irq_domain *domain`` The domain where to perform the lookup h](j)}(h``struct irq_domain *domain``h]j)}(hj{h]hstruct irq_domain *domain}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjuubj)}(hhh]j)}(h&The domain where to perform the lookuph]h&The domain where to perform the lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhMhjrubj)}(hH``irq_hw_number_t hwirq`` The HW irq number to convert to a logical one h](j)}(h``irq_hw_number_t hwirq``h]j)}(hjh]hirq_hw_number_t hwirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h-The HW irq number to convert to a logical oneh]h-The HW irq number to convert to a logical one}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjrubeh}(h]h ]h"]h$]h&]uh1jhjVubj)}(h **Return**h]jz)}(hjh]hReturn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjVubj)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjVubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjVubj)}(hKThis function must be called from an IRQ context with irq regs initialized.h]j)}(hKThis function must be called from an IRQ context with irq regs initialized.h]hKThis function must be called from an IRQ context with irq regs initialized.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj,ubah}(h]h ]h"]h$]h&]uh1jhj>hMhjVubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&generic_handle_domain_nmi (C function)c.generic_handle_domain_nmihNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hPint generic_handle_domain_nmi (struct irq_domain *domain, irq_hw_number_t hwirq)h]j])}(hOint generic_handle_domain_nmi(struct irq_domain *domain, irq_hw_number_t hwirq)h](jc)}(hinth]hint}(hjehhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjahhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjahhhjshMubj)}(hgeneric_handle_domain_nmih]j)}(hgeneric_handle_domain_nmih]hgeneric_handle_domain_nmi}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjahhhjshMubj)}(h2(struct irq_domain *domain, irq_hw_number_t hwirq)h](j)}(hstruct irq_domain *domainh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.generic_handle_domain_nmiasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdomainh]hdomain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hirq_hw_number_t hwirqh](h)}(hhh]j)}(hirq_hw_number_th]hirq_hw_number_t}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]jc.generic_handle_domain_nmiasbuh1hhjubju)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhwirqh]hhwirq}(hjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjahhhjshMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj]hhhjshMubah}(h]jXah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjshMhjZhhubjI)}(hhh]j)}(h6Invoke the handler for a HW nmi belonging to a domain.h]h6Invoke the handler for a HW nmi belonging to a domain.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjjhhubah}(h]h ]h"]h$]h&]uh1jHhjZhhhjshMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(hXX**Parameters** ``struct irq_domain *domain`` The domain where to perform the lookup ``irq_hw_number_t hwirq`` The HW irq number to convert to a logical one **Return** 0 on success, or -EINVAL if conversion has failed **Description** This function must be called from an NMI context with irq regs initialized.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh](j)}(hE``struct irq_domain *domain`` The domain where to perform the lookup h](j)}(h``struct irq_domain *domain``h]j)}(hjh]hstruct irq_domain *domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h&The domain where to perform the lookuph]h&The domain where to perform the lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(hH``irq_hw_number_t hwirq`` The HW irq number to convert to a logical one h](j)}(h``irq_hw_number_t hwirq``h]j)}(hjh]hirq_hw_number_t hwirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h-The HW irq number to convert to a logical oneh]h-The HW irq number to convert to a logical one}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h **Return**h]jz)}(hj"h]hReturn}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(h**Description**h]jz)}(hjIh]h Description}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjGubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hKThis function must be called from an NMI context with irq regs initialized.h]j)}(hKThis function must be called from an NMI context with irq regs initialized.h]hKThis function must be called from an NMI context with irq regs initialized.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj_ubah}(h]h ]h"]h$]h&]uh1jhjqhMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM,generic_handle_demux_domain_irq (C function)!c.generic_handle_demux_domain_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hWbool generic_handle_demux_domain_irq (struct irq_domain *domain, irq_hw_number_t hwirq)h]j])}(hVbool generic_handle_demux_domain_irq(struct irq_domain *domain, irq_hw_number_t hwirq)h](jc)}(hjah]hbool}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM?ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM?ubj)}(hgeneric_handle_demux_domain_irqh]j)}(hgeneric_handle_demux_domain_irqh]hgeneric_handle_demux_domain_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM?ubj)}(h2(struct irq_domain *domain, irq_hw_number_t hwirq)h](j)}(hstruct irq_domain *domainh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb!c.generic_handle_demux_domain_irqasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdomainh]hdomain}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hirq_hw_number_t hwirqh](h)}(hhh]j)}(hirq_hw_number_th]hirq_hw_number_t}(hjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjKmodnameN classnameNjj)}j]j!c.generic_handle_demux_domain_irqasbuh1hhjBubju)}(h h]h }(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjBubj)}(hhwirqh]hhwirq}(hjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM?ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM?ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhM?hjhhubjI)}(hhh]j)}(hGInvoke the handler for a hardware interrupt of a demultiplexing domain.h]hGInvoke the handler for a hardware interrupt of a demultiplexing domain.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM?hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhM?ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``struct irq_domain *domain`` The domain where to perform the lookup ``irq_hw_number_t hwirq`` The hardware interrupt number to convert to a logical one **Return** True on success, or false if lookup has failedh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMChjubj)}(hhh](j)}(hE``struct irq_domain *domain`` The domain where to perform the lookup h](j)}(h``struct irq_domain *domain``h]j)}(hjh]hstruct irq_domain *domain}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMAhjubj)}(hhh]j)}(h&The domain where to perform the lookuph]h&The domain where to perform the lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMAhjubj)}(hT``irq_hw_number_t hwirq`` The hardware interrupt number to convert to a logical one h](j)}(h``irq_hw_number_t hwirq``h]j)}(hjh]hirq_hw_number_t hwirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMBhjubj)}(hhh]j)}(h9The hardware interrupt number to convert to a logical oneh]h9The hardware interrupt number to convert to a logical one}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.hMBhj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj.hMBhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h **Return**h]jz)}(hjTh]hReturn}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjRubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMDhjubj)}(h.True on success, or false if lookup has failedh]h.True on success, or false if lookup has failed}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMDhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_free_descs (C function)c.irq_free_descshNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h9void irq_free_descs (unsigned int from, unsigned int cnt)h]j])}(h8void irq_free_descs(unsigned int from, unsigned int cnt)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMYubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMYubj)}(hirq_free_descsh]j)}(hirq_free_descsh]hirq_free_descs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMYubj)}(h%(unsigned int from, unsigned int cnt)h](j)}(hunsigned int fromh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hfromh]hfrom}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int cnth](jc)}(hunsignedh]hunsigned}(hj'hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj#ubju)}(h h]h }(hj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubjc)}(hinth]hint}(hjChhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj#ubju)}(h h]h }(hjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubj)}(hcnth]hcnt}(hj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMYubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMYubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMYhjhhubjI)}(hhh]j)}(hfree irq descriptorsh]hfree irq descriptors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMYhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMYubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h|**Parameters** ``unsigned int from`` Start of descriptor range ``unsigned int cnt`` Number of consecutive irqs to freeh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM]hjubj)}(hhh](j)}(h0``unsigned int from`` Start of descriptor range h](j)}(h``unsigned int from``h]j)}(hjh]hunsigned int from}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMZhjubj)}(hhh]j)}(hStart of descriptor rangeh]hStart of descriptor range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMZhjubj)}(h7``unsigned int cnt`` Number of consecutive irqs to freeh](j)}(h``unsigned int cnt``h]j)}(hjh]hunsigned int cnt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM\hjubj)}(hhh]j)}(h"Number of consecutive irqs to freeh]h"Number of consecutive irqs to free}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM\hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM__irq_alloc_descs (C function)c.__irq_alloc_descshNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hint __ref __irq_alloc_descs (int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h]j])}(hint __ref __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h](jc)}(hinth]hint}(hj]hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjYhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMkubju)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjYhhhjkhMkubh__ref}(hjYhhhNhNubju)}(h h]h }(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjYhhhjkhMkubj)}(h__irq_alloc_descsh]j)}(h__irq_alloc_descsh]h__irq_alloc_descs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjYhhhjkhMkubj)}(hx(int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h](j)}(hint irqh](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int fromh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hfromh]hfrom}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int cnth](jc)}(hunsignedh]hunsigned}(hj2hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj.ubju)}(h h]h }(hj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj.ubjc)}(hinth]hint}(hjNhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj.ubju)}(h h]h }(hj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj.ubj)}(hcnth]hcnt}(hjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hint nodeh](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hnodeh]hnode}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hmoduleh]hmodule}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.__irq_alloc_descsasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h(const struct irq_affinity_desc *affinityh](j)}(hjh]hconst}(hj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubju)}(h h]h }(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubj)}(hjh]hstruct}(hjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubju)}(h h]h }(hjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubh)}(hhh]j)}(hirq_affinity_desch]hirq_affinity_desc}(hjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjemodnameN classnameNjj)}j]jc.__irq_alloc_descsasbuh1hhj&ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubj)}(haffinityh]haffinity}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjYhhhjkhMkubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjUhhhjkhMkubah}(h]jPah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjkhMkhjRhhubjI)}(hhh]j)}(h2allocate and initialize a range of irq descriptorsh]h2allocate and initialize a range of irq descriptors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMkhjhhubah}(h]h ]h"]h$]h&]uh1jHhjRhhhjkhMkubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(hXZ**Parameters** ``int irq`` Allocate for specific irq number if irq >= 0 ``unsigned int from`` Start the search from this irq number ``unsigned int cnt`` Number of consecutive irqs to allocate. ``int node`` Preferred node on which the irq descriptor should be allocated ``struct module *owner`` Owning module (can be NULL) ``const struct irq_affinity_desc *affinity`` Optional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to use **Description** Returns the first irq number or error codeh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMohjubj)}(hhh](j)}(h9``int irq`` Allocate for specific irq number if irq >= 0 h](j)}(h ``int irq``h]j)}(hjh]hint irq}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMlhjubj)}(hhh]j)}(h,Allocate for specific irq number if irq >= 0h]h,Allocate for specific irq number if irq >= 0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMlhjubj)}(h<``unsigned int from`` Start the search from this irq number h](j)}(h``unsigned int from``h]j)}(hj@h]hunsigned int from}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMmhj:ubj)}(hhh]j)}(h%Start the search from this irq numberh]h%Start the search from this irq number}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUhMmhjVubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhMmhjubj)}(h=``unsigned int cnt`` Number of consecutive irqs to allocate. h](j)}(h``unsigned int cnt``h]j)}(hjyh]hunsigned int cnt}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMnhjsubj)}(hhh]j)}(h'Number of consecutive irqs to allocate.h]h'Number of consecutive irqs to allocate.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMnhjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjhMnhjubj)}(hL``int node`` Preferred node on which the irq descriptor should be allocated h](j)}(h ``int node``h]j)}(hjh]hint node}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMohjubj)}(hhh]j)}(h>Preferred node on which the irq descriptor should be allocatedh]h>Preferred node on which the irq descriptor should be allocated}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMohjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMohjubj)}(h5``struct module *owner`` Owning module (can be NULL) h](j)}(h``struct module *owner``h]j)}(hjh]hstruct module *owner}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMphjubj)}(hhh]j)}(hOwning module (can be NULL)h]hOwning module (can be NULL)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMphjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMphjubj)}(h``const struct irq_affinity_desc *affinity`` Optional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to use h](j)}(h,``const struct irq_affinity_desc *affinity``h]j)}(hj$h]h(const struct irq_affinity_desc *affinity}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMshjubj)}(hhh]j)}(hOptional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to useh](h3Optional pointer to an affinity mask array of size }(hj=hhhNhNubjz)}(h**cnt**h]hcnt}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj=ubh^ which hints where the irq descriptors should be allocated and which default affinities to use}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMqhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj9hMshjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjrh]h Description}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjpubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMuhjubj)}(h*Returns the first irq number or error codeh]h*Returns the first irq number or error code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMthjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_get_next_irq (C function)c.irq_get_next_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h3unsigned int irq_get_next_irq (unsigned int offset)h]j])}(h2unsigned int irq_get_next_irq(unsigned int offset)h](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhjhMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_get_next_irqh]j)}(hirq_get_next_irqh]hirq_get_next_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(unsigned int offset)h]j)}(hunsigned int offseth](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubjc)}(hinth]hint}(hj,hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj ubju)}(h h]h }(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubj)}(hoffseth]hoffset}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(hget next allocated irq numberh]hget next allocated irq number}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjohhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``unsigned int offset`` where to start the search **Description** Returns next irq number after offset or nr_irqs if none is found.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h2``unsigned int offset`` where to start the search h](j)}(h``unsigned int offset``h]j)}(hjh]hunsigned int offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(hwhere to start the searchh]hwhere to start the search}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hAReturns next irq number after offset or nr_irqs if none is found.h]hAReturns next irq number after offset or nr_irqs if none is found.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMkstat_irqs_cpu (C function)c.kstat_irqs_cpuhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h7unsigned int kstat_irqs_cpu (unsigned int irq, int cpu)h]j])}(h6unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)h](jc)}(hunsignedh]hunsigned}(hj3hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj/hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj/hhhjAhMubjc)}(hinth]hint}(hjPhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj/hhhjAhMubju)}(h h]h }(hj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj/hhhjAhMubj)}(hkstat_irqs_cpuh]j)}(hkstat_irqs_cpuh]hkstat_irqs_cpu}(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjlubah}(h]h ](jjeh"]h$]h&]hhuh1jhj/hhhjAhMubj)}(h(unsigned int irq, int cpu)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hint cpuh](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hcpuh]hcpu}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj/hhhjAhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj+hhhjAhMubah}(h]j&ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjAhMhj(hhubjI)}(hhh]j)}(h,Get the statistics for an interrupt on a cpuh]h,Get the statistics for an interrupt on a cpu}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj hhubah}(h]h ]h"]h$]h&]uh1jHhj(hhhjAhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj;jkj;jljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``unsigned int irq`` The interrupt number ``int cpu`` The cpu number **Description** Returns the sum of interrupt counts on **cpu** since boot for **irq**. The caller must ensure that the interrupt is not removed concurrently.h](j)}(h**Parameters**h]jz)}(hjEh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj?ubj)}(hhh](j)}(h*``unsigned int irq`` The interrupt number h](j)}(h``unsigned int irq``h]j)}(hjdh]hunsigned int irq}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj^ubj)}(hhh]j)}(hThe interrupt numberh]hThe interrupt number}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyhMhjzubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jhjyhMhj[ubj)}(h``int cpu`` The cpu number h](j)}(h ``int cpu``h]j)}(hjh]hint cpu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(hThe cpu numberh]hThe cpu number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj[ubeh}(h]h ]h"]h$]h&]uh1jhj?ubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj?ubj)}(hReturns the sum of interrupt counts on **cpu** since boot for **irq**. The caller must ensure that the interrupt is not removed concurrently.h](h'Returns the sum of interrupt counts on }(hjhhhNhNubjz)}(h**cpu**h]hcpu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh since boot for }(hjhhhNhNubjz)}(h**irq**h]hirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubhH. The caller must ensure that the interrupt is not removed concurrently.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj?ubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMkstat_irqs_usr (C function)c.kstat_irqs_usrhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h.unsigned int kstat_irqs_usr (unsigned int irq)h]j])}(h-unsigned int kstat_irqs_usr(unsigned int irq)h](jc)}(hunsignedh]hunsigned}(hjAhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj=hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj=hhhjOhMubjc)}(hinth]hint}(hj^hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj=hhhjOhMubju)}(h h]h }(hjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj=hhhjOhMubj)}(hkstat_irqs_usrh]j)}(hkstat_irqs_usrh]hkstat_irqs_usr}(hj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjzubah}(h]h ](jjeh"]h$]h&]hhuh1jhj=hhhjOhMubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj=hhhjOhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj9hhhjOhMubah}(h]j4ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjOhMhj6hhubjI)}(hhh]j)}(h7Get the statistics for an interrupt from thread contexth]h7Get the statistics for an interrupt from thread context}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhj6hhhjOhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(hX>**Parameters** ``unsigned int irq`` The interrupt number **Description** Returns the sum of interrupt counts on all cpus since boot for **irq**. It uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM hjubj)}(hhh]j)}(h*``unsigned int irq`` The interrupt number h](j)}(h``unsigned int irq``h]j)}(hj=h]hunsigned int irq}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhj7ubj)}(hhh]j)}(hThe interrupt numberh]hThe interrupt number}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRhMhjSubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhMhj4ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjxh]h Description}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjvubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hGReturns the sum of interrupt counts on all cpus since boot for **irq**.h](h?Returns the sum of interrupt counts on all cpus since boot for }(hjhhhNhNubjz)}(h**irq**h]hirq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chMhjubj)}(hIt uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().h]hIt uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/irqdesc.chM hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_bad_irq (C function)c.handle_bad_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h+void handle_bad_irq (struct irq_desc *desc)h]j])}(h*void handle_bad_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chKubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubj)}(hhandle_bad_irqh]j)}(hhandle_bad_irqh]hhandle_bad_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetj;modnameN classnameNjj)}j]j)}jjsbc.handle_bad_irqasbuh1hhjubju)}(h h]h }(hjYhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hjthhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKhjhhubjI)}(hhh]j)}(h"handle spurious and unhandled irqsh]h"handle spurious and unhandled irqs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chKhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``struct irq_desc *desc`` description of the interrupt **Description** Handles spurious and unhandled IRQ's. It also prints a debugmessage.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chK hjubj)}(hhh]j)}(h7``struct irq_desc *desc`` description of the interrupt h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chKhjubj)}(hhh]j)}(hdescription of the interrupth]hdescription of the interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chKhjubj)}(hDHandles spurious and unhandled IRQ's. It also prints a debugmessage.h]hFHandles spurious and unhandled IRQ’s. It also prints a debugmessage.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$generic_handle_arch_irq (C function)c.generic_handle_arch_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h;void noinstr generic_handle_arch_irq (struct pt_regs *regs)h]j])}(h:void noinstr generic_handle_arch_irq(struct pt_regs *regs)h](jc)}(hvoidh]hvoid}(hj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj[hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.cJhMubju)}(h h]h }(hjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[hhhjmhMubhnoinstr}(hj[hhhNhNubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[hhhjmhMubj)}(hgeneric_handle_arch_irqh]j)}(hgeneric_handle_arch_irqh]hgeneric_handle_arch_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj[hhhjmhMubj)}(h(struct pt_regs *regs)h]j)}(hstruct pt_regs *regsh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hpt_regsh]hpt_regs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.generic_handle_arch_irqasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hregsh]hregs}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj[hhhjmhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjWhhhjmhMubah}(h]jRah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjmhMhjThhubjI)}(hhh]j)}(hJroot irq handler for architectures which do no entry accounting themselvesh]hJroot irq handler for architectures which do no entry accounting themselves}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chMhj.hhubah}(h]h ]h"]h$]h&]uh1jHhjThhhjmhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjIjkjIjljmjnuh1jQhhhj:hNhNubjp)}(h`**Parameters** ``struct pt_regs *regs`` Register file coming from the low-level handling codeh](j)}(h**Parameters**h]jz)}(hjSh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjQubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chMhjMubj)}(hhh]j)}(hN``struct pt_regs *regs`` Register file coming from the low-level handling codeh](j)}(h``struct pt_regs *regs``h]j)}(hjrh]hstruct pt_regs *regs}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chMhjlubj)}(hhh]j)}(h5Register file coming from the low-level handling codeh]h5Register file coming from the low-level handling code}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/handle.chMhjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjhMhjiubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_set_msi_desc_off (C function)c.irq_set_msi_desc_offhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(haint irq_set_msi_desc_off (unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h]j])}(h`int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKXubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKXubj)}(hirq_set_msi_desc_offh]j)}(hirq_set_msi_desc_offh]hirq_set_msi_desc_off}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKXubj)}(hH(unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h](j)}(hunsigned int irq_baseh](jc)}(hunsignedh]hunsigned}(hj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hj%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirq_baseh]hirq_base}(hjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int irq_offseth](jc)}(hunsignedh]hunsigned}(hjZhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjVubju)}(h h]h }(hjhhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjVubjc)}(hinth]hint}(hjvhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjVubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjVubj)}(h irq_offseth]h irq_offset}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct msi_desc *entryh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hmsi_desch]hmsi_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_set_msi_desc_offasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hentryh]hentry}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKXubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKXubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhKXhjhhubjI)}(hhh]j)}(h,set MSI descriptor data for an irq at offseth]h,set MSI descriptor data for an irq at offset}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKXhj+hhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhKXubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjFjkjFjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``unsigned int irq_base`` Interrupt number base ``unsigned int irq_offset`` Interrupt number offset ``struct msi_desc *entry`` Pointer to MSI descriptor data **Description** Set the MSI descriptor entry for an irq at offseth](j)}(h**Parameters**h]jz)}(hjPh]h Parameters}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chK\hjJubj)}(hhh](j)}(h0``unsigned int irq_base`` Interrupt number base h](j)}(h``unsigned int irq_base``h]j)}(hjoh]hunsigned int irq_base}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKYhjiubj)}(hhh]j)}(hInterrupt number baseh]hInterrupt number base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKYhjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjhKYhjfubj)}(h4``unsigned int irq_offset`` Interrupt number offset h](j)}(h``unsigned int irq_offset``h]j)}(hjh]hunsigned int irq_offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKZhjubj)}(hhh]j)}(hInterrupt number offseth]hInterrupt number offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKZhjfubj)}(h:``struct msi_desc *entry`` Pointer to MSI descriptor data h](j)}(h``struct msi_desc *entry``h]j)}(hjh]hstruct msi_desc *entry}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chK[hjubj)}(hhh]j)}(hPointer to MSI descriptor datah]hPointer to MSI descriptor data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhK[hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK[hjfubeh}(h]h ]h"]h$]h&]uh1jhjJubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chK]hjJubj)}(h1Set the MSI descriptor entry for an irq at offseth]h1Set the MSI descriptor entry for an irq at offset}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chK\hjJubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_msi_desc (C function)c.irq_set_msi_deschNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h?int irq_set_msi_desc (unsigned int irq, struct msi_desc *entry)h]j])}(h>int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)h](jc)}(hinth]hint}(hjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj]hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKkubju)}(h h]h }(hjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]hhhjohKkubj)}(hirq_set_msi_desch]j)}(hirq_set_msi_desch]hirq_set_msi_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]hhhjohKkubj)}(h*(unsigned int irq, struct msi_desc *entry)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct msi_desc *entryh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hmsi_desch]hmsi_desc}(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_set_msi_descasbuh1hhjubju)}(h h]h }(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj;hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hentryh]hentry}(hjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj]hhhjohKkubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjYhhhjohKkubah}(h]jTah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjohKkhjVhhubjI)}(hhh]j)}(h"set MSI descriptor data for an irqh]h"set MSI descriptor data for an irq}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKkhjohhubah}(h]h ]h"]h$]h&]uh1jHhjVhhhjohKkubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``unsigned int irq`` Interrupt number ``struct msi_desc *entry`` Pointer to MSI descriptor data **Description** Set the MSI descriptor entry for an irqh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKohjubj)}(hhh](j)}(h&``unsigned int irq`` Interrupt number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKlhjubj)}(hhh]j)}(hInterrupt numberh]hInterrupt number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKlhjubj)}(h:``struct msi_desc *entry`` Pointer to MSI descriptor data h](j)}(h``struct msi_desc *entry``h]j)}(hjh]hstruct msi_desc *entry}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKmhjubj)}(hhh]j)}(hPointer to MSI descriptor datah]hPointer to MSI descriptor data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKmhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKmhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj'h]h Description}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj%ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKohjubj)}(h'Set the MSI descriptor entry for an irqh]h'Set the MSI descriptor entry for an irq}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKnhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_disable (C function) c.irq_disablehNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h(void irq_disable (struct irq_desc *desc)h]j])}(h'void irq_disable(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMwubju)}(h h]h }(hj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhhjzhMwubj)}(h irq_disableh]j)}(h irq_disableh]h irq_disable}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhhjzhMwubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsb c.irq_disableasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhhjzhMwubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjdhhhjzhMwubah}(h]j_ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjzhMwhjahhubjI)}(hhh]j)}(hMark interrupt disabledh]hMark interrupt disabled}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMwhj)hhubah}(h]h ]h"]h$]h&]uh1jHhjahhhjzhMwubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjDjkjDjljmjnuh1jQhhhj:hNhNubjp)}(hXe**Parameters** ``struct irq_desc *desc`` irq descriptor which should be disabled **Description** If the chip does not implement the irq_disable callback, we use a lazy disable approach. That means we mark the interrupt disabled, but leave the hardware unmasked. That's an optimization because we avoid the hardware access for the common case where no interrupt happens after we marked it disabled. If an interrupt happens, then the interrupt flow handler masks the line at the hardware level and marks it pending. If the interrupt chip does not implement the irq_disable callback, a driver can disable the lazy approach for a particular irq line by calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead.h](j)}(h**Parameters**h]jz)}(hjNh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjLubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM{hjHubj)}(hhh]j)}(hB``struct irq_desc *desc`` irq descriptor which should be disabled h](j)}(h``struct irq_desc *desc``h]j)}(hjmh]hstruct irq_desc *desc}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMxhjgubj)}(hhh]j)}(h'irq descriptor which should be disabledh]h'irq descriptor which should be disabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMxhjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jhjhMxhjdubah}(h]h ]h"]h$]h&]uh1jhjHubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMzhjHubj)}(hXIf the chip does not implement the irq_disable callback, we use a lazy disable approach. That means we mark the interrupt disabled, but leave the hardware unmasked. That's an optimization because we avoid the hardware access for the common case where no interrupt happens after we marked it disabled. If an interrupt happens, then the interrupt flow handler masks the line at the hardware level and marks it pending.h]hXIf the chip does not implement the irq_disable callback, we use a lazy disable approach. That means we mark the interrupt disabled, but leave the hardware unmasked. That’s an optimization because we avoid the hardware access for the common case where no interrupt happens after we marked it disabled. If an interrupt happens, then the interrupt flow handler masks the line at the hardware level and marks it pending.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMyhjHubj)}(hX]If the interrupt chip does not implement the irq_disable callback, a driver can disable the lazy approach for a particular irq line by calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead.h]hXaIf the interrupt chip does not implement the irq_disable callback, a driver can disable the lazy approach for a particular irq line by calling ‘irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)’. This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjHubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_percpu_irq (C function)c.handle_percpu_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h.void handle_percpu_irq (struct irq_desc *desc)h]j])}(h-void handle_percpu_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM_ubju)}(h h]h }(hj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj hM_ubj)}(hhandle_percpu_irqh]j)}(hhandle_percpu_irqh]hhandle_percpu_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj hM_ubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubju)}(h h]h }(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjYmodnameN classnameNjj)}j]j)}jjsbc.handle_percpu_irqasbuh1hhj5ubju)}(h h]h }(hjwhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj1ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj hM_ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj hM_ubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj hM_hjhhubjI)}(hhh]j)}(hPer CPU local irq handlerh]hPer CPU local irq handler}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM_hjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj hM_ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Per CPU interrupts on SMP machines without locking requirementsh](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMchjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM`hjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhM`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM`hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj8h]h Description}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj6ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMbhjubj)}(h?Per CPU interrupts on SMP machines without locking requirementsh]j)}(hjPh]h?Per CPU interrupts on SMP machines without locking requirements}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMahjNubah}(h]h ]h"]h$]h&]uh1jhj_hMahjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$handle_percpu_devid_irq (C function)c.handle_percpu_devid_irqhNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h4void handle_percpu_devid_irq (struct irq_desc *desc)h]j])}(h3void handle_percpu_devid_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMxubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMxubj)}(hhandle_percpu_devid_irqh]j)}(hhandle_percpu_devid_irqh]hhandle_percpu_devid_irq}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMxubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_percpu_devid_irqasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMxubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj~hhhjhMxubah}(h]jyah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMxhj{hhubjI)}(hhh]j)}(h.Per CPU local irq handler with per cpu dev idsh]h.Per CPU local irq handler with per cpu dev ids}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMxhjChhubah}(h]h ]h"]h$]h&]uh1jHhj{hhhjhMxubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj^jkj^jljmjnuh1jQhhhj:hNhNubjp)}(hXu**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Per CPU interrupts on SMP machines without locking requirements. Same as handle_percpu_irq() above but with the following extras: action->percpu_dev_id is a pointer to percpu variables which contain the real device id for the cpu on which this handler is calledh](j)}(h**Parameters**h]jz)}(hjhh]h Parameters}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjfubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM|hjbubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMyhjubj)}(hhh]j)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMyhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMyhj~ubah}(h]h ]h"]h$]h&]uh1jhjbubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM{hjbubj)}(hPer CPU interrupts on SMP machines without locking requirements. Same as handle_percpu_irq() above but with the following extras:h]hPer CPU interrupts on SMP machines without locking requirements. Same as handle_percpu_irq() above but with the following extras:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMzhjbubj)}(haction->percpu_dev_id is a pointer to percpu variables which contain the real device id for the cpu on which this handler is calledh]haction->percpu_dev_id is a pointer to percpu variables which contain the real device id for the cpu on which this handler is called}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM}hjbubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_cpu_online (C function)c.irq_cpu_onlinehNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hvoid irq_cpu_online (void)h]j])}(hvoid irq_cpu_online(void)h](jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM4ubju)}(h h]h }(hj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj$hM4ubj)}(hirq_cpu_onlineh]j)}(hirq_cpu_onlineh]hirq_cpu_online}(hj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj$hM4ubj)}(h(void)h]j)}(hvoidh]jc)}(hvoidh]hvoid}(hjShhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjOubah}(h]h ]h"]h$]h&]noemphhhuh1jhjKubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj$hM4ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj$hM4ubah}(h]j ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj$hM4hj hhubjI)}(hhh]j)}(h$Invoke all irq_cpu_online functions.h]h$Invoke all irq_cpu_online functions.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM4hjzhhubah}(h]h ]h"]h$]h&]uh1jHhj hhhj$hM4ubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``void`` no arguments **Description** Iterate through all irqs and invoke the chip.irq_cpu_online() for each.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM8hjubj)}(hhh]j)}(h``void`` no arguments h](j)}(h``void``h]j)}(hjh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKhjubj)}(hhh]j)}(h no argumentsh]h no arguments}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKhjubj)}(hGIterate through all irqs and invoke the chip.irq_cpu_online() for each.h]j)}(hGIterate through all irqs and invoke the chip.irq_cpu_online() for each.h]hGIterate through all irqs and invoke the chip.irq_cpu_online() for each.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chM5hjubah}(h]h ]h"]h$]h&]uh1jhj!hM5hjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_cpu_offline (C function)c.irq_cpu_offlinehNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hvoid irq_cpu_offline (void)h]j])}(hvoid irq_cpu_offline(void)h](jc)}(hvoidh]hvoid}(hjHhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjDhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMNubju)}(h h]h }(hjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjDhhhjVhMNubj)}(hirq_cpu_offlineh]j)}(hirq_cpu_offlineh]hirq_cpu_offline}(hjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubah}(h]h ](jjeh"]h$]h&]hhuh1jhjDhhhjVhMNubj)}(h(void)h]j)}(hvoidh]jc)}(hvoidh]hvoid}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubah}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubah}(h]h ]h"]h$]h&]hhuh1jhjDhhhjVhMNubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj@hhhjVhMNubah}(h]j;ah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjVhMNhj=hhubjI)}(hhh]j)}(h%Invoke all irq_cpu_offline functions.h]h%Invoke all irq_cpu_offline functions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMNhjhhubah}(h]h ]h"]h$]h&]uh1jHhj=hhhjVhMNubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``void`` no arguments **Description** Iterate through all irqs and invoke the chip.irq_cpu_offline() for each.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMRhjubj)}(hhh]j)}(h``void`` no arguments h](j)}(h``void``h]j)}(hjh]hvoid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKhjubj)}(hhh]j)}(h no argumentsh]h no arguments}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj+h]h Description}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj)ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chKhjubj)}(hHIterate through all irqs and invoke the chip.irq_cpu_offline() for each.h]j)}(hHIterate through all irqs and invoke the chip.irq_cpu_offline() for each.h]hHIterate through all irqs and invoke the chip.irq_cpu_offline() for each.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMOhjAubah}(h]h ]h"]h$]h&]uh1jhjShMOhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_compose_msi_msg (C function)c.irq_chip_compose_msi_msghNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(hIint irq_chip_compose_msi_msg (struct irq_data *data, struct msi_msg *msg)h]j])}(hHint irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)h](jc)}(hinth]hint}(hjzhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjvhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjvhhhjhMubj)}(hirq_chip_compose_msi_msgh]j)}(hirq_chip_compose_msi_msgh]hirq_chip_compose_msi_msg}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjvhhhjhMubj)}(h,(struct irq_data *data, struct msi_msg *msg)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_compose_msi_msgasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct msi_msg *msgh](j)}(hjh]hstruct}(hj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubju)}(h h]h }(hj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubh)}(hhh]j)}(hmsi_msgh]hmsi_msg}(hjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjImodnameN classnameNjj)}j]jc.irq_chip_compose_msi_msgasbuh1hhj%ubju)}(h h]h }(hjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubj )}(hj h]h*}(hjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubj)}(hmsgh]hmsg}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjvhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjrhhhjhMubah}(h]jmah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjohhubjI)}(hhh]j)}(h"Compose msi message for a irq chiph]h"Compose msi message for a irq chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjohhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(hX:**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``struct msi_msg *msg`` Pointer to the MSI message **Description** For hierarchical domains we find the first chip in the hierarchy which implements the irq_compose_msi_msg callback. For non hierarchical we use the top level chip.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh](j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h3``struct msi_msg *msg`` Pointer to the MSI message h](j)}(h``struct msi_msg *msg``h]j)}(hj$h]hstruct msi_msg *msg}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(hPointer to the MSI messageh]hPointer to the MSI message}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9hMhj:ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj9hMhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hj_h]h Description}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj]ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hFor hierarchical domains we find the first chip in the hierarchy which implements the irq_compose_msi_msg callback. For non hierarchical we use the top level chip.h]hFor hierarchical domains we find the first chip in the hierarchy which implements the irq_compose_msi_msg callback. For non hierarchical we use the top level chip.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_pm_get (C function)c.irq_chip_pm_gethNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h+int irq_chip_pm_get (struct irq_data *data)h]j])}(h*int irq_chip_pm_get(struct irq_data *data)h](jc)}(hinth]hint}(hjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_pm_geth]j)}(hirq_chip_pm_geth]hirq_chip_pm_get}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_pm_getasbuh1hhjubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hj:hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhjhMhjhhubjI)}(hhh]j)}(hEnable power for an IRQ chiph]hEnable power for an IRQ chip}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjahhubah}(h]h ]h"]h$]h&]uh1jHhjhhhjhMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjj|jkj|jljmjnuh1jQhhhj:hNhNubjp)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data **Description** Enable the power to the IRQ chip referenced by the interrupt data structure.h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hLEnable the power to the IRQ chip referenced by the interrupt data structure.h]hLEnable the power to the IRQ chip referenced by the interrupt data structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_pm_put (C function)c.irq_chip_pm_puthNtauh1j@hj:hhhNhNubjR)}(hhh](jW)}(h,void irq_chip_pm_put (struct irq_data *data)h]j])}(h+void irq_chip_pm_put(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hj%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj!hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMubju)}(h h]h }(hj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj!hhhj3hMubj)}(hirq_chip_pm_puth]j)}(hirq_chip_pm_puth]hirq_chip_pm_put}(hjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubah}(h]h ](jjeh"]h$]h&]hhuh1jhj!hhhj3hMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubju)}(h h]h }(hjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj^ubh)}(hhh]j)}(hirq_datah]hirq_data}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&] refdomainj_ reftypej reftargetjmodnameN classnameNjj)}j]j)}jjHsbc.irq_chip_pm_putasbuh1hhj^ubju)}(h h]h }(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj^ubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubj)}(hdatah]hdata}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjZubah}(h]h ]h"]h$]h&]hhuh1jhj!hhhj3hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj3hMubah}(h]jah ](j@jAeh"]h$]h&]jEjF)jGhuh1jVhj3hMhjhhubjI)}(hhh]j)}(h"Drop a PM reference on an IRQ chiph]h"Drop a PM reference on an IRQ chip}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jHhjhhhj3hMubeh}(h]h ](j_ functioneh"]h$]h&]jij_ jjjjkjjljmjnuh1jQhhhj:hNhNubjp)}(hX**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data **Description** Drop a power management reference, acquired via irq_chip_pm_get(), on the IRQ chip represented by the interrupt data structure. Note that this will not disable power to the IRQ chip until this function has been called for all IRQs that have called irq_chip_pm_get() and it may not disable power at all (if user space prevents that, for example).h](j)}(h**Parameters**h]jz)}(hjh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jyhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hj&h]hstruct irq_data *data}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhj ubj)}(hhh]j)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h**Description**h]jz)}(hjah]h Description}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jyhj_ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hDrop a power management reference, acquired via irq_chip_pm_get(), on the IRQ chip represented by the interrupt data structure.h]hDrop a power management reference, acquired via irq_chip_pm_get(), on the IRQ chip represented by the interrupt data structure.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubj)}(hNote that this will not disable power to the IRQ chip until this function has been called for all IRQs that have called irq_chip_pm_get() and it may not disable power at all (if user space prevents that, for example).h]hNote that this will not disable power to the IRQ chip until this function has been called for all IRQs that have called irq_chip_pm_get() and it may not disable power at all (if user space prevents that, for example).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:520: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1johj:hhhNhNubeh}(h]internal-functions-providedah ]h"]internal functions providedah$]h&]uh1jLhjNhhhjahMubjM)}(hhh](jR)}(hCreditsh]hCredits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jQhjhhhjahMubj)}(h7The following people have contributed to this document:h]h7The following people have contributed to this document:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjahMhjhhubj)}(hhh](jB)}(h Thomas Gleixner tglx@kernel.org h]j)}(hThomas Gleixner tglx@kernel.orgh](hThomas Gleixner }(hjhhhNhNubh reference)}(htglx@kernel.orgh]htglx@kernel.org}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:tglx@kernel.orguh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjahMhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubjB)}(hIngo Molnar mingo@elte.huh]j)}(hjh](h Ingo Molnar }(hjhhhNhNubj)}(h mingo@elte.huh]h mingo@elte.hu}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:mingo@elte.huuh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjahMhjubah}(h]h ]h"]h$]h&]uh1jAhjhhhjahNubeh}(h]h ]h"]h$]h&]j>j?j@hjAjBuh1jhjhhhjahMubeh}(h]creditsah ]h"]creditsah$]h&]uh1jLhjNhhhjahMubeh}(h]linux-generic-irq-handlingah ]h"]linux generic irq handlingah$]h&]uh1jLhhhhhjahKubeh}(h]h ]h"]h$]h&]sourcejauh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jQN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjPerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceja _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}(hhhhjhjjj jj/j#j>j2jMjAj\jPjkj_jzjnjj}jjjjjjjjjjjjjjjjjjjjj.j"j=j1jLj@j[jOjjj^jyjmjj|jjjjjjjjjjjjjjjjjjjjj-j!j<j0jKj?jZjNjij]jxjljj{jjjjjjjjjjjjjjjjjjjjj,j j;j/jJj>jYjMjhj\jwjkjjzjjjjjjjjjjjjjjjjj jjjj+jj:j.jIj=usubstitution_names}(amphaposhastjbrvbarjbsolj centj/colonj>commajMcommatj\copyjkcurrenjzdarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34jfrac38jfrac58j.frac78j=gtjLhalfj[horbarjjhyphenjyiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquojltjmicroj-middotj<nbspjKnotjZnumjiohmjxordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotjraquojrarrj,rcubj;rdquojJregjYrparjhrsqbjwrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesj tradejuarrj+verbarj:yenjIurefnames}refids}nameids}(j*j'j j jjjjjjjujrj j j4 j1 j j j j j j jU jR j j j j j7 j4 j j j j j j j j j, j) jjjjjjj<3j93jIajFaj7j4jjj"ju nametypes}(j*j jjjjuj j4 j j j jU j j j7 j j j j j, jjjj<3jIaj7jj"uh}(j'jNj jjjjjjjjrjCj jxj1 j j j j j j j jR j j jX j j j4 j j j: j j j j j j j) j jj7 jjjjj93j!jOjXjjjmjrjjjmjrjjjGjLjjjjjjj!j!jT#jY#jR(jW(jq*jv*j#.j(.j-0j20jFaj?3jj3jo3j5j5j8j8jAjAjCjCjFjFj KjKjLjLjOjOjSjSjdWjiWjRYjWYj[j[j\j\j_j_j4jLajwaj|aj+cj0cjdjdjejejTgjYgjhjhj0jj5jjJljOljpnjunjpjpjrjrjtjtjvjvjwjwjQyjVyjzjzj/|j4|j}j}jjjdjijjj3j8jًjދjjjjjjjɖjΖjΚjӚjLjQjjjbjgjjj[j`jVj[jVj[jjjjjЭjխj0j5jذjݰjjjjjjjj!jjjj#jjj7j<jjjOjTjjjGjLjjjjjXj]jjjjjijnjj j&j+jjj}jjjjjjj:jejjjjj jjjj%j*jXj]jjjjjPjUjjj&j+j4j9jjjRjWjjjTjYj_jdjjjyj~j jj;j@jmjrjjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log]%Documentation/core-api/genericirq.rst(NNNNta decorationNhhub.