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YEN SIGN h]h¥}(hhhj)ubah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(hLinux generic IRQ handlingh]hLinux generic IRQ handling}(hjAhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj:hhhA/var/lib/git/docbuild/linux/Documentation/core-api/genericirq.rsthKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hj\hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jXhjUhjMhKubh field_body)}(h!|copy| 2005-2010: Thomas Gleixnerh]h paragraph)}(hjlh](h©}(hhhjphhhNhNubh 2005-2010: Thomas Gleixner}(h 2005-2010: Thomas GleixnerhjphhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhKhjjubah}(h]h ]h"]h$]h&]uh1jhhjUubeh}(h]h ]h"]h$]h&]uh1jShjMhKhjPhhubjT)}(hhh](jY)}(h Copyrighth]h Copyright}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jXhjhjMhKubji)}(h|copy| 2005-2006: Ingo Molnar h]jo)}(h|copy| 2005-2006: Ingo Molnarh](h©}(hhhjhhhNhNubh 2005-2006: Ingo Molnar}(h 2005-2006: Ingo MolnarhjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1jhhjubeh}(h]h ]h"]h$]h&]uh1jShjMhKhjPhhubeh}(h]h ]h"]h$]h&]uh1jNhj:hhhjMhKubj9)}(hhh](j>)}(h Introductionh]h Introduction}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhK ubjo)}(hXThe generic interrupt handling layer is designed to provide a complete abstraction of interrupt handling for device drivers. It is able to handle all the different types of interrupt controller hardware. Device drivers use generic API functions to request, enable, disable and free interrupts. The drivers do not have to know anything about interrupt hardware details, so they can be used on different platforms without code changes.h]hXThe generic interrupt handling layer is designed to provide a complete abstraction of interrupt handling for device drivers. It is able to handle all the different types of interrupt controller hardware. Device drivers use generic API functions to request, enable, disable and free interrupts. The drivers do not have to know anything about interrupt hardware details, so they can be used on different platforms without code changes.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK hjhhubjo)}(hThis documentation is provided to developers who want to implement an interrupt subsystem based for their architecture, with the help of the generic IRQ handling layer.h]hThis documentation is provided to developers who want to implement an interrupt subsystem based for their architecture, with the help of the generic IRQ handling layer.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1j8hj:hhhjMhK ubj9)}(hhh](j>)}(h Rationaleh]h Rationale}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhKubjo)}(hThe original implementation of interrupt handling in Linux uses the __do_IRQ() super-handler, which is able to deal with every type of interrupt logic.h]hThe original implementation of interrupt handling in Linux uses the __do_IRQ() super-handler, which is able to deal with every type of interrupt logic.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjhhubjo)}(hOriginally, Russell King identified different types of handlers to build a quite universal set for the ARM interrupt handler implementation in Linux 2.5/2.6. He distinguished between:h]hOriginally, Russell King identified different types of handlers to build a quite universal set for the ARM interrupt handler implementation in Linux 2.5/2.6. He distinguished between:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK hjhhubh bullet_list)}(hhh](h list_item)}(h Level type h]jo)}(h Level typeh]h Level type}(hj7hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK$hj1ubah}(h]h ]h"]h$]h&]uh1j/hj,hhhjMhNubj0)}(h Edge type h]jo)}(h Edge typeh]h Edge type}(hjOhjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK&hjIubah}(h]h ]h"]h$]h&]uh1j/hj,hhhjMhNubj0)}(h Simple type h]jo)}(h Simple typeh]h Simple type}(hjghjehhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK(hjaubah}(h]h ]h"]h$]h&]uh1j/hj,hhhjMhNubeh}(h]h ]h"]h$]h&]bullet-uh1j*hjMhK$hjhhubjo)}(h5During the implementation we identified another type:h]h5During the implementation we identified another type:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK*hjhhubj+)}(hhh]j0)}(hFast EOI type h]jo)}(h Fast EOI typeh]h Fast EOI type}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK,hjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubah}(h]h ]h"]h$]h&]jjuh1j*hjMhK,hjhhubjo)}(hMIn the SMP world of the __do_IRQ() super-handler another type was identified:h]hMIn the SMP world of the __do_IRQ() super-handler another type was identified:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK.hjhhubj+)}(hhh]j0)}(h Per CPU type h]jo)}(h Per CPU typeh]h Per CPU type}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK1hjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubah}(h]h ]h"]h$]h&]jjuh1j*hjMhK1hjhhubjo)}(hThis split implementation of high-level IRQ handlers allows us to optimize the flow of the interrupt handling for each specific interrupt type. This reduces complexity in that particular code path and allows the optimized handling of a given type.h]hThis split implementation of high-level IRQ handlers allows us to optimize the flow of the interrupt handling for each specific interrupt type. This reduces complexity in that particular code path and allows the optimized handling of a given type.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK3hjhhubjo)}(hXThe original general IRQ implementation used hw_interrupt_type structures and their ``->ack``, ``->end`` [etc.] callbacks to differentiate the flow control in the super-handler. This leads to a mix of flow logic and low-level hardware logic, and it also leads to unnecessary code duplication: for example in i386, there is an ``ioapic_level_irq`` and an ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but have different flow handling.h](hTThe original general IRQ implementation used hw_interrupt_type structures and their }(hTThe original general IRQ implementation used hw_interrupt_type structures and their hjhhhNhNubhliteral)}(h ``->ack``h]h->ack}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(h, hjhhhNhNubj)}(h ``->end``h]h->end}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh [etc.] callbacks to differentiate the flow control in the super-handler. This leads to a mix of flow logic and low-level hardware logic, and it also leads to unnecessary code duplication: for example in i386, there is an }(h [etc.] callbacks to differentiate the flow control in the super-handler. This leads to a mix of flow logic and low-level hardware logic, and it also leads to unnecessary code duplication: for example in i386, there is an hjhhhNhNubj)}(h``ioapic_level_irq``h]hioapic_level_irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and an }(h and an hjhhhNhNubj)}(h``ioapic_edge_irq``h]hioapic_edge_irq}(hhhj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhU IRQ-type which share many of the low-level details but have different flow handling.}(hU IRQ-type which share many of the low-level details but have different flow handling.hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhK8hjhhubjo)}(h\A more natural abstraction is the clean separation of the 'irq flow' and the 'chip details'.h]hdA more natural abstraction is the clean separation of the ‘irq flow’ and the ‘chip details’.}(hjLhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK@hjhhubjo)}(hX}Analysing a couple of architecture's IRQ subsystem implementations reveals that most of them can use a generic set of 'irq flow' methods and only need to add the chip-level specific code. The separation is also valuable for (sub)architectures which need specific quirks in the IRQ flow itself but not in the chip details - and thus provides a more transparent IRQ subsystem design.h]hXAnalysing a couple of architecture’s IRQ subsystem implementations reveals that most of them can use a generic set of ‘irq flow’ methods and only need to add the chip-level specific code. The separation is also valuable for (sub)architectures which need specific quirks in the IRQ flow itself but not in the chip details - and thus provides a more transparent IRQ subsystem design.}(hjZhjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKChjhhubjo)}(hX%Each interrupt descriptor is assigned its own high-level flow handler, which is normally one of the generic implementations. (This high-level flow handler implementation also makes it simple to provide demultiplexing handlers which can be found in embedded platforms on various architectures.)h]hX%Each interrupt descriptor is assigned its own high-level flow handler, which is normally one of the generic implementations. (This high-level flow handler implementation also makes it simple to provide demultiplexing handlers which can be found in embedded platforms on various architectures.)}(hjhhjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKJhjhhubjo)}(hXThe separation makes the generic interrupt handling layer more flexible and extensible. For example, an (sub)architecture can use a generic IRQ-flow implementation for 'level type' interrupts and add a (sub)architecture specific 'edge type' implementation.h]hXThe separation makes the generic interrupt handling layer more flexible and extensible. For example, an (sub)architecture can use a generic IRQ-flow implementation for ‘level type’ interrupts and add a (sub)architecture specific ‘edge type’ implementation.}(hjvhjthhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKPhjhhubjo)}(hXTo make the transition to the new model easier and prevent the breakage of existing implementations, the __do_IRQ() super-handler is still available. This leads to a kind of duality for the time being. Over time the new model should be used in more and more architectures, as it enables smaller and cleaner IRQ subsystems. It's deprecated for three years now and about to be removed.h]hXTo make the transition to the new model easier and prevent the breakage of existing implementations, the __do_IRQ() super-handler is still available. This leads to a kind of duality for the time being. Over time the new model should be used in more and more architectures, as it enables smaller and cleaner IRQ subsystems. It’s deprecated for three years now and about to be removed.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKUhjhhubeh}(h] rationaleah ]h"] rationaleah$]h&]uh1j8hj:hhhjMhKubj9)}(hhh](j>)}(hKnown Bugs And Assumptionsh]hKnown Bugs And Assumptions}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhK]ubjo)}(hNone (knock on wood).h]hNone (knock on wood).}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK_hjhhubeh}(h]known-bugs-and-assumptionsah ]h"]known bugs and assumptionsah$]h&]uh1j8hj:hhhjMhK]ubj9)}(hhh](j>)}(hAbstraction layersh]hAbstraction layers}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhKbubjo)}(hAThere are three main levels of abstraction in the interrupt code:h]hAThere are three main levels of abstraction in the interrupt code:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKdhjhhubhenumerated_list)}(hhh](j0)}(hHigh-level driver API h]jo)}(hHigh-level driver APIh]hHigh-level driver API}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKfhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hHigh-level IRQ flow handlers h]jo)}(hHigh-level IRQ flow handlersh]hHigh-level IRQ flow handlers}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(h"Chip-level hardware encapsulation h]jo)}(h!Chip-level hardware encapsulationh]h!Chip-level hardware encapsulation}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKjhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjhhhjMhKfubj9)}(hhh](j>)}(hInterrupt control flowh]hInterrupt control flow}(hj;hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj6hhhjMhKmubjo)}(hXEach interrupt is described by an interrupt descriptor structure irq_desc. The interrupt is referenced by an 'unsigned int' numeric value which selects the corresponding interrupt description structure in the descriptor structures array. The descriptor structure contains status information and pointers to the interrupt flow method and the interrupt chip structure which are assigned to this interrupt.h]hXEach interrupt is described by an interrupt descriptor structure irq_desc. The interrupt is referenced by an ‘unsigned int’ numeric value which selects the corresponding interrupt description structure in the descriptor structures array. The descriptor structure contains status information and pointers to the interrupt flow method and the interrupt chip structure which are assigned to this interrupt.}(hjIhjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKohj6hhubjo)}(hX Whenever an interrupt triggers, the low-level architecture code calls into the generic interrupt code by calling desc->handle_irq(). This high-level IRQ handling function only uses desc->irq_data.chip primitives referenced by the assigned chip descriptor structure.h]hX Whenever an interrupt triggers, the low-level architecture code calls into the generic interrupt code by calling desc->handle_irq(). This high-level IRQ handling function only uses desc->irq_data.chip primitives referenced by the assigned chip descriptor structure.}(hjWhjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKvhj6hhubeh}(h]interrupt-control-flowah ]h"]interrupt control flowah$]h&]uh1j8hjhhhjMhKmubj9)}(hhh](j>)}(hHigh-level Driver APIh]hHigh-level Driver API}(hjphjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjkhhhjMhK|ubjo)}(h:The high-level Driver API consists of following functions:h]h:The high-level Driver API consists of following functions:}(hj~hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhK~hjkhhubj+)}(hhh](j0)}(hrequest_irq() h]jo)}(h request_irq()h]h request_irq()}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hrequest_threaded_irq() h]jo)}(hrequest_threaded_irq()h]hrequest_threaded_irq()}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(h free_irq() h]jo)}(h free_irq()h]h free_irq()}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hdisable_irq() h]jo)}(h disable_irq()h]h disable_irq()}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(h enable_irq() h]jo)}(h enable_irq()h]h enable_irq()}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(h disable_irq_nosync() (SMP only) h]jo)}(hdisable_irq_nosync() (SMP only)h]hdisable_irq_nosync() (SMP only)}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hsynchronize_irq() (SMP only) h]jo)}(hsynchronize_irq() (SMP only)h]hsynchronize_irq() (SMP only)}(hj# hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hirq_set_irq_type() h]jo)}(hirq_set_irq_type()h]hirq_set_irq_type()}(hj; hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj5 ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hirq_set_irq_wake() h]jo)}(hirq_set_irq_wake()h]hirq_set_irq_wake()}(hjS hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjM ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hirq_set_handler_data() h]jo)}(hirq_set_handler_data()h]hirq_set_handler_data()}(hjk hji hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhje ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hirq_set_chip() h]jo)}(hirq_set_chip()h]hirq_set_chip()}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj} ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubj0)}(hirq_set_chip_data() h]jo)}(hirq_set_chip_data()h]hirq_set_chip_data()}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hjhhhjMhNubeh}(h]h ]h"]h$]h&]jjuh1j*hjMhKhjkhhubjo)}(h9See the autogenerated function documentation for details.h]h9See the autogenerated function documentation for details.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjkhhubeh}(h]high-level-driver-apiah ]h"]high-level driver apiah$]h&]uh1j8hjhhhjMhK|ubj9)}(hhh](j>)}(hHigh-level IRQ flow handlersh]hHigh-level IRQ flow handlers}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubjo)}(hAThe generic layer provides a set of pre-defined irq-flow methods:h]hAThe generic layer provides a set of pre-defined irq-flow methods:}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubj+)}(hhh](j0)}(hhandle_level_irq() h]jo)}(hhandle_level_irq()h]hhandle_level_irq()}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_edge_irq() h]jo)}(hhandle_edge_irq()h]hhandle_edge_irq()}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_fasteoi_irq() h]jo)}(hhandle_fasteoi_irq()h]hhandle_fasteoi_irq()}(hj! hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_simple_irq() h]jo)}(hhandle_simple_irq()h]hhandle_simple_irq()}(hj9 hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj3 ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_percpu_irq() h]jo)}(hhandle_percpu_irq()h]hhandle_percpu_irq()}(hjQ hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjK ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_edge_eoi_irq() h]jo)}(hhandle_edge_eoi_irq()h]hhandle_edge_eoi_irq()}(hji hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjc ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubj0)}(hhandle_bad_irq() h]jo)}(hhandle_bad_irq()h]hhandle_bad_irq()}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj{ ubah}(h]h ]h"]h$]h&]uh1j/hj hhhjMhNubeh}(h]h ]h"]h$]h&]jjuh1j*hjMhKhj hhubjo)}(hThe interrupt flow handlers (either pre-defined or architecture specific) are assigned to specific interrupts by the architecture either during bootup or during device initialization.h]hThe interrupt flow handlers (either pre-defined or architecture specific) are assigned to specific interrupts by the architecture either during bootup or during device initialization.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubj9)}(hhh](j>)}(hDefault flow implementationsh]hDefault flow implementations}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubj9)}(hhh](j>)}(hHelper functionsh]hHelper functions}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubjo)}(hThe helper functions call the chip primitives and are used by the default flow implementations. The following helper functions are implemented (simplified excerpt)::h]hThe helper functions call the chip primitives and are used by the default flow implementations. The following helper functions are implemented (simplified excerpt):}(hThe helper functions call the chip primitives and are used by the default flow implementations. The following helper functions are implemented (simplified excerpt):hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubh literal_block)}(hXdefault_enable(struct irq_data *data) { desc->irq_data.chip->irq_unmask(data); } default_disable(struct irq_data *data) { if (!delay_disable(data)) desc->irq_data.chip->irq_mask(data); } default_ack(struct irq_data *data) { chip->irq_ack(data); } default_mask_ack(struct irq_data *data) { if (chip->irq_mask_ack) { chip->irq_mask_ack(data); } else { chip->irq_mask(data); chip->irq_ack(data); } } noop(struct irq_data *data)) { }h]hXdefault_enable(struct irq_data *data) { desc->irq_data.chip->irq_unmask(data); } default_disable(struct irq_data *data) { if (!delay_disable(data)) desc->irq_data.chip->irq_mask(data); } default_ack(struct irq_data *data) { chip->irq_ack(data); } default_mask_ack(struct irq_data *data) { if (chip->irq_mask_ack) { chip->irq_mask_ack(data); } else { chip->irq_mask(data); chip->irq_ack(data); } } noop(struct irq_data *data)) { }}(hhhj ubah}(h]h ]h"]h$]h&]hhuh1j hjMhKhj hhubeh}(h]helper-functionsah ]h"]helper functionsah$]h&]uh1j8hj hhhjMhKubeh}(h]default-flow-implementationsah ]h"]default flow implementationsah$]h&]uh1j8hj hhhjMhKubj9)}(hhh](j>)}(h$Default flow handler implementationsh]h$Default flow handler implementations}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubj9)}(hhh](j>)}(hDefault Level IRQ flow handlerh]hDefault Level IRQ flow handler}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubjo)}(hRhandle_level_irq provides a generic implementation for level-triggered interrupts.h]hRhandle_level_irq provides a generic implementation for level-triggered interrupts.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubjo)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(h?The following control flow is implemented (simplified excerpt):hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubj )}(hgdesc->irq_data.chip->irq_mask_ack(); handle_irq_event(desc->action); desc->irq_data.chip->irq_unmask();h]hgdesc->irq_data.chip->irq_mask_ack(); handle_irq_event(desc->action); desc->irq_data.chip->irq_unmask();}(hhhj7 ubah}(h]h ]h"]h$]h&]hhuh1j hjMhKhj hhubeh}(h]default-level-irq-flow-handlerah ]h"]default level irq flow handlerah$]h&]uh1j8hj hhhjMhKubj9)}(hhh](j>)}(h!Default Fast EOI IRQ flow handlerh]h!Default Fast EOI IRQ flow handler}(hjR hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjM hhhjMhKubjo)}(hvhandle_fasteoi_irq provides a generic implementation for interrupts, which only need an EOI at the end of the handler.h]hvhandle_fasteoi_irq provides a generic implementation for interrupts, which only need an EOI at the end of the handler.}(hj` hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjM hhubjo)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(h?The following control flow is implemented (simplified excerpt):hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhjM hhubj )}(h?handle_irq_event(desc->action); desc->irq_data.chip->irq_eoi();h]h?handle_irq_event(desc->action); desc->irq_data.chip->irq_eoi();}(hhhj{ ubah}(h]h ]h"]h$]h&]hhuh1j hjMhKhjM hhubeh}(h]!default-fast-eoi-irq-flow-handlerah ]h"]!default fast eoi irq flow handlerah$]h&]uh1j8hj hhhjMhKubj9)}(hhh](j>)}(hDefault Edge IRQ flow handlerh]hDefault Edge IRQ flow handler}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhKubjo)}(hPhandle_edge_irq provides a generic implementation for edge-triggered interrupts.h]hPhandle_edge_irq provides a generic implementation for edge-triggered interrupts.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubjo)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(h?The following control flow is implemented (simplified excerpt):hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhKhj hhubj )}(hXif (desc->status & running) { desc->irq_data.chip->irq_mask_ack(); desc->status |= pending | masked; return; } desc->irq_data.chip->irq_ack(); desc->status |= running; do { if (desc->status & masked) desc->irq_data.chip->irq_unmask(); desc->status &= ~pending; handle_irq_event(desc->action); } while (desc->status & pending); desc->status &= ~running;h]hXif (desc->status & running) { desc->irq_data.chip->irq_mask_ack(); desc->status |= pending | masked; return; } desc->irq_data.chip->irq_ack(); desc->status |= running; do { if (desc->status & masked) desc->irq_data.chip->irq_unmask(); desc->status &= ~pending; handle_irq_event(desc->action); } while (desc->status & pending); desc->status &= ~running;}(hhhj ubah}(h]h ]h"]h$]h&]hhuh1j hjMhKhj hhubeh}(h]default-edge-irq-flow-handlerah ]h"]default edge irq flow handlerah$]h&]uh1j8hj hhhjMhKubj9)}(hhh](j>)}(hDefault simple IRQ flow handlerh]hDefault simple IRQ flow handler}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhMubjo)}(hJhandle_simple_irq provides a generic implementation for simple interrupts.h]hJhandle_simple_irq provides a generic implementation for simple interrupts.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhj hhubhnote)}(hBThe simple flow handler does not call any handler/chip primitives.h]jo)}(hj h]hBThe simple flow handler does not call any handler/chip primitives.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhj ubah}(h]h ]h"]h$]h&]uh1j hj hhhjMhNubjo)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(h?The following control flow is implemented (simplified excerpt):hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhj hhubj )}(hhandle_irq_event(desc->action);h]hhandle_irq_event(desc->action);}(hhhj ubah}(h]h ]h"]h$]h&]hhuh1j hjMhMhj hhubeh}(h]default-simple-irq-flow-handlerah ]h"]default simple irq flow handlerah$]h&]uh1j8hj hhhjMhMubj9)}(hhh](j>)}(hDefault per CPU flow handlerh]hDefault per CPU flow handler}(hj7 hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj2 hhhjMhMubjo)}(hKhandle_percpu_irq provides a generic implementation for per CPU interrupts.h]hKhandle_percpu_irq provides a generic implementation for per CPU interrupts.}(hjE hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM!hj2 hhubjo)}(hkPer CPU interrupts are only available on SMP and the handler provides a simplified version without locking.h]hkPer CPU interrupts are only available on SMP and the handler provides a simplified version without locking.}(hjS hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM$hj2 hhubjo)}(h@The following control flow is implemented (simplified excerpt)::h]h?The following control flow is implemented (simplified excerpt):}(h?The following control flow is implemented (simplified excerpt):hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM'hj2 hhubj )}(hif (desc->irq_data.chip->irq_ack) desc->irq_data.chip->irq_ack(); handle_irq_event(desc->action); if (desc->irq_data.chip->irq_eoi) desc->irq_data.chip->irq_eoi();h]hif (desc->irq_data.chip->irq_ack) desc->irq_data.chip->irq_ack(); handle_irq_event(desc->action); if (desc->irq_data.chip->irq_eoi) desc->irq_data.chip->irq_eoi();}(hhhjn ubah}(h]h ]h"]h$]h&]hhuh1j hjMhM)hj2 hhubeh}(h]default-per-cpu-flow-handlerah ]h"]default per cpu flow handlerah$]h&]uh1j8hj hhhjMhMubj9)}(hhh](j>)}(hEOI Edge IRQ flow handlerh]hEOI Edge IRQ flow handler}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhM1ubjo)}(hhandle_edge_eoi_irq provides an abnomination of the edge handler which is solely used to tame a badly wreckaged irq controller on powerpc/cell.h]hhandle_edge_eoi_irq provides an abnomination of the edge handler which is solely used to tame a badly wreckaged irq controller on powerpc/cell.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM3hj hhubeh}(h]eoi-edge-irq-flow-handlerah ]h"]eoi edge irq flow handlerah$]h&]uh1j8hj hhhjMhM1ubj9)}(hhh](j>)}(hBad IRQ flow handlerh]hBad IRQ flow handler}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhM8ubjo)}(hThandle_bad_irq is used for spurious interrupts which have no real handler assigned..h]hThandle_bad_irq is used for spurious interrupts which have no real handler assigned..}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM:hj hhubeh}(h]bad-irq-flow-handlerah ]h"]bad irq flow handlerah$]h&]uh1j8hj hhhjMhM8ubeh}(h]$default-flow-handler-implementationsah ]h"]$default flow handler implementationsah$]h&]uh1j8hj hhhjMhKubj9)}(hhh](j>)}(hQuirks and optimizationsh]hQuirks and optimizations}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhM>ubjo)}(hThe generic functions are intended for 'clean' architectures and chips, which have no platform-specific IRQ handling quirks. If an architecture needs to implement quirks on the 'flow' level then it can do so by overriding the high-level irq-flow handler.h]hXThe generic functions are intended for ‘clean’ architectures and chips, which have no platform-specific IRQ handling quirks. If an architecture needs to implement quirks on the ‘flow’ level then it can do so by overriding the high-level irq-flow handler.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhM@hj hhubeh}(h]quirks-and-optimizationsah ]h"]quirks and optimizationsah$]h&]uh1j8hj hhhjMhM>ubj9)}(hhh](j>)}(hDelayed interrupt disableh]hDelayed interrupt disable}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj hhhjMhMFubjo)}(hXThis per interrupt selectable feature, which was introduced by Russell King in the ARM interrupt implementation, does not mask an interrupt at the hardware level when disable_irq() is called. The interrupt is kept enabled and is masked in the flow handler when an interrupt event happens. This prevents losing edge interrupts on hardware which does not store an edge interrupt event while the interrupt is disabled at the hardware level. When an interrupt arrives while the IRQ_DISABLED flag is set, then the interrupt is masked at the hardware level and the IRQ_PENDING bit is set. When the interrupt is re-enabled by enable_irq() the pending bit is checked and if it is set, the interrupt is resent either via hardware or by a software resend mechanism. (It's necessary to enable CONFIG_HARDIRQS_SW_RESEND when you want to use the delayed interrupt disable feature and your hardware is not capable of retriggering an interrupt.) The delayed interrupt disable is not configurable.h]hXThis per interrupt selectable feature, which was introduced by Russell King in the ARM interrupt implementation, does not mask an interrupt at the hardware level when disable_irq() is called. The interrupt is kept enabled and is masked in the flow handler when an interrupt event happens. This prevents losing edge interrupts on hardware which does not store an edge interrupt event while the interrupt is disabled at the hardware level. When an interrupt arrives while the IRQ_DISABLED flag is set, then the interrupt is masked at the hardware level and the IRQ_PENDING bit is set. When the interrupt is re-enabled by enable_irq() the pending bit is checked and if it is set, the interrupt is resent either via hardware or by a software resend mechanism. (It’s necessary to enable CONFIG_HARDIRQS_SW_RESEND when you want to use the delayed interrupt disable feature and your hardware is not capable of retriggering an interrupt.) The delayed interrupt disable is not configurable.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMHhj hhubeh}(h]delayed-interrupt-disableah ]h"]delayed interrupt disableah$]h&]uh1j8hj hhhjMhMFubeh}(h]high-level-irq-flow-handlersah ]h"]high-level irq flow handlersah$]h&]uh1j8hjhhhjMhKubj9)}(hhh](j>)}(h!Chip-level hardware encapsulationh]h!Chip-level hardware encapsulation}(hj5 hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj0 hhhjMhMYubjo)}(hThe chip-level hardware descriptor structure :c:type:`irq_chip` contains all the direct chip relevant functions, which can be utilized by the irq flow implementations.h](h-The chip-level hardware descriptor structure }(h-The chip-level hardware descriptor structure hjA hhhNhNubh)}(h:c:type:`irq_chip`h]j)}(hjL h]hirq_chip}(hhhjN hhhNhNubah}(h]h ](xrefcc-typeeh"]h$]h&]uh1jhjJ ubah}(h]h ]h"]h$]h&]refdoccore-api/genericirq refdomainjY reftypetype refexplicitrefwarn reftargetirq_chipuh1hhjMhM[hjA ubhh contains all the direct chip relevant functions, which can be utilized by the irq flow implementations.}(hh contains all the direct chip relevant functions, which can be utilized by the irq flow implementations.hjA hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhM[hj0 hhubj+)}(hhh](j0)}(h ``irq_ack`` h]jo)}(h ``irq_ack``h]j)}(hj h]hirq_ack}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jnhjMhM_hj{ ubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h9``irq_mask_ack`` - Optional, recommended for performance h]jo)}(h8``irq_mask_ack`` - Optional, recommended for performanceh](j)}(h``irq_mask_ack``h]h irq_mask_ack}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh( - Optional, recommended for performance}(h( - Optional, recommended for performancehj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhMahj ubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h ``irq_mask`` h]jo)}(h ``irq_mask``h]j)}(hj h]hirq_mask}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jnhjMhMchj ubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h``irq_unmask`` h]jo)}(h``irq_unmask``h]j)}(hj h]h irq_unmask}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jnhjMhMehj ubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h7``irq_eoi`` - Optional, required for EOI flow handlers h]jo)}(h6``irq_eoi`` - Optional, required for EOI flow handlersh](j)}(h ``irq_eoi``h]hirq_eoi}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh+ - Optional, required for EOI flow handlers}(h+ - Optional, required for EOI flow handlershj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhMghjubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h``irq_retrigger`` - Optional h]jo)}(h``irq_retrigger`` - Optionalh](j)}(h``irq_retrigger``h]h irq_retrigger}(hhhj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh - Optional}(h - Optionalhj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhMihj,ubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h``irq_set_type`` - Optional h]jo)}(h``irq_set_type`` - Optionalh](j)}(h``irq_set_type``h]h irq_set_type}(hhhj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh - Optional}(h - OptionalhjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhMkhjSubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubj0)}(h``irq_set_wake`` - Optional h]jo)}(h``irq_set_wake`` - Optionalh](j)}(h``irq_set_wake``h]h irq_set_wake}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubh - Optional}(h - Optionalhj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjMhMmhjzubah}(h]h ]h"]h$]h&]uh1j/hjx hhhjMhNubeh}(h]h ]h"]h$]h&]jjuh1j*hjMhM_hj0 hhubjo)}(hThese primitives are strictly intended to mean what they say: ack means ACK, masking means masking of an IRQ line, etc. It is up to the flow handler(s) to use these basic units of low-level functionality.h]hThese primitives are strictly intended to mean what they say: ack means ACK, masking means masking of an IRQ line, etc. It is up to the flow handler(s) to use these basic units of low-level functionality.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMohj0 hhubeh}(h]!chip-level-hardware-encapsulationah ]h"]!chip-level hardware encapsulationah$]h&]uh1j8hjhhhjMhMYubeh}(h]abstraction-layersah ]h"]abstraction layersah$]h&]uh1j8hj:hhhjMhKbubj9)}(hhh](j>)}(h__do_IRQ entry pointh]h__do_IRQ entry point}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhMtubjo)}(hwThe original implementation __do_IRQ() was an alternative entry point for all types of interrupts. It no longer exists.h]hwThe original implementation __do_IRQ() was an alternative entry point for all types of interrupts. It no longer exists.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMvhjhhubjo)}(hThis handler turned out to be not suitable for all interrupt hardware and was therefore reimplemented with split functionality for edge/level/simple/percpu interrupts. This is not only a functional optimization. It also shortens code paths for interrupts.h]hThis handler turned out to be not suitable for all interrupt hardware and was therefore reimplemented with split functionality for edge/level/simple/percpu interrupts. This is not only a functional optimization. It also shortens code paths for interrupts.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMyhjhhubeh}(h]do-irq-entry-pointah ]h"]__do_irq entry pointah$]h&]uh1j8hj:hhhjMhMtubj9)}(hhh](j>)}(hLocking on SMPh]hLocking on SMP}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1j=hjhhhjMhMubjo)}(hThe locking of chip registers is up to the architecture that defines the chip primitives. The per-irq structure is protected via desc->lock, by the generic layer.h]hThe locking of chip registers is up to the architecture that defines the chip primitives. The per-irq structure is protected via desc->lock, by the generic layer.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhjhhubeh}(h]locking-on-smpah ]h"]locking on smpah$]h&]uh1j8hj:hhhjMhMubj9)}(hhh](j>)}(hGeneric interrupt chiph]hGeneric interrupt chip}(hj&hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj!hhhjMhMubjo)}(hXTo avoid copies of identical implementations of IRQ chips the core provides a configurable generic interrupt chip implementation. Developers should check carefully whether the generic chip fits their needs before implementing the same functionality slightly differently themselves.h]hXTo avoid copies of identical implementations of IRQ chips the core provides a configurable generic interrupt chip implementation. Developers should check carefully whether the generic chip fits their needs before implementing the same functionality slightly differently themselves.}(hj4hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhj!hhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleirq_gc_noop (C function) c.irq_gc_noophNtauh1j@hj!hhhNhNubhdesc)}(hhh](hdesc_signature)}(h%void irq_gc_noop (struct irq_data *d)h]hdesc_signature_line)}(h$void irq_gc_noop(struct irq_data *d)h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hhhjdhhhNhNubah}(h]h ]ktah"]h$]h&]uh1jbhj^hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKubhdesc_sig_space)}(h h]h }(hhhjvhhhNhNubah}(h]h ]wah"]h$]h&]uh1jthj^hhhjshKubh desc_name)}(h irq_gc_nooph]h desc_sig_name)}(h irq_gc_nooph]h irq_gc_noop}(hhhjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhj^hhhjshKubhdesc_parameterlist)}(h(struct irq_data *d)h]hdesc_parameter)}(hstruct irq_data *dh](hdesc_sig_keyword)}(hstructh]hstruct}(hhhjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftype identifier reftargetjmodnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]j ASTIdentifier)}jjsb c.irq_gc_noopasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubhdesc_sig_punctuation)}(h*h]h*}(hhhj hhhNhNubah}(h]h ]pah"]h$]h&]uh1jhjubj)}(hdh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj^hhhjshKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1j\sphinx_line_type declaratorhjXhhhjshKubah}(h]jOah ](sig sig-objecteh"]h$]h&] is_multilineuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjShhubh desc_content)}(hhh]jo)}(h NOOP functionh]h NOOP function}(hjNhjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjIhhubah}(h]h ]h"]h$]h&]uh1jGhjShhhjshKubeh}(h]h ](jY functioneh"]h$]h&]domainjY objtypejddesctypejdnoindexuh1jQhhhj!hNhNubh container)}(h1**Parameters** ``struct irq_data *d`` irq_datah](jo)}(h**Parameters**h]hstrong)}(hjth]h Parameters}(hhhjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjrubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjnubhdefinition_list)}(hhh]hdefinition_list_item)}(h``struct irq_data *d`` irq_datah](hterm)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubh definition)}(hhh]jo)}(hirq_datah]hirq_data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_gc_mask_disable_reg (C function)c.irq_gc_mask_disable_reghNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h1void irq_gc_mask_disable_reg (struct irq_data *d)h]j])}(h0void irq_gc_mask_disable_reg(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhK ubj)}(hirq_gc_mask_disable_regh]j)}(hirq_gc_mask_disable_regh]hirq_gc_mask_disable_reg}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhK ubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hhhj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubju)}(h h]h }(hhhjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj0ubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjTmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_mask_disable_regasbuh1hhj0ubju)}(h h]h }(hhhjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj0ubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubj)}(hjh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj,ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhK ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhK ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK%hjhhubjH)}(hhh]jo)}(hMask chip via disable registerh]hMask chip via disable register}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhK ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj!hNhNubjm)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has separate enable/disable registers instead of a single mask register.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK#hjubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjh]hstruct irq_data *d}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK hjubj)}(hhh]jo)}(hirq_datah]hirq_data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj hK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hK hjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hj3h]h Description}(hhhj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj1ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK"hjubjo)}(hMChip has separate enable/disable registers instead of a single mask register.h]hMChip has separate enable/disable registers instead of a single mask register.}(hjKhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK"hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM irq_gc_mask_set_bit (C function)c.irq_gc_mask_set_bithNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h-void irq_gc_mask_set_bit (struct irq_data *d)h]j])}(h,void irq_gc_mask_set_bit(struct irq_data *d)h](jc)}(hvoidh]hvoid}(hhhjxhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjthhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK4ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjthhhjhK4ubj)}(hirq_gc_mask_set_bith]j)}(hirq_gc_mask_set_bith]hirq_gc_mask_set_bit}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjthhhjhK4ubj)}(h(struct irq_data *d)h]j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_mask_set_bitasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjthhhjhK4ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjphhhjhK4ubah}(h]jkah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK9hjmhhubjH)}(hhh]jo)}(h*Mask chip via setting bit in mask registerh]h*Mask chip via setting bit in mask register}(hj:hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK3hj5hhubah}(h]h ]h"]h$]h&]uh1jGhjmhhhjhK4ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijPjjjPjkuh1jQhhhj!hNhNubjm)}(h**Parameters** ``struct irq_data *d`` irq_data **Description** Chip has a single mask register. Values of this register are cached and protected by gc->lockh](jo)}(h**Parameters**h]jw)}(hjZh]h Parameters}(hhhj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjXubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK7hjTubj)}(hhh]j)}(h ``struct irq_data *d`` irq_data h](j)}(h``struct irq_data *d``h]j)}(hjyh]hstruct irq_data *d}(hhhj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK4hjsubj)}(hhh]jo)}(hirq_datah]hirq_data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhK4hjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjhK4hjpubah}(h]h ]h"]h$]h&]uh1jhjTubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK6hjTubjo)}(h]Chip has a single mask register. Values of this register are cached and protected by gc->lockh]h]Chip has a single mask register. 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]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_gc_unmask_enable_regasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjvhhhjhK\ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjrhhhjhK\ubah}(h]jmah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKahjohhubjH)}(hhh]jo)}(hUnmask chip via enable registerh]hUnmask chip via enable register}(hj<hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chK[hj7hhubah}(h]h ]h"]h$]h&]uh1jGhjohhhjhK\ubeh}(h]h ](jY functioneh"]h$]h&]jhjY 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]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjysbc.irq_gc_set_wakeasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hjh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int onh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(honh]hon}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjRhhhjdhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjNhhhjdhKubah}(h]jIah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjKhhubjH)}(hhh]jo)}(h!Set/clr wake bit for an interrupth]h!Set/clr wake bit for an interrupt}(hjihjghhhNhNubah}(h]h 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configured in a separate register and the wakeup active state is just stored in a bitmask.h]hFor chips where the wake from suspend functionality is not configured in a separate register and the wakeup active state is just stored in a bitmask.}(hj4hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#irq_alloc_generic_chip (C function)c.irq_alloc_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hstruct irq_chip_generic * irq_alloc_generic_chip (const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h]j])}(hstruct irq_chip_generic *irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h](j)}(hjh]hstruct}(hhhjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKubju)}(h h]h }(hhhjohhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]hhhjnhKubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jirq_alloc_generic_chipsbc.irq_alloc_generic_chipasbuh1hhj]hhhjnhKubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]hhhjnhKubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]hhhjnhKubj)}(hirq_alloc_generic_chiph]j)}(hjh]hirq_alloc_generic_chip}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]hhhjnhKubj)}(hi(const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler)h](j)}(hconst char *nameh](j)}(hconsth]hconst}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hcharh]hchar}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hnameh]hname}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(h int num_cth](jc)}(hinth]hint}(hhhj9hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj5ubju)}(h h]h }(hhhjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubj)}(hnum_cth]hnum_ct}(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int irq_baseh](jc)}(hunsignedh]hunsigned}(hhhjnhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjjubju)}(h h]h }(hhhj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjjubj)}(hirq_baseh]hirq_base}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hvoid __iomem *reg_baseh](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__iomem}(hhhjhhhNhNubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hreg_baseh]hreg_base}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hirq_flow_handler_t handlerh](h)}(hhh]j)}(hirq_flow_handler_th]hirq_flow_handler_t}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]jc.irq_alloc_generic_chipasbuh1hhjubju)}(h h]h }(hhhj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hhhjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj]hhhjnhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjYhhhjnhKubah}(h]jTah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjVhhubjH)}(hhh]jo)}(h)Allocate a generic chip and initialize ith]h)Allocate a generic chip and initialize it}(hjohjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjjhhubah}(h]h ]h"]h$]h&]uh1jGhjVhhhjnhKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj!hNhNubjm)}(hX**Parameters** ``const char *name`` Name of the irq chip ``int num_ct`` Number of irq_chip_type instances associated with this ``unsigned int irq_base`` Interrupt base nr for this chip ``void __iomem *reg_base`` Register base address (virtual) ``irq_flow_handler_t handler`` Default flow handler associated with this chip **Description** Returns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and **handler**h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubj)}(hhh](j)}(h*``const char *name`` Name of the irq chip h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubj)}(hhh]jo)}(hName of the irq chiph]hName of the irq chip}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(hF``int num_ct`` Number of irq_chip_type instances associated with this h](j)}(h``int num_ct``h]j)}(hjh]h int num_ct}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubj)}(hhh]jo)}(h6Number of irq_chip_type instances associated with thish]h6Number of irq_chip_type instances associated with this}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubj)}(h:``unsigned int irq_base`` Interrupt base nr for this chip h](j)}(h``unsigned int irq_base``h]j)}(hj h]hunsigned int irq_base}(hhhj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubj)}(hhh]jo)}(hInterrupt base nr for this chiph]hInterrupt base nr for this chip}(hj;hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj5hKhj6ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj5hKhjubj)}(h;``void __iomem *reg_base`` Register base address (virtual) h](j)}(h``void __iomem *reg_base``h]j)}(hjYh]hvoid __iomem *reg_base}(hhhj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjSubj)}(hhh]jo)}(hRegister base address (virtual)h]hRegister base address (virtual)}(hjthjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjnhKhjoubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhjnhKhjubj)}(hN``irq_flow_handler_t handler`` Default flow handler associated with this chip h](j)}(h``irq_flow_handler_t handler``h]j)}(hjh]hirq_flow_handler_t handler}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubj)}(hhh]jo)}(h.Default flow handler associated with this chiph]h.Default flow handler associated with this chip}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubeh}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubjo)}(h{Returns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and **handler**h](hpReturns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and }(hpReturns an initialized irq_chip_generic structure. The chip defaults to the primary (index 0) irq_chip_type and hjhhhNhNubjw)}(h **handler**h]hhandler}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubeh}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chKhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM-__irq_alloc_domain_generic_chips (C function)"c.__irq_alloc_domain_generic_chipshNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hint __irq_alloc_domain_generic_chips (struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h]j])}(hint __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h](jc)}(hinth]hint}(hhhj!hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hhhj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj/hMubj)}(h __irq_alloc_domain_generic_chipsh]j)}(h __irq_alloc_domain_generic_chipsh]h __irq_alloc_domain_generic_chips}(hhhjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj/hMubj)}(h(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags)h](j)}(hstruct irq_domain *dh](j)}(hjh]hstruct}(hhhj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubju)}(h h]h }(hhhjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hhhj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj~modnameN classnameNjj)}j]j)}jjDsb"c.__irq_alloc_domain_generic_chipsasbuh1hhjZubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubj)}(hjh]hd}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(hint irqs_per_chiph](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(h irqs_per_chiph]h irqs_per_chip}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(h int num_cth](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hnum_cth]hnum_ct}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(hconst char *nameh](j)}(hjh]hconst}(hhhj9hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubju)}(h h]h }(hhhjFhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubjc)}(hcharh]hchar}(hhhjThhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj5ubju)}(h h]h }(hhhjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj5ubj )}(hj h]h*}(hhhjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubj)}(hnameh]hname}(hhhj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(hirq_flow_handler_t handlerh](h)}(hhh]j)}(hirq_flow_handler_th]hirq_flow_handler_t}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j"c.__irq_alloc_domain_generic_chipsasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hclrh]hclr}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hhhj/ hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ ubju)}(h h]h }(hhhj= hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ ubjc)}(hinth]hint}(hhhjK hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ ubju)}(h h]h }(hhhjY hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ ubj)}(hseth]hset}(hhhjg hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubj)}(henum irq_gc_flags gcflagsh](j)}(henumh]henum}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj| ubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj| ubh)}(hhh]j)}(h irq_gc_flagsh]h irq_gc_flags}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj modnameN classnameNjj)}j]j"c.__irq_alloc_domain_generic_chipsasbuh1hhj| ubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj| ubj)}(hgcflagsh]hgcflags}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj| ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj/hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj/hMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM!hjhhubjH)}(hhh]jo)}(h(Allocate generic chips for an irq domainh]h(Allocate generic chips for an irq domain}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj/hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij!jjj!jkuh1jQhhhj!hNhNubjm)}(hX,**Parameters** ``struct irq_domain *d`` irq domain for which to allocate chips ``int irqs_per_chip`` Number of interrupts each chip handles (max 32) ``int num_ct`` Number of irq_chip_type instances associated with this ``const char *name`` Name of the irq chip ``irq_flow_handler_t handler`` Default flow handler associated with these chips ``unsigned int clr`` IRQ_* bits to clear in the mapping function ``unsigned int set`` IRQ_* bits to set in the mapping function ``enum irq_gc_flags gcflags`` Generic chip specific setup flagsh](jo)}(h**Parameters**h]jw)}(hj!h]h Parameters}(hhhj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj!ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj!ubj)}(hhh](j)}(h@``struct irq_domain *d`` irq domain for which to allocate chips h](j)}(h``struct irq_domain *d``h]j)}(hj7!h]hstruct irq_domain *d}(hhhj9!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj1!ubj)}(hhh]jo)}(h&irq domain for which to allocate chipsh]h&irq domain for which to allocate chips}(hjR!hjP!hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjL!hMhjM!ubah}(h]h ]h"]h$]h&]uh1jhj1!ubeh}(h]h ]h"]h$]h&]uh1jhjL!hMhj.!ubj)}(hF``int irqs_per_chip`` Number of interrupts each chip handles (max 32) h](j)}(h``int irqs_per_chip``h]j)}(hjp!h]hint irqs_per_chip}(hhhjr!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjn!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjj!ubj)}(hhh]jo)}(h/Number of interrupts each chip handles (max 32)h]h/Number of interrupts each chip handles (max 32)}(hj!hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1jhjj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMhj.!ubj)}(hF``int num_ct`` Number of irq_chip_type instances associated with this h](j)}(h``int num_ct``h]j)}(hj!h]h int num_ct}(hhhj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj!ubj)}(hhh]jo)}(h6Number of irq_chip_type instances associated with thish]h6Number of irq_chip_type instances associated with this}(hj!hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMhj.!ubj)}(h*``const char *name`` Name of the irq chip h](j)}(h``const char *name``h]j)}(hj!h]hconst char *name}(hhhj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj!ubj)}(hhh]jo)}(hName of the irq chiph]hName of the irq chip}(hj!hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj!hMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhj!hMhj.!ubj)}(hP``irq_flow_handler_t handler`` Default flow handler associated with these chips h](j)}(h``irq_flow_handler_t handler``h]j)}(hj"h]hirq_flow_handler_t handler}(hhhj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj"ubj)}(hhh]jo)}(h0Default flow handler associated with these chipsh]h0Default flow handler associated with these chips}(hj6"hj4"hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj0"hMhj1"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj0"hMhj.!ubj)}(hA``unsigned int clr`` IRQ_* bits to clear in the mapping function h](j)}(h``unsigned int clr``h]j)}(hjT"h]hunsigned int clr}(hhhjV"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjN"ubj)}(hhh]jo)}(h+IRQ_* bits to clear in the mapping functionh]h+IRQ_* bits to clear in the mapping function}(hjo"hjm"hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhji"hMhjj"ubah}(h]h ]h"]h$]h&]uh1jhjN"ubeh}(h]h ]h"]h$]h&]uh1jhji"hMhj.!ubj)}(h?``unsigned int set`` IRQ_* bits to set in the mapping function h](j)}(h``unsigned int set``h]j)}(hj"h]hunsigned int set}(hhhj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj"ubj)}(hhh]jo)}(h)IRQ_* bits to set in the mapping functionh]h)IRQ_* bits to set in the mapping function}(hj"hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj"hMhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hMhj.!ubj)}(h?``enum irq_gc_flags gcflags`` Generic chip specific setup flagsh](j)}(h``enum irq_gc_flags gcflags``h]j)}(hj"h]henum irq_gc_flags gcflags}(hhhj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM hj"ubj)}(hhh]jo)}(h!Generic chip specific setup flagsh]h!Generic chip specific setup flags}(hj"hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj"hM hj.!ubeh}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM(irq_get_domain_generic_chip (C function)c.irq_get_domain_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hastruct irq_chip_generic * irq_get_domain_generic_chip (struct irq_domain *d, unsigned int hw_irq)h]j])}(h_struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)h](j)}(hjh]hstruct}(hhhj #hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMnubju)}(h h]h }(hhhj.#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#hhhj-#hMnubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hhhj?#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<#ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjA#modnameN classnameNjj)}j]j)}jirq_get_domain_generic_chipsbc.irq_get_domain_generic_chipasbuh1hhj#hhhj-#hMnubju)}(h h]h }(hhhj`#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#hhhj-#hMnubj )}(hj h]h*}(hhhjn#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#hhhj-#hMnubj)}(hirq_get_domain_generic_chiph]j)}(hj]#h]hirq_get_domain_generic_chip}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj{#ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj#hhhj-#hMnubj)}(h+(struct irq_domain *d, unsigned int hw_irq)h](j)}(hstruct irq_domain *dh](j)}(hjh]hstruct}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubju)}(h h]h }(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj#modnameN classnameNjj)}j]j[#c.irq_get_domain_generic_chipasbuh1hhj#ubju)}(h h]h }(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj#ubj )}(hj h]h*}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubj)}(hjh]hd}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubj)}(hunsigned int hw_irqh](jc)}(hunsignedh]hunsigned}(hhhj $hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj$ubju)}(h h]h }(hhhj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$ubjc)}(hinth]hint}(hhhj%$hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj$ubju)}(h h]h }(hhhj3$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$ubj)}(hhw_irqh]hhw_irq}(hhhjA$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj#ubeh}(h]h ]h"]h$]h&]hhuh1jhj#hhhj-#hMnubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj#hhhj-#hMnubah}(h]j#ah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMqhj#hhubjH)}(hhh]jo)}(h-Get a pointer to the generic chip of a hw_irqh]h-Get a pointer to the generic chip of a hw_irq}(hjn$hjl$hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMmhji$hhubah}(h]h ]h"]h$]h&]uh1jGhj#hhhj-#hMnubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij$jjj$jkuh1jQhhhj!hNhNubjm)}(hr**Parameters** ``struct irq_domain *d`` irq domain pointer ``unsigned int hw_irq`` Hardware interrupt numberh](jo)}(h**Parameters**h]jw)}(hj$h]h Parameters}(hhhj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj$ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMqhj$ubj)}(hhh](j)}(h,``struct irq_domain *d`` irq domain pointer h](j)}(h``struct irq_domain *d``h]j)}(hj$h]hstruct irq_domain *d}(hhhj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMnhj$ubj)}(hhh]jo)}(hirq domain pointerh]hirq domain pointer}(hj$hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj$hMnhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMnhj$ubj)}(h1``unsigned int hw_irq`` Hardware interrupt numberh](j)}(h``unsigned int hw_irq``h]j)}(hj$h]hunsigned int hw_irq}(hhhj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMphj$ubj)}(hhh]jo)}(hHardware interrupt numberh]hHardware interrupt number}(hj%hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMohj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj$hMphj$ubeh}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#irq_setup_generic_chip (C function)c.irq_setup_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hvoid irq_setup_generic_chip (struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h]j])}(h~void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h](jc)}(hvoidh]hvoid}(hhhj@%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj<%hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hhhjO%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<%hhhjN%hMubj)}(hirq_setup_generic_chiph]j)}(hirq_setup_generic_chiph]hirq_setup_generic_chip}(hhhja%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]%ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj<%hhhjN%hMubj)}(hc(struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set)h](j)}(hstruct irq_chip_generic *gch](j)}(hjh]hstruct}(hhhj}%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy%ubju)}(h h]h }(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjy%ubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj%modnameN classnameNjj)}j]j)}jjc%sbc.irq_setup_generic_chipasbuh1hhjy%ubju)}(h h]h }(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjy%ubj )}(hj h]h*}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy%ubj)}(hgch]hgc}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjy%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju%ubj)}(hu32 mskh](h)}(hhh]j)}(hu32h]hu32}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj%modnameN classnameNjj)}j]j%c.irq_setup_generic_chipasbuh1hhj%ubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj%ubj)}(hmskh]hmsk}(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju%ubj)}(henum irq_gc_flags flagsh](j)}(hj h]henum}(hhhj7&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3&ubju)}(h h]h }(hhhjD&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3&ubh)}(hhh]j)}(h irq_gc_flagsh]h irq_gc_flags}(hhhjU&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR&ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjW&modnameN classnameNjj)}j]j%c.irq_setup_generic_chipasbuh1hhj3&ubju)}(h h]h }(hhhjs&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj3&ubj)}(hflagsh]hflags}(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj3&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju%ubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hhhj&hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&ubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubjc)}(hinth]hint}(hhhj&hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&ubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubj)}(hclrh]hclr}(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju%ubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hhhj&hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&ubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubjc)}(hinth]hint}(hhhj'hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&ubju)}(h h]h }(hhhj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&ubj)}(hseth]hset}(hhhj#'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhju%ubeh}(h]h ]h"]h$]h&]hhuh1jhj<%hhhjN%hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj8%hhhjN%hMubah}(h]j3%ah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj5%hhubjH)}(hhh]jo)}(h/Setup a range of interrupts with a generic chiph]h/Setup a range of interrupts with a generic chip}(hjP'hjN'hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjK'hhubah}(h]h ]h"]h$]h&]uh1jGhj5%hhhjN%hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijf'jjjf'jkuh1jQhhhj!hNhNubjm)}(hX**Parameters** ``struct irq_chip_generic *gc`` Generic irq chip holding all data ``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base ``enum irq_gc_flags flags`` Flags for initialization ``unsigned int clr`` IRQ_* bits to clear ``unsigned int set`` IRQ_* bits to set **Description** Set up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.h](jo)}(h**Parameters**h]jw)}(hjp'h]h Parameters}(hhhjr'hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjn'ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjj'ubj)}(hhh](j)}(hB``struct irq_chip_generic *gc`` Generic irq chip holding all data h](j)}(h``struct irq_chip_generic *gc``h]j)}(hj'h]hstruct irq_chip_generic *gc}(hhhj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj'ubj)}(hhh]jo)}(h!Generic irq chip holding all datah]h!Generic irq chip holding all data}(hj'hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj'ubj)}(hL``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base h](j)}(h ``u32 msk``h]j)}(hj'h]hu32 msk}(hhhj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj'ubj)}(hhh]jo)}(h?Bitmask holding the irqs to initialize relative to gc->irq_baseh]h?Bitmask holding the irqs to initialize relative to gc->irq_base}(hj'hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj'hMhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj'hMhj'ubj)}(h5``enum irq_gc_flags flags`` Flags for initialization h](j)}(h``enum irq_gc_flags flags``h]j)}(hj(h]henum irq_gc_flags flags}(hhhj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj'ubj)}(hhh]jo)}(hFlags for initializationh]hFlags for initialization}(hj(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj(hMhj(ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhj'ubj)}(h)``unsigned int clr`` IRQ_* bits to clear h](j)}(h``unsigned int clr``h]j)}(hj:(h]hunsigned int clr}(hhhj<(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj4(ubj)}(hhh]jo)}(hIRQ_* bits to clearh]hIRQ_* bits to clear}(hjU(hjS(hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjO(hMhjP(ubah}(h]h ]h"]h$]h&]uh1jhj4(ubeh}(h]h ]h"]h$]h&]uh1jhjO(hMhj'ubj)}(h'``unsigned int set`` IRQ_* bits to set h](j)}(h``unsigned int set``h]j)}(hjs(h]hunsigned int set}(hhhju(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjq(ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjm(ubj)}(hhh]jo)}(hIRQ_* bits to seth]hIRQ_* bits to set}(hj(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj(hMhj(ubah}(h]h ]h"]h$]h&]uh1jhjm(ubeh}(h]h ]h"]h$]h&]uh1jhj(hMhj'ubeh}(h]h ]h"]h$]h&]uh1jhjj'ubjo)}(h**Description**h]jw)}(hj(h]h Description}(hhhj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj(ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjj'ubjo)}(hSet up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.h]hSet up max. 32 interrupts starting from gc->irq_base. Note, this initializes all interrupts to the primary irq_chip_type and its associated handler.}(hj(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjj'ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_setup_alt_chip (C function)c.irq_setup_alt_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(h>int irq_setup_alt_chip (struct irq_data *d, unsigned int type)h]j])}(h=int irq_setup_alt_chip(struct irq_data *d, unsigned int type)h](jc)}(hinth]hint}(hhhj(hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj(hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj(hhhj)hMubj)}(hirq_setup_alt_chiph]j)}(hirq_setup_alt_chiph]hirq_setup_alt_chip}(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj(hhhj)hMubj)}(h'(struct irq_data *d, unsigned int type)h](j)}(hstruct irq_data *dh](j)}(hjh]hstruct}(hhhj0)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,)ubju)}(h h]h }(hhhj=)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj,)ubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjN)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjK)ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjP)modnameN classnameNjj)}j]j)}jj)sbc.irq_setup_alt_chipasbuh1hhj,)ubju)}(h h]h }(hhhjn)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj,)ubj )}(hj h]h*}(hhhj|)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,)ubj)}(hjh]hd}(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj()ubj)}(hunsigned int typeh](jc)}(hunsignedh]hunsigned}(hhhj)hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj)ubju)}(h h]h }(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)ubjc)}(hinth]hint}(hhhj)hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj)ubju)}(h h]h }(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)ubj)}(htypeh]htype}(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj()ubeh}(h]h ]h"]h$]h&]hhuh1jhj(hhhj)hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj(hhhj)hMubah}(h]j(ah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM hj(hhubjH)}(hhh]jo)}(hSwitch to alternative chiph]hSwitch to alternative chip}(hj*hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj*hhubah}(h]h ]h"]h$]h&]uh1jGhj(hhhj)hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij*jjj*jkuh1jQhhhj!hNhNubjm)}(h**Parameters** ``struct irq_data *d`` irq_data for this interrupt ``unsigned int type`` Flow type to be initialized **Description** Only to be called from chip->irq_set_type() callbacks.h](jo)}(h**Parameters**h]jw)}(hj&*h]h Parameters}(hhhj(*hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj$*ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj *ubj)}(hhh](j)}(h3``struct irq_data *d`` irq_data for this interrupt h](j)}(h``struct irq_data *d``h]j)}(hjE*h]hstruct irq_data *d}(hhhjG*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjC*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj?*ubj)}(hhh]jo)}(hirq_data for this interrupth]hirq_data for this interrupt}(hj`*hj^*hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjZ*hMhj[*ubah}(h]h ]h"]h$]h&]uh1jhj?*ubeh}(h]h ]h"]h$]h&]uh1jhjZ*hMhj<*ubj)}(h2``unsigned int type`` Flow type to be initialized h](j)}(h``unsigned int type``h]j)}(hj~*h]hunsigned int type}(hhhj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|*ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjx*ubj)}(hhh]jo)}(hFlow type to be initializedh]hFlow type to be initialized}(hj*hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj*hMhj*ubah}(h]h ]h"]h$]h&]uh1jhjx*ubeh}(h]h ]h"]h$]h&]uh1jhj*hMhj<*ubeh}(h]h ]h"]h$]h&]uh1jhj *ubjo)}(h**Description**h]jw)}(hj*h]h Description}(hhhj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj*ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj *ubjo)}(h6Only to be called from chip->irq_set_type() callbacks.h]h6Only to be called from chip->irq_set_type() callbacks.}(hj*hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj *ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_remove_generic_chip (C function)c.irq_remove_generic_chiphNtauh1j@hj!hhhNhNubjR)}(hhh](jW)}(hgvoid irq_remove_generic_chip (struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h]j])}(hfvoid irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h](jc)}(hvoidh]hvoid}(hhhj*hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj*hhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMubju)}(h h]h }(hhhj +hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj*hhhj +hMubj)}(hirq_remove_generic_chiph]j)}(hirq_remove_generic_chiph]hirq_remove_generic_chip}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj*hhhj +hMubj)}(hJ(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set)h](j)}(hstruct irq_chip_generic *gch](j)}(hjh]hstruct}(hhhj;+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7+ubju)}(h h]h }(hhhjH+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj7+ubh)}(hhh]j)}(hirq_chip_generich]hirq_chip_generic}(hhhjY+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjV+ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj[+modnameN classnameNjj)}j]j)}jj!+sbc.irq_remove_generic_chipasbuh1hhj7+ubju)}(h h]h }(hhhjy+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj7+ubj )}(hj h]h*}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7+ubj)}(hgch]hgc}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj7+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj3+ubj)}(hu32 mskh](h)}(hhh]j)}(hu32h]hu32}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj+modnameN classnameNjj)}j]ju+c.irq_remove_generic_chipasbuh1hhj+ubju)}(h h]h }(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ubj)}(hmskh]hmsk}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj3+ubj)}(hunsigned int clrh](jc)}(hunsignedh]hunsigned}(hhhj+hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ubju)}(h h]h }(hhhj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ubjc)}(hinth]hint}(hhhj,hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj+ubju)}(h h]h }(hhhj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj+ubj)}(hclrh]hclr}(hhhj-,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj3+ubj)}(hunsigned int seth](jc)}(hunsignedh]hunsigned}(hhhjF,hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjB,ubju)}(h h]h }(hhhjT,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjB,ubjc)}(hinth]hint}(hhhjb,hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjB,ubju)}(h h]h }(hhhjp,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjB,ubj)}(hseth]hset}(hhhj~,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjB,ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj3+ubeh}(h]h ]h"]h$]h&]hhuh1jhj*hhhj +hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj*hhhj +hMubah}(h]j*ah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM$hj*hhubjH)}(hhh]jo)}(h Remove a chiph]h Remove a chip}(hj,hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj,hhubah}(h]h ]h"]h$]h&]uh1jGhj*hhhj +hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij,jjj,jkuh1jQhhhj!hNhNubjm)}(hXA**Parameters** ``struct irq_chip_generic *gc`` Generic irq chip holding all data ``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base ``unsigned int clr`` IRQ_* bits to clear ``unsigned int set`` IRQ_* bits to set **Description** Remove up to 32 interrupts starting from gc->irq_base.h](jo)}(h**Parameters**h]jw)}(hj,h]h Parameters}(hhhj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj,ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM hj,ubj)}(hhh](j)}(hB``struct irq_chip_generic *gc`` Generic irq chip holding all data h](j)}(h``struct irq_chip_generic *gc``h]j)}(hj,h]hstruct irq_chip_generic *gc}(hhhj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj,ubj)}(hhh]jo)}(h!Generic irq chip holding all datah]h!Generic irq chip holding all data}(hj-hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj,hMhj-ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj,hMhj,ubj)}(hL``u32 msk`` Bitmask holding the irqs to initialize relative to gc->irq_base h](j)}(h ``u32 msk``h]j)}(hj#-h]hu32 msk}(hhhj%-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhj-ubj)}(hhh]jo)}(h?Bitmask holding the irqs to initialize relative to gc->irq_baseh]h?Bitmask holding the irqs to initialize relative to gc->irq_base}(hj>-hj<-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj8-hMhj9-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj8-hMhj,ubj)}(h)``unsigned int clr`` IRQ_* bits to clear h](j)}(h``unsigned int clr``h]j)}(hj\-h]hunsigned int clr}(hhhj^-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chMhjV-ubj)}(hhh]jo)}(hIRQ_* bits to clearh]hIRQ_* bits to clear}(hjw-hju-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjq-hMhjr-ubah}(h]h ]h"]h$]h&]uh1jhjV-ubeh}(h]h ]h"]h$]h&]uh1jhjq-hMhj,ubj)}(h'``unsigned int set`` IRQ_* bits to set h](j)}(h``unsigned int set``h]j)}(hj-h]hunsigned int set}(hhhj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM hj-ubj)}(hhh]jo)}(hIRQ_* bits to seth]hIRQ_* bits to set}(hj-hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj-hM hj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jhj-hM hj,ubeh}(h]h ]h"]h$]h&]uh1jhj,ubjo)}(h**Description**h]jw)}(hj-h]h Description}(hhhj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj-ubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM"hj,ubjo)}(h6Remove up to 32 interrupts starting from gc->irq_base.h]h6Remove up to 32 interrupts starting from gc->irq_base.}(hj-hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:482: ./kernel/irq/generic-chip.chM"hj,ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj!hhhNhNubeh}(h]generic-interrupt-chipah ]h"]generic interrupt chipah$]h&]uh1j8hj:hhhjMhMubj9)}(hhh](j>)}(h Structuresh]h Structures}(hj .hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j=hj.hhhjMhMubjo)}(hpThis chapter contains the autogenerated documentation of the structures which are used in the generic IRQ layer.h]hpThis chapter contains the autogenerated documentation of the structures which are used in the generic IRQ layer.}(hj.hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjMhMhj.hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_common_data (C struct)c.irq_common_datahNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(hirq_common_datah]j])}(hstruct irq_common_datah](j)}(hjh]hstruct}(hhhj<.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8.hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKubju)}(h h]h }(hhhjJ.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8.hhhjI.hKubj)}(hirq_common_datah]j)}(hj6.h]hirq_common_data}(hhhj\.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjX.ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj8.hhhjI.hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj4.hhhjI.hKubah}(h]j/.ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj1.hhubjH)}(hhh]jo)}(h#per irq data shared by all irqchipsh]h#per irq data shared by all irqchips}(hj.hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj|.hhubah}(h]h ]h"]h$]h&]uh1jGhj1.hhhjI.hKubeh}(h]h ](jY structeh"]h$]h&]jhjY jij.jjj.jkuh1jQhhhj.hNhNubjm)}(hXN**Definition**:: struct irq_common_data { unsigned int __private state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; }; **Members** ``state_use_accessors`` status information for irq chip functions. Use accessor functions to deal with it ``node`` node index useful for balancing ``handler_data`` per-IRQ data for the irq_chip methods ``msi_desc`` MSI descriptor ``affinity`` IRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent. ``effective_affinity`` The effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of **affinity**. ``ipi_offset`` Offset of first IPI target cpu in **affinity**. Optional.h](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj.ubh:}(h:hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj.ubj )}(hXstruct irq_common_data { unsigned int __private state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; };h]hXstruct irq_common_data { unsigned int __private state_use_accessors; #ifdef CONFIG_NUMA; unsigned int node; #endif; void *handler_data; struct msi_desc *msi_desc; #ifdef CONFIG_SMP; cpumask_var_t affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK; cpumask_var_t effective_affinity; #endif; #ifdef CONFIG_GENERIC_IRQ_IPI; unsigned int ipi_offset; #endif; };}(hhhj.ubah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj.ubjo)}(h **Members**h]jw)}(hj.h]hMembers}(hhhj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj.ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj.ubj)}(hhh](j)}(hj``state_use_accessors`` status information for irq chip functions. Use accessor functions to deal with it h](j)}(h``state_use_accessors``h]j)}(hj.h]hstate_use_accessors}(hhhj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj.ubj)}(hhh]jo)}(hQstatus information for irq chip functions. Use accessor functions to deal with ith]hQstatus information for irq chip functions. Use accessor functions to deal with it}(hj/hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj/ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jhj/hKhj.ubj)}(h)``node`` node index useful for balancing h](j)}(h``node``h]j)}(hj'/h]hnode}(hhhj)/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%/ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj!/ubj)}(hhh]jo)}(hnode index useful for balancingh]hnode index useful for balancing}(hjB/hj@/hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj``mask`` precomputed bitmask for accessing the chip registers h](j)}(h``mask``h]j)}(hjw1h]hmask}(hhhjy1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhju1ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhjq1ubj)}(hhh]jo)}(h4precomputed bitmask for accessing the chip registersh]h4precomputed bitmask for accessing the chip registers}(hj1hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj1hKhj1ubah}(h]h ]h"]h$]h&]uh1jhjq1ubeh}(h]h ]h"]h$]h&]uh1jhj1hKhjn1ubj)}(h``irq`` interrupt number h](j)}(h``irq``h]j)}(hj1h]hirq}(hhhj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj1ubj)}(hhh]jo)}(hinterrupt numberh]hinterrupt number}(hj1hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj1hKhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hKhjn1ubj)}(hC``hwirq`` hardware interrupt number, local to the interrupt domain h](j)}(h ``hwirq``h]j)}(hj1h]hhwirq}(hhhj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj1ubj)}(hhh]jo)}(h8hardware interrupt number, local to the interrupt domainh]h8hardware interrupt number, local to the interrupt domain}(hj2hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj1hKhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhj1hKhjn1ubj)}(h0``common`` point to data shared by all irqchips h](j)}(h ``common``h]j)}(hj"2h]hcommon}(hhhj$2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 2ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj2ubj)}(hhh]jo)}(h$point to data shared by all irqchipsh]h$point to data shared by all irqchips}(hj=2hj;2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj72hKhj82ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj72hKhjn1ubj)}(h-``chip`` low level interrupt hardware access h](j)}(h``chip``h]j)}(hj[2h]hchip}(hhhj]2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjY2ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhjU2ubj)}(hhh]jo)}(h#low level interrupt hardware accessh]h#low level interrupt hardware access}(hjv2hjt2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjp2hKhjq2ubah}(h]h ]h"]h$]h&]uh1jhjU2ubeh}(h]h ]h"]h$]h&]uh1jhjp2hKhjn1ubj)}(hl``domain`` Interrupt translation domain; responsible for mapping between hwirq number and linux irq number. h](j)}(h ``domain``h]j)}(hj2h]hdomain}(hhhj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj2ubj)}(hhh]jo)}(h`Interrupt translation domain; responsible for mapping between hwirq number and linux irq number.h]h`Interrupt translation domain; responsible for mapping between hwirq number and linux irq number.}(hj2hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hKhjn1ubj)}(hR``parent_data`` pointer to parent struct irq_data to support hierarchy irq_domain h](j)}(h``parent_data``h]j)}(hj2h]h parent_data}(hhhj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj2ubj)}(hhh]jo)}(hApointer to parent struct irq_data to support hierarchy irq_domainh]hApointer to parent struct irq_data to support hierarchy irq_domain}(hj2hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhj2hKhjn1ubj)}(hp``chip_data`` platform-specific per-chip private data for the chip methods, to allow shared chip implementationsh](j)}(h ``chip_data``h]j)}(hj3h]h chip_data}(hhhj 3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhj3ubj)}(hhh]jo)}(hbplatform-specific per-chip private data for the chip methods, to allow shared chip implementationsh]hbplatform-specific per-chip private data for the chip methods, to allow shared chip implementations}(hj#3hj!3hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj3hKhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhj3hKhjn1ubeh}(h]h ]h"]h$]h&]uh1jhj&1ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip (C struct) c.irq_chiphNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(hirq_chiph]j])}(hstruct irq_chiph](j)}(hjh]hstruct}(hhhja3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj]3hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMubju)}(h h]h }(hhhjo3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]3hhhjn3hMubj)}(hirq_chiph]j)}(hj[3h]hirq_chip}(hhhj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}3ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]3hhhjn3hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjY3hhhjn3hMubah}(h]jT3ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhKhjV3hhubjH)}(hhh]jo)}(h"hardware interrupt chip descriptorh]h"hardware interrupt chip descriptor}(hj3hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj3hhubah}(h]h ]h"]h$]h&]uh1jGhjV3hhhjn3hMubeh}(h]h ](jY structeh"]h$]h&]jhjY jij3jjj3jkuh1jQhhhj.hNhNubjm)}(hX **Definition**:: struct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); unsigned long flags; }; **Members** ``name`` name for /proc/interrupts ``irq_startup`` start up the interrupt (defaults to ->enable if NULL) ``irq_shutdown`` shut down the interrupt (defaults to ->disable if NULL) ``irq_enable`` enable the interrupt (defaults to chip->unmask if NULL) ``irq_disable`` disable the interrupt ``irq_ack`` start of a new interrupt ``irq_mask`` mask an interrupt source ``irq_mask_ack`` ack and mask an interrupt source ``irq_unmask`` unmask an interrupt source ``irq_eoi`` end of interrupt ``irq_set_affinity`` Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask. ``irq_retrigger`` resend an IRQ to the CPU ``irq_set_type`` set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ ``irq_set_wake`` enable/disable power-management wake-on of an IRQ ``irq_bus_lock`` function to lock access to slow bus (i2c) chips ``irq_bus_sync_unlock`` function to sync and unlock slow bus (i2c) chips ``irq_cpu_online`` configure an interrupt source for a secondary CPU ``irq_cpu_offline`` un-configure an interrupt source for a secondary CPU ``irq_suspend`` function called from core code on suspend once per chip, when one or more interrupts are installed ``irq_resume`` function called from core code on resume once per chip, when one ore more interrupts are installed ``irq_pm_shutdown`` function called from core code on shutdown once per chip ``irq_calc_mask`` Optional function to set irq_data.mask for special cases ``irq_print_chip`` optional to print special chip info in show_interrupts ``irq_request_resources`` optional to request resources before calling any other callback related to this irq ``irq_release_resources`` optional to release resources acquired with irq_request_resources ``irq_compose_msi_msg`` optional to compose message content for MSI ``irq_write_msi_msg`` optional to write message content for MSI ``irq_get_irqchip_state`` return the internal state of an interrupt ``irq_set_irqchip_state`` set the internal state of a interrupt ``irq_set_vcpu_affinity`` optional to target a vCPU in a virtual machine ``ipi_send_single`` send a single IPI to destination cpus ``ipi_send_mask`` send an IPI to destination cpus in cpumask ``irq_nmi_setup`` function called from core code before enabling an NMI ``irq_nmi_teardown`` function called from core code after disabling an NMI ``flags`` chip specific flagsh](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj3ubh:}(hj.hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj3ubj )}(hX6struct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); unsigned long flags; };h]hX6struct irq_chip { const char *name; unsigned int (*irq_startup)(struct irq_data *data); void (*irq_shutdown)(struct irq_data *data); void (*irq_enable)(struct irq_data *data); void (*irq_disable)(struct irq_data *data); void (*irq_ack)(struct irq_data *data); void (*irq_mask)(struct irq_data *data); void (*irq_mask_ack)(struct irq_data *data); void (*irq_unmask)(struct irq_data *data); void (*irq_eoi)(struct irq_data *data); int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE; void (*irq_cpu_online)(struct irq_data *data); void (*irq_cpu_offline)(struct irq_data *data); #endif; void (*irq_suspend)(struct irq_data *data); void (*irq_resume)(struct irq_data *data); void (*irq_pm_shutdown)(struct irq_data *data); void (*irq_calc_mask)(struct irq_data *data); void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); int (*irq_request_resources)(struct irq_data *data); void (*irq_release_resources)(struct irq_data *data); void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); int (*irq_nmi_setup)(struct irq_data *data); void (*irq_nmi_teardown)(struct irq_data *data); unsigned long flags; };}(hhhj3ubah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj3ubjo)}(h **Members**h]jw)}(hj3h]hMembers}(hhhj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj3ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj3ubj)}(hhh](j)}(h#``name`` name for /proc/interrupts h](j)}(h``name``h]j)}(hj4h]hname}(hhhj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj 4ubj)}(hhh]jo)}(hname for /proc/interruptsh]hname for /proc/interrupts}(hj,4hj*4hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj&4hMhj'4ubah}(h]h ]h"]h$]h&]uh1jhj 4ubeh}(h]h ]h"]h$]h&]uh1jhj&4hMhj4ubj)}(hF``irq_startup`` start up the interrupt (defaults to ->enable if NULL) h](j)}(h``irq_startup``h]j)}(hjJ4h]h irq_startup}(hhhjL4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjH4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjD4ubj)}(hhh]jo)}(h5start up the interrupt (defaults to ->enable if NULL)h]h5start up the interrupt (defaults to ->enable if NULL)}(hje4hjc4hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj_4hMhj`4ubah}(h]h ]h"]h$]h&]uh1jhjD4ubeh}(h]h ]h"]h$]h&]uh1jhj_4hMhj4ubj)}(hI``irq_shutdown`` shut down the interrupt (defaults to ->disable if NULL) h](j)}(h``irq_shutdown``h]j)}(hj4h]h irq_shutdown}(hhhj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj}4ubj)}(hhh]jo)}(h7shut down the interrupt (defaults to ->disable if NULL)h]h7shut down the interrupt (defaults to ->disable if NULL)}(hj4hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj}4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj4ubj)}(hG``irq_enable`` enable the interrupt (defaults to chip->unmask if NULL) h](j)}(h``irq_enable``h]j)}(hj4h]h irq_enable}(hhhj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj4ubj)}(hhh]jo)}(h7enable the interrupt (defaults to chip->unmask if NULL)h]h7enable the interrupt (defaults to chip->unmask if NULL)}(hj4hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj4hMhj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj4hMhj4ubj)}(h&``irq_disable`` disable the interrupt h](j)}(h``irq_disable``h]j)}(hj4h]h irq_disable}(hhhj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj4ubj)}(hhh]jo)}(hdisable the interrupth]hdisable the interrupt}(hj5hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj 5hMhj 5ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jhj 5hMhj4ubj)}(h%``irq_ack`` start of a new interrupt h](j)}(h ``irq_ack``h]j)}(hj.5h]hirq_ack}(hhhj05hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj(5ubj)}(hhh]jo)}(hstart of a new interrupth]hstart of a new interrupt}(hjI5hjG5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjC5hMhjD5ubah}(h]h ]h"]h$]h&]uh1jhj(5ubeh}(h]h ]h"]h$]h&]uh1jhjC5hMhj4ubj)}(h&``irq_mask`` mask an interrupt source h](j)}(h ``irq_mask``h]j)}(hjg5h]hirq_mask}(hhhji5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhje5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhja5ubj)}(hhh]jo)}(hmask an interrupt sourceh]hmask an interrupt source}(hj5hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj|5hMhj}5ubah}(h]h ]h"]h$]h&]uh1jhja5ubeh}(h]h ]h"]h$]h&]uh1jhj|5hMhj4ubj)}(h2``irq_mask_ack`` ack and mask an interrupt source h](j)}(h``irq_mask_ack``h]j)}(hj5h]h irq_mask_ack}(hhhj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj5ubj)}(hhh]jo)}(h ack and mask an interrupt sourceh]h ack and mask an interrupt source}(hj5hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMhj4ubj)}(h*``irq_unmask`` unmask an interrupt source h](j)}(h``irq_unmask``h]j)}(hj5h]h irq_unmask}(hhhj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj5ubj)}(hhh]jo)}(hunmask an interrupt sourceh]hunmask an interrupt source}(hj5hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj5hMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jhj5hMhj4ubj)}(h``irq_eoi`` end of interrupt h](j)}(h ``irq_eoi``h]j)}(hj6h]hirq_eoi}(hhhj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj 6ubj)}(hhh]jo)}(hend of interrupth]hend of interrupt}(hj-6hj+6hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj'6hMhj(6ubah}(h]h ]h"]h$]h&]uh1jhj 6ubeh}(h]h ]h"]h$]h&]uh1jhj'6hMhj4ubj)}(hX9``irq_set_affinity`` Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask. h](j)}(h``irq_set_affinity``h]j)}(hjK6h]hirq_set_affinity}(hhhjM6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjE6ubj)}(hhh]jo)}(hX#Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask.h]hX#Set the CPU affinity on SMP machines. If the force argument is true, it tells the driver to unconditionally apply the affinity setting. Sanity checks against the supplied affinity mask are not required. This is used for CPU hotplug where the target CPU is not yet set in the cpu_online_mask.}(hjf6hjd6hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhja6ubah}(h]h ]h"]h$]h&]uh1jhjE6ubeh}(h]h ]h"]h$]h&]uh1jhj`6hMhj4ubj)}(h+``irq_retrigger`` resend an IRQ to the CPU h](j)}(h``irq_retrigger``h]j)}(hj6h]h irq_retrigger}(hhhj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj6ubj)}(hhh]jo)}(hresend an IRQ to the CPUh]hresend an IRQ to the CPU}(hj6hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj4ubj)}(hC``irq_set_type`` set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ h](j)}(h``irq_set_type``h]j)}(hj6h]h irq_set_type}(hhhj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj6ubj)}(hhh]jo)}(h1set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQh]h1set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ}(hj6hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj6hMhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj6hMhj4ubj)}(hC``irq_set_wake`` enable/disable power-management wake-on of an IRQ h](j)}(h``irq_set_wake``h]j)}(hj6h]h irq_set_wake}(hhhj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj6ubj)}(hhh]jo)}(h1enable/disable power-management wake-on of an IRQh]h1enable/disable power-management wake-on of an IRQ}(hj7hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj 7hMhj 7ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhj 7hMhj4ubj)}(hA``irq_bus_lock`` function to lock access to slow bus (i2c) chips h](j)}(h``irq_bus_lock``h]j)}(hj07h]h irq_bus_lock}(hhhj27hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj*7ubj)}(hhh]jo)}(h/function to lock access to slow bus (i2c) chipsh]h/function to lock access to slow bus (i2c) chips}(hjK7hjI7hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjE7hMhjF7ubah}(h]h ]h"]h$]h&]uh1jhj*7ubeh}(h]h ]h"]h$]h&]uh1jhjE7hMhj4ubj)}(hI``irq_bus_sync_unlock`` function to sync and unlock slow bus (i2c) chips h](j)}(h``irq_bus_sync_unlock``h]j)}(hji7h]hirq_bus_sync_unlock}(hhhjk7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjg7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjc7ubj)}(hhh]jo)}(h0function to sync and unlock slow bus (i2c) chipsh]h0function to sync and unlock slow bus (i2c) chips}(hj7hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj~7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhjc7ubeh}(h]h ]h"]h$]h&]uh1jhj~7hMhj4ubj)}(hE``irq_cpu_online`` configure an interrupt source for a secondary CPU h](j)}(h``irq_cpu_online``h]j)}(hj7h]hirq_cpu_online}(hhhj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj7ubj)}(hhh]jo)}(h1configure an interrupt source for a secondary CPUh]h1configure an interrupt source for a secondary CPU}(hj7hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj4ubj)}(hI``irq_cpu_offline`` un-configure an interrupt source for a secondary CPU h](j)}(h``irq_cpu_offline``h]j)}(hj7h]hirq_cpu_offline}(hhhj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj7ubj)}(hhh]jo)}(h4un-configure an interrupt source for a secondary CPUh]h4un-configure an interrupt source for a secondary CPU}(hj7hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj7hMhj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhj7hMhj4ubj)}(hs``irq_suspend`` function called from core code on suspend once per chip, when one or more interrupts are installed h](j)}(h``irq_suspend``h]j)}(hj8h]h irq_suspend}(hhhj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj8ubj)}(hhh]jo)}(hbfunction called from core code on suspend once per chip, when one or more interrupts are installedh]hbfunction called from core code on suspend once per chip, when one or more interrupts are installed}(hj/8hj-8hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj*8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj)8hMhj4ubj)}(hr``irq_resume`` function called from core code on resume once per chip, when one ore more interrupts are installed h](j)}(h``irq_resume``h]j)}(hjN8h]h irq_resume}(hhhjP8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjH8ubj)}(hhh]jo)}(hbfunction called from core code on resume once per chip, when one ore more interrupts are installedh]hbfunction called from core code on resume once per chip, when one ore more interrupts are installed}(hji8hjg8hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjd8ubah}(h]h ]h"]h$]h&]uh1jhjH8ubeh}(h]h ]h"]h$]h&]uh1jhjc8hMhj4ubj)}(hM``irq_pm_shutdown`` function called from core code on shutdown once per chip h](j)}(h``irq_pm_shutdown``h]j)}(hj8h]hirq_pm_shutdown}(hhhj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj8ubj)}(hhh]jo)}(h8function called from core code on shutdown once per chiph]h8function called from core code on shutdown once per chip}(hj8hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj4ubj)}(hK``irq_calc_mask`` Optional function to set irq_data.mask for special cases h](j)}(h``irq_calc_mask``h]j)}(hj8h]h irq_calc_mask}(hhhj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj8ubj)}(hhh]jo)}(h8Optional function to set irq_data.mask for special casesh]h8Optional function to set irq_data.mask for special cases}(hj8hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj8hMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj8hMhj4ubj)}(hJ``irq_print_chip`` optional to print special chip info in show_interrupts h](j)}(h``irq_print_chip``h]j)}(hj8h]hirq_print_chip}(hhhj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj8ubj)}(hhh]jo)}(h6optional to print special chip info in show_interruptsh]h6optional to print special chip info in show_interrupts}(hj9hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj4ubj)}(hn``irq_request_resources`` optional to request resources before calling any other callback related to this irq h](j)}(h``irq_request_resources``h]j)}(hj39h]hirq_request_resources}(hhhj59hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj19ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj-9ubj)}(hhh]jo)}(hSoptional to request resources before calling any other callback related to this irqh]hSoptional to request resources before calling any other callback related to this irq}(hjN9hjL9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjI9ubah}(h]h ]h"]h$]h&]uh1jhj-9ubeh}(h]h ]h"]h$]h&]uh1jhjH9hMhj4ubj)}(h\``irq_release_resources`` optional to release resources acquired with irq_request_resources h](j)}(h``irq_release_resources``h]j)}(hjm9h]hirq_release_resources}(hhhjo9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjk9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjg9ubj)}(hhh]jo)}(hAoptional to release resources acquired with irq_request_resourcesh]hAoptional to release resources acquired with irq_request_resources}(hj9hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj9ubah}(h]h ]h"]h$]h&]uh1jhjg9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj4ubj)}(hD``irq_compose_msi_msg`` optional to compose message content for MSI h](j)}(h``irq_compose_msi_msg``h]j)}(hj9h]hirq_compose_msi_msg}(hhhj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj9ubj)}(hhh]jo)}(h+optional to compose message content for MSIh]h+optional to compose message content for MSI}(hj9hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj4ubj)}(h@``irq_write_msi_msg`` optional to write message content for MSI h](j)}(h``irq_write_msi_msg``h]j)}(hj9h]hirq_write_msi_msg}(hhhj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj9ubj)}(hhh]jo)}(h)optional to write message content for MSIh]h)optional to write message content for MSI}(hj9hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj9hMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jhj9hMhj4ubj)}(hD``irq_get_irqchip_state`` return the internal state of an interrupt h](j)}(h``irq_get_irqchip_state``h]j)}(hj:h]hirq_get_irqchip_state}(hhhj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj:ubj)}(hhh]jo)}(h)return the internal state of an interrupth]h)return the internal state of an interrupt}(hj4:hj2:hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj.:hMhj/:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj.:hMhj4ubj)}(h@``irq_set_irqchip_state`` set the internal state of a interrupt h](j)}(h``irq_set_irqchip_state``h]j)}(hjR:h]hirq_set_irqchip_state}(hhhjT:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjP:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjL:ubj)}(hhh]jo)}(h%set the internal state of a interrupth]h%set the internal state of a interrupt}(hjm:hjk:hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjg:hMhjh:ubah}(h]h ]h"]h$]h&]uh1jhjL:ubeh}(h]h ]h"]h$]h&]uh1jhjg:hMhj4ubj)}(hI``irq_set_vcpu_affinity`` optional to target a vCPU in a virtual machine h](j)}(h``irq_set_vcpu_affinity``h]j)}(hj:h]hirq_set_vcpu_affinity}(hhhj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj:ubj)}(hhh]jo)}(h.optional to target a vCPU in a virtual machineh]h.optional to target a vCPU in a virtual machine}(hj:hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj4ubj)}(h:``ipi_send_single`` send a single IPI to destination cpus h](j)}(h``ipi_send_single``h]j)}(hj:h]hipi_send_single}(hhhj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj:ubj)}(hhh]jo)}(h%send a single IPI to destination cpush]h%send a single IPI to destination cpus}(hj:hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj:hMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj:hMhj4ubj)}(h=``ipi_send_mask`` send an IPI to destination cpus in cpumask h](j)}(h``ipi_send_mask``h]j)}(hj:h]h ipi_send_mask}(hhhj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj:ubj)}(hhh]jo)}(h*send an IPI to destination cpus in cpumaskh]h*send an IPI to destination cpus in cpumask}(hj;hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj4ubj)}(hH``irq_nmi_setup`` function called from core code before enabling an NMI h](j)}(h``irq_nmi_setup``h]j)}(hj6;h]h irq_nmi_setup}(hhhj8;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj0;ubj)}(hhh]jo)}(h5function called from core code before enabling an NMIh]h5function called from core code before enabling an NMI}(hjQ;hjO;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjK;hMhjL;ubah}(h]h ]h"]h$]h&]uh1jhj0;ubeh}(h]h ]h"]h$]h&]uh1jhjK;hMhj4ubj)}(hK``irq_nmi_teardown`` function called from core code after disabling an NMI h](j)}(h``irq_nmi_teardown``h]j)}(hjo;h]hirq_nmi_teardown}(hhhjq;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjm;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhji;ubj)}(hhh]jo)}(h5function called from core code after disabling an NMIh]h5function called from core code after disabling an NMI}(hj;hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj;hMhj;ubah}(h]h ]h"]h$]h&]uh1jhji;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj4ubj)}(h``flags`` chip specific flagsh](j)}(h ``flags``h]j)}(hj;h]hflags}(hhhj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj;ubj)}(hhh]jo)}(hchip specific flagsh]hchip specific flags}(hj;hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jhj;hMhj4ubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_regs (C struct)c.irq_chip_regshNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(h irq_chip_regsh]j])}(hstruct irq_chip_regsh](j)}(hjh]hstruct}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMubju)}(h h]h }(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj;hhhj<hMubj)}(h irq_chip_regsh]j)}(hj;h]h irq_chip_regs}(hhhj"<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj;hhhj<hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj;hhhj<hMubah}(h]j;ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj;hhubjH)}(hhh]jo)}(h#register offsets for struct irq_gcih]h#register offsets for struct irq_gci}(hjG<hjE<hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjB<hhubah}(h]h ]h"]h$]h&]uh1jGhj;hhhj<hMubeh}(h]h ](jY structeh"]h$]h&]jhjY jij]<jjj]<jkuh1jQhhhj.hNhNubjm)}(hX**Definition**:: struct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; unsigned long polarity; }; **Members** ``enable`` Enable register offset to reg_base ``disable`` Disable register offset to reg_base ``mask`` Mask register offset to reg_base ``ack`` Ack register offset to reg_base ``eoi`` Eoi register offset to reg_base ``type`` Type configuration register offset to reg_base ``polarity`` Polarity configuration register offset to reg_baseh](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhji<hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhje<ubh:}(hj.hje<hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhja<ubj )}(hXstruct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; unsigned long polarity; };h]hXstruct irq_chip_regs { unsigned long enable; unsigned long disable; unsigned long mask; unsigned long ack; unsigned long eoi; unsigned long type; unsigned long polarity; };}(hhhj<ubah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhja<ubjo)}(h **Members**h]jw)}(hj<h]hMembers}(hhhj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj<ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhja<ubj)}(hhh](j)}(h.``enable`` Enable register offset to reg_base h](j)}(h ``enable``h]j)}(hj<h]henable}(hhhj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj<ubj)}(hhh]jo)}(h"Enable register offset to reg_baseh]h"Enable register offset to reg_base}(hj<hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj<hMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj<hMhj<ubj)}(h0``disable`` Disable register offset to reg_base h](j)}(h ``disable``h]j)}(hj<h]hdisable}(hhhj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj<ubj)}(hhh]jo)}(h#Disable register offset to reg_baseh]h#Disable register offset to reg_base}(hj=hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<ubj)}(h*``mask`` Mask register offset to reg_base h](j)}(h``mask``h]j)}(hj$=h]hmask}(hhhj&=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj=ubj)}(hhh]jo)}(h Mask register offset to reg_baseh]h Mask register offset to reg_base}(hj?=hj==hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj9=hMhj:=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj9=hMhj<ubj)}(h(``ack`` Ack register offset to reg_base h](j)}(h``ack``h]j)}(hj]=h]hack}(hhhj_=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjW=ubj)}(hhh]jo)}(hAck register offset to reg_baseh]hAck register offset to reg_base}(hjx=hjv=hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjr=hMhjs=ubah}(h]h ]h"]h$]h&]uh1jhjW=ubeh}(h]h ]h"]h$]h&]uh1jhjr=hMhj<ubj)}(h(``eoi`` Eoi register offset to reg_base h](j)}(h``eoi``h]j)}(hj=h]heoi}(hhhj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj=ubj)}(hhh]jo)}(hEoi register offset to reg_baseh]hEoi register offset to reg_base}(hj=hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<ubj)}(h8``type`` Type configuration register offset to reg_base h](j)}(h``type``h]j)}(hj=h]htype}(hhhj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj=ubj)}(hhh]jo)}(h.Type configuration register offset to reg_baseh]h.Type configuration register offset to reg_base}(hj=hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj=hMhj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhj<ubj)}(h?``polarity`` Polarity configuration register offset to reg_baseh](j)}(h ``polarity``h]j)}(hj>h]hpolarity}(hhhj >hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>ubj)}(hhh]jo)}(h2Polarity configuration register offset to reg_baseh]h2Polarity configuration register offset to reg_base}(hj#>hj!>hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1jhj>hMhj<ubeh}(h]h ]h"]h$]h&]uh1jhja<ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_type (C struct)c.irq_chip_typehNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(h irq_chip_typeh]j])}(hstruct irq_chip_typeh](j)}(hjh]hstruct}(hhhjb>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj^>hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMubju)}(h h]h }(hhhjp>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj^>hhhjo>hMubj)}(h irq_chip_typeh]j)}(hj\>h]h irq_chip_type}(hhhj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~>ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj^>hhhjo>hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjZ>hhhjo>hMubah}(h]jU>ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjW>hhubjH)}(hhh]jo)}(h/Generic interrupt chip instance for a flow typeh]h/Generic interrupt chip instance for a flow type}(hj>hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>hhubah}(h]h ]h"]h$]h&]uh1jGhjW>hhhjo>hMubeh}(h]h ](jY structeh"]h$]h&]jhjY jij>jjj>jkuh1jQhhhj.hNhNubjm)}(hX.**Definition**:: struct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; }; **Members** ``chip`` The real interrupt chip which provides the callbacks ``regs`` Register offsets for this chip ``handler`` Flow handler associated with this chip ``type`` Chip can handle these flow types ``mask_cache_priv`` Cached mask register private to the chip type ``mask_cache`` Pointer to cached mask registerh](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj>ubh:}(hj.hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>ubj )}(hstruct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; };h]hstruct irq_chip_type { struct irq_chip chip; struct irq_chip_regs regs; irq_flow_handler_t handler; u32 type; u32 mask_cache_priv; u32 *mask_cache; };}(hhhj>ubah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>ubjo)}(h **Members**h]jw)}(hj>h]hMembers}(hhhj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj>ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj>ubj)}(hhh](j)}(h>``chip`` The real interrupt chip which provides the callbacks h](j)}(h``chip``h]j)}(hj?h]hchip}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj ?ubj)}(hhh]jo)}(h4The real interrupt chip which provides the callbacksh]h4The real interrupt chip which provides the callbacks}(hj-?hj+?hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj'?hMhj(?ubah}(h]h ]h"]h$]h&]uh1jhj ?ubeh}(h]h ]h"]h$]h&]uh1jhj'?hMhj ?ubj)}(h(``regs`` Register offsets for this chip h](j)}(h``regs``h]j)}(hjK?h]hregs}(hhhjM?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjE?ubj)}(hhh]jo)}(hRegister offsets for this chiph]hRegister offsets for this chip}(hjf?hjd?hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj`?hMhja?ubah}(h]h ]h"]h$]h&]uh1jhjE?ubeh}(h]h ]h"]h$]h&]uh1jhj`?hMhj ?ubj)}(h3``handler`` Flow handler associated with this chip h](j)}(h ``handler``h]j)}(hj?h]hhandler}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj~?ubj)}(hhh]jo)}(h&Flow handler associated with this chiph]h&Flow handler associated with this chip}(hj?hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj~?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj ?ubj)}(h*``type`` Chip can handle these flow types h](j)}(h``type``h]j)}(hj?h]htype}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj?ubj)}(hhh]jo)}(h Chip can handle these flow typesh]h Chip can handle these flow types}(hj?hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj?hMhj?ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhj ?ubj)}(hB``mask_cache_priv`` Cached mask register private to the chip type h](j)}(h``mask_cache_priv``h]j)}(hj?h]hmask_cache_priv}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj?ubj)}(hhh]jo)}(h-Cached mask register private to the chip typeh]h-Cached mask register private to the chip type}(hj@hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj @hMhj @ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhj @hMhj ?ubj)}(h.``mask_cache`` Pointer to cached mask registerh](j)}(h``mask_cache``h]j)}(hj/@h]h mask_cache}(hhhj1@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj)@ubj)}(hhh]jo)}(hPointer to cached mask registerh]hPointer to cached mask register}(hjJ@hjH@hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjE@ubah}(h]h ]h"]h$]h&]uh1jhj)@ubeh}(h]h ]h"]h$]h&]uh1jhjD@hMhj ?ubeh}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjo)}(h**Description**h]jw)}(hjr@h]h Description}(hhhjt@hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjp@ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj.hhubjo)}(hA irq_generic_chip can have several instances of irq_chip_type when it requires different functions and register offsets for different flow types.h]hA irq_generic_chip can have several instances of irq_chip_type when it requires different functions and register offsets for different flow types.}(hj@hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj.hhubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_chip_generic (C struct)c.irq_chip_generichNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(hirq_chip_generich]j])}(hstruct irq_chip_generich](j)}(hjh]hstruct}(hhhj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMubju)}(h h]h }(hhhj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@hhhj@hMubj)}(hirq_chip_generich]j)}(hj@h]hirq_chip_generic}(hhhj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj@hhhj@hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj@hhhj@hMubah}(h]j@ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj@hhubjH)}(hhh]jo)}(hGeneric irq chip data structureh]hGeneric irq chip data structure}(hj@hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj@hhubah}(h]h ]h"]h$]h&]uh1jGhj@hhhj@hMubeh}(h]h ](jY structeh"]h$]h&]jhjY jij Ajjj Ajkuh1jQhhhj.hNhNubjm)}(hX`**Definition**:: struct irq_chip_generic { raw_spinlock_t lock; void __iomem *reg_base; u32 (*reg_readl)(void __iomem *addr); void (*reg_writel)(u32 val, void __iomem *addr); void (*suspend)(struct irq_chip_generic *gc); void (*resume)(struct irq_chip_generic *gc); unsigned int irq_base; unsigned int irq_cnt; u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; u32 wake_active; unsigned int num_ct; void *private; unsigned long installed; unsigned long unused; struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[]; }; **Members** ``lock`` Lock to protect register and cache data access ``reg_base`` Register base address (virtual) ``reg_readl`` Alternate I/O accessor (defaults to readl if NULL) ``reg_writel`` Alternate I/O accessor (defaults to writel if NULL) ``suspend`` Function called from core code on suspend once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use ``resume`` Function called from core code on resume once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use ``irq_base`` Interrupt base nr for this chip ``irq_cnt`` Number of interrupts handled by this chip ``mask_cache`` Cached mask register shared between all chip types ``type_cache`` Cached type register ``polarity_cache`` Cached polarity register ``wake_enabled`` Interrupt can wakeup from suspend ``wake_active`` Interrupt is marked as an wakeup from suspend source ``num_ct`` Number of available irq_chip_type instances (usually 1) ``private`` Private data for non generic chip callbacks ``installed`` bitfield to denote installed interrupts ``unused`` bitfield to denote unused interrupts ``domain`` irq domain pointer ``list`` List head for keeping track of instances ``chip_types`` Array of interrupt irq_chip_typesh](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjAubh:}(hj.hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hjAubj )}(hXstruct irq_chip_generic { raw_spinlock_t lock; void __iomem *reg_base; u32 (*reg_readl)(void __iomem *addr); void (*reg_writel)(u32 val, void __iomem *addr); void (*suspend)(struct irq_chip_generic *gc); void (*resume)(struct irq_chip_generic *gc); unsigned int irq_base; unsigned int irq_cnt; u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; u32 wake_active; unsigned int num_ct; void *private; unsigned long installed; unsigned long unused; struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[]; };h]hXstruct irq_chip_generic { raw_spinlock_t lock; void __iomem *reg_base; u32 (*reg_readl)(void __iomem *addr); void (*reg_writel)(u32 val, void __iomem *addr); void (*suspend)(struct irq_chip_generic *gc); void (*resume)(struct irq_chip_generic *gc); unsigned int irq_base; unsigned int irq_cnt; u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; u32 wake_active; unsigned int num_ct; void *private; unsigned long installed; unsigned long unused; struct irq_domain *domain; struct list_head list; struct irq_chip_type chip_types[]; };}(hhhj0Aubah}(h]h ]h"]h$]h&]hhuh1j hX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hjAubjo)}(h **Members**h]jw)}(hjAAh]hMembers}(hhhjCAhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj?Aubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM"hjAubj)}(hhh](j)}(h8``lock`` Lock to protect register and cache data access h](j)}(h``lock``h]j)}(hj`Ah]hlock}(hhhjbAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Aubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjZAubj)}(hhh]jo)}(h.Lock to protect register and cache data accessh]h.Lock to protect register and cache data access}(hj{AhjyAhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjuAhMhjvAubah}(h]h ]h"]h$]h&]uh1jhjZAubeh}(h]h ]h"]h$]h&]uh1jhjuAhMhjWAubj)}(h-``reg_base`` Register base address (virtual) h](j)}(h ``reg_base``h]j)}(hjAh]hreg_base}(hhhjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjAubj)}(hhh]jo)}(hRegister base address (virtual)h]hRegister base address (virtual)}(hjAhjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjAhMhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjAhMhjWAubj)}(hA``reg_readl`` Alternate I/O accessor (defaults to readl if NULL) h](j)}(h ``reg_readl``h]j)}(hjAh]h reg_readl}(hhhjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hjAubj)}(hhh]jo)}(h2Alternate I/O accessor (defaults to readl if NULL)h]h2Alternate I/O accessor (defaults to readl if NULL)}(hjAhjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjAhM hjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhjAhM hjWAubj)}(hC``reg_writel`` Alternate I/O accessor (defaults to writel if NULL) h](j)}(h``reg_writel``h]j)}(hj Bh]h reg_writel}(hhhj BhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Bubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hjBubj)}(hhh]jo)}(h3Alternate I/O accessor (defaults to writel if NULL)h]h3Alternate I/O accessor (defaults to writel if NULL)}(hj&Bhj$BhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj BhM hj!Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhj BhM hjWAubj)}(h``suspend`` Function called from core code on suspend once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use h](j)}(h ``suspend``h]j)}(hjDBh]hsuspend}(hhhjFBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hj>Bubj)}(hhh]jo)}(hFunction called from core code on suspend once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in useh]hFunction called from core code on suspend once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use}(hj_Bhj]BhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM hjZBubah}(h]h ]h"]h$]h&]uh1jhj>Bubeh}(h]h ]h"]h$]h&]uh1jhjYBhM hjWAubj)}(h``resume`` Function called from core code on resume once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use h](j)}(h ``resume``h]j)}(hj~Bh]hresume}(hhhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|Bubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjxBubj)}(hhh]jo)}(hFunction called from core code on resume once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in useh]hFunction called from core code on resume once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use}(hjBhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjBubah}(h]h ]h"]h$]h&]uh1jhjxBubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjWAubj)}(h-``irq_base`` Interrupt base nr for this chip h](j)}(h ``irq_base``h]j)}(hjBh]hirq_base}(hhhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjBubj)}(hhh]jo)}(hInterrupt base nr for this chiph]hInterrupt base nr for this chip}(hjBhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjBhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjBhMhjWAubj)}(h6``irq_cnt`` Number of interrupts handled by this chip h](j)}(h ``irq_cnt``h]j)}(hjBh]hirq_cnt}(hhhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjBubj)}(hhh]jo)}(h)Number of interrupts handled by this chiph]h)Number of interrupts handled by this chip}(hj Chj ChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjChMhjWAubj)}(hB``mask_cache`` Cached mask register shared between all chip types h](j)}(h``mask_cache``h]j)}(hj*Ch]h mask_cache}(hhhj,ChhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(Cubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj$Cubj)}(hhh]jo)}(h2Cached mask register shared between all chip typesh]h2Cached mask register shared between all chip types}(hjEChjCChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj?ChMhj@Cubah}(h]h ]h"]h$]h&]uh1jhj$Cubeh}(h]h ]h"]h$]h&]uh1jhj?ChMhjWAubj)}(h$``type_cache`` Cached type register h](j)}(h``type_cache``h]j)}(hjcCh]h type_cache}(hhhjeChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaCubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj]Cubj)}(hhh]jo)}(hCached type registerh]hCached type register}(hj~Chj|ChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjxChMhjyCubah}(h]h ]h"]h$]h&]uh1jhj]Cubeh}(h]h ]h"]h$]h&]uh1jhjxChMhjWAubj)}(h,``polarity_cache`` Cached polarity register h](j)}(h``polarity_cache``h]j)}(hjCh]hpolarity_cache}(hhhjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjCubj)}(hhh]jo)}(hCached polarity registerh]hCached polarity register}(hjChjChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhjChMhjWAubj)}(h3``wake_enabled`` Interrupt can wakeup from suspend h](j)}(h``wake_enabled``h]j)}(hjCh]h wake_enabled}(hhhjChhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjCubj)}(hhh]jo)}(h!Interrupt can wakeup from suspendh]h!Interrupt can wakeup from suspend}(hjChjChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjChMhjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhjChMhjWAubj)}(hE``wake_active`` Interrupt is marked as an wakeup from suspend source h](j)}(h``wake_active``h]j)}(hjDh]h wake_active}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Dubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjDubj)}(hhh]jo)}(h4Interrupt is marked as an wakeup from suspend sourceh]h4Interrupt is marked as an wakeup from suspend source}(hj)Dhj'DhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj#DhMhj$Dubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhj#DhMhjWAubj)}(hC``num_ct`` Number of available irq_chip_type instances (usually 1) h](j)}(h ``num_ct``h]j)}(hjGDh]hnum_ct}(hhhjIDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEDubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjADubj)}(hhh]jo)}(h7Number of available irq_chip_type instances (usually 1)h]h7Number of available irq_chip_type instances (usually 1)}(hjbDhj`DhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj\DhMhj]Dubah}(h]h ]h"]h$]h&]uh1jhjADubeh}(h]h ]h"]h$]h&]uh1jhj\DhMhjWAubj)}(h8``private`` Private data for non generic chip callbacks h](j)}(h ``private``h]j)}(hjDh]hprivate}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~Dubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjzDubj)}(hhh]jo)}(h+Private data for non generic chip callbacksh]h+Private data for non generic chip callbacks}(hjDhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjzDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjWAubj)}(h6``installed`` bitfield to denote installed interrupts h](j)}(h ``installed``h]j)}(hjDh]h installed}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjDubj)}(hhh]jo)}(h'bitfield to denote installed interruptsh]h'bitfield to denote installed interrupts}(hjDhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjDhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjDhMhjWAubj)}(h0``unused`` bitfield to denote unused interrupts h](j)}(h ``unused``h]j)}(hjDh]hunused}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjDubj)}(hhh]jo)}(h$bitfield to denote unused interruptsh]h$bitfield to denote unused interrupts}(hj Ehj EhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjEhMhjEubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjWAubj)}(h``domain`` irq domain pointer h](j)}(h ``domain``h]j)}(hj+Eh]hdomain}(hhhj-EhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj)Eubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj%Eubj)}(hhh]jo)}(hirq domain pointerh]hirq domain pointer}(hjFEhjDEhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj@EhMhjAEubah}(h]h ]h"]h$]h&]uh1jhj%Eubeh}(h]h ]h"]h$]h&]uh1jhj@EhMhjWAubj)}(h2``list`` List head for keeping track of instances h](j)}(h``list``h]j)}(hjdEh]hlist}(hhhjfEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbEubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhj^Eubj)}(hhh]jo)}(h(List head for keeping track of instancesh]h(List head for keeping track of instances}(hjEhj}EhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjyEhMhjzEubah}(h]h ]h"]h$]h&]uh1jhj^Eubeh}(h]h ]h"]h$]h&]uh1jhjyEhMhjWAubj)}(h0``chip_types`` Array of interrupt irq_chip_typesh](j)}(h``chip_types``h]j)}(hjEh]h chip_types}(hhhjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjEubj)}(hhh]jo)}(h!Array of interrupt irq_chip_typesh]h!Array of interrupt irq_chip_types}(hjEhjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jhjEhMhjWAubeh}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjo)}(h**Description**h]jw)}(hjEh]h Description}(hhhjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjEubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhM!hj.hhubjo)}(hX-Note, that irq_chip_generic can have multiple irq_chip_type implementations which can be associated to a particular irq line of an irq_chip_generic instance. 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Usually GPIO implementations h](j)}(h``IRQ_GC_INIT_NESTED_LOCK``h]j)}(hjFh]hIRQ_GC_INIT_NESTED_LOCK}(hhhjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:491: ./include/linux/irq.hhMIhjFubj)}(hhh]jo)}(hSet the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. Usually GPIO implementationsh]hSet the lock class of the irqs to nested for irq chips which need to call irq_set_wake() on the parent irq. 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irqactionh]j])}(hstruct irqactionh](j)}(hjh]hstruct}(hhhjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGhhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKkubju)}(h h]h }(hhhjGhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjGhhhjGhKkubj)}(h irqactionh]j)}(hjGh]h irqaction}(hhhjHhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjGubah}(h]h ](jjeh"]h$]h&]hhuh1jhjGhhhjGhKkubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjGhhhjGhKkubah}(h]jGah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKhjGhhubjH)}(hhh]jo)}(hper interrupt action descriptorh]hper interrupt action descriptor}(hj&Hhj$HhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKjhj!Hhhubah}(h]h ]h"]h$]h&]uh1jGhjGhhhjGhKkubeh}(h]h ](jY structeh"]h$]h&]jhjY jijIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:Iubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKphj6Iubj)}(hhh]jo)}(h3pointer to the next irqaction for shared interruptsh]h3pointer to the next irqaction for shared interrupts}(hjWIhjUIhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjQIhKphjRIubah}(h]h ]h"]h$]h&]uh1jhj6Iubeh}(h]h ]h"]h$]h&]uh1jhjQIhKphjHubj)}(hA``thread_fn`` interrupt handler function for threaded interrupts h](j)}(h ``thread_fn``h]j)}(hjuIh]h thread_fn}(hhhjwIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsIubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKshjoIubj)}(hhh]jo)}(h2interrupt handler function for threaded interruptsh]h2interrupt handler function for threaded interrupts}(hjIhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjIhKshjIubah}(h]h ]h"]h$]h&]uh1jhjoIubeh}(h]h ]h"]h$]h&]uh1jhjIhKshjHubj)}(h2``thread`` thread pointer for threaded interrupts h](j)}(h ``thread``h]j)}(hjIh]hthread}(hhhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKthjIubj)}(hhh]jo)}(h&thread pointer for threaded interruptsh]h&thread pointer for threaded interrupts}(hjIhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjIhKthjIubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjIhKthjHubj)}(h?``secondary`` pointer to secondary irqaction (force threading) h](j)}(h ``secondary``h]j)}(hjIh]h secondary}(hhhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKuhjIubj)}(hhh]jo)}(h0pointer to secondary irqaction (force threading)h]h0pointer to secondary irqaction (force threading)}(hjJhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjIhKuhjIubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jhjIhKuhjHubj)}(h``irq`` interrupt number h](j)}(h``irq``h]j)}(hj Jh]hirq}(hhhj"JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKqhjJubj)}(hhh]jo)}(hinterrupt numberh]hinterrupt number}(hj;Jhj9JhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj5JhKqhj6Jubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhj5JhKqhjHubj)}(h#``flags`` flags (see IRQF_* above) h](j)}(h ``flags``h]j)}(hjYJh]hflags}(hhhj[JhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKrhjSJubj)}(hhh]jo)}(hflags (see IRQF_* above)h]hflags (see IRQF_* above)}(hjtJhjrJhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjnJhKrhjoJubah}(h]h ]h"]h$]h&]uh1jhjSJubeh}(h]h ]h"]h$]h&]uh1jhjnJhKrhjHubj)}(h-``thread_flags`` flags related to **thread** h](j)}(h``thread_flags``h]j)}(hjJh]h thread_flags}(hhhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKvhjJubj)}(hhh]jo)}(hflags related to **thread**h](hflags related to }(hflags related to hjJhhhNhNubjw)}(h **thread**h]hthread}(hhhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjJubeh}(h]h ]h"]h$]h&]uh1jnhjJhKvhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhKvhjHubj)}(hA``thread_mask`` bitmask for keeping track of **thread** activity h](j)}(h``thread_mask``h]j)}(hjJh]h thread_mask}(hhhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjJubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKwhjJubj)}(hhh]jo)}(h0bitmask for keeping track of **thread** activityh](hbitmask for keeping track of }(hbitmask for keeping track of hjJhhhNhNubjw)}(h **thread**h]hthread}(hhhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjJubh activity}(h activityhjJhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhjJhKwhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjJhKwhjHubj)}(h``name`` name of the device h](j)}(h``name``h]j)}(hj'Kh]hname}(hhhj)KhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%Kubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhKmhj!Kubj)}(hhh]jo)}(hname of the deviceh]hname of the device}(hjBKhj@KhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjPhjCallback for calculating the number and size of interrupt setsh]h>Callback for calculating the number and size of interrupt sets}(hjShjShhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjRhMhjQubj)}(hc``priv`` Private data for usage by **calc_sets**, usually a pointer to driver/device specific data.h](j)}(h``priv``h]j)}(hj"Sh]hpriv}(hhhj$ShhhNhNubah}(h]h ]h"]h$]h&]uh1jhj Subah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMhjSubj)}(hhh]jo)}(hZPrivate data for usage by **calc_sets**, usually a pointer to driver/device specific data.h](hPrivate data for usage by }(hPrivate data for usage by hj;ShhhNhNubjw)}(h **calc_sets**h]h calc_sets}(hhhjDShhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj;Subh3, usually a pointer to driver/device specific data.}(h3, usually a pointer to driver/device specific data.hj;ShhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhj7ShMhj8Subah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jhj7ShMhjQubeh}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj.hhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_affinity_desc (C struct)c.irq_affinity_deschNtauh1j@hj.hhhNhNubjR)}(hhh](jW)}(hirq_affinity_desch]j])}(hstruct irq_affinity_desch](j)}(hjh]hstruct}(hhhjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjShhh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhM+ubju)}(h h]h }(hhhjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjShhhjShM+ubj)}(hirq_affinity_desch]j)}(hjSh]hirq_affinity_desc}(hhhjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjSubah}(h]h ](jjeh"]h$]h&]hhuh1jhjShhhjShM+ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjShhhjShM+ubah}(h]jSah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhM%hjShhubjH)}(hhh]jo)}(hInterrupt affinity descriptorh]hInterrupt affinity descriptor}(hjShjShhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhM*hjShhubah}(h]h ]h"]h$]h&]uh1jGhjShhhjShM+ubeh}(h]h ](jY structeh"]h$]h&]jhjY jijSjjjSjkuh1jQhhhj.hNhNubjm)}(h**Definition**:: struct irq_affinity_desc { struct cpumask mask; unsigned int is_managed : 1; }; **Members** ``mask`` cpumask to hold the affinity assignment ``is_managed`` 1 if the interrupt is managed internallyh](jo)}(h**Definition**::h](jw)}(h**Definition**h]h Definition}(hhhjShhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjSubh:}(hj.hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhM.hjSubj )}(h[struct irq_affinity_desc { struct cpumask mask; unsigned int is_managed : 1; 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h]h }(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\Uubh)}(hhh]j)}(hcpumaskh]hcpumask}(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjUmodnameN classnameNjj)}j]j)}jjTsbc.irq_update_affinity_hintasbuh1hhj\Uubju)}(h h]h }(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\Uubj )}(hj h]h*}(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\Uubj)}(hmh]hm}(hhhjUhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\Uubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubeh}(h]h ]h"]h$]h&]hhuh1jhjThhhjThMBubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjThhhjThMBubah}(h]jTah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMGhjThhubjH)}(hhh]jo)}(hUpdate the affinity hinth]hUpdate the affinity hint}(hjVhjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMAhjUhhubah}(h]h ]h"]h$]h&]uh1jGhjThhhjThMBubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijVjjjVjkuh1jQhhhj.hNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt to update ``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) **Description** Updates the affinity hint, but does not change the affinity of the interrupt.h](jo)}(h**Parameters**h]jw)}(hj!Vh]h Parameters}(hhhj#VhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjVubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMEhjVubj)}(hhh](j)}(h)``unsigned int irq`` Interrupt to update h](j)}(h``unsigned int irq``h]j)}(hj@Vh]hunsigned int irq}(hhhjBVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>Vubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMBhj:Vubj)}(hhh]jo)}(hInterrupt to updateh]hInterrupt to update}(hj[VhjYVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjUVhMBhjVVubah}(h]h ]h"]h$]h&]uh1jhj:Vubeh}(h]h ]h"]h$]h&]uh1jhjUVhMBhj7Vubj)}(hE``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) h](j)}(h``const struct cpumask *m``h]j)}(hjyVh]hconst struct cpumask *m}(hhhj{VhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwVubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMChjsVubj)}(hhh]jo)}(h(cpumask pointer (NULL to clear the hint)h]h(cpumask pointer (NULL to clear the hint)}(hjVhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjVhMChjVubah}(h]h ]h"]h$]h&]uh1jhjsVubeh}(h]h ]h"]h$]h&]uh1jhjVhMChj7Vubeh}(h]h ]h"]h$]h&]uh1jhjVubjo)}(h**Description**h]jw)}(hjVh]h Description}(hhhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjVubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMEhjVubjo)}(hMUpdates the affinity hint, but does not change the affinity of the interrupt.h]hMUpdates the affinity hint, but does not change the affinity of the interrupt.}(hjVhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: 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]jah"]h$]h&]uh1jthj2Wubjc)}(hinth]hint}(hhhjRWhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj2Wubju)}(h h]h }(hhhj`WhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj2Wubj)}(hirqh]hirq}(hhhjnWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2Wubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj.Wubj)}(hconst struct cpumask *mh](j)}(hjh]hconst}(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubju)}(h h]h }(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubj)}(hjh]hstruct}(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubju)}(h h]h }(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubh)}(hhh]j)}(hcpumaskh]hcpumask}(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjWmodnameN classnameNjj)}j]j)}jjWsbc.irq_set_affinity_and_hintasbuh1hhjWubju)}(h h]h }(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubj )}(hj h]h*}(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubj)}(hjUh]hm}(hhhjWhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj.Wubeh}(h]h ]h"]h$]h&]hhuh1jhjVhhhjWhMOubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjVhhhjWhMOubah}(h]jVah ](j@jAeh"]h$]h&]jEuh1jVh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMVhjVhhubjH)}(hhh]jo)}(hHUpdate the affinity hint and apply the provided cpumask to the interrupth]hHUpdate the affinity hint and apply the provided cpumask to the interrupt}(hj'Xhj%XhhhNhNubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMNhj"Xhhubah}(h]h ]h"]h$]h&]uh1jGhjVhhhjWhMOubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij=Xjjj=Xjkuh1jQhhhj.hNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt to update ``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) **Description** Updates the affinity hint and if **m** is not NULL it applies it as the affinity of that interrupt.h](jo)}(h**Parameters**h]jw)}(hjGXh]h Parameters}(hhhjIXhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjEXubah}(h]h ]h"]h$]h&]uh1jnh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMRhjAXubj)}(hhh](j)}(h)``unsigned int irq`` Interrupt to update h](j)}(h``unsigned int irq``h]j)}(hjfXh]hunsigned int irq}(hhhjhXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdXubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMPhj`Xubj)}(hhh]jo)}(hInterrupt to updateh]hInterrupt to update}(hjXhjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj{XhMPhj|Xubah}(h]h ]h"]h$]h&]uh1jhj`Xubeh}(h]h ]h"]h$]h&]uh1jhj{XhMPhj]Xubj)}(hE``const struct cpumask *m`` cpumask pointer (NULL to clear the hint) h](j)}(h``const struct cpumask *m``h]j)}(hjXh]hconst struct cpumask *m}(hhhjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubah}(h]h ]h"]h$]h&]uh1jh^/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:494: ./include/linux/interrupt.hhMQhjXubj)}(hhh]jo)}(h(cpumask pointer (NULL to clear the hint)h]h(cpumask pointer (NULL to clear the hint)}(hjXhjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjXhMQhjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h 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If you use this function while holding a resource the IRQ handler may need you will deadlock. It does not take associated threaded handlers into account. Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed. h](j)}(h``unsigned int irq``h]j)}(hj;Zh]hunsigned int irq}(hhhj=ZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj9Zubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKWhj5Zubj)}(hhh](jo)}(hinterrupt number to wait forh]hinterrupt number to wait for}(hjVZhjTZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKNhjQZubjo)}(hXThis function waits for any pending hard IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. 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It does not take associated threaded handlers into account.}(hjeZhjcZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKPhjQZubjo)}(h{Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed.h]h{Do not use this for shutdown scenarios where you must be sure that all parts (hardirq and threaded handler) have completed.}(hjtZhjrZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKVhjQZubeh}(h]h ]h"]h$]h&]uh1jhj5Zubeh}(h]h ]h"]h$]h&]uh1jhjPZhKWhj2Zubah}(h]h ]h"]h$]h&]uh1jhjZubjo)}(h **Return**h]jw)}(hjZh]hReturn}(hhhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjZubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKYhjZubjo)}(h&false if a threaded handler is active.h]h&false if a threaded handler is active.}(hjZhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKYhjZubh block_quote)}(hhh](jo)}(h;This function may be called - with care - from IRQ context.h]h;This function may be called - with care - from IRQ context.}(hjZhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK[hjZubjo)}(hIt does not check whether there is an interrupt in flight at the hardware level, but not serviced yet, as this might deadlock when called with interrupts disabled and the target CPU of the interrupt is the current CPU.h]hIt does not check whether there is an interrupt in flight at the hardware level, but not serviced yet, as this might deadlock when called with interrupts disabled and the target CPU of the interrupt is the current CPU.}(hjZhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK]hjZubeh}(h]h ]h"]h$]h&]uh1jZhjZubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMsynchronize_irq (C function)c.synchronize_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h'void synchronize_irq (unsigned int irq)h]j])}(h&void synchronize_irq(unsigned int irq)h](jc)}(hvoidh]hvoid}(hhhj[hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjZhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK{ubju)}(h h]h }(hhhj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZhhhj[hK{ubj)}(hsynchronize_irqh]j)}(hsynchronize_irqh]hsynchronize_irq}(hhhj$[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj [ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjZhhhj[hK{ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj@[hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj<[ubju)}(h h]h }(hhhjN[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<[ubjc)}(hinth]hint}(hhhj\[hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj<[ubju)}(h h]h }(hhhjj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<[ubj)}(hirqh]hirq}(hhhjx[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj8[ubah}(h]h ]h"]h$]h&]hhuh1jhjZhhhj[hK{ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjZhhhj[hK{ubah}(h]jZah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjZhhubjH)}(hhh]jo)}(h-wait for pending IRQ handlers (on other CPUs)h]h-wait for pending IRQ handlers (on other CPUs)}(hj[hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKzhj[hhubah}(h]h ]h"]h$]h&]uh1jGhjZhhhj[hK{ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij[jjj[jkuh1jQhhhj"YhNhNubjm)}(hX **Parameters** ``unsigned int irq`` interrupt number to wait for This function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. Can only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**. It optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.h](jo)}(h**Parameters**h]jw)}(hj[h]h Parameters}(hhhj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj[ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK~hj[ubj)}(hhh]j)}(hX``unsigned int irq`` interrupt number to wait for This function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. Can only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**. It optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.h](j)}(h``unsigned int irq``h]j)}(hj[h]hunsigned int irq}(hhhj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj[ubj)}(hhh](jo)}(hinterrupt number to wait forh]hinterrupt number to wait for}(hj[hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK{hj[ubjo)}(hThis function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock.h]hThis function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock.}(hj\hj \hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chK}hj[ubjo)}(hmCan only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**.h](heCan only be called from preemptible code as it might sleep when an interrupt thread is associated to }(heCan only be called from preemptible code as it might sleep when an interrupt thread is associated to hj\hhhNhNubjw)}(h**irq**h]hirq}(hhhj$\hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj\ubh.}(hj5hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj[ubjo)}(hIt optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.h]hIt optionally makes sure (when the irq chip supports that method) that the interrupt is not pending in any CPU and waiting for service.}(hj?\hj=\hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj[ubeh}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhj[hKhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_can_set_affinity (C function)c.irq_can_set_affinityhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h+int irq_can_set_affinity (unsigned int irq)h]j])}(h*int irq_can_set_affinity(unsigned int irq)h](jc)}(hinth]hint}(hhhj~\hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjz\hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKubju)}(h h]h }(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjz\hhhj\hKubj)}(hirq_can_set_affinityh]j)}(hirq_can_set_affinityh]hirq_can_set_affinity}(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjz\hhhj\hKubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj\hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubjc)}(hinth]hint}(hhhj\hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubj)}(hirqh]hirq}(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj\ubah}(h]h ]h"]h$]h&]hhuh1jhjz\hhhj\hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjv\hhhj\hKubah}(h]jq\ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjs\hhubjH)}(hhh]jo)}(h/Check if the affinity of a given irq can be seth]h/Check if the affinity of a given irq can be set}(hj ]hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj]hhubah}(h]h ]h"]h$]h&]uh1jGhjs\hhhj\hKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij6]jjj6]jkuh1jQhhhj"YhNhNubjm)}(h9**Parameters** ``unsigned int irq`` Interrupt to checkh](jo)}(h**Parameters**h]jw)}(hj@]h]h Parameters}(hhhjB]hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj>]ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj:]ubj)}(hhh]j)}(h'``unsigned int irq`` Interrupt to checkh](j)}(h``unsigned int irq``h]j)}(hj_]h]hunsigned int irq}(hhhja]hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj]]ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjY]ubj)}(hhh]jo)}(hInterrupt to checkh]hInterrupt to check}(hjz]hjx]hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhju]ubah}(h]h ]h"]h$]h&]uh1jhjY]ubeh}(h]h ]h"]h$]h&]uh1jhjt]hKhjV]ubah}(h]h ]h"]h$]h&]uh1jhj:]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_can_set_affinity_usr (C function)c.irq_can_set_affinity_usrhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h0bool irq_can_set_affinity_usr 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](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj]hhubjH)}(hhh]jo)}(h5Check if affinity of a irq can be set from user spaceh]h5Check if affinity of a irq can be set from user space}(hjZ^hjX^hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjU^hhubah}(h]h ]h"]h$]h&]uh1jGhj]hhhj]hKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijp^jjjp^jkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt to check **Description** Like irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.h](jo)}(h**Parameters**h]jw)}(hjz^h]h Parameters}(hhhj|^hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjx^ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjt^ubj)}(hhh]j)}(h(``unsigned int irq`` Interrupt to check h](j)}(h``unsigned int irq``h]j)}(hj^h]hunsigned int irq}(hhhj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj^ubj)}(hhh]jo)}(hInterrupt to checkh]hInterrupt to check}(hj^hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj^hKhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jhj^hKhj^ubah}(h]h ]h"]h$]h&]uh1jhjt^ubjo)}(h**Description**h]jw)}(hj^h]h Description}(hhhj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj^ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjt^ubjo)}(hYLike irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.h]hYLike irq_can_set_affinity() above, but additionally checks for the AFFINITY_MANAGED flag.}(hj^hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhjt^ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$irq_set_thread_affinity (C function)c.irq_set_thread_affinityhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h4void irq_set_thread_affinity (struct irq_desc *desc)h]j])}(h3void irq_set_thread_affinity(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKubju)}(h h]h }(hhhj(_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_hhhj'_hKubj)}(hirq_set_thread_affinityh]j)}(hirq_set_thread_affinityh]hirq_set_thread_affinity}(hhhj:_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj6_ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_hhhj'_hKubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjV_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR_ubju)}(h h]h }(hhhjc_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjR_ubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjt_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjq_ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjv_modnameN classnameNjj)}j]j)}jj<_sbc.irq_set_thread_affinityasbuh1hhjR_ubju)}(h h]h }(hhhj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjR_ubj )}(hj h]h*}(hhhj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR_ubj)}(hdesch]hdesc}(hhhj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjR_ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjN_ubah}(h]h ]h"]h$]h&]hhuh1jhj_hhhj'_hKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj_hhhj'_hKubah}(h]j _ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj_hhubjH)}(hhh]jo)}(h%Notify irq threads to adjust affinityh]h%Notify irq threads to adjust affinity}(hj_hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj_hhubah}(h]h ]h"]h$]h&]uh1jGhj_hhhj'_hKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij_jjj_jkuh1jQhhhj"YhNhNubjm)}(hX6**Parameters** ``struct irq_desc *desc`` irq descriptor which has affinity changed We just set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.h](jo)}(h**Parameters**h]jw)}(hj_h]h Parameters}(hhhj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj_ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj_ubj)}(hhh]j)}(hX``struct irq_desc *desc`` irq descriptor which has affinity changed We just set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.h](j)}(h``struct irq_desc *desc``h]j)}(hj`h]hstruct irq_desc *desc}(hhhj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj`ubj)}(hhh](jo)}(h)irq descriptor which has affinity changedh]h)irq descriptor which has affinity changed}(hj6`hj4`hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj1`ubjo)}(hWe just set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.h]hWe just set IRQTF_AFFINITY and delegate the affinity setting to the interrupt thread itself. We can not call set_cpus_allowed_ptr() here as we hold desc->lock and this code can be called from hard interrupt context.}(hjE`hjC`hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chKhj1`ubeh}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhj0`hKhj`ubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_update_affinity_desc (C function)c.irq_update_affinity_deschNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hSint irq_update_affinity_desc (unsigned int irq, struct irq_affinity_desc *affinity)h]j])}(hRint irq_update_affinity_desc(unsigned int irq, struct irq_affinity_desc *affinity)h](jc)}(hinth]hint}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj`hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMubju)}(h h]h }(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj`hhhj`hMubj)}(hirq_update_affinity_desch]j)}(hirq_update_affinity_desch]hirq_update_affinity_desc}(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj`hhhj`hMubj)}(h6(unsigned int irq, struct irq_affinity_desc *affinity)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj`ubju)}(h h]h }(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj`ubjc)}(hinth]hint}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj`ubju)}(h h]h }(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj`ubj)}(hirqh]hirq}(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj`ubj)}(h"struct irq_affinity_desc *affinityh](j)}(hjh]hstruct}(hhhjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubju)}(h h]h }(hhhjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubh)}(hhh]j)}(hirq_affinity_desch]hirq_affinity_desc}(hhhj0ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-aubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj2amodnameN classnameNjj)}j]j)}jj`sbc.irq_update_affinity_descasbuh1hhjaubju)}(h h]h }(hhhjPahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjaubj )}(hj h]h*}(hhhj^ahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubj)}(haffinityh]haffinity}(hhhjkahhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj`ubeh}(h]h ]h"]h$]h&]hhuh1jhj`hhhj`hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj|`hhhj`hMubah}(h]jw`ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjy`hhubjH)}(hhh]jo)}(h+Update affinity management for an interrupth]h+Update affinity management for an interrupt}(hjahjahhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjahhubah}(h]h ]h"]h$]h&]uh1jGhjy`hhhj`hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijajjjajkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` The interrupt number to update ``struct irq_affinity_desc *affinity`` Pointer to the affinity descriptor **Description** This interface can be used to configure the affinity management of interrupts which have been allocated already. There are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.h](jo)}(h**Parameters**h]jw)}(hjah]h Parameters}(hhhjahhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjaubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubj)}(hhh](j)}(h4``unsigned int irq`` The interrupt number to update h](j)}(h``unsigned int irq``h]j)}(hjah]hunsigned int irq}(hhhjahhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubj)}(hhh]jo)}(hThe interrupt number to updateh]hThe interrupt number to update}(hjahjahhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjahMhjaubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhjahMhjaubj)}(hJ``struct irq_affinity_desc *affinity`` Pointer to the affinity descriptor h](j)}(h&``struct irq_affinity_desc *affinity``h]j)}(hjbh]h"struct irq_affinity_desc *affinity}(hhhjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj bubj)}(hhh]jo)}(h"Pointer to the affinity descriptorh]h"Pointer to the affinity descriptor}(hj+bhj)bhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj%bhMhj&bubah}(h]h ]h"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]uh1jhj%bhMhjaubeh}(h]h ]h"]h$]h&]uh1jhjaubjo)}(h**Description**h]jw)}(hjKbh]h Description}(hhhjMbhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjIbubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubjo)}(hpThis interface can be used to configure the affinity management of interrupts which have been allocated already.h]hpThis interface can be used to configure the affinity management of interrupts which have been allocated already.}(hjcbhjabhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubjo)}(hXThere are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.h]hXThere are certain limitations on when it may be used - attempts to use it for when the kernel is configured for generic IRQ reservation mode (in config GENERIC_IRQ_RESERVATION_MODE) will fail, as it may conflict with managed/non-managed interrupt accounting. In addition, attempts to use it on an interrupt which is already started or which has already been configured as managed will also fail, as these mean invalid init state or double init.}(hjrbhjpbhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_affinity (C function)c.irq_set_affinityhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hFint irq_set_affinity (unsigned int irq, const struct cpumask *cpumask)h]j])}(hEint irq_set_affinity(unsigned int irq, const struct cpumask *cpumask)h](jc)}(hinth]hint}(hhhjbhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjbhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMubju)}(h h]h }(hhhjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbhhhjbhMubj)}(hirq_set_affinityh]j)}(hirq_set_affinityh]hirq_set_affinity}(hhhjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubah}(h]h ](jjeh"]h$]h&]hhuh1jhjbhhhjbhMubj)}(h1(unsigned int irq, const struct cpumask *cpumask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjbhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjbubju)}(h h]h }(hhhjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbubjc)}(hinth]hint}(hhhjbhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjbubju)}(h h]h }(hhhjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjbubj)}(hirqh]hirq}(hhhjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjbubj)}(hconst struct cpumask *cpumaskh](j)}(hjh]hconst}(hhhj-chhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)cubju)}(h h]h }(hhhj:chhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)cubj)}(hjh]hstruct}(hhhjHchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)cubju)}(h h]h }(hhhjUchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)cubh)}(hhh]j)}(hcpumaskh]hcpumask}(hhhjfchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjccubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjhcmodnameN classnameNjj)}j]j)}jjbsbc.irq_set_affinityasbuh1hhj)cubju)}(h h]h }(hhhjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj)cubj )}(hj h]h*}(hhhjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)cubj)}(hcpumaskh]hcpumask}(hhhjchhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj)cubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjbubeh}(h]h ]h"]h$]h&]hhuh1jhjbhhhjbhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjbhhhjbhMubah}(h]jbah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjbhhubjH)}(hhh]jo)}(h#Set the irq affinity of a given irqh]h#Set the irq affinity of a given irq}(hjchjchhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjchhubah}(h]h ]h"]h$]h&]uh1jGhjbhhhjbhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijcjjjcjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt to set affinity ``const struct cpumask *cpumask`` cpumask **Description** Fails if cpumask does not contain an online CPUh](jo)}(h**Parameters**h]jw)}(hjch]h Parameters}(hhhjchhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjcubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjcubj)}(hhh](j)}(h/``unsigned int irq`` Interrupt to set affinity h](j)}(h``unsigned int irq``h]j)}(hj dh]hunsigned int irq}(hhhjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj dubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjdubj)}(hhh]jo)}(hInterrupt to set affinityh]hInterrupt to set affinity}(hj(dhj&dhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj"dhMhj#dubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhj"dhMhjdubj)}(h*``const struct cpumask *cpumask`` cpumask h](j)}(h!``const struct cpumask *cpumask``h]j)}(hjFdh]hconst struct cpumask *cpumask}(hhhjHdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDdubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj@dubj)}(hhh]jo)}(hcpumaskh]hcpumask}(hjadhj_dhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj[dhMhj\dubah}(h]h ]h"]h$]h&]uh1jhj@dubeh}(h]h ]h"]h$]h&]uh1jhj[dhMhjdubeh}(h]h ]h"]h$]h&]uh1jhjcubjo)}(h**Description**h]jw)}(hjdh]h Description}(hhhjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjdubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjcubjo)}(h/Fails if cpumask does not contain an online CPUh]h/Fails if cpumask does not contain an online CPU}(hjdhjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjcubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_force_affinity (C function)c.irq_force_affinityhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hHint irq_force_affinity (unsigned int irq, const struct cpumask *cpumask)h]j])}(hGint irq_force_affinity(unsigned int irq, const struct cpumask *cpumask)h](jc)}(hinth]hint}(hhhjdhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjdhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMubju)}(h h]h }(hhhjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdhhhjdhMubj)}(hirq_force_affinityh]j)}(hirq_force_affinityh]hirq_force_affinity}(hhhjdhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubah}(h]h ](jjeh"]h$]h&]hhuh1jhjdhhhjdhMubj)}(h1(unsigned int irq, const struct cpumask *cpumask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjehhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjdubju)}(h h]h }(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdubjc)}(hinth]hint}(hhhjehhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjdubju)}(h h]h }(hhhj-ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjdubj)}(hirqh]hirq}(hhhj;ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjdubj)}(hconst struct cpumask *cpumaskh](j)}(hjh]hconst}(hhhjTehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPeubju)}(h h]h }(hhhjaehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPeubj)}(hjh]hstruct}(hhhjoehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPeubju)}(h h]h }(hhhj|ehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPeubh)}(hhh]j)}(hcpumaskh]hcpumask}(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjemodnameN classnameNjj)}j]j)}jjdsbc.irq_force_affinityasbuh1hhjPeubju)}(h h]h }(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPeubj )}(hj h]h*}(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPeubj)}(hcpumaskh]hcpumask}(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPeubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjdubeh}(h]h ]h"]h$]h&]hhuh1jhjdhhhjdhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjdhhhjdhMubah}(h]jdah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjdhhubjH)}(hhh]jo)}(h%Force the irq affinity of a given irqh]h%Force the irq affinity of a given irq}(hjehjehhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjehhubah}(h]h ]h"]h$]h&]uh1jGhjdhhhjdhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij fjjj fjkuh1jQhhhj"YhNhNubjm)}(hXC**Parameters** ``unsigned int irq`` Interrupt to set affinity ``const struct cpumask *cpumask`` cpumask **Description** Same as irq_set_affinity, but without checking the mask against online cpus. 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Function pointers must be initialised; the other fields will be initialised by this function. Must be called in process context. Notification may only be enabled after the IRQ is allocated and must be disabled before the IRQ is freed using free_irq().h](jo)}(h**Parameters**h]jw)}(hj0hh]h Parameters}(hhhj2hhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj.hubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM'hj*hubj)}(hhh](j)}(hH``unsigned int irq`` Interrupt for which to enable/disable notification h](j)}(h``unsigned int irq``h]j)}(hjOhh]hunsigned int irq}(hhhjQhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMhubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM$hjIhubj)}(hhh]jo)}(h2Interrupt for which to enable/disable notificationh]h2Interrupt for which to enable/disable notification}(hjjhhjhhhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjdhhM$hjehubah}(h]h ]h"]h$]h&]uh1jhjIhubeh}(h]h ]h"]h$]h&]uh1jhjdhhM$hjFhubj)}(hXs``struct irq_affinity_notify *notify`` Context for notification, or ``NULL`` to disable notification. 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Enables and Disables are nested. This function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. Can only be called from preemptible code as it might sleep when an interrupt thread is associated to **irq**.h](jo)}(h**Parameters**h]jw)}(hjlh]h Parameters}(hhhjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjlubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjlubj)}(hhh]j)}(hX``unsigned int irq`` Interrupt to disable Disable the selected interrupt line. Enables and Disables are nested. This function waits for any pending IRQ handlers for this interrupt to complete before returning. If you use this function while holding a resource the IRQ handler may need you will deadlock. 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If this matches the last disable, processing of interrupts on this IRQ line is re-enabled. This function may be called from IRQ context only when desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL !h](j)}(h``unsigned int irq``h]j)}(hjbqh]hunsigned int irq}(hhhjdqhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`qubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM<hj\qubj)}(hhh](jo)}(hInterrupt to enableh]hInterrupt to enable}(hj}qhj{qhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM6hjxqubjo)}(hUndoes the effect of one call to disable_irq(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h]hUndoes the effect of one call to disable_irq(). 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Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h](jo)}(h**Parameters**h]jw)}(hjrh]h Parameters}(hhhjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjrubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMUhjrubj)}(hhh]j)}(h``unsigned int irq`` Interrupt to enable The interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h](j)}(h``unsigned int irq``h]j)}(hjrh]hunsigned int irq}(hhhjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMVhjrubj)}(hhh](jo)}(hInterrupt to enableh]hInterrupt to enable}(hjrhjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMRhjrubjo)}(hThe interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). If this matches the last disable, processing of interrupts on this IRQ line is re-enabled.h]hThe interrupt to enable must have been requested through request_nmi. Undoes the effect of one call to disable_nmi(). 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Enables and disables must match, just as they match for non-wakeup mode support. Wakeup mode lets this IRQ wake the system from sleep states like "suspend to RAM". **Note** irq enable/disable state is completely orthogonal to the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. 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Wakeup mode lets this IRQ wake the system from sleep states like "suspend to RAM". h](j)}(h``unsigned int on``h]j)}(hjth]hunsigned int on}(hhhjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMvhjtubj)}(hhh](jo)}(h&enable/disable power management wakeuph]h&enable/disable power management wakeup}(hjthjthhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMohjtubjo)}(hEnable/disable power management wakeup mode, which is disabled by default. Enables and disables must match, just as they match for non-wakeup mode support.h]hEnable/disable power management wakeup mode, which is disabled by default. Enables and disables must match, just as they match for non-wakeup mode support.}(hjthjthhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMqhjtubjo)}(hRWakeup mode lets this IRQ wake the system from sleep states like "suspend to RAM".h]hVWakeup mode lets this IRQ wake the system from sleep states like “suspend to RAM”.}(hjthjthhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMuhjtubeh}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjthMvhjLtubeh}(h]h ]h"]h$]h&]uh1jhj0tubjo)}(h**Note**h]jw)}(hjth]hNote}(hhhjthhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjtubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMxhj0tubj)}(hhh]j)}(hX'irq enable/disable state is completely orthogonal to the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. If this does not hold, then the underlying irq chip and the related driver need to be investigated.h](j)}(h1irq enable/disable state is completely orthogonalh]h1irq enable/disable state is completely orthogonal}(hjuhjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM|hjuubj)}(hhh]jo)}(hto the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. If this does not hold, then the underlying irq chip and the related driver need to be investigated.h]hto the enable/disable state of irq wake. An irq can be disabled with disable_irq() and still wake the system as long as the irq has wake enabled. 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Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed. ``irq_handler_t thread_fn`` Function called from the irq handler thread If NULL, no irq thread is created ``unsigned long irqflags`` Interrupt type flags ``const char *devname`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order. If you want to set up a threaded irq handler for your device then you need to supply **handler** and **thread_fn**. **handler** is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run **thread_fn**. This split handler design is necessary to support shared interrupts. Dev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt. Flags: IRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh](jo)}(h**Parameters**h]jw)}(hj]{h]h Parameters}(hhhj_{hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj[{ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMBhjW{ubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hj|{h]hunsigned int irq}(hhhj~{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM?hjv{ubj)}(hhh]jo)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hj{hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj{hM?hj{ubah}(h]h ]h"]h$]h&]uh1jhjv{ubeh}(h]h ]h"]h$]h&]uh1jhj{hM?hjs{ubj)}(h``irq_handler_t handler`` Function to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed. h](j)}(h``irq_handler_t handler``h]j)}(hj{h]hirq_handler_t handler}(hhhj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMChj{ubj)}(hhh]jo)}(hFunction to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed.h]hFunction to be called when the IRQ occurs. Primary handler for threaded interrupts. If handler is NULL and thread_fn != NULL the default primary handler is installed.}(hj{hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM@hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhj{hMChjs{ubj)}(hj``irq_handler_t thread_fn`` Function called from the irq handler thread If NULL, no irq thread is created h](j)}(h``irq_handler_t thread_fn``h]j)}(hj{h]hirq_handler_t thread_fn}(hhhj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj{ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMEhj{ubj)}(hhh]jo)}(hMFunction called from the irq handler thread If NULL, no irq thread is createdh]hMFunction called from the irq handler thread If NULL, no irq thread is created}(hj |hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMDhj|ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhj|hMEhjs{ubj)}(h0``unsigned long irqflags`` Interrupt type flags h](j)}(h``unsigned long irqflags``h]j)}(hj)|h]hunsigned long irqflags}(hhhj+|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'|ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMFhj#|ubj)}(hhh]jo)}(hInterrupt type flagsh]hInterrupt type flags}(hjD|hjB|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj>|hMFhj?|ubah}(h]h ]h"]h$]h&]uh1jhj#|ubeh}(h]h ]h"]h$]h&]uh1jhj>|hMFhjs{ubj)}(h>``const char *devname`` An ascii name for the claiming device h](j)}(h``const char *devname``h]j)}(hjb|h]hconst char *devname}(hhhjd|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`|ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMGhj\|ubj)}(hhh]jo)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hj}|hj{|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjw|hMGhjx|ubah}(h]h ]h"]h$]h&]uh1jhj\|ubeh}(h]h ]h"]h$]h&]uh1jhjw|hMGhjs{ubj)}(hX``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order. If you want to set up a threaded irq handler for your device then you need to supply **handler** and **thread_fn**. **handler** is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run **thread_fn**. This split handler design is necessary to support shared interrupts. Dev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt. Flags: IRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh](j)}(h``void *dev_id``h]j)}(hj|h]h void *dev_id}(hhhj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMdhj|ubj)}(hhh](jo)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hj|hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMHhj|ubjo)}(hXRThis call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order.h]hXRThis call allocates interrupt resources and enables the interrupt line and IRQ handling. From the point this call is made your handler function may be invoked. Since your handler function must clear any interrupt the board raises, you must take care both to initialise your hardware and to set up the interrupt handler in the right order.}(hj|hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMJhj|ubjo)}(hXIf you want to set up a threaded irq handler for your device then you need to supply **handler** and **thread_fn**. **handler** is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run **thread_fn**. This split handler design is necessary to support shared interrupts.h](hUIf you want to set up a threaded irq handler for your device then you need to supply }(hUIf you want to set up a threaded irq handler for your device then you need to supply hj|hhhNhNubjw)}(h **handler**h]hhandler}(hhhj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj|ubh and }(h and hj|hhhNhNubjw)}(h **thread_fn**h]h thread_fn}(hhhj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj|ubh. }(h. hj|hhhNhNubjw)}(h **handler**h]hhandler}(hhhj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj|ubh is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run }(h is still called in hard interrupt context and has to check whether the interrupt originates from the device. If yes it needs to disable the interrupt on the device and return IRQ_WAKE_THREAD which will wake up the handler thread and run hj|hhhNhNubjw)}(h **thread_fn**h]h thread_fn}(hhhj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj|ubhF. This split handler design is necessary to support shared interrupts.}(hF. This split handler design is necessary to support shared interrupts.hj|hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMQhj|ubjo)}(hDev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.h]hDev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.}(hj0}hj.}hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMZhj|ubjo)}(hkIf your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt.h]hkIf your interrupt is shared you must pass a non NULL dev_id as this is required when freeing the interrupt.}(hj?}hj=}hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM^hj|ubjo)}(hFlags:h]hFlags:}(hjN}hjL}hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMahj|ubjo)}(hIRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line maskedh]hIRQF_SHARED Interrupt is shared IRQF_TRIGGER_* Specify active edge(s) or level IRQF_ONESHOT Run thread_fn with interrupt line masked}(hj]}hj[}hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMchj|ubeh}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhj|hMdhjs{ubeh}(h]h ]h"]h$]h&]uh1jhjW{ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$request_any_context_irq (C function)c.request_any_context_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hzint request_any_context_irq (unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h]j])}(hyint request_any_context_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h](jc)}(hinth]hint}(hhhj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}hhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMubju)}(h h]h }(hhhj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}hhhj}hMubj)}(hrequest_any_context_irqh]j)}(hrequest_any_context_irqh]hrequest_any_context_irq}(hhhj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj}hhhj}hMubj)}(h^(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}ubju)}(h h]h }(hhhj}hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubjc)}(hinth]hint}(hhhj}hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj}ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj}ubj)}(hirqh]hirq}(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hhhj-~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj*~ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj/~modnameN classnameNjj)}j]j)}jj}sbc.request_any_context_irqasbuh1hhj&~ubju)}(h h]h }(hhhjM~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj&~ubj)}(hhandlerh]hhandler}(hhhj[~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubj)}(hunsigned long flagsh](jc)}(hunsignedh]hunsigned}(hhhjt~hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjp~ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjp~ubjc)}(hlongh]hlong}(hhhj~hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjp~ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjp~ubj)}(hflagsh]hflags}(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjp~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubj)}(hconst char *nameh](j)}(hjh]hconst}(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~ubjc)}(hcharh]hchar}(hhhj~hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj~ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~ubj )}(hj h]h*}(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hnameh]hname}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hhhj"hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hhhjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj}ubeh}(h]h ]h"]h$]h&]hhuh1jhj}hhhj}hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj}hhhj}hMubah}(h]j}ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj}hhubjH)}(hhh]jo)}(hallocate an interrupt lineh]hallocate an interrupt line}(hjxhjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjshhubah}(h]h ]h"]h$]h&]uh1jGhj}hhhj}hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. ``unsigned long flags`` Interrupt type flags ``const char *name`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context. On failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubj)}(hhh]jo)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(ho``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. h](j)}(h``irq_handler_t handler``h]j)}(hjh]hirq_handler_t handler}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubj)}(hhh]jo)}(hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.h]hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h-``unsigned long flags`` Interrupt type flags h](j)}(h``unsigned long flags``h]j)}(hj*h]hunsigned long flags}(hhhj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj$ubj)}(hhh]jo)}(hInterrupt type flagsh]hInterrupt type flags}(hjEhjChhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj?hMhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jhj?hMhjubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjch]hconst char *name}(hhhjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj]ubj)}(hhh]jo)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hj~hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjxhMhjyubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjxhMhjubj)}(hXT``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context. On failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.h](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubj)}(hhh](jo)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubjo)}(hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context.h]hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It selects either a hardirq or threaded handling method depending on the context.}(hjƀhjĀhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubjo)}(hiOn failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.h]hiOn failure, it returns a negative value. On success, it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED.}(hjՀhjӀhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMrequest_nmi (C function) c.request_nmihNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hqint request_nmi (unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h]j])}(hpint request_nmi(unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMubju)}(h h]h }(hhhj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj!hMubj)}(h request_nmih]j)}(h request_nmih]h request_nmi}(hhhj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj!hMubj)}(ha(unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *name, void *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjPhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjLubju)}(h h]h }(hhhj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLubjc)}(hinth]hint}(hhhjlhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjLubju)}(h h]h }(hhhjzhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj6sb c.request_nmiasbuh1hhjubju)}(h h]h }(hhhjāhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hhhjҁhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubj)}(hunsigned long irqflagsh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hlongh]hlong}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqflagsh]hirqflags}(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubj)}(hconst char *nameh](j)}(hjh]hconst}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubju)}(h h]h }(hhhjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8ubjc)}(hcharh]hchar}(hhhjWhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj8ubju)}(h h]h }(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj8ubj )}(hj h]h*}(hhhjshhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubj)}(hnameh]hname}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubj)}(h void *dev_idh](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hhhj‚hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj!hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj hhhj!hMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(h+allocate an interrupt line for NMI deliveryh]h+allocate an interrupt line for NMI delivery}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj!hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. ``unsigned long irqflags`` Interrupt type flags ``const char *name`` An ascii name for the claiming device ``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI. An interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded. Interrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled. Dev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj ubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hj.h]hunsigned int irq}(hhhj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj(ubj)}(hhh]jo)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjIhjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjChMhjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhjChMhj%ubj)}(ho``irq_handler_t handler`` Function to be called when the IRQ occurs. Threaded handler for threaded interrupts. h](j)}(h``irq_handler_t handler``h]j)}(hjgh]hirq_handler_t handler}(hhhjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjaubj)}(hhh]jo)}(hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.h]hTFunction to be called when the IRQ occurs. Threaded handler for threaded interrupts.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj}ubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jhj|hMhj%ubj)}(h0``unsigned long irqflags`` Interrupt type flags h](j)}(h``unsigned long irqflags``h]j)}(hjh]hunsigned long irqflags}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjubj)}(hhh]jo)}(hInterrupt type flagsh]hInterrupt type flags}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhj%ubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjڃh]hconst char *name}(hhhj܃hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj؃ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhjԃubj)}(hhh]jo)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjԃubeh}(h]h ]h"]h$]h&]uh1jhjhMhj%ubj)}(hX``void *dev_id`` A cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI. An interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded. Interrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled. Dev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it. If the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.h](j)}(h``void *dev_id``h]j)}(hjh]h void *dev_id}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj ubj)}(hhh](jo)}(h,A cookie passed back to the handler functionh]h,A cookie passed back to the handler function}(hj.hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj)ubjo)}(hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI.h]hThis call allocates interrupt resources and enables the interrupt line and IRQ handling. It sets up the IRQ line to be handled as an NMI.}(hj=hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj)ubjo)}(hWAn interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded.h]hWAn interrupt line delivering NMIs cannot be shared and IRQ handling cannot be threaded.}(hjLhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj)ubjo)}(huInterrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled.h]huInterrupt lines requested for NMI delivering must produce per cpu interrupts and have auto enabling setting disabled.}(hj[hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj)ubjo)}(hDev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.h]hDev_id must be globally unique. Normally the address of the device data structure is used as the cookie. Since the handler receives this value it makes sense to use it.}(hjjhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMhj)ubjo)}(heIf the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.h]heIf the interrupt line cannot be used to deliver NMIs, function will fail and return a negative value.}(hjyhjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj(hM hj)ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj(hM hj%ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_percpu_is_enabled (C function)c.irq_percpu_is_enabledhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h-bool irq_percpu_is_enabled (unsigned int irq)h]j])}(h,bool irq_percpu_is_enabled(unsigned int irq)h](jc)}(hj\Yh]hbool}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMt ubju)}(h h]h }(hhhjńhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjĄhMt ubj)}(hirq_percpu_is_enabledh]j)}(hirq_percpu_is_enabledh]hirq_percpu_is_enabled}(hhhjׄhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjӄubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjĄhMt ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hhhj+hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjĄhMt ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjĄhMt ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMy hjhhubjH)}(hhh]jo)}(h(Check whether the per cpu irq is enabledh]h(Check whether the per cpu irq is enabled}(hjXhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMs hjShhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjĄhMt ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijnjjjnjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` Linux irq number to check for **Description** Must be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.h](jo)}(h**Parameters**h]jw)}(hjxh]h Parameters}(hhhjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjvubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMw hjrubj)}(hhh]j)}(h3``unsigned int irq`` Linux irq number to check for h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMt hjubj)}(hhh]jo)}(hLinux irq number to check forh]hLinux irq number to check for}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMt hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMt hjubah}(h]h ]h"]h$]h&]uh1jhjrubjo)}(h**Description**h]jw)}(hj҅h]h Description}(hhhjԅhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjЅubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMv hjrubjo)}(hqMust be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.h]hqMust be called from a non migratable context. Returns the enable state of a per cpu interrupt on the current cpu.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMv hjrubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMremove_percpu_irq (C function)c.remove_percpu_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h@void remove_percpu_irq (unsigned int irq, struct irqaction *act)h]j])}(h?void remove_percpu_irq(unsigned int irq, struct irqaction *act)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj%hM ubj)}(hremove_percpu_irqh]j)}(hremove_percpu_irqh]hremove_percpu_irq}(hhhj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj%hM ubj)}(h)(unsigned int irq, struct irqaction *act)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjThhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjPubju)}(h h]h }(hhhjbhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPubjc)}(hinth]hint}(hhhjphhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjPubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubj)}(hstruct irqaction *acth](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(h irqactionh]h irqaction}(hhhjÆhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjņmodnameN classnameNjj)}j]j)}jj:sbc.remove_percpu_irqasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hacth]hact}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj%hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj%hM ubah}(h]j ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj hhubjH)}(hhh]jo)}(hfree a per-cpu interrupth]hfree a per-cpu interrupt}(hj+hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj&hhubah}(h]h ]h"]h$]h&]uh1jGhj hhhj%hM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijAjjjAjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt line to free ``struct irqaction *act`` irqaction for the interrupt **Description** Used to remove interrupts statically setup by the early boot process.h](jo)}(h**Parameters**h]jw)}(hjKh]h Parameters}(hhhjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjIubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjEubj)}(hhh](j)}(h,``unsigned int irq`` Interrupt line to free h](j)}(h``unsigned int irq``h]j)}(hjjh]hunsigned int irq}(hhhjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjdubj)}(hhh]jo)}(hInterrupt line to freeh]hInterrupt line to free}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jhjhM hjaubj)}(h6``struct irqaction *act`` irqaction for the interrupt h](j)}(h``struct irqaction *act``h]j)}(hjh]hstruct irqaction *act}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh]jo)}(hirqaction for the interrupth]hirqaction for the interrupt}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjaubeh}(h]h ]h"]h$]h&]uh1jhjEubjo)}(h**Description**h]jw)}(hjއh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj܇ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjEubjo)}(hEUsed to remove interrupts statically setup by the early boot process.h]hEUsed to remove interrupts statically setup by the early boot process.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjEubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMfree_percpu_irq (C function)c.free_percpu_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h>void free_percpu_irq (unsigned int irq, void __percpu *dev_id)h]j])}(h=void free_percpu_irq(unsigned int irq, void __percpu *dev_id)h](jc)}(hvoidh]hvoid}(hhhj#hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj1hM ubj)}(hfree_percpu_irqh]j)}(hfree_percpu_irqh]hfree_percpu_irq}(hhhjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj1hM ubj)}(h)(unsigned int irq, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubjc)}(hinth]hint}(hhhj|hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__percpu}(hhhjhhhNhNubju)}(h h]h }(hhhjшhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj߈hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj1hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj1hM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(h3free an interrupt allocated with request_percpu_irqh]h3free an interrupt allocated with request_percpu_irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj1hM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij/jjj/jkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line to free ``void __percpu *dev_id`` Device identity to free Remove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed. This function must not be called from interrupt context.h](jo)}(h**Parameters**h]jw)}(hj9h]h Parameters}(hhhj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj7ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj3ubj)}(hhh](j)}(h,``unsigned int irq`` Interrupt line to free h](j)}(h``unsigned int irq``h]j)}(hjXh]hunsigned int irq}(hhhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjRubj)}(hhh]jo)}(hInterrupt line to freeh]hInterrupt line to free}(hjshjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjmhM hjnubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jhjmhM hjOubj)}(hXd``void __percpu *dev_id`` Device identity to free Remove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed. This function must not be called from interrupt context.h](j)}(h``void __percpu *dev_id``h]j)}(hjh]hvoid __percpu *dev_id}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh](jo)}(hDevice identity to freeh]hDevice identity to free}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hRemove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed.h]hRemove a percpu interrupt handler. The handler is removed, but the interrupt line is not disabled. This must be done on each CPU before calling this function. The function does not return until any executing interrupts for this IRQ have completed.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(h8This function must not be called from interrupt context.h]h8This function must not be called from interrupt context.}(hjʉhjȉhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjOubeh}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMsetup_percpu_irq (C function)c.setup_percpu_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h>int setup_percpu_irq (unsigned int irq, struct irqaction *act)h]j])}(h=int setup_percpu_irq(unsigned int irq, struct irqaction *act)h](jc)}(hinth]hint}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hsetup_percpu_irqh]j)}(hsetup_percpu_irqh]hsetup_percpu_irq}(hhhj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj&ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h)(unsigned int irq, struct irqaction *act)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjFhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjBubju)}(h h]h }(hhhjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjBubjc)}(hinth]hint}(hhhjbhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjBubju)}(h h]h }(hhhjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjBubj)}(hirqh]hirq}(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj>ubj)}(hstruct irqaction *acth](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(h irqactionh]h irqaction}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj,sbc.setup_percpu_irqasbuh1hhjubju)}(h h]h }(hhhjՊhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hacth]hact}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj>ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(hsetup a per-cpu interrupth]hsetup a per-cpu interrupt}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij3jjj3jkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt line to setup ``struct irqaction *act`` irqaction for the interrupt **Description** Used to statically setup per-cpu interrupts in the early boot process.h](jo)}(h**Parameters**h]jw)}(hj=h]h Parameters}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj;ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj7ubj)}(hhh](j)}(h-``unsigned int irq`` Interrupt line to setup h](j)}(h``unsigned int irq``h]j)}(hj\h]hunsigned int irq}(hhhj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjVubj)}(hhh]jo)}(hInterrupt line to setuph]hInterrupt line to setup}(hjwhjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjqhM hjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhM hjSubj)}(h6``struct irqaction *act`` irqaction for the interrupt h](j)}(h``struct irqaction *act``h]j)}(hjh]hstruct irqaction *act}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh]jo)}(hirqaction for the interrupth]hirqaction for the interrupt}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjSubeh}(h]h ]h"]h$]h&]uh1jhj7ubjo)}(h**Description**h]jw)}(hjЋh]h Description}(hhhjҋhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj΋ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj7ubjo)}(hFUsed to statically setup per-cpu interrupts in the early boot process.h]hFUsed to statically setup per-cpu interrupts in the early boot process.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj7ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!__request_percpu_irq (C function)c.__request_percpu_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hint __request_percpu_irq (unsigned int irq, irq_handler_t handler, unsigned long flags, const char *devname, void __percpu *dev_id)h]j])}(hint __request_percpu_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *devname, void __percpu *dev_id)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj#hM ubj)}(h__request_percpu_irqh]j)}(h__request_percpu_irqh]h__request_percpu_irq}(hhhj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj2ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj#hM ubj)}(hj(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *devname, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjRhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjNubju)}(h h]h }(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjNubjc)}(hinth]hint}(hhhjnhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjNubju)}(h h]h }(hhhj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjNubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj8sbc.__request_percpu_irqasbuh1hhjubju)}(h h]h }(hhhjƌhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhandlerh]hhandler}(hhhjԌhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(hunsigned long flagsh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hlongh]hlong}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hflagsh]hflags}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(hconst char *devnameh](j)}(hjh]hconst}(hhhj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubju)}(h h]h }(hhhjKhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj:ubjc)}(hcharh]hchar}(hhhjYhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj:ubju)}(h h]h }(hhhjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj:ubj )}(hj h]h*}(hhhjuhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubj)}(hdevnameh]hdevname}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh__percpu}(hhhjhhhNhNubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjɍhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdev_idh]hdev_id}(hhhj֍hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjJubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj#hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj hhhj#hM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM- hj hhubjH)}(hhh]jo)}(h allocate a percpu interrupt lineh]h allocate a percpu interrupt line}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jGhj hhhj#hM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. ``unsigned long flags`` Interrupt type flags (IRQF_TIMER only) ``const char *devname`` An ascii name for the claiming device ``void __percpu *dev_id`` A percpu cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt on the local CPU. If the interrupt is supposed to be enabled on other CPUs, it has to be done on each CPU using enable_percpu_irq(). Dev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h](jo)}(h**Parameters**h]jw)}(hj#h]h Parameters}(hhhj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj!ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM! hjubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjBh]hunsigned int irq}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj@ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj<ubj)}(hhh]jo)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hj]hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjWhM hjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jhjWhM hj9ubj)}(hE``irq_handler_t handler`` Function to be called when the IRQ occurs. h](j)}(h``irq_handler_t handler``h]j)}(hj{h]hirq_handler_t handler}(hhhj}hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjuubj)}(hhh]jo)}(h*Function to be called when the IRQ occurs.h]h*Function to be called when the IRQ occurs.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jhjhM hj9ubj)}(h?``unsigned long flags`` Interrupt type flags (IRQF_TIMER only) h](j)}(h``unsigned long flags``h]j)}(hjh]hunsigned long flags}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh]jo)}(h&Interrupt type flags (IRQF_TIMER only)h]h&Interrupt type flags (IRQF_TIMER only)}(hjώhj͎hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjɎhM hjʎubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjɎhM hj9ubj)}(h>``const char *devname`` An ascii name for the claiming device h](j)}(h``const char *devname``h]j)}(hjh]hconst char *devname}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM! hjubj)}(hhh]jo)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM! hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM! hj9ubj)}(hX``void __percpu *dev_id`` A percpu cookie passed back to the handler function This call allocates interrupt resources and enables the interrupt on the local CPU. If the interrupt is supposed to be enabled on other CPUs, it has to be done on each CPU using enable_percpu_irq(). Dev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h](j)}(h``void __percpu *dev_id``h]j)}(hj&h]hvoid __percpu *dev_id}(hhhj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM* hj ubj)}(hhh](jo)}(h3A percpu cookie passed back to the handler functionh]h3A percpu cookie passed back to the handler function}(hjAhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM" hj<ubjo)}(hThis call allocates interrupt resources and enables the interrupt on the local CPU. If the interrupt is supposed to be enabled on other CPUs, it has to be done on each CPU using enable_percpu_irq().h]hThis call allocates interrupt resources and enables the interrupt on the local CPU. If the interrupt is supposed to be enabled on other CPUs, it has to be done on each CPU using enable_percpu_irq().}(hjPhjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM$ hj<ubjo)}(hDev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h]hDev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU’s instance of that variable.}(hj_hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM) hj<ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj;hM* hj9ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMrequest_percpu_nmi (C function)c.request_percpu_nmihNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hiint request_percpu_nmi (unsigned int irq, irq_handler_t handler, const char *name, void __percpu *dev_id)h]j])}(hhint request_percpu_nmi(unsigned int irq, irq_handler_t handler, const char *name, void __percpu *dev_id)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM\ ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM\ ubj)}(hrequest_percpu_nmih]j)}(hrequest_percpu_nmih]hrequest_percpu_nmi}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM\ ubj)}(hR(unsigned int irq, irq_handler_t handler, const char *name, void __percpu *dev_id)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjۏhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj׏ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj׏ubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj׏ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj׏ubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj׏ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjӏubj)}(hirq_handler_t handlerh](h)}(hhh]j)}(h irq_handler_th]h irq_handler_t}(hhhj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj1modnameN classnameNjj)}j]j)}jjsbc.request_percpu_nmiasbuh1hhj(ubju)}(h h]h }(hhhjOhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj(ubj)}(hhandlerh]hhandler}(hhhj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjӏubj)}(hconst char *nameh](j)}(hjh]hconst}(hhhjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjrubjc)}(hcharh]hchar}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjrubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjrubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubj)}(hnameh]hname}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjӏubj)}(hvoid __percpu *dev_idh](jc)}(hvoidh]hvoid}(hhhjӐhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjϐubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjϐubh__percpu}(hhhjϐhhhNhNubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjϐubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϐubj)}(hdev_idh]hdev_id}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjϐubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjӏubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM\ ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM\ ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMo hjhhubjH)}(hhh]jo)}(h1allocate a percpu interrupt line for NMI deliveryh]h1allocate a percpu interrupt line for NMI delivery}(hj;hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM[ hj6hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhM\ ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijQjjjQjkuh1jQhhhj"YhNhNubjm)}(hXB**Parameters** ``unsigned int irq`` Interrupt line to allocate ``irq_handler_t handler`` Function to be called when the IRQ occurs. ``const char *name`` An ascii name for the claiming device ``void __percpu *dev_id`` A percpu cookie passed back to the handler function This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi(). Dev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable. Interrupt lines requested for NMI delivering should have auto enabling setting disabled. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](jo)}(h**Parameters**h]jw)}(hj[h]h Parameters}(hhhj]hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjYubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM_ hjUubj)}(hhh](j)}(h0``unsigned int irq`` Interrupt line to allocate h](j)}(h``unsigned int irq``h]j)}(hjzh]hunsigned int irq}(hhhj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM\ hjtubj)}(hhh]jo)}(hInterrupt line to allocateh]hInterrupt line to allocate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM\ hjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jhjhM\ hjqubj)}(hE``irq_handler_t handler`` Function to be called when the IRQ occurs. h](j)}(h``irq_handler_t handler``h]j)}(hjh]hirq_handler_t handler}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM] hjubj)}(hhh]jo)}(h*Function to be called when the IRQ occurs.h]h*Function to be called when the IRQ occurs.}(hjΑhj̑hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjȑhM] hjɑubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjȑhM] hjqubj)}(h;``const char *name`` An ascii name for the claiming device h](j)}(h``const char *name``h]j)}(hjh]hconst char *name}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM^ hjubj)}(hhh]jo)}(h%An ascii name for the claiming deviceh]h%An ascii name for the claiming device}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM^ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM^ hjqubj)}(hXc``void __percpu *dev_id`` A percpu cookie passed back to the handler function This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi(). Dev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable. Interrupt lines requested for NMI delivering should have auto enabling setting disabled. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](j)}(h``void __percpu *dev_id``h]j)}(hj%h]hvoid __percpu *dev_id}(hhhj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMl hjubj)}(hhh](jo)}(h3A percpu cookie passed back to the handler functionh]h3A percpu cookie passed back to the handler function}(hj@hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM_ hj;ubjo)}(hThis call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi().h]hThis call allocates interrupt resources for a per CPU NMI. Per CPU NMIs have to be setup on each CPU by calling prepare_percpu_nmi() before being enabled on the same CPU by using enable_percpu_nmi().}(hjOhjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMa hj;ubjo)}(hDev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU's instance of that variable.h]hDev_id must be globally unique. It is a per-cpu variable, and the handler gets called with the interrupted CPU’s instance of that variable.}(hj^hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMe hj;ubjo)}(hXInterrupt lines requested for NMI delivering should have auto enabling setting disabled.h]hXInterrupt lines requested for NMI delivering should have auto enabling setting disabled.}(hjmhjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMi hj;ubjo)}(hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h]hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.}(hj|hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj:hMl hj;ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj:hMl hjqubeh}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMprepare_percpu_nmi (C function)c.prepare_percpu_nmihNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h)int prepare_percpu_nmi (unsigned int irq)h]j])}(h(int prepare_percpu_nmi(unsigned int irq)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhjɒhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjȒhM ubj)}(hprepare_percpu_nmih]j)}(hprepare_percpu_nmih]hprepare_percpu_nmi}(hhhjےhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjגubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjȒhM ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hhhj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjȒhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjȒhM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(h)performs CPU local setup for NMI deliveryh]h)performs CPU local setup for NMI delivery}(hj\hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjWhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjȒhM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijrjjjrjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line to prepare for NMI delivery This call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi(). As a CPU local operation, this should be called from non-preemptible context. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](jo)}(h**Parameters**h]jw)}(hj|h]h Parameters}(hhhj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjzubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjvubj)}(hhh]j)}(hX``unsigned int irq`` Interrupt line to prepare for NMI delivery This call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi(). As a CPU local operation, this should be called from non-preemptible context. If the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh](jo)}(h*Interrupt line to prepare for NMI deliveryh]h*Interrupt line to prepare for NMI delivery}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hThis call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi().h]hThis call prepares an interrupt line to deliver NMI on the current CPU, before that interrupt line gets enabled with enable_percpu_nmi().}(hjœhjÓhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hMAs a CPU local operation, this should be called from non-preemptible context.h]hMAs a CPU local operation, this should be called from non-preemptible context.}(hjԓhjғhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.h]hdIf the interrupt line cannot be used to deliver NMIs, function will fail returning a negative value.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM teardown_percpu_nmi (C function)c.teardown_percpu_nmihNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h+void teardown_percpu_nmi (unsigned int irq)h]j])}(h*void teardown_percpu_nmi(unsigned int irq)h](jc)}(hvoidh]hvoid}(hhhj!hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj/hM ubj)}(hteardown_percpu_nmih]j)}(hteardown_percpu_nmih]hteardown_percpu_nmi}(hhhjBhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj>ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj/hM ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj^hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjZubju)}(h h]h }(hhhjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZubjc)}(hinth]hint}(hhhjzhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjZubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjZubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjVubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj/hM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj/hM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(hundoes NMI setup of IRQ lineh]hundoes NMI setup of IRQ line}(hjÔhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj/hM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijٔjjjٔjkuh1jQhhhj"YhNhNubjm)}(hXJ**Parameters** ``unsigned int irq`` Interrupt line from which CPU local NMI configuration should be removed This call undoes the setup done by prepare_percpu_nmi(). IRQ line should not be enabled for the current CPU. As a CPU local operation, this should be called from non-preemptible context.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjݔubj)}(hhh]j)}(hX.``unsigned int irq`` Interrupt line from which CPU local NMI configuration should be removed This call undoes the setup done by prepare_percpu_nmi(). IRQ line should not be enabled for the current CPU. As a CPU local operation, this should be called from non-preemptible context.h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh](jo)}(hGInterrupt line from which CPU local NMI configuration should be removedh]hGInterrupt line from which CPU local NMI configuration should be removed}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjZ)}(hhh](jo)}(h8This call undoes the setup done by prepare_percpu_nmi().h]h8This call undoes the setup done by prepare_percpu_nmi().}(hj/hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj*ubjo)}(h3IRQ line should not be enabled for the current CPU.h]h3IRQ line should not be enabled for the current CPU.}(hj>hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hj*ubjo)}(hMAs a CPU local operation, this should be called from non-preemptible context.h]hMAs a CPU local operation, this should be called from non-preemptible context.}(hjMhjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hj*ubeh}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjݔubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_get_irqchip_state (C function)c.irq_get_irqchip_statehNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hWint irq_get_irqchip_state (unsigned int irq, enum irqchip_irq_state which, bool *state)h]j])}(hVint irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool *state)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhM ubj)}(hirq_get_irqchip_stateh]j)}(hirq_get_irqchip_stateh]hirq_get_irqchip_state}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhM ubj)}(h=(unsigned int irq, enum irqchip_irq_state which, bool *state)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjΕhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjʕubju)}(h h]h }(hhhjܕhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjʕubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjʕubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjʕubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʕubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjƕubj)}(henum irqchip_irq_state whichh](j)}(hj h]henum}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhj,hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hhhj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj?modnameN classnameNjj)}j]j)}jjsbc.irq_get_irqchip_stateasbuh1hhjubju)}(h h]h }(hhhj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hwhichh]hwhich}(hhhjkhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjƕubj)}(h bool *stateh](jc)}(hj\Yh]hbool}(hhhj%hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hstateh]hstate}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjƕubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhM ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjhhubjH)}(hhh]jo)}(h)returns the irqchip state of a interrupt.h]h)returns the irqchip state of a interrupt.}(hjٖhjזhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjԖhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line that is forwarded to a VM ``enum irqchip_irq_state which`` One of IRQCHIP_STATE_* the caller wants to know about ``bool *state`` a pointer to a boolean where the state is to be stored This call snapshots the internal irqchip state of an interrupt, returning into **state** the bit corresponding to stage **which** This function should be called with preemption disabled if the interrupt controller has per-cpu registers.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh](j)}(h>``unsigned int irq`` Interrupt line that is forwarded to a VM h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh]jo)}(h(Interrupt line that is forwarded to a VMh]h(Interrupt line that is forwarded to a VM}(hj3hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj-hM hj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj-hM hjubj)}(hW``enum irqchip_irq_state which`` One of IRQCHIP_STATE_* the caller wants to know about h](j)}(h ``enum irqchip_irq_state which``h]j)}(hjQh]henum irqchip_irq_state which}(hhhjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjOubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjKubj)}(hhh]jo)}(h5One of IRQCHIP_STATE_* the caller wants to know abouth]h5One of IRQCHIP_STATE_* the caller wants to know about}(hjlhjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjfhM hjgubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jhjfhM hjubj)}(hX5``bool *state`` a pointer to a boolean where the state is to be stored This call snapshots the internal irqchip state of an interrupt, returning into **state** the bit corresponding to stage **which** This function should be called with preemption disabled if the interrupt controller has per-cpu registers.h](j)}(h``bool *state``h]j)}(hjh]h bool *state}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubj)}(hhh](jo)}(h6a pointer to a boolean where the state is to be storedh]h6a pointer to a boolean where the state is to be stored}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hThis call snapshots the internal irqchip state of an interrupt, returning into **state** the bit corresponding to stage **which**h](hOThis call snapshots the internal irqchip state of an interrupt, returning into }(hOThis call snapshots the internal irqchip state of an interrupt, returning into hjhhhNhNubjw)}(h **state**h]hstate}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubh the bit corresponding to stage }(h the bit corresponding to stage hjhhhNhNubjw)}(h **which**h]hwhich}(hhhjΗhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM hjubjo)}(hjThis function should be called with preemption disabled if the interrupt controller has per-cpu registers.h]hjThis function should be called with preemption disabled if the interrupt controller has per-cpu registers.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM"irq_set_irqchip_state (C function)c.irq_set_irqchip_statehNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hTint irq_set_irqchip_state (unsigned int irq, enum irqchip_irq_state which, bool val)h]j])}(hSint irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool val)h](jc)}(hinth]hint}(hhhj#hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM. ubju)}(h h]h }(hhhj2hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj1hM. ubj)}(hirq_set_irqchip_stateh]j)}(hirq_set_irqchip_stateh]hirq_set_irqchip_state}(hhhjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj1hM. ubj)}(h:(unsigned int irq, enum irqchip_irq_state which, bool val)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubjc)}(hinth]hint}(hhhj|hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj\ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj\ubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubj)}(henum irqchip_irq_state whichh](j)}(hj h]henum}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hhhjϘhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̘ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjјmodnameN classnameNjj)}j]j)}jjFsbc.irq_set_irqchip_stateasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hwhichh]hwhich}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubj)}(hbool valh](jc)}(hj\Yh]hbool}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hvalh]hval}(hhhj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjXubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj1hM. ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj1hM. ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM8 hjhhubjH)}(hhh]jo)}(h'set the state of a forwarded interrupt.h]h'set the state of a forwarded interrupt.}(hj^hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM- hjYhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj1hM. ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijtjjjtjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``unsigned int irq`` Interrupt line that is forwarded to a VM ``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) ``bool val`` Value corresponding to **which** This call sets the internal irqchip state of an interrupt, depending on the value of **which**. This function should be called with migration disabled if the interrupt controller has per-cpu registers.h](jo)}(h**Parameters**h]jw)}(hj~h]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj|ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM1 hjxubj)}(hhh](j)}(h>``unsigned int irq`` Interrupt line that is forwarded to a VM h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM. hjubj)}(hhh]jo)}(h(Interrupt line that is forwarded to a VMh]h(Interrupt line that is forwarded to a VM}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM. hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM. hjubj)}(hO``enum irqchip_irq_state which`` State to be restored (one of IRQCHIP_STATE_*) h](j)}(h ``enum irqchip_irq_state which``h]j)}(hj֙h]henum irqchip_irq_state which}(hhhjؙhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjԙubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM/ hjЙubj)}(hhh]jo)}(h-State to be restored (one of IRQCHIP_STATE_*)h]h-State to be restored (one of IRQCHIP_STATE_*)}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM/ hjubah}(h]h ]h"]h$]h&]uh1jhjЙubeh}(h]h ]h"]h$]h&]uh1jhjhM/ hjubj)}(h``bool val`` Value corresponding to **which** This call sets the internal irqchip state of an interrupt, depending on the value of **which**. This function should be called with migration disabled if the interrupt controller has per-cpu registers.h](j)}(h ``bool val``h]j)}(hjh]hbool val}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM5 hj ubj)}(hhh](jo)}(h Value corresponding to **which**h](hValue corresponding to }(hValue corresponding to hj(hhhNhNubjw)}(h **which**h]hwhich}(hhhj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj(ubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM0 hj%ubjo)}(h_This call sets the internal irqchip state of an interrupt, depending on the value of **which**.h](hUThis call sets the internal irqchip state of an interrupt, depending on the value of }(hUThis call sets the internal irqchip state of an interrupt, depending on the value of hjFhhhNhNubjw)}(h **which**h]hwhich}(hhhjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjFubh.}(hj5hjFhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM2 hj%ubjo)}(hiThis function should be called with migration disabled if the interrupt controller has per-cpu registers.h]hiThis function should be called with migration disabled if the interrupt controller has per-cpu registers.}(hjjhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj$hM5 hj%ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj$hM5 hjubeh}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_has_action (C function)c.irq_has_actionhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h&bool irq_has_action (unsigned int irq)h]j])}(h%bool irq_has_action(unsigned int irq)h](jc)}(hj\Yh]hbool}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMa ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMa ubj)}(hirq_has_actionh]j)}(hirq_has_actionh]hirq_has_action}(hhhjȚhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĚubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMa ubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjܚubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMa ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMa ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMe hjhhubjH)}(hhh]jo)}(h'Check whether an interrupt is requestedh]h'Check whether an interrupt is requested}(hjIhjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chM` hjDhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMa ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij_jjj_jkuh1jQhhhj"YhNhNubjm)}(hh**Parameters** ``unsigned int irq`` The linux irq number **Return** A snapshot of the current stateh](jo)}(h**Parameters**h]jw)}(hjih]h Parameters}(hhhjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjgubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMd hjcubj)}(hhh]j)}(h*``unsigned int irq`` The linux irq number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMa hjubj)}(hhh]jo)}(hThe linux irq numberh]hThe linux irq number}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMa hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMa hjubah}(h]h ]h"]h$]h&]uh1jhjcubjo)}(h **Return**h]jw)}(hjÛh]hReturn}(hhhjśhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMc hjcubjo)}(hA snapshot of the current stateh]hA snapshot of the current state}(hjۛhjٛhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMc hjcubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_check_status_bit (C function)c.irq_check_status_bithNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hBbool irq_check_status_bit (unsigned int irq, unsigned int bitmask)h]j])}(hAbool irq_check_status_bit(unsigned int irq, unsigned int bitmask)h](jc)}(hj\Yh]hbool}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMr ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMr ubj)}(hirq_check_status_bith]j)}(hirq_check_status_bith]hirq_check_status_bit}(hhhj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj$ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMr ubj)}(h((unsigned int irq, unsigned int bitmask)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjDhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj@ubju)}(h h]h }(hhhjRhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@ubjc)}(hinth]hint}(hhhj`hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj@ubju)}(h h]h }(hhhjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj@ubj)}(hirqh]hirq}(hhhj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj<ubj)}(hunsigned int bitmaskh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hbitmaskh]hbitmask}(hhhj͜hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj<ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMr ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMr ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMw hjhhubjH)}(hhh]jo)}(h7Check whether bits in the irq descriptor status are seth]h7Check whether bits in the irq descriptor status are set}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMq hjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMr ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``unsigned int irq`` The linux irq number ``unsigned int bitmask`` The bitmask to evaluate **Return** True if one of the bits in **bitmask** is seth](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMu hjubj)}(hhh](j)}(h*``unsigned int irq`` The linux irq number h](j)}(h``unsigned int irq``h]j)}(hj9h]hunsigned int irq}(hhhj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7ubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMr hj3ubj)}(hhh]jo)}(hThe linux irq numberh]hThe linux irq number}(hjThjRhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjNhMr hjOubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjNhMr hj0ubj)}(h1``unsigned int bitmask`` The bitmask to evaluate h](j)}(h``unsigned int bitmask``h]j)}(hjrh]hunsigned int bitmask}(hhhjthhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMs hjlubj)}(hhh]jo)}(hThe bitmask to evaluateh]hThe bitmask to evaluate}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMs hjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjhMs hj0ubeh}(h]h ]h"]h$]h&]uh1jhjubjo)}(h **Return**h]jw)}(hjh]hReturn}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:503: ./kernel/irq/manage.chMu hjubjo)}(h-True if one of the bits in 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irq_chip *chip)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjChhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj?ubju)}(h h]h }(hhhjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj?ubjc)}(hinth]hint}(hhhj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj?ubju)}(h h]h }(hhhjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj?ubj)}(hirqh]hirq}(hhhj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj;ubj)}(hconst struct irq_chip *chiph](j)}(hjh]hconst}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_chiph]hirq_chip}(hhhj͞hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjʞubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjϞmodnameN classnameNjj)}j]j)}jj)sbc.irq_set_chipasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hchiph]hchip}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj;ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhK&ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhK&ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK)hjhhubjH)}(hhh]jo)}(hset the irq chip for an irqh]hset the irq chip for an irq}(hj5hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK%hj0hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhK&ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijKjjjKjkuh1jQhhhj"YhNhNubjm)}(h~**Parameters** ``unsigned int irq`` irq number ``const struct irq_chip *chip`` pointer to irq chip description structureh](jo)}(h**Parameters**h]jw)}(hjUh]h Parameters}(hhhjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjSubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK)hjOubj)}(hhh](j)}(h ``unsigned int irq`` irq number h](j)}(h``unsigned int irq``h]j)}(hjth]hunsigned int irq}(hhhjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK&hjnubj)}(hhh]jo)}(h irq numberh]h irq number}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhK&hjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhK&hjkubj)}(hI``const struct irq_chip *chip`` pointer to irq chip description structureh](j)}(h``const struct irq_chip *chip``h]j)}(hjh]hconst struct irq_chip *chip}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK(hjubj)}(hhh]jo)}(h)pointer to irq chip description structureh]h)pointer to irq chip description structure}(hjȟhjƟhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chK'hjßubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjŸhK(hjkubeh}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ] 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hardware, where no interrupt hardware control is necessary. h](j)}(h``struct irq_desc *desc``h]j)}(hjXh]hstruct irq_desc *desc}(hhhjZhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjRubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjshjqhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjnubjo)}(hSimple interrupts are either sent from a demultiplexing interrupt handler or come from hardware, where no interrupt hardware control is necessary.h]hSimple interrupts are either sent from a demultiplexing interrupt handler or come from hardware, where no interrupt hardware control is necessary.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjnubeh}(h]h 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]h"]h$]h&]entries](jM!handle_untracked_irq (C function)c.handle_untracked_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h1void handle_untracked_irq (struct irq_desc *desc)h]j])}(h0void handle_untracked_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM2ubju)}(h h]h }(hhhj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj!hM2ubj)}(hhandle_untracked_irqh]j)}(hhandle_untracked_irqh]hhandle_untracked_irq}(hhhj4hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj0ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj!hM2ubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjPhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubju)}(h h]h }(hhhj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjkubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjpmodnameN classnameNjj)}j]j)}jj6sbc.handle_untracked_irqasbuh1hhjLubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjLubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubj)}(hdesch]hdesc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjHubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj!hM2ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj hhhj!hM2ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM=hjhhubjH)}(hhh]jo)}(h!Simple and software-decoded IRQs.h]h!Simple and software-decoded IRQs.}(hj֧hjԧhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM1hjѧhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj!hM2ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq Untracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. IRQ's handled through here are not subjected to stats tracking, randomness, or spurious interrupt detection. **Note** Like handle_simple_irq, the caller is expected to handle the ack, clear, mask and unmask issues if necessary.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM5hjubj)}(hhh]j)}(hXh``struct irq_desc *desc`` the interrupt description structure for this irq Untracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. IRQ's handled through here are not subjected to stats tracking, randomness, or spurious interrupt detection. h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM8hjubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hj0hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM2hj+ubjo)}(hXUntracked interrupts are sent from a demultiplexing interrupt handler when the demultiplexer does not know which device it its multiplexed irq domain generated the interrupt. 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This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMphjubj)}(hhh]j)}(hX9``struct irq_desc *desc`` the interrupt description structure for this irq Level type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.h](j)}(h``struct irq_desc *desc``h]j)}(hjҩh]hstruct irq_desc *desc}(hhhjԩhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjЩubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMqhj̩ubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMmhjubjo)}(hLevel type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.h]hLevel type interrupts are active as long as the hardware line has the active level. This may require to mask the interrupt and unmask it after the associated handler has acknowledged the device, so the interrupt line is back to inactive.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMohjubeh}(h]h ]h"]h$]h&]uh1jhj̩ubeh}(h]h ]h"]h$]h&]uh1jhjhMqhjɩubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_fasteoi_irq (C function)c.handle_fasteoi_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h/void handle_fasteoi_irq (struct irq_desc *desc)h]j])}(h.void handle_fasteoi_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhj;hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj7hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjJhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj7hhhjIhMubj)}(hhandle_fasteoi_irqh]j)}(hhandle_fasteoi_irqh]hhandle_fasteoi_irq}(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjXubah}(h]h ](jjeh"]h$]h&]hhuh1jhj7hhhjIhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjxhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjtubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj^sbc.handle_fasteoi_irqasbuh1hhjtubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjtubj )}(hj h]h*}(hhhjĪhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubj)}(hdesch]hdesc}(hhhjѪhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjpubah}(h]h ]h"]h$]h&]hhuh1jhj7hhhjIhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj3hhhjIhMubah}(h]j.ah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj0hhubjH)}(hhh]jo)}(h'irq handler for transparent controllersh]h'irq handler for transparent controllers}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhj0hhhjIhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hXE**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq Only a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(hX+``struct irq_desc *desc`` the interrupt description structure for this irq Only a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](j)}(h``struct irq_desc *desc``h]j)}(hj=h]hstruct irq_desc *desc}(hhhj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj7ubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjXhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjSubjo)}(hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h]hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.}(hjghjehhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjSubeh}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjRhMhj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_fasteoi_nmi (C function)c.handle_fasteoi_nmihNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h/void handle_fasteoi_nmi (struct irq_desc *desc)h]j])}(h.void handle_fasteoi_nmi(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hhandle_fasteoi_nmih]j)}(hhandle_fasteoi_nmih]hhandle_fasteoi_nmi}(hhhjǫhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjëubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj߫ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj߫ubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjɫsbc.handle_fasteoi_nmiasbuh1hhj߫ubju)}(h h]h }(hhhj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj߫ubj )}(hj h]h*}(hhhj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj߫ubj)}(hdesch]hdesc}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj߫ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj۫ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(h#irq handler for NMI interrupt linesh]h#irq handler for NMI interrupt lines}(hjihjghhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjdhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq A simple NMI-safe handler, considering the restrictions from request_nmi. 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This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjìhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hIA simple NMI-safe handler, considering the restrictions from request_nmi.h]hIA simple NMI-safe handler, considering the restrictions from request_nmi.}(hjҬhjЬhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.h]hOnly a single callback will be issued to the chip: an ->eoi() call when the interrupt has been serviced. This enables support for modern forms of interrupt handlers, which handle the flow details in hardware, transparently.}(hjhj߬hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_edge_irq (C function)c.handle_edge_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h,void handle_edge_irq (struct irq_desc *desc)h]j])}(h+void handle_edge_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhj/hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj.hMubj)}(hhandle_edge_irqh]j)}(hhandle_edge_irqh]hhandle_edge_irq}(hhhjAhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj=ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj.hMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhj]hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubju)}(h h]h }(hhhjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjYubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhj{hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj}modnameN classnameNjj)}j]j)}jjCsbc.handle_edge_irqasbuh1hhjYubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjYubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubj)}(hdesch]hdesc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjUubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj.hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj.hMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(hedge type IRQ handlerh]hedge type IRQ handler}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjޭhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj.hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq Interrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM hjubj)}(hhh]j)}(hX``struct irq_desc *desc`` the interrupt description structure for this irq Interrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.h](j)}(h``struct irq_desc *desc``h]j)}(hj"h]hstruct irq_desc *desc}(hhhj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hj=hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj8ubjo)}(hXbInterrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.h]hXbInterrupt occurs on the falling and/or rising edge of a hardware signal. The occurrence is latched into the irq controller hardware and must be acked in order to be reenabled. After the ack another interrupt can happen on the same source even before the first one is handled by the associated event handler. If this happens it might be necessary to disable (mask) the interrupt depending on the controller hardware. This requires to reenable the interrupt inside of the loop which handles the interrupts which have arrived while the handler was running. If all pending interrupts are handled, the loop is left.}(hjLhjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj8ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj7hMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#handle_fasteoi_ack_irq (C function)c.handle_fasteoi_ack_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h3void handle_fasteoi_ack_irq (struct irq_desc *desc)h]j])}(h2void handle_fasteoi_ack_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hhandle_fasteoi_ack_irqh]j)}(hhandle_fasteoi_ack_irqh]hhandle_fasteoi_ack_irq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjȮhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĮubju)}(h h]h }(hhhjծhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjĮubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_fasteoi_ack_irqasbuh1hhjĮubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjĮubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĮubj)}(hdesch]hdesc}(hhhj!hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĮubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]j~ah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(hAirq handler for edge hierarchy stacked on transparent controllersh]hAirq handler for edge hierarchy stacked on transparent controllers}(hjNhjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjIhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijdjjjdjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.h](jo)}(h**Parameters**h]jw)}(hjnh]h Parameters}(hhhjphhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjlubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhubj)}(hhh]j)}(h``struct irq_desc *desc`` the interrupt description structure for this irq Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(h|Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.h]h|Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_ack() function called.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$handle_fasteoi_mask_irq (C function)c.handle_fasteoi_mask_irqhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h4void handle_fasteoi_mask_irq (struct irq_desc *desc)h]j])}(h3void handle_fasteoi_mask_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hhandle_fasteoi_mask_irqh]j)}(hhandle_fasteoi_mask_irqh]hhandle_fasteoi_mask_irq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhj3hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubju)}(h h]h }(hhhj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj/ubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjNubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjSmodnameN classnameNjj)}j]j)}jjsbc.handle_fasteoi_mask_irqasbuh1hhj/ubju)}(h h]h }(hhhjqhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj/ubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubj)}(hdesch]hdesc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj+ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(hBirq handler for level hierarchy stacked on transparent controllersh]hBirq handler for level hierarchy stacked on transparent controllers}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijϰjjjϰjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.h](jo)}(h**Parameters**h]jw)}(hjٰh]h Parameters}(hhhj۰hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjװubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjӰubj)}(hhh]j)}(h``struct irq_desc *desc`` the interrupt description structure for this irq Like handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh](jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hLike handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.h]hLike handle_fasteoi_irq(), but for use with hierarchy where the irq_chip also needs to have its ->irq_mask_ack() function called.}(hj"hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hMhjubah}(h]h ]h"]h$]h&]uh1jhjӰubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&irq_chip_set_parent_state (C function)c.irq_chip_set_parent_statehNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h]int irq_chip_set_parent_state (struct irq_data *data, enum irqchip_irq_state which, bool val)h]j])}(h\int irq_chip_set_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool val)h](jc)}(hinth]hint}(hhhjahhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj]hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjphhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj]hhhjohMubj)}(hirq_chip_set_parent_stateh]j)}(hirq_chip_set_parent_stateh]hirq_chip_set_parent_state}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj]hhhjohMubj)}(h?(struct irq_data *data, enum irqchip_irq_state which, bool val)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_set_parent_stateasbuh1hhjubju)}(h h]h }(hhhjܱhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(henum irqchip_irq_state whichh](j)}(hj h]henum}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hhhj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj0modnameN classnameNjj)}j]jرc.irq_chip_set_parent_stateasbuh1hhj ubju)}(h h]h }(hhhjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubj)}(hwhichh]hwhich}(hhhjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hbool valh](jc)}(hj\Yh]hbool}(hhhjshhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjoubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjoubj)}(hvalh]hval}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj]hhhjohMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjYhhhjohMubah}(h]jTah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM!hjVhhubjH)}(hhh]jo)}(h$set the state of a parent interrupt.h]h$set the state of a parent interrupt.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjVhhhjohMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijѲjjjѲjkuh1jQhhhj"YhNhNubjm)}(hX)**Parameters** ``struct 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whichh](j)}(hj h]henum}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirqchip_irq_stateh]hirqchip_irq_state}(hhhjȴhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjŴubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjʴmodnameN classnameNjj)}j]jrc.irq_chip_get_parent_stateasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hwhichh]hwhich}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0ubj)}(h bool *stateh](jc)}(hj\Yh]hbool}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj ubj )}(hj h]h*}(hhhj(hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubj)}(hstateh]hstate}(hhhj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj0ubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj hM0ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj hM0ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM7hjhhubjH)}(hhh]jo)}(h$get the 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}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj̶ubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̶ubj)}(hdatah]hdata}(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj̶ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjȶubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMFubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMFubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMIhjhhubjH)}(hhh]jo)}(h8Enable the parent interrupt (defaults to unmask if NULL)h]h8Enable the parent interrupt (defaults to unmask if NULL)}(hjVhjThhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMEhjQhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMFubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijljjjljkuh1jQhhhj"YhNhNubjm)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](jo)}(h**Parameters**h]jw)}(hjvh]h Parameters}(hhhjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjtubah}(h]h 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*data}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMZhjubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMVhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMZhjubah}(h]h ]h"]h$]h&]uh1jhj̸ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM irq_chip_ack_parent (C function)c.irq_chip_ack_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h0void irq_chip_ack_parent (struct irq_data *data)h]j])}(h/void irq_chip_ack_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hhhjKhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjGhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMdubju)}(h h]h }(hhhjZhhhNhNubah}(h]h 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interrupth]h Acknowledge the parent interrupt}(hjhj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMchj hhubah}(h]h ]h"]h$]h&]uh1jGhj@hhhjYhMdubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij$jjj$jkuh1jQhhhj"YhNhNubjm)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](jo)}(h**Parameters**h]jw)}(hj.h]h Parameters}(hhhj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj,ubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMghj(ubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjMh]hstruct irq_data *data}(hhhjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMihjGubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhhjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMdhjcubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jhjbhMihjDubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_chip_mask_parent (C function)c.irq_chip_mask_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h1void irq_chip_mask_parent (struct irq_data *data)h]j])}(h0void irq_chip_mask_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMoubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMoubj)}(hirq_chip_mask_parenth]j)}(hirq_chip_mask_parenth]hirq_chip_mask_parent}(hhhjȺhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjĺubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMoubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjʺsbc.irq_chip_mask_parentasbuh1hhjubju)}(h h]h }(hhhj"hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj0hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhj=hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjܺubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMoubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMoubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMqhjhhubjH)}(hhh]jo)}(hMask the parent interrupth]hMask the parent interrupt}(hjjhjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMnhjehhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMoubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMrhjubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMthjubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjĻhj»hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMohjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMthjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_mask_ack_parent (C function)c.irq_chip_mask_ack_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h5void irq_chip_mask_ack_parent (struct irq_data *data)h]j])}(h4void irq_chip_mask_ack_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMzubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMzubj)}(hirq_chip_mask_ack_parenth]j)}(hirq_chip_mask_ack_parenth]hirq_chip_mask_ack_parent}(hhhj$hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMzubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhj@hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubju)}(h h]h }(hhhjMhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<ubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj`modnameN classnameNjj)}j]j)}jj&sbc.irq_chip_mask_ack_parentasbuh1hhj<ubju)}(h h]h }(hhhj~hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj<ubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubj)}(hdatah]hdata}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj8ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMzubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMzubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM|hjhhubjH)}(hhh]jo)}(h)Mask and acknowledge the parent interrupth]h)Mask and acknowledge the parent interrupt}(hjƼhjļhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMyhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMzubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijܼjjjܼjkuh1jQhhhj"YhNhNubjm)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chM}hjubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMzhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM#irq_chip_unmask_parent (C function)c.irq_chip_unmask_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h3void irq_chip_unmask_parent (struct irq_data *data)h]j])}(h2void irq_chip_unmask_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hhhj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj[hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjnhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[hhhjmhMubj)}(hirq_chip_unmask_parenth]j)}(hirq_chip_unmask_parenth]hirq_chip_unmask_parent}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj|ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj[hhhjmhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_chip_unmask_parentasbuh1hhjubju)}(h h]h }(hhhjڽhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhj[hhhjmhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjWhhhjmhMubah}(h]jRah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjThhubjH)}(hhh]jo)}(hUnmask the parent interrupth]hUnmask the parent interrupt}(hj"hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjThhhjmhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij8jjj8jkuh1jQhhhj"YhNhNubjm)}(hN**Parameters** ``struct irq_data *data`` Pointer to interrupt specific datah](jo)}(h**Parameters**h]jw)}(hjBh]h Parameters}(hhhjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj@ubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj<ubj)}(hhh]j)}(h<``struct irq_data *data`` Pointer to interrupt specific datah](j)}(h``struct irq_data *data``h]j)}(hjah]hstruct irq_data *data}(hhhjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj[ubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hj|hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjwubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jhjvhMhjXubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM irq_chip_eoi_parent (C function)c.irq_chip_eoi_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h0void irq_chip_eoi_parent (struct irq_data *data)h]j])}(h/void irq_chip_eoi_parent(struct irq_data *data)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjʾhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjɾhMubj)}(hirq_chip_eoi_parenth]j)}(hirq_chip_eoi_parenth]hirq_chip_eoi_parent}(hhhjܾhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjؾubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjɾhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj޾sbc.irq_chip_eoi_parentasbuh1hhjubju)}(h h]h }(hhhj6hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjDhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjɾhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjɾhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(h"Invoke EOI on the parent interrupth]h"Invoke EOI on the parent interrupt}(hj~hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjyhhubah}(h]h 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kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM)irq_chip_set_affinity_parent (C function)c.irq_chip_set_affinity_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h`int irq_chip_set_affinity_parent (struct irq_data *data, const struct cpumask *dest, bool force)h]j])}(h_int irq_chip_set_affinity_parent(struct irq_data *data, const struct cpumask *dest, bool force)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj%hMubj)}(hirq_chip_set_affinity_parenth]j)}(hirq_chip_set_affinity_parenth]hirq_chip_set_affinity_parent}(hhhj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj%hMubj)}(h?(struct irq_data *data, const struct cpumask *dest, bool force)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubju)}(h h]h }(hhhjahhhNhNubah}(h]h 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]jah"]h$]h&]uh1jhjubj)}(hdesth]hdest}(hhhj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubj)}(h bool forceh](jc)}(hj\Yh]hbool}(hhhjQhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjMubju)}(h h]h }(hhhj^hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjMubj)}(hforceh]hforce}(hhhjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj%hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj%hMubah}(h]j ah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhj hhubjH)}(hhh]jo)}(h$Set affinity on the parent interrupth]h$Set affinity on the parent interrupt}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhj hhhj%hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(hX **Parameters** ``struct irq_data *data`` Pointer to interrupt specific data ``const struct cpumask *dest`` The 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]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hBConditional, as the underlying parent chip might not implement it.h]hBConditional, as the underlying parent chip might not implement it.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM%irq_chip_set_type_parent (C function)c.irq_chip_set_type_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hGint irq_chip_set_type_parent (struct irq_data *data, unsigned int type)h]j])}(hFint irq_chip_set_type_parent(struct irq_data *data, unsigned int type)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_set_type_parenth]j)}(hirq_chip_set_type_parenth]hirq_chip_set_type_parent}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h*(struct irq_data *data, unsigned int type)h](j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhj%hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj'modnameN classnameNjj)}j]j)}jjsbc.irq_chip_set_type_parentasbuh1hhjubju)}(h h]h }(hhhjEhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjShhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int typeh](jc)}(hunsignedh]hunsigned}(hhhjyhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjuubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjuubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h 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value - see include/linux/irq.hh]h7IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h}(hjqhjohhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjkhMhjlubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhjkhMhjubeh}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hBConditional, as the underlying parent chip might not implement it.h]hBConditional, as the underlying parent chip might not implement it.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM)irq_chip_retrigger_hierarchy (C function)c.irq_chip_retrigger_hierarchyhNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(h8int irq_chip_retrigger_hierarchy (struct irq_data *data)h]j])}(h7int irq_chip_retrigger_hierarchy(struct irq_data *data)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hirq_chip_retrigger_hierarchyh]j)}(hirq_chip_retrigger_hierarchyh]hirq_chip_retrigger_hierarchy}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(struct irq_data *data)h]j)}(hstruct irq_data *datah](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_datah]hirq_data}(hhhj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj.ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj3modnameN classnameNjj)}j]j)}jjsbc.irq_chip_retrigger_hierarchyasbuh1hhjubju)}(h h]h }(hhhjQhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj_hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdatah]hdata}(hhhjlhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj ubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubjH)}(hhh]jo)}(h"Retrigger an interrupt in hardwareh]h"Retrigger an interrupt in hardware}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhj"YhNhNubjm)}(h**Parameters** ``struct irq_data *data`` Pointer to interrupt specific data **Description** Iterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh]j)}(h=``struct irq_data *data`` Pointer to interrupt specific data h](j)}(h``struct irq_data *data``h]j)}(hjh]hstruct irq_data *data}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubj)}(hhh]jo)}(h"Pointer to interrupt specific datah]h"Pointer to interrupt specific data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubjo)}(hzIterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.h]hzIterate through the domain hierarchy of the interrupt and check whether a hw retrigger function exists. If yes, invoke it.}(hj+hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhj"YhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM.irq_chip_set_vcpu_affinity_parent (C function)#c.irq_chip_set_vcpu_affinity_parenthNtauh1j@hj"YhhhNhNubjR)}(hhh](jW)}(hNint irq_chip_set_vcpu_affinity_parent (struct irq_data *data, void *vcpu_info)h]j])}(hMint irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)h](jc)}(hinth]hint}(hhhjXhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjThhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:505: ./kernel/irq/chip.chMubju)}(h h]h }(hhhjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjThhhjfhMubj)}(h!irq_chip_set_vcpu_affinity_parenth]j)}(h!irq_chip_set_vcpu_affinity_parenth]h!irq_chip_set_vcpu_affinity_parent}(hhhjyhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjuubah}(h]h ](jjeh"]h$]h&]hhuh1jhjThhhjfhMubj)}(h((struct irq_data *data, void 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]h"]h$]h&]uh1jhjubjo)}(h **Return**h]jw)}(hj6h]hReturn}(hhhj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj4ubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubjo)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hjNhjLhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubjZ)}(hhh]jo)}(hKThis function must be called from an IRQ context with irq regs initialized.h]hKThis function must be called from an IRQ context with irq regs initialized.}(hj`hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj[ubah}(h]h ]h"]h$]h&]uh1jZhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM$generic_handle_irq_safe (C function)c.generic_handle_irq_safehNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h.int generic_handle_irq_safe (unsigned int irq)h]j])}(h-int generic_handle_irq_safe(unsigned int irq)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hgeneric_handle_irq_safeh]j)}(hgeneric_handle_irq_safeh]hgeneric_handle_irq_safe}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(unsigned int irq)h]j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjhhubjH)}(hhh]jo)}(h9Invoke the handler for a particular irq from any context.h]h9Invoke the handler for a particular irq from any context.}(hj5hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj0hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijKjjjKjkuh1jQhhhjhNhNubjm)}(hX?**Parameters** ``unsigned int irq`` The irq number to handle **Return** 0 on success, a negative value on error. **Description** This function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.h](jo)}(h**Parameters**h]jw)}(hjUh]h Parameters}(hhhjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjSubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjOubj)}(hhh]j)}(h.``unsigned int irq`` The irq number to handle h](j)}(h``unsigned int irq``h]j)}(hjth]hunsigned int irq}(hhhjvhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjnubj)}(hhh]jo)}(hThe irq number to handleh]hThe irq number to handle}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjhMhjkubah}(h]h ]h"]h$]h&]uh1jhjOubjo)}(h **Return**h]jw)}(hjh]hReturn}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjOubjo)}(h(0 on success, a negative value on error.h]h(0 on success, a negative value on error.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjOubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjOubjo)}(hThis function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.h]hThis function can be called from any context (IRQ or process context). It will report an error if not invoked from IRQ context and the irq has been marked to enforce IRQ-context only.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjOubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&generic_handle_domain_irq (C function)c.generic_handle_domain_irqhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(hMint generic_handle_domain_irq (struct irq_domain *domain, unsigned int hwirq)h]j])}(hLint generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hhhj*hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj)hMubj)}(hgeneric_handle_domain_irqh]j)}(hgeneric_handle_domain_irqh]hgeneric_handle_domain_irq}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj8ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj)hMubj)}(h/(struct irq_domain *domain, unsigned int hwirq)h](j)}(hstruct irq_domain *domainh](j)}(hjh]hstruct}(hhhjXhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubju)}(h h]h }(hhhjehhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjTubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hhhjvhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjxmodnameN classnameNjj)}j]j)}jj>sbc.generic_handle_domain_irqasbuh1hhjTubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjTubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubj)}(hdomainh]hdomain}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjPubj)}(hunsigned int hwirqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhwirqh]hhwirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjPubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj)hMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj)hMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjhhubjH)}(hhh]jo)}(h6Invoke the handler for a HW irq belonging to a domain.h]h6Invoke the handler for a HW irq belonging to a domain.}(hj/hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj*hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj)hMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijEjjjEjkuh1jQhhhjhNhNubjm)}(hXD**Parameters** ``struct irq_domain *domain`` The domain where to perform the lookup ``unsigned int hwirq`` The HW irq number to convert to a logical one **Return** 0 on success, or -EINVAL if conversion has failed This function must be called from an IRQ context with irq regs initialized.h](jo)}(h**Parameters**h]jw)}(hjOh]h Parameters}(hhhjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjMubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjIubj)}(hhh](j)}(hE``struct irq_domain *domain`` The domain where to perform the lookup h](j)}(h``struct irq_domain *domain``h]j)}(hjnh]hstruct irq_domain *domain}(hhhjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjhubj)}(hhh]jo)}(h&The domain where to perform the lookuph]h&The domain where to perform the lookup}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubj)}(hE``unsigned int hwirq`` The HW irq number to convert to a logical one h](j)}(h``unsigned int hwirq``h]j)}(hjh]hunsigned int hwirq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubj)}(hhh]jo)}(h-The HW irq number to convert to a logical oneh]h-The HW irq number to convert to a logical one}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjeubeh}(h]h ]h"]h$]h&]uh1jhjIubjo)}(h **Return**h]jw)}(hjh]hReturn}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjIubjo)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjIubjZ)}(hhh]jo)}(hKThis function must be called from an IRQ context with irq regs initialized.h]hKThis function must be called from an IRQ context with irq regs initialized.}(hj hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubah}(h]h ]h"]h$]h&]uh1jZhjIubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM&generic_handle_domain_nmi (C function)c.generic_handle_domain_nmihNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(hMint generic_handle_domain_nmi (struct irq_domain *domain, unsigned int hwirq)h]j])}(hLint generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq)h](jc)}(hinth]hint}(hhhj?hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj;hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM ubju)}(h h]h }(hhhjNhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj;hhhjMhM ubj)}(hgeneric_handle_domain_nmih]j)}(hgeneric_handle_domain_nmih]hgeneric_handle_domain_nmi}(hhhj`hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj\ubah}(h]h ](jjeh"]h$]h&]hhuh1jhj;hhhjMhM ubj)}(h/(struct irq_domain *domain, unsigned int hwirq)h](j)}(hstruct irq_domain *domainh](j)}(hjh]hstruct}(hhhj|hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjxubh)}(hhh]j)}(h irq_domainh]h irq_domain}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjbsbc.generic_handle_domain_nmiasbuh1hhjxubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjxubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubj)}(hdomainh]hdomain}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubj)}(hunsigned int hwirqh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hhwirqh]hhwirq}(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjtubeh}(h]h ]h"]h$]h&]hhuh1jhj;hhhjMhM ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj7hhhjMhM ubah}(h]j2ah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj4hhubjH)}(hhh]jo)}(h6Invoke the handler for a HW nmi belonging to a domain.h]h6Invoke the handler for a HW nmi belonging to a domain.}(hjShjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjNhhubah}(h]h ]h"]h$]h&]uh1jGhj4hhhjMhM ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijijjjijkuh1jQhhhjhNhNubjm)}(hXD**Parameters** ``struct irq_domain *domain`` The domain where to perform the lookup ``unsigned int hwirq`` The HW irq number to convert to a logical one **Return** 0 on success, or -EINVAL if conversion has failed This function must be called from an NMI context with irq regs initialized.h](jo)}(h**Parameters**h]jw)}(hjsh]h Parameters}(hhhjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjqubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjmubj)}(hhh](j)}(hE``struct irq_domain *domain`` The domain where to perform the lookup h](j)}(h``struct irq_domain *domain``h]j)}(hjh]hstruct irq_domain *domain}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjubj)}(hhh]jo)}(h&The domain where to perform the lookuph]h&The domain where to perform the lookup}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubj)}(hE``unsigned int hwirq`` The HW irq number to convert to a logical one h](j)}(h``unsigned int hwirq``h]j)}(hjh]hunsigned int hwirq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjubj)}(hhh]jo)}(h-The HW irq number to convert to a logical oneh]h-The HW irq number to convert to a logical one}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM hjubeh}(h]h ]h"]h$]h&]uh1jhjmubjo)}(h **Return**h]jw)}(hjh]hReturn}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjmubjo)}(h10 on success, or -EINVAL if conversion has failedh]h10 on success, or -EINVAL if conversion has failed}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjmubjZ)}(hhh]jo)}(hKThis function must be called from an NMI context with irq regs initialized.h]hKThis function must be called from an NMI context with irq regs initialized.}(hj0hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj+ubah}(h]h ]h"]h$]h&]uh1jZhjmubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_free_descs (C function)c.irq_free_descshNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h9void irq_free_descs (unsigned int from, unsigned int cnt)h]j])}(h8void irq_free_descs(unsigned int from, unsigned int cnt)h](jc)}(hvoidh]hvoid}(hhhjchhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj_hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hhhjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj_hhhjqhMubj)}(hirq_free_descsh]j)}(hirq_free_descsh]hirq_free_descs}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhj_hhhjqhMubj)}(h%(unsigned int from, unsigned int cnt)h](j)}(hunsigned int fromh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hfromh]hfrom}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int cnth](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhj hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hcnth]hcnt}(hhhj)hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhj_hhhjqhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj[hhhjqhMubah}(h]jVah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjXhhubjH)}(hhh]jo)}(hfree irq descriptorsh]hfree irq descriptors}(hjVhjThhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjQhhubah}(h]h ]h"]h$]h&]uh1jGhjXhhhjqhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijljjjljkuh1jQhhhjhNhNubjm)}(h|**Parameters** ``unsigned int from`` Start of descriptor range ``unsigned int cnt`` Number of consecutive irqs to freeh](jo)}(h**Parameters**h]jw)}(hjvh]h Parameters}(hhhjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjtubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM hjpubj)}(hhh](j)}(h0``unsigned int from`` Start of descriptor range h](j)}(h``unsigned int from``h]j)}(hjh]hunsigned int from}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubj)}(hhh]jo)}(hStart of descriptor rangeh]hStart of descriptor range}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubj)}(h7``unsigned int cnt`` Number of consecutive irqs to freeh](j)}(h``unsigned int cnt``h]j)}(hjh]hunsigned int cnt}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubj)}(hhh]jo)}(h"Number of consecutive irqs to freeh]h"Number of consecutive irqs to free}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMhjubeh}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM__irq_alloc_descs (C function)c.__irq_alloc_descshNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(hint __ref __irq_alloc_descs (int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h]j])}(hint __ref __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h](jc)}(hinth]hint}(hhhj(hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj$hhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM1ubju)}(h h]h }(hhhj7hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$hhhj6hM1ubh__ref}(hhhj$hhhNhNubju)}(h h]h }(hhhjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj$hhhj6hM1ubj)}(h__irq_alloc_descsh]j)}(h__irq_alloc_descsh]h__irq_alloc_descs}(hhhj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubah}(h]h ](jjeh"]h$]h&]hhuh1jhj$hhhj6hM1ubj)}(hx(int irq, unsigned int from, unsigned int cnt, int node, struct module *owner, const struct irq_affinity_desc *affinity)h](j)}(hint irqh](jc)}(hinth]hint}(hhhjwhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjsubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjsubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubj)}(hunsigned int fromh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hfromh]hfrom}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubj)}(hunsigned int cnth](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj'hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hcnth]hcnt}(hhhj5hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubj)}(hint nodeh](jc)}(hinth]hint}(hhhjNhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjJubju)}(h h]h }(hhhj\hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjJubj)}(hnodeh]hnode}(hhhjjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubj)}(hstruct module *ownerh](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hmoduleh]hmodule}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jj]sbc.__irq_alloc_descsasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hownerh]howner}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubj)}(h(const struct irq_affinity_desc *affinityh](j)}(hjh]hconst}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_affinity_desch]hirq_affinity_desc}(hhhj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetj0modnameN classnameNjj)}j]jc.__irq_alloc_descsasbuh1hhjubju)}(h h]h }(hhhjLhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjZhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(haffinityh]haffinity}(hhhjghhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjoubeh}(h]h ]h"]h$]h&]hhuh1jhj$hhhj6hM1ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj hhhj6hM1ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM<hjhhubjH)}(hhh]jo)}(h2allocate and initialize a range of irq descriptorsh]h2allocate and initialize a range of irq descriptors}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM0hjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj6hM1ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhjhNhNubjm)}(hXZ**Parameters** ``int irq`` Allocate for specific irq number if irq >= 0 ``unsigned int from`` Start the search from this irq number ``unsigned int cnt`` Number of consecutive irqs to allocate. ``int node`` Preferred node on which the irq descriptor should be allocated ``struct module *owner`` Owning module (can be NULL) ``const struct irq_affinity_desc *affinity`` Optional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to use **Description** Returns the first irq number or error codeh](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM4hjubj)}(hhh](j)}(h9``int irq`` Allocate for specific irq number if irq >= 0 h](j)}(h ``int irq``h]j)}(hjh]hint irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM1hjubj)}(hhh]jo)}(h,Allocate for specific irq number if irq >= 0h]h,Allocate for specific irq number if irq >= 0}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM1hjubj)}(h<``unsigned int from`` Start the search from this irq number h](j)}(h``unsigned int from``h]j)}(hj h]hunsigned int from}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM2hjubj)}(hhh]jo)}(h%Start the search from this irq numberh]h%Start the search from this irq number}(hj'hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj!hM2hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj!hM2hjubj)}(h=``unsigned int cnt`` Number of consecutive irqs to allocate. h](j)}(h``unsigned int cnt``h]j)}(hjEh]hunsigned int cnt}(hhhjGhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjCubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM3hj?ubj)}(hhh]jo)}(h'Number of consecutive irqs to allocate.h]h'Number of consecutive irqs to allocate.}(hj`hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjZhM3hj[ubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjZhM3hjubj)}(hL``int node`` Preferred node on which the irq descriptor should be allocated h](j)}(h ``int node``h]j)}(hj~h]hint node}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM4hjxubj)}(hhh]jo)}(h>Preferred node on which the irq descriptor should be allocatedh]h>Preferred node on which the irq descriptor should be allocated}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM4hjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jhjhM4hjubj)}(h5``struct module *owner`` Owning module (can be NULL) h](j)}(h``struct module *owner``h]j)}(hjh]hstruct module *owner}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM5hjubj)}(hhh]jo)}(hOwning module (can be NULL)h]hOwning module (can be NULL)}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM5hjubj)}(h``const struct irq_affinity_desc *affinity`` Optional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to use h](j)}(h,``const struct irq_affinity_desc *affinity``h]j)}(hjh]h(const struct irq_affinity_desc *affinity}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM8hjubj)}(hhh]jo)}(hOptional pointer to an affinity mask array of size **cnt** which hints where the irq descriptors should be allocated and which default affinities to useh](h3Optional pointer to an affinity mask array of size }(h3Optional pointer to an affinity mask array of size hj hhhNhNubjw)}(h**cnt**h]hcnt}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj ubh^ which hints where the irq descriptors should be allocated and which default affinities to use}(h^ which hints where the irq descriptors should be allocated and which default affinities to usehj hhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhM8hjubeh}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hj@h]h Description}(hhhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj>ubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM:hjubjo)}(h*Returns the first irq number or error codeh]h*Returns the first irq number or error code}(hjXhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chM:hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_get_next_irq (C function)c.irq_get_next_irqhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h3unsigned int irq_get_next_irq (unsigned int offset)h]j])}(h2unsigned int irq_get_next_irq(unsigned int offset)h](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMgubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMgubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhjhMgubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMgubj)}(hirq_get_next_irqh]j)}(hirq_get_next_irqh]hirq_get_next_irq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMgubj)}(h(unsigned int offset)h]j)}(hunsigned int offseth](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hoffseth]hoffset}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMgubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj}hhhjhMgubah}(h]jxah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMkhjzhhubjH)}(hhh]jo)}(hget next allocated irq numberh]hget next allocated irq number}(hjChjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMfhj>hhubah}(h]h ]h"]h$]h&]uh1jGhjzhhhjhMgubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijYjjjYjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``unsigned int offset`` where to start the search **Description** Returns next irq number after offset or nr_irqs if none is found.h](jo)}(h**Parameters**h]jw)}(hjch]h Parameters}(hhhjehhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjaubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMjhj]ubj)}(hhh]j)}(h2``unsigned int offset`` where to start the search h](j)}(h``unsigned int offset``h]j)}(hjh]hunsigned int offset}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMghj|ubj)}(hhh]jo)}(hwhere to start the searchh]hwhere to start the search}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMghjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jhjhMghjyubah}(h]h ]h"]h$]h&]uh1jhj]ubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMihj]ubjo)}(hAReturns next irq number after offset or nr_irqs if none is found.h]hAReturns next irq number after offset or nr_irqs if none is found.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMihj]ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMkstat_irqs_cpu (C function)c.kstat_irqs_cpuhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h7unsigned int kstat_irqs_cpu (unsigned int irq, int cpu)h]j])}(h6unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)h](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhjhMubju)}(h h]h }(hhhj-hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMubj)}(hkstat_irqs_cpuh]j)}(hkstat_irqs_cpuh]hkstat_irqs_cpu}(hhhj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj;ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMubj)}(h(unsigned int irq, int cpu)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj[hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjWubju)}(h h]h }(hhhjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubjc)}(hinth]hint}(hhhjwhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjWubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjWubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjSubj)}(hint cpuh](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hcpuh]hcpu}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjSubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjhhubjH)}(hhh]jo)}(h,Get the statistics for an interrupt on a cpuh]h,Get the statistics for an interrupt on a cpu}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij jjj jkuh1jQhhhjhNhNubjm)}(h**Parameters** ``unsigned int irq`` The interrupt number ``int cpu`` The cpu number **Description** Returns the sum of interrupt counts on **cpu** since boot for **irq**. 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It uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubj)}(hhh]j)}(h*``unsigned int irq`` The interrupt number h](j)}(h``unsigned int irq``h]j)}(hjh]hunsigned int irq}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhj ubj)}(hhh]jo)}(hThe interrupt numberh]hThe interrupt number}(hj,hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj&hMhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj&hMhjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjLh]h Description}(hhhjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjJubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubjo)}(hGReturns the sum of interrupt counts on all cpus since boot for **irq**.h](h?Returns the sum of interrupt counts on all cpus since boot for }(h?Returns the sum of interrupt counts on all cpus since boot for hjbhhhNhNubjw)}(h**irq**h]hirq}(hhhjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjbubh.}(hj5hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubjo)}(hIt uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().h]hIt uses rcu to protect the access since a concurrent removal of an interrupt descriptor is observing an rcu grace period before delayed_free_desc()/irq_kobj_release().}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhY/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:514: ./kernel/irq/irqdesc.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_bad_irq (C function)c.handle_bad_irqhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h+void handle_bad_irq (struct irq_desc *desc)h]j])}(h*void handle_bad_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKubj)}(hhandle_bad_irqh]j)}(hhandle_bad_irqh]hhandle_bad_irq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_bad_irqasbuh1hhjubju)}(h h]h }(hhhj.hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj<hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hhhjIhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chK!hjhhubjH)}(hhh]jo)}(h"handle spurious and unhandled irqsh]h"handle spurious and unhandled irqs}(hjvhjthhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhjqhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``struct irq_desc *desc`` description of the interrupt **Description** Handles spurious and unhandled IRQ's. It also prints a debugmessage.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chK hjubj)}(hhh]j)}(h7``struct irq_desc *desc`` description of the interrupt h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhjubj)}(hhh]jo)}(hdescription of the interrupth]hdescription of the interrupt}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhjubjo)}(hDHandles spurious and unhandled IRQ's. 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*regsh](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hpt_regsh]hpt_regs}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjjsbc.generic_handle_arch_irqasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hregsh]hregs}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhj|ubah}(h]h ]h"]h$]h&]hhuh1jhj1hhhjChKubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hj-hhhjChKubah}(h]j(ah ](j@jAeh"]h$]h&]jEuh1jVhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhj*hhubjH)}(hhh]jo)}(hJroot irq handler for architectures which do no entry accounting themselvesh]hJroot irq handler for architectures which do no entry accounting themselves}(hj hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhjhhubah}(h]h ]h"]h$]h&]uh1jGhj*hhhjChKubeh}(h]h ](jY functioneh"]h$]h&]jhjY jij jjj jkuh1jQhhhjhNhNubjm)}(h`**Parameters** ``struct pt_regs *regs`` Register file coming from the low-level handling codeh](jo)}(h**Parameters**h]jw)}(hj*h]h Parameters}(hhhj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj(ubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhj$ubj)}(hhh]j)}(hN``struct pt_regs *regs`` Register file coming from the low-level handling codeh](j)}(h``struct pt_regs *regs``h]j)}(hjIh]hstruct pt_regs *regs}(hhhjKhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjGubah}(h]h ]h"]h$]h&]uh1jhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhjCubj)}(hhh]jo)}(h5Register file coming from the low-level handling codeh]h5Register file coming from the low-level handling code}(hjdhjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhX/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:516: ./kernel/irq/handle.chKhj_ubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jhj^hKhj@ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM!irq_set_msi_desc_off (C function)c.irq_set_msi_desc_offhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(haint irq_set_msi_desc_off (unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h]j])}(h`int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h](jc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKfubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhKfubj)}(hirq_set_msi_desc_offh]j)}(hirq_set_msi_desc_offh]hirq_set_msi_desc_off}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhKfubj)}(hH(unsigned int irq_base, unsigned int irq_offset, struct msi_desc *entry)h](j)}(hunsigned int irq_baseh](jc)}(hunsignedh]hunsigned}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubjc)}(hinth]hint}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjubju)}(h h]h }(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj)}(hirq_baseh]hirq_base}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hunsigned int irq_offseth](jc)}(hunsignedh]hunsigned}(hhhj1hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj-ubju)}(h h]h }(hhhj?hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj-ubjc)}(hinth]hint}(hhhjMhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj-ubju)}(h h]h }(hhhj[hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj-ubj)}(h irq_offseth]h irq_offset}(hhhjihhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubj)}(hstruct msi_desc *entryh](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~ubh)}(hhh]j)}(hmsi_desch]hmsi_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.irq_set_msi_desc_offasbuh1hhj~ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj~ubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubj)}(hentryh]hentry}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhjhKfubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhKfubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKlhjhhubjH)}(hhh]jo)}(h,set MSI descriptor data for an irq at offseth]h,set MSI descriptor data for an irq at offset}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKehjhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhKfubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``unsigned int irq_base`` Interrupt number base ``unsigned int irq_offset`` Interrupt number offset ``struct msi_desc *entry`` Pointer to MSI descriptor data Set the MSI descriptor entry for an irq at offseth](jo)}(h**Parameters**h]jw)}(hj(h]h Parameters}(hhhj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jvhj&ubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKihj"ubj)}(hhh](j)}(h0``unsigned int irq_base`` Interrupt number base h](j)}(h``unsigned int irq_base``h]j)}(hjGh]hunsigned int irq_base}(hhhjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjEubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKfhjAubj)}(hhh]jo)}(hInterrupt number baseh]hInterrupt number base}(hjbhj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj\hKfhj]ubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jhj\hKfhj>ubj)}(h4``unsigned int irq_offset`` Interrupt number offset h](j)}(h``unsigned int irq_offset``h]j)}(hjh]hunsigned int irq_offset}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKghjzubj)}(hhh]jo)}(hInterrupt number offseth]hInterrupt number offset}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhKghjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jhjhKghj>ubj)}(hl``struct msi_desc *entry`` Pointer to MSI descriptor data Set the MSI descriptor entry for an irq at offseth](j)}(h``struct msi_desc *entry``h]j)}(hjh]hstruct msi_desc *entry}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKihjubj)}(hhh](jo)}(hPointer to MSI descriptor datah]hPointer to MSI descriptor data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKhhjubjo)}(h1Set the MSI descriptor entry for an irq at offseth]h1Set the MSI descriptor entry for an irq at offset}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKjhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKihj>ubeh}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_set_msi_desc (C function)c.irq_set_msi_deschNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h?int irq_set_msi_desc (unsigned int irq, struct msi_desc *entry)h]j])}(h>int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)h](jc)}(hinth]hint}(hhhj"hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chK}ubju)}(h h]h }(hhhj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj0hK}ubj)}(hirq_set_msi_desch]j)}(hirq_set_msi_desch]hirq_set_msi_desc}(hhhjChhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj?ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj0hK}ubj)}(h*(unsigned int irq, struct msi_desc *entry)h](j)}(hunsigned int irqh](jc)}(hunsignedh]hunsigned}(hhhj_hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj[ubju)}(h h]h }(hhhjmhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[ubjc)}(hinth]hint}(hhhj{hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj[ubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthj[ubj)}(hirqh]hirq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjWubj)}(hstruct msi_desc *entryh](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hmsi_desch]hmsi_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjEsbc.irq_set_msi_descasbuh1hhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hentryh]hentry}(hhhj hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjWubeh}(h]h ]h"]h$]h&]hhuh1jhjhhhj0hK}ubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj0hK}ubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKhjhhubjH)}(hhh]jo)}(h"set MSI descriptor data for an irqh]h"set MSI descriptor data for an irq}(hj6hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chK|hj1hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhj0hK}ubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijLjjjLjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``unsigned int irq`` Interrupt number ``struct msi_desc *entry`` Pointer to MSI descriptor data Set the MSI descriptor entry for an irqh](jo)}(h**Parameters**h]jw)}(hjVh]h Parameters}(hhhjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjTubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKhjPubj)}(hhh](j)}(h&``unsigned int irq`` Interrupt number h](j)}(h``unsigned int irq``h]j)}(hjuh]hunsigned int irq}(hhhjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chK}hjoubj)}(hhh]jo)}(hInterrupt numberh]hInterrupt number}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhK}hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhjhK}hjlubj)}(hb``struct msi_desc *entry`` Pointer to MSI descriptor data Set the MSI descriptor entry for an irqh](j)}(h``struct msi_desc *entry``h]j)}(hjh]hstruct msi_desc *entry}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKhjubj)}(hhh](jo)}(hPointer to MSI descriptor datah]hPointer to MSI descriptor data}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chK~hjubjo)}(h'Set the MSI descriptor entry for an irqh]h'Set the MSI descriptor entry for an irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chKhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhKhjlubeh}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_disable (C function) c.irq_disablehNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h(void irq_disable (struct irq_desc *desc)h]j])}(h'void irq_disable(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMpubju)}(h h]h }(hhhj&hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhj%hMpubj)}(h irq_disableh]j)}(h irq_disableh]h irq_disable}(hhhj8hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhj4ubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhj%hMpubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjThhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubju)}(h h]h }(hhhjahhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjrhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjoubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjtmodnameN classnameNjj)}j]j)}jj:sb c.irq_disableasbuh1hhjPubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjPubj )}(hj h]h*}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubj)}(hdesch]hdesc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjLubah}(h]h ]h"]h$]h&]hhuh1jhjhhhj%hMpubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhj%hMpubah}(h]j ah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhj hhubjH)}(hhh]jo)}(hMark interrupt disabledh]hMark interrupt disabled}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMohjhhubah}(h]h ]h"]h$]h&]uh1jGhj hhhj%hMpubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhjhNhNubjm)}(hXe**Parameters** ``struct irq_desc *desc`` irq descriptor which should be disabled **Description** If the chip does not implement the irq_disable callback, we use a lazy disable approach. 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This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMshjubj)}(hhh]j)}(hB``struct irq_desc *desc`` irq descriptor which should be disabled h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMphjubj)}(hhh]jo)}(h'irq descriptor which should be disabledh]h'irq descriptor which should be disabled}(hj4hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jnhj.hMphj/ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj.hMphjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjTh]h Description}(hhhjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjRubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMrhjubjo)}(hXIf the chip does not implement the irq_disable callback, we use a lazy disable approach. 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This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead.}(hj{hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chM{hjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM handle_edge_eoi_irq (C function)c.handle_edge_eoi_irqhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h0void handle_edge_eoi_irq (struct irq_desc *desc)h]j])}(h/void handle_edge_eoi_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMLubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMLubj)}(hhandle_edge_eoi_irqh]j)}(hhandle_edge_eoi_irqh]hhandle_edge_eoi_irq}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ](jjeh"]h$]h&]hhuh1jhjhhhjhMLubj)}(h(struct irq_desc *desc)h]j)}(hstruct irq_desc *desch](j)}(hjh]hstruct}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubh)}(hhh]j)}(hirq_desch]hirq_desc}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&] refdomainjY reftypej reftargetjmodnameN classnameNjj)}j]j)}jjsbc.handle_edge_eoi_irqasbuh1hhjubju)}(h h]h }(hhhj#hhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjubj )}(hj h]h*}(hhhj1hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(hdesch]hdesc}(hhhj>hhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]noemphhhuh1jhjubah}(h]h ]h"]h$]h&]hhuh1jhjhhhjhMLubeh}(h]h ]h"]h$]h&]hhj:uh1j\j;j<hjhhhjhMLubah}(h]jah ](j@jAeh"]h$]h&]jEuh1jVhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMQhjhhubjH)}(hhh]jo)}(hedge eoi type IRQ handlerh]hedge eoi type IRQ handler}(hjkhjihhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMKhjfhhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMLubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijjjjjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``struct irq_desc *desc`` the interrupt description structure for this irq **Description** Similar as the above handle_edge_irq, but using eoi and w/o the mask/unmask logic.h](jo)}(h**Parameters**h]jw)}(hjh]h Parameters}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMOhjubj)}(hhh]j)}(hK``struct irq_desc *desc`` the interrupt description structure for this irq h](j)}(h``struct irq_desc *desc``h]j)}(hjh]hstruct irq_desc *desc}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMLhjubj)}(hhh]jo)}(h0the interrupt description structure for this irqh]h0the interrupt description structure for this irq}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhMLhjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjh]h Description}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMNhjubjo)}(hRSimilar as the above handle_edge_irq, but using eoi and w/o the mask/unmask logic.h]hRSimilar as the above handle_edge_irq, but using eoi and w/o the mask/unmask logic.}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMNhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMhandle_percpu_irq (C function)c.handle_percpu_irqhNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(h.void handle_percpu_irq (struct irq_desc *desc)h]j])}(h-void handle_percpu_irq(struct irq_desc *desc)h](jc)}(hvoidh]hvoid}(hhhj*hhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhj&hhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMzubju)}(h h]h }(hhhj9hhhNhNubah}(h]h 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Same as handle_percpu_irq() above but with the following extras:}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhjrubjo)}(haction->percpu_dev_id is a pointer to percpu variables which contain the real device id for the cpu on which this handler is calledh]haction->percpu_dev_id is a pointer to percpu variables which contain the real device id for the cpu on which this handler is called}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhjrubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jM,handle_percpu_devid_fasteoi_nmi (C function)!c.handle_percpu_devid_fasteoi_nmihNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(hubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhj=hMhjubah}(h]h ]h"]h$]h&]uh1jhjubjo)}(h**Description**h]jw)}(hjch]h Description}(hhhjehhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjaubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhjubjo)}(hRSimilar to handle_fasteoi_nmi, but handling the dev_id cookie as a percpu pointer.h]hRSimilar to handle_fasteoi_nmi, but handling the dev_id cookie as a percpu pointer.}(hj{hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jlhjhhhNhNubjA)}(hhh]h}(h]h ]h"]h$]h&]entries](jMirq_cpu_online (C function)c.irq_cpu_onlinehNtauh1j@hjhhhNhNubjR)}(hhh](jW)}(hvoid irq_cpu_online (void)h]j])}(hvoid irq_cpu_online(void)h](jc)}(hvoidh]hvoid}(hhhjhhhNhNubah}(h]h ]joah"]h$]h&]uh1jbhjhhhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMtubju)}(h h]h }(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jthjhhhjhMtubj)}(hirq_cpu_onlineh]j)}(hirq_cpu_onlineh]hirq_cpu_online}(hhhjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubah}(h]h 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functions.}(hjDhjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhj?hhubah}(h]h ]h"]h$]h&]uh1jGhjhhhjhMubeh}(h]h ](jY functioneh"]h$]h&]jhjY jijZjjjZjkuh1jQhhhjhNhNubjm)}(h**Parameters** ``void`` no arguments **Description** Iterate through all irqs and invoke the chip.irq_cpu_offline() for each.h](jo)}(h**Parameters**h]jw)}(hjdh]h Parameters}(hhhjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jvhjbubah}(h]h ]h"]h$]h&]uh1jnhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhj^ubj)}(hhh]j)}(h``void`` no arguments h](j)}(h``void``h]j)}(hjh]hvoid}(hhhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhV/var/lib/git/docbuild/linux/Documentation/core-api/genericirq:518: ./kernel/irq/chip.chMhj}ubj)}(hhh]jo)}(h no argumentsh]h no arguments}(hjhjhhhNhNubah}(h]h ]h"]h$]h&]uh1jnhjhMhjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jhjhMhjzubah}(h]h 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