€•ÛN      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ+/translations/zh_CN/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ+/translations/zh_TW/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ+/translations/it_IT/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ+/translations/ja_JP/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ+/translations/ko_KR/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ+/translations/sp_SP/core-api/dma-attributes”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒDMA attributes”h]”hŒDMA attributes”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒE/var/lib/git/docbuild/linux/Documentation/core-api/dma-attributes.rst”h KubhŒ	paragraph”“”)”}”(hŒdThis document describes the semantics of the DMA attributes that are
defined in linux/dma-mapping.h.”h]”hŒdThis document describes the semantics of the DMA attributes that are
defined in linux/dma-mapping.h.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_WEAK_ORDERING”h]”hŒDMA_ATTR_WEAK_ORDERING”…””}”(hhÊhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÇhžhhŸh¶h K	ubh¸)”}”(hŒDMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
may be weakly ordered, that is that reads and writes may pass each other.”h]”hŒDMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
may be weakly ordered, that is that reads and writes may pass each other.”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubh¸)”}”(hŒ˜Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.”h]”hŒ˜Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.”…””}”(hhæhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÇhžhubeh}”(h]”Œdma-attr-weak-ordering”ah ]”h"]”Œdma_attr_weak_ordering”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K	ubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_WRITE_COMBINE”h]”hŒDMA_ATTR_WRITE_COMBINE”…””}”(hhÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhühžhhŸh¶h Kubh¸)”}”(hŒcDMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
buffered to improve performance.”h]”hŒcDMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
buffered to improve performance.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhühžhubh¸)”}”(hŒ˜Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
those that do not will simply ignore the attribute and exhibit default
behavior.”h]”hŒ˜Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
those that do not will simply ignore the attribute and exhibit default
behavior.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhühžhubeh}”(h]”Œdma-attr-write-combine”ah ]”h"]”Œdma_attr_write_combine”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_NO_KERNEL_MAPPING”h]”hŒDMA_ATTR_NO_KERNEL_MAPPING”…””}”(hj4  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj1  hžhhŸh¶h Kubh¸)”}”(hX  DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
virtual mapping for the allocated buffer. On some architectures creating
such mapping is non-trivial task and consumes very limited resources
(like kernel virtual address space or dma consistent address space).
Buffers allocated with this attribute can be only passed to user space
by calling dma_mmap_attrs(). By using this API, you are guaranteeing
that you won't dereference the pointer returned by dma_alloc_attr(). You
can treat it as a cookie that must be passed to dma_mmap_attrs() and
dma_free_attrs(). Make sure that both of these also get this attribute
set on each call.”h]”hX  DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
virtual mapping for the allocated buffer. On some architectures creating
such mapping is non-trivial task and consumes very limited resources
(like kernel virtual address space or dma consistent address space).
Buffers allocated with this attribute can be only passed to user space
by calling dma_mmap_attrs(). By using this API, you are guaranteeing
that you wonâ€™t dereference the pointer returned by dma_alloc_attr(). You
can treat it as a cookie that must be passed to dma_mmap_attrs() and
dma_free_attrs(). Make sure that both of these also get this attribute
set on each call.”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj1  hžhubh¸)”}”(hŒœSince it is optional for platforms to implement
DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
attribute and exhibit default behavior.”h]”hŒœSince it is optional for platforms to implement
DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
attribute and exhibit default behavior.”…””}”(hjP  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K*hj1  hžhubeh}”(h]”Œdma-attr-no-kernel-mapping”ah ]”h"]”Œdma_attr_no_kernel_mapping”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_SKIP_CPU_SYNC”h]”hŒDMA_ATTR_SKIP_CPU_SYNC”…””}”(hji  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjf  hžhhŸh¶h K/ubh¸)”}”(hX  By default dma_map_{single,page,sg} functions family transfer a given
buffer from CPU domain to device domain. Some advanced use cases might
require sharing a buffer between more than one device. This requires
having a mapping created separately for each device and is usually
performed by calling dma_map_{single,page,sg} function more than once
for the given buffer with device pointer to each device taking part in
the buffer sharing. The first call transfers a buffer from 'CPU' domain
to 'device' domain, what synchronizes CPU caches for the given region
(usually it means that the cache has been flushed or invalidated
depending on the dma direction). However, next calls to
dma_map_{single,page,sg}() for other devices will perform exactly the
same synchronization operation on the CPU cache. CPU cache synchronization
might be a time consuming operation, especially if the buffers are
large, so it is highly recommended to avoid it if possible.
DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
the CPU cache for the given buffer assuming that it has been already
transferred to 'device' domain. This attribute can be also used for
dma_unmap_{single,page,sg} functions family to force buffer to stay in
device domain after releasing a mapping for it. Use this attribute with
care!”h]”hX)  By default dma_map_{single,page,sg} functions family transfer a given
buffer from CPU domain to device domain. Some advanced use cases might
require sharing a buffer between more than one device. This requires
having a mapping created separately for each device and is usually
performed by calling dma_map_{single,page,sg} function more than once
for the given buffer with device pointer to each device taking part in
the buffer sharing. The first call transfers a buffer from â€˜CPUâ€™ domain
to â€˜deviceâ€™ domain, what synchronizes CPU caches for the given region
(usually it means that the cache has been flushed or invalidated
depending on the dma direction). However, next calls to
dma_map_{single,page,sg}() for other devices will perform exactly the
same synchronization operation on the CPU cache. CPU cache synchronization
might be a time consuming operation, especially if the buffers are
large, so it is highly recommended to avoid it if possible.
DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
the CPU cache for the given buffer assuming that it has been already
transferred to â€˜deviceâ€™ domain. This attribute can be also used for
dma_unmap_{single,page,sg} functions family to force buffer to stay in
device domain after releasing a mapping for it. Use this attribute with
care!”…””}”(hjw  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K1hjf  hžhubeh}”(h]”Œdma-attr-skip-cpu-sync”ah ]”h"]”Œdma_attr_skip_cpu_sync”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K/ubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_FORCE_CONTIGUOUS”h]”hŒDMA_ATTR_FORCE_CONTIGUOUS”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj  hžhhŸh¶h KGubh¸)”}”(hX-  By default DMA-mapping subsystem is allowed to assemble the buffer
allocated by dma_alloc_attrs() function from individual pages if it can
be mapped as contiguous chunk into device dma address space. By
specifying this attribute the allocated buffer is forced to be contiguous
also in physical memory.”h]”hX-  By default DMA-mapping subsystem is allowed to assemble the buffer
allocated by dma_alloc_attrs() function from individual pages if it can
be mapped as contiguous chunk into device dma address space. By
specifying this attribute the allocated buffer is forced to be contiguous
also in physical memory.”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KIhj  hžhubeh}”(h]”Œdma-attr-force-contiguous”ah ]”h"]”Œdma_attr_force_contiguous”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KGubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_ALLOC_SINGLE_PAGES”h]”hŒDMA_ATTR_ALLOC_SINGLE_PAGES”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj´  hžhhŸh¶h KPubh¸)”}”(hX  This is a hint to the DMA-mapping subsystem that it's probably not worth
the time to try to allocate memory to in a way that gives better TLB
efficiency (AKA it's not worth trying to build the mapping out of larger
pages).  You might want to specify this if:”h]”hX  This is a hint to the DMA-mapping subsystem that itâ€™s probably not worth
the time to try to allocate memory to in a way that gives better TLB
efficiency (AKA itâ€™s not worth trying to build the mapping out of larger
pages).  You might want to specify this if:”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KRhj´  hžhubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX  You know that the accesses to this memory won't thrash the TLB.
You might know that the accesses are likely to be sequential or
that they aren't sequential but it's unlikely you'll ping-pong
between many addresses that are likely to be in different physical
pages.”h]”h¸)”}”(hX  You know that the accesses to this memory won't thrash the TLB.
You might know that the accesses are likely to be sequential or
that they aren't sequential but it's unlikely you'll ping-pong
between many addresses that are likely to be in different physical
pages.”h]”hX  You know that the accesses to this memory wonâ€™t thrash the TLB.
You might know that the accesses are likely to be sequential or
that they arenâ€™t sequential but itâ€™s unlikely youâ€™ll ping-pong
between many addresses that are likely to be in different physical
pages.”…””}”(hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KWhjÚ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jØ  hjÕ  hžhhŸh¶h NubjÙ  )”}”(hŒËYou know that the penalty of TLB misses while accessing the
memory will be small enough to be inconsequential.  If you are
doing a heavy operation like decryption or decompression this
might be the case.”h]”h¸)”}”(hŒËYou know that the penalty of TLB misses while accessing the
memory will be small enough to be inconsequential.  If you are
doing a heavy operation like decryption or decompression this
might be the case.”h]”hŒËYou know that the penalty of TLB misses while accessing the
memory will be small enough to be inconsequential.  If you are
doing a heavy operation like decryption or decompression this
might be the case.”…””}”(hjö  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K\hjò  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jØ  hjÕ  hžhhŸh¶h NubjÙ  )”}”(hŒùYou know that the DMA mapping is fairly transitory.  If you expect
the mapping to have a short lifetime then it may be worth it to
optimize allocation (avoid coming up with large pages) instead of
getting the slight performance win of larger pages.
”h]”h¸)”}”(hŒøYou know that the DMA mapping is fairly transitory.  If you expect
the mapping to have a short lifetime then it may be worth it to
optimize allocation (avoid coming up with large pages) instead of
getting the slight performance win of larger pages.”h]”hŒøYou know that the DMA mapping is fairly transitory.  If you expect
the mapping to have a short lifetime then it may be worth it to
optimize allocation (avoid coming up with large pages) instead of
getting the slight performance win of larger pages.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K`hj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jØ  hjÕ  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jÓ  hŸh¶h KWhj´  hžhubh¸)”}”(hŒ|Setting this hint doesn't guarantee that you won't get huge pages, but it
means that we won't try quite as hard to get them.”h]”hŒ‚Setting this hint doesnâ€™t guarantee that you wonâ€™t get huge pages, but it
means that we wonâ€™t try quite as hard to get them.”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kehj´  hžhubhŒnote”“”)”}”(hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM,
though ARM64 patches will likely be posted soon.”h]”h¸)”}”(hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM,
though ARM64 patches will likely be posted soon.”h]”hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM,
though ARM64 patches will likely be posted soon.”…””}”(hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhj:  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j8  hj´  hžhhŸh¶h Nubeh}”(h]”Œdma-attr-alloc-single-pages”ah ]”h"]”Œdma_attr_alloc_single_pages”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KPubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_NO_WARN”h]”hŒDMA_ATTR_NO_WARN”…””}”(hj]  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjZ  hžhhŸh¶h Klubh¸)”}”(hŒhThis tells the DMA-mapping subsystem to suppress allocation failure reports
(similarly to __GFP_NOWARN).”h]”hŒhThis tells the DMA-mapping subsystem to suppress allocation failure reports
(similarly to __GFP_NOWARN).”…””}”(hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KnhjZ  hžhubh¸)”}”(hXu  On some architectures allocation failures are reported with error messages
to the system logs.  Although this can help to identify and debug problems,
drivers which handle failures (eg, retry later) have no problems with them,
and can actually flood the system logs with error messages that aren't any
problem at all, depending on the implementation of the retry mechanism.”h]”hXw  On some architectures allocation failures are reported with error messages
to the system logs.  Although this can help to identify and debug problems,
drivers which handle failures (eg, retry later) have no problems with them,
and can actually flood the system logs with error messages that arenâ€™t any
problem at all, depending on the implementation of the retry mechanism.”…””}”(hjy  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KqhjZ  hžhubh¸)”}”(hŒ–So, this provides a way for drivers to avoid those error messages on calls
where allocation failures are not a problem, and shouldn't bother the logs.”h]”hŒ˜So, this provides a way for drivers to avoid those error messages on calls
where allocation failures are not a problem, and shouldnâ€™t bother the logs.”…””}”(hj‡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KwhjZ  hžhubj9  )”}”(hŒ>At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.”h]”h¸)”}”(hj—  h]”hŒ>At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.”…””}”(hj™  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kzhj•  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j8  hjZ  hžhhŸh¶h Nubeh}”(h]”Œdma-attr-no-warn”ah ]”h"]”Œdma_attr_no_warn”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Klubh¢)”}”(hhh]”(h§)”}”(hŒDMA_ATTR_PRIVILEGED”h]”hŒDMA_ATTR_PRIVILEGED”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj´  hžhhŸh¶h K}ubh¸)”}”(hXr  Some advanced peripherals such as remote processors and GPUs perform
accesses to DMA buffers in both privileged "supervisor" and unprivileged
"user" modes.  This attribute is used to indicate to the DMA-mapping
subsystem that the buffer is fully accessible at the elevated privilege
level (and ideally inaccessible or at least read-only at the
lesser-privileged levels).”h]”hXz  Some advanced peripherals such as remote processors and GPUs perform
accesses to DMA buffers in both privileged â€œsupervisorâ€ and unprivileged
â€œuserâ€ modes.  This attribute is used to indicate to the DMA-mapping
subsystem that the buffer is fully accessible at the elevated privilege
level (and ideally inaccessible or at least read-only at the
lesser-privileged levels).”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj´  hžhubeh}”(h]”Œdma-attr-privileged”ah ]”h"]”Œdma_attr_privileged”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K}ubeh}”(h]”Œdma-attributes”ah ]”h"]”Œdma attributes”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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