€•KeŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ+/translations/zh_CN/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/zh_TW/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/it_IT/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/ja_JP/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/ko_KR/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/pt_BR/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/sp_SP/core-api/dma-attributes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒDMA attributes”h]”hŒDMA attributes”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒE/var/lib/git/docbuild/linux/Documentation/core-api/dma-attributes.rst”h´KubhŒ paragraph”“”)”}”(hŒdThis document describes the semantics of the DMA attributes that are defined in linux/dma-mapping.h.”h]”hŒdThis document describes the semantics of the DMA attributes that are defined in linux/dma-mapping.h.”…””}”(hhÍh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_WEAK_ORDERING”h]”hŒDMA_ATTR_WEAK_ORDERING”…””}”(hhÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhÛh²hh³hÊh´K ubhÌ)”}”(hŒDMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping may be weakly ordered, that is that reads and writes may pass each other.”h]”hŒDMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping may be weakly ordered, that is that reads and writes may pass each other.”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hhÛh²hubhÌ)”}”(hŒ˜Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, those that do not will simply ignore the attribute and exhibit default behavior.”h]”hŒ˜Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, those that do not will simply ignore the attribute and exhibit default behavior.”…””}”(hhúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhhÛh²hubeh}”(h]”Œdma-attr-weak-ordering”ah ]”h"]”Œdma_attr_weak_ordering”ah$]”h&]”uh1hµhh·h²hh³hÊh´K ubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_WRITE_COMBINE”h]”hŒDMA_ATTR_WRITE_COMBINE”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjh²hh³hÊh´KubhÌ)”}”(hŒcDMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be buffered to improve performance.”h]”hŒcDMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be buffered to improve performance.”…””}”(hj!h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khjh²hubhÌ)”}”(hŒ˜Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, those that do not will simply ignore the attribute and exhibit default behavior.”h]”hŒ˜Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, those that do not will simply ignore the attribute and exhibit default behavior.”…””}”(hj/h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khjh²hubeh}”(h]”Œdma-attr-write-combine”ah ]”h"]”Œdma_attr_write_combine”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_NO_KERNEL_MAPPING”h]”hŒDMA_ATTR_NO_KERNEL_MAPPING”…””}”(hjHh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjEh²hh³hÊh´KubhÌ)”}”(hXDMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel virtual mapping for the allocated buffer. On some architectures creating such mapping is non-trivial task and consumes very limited resources (like kernel virtual address space or dma consistent address space). Buffers allocated with this attribute can be only passed to user space by calling dma_mmap_attrs(). By using this API, you are guaranteeing that you won't dereference the pointer returned by dma_alloc_attr(). You can treat it as a cookie that must be passed to dma_mmap_attrs() and dma_free_attrs(). Make sure that both of these also get this attribute set on each call.”h]”hXDMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel virtual mapping for the allocated buffer. On some architectures creating such mapping is non-trivial task and consumes very limited resources (like kernel virtual address space or dma consistent address space). Buffers allocated with this attribute can be only passed to user space by calling dma_mmap_attrs(). By using this API, you are guaranteeing that you won’t dereference the pointer returned by dma_alloc_attr(). You can treat it as a cookie that must be passed to dma_mmap_attrs() and dma_free_attrs(). Make sure that both of these also get this attribute set on each call.”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjEh²hubhÌ)”}”(hŒœSince it is optional for platforms to implement DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the attribute and exhibit default behavior.”h]”hŒœSince it is optional for platforms to implement DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the attribute and exhibit default behavior.”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K*hjEh²hubeh}”(h]”Œdma-attr-no-kernel-mapping”ah ]”h"]”Œdma_attr_no_kernel_mapping”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_SKIP_CPU_SYNC”h]”hŒDMA_ATTR_SKIP_CPU_SYNC”…””}”(hj}h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjzh²hh³hÊh´K/ubhÌ)”}”(hXBy default dma_map_{single,page,sg} functions family transfer a given buffer from CPU domain to device domain. Some advanced use cases might require sharing a buffer between more than one device. This requires having a mapping created separately for each device and is usually performed by calling dma_map_{single,page,sg} function more than once for the given buffer with device pointer to each device taking part in the buffer sharing. The first call transfers a buffer from 'CPU' domain to 'device' domain, what synchronizes CPU caches for the given region (usually it means that the cache has been flushed or invalidated depending on the dma direction). However, next calls to dma_map_{single,page,sg}() for other devices will perform exactly the same synchronization operation on the CPU cache. CPU cache synchronization might be a time consuming operation, especially if the buffers are large, so it is highly recommended to avoid it if possible. DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of the CPU cache for the given buffer assuming that it has been already transferred to 'device' domain. This attribute can be also used for dma_unmap_{single,page,sg} functions family to force buffer to stay in device domain after releasing a mapping for it. Use this attribute with care!”h]”hX)By default dma_map_{single,page,sg} functions family transfer a given buffer from CPU domain to device domain. Some advanced use cases might require sharing a buffer between more than one device. This requires having a mapping created separately for each device and is usually performed by calling dma_map_{single,page,sg} function more than once for the given buffer with device pointer to each device taking part in the buffer sharing. The first call transfers a buffer from ‘CPU’ domain to ‘device’ domain, what synchronizes CPU caches for the given region (usually it means that the cache has been flushed or invalidated depending on the dma direction). However, next calls to dma_map_{single,page,sg}() for other devices will perform exactly the same synchronization operation on the CPU cache. CPU cache synchronization might be a time consuming operation, especially if the buffers are large, so it is highly recommended to avoid it if possible. DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of the CPU cache for the given buffer assuming that it has been already transferred to ‘device’ domain. This attribute can be also used for dma_unmap_{single,page,sg} functions family to force buffer to stay in device domain after releasing a mapping for it. Use this attribute with care!”…””}”(hj‹h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K1hjzh²hubeh}”(h]”Œdma-attr-skip-cpu-sync”ah ]”h"]”Œdma_attr_skip_cpu_sync”ah$]”h&]”uh1hµhh·h²hh³hÊh´K/ubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_FORCE_CONTIGUOUS”h]”hŒDMA_ATTR_FORCE_CONTIGUOUS”…””}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj¡h²hh³hÊh´KGubhÌ)”}”(hX-By default DMA-mapping subsystem is allowed to assemble the buffer allocated by dma_alloc_attrs() function from individual pages if it can be mapped as contiguous chunk into device dma address space. By specifying this attribute the allocated buffer is forced to be contiguous also in physical memory.”h]”hX-By default DMA-mapping subsystem is allowed to assemble the buffer allocated by dma_alloc_attrs() function from individual pages if it can be mapped as contiguous chunk into device dma address space. By specifying this attribute the allocated buffer is forced to be contiguous also in physical memory.”…””}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KIhj¡h²hubeh}”(h]”Œdma-attr-force-contiguous”ah ]”h"]”Œdma_attr_force_contiguous”ah$]”h&]”uh1hµhh·h²hh³hÊh´KGubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_ALLOC_SINGLE_PAGES”h]”hŒDMA_ATTR_ALLOC_SINGLE_PAGES”…””}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÈh²hh³hÊh´KPubhÌ)”}”(hXThis is a hint to the DMA-mapping subsystem that it's probably not worth the time to try to allocate memory to in a way that gives better TLB efficiency (AKA it's not worth trying to build the mapping out of larger pages). You might want to specify this if:”h]”hXThis is a hint to the DMA-mapping subsystem that it’s probably not worth the time to try to allocate memory to in a way that gives better TLB efficiency (AKA it’s not worth trying to build the mapping out of larger pages). You might want to specify this if:”…””}”(hjÙh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KRhjÈh²hubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hXYou know that the accesses to this memory won't thrash the TLB. You might know that the accesses are likely to be sequential or that they aren't sequential but it's unlikely you'll ping-pong between many addresses that are likely to be in different physical pages.”h]”hÌ)”}”(hXYou know that the accesses to this memory won't thrash the TLB. You might know that the accesses are likely to be sequential or that they aren't sequential but it's unlikely you'll ping-pong between many addresses that are likely to be in different physical pages.”h]”hXYou know that the accesses to this memory won’t thrash the TLB. You might know that the accesses are likely to be sequential or that they aren’t sequential but it’s unlikely you’ll ping-pong between many addresses that are likely to be in different physical pages.”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KWhjîubah}”(h]”h ]”h"]”h$]”h&]”uh1jìhjéh²hh³hÊh´Nubjí)”}”(hŒËYou know that the penalty of TLB misses while accessing the memory will be small enough to be inconsequential. If you are doing a heavy operation like decryption or decompression this might be the case.”h]”hÌ)”}”(hŒËYou know that the penalty of TLB misses while accessing the memory will be small enough to be inconsequential. If you are doing a heavy operation like decryption or decompression this might be the case.”h]”hŒËYou know that the penalty of TLB misses while accessing the memory will be small enough to be inconsequential. If you are doing a heavy operation like decryption or decompression this might be the case.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K\hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jìhjéh²hh³hÊh´Nubjí)”}”(hŒùYou know that the DMA mapping is fairly transitory. If you expect the mapping to have a short lifetime then it may be worth it to optimize allocation (avoid coming up with large pages) instead of getting the slight performance win of larger pages. ”h]”hÌ)”}”(hŒøYou know that the DMA mapping is fairly transitory. If you expect the mapping to have a short lifetime then it may be worth it to optimize allocation (avoid coming up with large pages) instead of getting the slight performance win of larger pages.”h]”hŒøYou know that the DMA mapping is fairly transitory. If you expect the mapping to have a short lifetime then it may be worth it to optimize allocation (avoid coming up with large pages) instead of getting the slight performance win of larger pages.”…””}”(hj"h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K`hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jìhjéh²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jçh³hÊh´KWhjÈh²hubhÌ)”}”(hŒ|Setting this hint doesn't guarantee that you won't get huge pages, but it means that we won't try quite as hard to get them.”h]”hŒ‚Setting this hint doesn’t guarantee that you won’t get huge pages, but it means that we won’t try quite as hard to get them.”…””}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KehjÈh²hubhŒnote”“”)”}”(hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM, though ARM64 patches will likely be posted soon.”h]”hÌ)”}”(hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM, though ARM64 patches will likely be posted soon.”h]”hŒvAt the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM, though ARM64 patches will likely be posted soon.”…””}”(hjRh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhhjNubah}”(h]”h ]”h"]”h$]”h&]”uh1jLhjÈh²hh³hÊh´Nubeh}”(h]”Œdma-attr-alloc-single-pages”ah ]”h"]”Œdma_attr_alloc_single_pages”ah$]”h&]”uh1hµhh·h²hh³hÊh´KPubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_NO_WARN”h]”hŒDMA_ATTR_NO_WARN”…””}”(hjqh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjnh²hh³hÊh´KlubhÌ)”}”(hŒhThis tells the DMA-mapping subsystem to suppress allocation failure reports (similarly to __GFP_NOWARN).”h]”hŒhThis tells the DMA-mapping subsystem to suppress allocation failure reports (similarly to __GFP_NOWARN).”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Knhjnh²hubhÌ)”}”(hXuOn some architectures allocation failures are reported with error messages to the system logs. Although this can help to identify and debug problems, drivers which handle failures (eg, retry later) have no problems with them, and can actually flood the system logs with error messages that aren't any problem at all, depending on the implementation of the retry mechanism.”h]”hXwOn some architectures allocation failures are reported with error messages to the system logs. Although this can help to identify and debug problems, drivers which handle failures (eg, retry later) have no problems with them, and can actually flood the system logs with error messages that aren’t any problem at all, depending on the implementation of the retry mechanism.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kqhjnh²hubhÌ)”}”(hŒ–So, this provides a way for drivers to avoid those error messages on calls where allocation failures are not a problem, and shouldn't bother the logs.”h]”hŒ˜So, this provides a way for drivers to avoid those error messages on calls where allocation failures are not a problem, and shouldn’t bother the logs.”…””}”(hj›h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kwhjnh²hubjM)”}”(hŒ>At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.”h]”hÌ)”}”(hj«h]”hŒ>At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.”…””}”(hj­h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kzhj©ubah}”(h]”h ]”h"]”h$]”h&]”uh1jLhjnh²hh³hÊh´Nubeh}”(h]”Œdma-attr-no-warn”ah ]”h"]”Œdma_attr_no_warn”ah$]”h&]”uh1hµhh·h²hh³hÊh´Klubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_PRIVILEGED”h]”hŒDMA_ATTR_PRIVILEGED”…””}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÈh²hh³hÊh´K}ubhÌ)”}”(hXrSome advanced peripherals such as remote processors and GPUs perform accesses to DMA buffers in both privileged "supervisor" and unprivileged "user" modes. This attribute is used to indicate to the DMA-mapping subsystem that the buffer is fully accessible at the elevated privilege level (and ideally inaccessible or at least read-only at the lesser-privileged levels).”h]”hXzSome advanced peripherals such as remote processors and GPUs perform accesses to DMA buffers in both privileged “supervisor†and unprivileged “user†modes. This attribute is used to indicate to the DMA-mapping subsystem that the buffer is fully accessible at the elevated privilege level (and ideally inaccessible or at least read-only at the lesser-privileged levels).”…””}”(hjÙh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjÈh²hubeh}”(h]”Œdma-attr-privileged”ah ]”h"]”Œdma_attr_privileged”ah$]”h&]”uh1hµhh·h²hh³hÊh´K}ubh¶)”}”(hhh]”(h»)”}”(hŒ DMA_ATTR_MMIO”h]”hŒ DMA_ATTR_MMIO”…””}”(hjòh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjïh²hh³hÊh´K‡ubhÌ)”}”(hŒíThis attribute indicates the physical address is not normal system memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page() functions, it may not be cacheable, and access using CPU load/store instructions may not be allowed.”h]”hŒíThis attribute indicates the physical address is not normal system memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page() functions, it may not be cacheable, and access using CPU load/store instructions may not be allowed.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K‰hjïh²hubhÌ)”}”(hX2Usually this will be used to describe MMIO addresses, or other non-cacheable register addresses. When DMA mapping this sort of address we call the operation Peer to Peer as a one device is DMA'ing to another device. For PCI devices the p2pdma APIs must be used to determine if DMA_ATTR_MMIO is appropriate.”h]”hX4Usually this will be used to describe MMIO addresses, or other non-cacheable register addresses. When DMA mapping this sort of address we call the operation Peer to Peer as a one device is DMA’ing to another device. For PCI devices the p2pdma APIs must be used to determine if DMA_ATTR_MMIO is appropriate.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KŽhjïh²hubhÌ)”}”(hŒ´For architectures that require cache flushing for DMA coherence DMA_ATTR_MMIO will not perform any cache flushing. The address provided must never be mapped cacheable into the CPU.”h]”hŒ´For architectures that require cache flushing for DMA coherence DMA_ATTR_MMIO will not perform any cache flushing. The address provided must never be mapped cacheable into the CPU.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K”hjïh²hubeh}”(h]”Œ dma-attr-mmio”ah ]”h"]”Œ dma_attr_mmio”ah$]”h&]”uh1hµhh·h²hh³hÊh´K‡ubh¶)”}”(hhh]”(h»)”}”(hŒ$DMA_ATTR_DEBUGGING_IGNORE_CACHELINES”h]”hŒ$DMA_ATTR_DEBUGGING_IGNORE_CACHELINES”…””}”(hj5h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj2h²hh³hÊh´K™ubhÌ)”}”(hŒwThis attribute indicates that CPU cache lines may overlap for buffers mapped with DMA_FROM_DEVICE or DMA_BIDIRECTIONAL.”h]”hŒwThis attribute indicates that CPU cache lines may overlap for buffers mapped with DMA_FROM_DEVICE or DMA_BIDIRECTIONAL.”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K›hj2h²hubhÌ)”}”(hXISuch overlap may occur when callers map multiple small buffers that reside within the same cache line. In this case, callers must guarantee that the CPU will not dirty these cache lines after the mappings are established. When this condition is met, multiple buffers can safely share a cache line without risking data corruption.”h]”hXISuch overlap may occur when callers map multiple small buffers that reside within the same cache line. In this case, callers must guarantee that the CPU will not dirty these cache lines after the mappings are established. When this condition is met, multiple buffers can safely share a cache line without risking data corruption.”…””}”(hjQh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kžhj2h²hubhÌ)”}”(hŒwAll mappings that share a cache line must set this attribute to suppress DMA debug warnings about overlapping mappings.”h]”hŒwAll mappings that share a cache line must set this attribute to suppress DMA debug warnings about overlapping mappings.”…””}”(hj_h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K¤hj2h²hubeh}”(h]”Œ$dma-attr-debugging-ignore-cachelines”ah ]”h"]”Œ$dma_attr_debugging_ignore_cachelines”ah$]”h&]”uh1hµhh·h²hh³hÊh´K™ubh¶)”}”(hhh]”(h»)”}”(hŒDMA_ATTR_REQUIRE_COHERENT”h]”hŒDMA_ATTR_REQUIRE_COHERENT”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjuh²hh³hÊh´K¨ubhÌ)”}”(hXgDMA mapping requests with the DMA_ATTR_REQUIRE_COHERENT fail on any system where SWIOTLB or cache management is required. This should only be used to support uAPI designs that require continuous HW DMA coherence with userspace processes, for example RDMA and DRM. At a minimum the memory being mapped must be userspace memory from pin_user_pages() or similar.”h]”hXgDMA mapping requests with the DMA_ATTR_REQUIRE_COHERENT fail on any system where SWIOTLB or cache management is required. This should only be used to support uAPI designs that require continuous HW DMA coherence with userspace processes, for example RDMA and DRM. At a minimum the memory being mapped must be userspace memory from pin_user_pages() or similar.”…””}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kªhjuh²hubhÌ)”}”(hŒrDrivers should consider using dma_mmap_pages() instead of this interface when building their uAPIs, when possible.”h]”hŒrDrivers should consider using dma_mmap_pages() instead of this interface when building their uAPIs, when possible.”…””}”(hj”h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K±hjuh²hubhÌ)”}”(hŒPIt must never be used in an in-kernel driver that only works with kernel memory.”h]”hŒPIt must never be used in an in-kernel driver that only works with kernel memory.”…””}”(hj¢h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K´hjuh²hubeh}”(h]”Œdma-attr-require-coherent”ah ]”h"]”Œdma_attr_require_coherent”ah$]”h&]”uh1hµhh·h²hh³hÊh´K¨ubeh}”(h]”Œdma-attributes”ah ]”h"]”Œdma attributes”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jãŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j½jºj j jBj?jwjtjžj›jÅjÂjkjhjÅjÂjìjéj/j,jrjojµj²uŒ nametypes”}”(j½‰j ‰jB‰jw‰jž‰jʼnjk‰jʼnjì‰j/‰jr‰jµ‰uh}”(jºh·j hÛj?jjtjEj›jzjÂj¡jhjÈjÂjnjéjÈj,jïjoj2j²juuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.