€•N      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ*/translations/zh_CN/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/zh_TW/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/it_IT/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ja_JP/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/ko_KR/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/pt_BR/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ*/translations/sp_SP/core-api/dma-api-howto”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒDynamic DMA mapping Guide”h]”hŒDynamic DMA mapping Guide”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒD/var/lib/git/docbuild/linux/Documentation/core-api/dma-api-howto.rst”h´KubhŒ
field_list”“”)”}”(hhh]”(hŒfield”“”)”}”(hhh]”(hŒ
field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hh×h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÕhhÒh³hÊh´K ubhŒ
field_body”“”)”}”(hŒ"David S. Miller <davem@redhat.com>”h]”hŒ	paragraph”“”)”}”(hhéh]”(hŒDavid S. Miller <”…””}”(hhíh²hh³Nh´NubhŒ	reference”“”)”}”(hŒdavem@redhat.com”h]”hŒdavem@redhat.com”…””}”(hhöh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:davem@redhat.com”uh1hôhhíubhŒ>”…””}”(hhíh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khhçubah}”(h]”h ]”h"]”h$]”h&]”uh1håhhÒubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÐh³hÊh´KhhÍh²hubhÑ)”}”(hhh]”(hÖ)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÕhj  h³hÊh´K ubhæ)”}”(hŒ"Richard Henderson <rth@cygnus.com>”h]”hì)”}”(hj/  h]”(hŒRichard Henderson <”…””}”(hj1  h²hh³Nh´Nubhõ)”}”(hŒrth@cygnus.com”h]”hŒrth@cygnus.com”…””}”(hj8  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:rth@cygnus.com”uh1hôhj1  ubhŒ>”…””}”(hj1  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khj-  ubah}”(h]”h ]”h"]”h$]”h&]”uh1håhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÐh³hÊh´KhhÍh²hubhÑ)”}”(hhh]”(hÖ)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hja  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÕhj^  h³hÊh´K ubhæ)”}”(hŒ!Jakub Jelinek <jakub@redhat.com>
”h]”hì)”}”(hŒ Jakub Jelinek <jakub@redhat.com>”h]”(hŒJakub Jelinek <”…””}”(hjs  h²hh³Nh´Nubhõ)”}”(hŒjakub@redhat.com”h]”hŒjakub@redhat.com”…””}”(hj{  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:jakub@redhat.com”uh1hôhjs  ubhŒ>”…””}”(hjs  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khjo  ubah}”(h]”h ]”h"]”h$]”h&]”uh1håhj^  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÐh³hÊh´KhhÍh²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËhh·h²hh³hÊh´Kubhì)”}”(hŒ«This is a guide to device driver writers on how to use the DMA API
with example pseudo-code.  For a concise description of the API, see
Documentation/core-api/dma-api.rst.”h]”hŒ«This is a guide to device driver writers on how to use the DMA API
with example pseudo-code.  For a concise description of the API, see
Documentation/core-api/dma-api.rst.”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K	hh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒCPU and DMA addresses”h]”hŒCPU and DMA addresses”…””}”(hj¸  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjµ  h²hh³hÊh´Kubhì)”}”(hŒoThere are several kinds of addresses involved in the DMA API, and it's
important to understand the differences.”h]”hŒqThere are several kinds of addresses involved in the DMA API, and itâ€™s
important to understand the differences.”…””}”(hjÆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khjµ  h²hubhì)”}”(hŒ©The kernel normally uses virtual addresses.  Any address returned by
kmalloc(), vmalloc(), and similar interfaces is a virtual address and can
be stored in a ``void *``.”h]”(hŒžThe kernel normally uses virtual addresses.  Any address returned by
kmalloc(), vmalloc(), and similar interfaces is a virtual address and can
be stored in a ”…””}”(hjÔ  h²hh³Nh´NubhŒliteral”“”)”}”(hŒ
``void *``”h]”hŒvoid *”…””}”(hjÞ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hjÔ  ubhŒ.”…””}”(hjÔ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khjµ  h²hubhì)”}”(hX–  The virtual memory system (TLB, page tables, etc.) translates virtual
addresses to CPU physical addresses, which are stored as "phys_addr_t" or
"resource_size_t".  The kernel manages device resources like registers as
physical addresses.  These are the addresses in /proc/iomem.  The physical
address is not directly useful to a driver; it must use ioremap() to map
the space and produce a virtual address.”h]”hXž  The virtual memory system (TLB, page tables, etc.) translates virtual
addresses to CPU physical addresses, which are stored as â€œphys_addr_tâ€ or
â€œresource_size_tâ€.  The kernel manages device resources like registers as
physical addresses.  These are the addresses in /proc/iomem.  The physical
address is not directly useful to a driver; it must use ioremap() to map
the space and produce a virtual address.”…””}”(hjö  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khjµ  h²hubhì)”}”(hX”  I/O devices use a third kind of address: a "bus address".  If a device has
registers at an MMIO address, or if it performs DMA to read or write system
memory, the addresses used by the device are bus addresses.  In some
systems, bus addresses are identical to CPU physical addresses, but in
general they are not.  IOMMUs and host bridges can produce arbitrary
mappings between physical and bus addresses.”h]”hX˜  I/O devices use a third kind of address: a â€œbus addressâ€.  If a device has
registers at an MMIO address, or if it performs DMA to read or write system
memory, the addresses used by the device are bus addresses.  In some
systems, bus addresses are identical to CPU physical addresses, but in
general they are not.  IOMMUs and host bridges can produce arbitrary
mappings between physical and bus addresses.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khjµ  h²hubhì)”}”(hX  From a device's point of view, DMA uses the bus address space, but it may
be restricted to a subset of that space.  For example, even if a system
supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
so devices only need to use 32-bit DMA addresses.”h]”hX  From a deviceâ€™s point of view, DMA uses the bus address space, but it may
be restricted to a subset of that space.  For example, even if a system
supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
so devices only need to use 32-bit DMA addresses.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K%hjµ  h²hubhì)”}”(hŒ$Here's a picture and some examples::”h]”hŒ%Hereâ€™s a picture and some examples:”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K*hjµ  h²hubhŒliteral_block”“”)”}”(hX·               CPU                  CPU                  Bus
           Virtual              Physical             Address
           Address              Address               Space
            Space                Space

          +-------+             +------+             +------+
          |       |             |MMIO  |   Offset    |      |
          |       |  Virtual    |Space |   applied   |      |
        C +-------+ --------> B +------+ ----------> +------+ A
          |       |  mapping    |      |   by host   |      |
+-----+   |       |             |      |   bridge    |      |   +--------+
|     |   |       |             +------+             |      |   |        |
| CPU |   |       |             | RAM  |             |      |   | Device |
|     |   |       |             |      |             |      |   |        |
+-----+   +-------+             +------+             +------+   +--------+
          |       |  Virtual    |Buffer|   Mapping   |      |
        X +-------+ --------> Y +------+ <---------- +------+ Z
          |       |  mapping    | RAM  |   by IOMMU
          |       |             |      |
          |       |             |      |
          +-------+             +------+”h]”hX·               CPU                  CPU                  Bus
           Virtual              Physical             Address
           Address              Address               Space
            Space                Space

          +-------+             +------+             +------+
          |       |             |MMIO  |   Offset    |      |
          |       |  Virtual    |Space |   applied   |      |
        C +-------+ --------> B +------+ ----------> +------+ A
          |       |  mapping    |      |   by host   |      |
+-----+   |       |             |      |   bridge    |      |   +--------+
|     |   |       |             +------+             |      |   |        |
| CPU |   |       |             | RAM  |             |      |   | Device |
|     |   |       |             |      |             |      |   |        |
+-----+   +-------+             +------+             +------+   +--------+
          |       |  Virtual    |Buffer|   Mapping   |      |
        X +-------+ --------> Y +------+ <---------- +------+ Z
          |       |  mapping    | RAM  |   by IOMMU
          |       |             |      |
          |       |             |      |
          +-------+             +------+”…””}”hj0  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1j.  h³hÊh´K,hjµ  h²hubhì)”}”(hX1  During the enumeration process, the kernel learns about I/O devices and
their MMIO space and the host bridges that connect them to the system.  For
example, if a PCI device has a BAR, the kernel reads the bus address (A)
from the BAR and converts it to a CPU physical address (B).  The address B
is stored in a struct resource and usually exposed via /proc/iomem.  When a
driver claims a device, it typically uses ioremap() to map physical address
B at a virtual address (C).  It can then use, e.g., ioread32(C), to access
the device registers at bus address A.”h]”hX1  During the enumeration process, the kernel learns about I/O devices and
their MMIO space and the host bridges that connect them to the system.  For
example, if a PCI device has a BAR, the kernel reads the bus address (A)
from the BAR and converts it to a CPU physical address (B).  The address B
is stored in a struct resource and usually exposed via /proc/iomem.  When a
driver claims a device, it typically uses ioremap() to map physical address
B at a virtual address (C).  It can then use, e.g., ioread32(C), to access
the device registers at bus address A.”…””}”(hj@  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KBhjµ  h²hubhì)”}”(hXf  If the device supports DMA, the driver sets up a buffer using kmalloc() or
a similar interface, which returns a virtual address (X).  The virtual
memory system maps X to a physical address (Y) in system RAM.  The driver
can use virtual address X to access the buffer, but the device itself
cannot because DMA doesn't go through the CPU virtual memory system.”h]”hXh  If the device supports DMA, the driver sets up a buffer using kmalloc() or
a similar interface, which returns a virtual address (X).  The virtual
memory system maps X to a physical address (Y) in system RAM.  The driver
can use virtual address X to access the buffer, but the device itself
cannot because DMA doesnâ€™t go through the CPU virtual memory system.”…””}”(hjN  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KKhjµ  h²hubhì)”}”(hX  In some simple systems, the device can do DMA directly to physical address
Y.  But in many others, there is IOMMU hardware that translates DMA
addresses to physical addresses, e.g., it translates Z to Y.  This is part
of the reason for the DMA API: the driver can give a virtual address X to
an interface like dma_map_single(), which sets up any required IOMMU
mapping and returns the DMA address Z.  The driver then tells the device to
do DMA to Z, and the IOMMU maps it to the buffer at address Y in system
RAM.”h]”hX  In some simple systems, the device can do DMA directly to physical address
Y.  But in many others, there is IOMMU hardware that translates DMA
addresses to physical addresses, e.g., it translates Z to Y.  This is part
of the reason for the DMA API: the driver can give a virtual address X to
an interface like dma_map_single(), which sets up any required IOMMU
mapping and returns the DMA address Z.  The driver then tells the device to
do DMA to Z, and the IOMMU maps it to the buffer at address Y in system
RAM.”…””}”(hj\  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KQhjµ  h²hubhì)”}”(hŒèSo that Linux can use the dynamic DMA mapping, it needs some help from the
drivers, namely it has to take into account that DMA addresses should be
mapped only for the time they are actually used and unmapped after the DMA
transfer.”h]”hŒèSo that Linux can use the dynamic DMA mapping, it needs some help from the
drivers, namely it has to take into account that DMA addresses should be
mapped only for the time they are actually used and unmapped after the DMA
transfer.”…””}”(hjj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KZhjµ  h²hubhì)”}”(hŒVThe following API will work of course even on platforms where no such
hardware exists.”h]”hŒVThe following API will work of course even on platforms where no such
hardware exists.”…””}”(hjx  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K_hjµ  h²hubhì)”}”(hŒñNote that the DMA API works with any bus independent of the underlying
microprocessor architecture. You should use the DMA API rather than the
bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the
pci_map_*() interfaces.”h]”hŒñNote that the DMA API works with any bus independent of the underlying
microprocessor architecture. You should use the DMA API rather than the
bus-specific DMA API, i.e., use the dma_map_*() interfaces rather than the
pci_map_*() interfaces.”…””}”(hj†  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kbhjµ  h²hubhì)”}”(hŒ$First of all, you should make sure::”h]”hŒ#First of all, you should make sure:”…””}”(hj”  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kghjµ  h²hubj/  )”}”(hŒ#include <linux/dma-mapping.h>”h]”hŒ#include <linux/dma-mapping.h>”…””}”hj¢  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Kihjµ  h²hubhì)”}”(hŒØis in your driver, which provides the definition of dma_addr_t.  This type
can hold any valid DMA address for the platform and should be used
everywhere you hold a DMA address returned from the DMA mapping functions.”h]”hŒØis in your driver, which provides the definition of dma_addr_t.  This type
can hold any valid DMA address for the platform and should be used
everywhere you hold a DMA address returned from the DMA mapping functions.”…””}”(hj°  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kkhjµ  h²hubeh}”(h]”Œcpu-and-dma-addresses”ah ]”h"]”Œcpu and dma addresses”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒWhat memory is DMA'able?”h]”hŒWhat memory is DMAâ€™able?”…””}”(hjÉ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÆ  h²hh³hÊh´Kpubhì)”}”(hŒáThe first piece of information you must know is what kernel memory can
be used with the DMA mapping facilities.  There has been an unwritten
set of rules regarding this, and this text is an attempt to finally
write them down.”h]”hŒáThe first piece of information you must know is what kernel memory can
be used with the DMA mapping facilities.  There has been an unwritten
set of rules regarding this, and this text is an attempt to finally
write them down.”…””}”(hj×  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KrhjÆ  h²hubhì)”}”(hŒëIf you acquired your memory via the page allocator
(i.e. __get_free_page*()) or the generic memory allocators
(i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/from
that memory using the addresses returned from those routines.”h]”hŒëIf you acquired your memory via the page allocator
(i.e. __get_free_page*()) or the generic memory allocators
(i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/from
that memory using the addresses returned from those routines.”…””}”(hjå  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KwhjÆ  h²hubhì)”}”(hX¬  This means specifically that you may _not_ use the memory/addresses
returned from vmalloc() for DMA.  It is possible to DMA to the
_underlying_ memory mapped into a vmalloc() area, but this requires
walking page tables to get the physical addresses, and then
translating each of those pages back to a kernel address using
something like __va().  [ EDIT: Update this when we integrate
Gerd Knorr's generic code which does this. ]”h]”hX®  This means specifically that you may _not_ use the memory/addresses
returned from vmalloc() for DMA.  It is possible to DMA to the
_underlying_ memory mapped into a vmalloc() area, but this requires
walking page tables to get the physical addresses, and then
translating each of those pages back to a kernel address using
something like __va().  [ EDIT: Update this when we integrate
Gerd Knorrâ€™s generic code which does this. ]”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K|hjÆ  h²hubhì)”}”(hXf  This rule also means that you may use neither kernel image addresses
(items in data/text/bss segments), nor module image addresses, nor
stack addresses for DMA.  These could all be mapped somewhere entirely
different than the rest of physical memory.  Even if those classes of
memory could physically work with DMA, you'd need to ensure the I/O
buffers were cacheline-aligned.  Without that, you'd see cacheline
sharing problems (data corruption) on CPUs with DMA-incoherent caches.
(The CPU could write to one word, DMA would write to a different one
in the same cache line, and one of them could be overwritten.)”h]”hXj  This rule also means that you may use neither kernel image addresses
(items in data/text/bss segments), nor module image addresses, nor
stack addresses for DMA.  These could all be mapped somewhere entirely
different than the rest of physical memory.  Even if those classes of
memory could physically work with DMA, youâ€™d need to ensure the I/O
buffers were cacheline-aligned.  Without that, youâ€™d see cacheline
sharing problems (data corruption) on CPUs with DMA-incoherent caches.
(The CPU could write to one word, DMA would write to a different one
in the same cache line, and one of them could be overwritten.)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K„hjÆ  h²hubhì)”}”(hŒvAlso, this means that you cannot take the return of a kmap()
call and DMA to/from that.  This is similar to vmalloc().”h]”hŒvAlso, this means that you cannot take the return of a kmap()
call and DMA to/from that.  This is similar to vmalloc().”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KŽhjÆ  h²hubhì)”}”(hŒ›What about block I/O and networking buffers?  The block I/O and
networking subsystems make sure that the buffers they use are valid
for you to DMA from/to.”h]”hŒ›What about block I/O and networking buffers?  The block I/O and
networking subsystems make sure that the buffers they use are valid
for you to DMA from/to.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K‘hjÆ  h²hubeh}”(h]”Œwhat-memory-is-dma-able”ah ]”h"]”Œwhat memory is dma'able?”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kpubh¶)”}”(hhh]”(h»)”}”(hŒ-__dma_from_device_group_begin/end annotations”h]”hŒ-__dma_from_device_group_begin/end annotations”…””}”(hj6  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj3  h²hh³hÊh´K–ubhì)”}”(hX!  As explained previously, when a structure contains a DMA_FROM_DEVICE /
DMA_BIDIRECTIONAL buffer (device writes to memory) alongside fields that the
CPU writes to, cache line sharing between the DMA buffer and CPU-written fields
can cause data corruption on CPUs with DMA-incoherent caches.”h]”hX!  As explained previously, when a structure contains a DMA_FROM_DEVICE /
DMA_BIDIRECTIONAL buffer (device writes to memory) alongside fields that the
CPU writes to, cache line sharing between the DMA buffer and CPU-written fields
can cause data corruption on CPUs with DMA-incoherent caches.”…””}”(hjD  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K˜hj3  h²hubhì)”}”(hŒ€The ``__dma_from_device_group_begin(GROUP)/__dma_from_device_group_end(GROUP)``
macros ensure proper alignment to prevent this::”h]”(hŒThe ”…””}”(hjR  h²hh³Nh´NubjÝ  )”}”(hŒK``__dma_from_device_group_begin(GROUP)/__dma_from_device_group_end(GROUP)``”h]”hŒG__dma_from_device_group_begin(GROUP)/__dma_from_device_group_end(GROUP)”…””}”(hjZ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hjR  ubhŒ0
macros ensure proper alignment to prevent this:”…””}”(hjR  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Khj3  h²hubj/  )”}”(hŒÕstruct my_device {
        spinlock_t lock1;
        __dma_from_device_group_begin();
        char dma_buffer1[16];
        char dma_buffer2[16];
        __dma_from_device_group_end();
        spinlock_t lock2;
};”h]”hŒÕstruct my_device {
        spinlock_t lock1;
        __dma_from_device_group_begin();
        char dma_buffer1[16];
        char dma_buffer2[16];
        __dma_from_device_group_end();
        spinlock_t lock2;
};”…””}”hjr  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´K hj3  h²hubhì)”}”(hX/  To isolate a DMA buffer from adjacent fields, use
``__dma_from_device_group_begin(GROUP)`` before the first DMA buffer
field and ``__dma_from_device_group_end(GROUP)`` after the last DMA
buffer field (with the same GROUP name). This protects both the head
and tail of the buffer from cache line sharing.”h]”(hŒ2To isolate a DMA buffer from adjacent fields, use
”…””}”(hj€  h²hh³Nh´NubjÝ  )”}”(hŒ(``__dma_from_device_group_begin(GROUP)``”h]”hŒ$__dma_from_device_group_begin(GROUP)”…””}”(hjˆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj€  ubhŒ' before the first DMA buffer
field and ”…””}”(hj€  h²hh³Nh´NubjÝ  )”}”(hŒ&``__dma_from_device_group_end(GROUP)``”h]”hŒ"__dma_from_device_group_end(GROUP)”…””}”(hjš  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj€  ubhŒˆ after the last DMA
buffer field (with the same GROUP name). This protects both the head
and tail of the buffer from cache line sharing.”…””}”(hj€  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K©hj3  h²hubhì)”}”(hŒ€The GROUP parameter is an optional identifier that names the DMA buffer group
(in case you have several in the same structure)::”h]”hŒThe GROUP parameter is an optional identifier that names the DMA buffer group
(in case you have several in the same structure):”…””}”(hj²  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K¯hj3  h²hubj/  )”}”(hXA  struct my_device {
        spinlock_t lock1;
        __dma_from_device_group_begin(buffer1);
        char dma_buffer1[16];
        __dma_from_device_group_end(buffer1);
        spinlock_t lock2;
        __dma_from_device_group_begin(buffer2);
        char dma_buffer2[16];
        __dma_from_device_group_end(buffer2);
};”h]”hXA  struct my_device {
        spinlock_t lock1;
        __dma_from_device_group_begin(buffer1);
        char dma_buffer1[16];
        __dma_from_device_group_end(buffer1);
        spinlock_t lock2;
        __dma_from_device_group_begin(buffer2);
        char dma_buffer2[16];
        __dma_from_device_group_end(buffer2);
};”…””}”hjÀ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´K²hj3  h²hubhì)”}”(hŒ¸On cache-coherent platforms these macros expand to zero-length array markers.
On non-coherent platforms, they also ensure the minimal DMA alignment, which
can be as large as 128 bytes.”h]”hŒ¸On cache-coherent platforms these macros expand to zero-length array markers.
On non-coherent platforms, they also ensure the minimal DMA alignment, which
can be as large as 128 bytes.”…””}”(hjÎ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´K½hj3  h²hubhŒnote”“”)”}”(hX-  It is allowed (though somewhat fragile) to include extra fields, not
intended for DMA from the device, within the group (in order to pack the
structure tightly) - but only as long as the CPU does not write these
fields while any fields in the group are mapped for DMA_FROM_DEVICE or
DMA_BIDIRECTIONAL.”h]”hì)”}”(hX-  It is allowed (though somewhat fragile) to include extra fields, not
intended for DMA from the device, within the group (in order to pack the
structure tightly) - but only as long as the CPU does not write these
fields while any fields in the group are mapped for DMA_FROM_DEVICE or
DMA_BIDIRECTIONAL.”h]”hX-  It is allowed (though somewhat fragile) to include extra fields, not
intended for DMA from the device, within the group (in order to pack the
structure tightly) - but only as long as the CPU does not write these
fields while any fields in the group are mapped for DMA_FROM_DEVICE or
DMA_BIDIRECTIONAL.”…””}”(hjâ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KÃhjÞ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj3  h²hh³hÊh´Nubeh}”(h]”Œ+dma-from-device-group-begin-end-annotations”ah ]”h"]”Œ-__dma_from_device_group_begin/end annotations”ah$]”h&]”uh1hµhh·h²hh³hÊh´K–ubh¶)”}”(hhh]”(h»)”}”(hŒDMA addressing capabilities”h]”hŒDMA addressing capabilities”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjþ  h²hh³hÊh´KÊubhì)”}”(hŒÍBy default, the kernel assumes that your device can address 32-bits of DMA
addressing.  For a 64-bit capable device, this needs to be increased, and for
a device with limitations, it needs to be decreased.”h]”hŒÍBy default, the kernel assumes that your device can address 32-bits of DMA
addressing.  For a 64-bit capable device, this needs to be increased, and for
a device with limitations, it needs to be decreased.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KÌhjþ  h²hubhì)”}”(hŒüSpecial note about PCI: PCI-X specification requires PCI-X devices to support
64-bit addressing (DAC) for all transactions.  And at least one platform (SGI
SN2) requires 64-bit coherent allocations to operate correctly when the IO
bus is in PCI-X mode.”h]”hŒüSpecial note about PCI: PCI-X specification requires PCI-X devices to support
64-bit addressing (DAC) for all transactions.  And at least one platform (SGI
SN2) requires 64-bit coherent allocations to operate correctly when the IO
bus is in PCI-X mode.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KÐhjþ  h²hubhì)”}”(hŒuFor correct operation, you must set the DMA mask to inform the kernel about
your devices DMA addressing capabilities.”h]”hŒuFor correct operation, you must set the DMA mask to inform the kernel about
your devices DMA addressing capabilities.”…””}”(hj+  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KÕhjþ  h²hubhì)”}”(hŒ=This is performed via a call to dma_set_mask_and_coherent()::”h]”hŒ<This is performed via a call to dma_set_mask_and_coherent():”…””}”(hj9  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KØhjþ  h²hubj/  )”}”(hŒ<int dma_set_mask_and_coherent(struct device *dev, u64 mask);”h]”hŒ<int dma_set_mask_and_coherent(struct device *dev, u64 mask);”…””}”hjG  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´KÚhjþ  h²hubhì)”}”(hŒ©which will set the mask for both streaming and coherent APIs together.  If you
have some special requirements, then the following two separate calls can be
used instead:”h]”hŒ©which will set the mask for both streaming and coherent APIs together.  If you
have some special requirements, then the following two separate calls can be
used instead:”…””}”(hjU  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KÜhjþ  h²hubhŒblock_quote”“”)”}”(hX!  The setup for streaming mappings is performed via a call to
dma_set_mask()::

        int dma_set_mask(struct device *dev, u64 mask);

The setup for coherent allocations is performed via a call
to dma_set_coherent_mask()::

        int dma_set_coherent_mask(struct device *dev, u64 mask);
”h]”(hì)”}”(hŒLThe setup for streaming mappings is performed via a call to
dma_set_mask()::”h]”hŒKThe setup for streaming mappings is performed via a call to
dma_set_mask():”…””}”(hji  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kàhje  ubj/  )”}”(hŒ/int dma_set_mask(struct device *dev, u64 mask);”h]”hŒ/int dma_set_mask(struct device *dev, u64 mask);”…””}”hjw  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Kãhje  ubhì)”}”(hŒWThe setup for coherent allocations is performed via a call
to dma_set_coherent_mask()::”h]”hŒVThe setup for coherent allocations is performed via a call
to dma_set_coherent_mask():”…””}”(hj…  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kåhje  ubj/  )”}”(hŒ8int dma_set_coherent_mask(struct device *dev, u64 mask);”h]”hŒ8int dma_set_coherent_mask(struct device *dev, u64 mask);”…””}”hj“  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Kèhje  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jc  h³hÊh´Kàhjþ  h²hubhì)”}”(hXz  Here, dev is a pointer to the device struct of your device, and mask is a bit
mask describing which bits of an address your device supports.  Often the
device struct of your device is embedded in the bus-specific device struct of
your device.  For example, &pdev->dev is a pointer to the device struct of a
PCI device (pdev is a pointer to the PCI device struct of your device).”h]”hXz  Here, dev is a pointer to the device struct of your device, and mask is a bit
mask describing which bits of an address your device supports.  Often the
device struct of your device is embedded in the bus-specific device struct of
your device.  For example, &pdev->dev is a pointer to the device struct of a
PCI device (pdev is a pointer to the PCI device struct of your device).”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kêhjþ  h²hubhì)”}”(hX×  These calls usually return zero to indicate your device can perform DMA
properly on the machine given the address mask you provided, but they might
return an error if the mask is too small to be supportable on the given
system.  If it returns non-zero, your device cannot perform DMA properly on
this platform, and attempting to do so will result in undefined behavior.
You must not use DMA on this device unless the dma_set_mask family of
functions has returned success.”h]”hX×  These calls usually return zero to indicate your device can perform DMA
properly on the machine given the address mask you provided, but they might
return an error if the mask is too small to be supportable on the given
system.  If it returns non-zero, your device cannot perform DMA properly on
this platform, and attempting to do so will result in undefined behavior.
You must not use DMA on this device unless the dma_set_mask family of
functions has returned success.”…””}”(hjµ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kðhjþ  h²hubhì)”}”(hŒ:This means that in the failure case, you have two options:”h]”hŒ:This means that in the failure case, you have two options:”…””}”(hjÃ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Køhjþ  h²hubhŒenumerated_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ5Use some non-DMA mode for data transfer, if possible.”h]”hì)”}”(hjÚ  h]”hŒ5Use some non-DMA mode for data transfer, if possible.”…””}”(hjÜ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´KúhjØ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjÓ  h²hh³hÊh´Nubj×  )”}”(hŒ-Ignore this device and do not initialize it.
”h]”hì)”}”(hŒ,Ignore this device and do not initialize it.”h]”hŒ,Ignore this device and do not initialize it.”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kûhjï  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjÓ  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ)”uh1jÑ  hjþ  h²hh³hÊh´Kúubhì)”}”(hX  It is recommended that your driver print a kernel KERN_WARNING message when
setting the DMA mask fails.  In this manner, if a user of your driver reports
that performance is bad or that the device is not even detected, you can ask
them for the kernel messages to find out exactly why.”h]”hX  It is recommended that your driver print a kernel KERN_WARNING message when
setting the DMA mask fails.  In this manner, if a user of your driver reports
that performance is bad or that the device is not even detected, you can ask
them for the kernel messages to find out exactly why.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Kýhjþ  h²hubhì)”}”(hŒ;The 24-bit addressing device would do something like this::”h]”hŒ:The 24-bit addressing device would do something like this:”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhjþ  h²hubj/  )”}”(hŒ—if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(24))) {
        dev_warn(dev, "mydev: No suitable DMA available\n");
        goto ignore_this_device;
}”h]”hŒ—if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(24))) {
        dev_warn(dev, "mydev: No suitable DMA available\n");
        goto ignore_this_device;
}”…””}”hj.  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mhjþ  h²hubhì)”}”(hŒDThe standard 64-bit addressing device would do something like this::”h]”hŒCThe standard 64-bit addressing device would do something like this:”…””}”(hj<  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M	hjþ  h²hubj/  )”}”(hŒ0dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))”h]”hŒ0dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))”…””}”hjJ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mhjþ  h²hubhì)”}”(hŒ^dma_set_mask_and_coherent() never return fail when DMA_BIT_MASK(64). Typical
error code like::”h]”hŒ]dma_set_mask_and_coherent() never return fail when DMA_BIT_MASK(64). Typical
error code like:”…””}”(hjX  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhjþ  h²hubj/  )”}”(hŒ/* Wrong code */
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))”h]”hŒ/* Wrong code */
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))”…””}”hjf  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mhjþ  h²hubhì)”}”(hŒadma_set_mask_and_coherent() will never return failure when bigger than 32.
So typical code like::”h]”hŒ`dma_set_mask_and_coherent() will never return failure when bigger than 32.
So typical code like:”…””}”(hjt  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhjþ  h²hubj/  )”}”(hŒ¢/* Recommended code */
if (support_64bit)
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
else
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));”h]”hŒ¢/* Recommended code */
if (support_64bit)
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
else
        dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));”…””}”hj‚  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mhjþ  h²hubhì)”}”(hŒ¥If the device only supports 32-bit addressing for descriptors in the
coherent allocations, but supports full 64-bits for streaming mappings
it would look like this::”h]”hŒ¤If the device only supports 32-bit addressing for descriptors in the
coherent allocations, but supports full 64-bits for streaming mappings
it would look like this:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhjþ  h²hubj/  )”}”(hŒŠif (dma_set_mask(dev, DMA_BIT_MASK(64))) {
        dev_warn(dev, "mydev: No suitable DMA available\n");
        goto ignore_this_device;
}”h]”hŒŠif (dma_set_mask(dev, DMA_BIT_MASK(64))) {
        dev_warn(dev, "mydev: No suitable DMA available\n");
        goto ignore_this_device;
}”…””}”hjž  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M!hjþ  h²hubhì)”}”(hŒôThe coherent mask will always be able to set the same or a smaller mask as
the streaming mask. However for the rare case that a device driver only
uses coherent allocations, one would have to check the return value from
dma_set_coherent_mask().”h]”hŒôThe coherent mask will always be able to set the same or a smaller mask as
the streaming mask. However for the rare case that a device driver only
uses coherent allocations, one would have to check the return value from
dma_set_coherent_mask().”…””}”(hj¬  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M&hjþ  h²hubhì)”}”(hŒ_Finally, if your device can only drive the low 24-bits of
address you might do something like::”h]”hŒ^Finally, if your device can only drive the low 24-bits of
address you might do something like:”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M+hjþ  h²hubj/  )”}”(hŒ”if (dma_set_mask(dev, DMA_BIT_MASK(24))) {
        dev_warn(dev, "mydev: 24-bit DMA addressing not available\n");
        goto ignore_this_device;
}”h]”hŒ”if (dma_set_mask(dev, DMA_BIT_MASK(24))) {
        dev_warn(dev, "mydev: 24-bit DMA addressing not available\n");
        goto ignore_this_device;
}”…””}”hjÈ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M.hjþ  h²hubhì)”}”(hŒÎWhen dma_set_mask() or dma_set_mask_and_coherent() is successful, and
returns zero, the kernel saves away this mask you have provided.  The
kernel will use this information later when you make DMA mappings.”h]”hŒÎWhen dma_set_mask() or dma_set_mask_and_coherent() is successful, and
returns zero, the kernel saves away this mask you have provided.  The
kernel will use this information later when you make DMA mappings.”…””}”(hjÖ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M3hjþ  h²hubhì)”}”(hXÙ  There is a case which we are aware of at this time, which is worth
mentioning in this documentation.  If your device supports multiple
functions (for example a sound card provides playback and record
functions) and the various different functions have _different_
DMA addressing limitations, you may wish to probe each mask and
only provide the functionality which the machine can handle.  It
is important that the last call to dma_set_mask() be for the
most specific mask.”h]”hXÙ  There is a case which we are aware of at this time, which is worth
mentioning in this documentation.  If your device supports multiple
functions (for example a sound card provides playback and record
functions) and the various different functions have _different_
DMA addressing limitations, you may wish to probe each mask and
only provide the functionality which the machine can handle.  It
is important that the last call to dma_set_mask() be for the
most specific mask.”…””}”(hjä  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M7hjþ  h²hubhì)”}”(hŒ4Here is pseudo-code showing how this might be done::”h]”hŒ3Here is pseudo-code showing how this might be done:”…””}”(hjò  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M@hjþ  h²hubj/  )”}”(hX_  #define PLAYBACK_ADDRESS_BITS   DMA_BIT_MASK(32)
#define RECORD_ADDRESS_BITS     DMA_BIT_MASK(24)

struct my_sound_card *card;
struct device *dev;

...
if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {
        card->playback_enabled = 1;
} else {
        card->playback_enabled = 0;
        dev_warn(dev, "%s: Playback disabled due to DMA limitations\n",
               card->name);
}
if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {
        card->record_enabled = 1;
} else {
        card->record_enabled = 0;
        dev_warn(dev, "%s: Record disabled due to DMA limitations\n",
               card->name);
}”h]”hX_  #define PLAYBACK_ADDRESS_BITS   DMA_BIT_MASK(32)
#define RECORD_ADDRESS_BITS     DMA_BIT_MASK(24)

struct my_sound_card *card;
struct device *dev;

...
if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {
        card->playback_enabled = 1;
} else {
        card->playback_enabled = 0;
        dev_warn(dev, "%s: Playback disabled due to DMA limitations\n",
               card->name);
}
if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {
        card->record_enabled = 1;
} else {
        card->record_enabled = 0;
        dev_warn(dev, "%s: Record disabled due to DMA limitations\n",
               card->name);
}”…””}”hj   sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MBhjþ  h²hubhì)”}”(hŒÄA sound card was used as an example here because this genre of PCI
devices seems to be littered with ISA chips given a PCI front end,
and thus retaining the 16MB DMA addressing limitations of ISA.”h]”hŒÄA sound card was used as an example here because this genre of PCI
devices seems to be littered with ISA chips given a PCI front end,
and thus retaining the 16MB DMA addressing limitations of ISA.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MXhjþ  h²hubeh}”(h]”Œdma-addressing-capabilities”ah ]”h"]”Œdma addressing capabilities”ah$]”h&]”uh1hµhh·h²hh³hÊh´KÊubh¶)”}”(hhh]”(h»)”}”(hŒTypes of DMA mappings”h]”hŒTypes of DMA mappings”…””}”(hj'  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj$  h²hh³hÊh´M]ubhì)”}”(hŒ$There are two types of DMA mappings:”h]”hŒ$There are two types of DMA mappings:”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M_hj$  h²hubhŒbullet_list”“”)”}”(hhh]”(j×  )”}”(hX  Coherent DMA mappings which are usually mapped at driver
initialization, unmapped at the end and for which the hardware should
guarantee that the device and the CPU can access the data
in parallel and will see updates made by each other without any
explicit software flushing.

Think of "coherent" as "synchronous".

The current default is to return coherent memory in the low 32
bits of the DMA space.  However, for future compatibility you should
set the coherent mask even if this default is fine for your
driver.

Good examples of what to use coherent mappings for are:

      - Network card DMA ring descriptors.
      - SCSI adapter mailbox command data structures.
      - Device firmware microcode executed out of
        main memory.

The invariant these examples all require is that any CPU store
to memory is immediately visible to the device, and vice
versa.  Coherent mappings guarantee this.

.. important::

           Coherent DMA memory does not preclude the usage of
           proper memory barriers.  The CPU may reorder stores to
           coherent memory just as it may normal memory.  Example:
           if it is important for the device to see the first word
           of a descriptor updated before the second, you must do
           something like::

              desc->word0 = address;
              wmb();
              desc->word1 = DESC_VALID;

           in order to get correct behavior on all platforms.

           Also, on some platforms your driver may need to flush CPU write
           buffers in much the same way as it needs to flush write buffers
           found in PCI bridges (such as by reading a register's value
           after writing it).
”h]”(hì)”}”(hX  Coherent DMA mappings which are usually mapped at driver
initialization, unmapped at the end and for which the hardware should
guarantee that the device and the CPU can access the data
in parallel and will see updates made by each other without any
explicit software flushing.”h]”hX  Coherent DMA mappings which are usually mapped at driver
initialization, unmapped at the end and for which the hardware should
guarantee that the device and the CPU can access the data
in parallel and will see updates made by each other without any
explicit software flushing.”…””}”(hjL  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MahjH  ubhì)”}”(hŒ%Think of "coherent" as "synchronous".”h]”hŒ-Think of â€œcoherentâ€ as â€œsynchronousâ€.”…””}”(hjZ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MghjH  ubhì)”}”(hŒÇThe current default is to return coherent memory in the low 32
bits of the DMA space.  However, for future compatibility you should
set the coherent mask even if this default is fine for your
driver.”h]”hŒÇThe current default is to return coherent memory in the low 32
bits of the DMA space.  However, for future compatibility you should
set the coherent mask even if this default is fine for your
driver.”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MihjH  ubhì)”}”(hŒ7Good examples of what to use coherent mappings for are:”h]”hŒ7Good examples of what to use coherent mappings for are:”…””}”(hjv  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MnhjH  ubjd  )”}”(hŒ- Network card DMA ring descriptors.
- SCSI adapter mailbox command data structures.
- Device firmware microcode executed out of
  main memory.
”h]”jD  )”}”(hhh]”(j×  )”}”(hŒ"Network card DMA ring descriptors.”h]”hì)”}”(hj  h]”hŒ"Network card DMA ring descriptors.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mphj‹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjˆ  ubj×  )”}”(hŒ-SCSI adapter mailbox command data structures.”h]”hì)”}”(hj¤  h]”hŒ-SCSI adapter mailbox command data structures.”…””}”(hj¦  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mqhj¢  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjˆ  ubj×  )”}”(hŒ7Device firmware microcode executed out of
main memory.
”h]”hì)”}”(hŒ6Device firmware microcode executed out of
main memory.”h]”hŒ6Device firmware microcode executed out of
main memory.”…””}”(hj½  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mrhj¹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjˆ  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jC  h³hÊh´Mphj„  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jc  h³hÊh´MphjH  ubhì)”}”(hŒ¡The invariant these examples all require is that any CPU store
to memory is immediately visible to the device, and vice
versa.  Coherent mappings guarantee this.”h]”hŒ¡The invariant these examples all require is that any CPU store
to memory is immediately visible to the device, and vice
versa.  Coherent mappings guarantee this.”…””}”(hjß  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MuhjH  ubhŒ	important”“”)”}”(hXg  Coherent DMA memory does not preclude the usage of
proper memory barriers.  The CPU may reorder stores to
coherent memory just as it may normal memory.  Example:
if it is important for the device to see the first word
of a descriptor updated before the second, you must do
something like::

   desc->word0 = address;
   wmb();
   desc->word1 = DESC_VALID;

in order to get correct behavior on all platforms.

Also, on some platforms your driver may need to flush CPU write
buffers in much the same way as it needs to flush write buffers
found in PCI bridges (such as by reading a register's value
after writing it).”h]”(hì)”}”(hX!  Coherent DMA memory does not preclude the usage of
proper memory barriers.  The CPU may reorder stores to
coherent memory just as it may normal memory.  Example:
if it is important for the device to see the first word
of a descriptor updated before the second, you must do
something like::”h]”hX   Coherent DMA memory does not preclude the usage of
proper memory barriers.  The CPU may reorder stores to
coherent memory just as it may normal memory.  Example:
if it is important for the device to see the first word
of a descriptor updated before the second, you must do
something like:”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M{hjï  ubj/  )”}”(hŒ7desc->word0 = address;
wmb();
desc->word1 = DESC_VALID;”h]”hŒ7desc->word0 = address;
wmb();
desc->word1 = DESC_VALID;”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M‚hjï  ubhì)”}”(hŒ2in order to get correct behavior on all platforms.”h]”hŒ2in order to get correct behavior on all platforms.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M†hjï  ubhì)”}”(hŒÎAlso, on some platforms your driver may need to flush CPU write
buffers in much the same way as it needs to flush write buffers
found in PCI bridges (such as by reading a register's value
after writing it).”h]”hŒÐAlso, on some platforms your driver may need to flush CPU write
buffers in much the same way as it needs to flush write buffers
found in PCI bridges (such as by reading a registerâ€™s value
after writing it).”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mˆhjï  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jí  hjH  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjE  h²hh³Nh´Nubj×  )”}”(hX¸  Streaming DMA mappings which are usually mapped for one DMA
transfer, unmapped right after it (unless you use dma_sync_* below)
and for which hardware can optimize for sequential accesses.

Think of "streaming" as "asynchronous" or "outside the coherency
domain".

Good examples of what to use streaming mappings for are:

      - Networking buffers transmitted/received by a device.
      - Filesystem buffers written/read by a SCSI device.

The interfaces for using this type of mapping were designed in
such a way that an implementation can make whatever performance
optimizations the hardware allows.  To this end, when using
such mappings you must be explicit about what you want to happen.
”h]”(hì)”}”(hŒ¼Streaming DMA mappings which are usually mapped for one DMA
transfer, unmapped right after it (unless you use dma_sync_* below)
and for which hardware can optimize for sequential accesses.”h]”hŒ¼Streaming DMA mappings which are usually mapped for one DMA
transfer, unmapped right after it (unless you use dma_sync_* below)
and for which hardware can optimize for sequential accesses.”…””}”(hj;  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhj7  ubhì)”}”(hŒIThink of "streaming" as "asynchronous" or "outside the coherency
domain".”h]”hŒUThink of â€œstreamingâ€ as â€œasynchronousâ€ or â€œoutside the coherency
domainâ€.”…””}”(hjI  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M‘hj7  ubhì)”}”(hŒ8Good examples of what to use streaming mappings for are:”h]”hŒ8Good examples of what to use streaming mappings for are:”…””}”(hjW  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M”hj7  ubjd  )”}”(hŒk- Networking buffers transmitted/received by a device.
- Filesystem buffers written/read by a SCSI device.
”h]”jD  )”}”(hhh]”(j×  )”}”(hŒ4Networking buffers transmitted/received by a device.”h]”hì)”}”(hjn  h]”hŒ4Networking buffers transmitted/received by a device.”…””}”(hjp  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M–hjl  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hji  ubj×  )”}”(hŒ2Filesystem buffers written/read by a SCSI device.
”h]”hì)”}”(hŒ1Filesystem buffers written/read by a SCSI device.”h]”hŒ1Filesystem buffers written/read by a SCSI device.”…””}”(hj‡  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M—hjƒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hji  ubeh}”(h]”h ]”h"]”h$]”h&]”j×  jØ  uh1jC  h³hÊh´M–hje  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jc  h³hÊh´M–hj7  ubhì)”}”(hŒüThe interfaces for using this type of mapping were designed in
such a way that an implementation can make whatever performance
optimizations the hardware allows.  To this end, when using
such mappings you must be explicit about what you want to happen.”h]”hŒüThe interfaces for using this type of mapping were designed in
such a way that an implementation can make whatever performance
optimizations the hardware allows.  To this end, when using
such mappings you must be explicit about what you want to happen.”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M™hj7  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjE  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j×  jØ  uh1jC  h³hÊh´Mahj$  h²hubhì)”}”(hX  Neither type of DMA mapping has alignment restrictions that come from
the underlying bus, although some devices may have such restrictions.
Also, systems with caches that aren't DMA-coherent will work better
when the underlying buffers don't share cache lines with other data.”h]”hX  Neither type of DMA mapping has alignment restrictions that come from
the underlying bus, although some devices may have such restrictions.
Also, systems with caches that arenâ€™t DMA-coherent will work better
when the underlying buffers donâ€™t share cache lines with other data.”…””}”(hjÁ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mžhj$  h²hubeh}”(h]”Œtypes-of-dma-mappings”ah ]”h"]”Œtypes of dma mappings”ah$]”h&]”uh1hµhh·h²hh³hÊh´M]ubh¶)”}”(hhh]”(h»)”}”(hŒUsing Coherent DMA mappings”h]”hŒUsing Coherent DMA mappings”…””}”(hjÚ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj×  h²hh³hÊh´M¥ubhì)”}”(hŒQTo allocate and map large (PAGE_SIZE or so) coherent DMA regions,
you should do::”h]”hŒPTo allocate and map large (PAGE_SIZE or so) coherent DMA regions,
you should do:”…””}”(hjè  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M§hj×  h²hubj/  )”}”(hŒSdma_addr_t dma_handle;

cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);”h]”hŒSdma_addr_t dma_handle;

cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);”…””}”hjö  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mªhj×  h²hubhì)”}”(hŒhwhere device is a ``struct device *``. This may be called in interrupt
context with the GFP_ATOMIC flag.”h]”(hŒwhere device is a ”…””}”(hj  h²hh³Nh´NubjÝ  )”}”(hŒ``struct device *``”h]”hŒstruct device *”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj  ubhŒC. This may be called in interrupt
context with the GFP_ATOMIC flag.”…””}”(hj  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M®hj×  h²hubhì)”}”(hŒ@Size is the length of the region you want to allocate, in bytes.”h]”hŒ@Size is the length of the region you want to allocate, in bytes.”…””}”(hj$  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M±hj×  h²hubhì)”}”(hŒûThis routine will allocate RAM for that region, so it acts similarly to
__get_free_pages() (but takes size instead of a page order).  If your
driver needs regions sized smaller than a page, you may prefer using
the dma_pool interface, described below.”h]”hŒûThis routine will allocate RAM for that region, so it acts similarly to
__get_free_pages() (but takes size instead of a page order).  If your
driver needs regions sized smaller than a page, you may prefer using
the dma_pool interface, described below.”…””}”(hj2  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M³hj×  h²hubhì)”}”(hX  The coherent DMA mapping interfaces, will by default return a DMA address
which is 32-bit addressable.  Even if the device indicates (via the DMA mask)
that it may address the upper 32-bits, coherent allocation will only
return > 32-bit addresses for DMA if the coherent DMA mask has been
explicitly changed via dma_set_coherent_mask().  This is true of the
dma_pool interface as well.”h]”hX  The coherent DMA mapping interfaces, will by default return a DMA address
which is 32-bit addressable.  Even if the device indicates (via the DMA mask)
that it may address the upper 32-bits, coherent allocation will only
return > 32-bit addresses for DMA if the coherent DMA mask has been
explicitly changed via dma_set_coherent_mask().  This is true of the
dma_pool interface as well.”…””}”(hj@  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¸hj×  h²hubhì)”}”(hŒ“dma_alloc_coherent() returns two values: the virtual address which you
can use to access it from the CPU and dma_handle which you pass to the
card.”h]”hŒ“dma_alloc_coherent() returns two values: the virtual address which you
can use to access it from the CPU and dma_handle which you pass to the
card.”…””}”(hjN  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¿hj×  h²hubhì)”}”(hXf  The CPU virtual address and the DMA address are both
guaranteed to be aligned to the smallest PAGE_SIZE order which
is greater than or equal to the requested size.  This invariant
exists (for example) to guarantee that if you allocate a chunk
which is smaller than or equal to 64 kilobytes, the extent of the
buffer you receive will not cross a 64K boundary.”h]”hXf  The CPU virtual address and the DMA address are both
guaranteed to be aligned to the smallest PAGE_SIZE order which
is greater than or equal to the requested size.  This invariant
exists (for example) to guarantee that if you allocate a chunk
which is smaller than or equal to 64 kilobytes, the extent of the
buffer you receive will not cross a 64K boundary.”…””}”(hj\  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÃhj×  h²hubhì)”}”(hŒ/To unmap and free such a DMA region, you call::”h]”hŒ.To unmap and free such a DMA region, you call:”…””}”(hjj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÊhj×  h²hubj/  )”}”(hŒ3dma_free_coherent(dev, size, cpu_addr, dma_handle);”h]”hŒ3dma_free_coherent(dev, size, cpu_addr, dma_handle);”…””}”hjx  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MÌhj×  h²hubhì)”}”(hŒ¸where dev, size are the same as in the above call and cpu_addr and
dma_handle are the values dma_alloc_coherent() returned to you.
This function may not be called in interrupt context.”h]”hŒ¸where dev, size are the same as in the above call and cpu_addr and
dma_handle are the values dma_alloc_coherent() returned to you.
This function may not be called in interrupt context.”…””}”(hj†  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÎhj×  h²hubhì)”}”(hXˆ  If your driver needs lots of smaller memory regions, you can write
custom code to subdivide pages returned by dma_alloc_coherent(),
or you can use the dma_pool API to do that.  A dma_pool is like
a kmem_cache, but it uses dma_alloc_coherent(), not __get_free_pages().
Also, it understands common hardware constraints for alignment,
like queue heads needing to be aligned on N byte boundaries.”h]”hXˆ  If your driver needs lots of smaller memory regions, you can write
custom code to subdivide pages returned by dma_alloc_coherent(),
or you can use the dma_pool API to do that.  A dma_pool is like
a kmem_cache, but it uses dma_alloc_coherent(), not __get_free_pages().
Also, it understands common hardware constraints for alignment,
like queue heads needing to be aligned on N byte boundaries.”…””}”(hj”  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÒhj×  h²hubhì)”}”(hŒCreate a dma_pool like this::”h]”hŒCreate a dma_pool like this:”…””}”(hj¢  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÙhj×  h²hubj/  )”}”(hŒQstruct dma_pool *pool;

pool = dma_pool_create(name, dev, size, align, boundary);”h]”hŒQstruct dma_pool *pool;

pool = dma_pool_create(name, dev, size, align, boundary);”…””}”hj°  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MÛhj×  h²hubhì)”}”(hXÌ  The "name" is for diagnostics (like a kmem_cache name); dev and size
are as above.  The device's hardware alignment requirement for this
type of data is "align" (which is expressed in bytes, and must be a
power of two).  If your device has no boundary crossing restrictions,
pass 0 for boundary; passing 4096 says memory allocated from this pool
must not cross 4KByte boundaries (but at that time it may be better to
use dma_alloc_coherent() directly instead).”h]”hXÖ  The â€œnameâ€ is for diagnostics (like a kmem_cache name); dev and size
are as above.  The deviceâ€™s hardware alignment requirement for this
type of data is â€œalignâ€ (which is expressed in bytes, and must be a
power of two).  If your device has no boundary crossing restrictions,
pass 0 for boundary; passing 4096 says memory allocated from this pool
must not cross 4KByte boundaries (but at that time it may be better to
use dma_alloc_coherent() directly instead).”…””}”(hj¾  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mßhj×  h²hubhì)”}”(hŒ+Allocate memory from a DMA pool like this::”h]”hŒ*Allocate memory from a DMA pool like this:”…””}”(hjÌ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mçhj×  h²hubj/  )”}”(hŒ4cpu_addr = dma_pool_alloc(pool, flags, &dma_handle);”h]”hŒ4cpu_addr = dma_pool_alloc(pool, flags, &dma_handle);”…””}”hjÚ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Méhj×  h²hubhì)”}”(hŒ»flags are GFP_KERNEL if blocking is permitted (not in_interrupt nor
holding SMP locks), GFP_ATOMIC otherwise.  Like dma_alloc_coherent(),
this returns two values, cpu_addr and dma_handle.”h]”hŒ»flags are GFP_KERNEL if blocking is permitted (not in_interrupt nor
holding SMP locks), GFP_ATOMIC otherwise.  Like dma_alloc_coherent(),
this returns two values, cpu_addr and dma_handle.”…””}”(hjè  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mëhj×  h²hubhì)”}”(hŒ:Free memory that was allocated from a dma_pool like this::”h]”hŒ9Free memory that was allocated from a dma_pool like this:”…””}”(hjö  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mïhj×  h²hubj/  )”}”(hŒ*dma_pool_free(pool, cpu_addr, dma_handle);”h]”hŒ*dma_pool_free(pool, cpu_addr, dma_handle);”…””}”hj	  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mñhj×  h²hubhì)”}”(hŒªwhere pool is what you passed to dma_pool_alloc(), and cpu_addr and
dma_handle are the values dma_pool_alloc() returned. This function
may be called in interrupt context.”h]”hŒªwhere pool is what you passed to dma_pool_alloc(), and cpu_addr and
dma_handle are the values dma_pool_alloc() returned. This function
may be called in interrupt context.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Móhj×  h²hubhì)”}”(hŒDestroy a dma_pool by calling::”h]”hŒDestroy a dma_pool by calling:”…””}”(hj 	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M÷hj×  h²hubj/  )”}”(hŒdma_pool_destroy(pool);”h]”hŒdma_pool_destroy(pool);”…””}”hj.	  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mùhj×  h²hubhì)”}”(hŒŸMake sure you've called dma_pool_free() for all memory allocated
from a pool before you destroy the pool. This function may not
be called in interrupt context.”h]”hŒ¡Make sure youâ€™ve called dma_pool_free() for all memory allocated
from a pool before you destroy the pool. This function may not
be called in interrupt context.”…””}”(hj<	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mûhj×  h²hubeh}”(h]”Œusing-coherent-dma-mappings”ah ]”h"]”Œusing coherent dma mappings”ah$]”h&]”uh1hµhh·h²hh³hÊh´M¥ubh¶)”}”(hhh]”(h»)”}”(hŒDMA Direction”h]”hŒDMA Direction”…””}”(hjU	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjR	  h²hh³hÊh´M ubhì)”}”(hŒžThe interfaces described in subsequent portions of this document
take a DMA direction argument, which is an integer and takes on
one of the following values::”h]”hŒThe interfaces described in subsequent portions of this document
take a DMA direction argument, which is an integer and takes on
one of the following values:”…””}”(hjc	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubj/  )”}”(hŒ8DMA_BIDIRECTIONAL
DMA_TO_DEVICE
DMA_FROM_DEVICE
DMA_NONE”h]”hŒ8DMA_BIDIRECTIONAL
DMA_TO_DEVICE
DMA_FROM_DEVICE
DMA_NONE”…””}”hjq	  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MhjR	  h²hubhì)”}”(hŒ:You should provide the exact DMA direction if you know it.”h]”hŒ:You should provide the exact DMA direction if you know it.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubhì)”}”(hŒ°DMA_TO_DEVICE means "from main memory to the device"
DMA_FROM_DEVICE means "from the device to main memory"
It is the direction in which the data moves during the DMA
transfer.”h]”hŒ¸DMA_TO_DEVICE means â€œfrom main memory to the deviceâ€
DMA_FROM_DEVICE means â€œfrom the device to main memoryâ€
It is the direction in which the data moves during the DMA
transfer.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubhì)”}”(hŒOYou are _strongly_ encouraged to specify this as precisely
as you possibly can.”h]”hŒOYou are _strongly_ encouraged to specify this as precisely
as you possibly can.”…””}”(hj›	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubhì)”}”(hX  If you absolutely cannot know the direction of the DMA transfer,
specify DMA_BIDIRECTIONAL.  It means that the DMA can go in
either direction.  The platform guarantees that you may legally
specify this, and that it will work, but this may be at the
cost of performance for example.”h]”hX  If you absolutely cannot know the direction of the DMA transfer,
specify DMA_BIDIRECTIONAL.  It means that the DMA can go in
either direction.  The platform guarantees that you may legally
specify this, and that it will work, but this may be at the
cost of performance for example.”…””•š¨      }”(hj©	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubhì)”}”(hŒîThe value DMA_NONE is to be used for debugging.  One can
hold this in a data structure before you come to know the
precise direction, and this will help catch cases where your
direction tracking logic has failed to set things up properly.”h]”hŒîThe value DMA_NONE is to be used for debugging.  One can
hold this in a data structure before you come to know the
precise direction, and this will help catch cases where your
direction tracking logic has failed to set things up properly.”…””}”(hj·	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjR	  h²hubhì)”}”(hX¬  Another advantage of specifying this value precisely (outside of
potential platform-specific optimizations of such) is for debugging.
Some platforms actually have a write permission boolean which DMA
mappings can be marked with, much like page protections in the user
program address space.  Such platforms can and do report errors in the
kernel logs when the DMA controller hardware detects violation of the
permission setting.”h]”hX¬  Another advantage of specifying this value precisely (outside of
potential platform-specific optimizations of such) is for debugging.
Some platforms actually have a write permission boolean which DMA
mappings can be marked with, much like page protections in the user
program address space.  Such platforms can and do report errors in the
kernel logs when the DMA controller hardware detects violation of the
permission setting.”…””}”(hjÅ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M hjR	  h²hubhì)”}”(hŒ‚Only streaming mappings specify a direction, coherent mappings
implicitly have a direction attribute setting of
DMA_BIDIRECTIONAL.”h]”hŒ‚Only streaming mappings specify a direction, coherent mappings
implicitly have a direction attribute setting of
DMA_BIDIRECTIONAL.”…””}”(hjÓ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M(hjR	  h²hubhì)”}”(hŒ‚The SCSI subsystem tells you the direction to use in the
'sc_data_direction' member of the SCSI command your driver is
working on.”h]”hŒ†The SCSI subsystem tells you the direction to use in the
â€˜sc_data_directionâ€™ member of the SCSI command your driver is
working on.”…””}”(hjá	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M,hjR	  h²hubhì)”}”(hŒìFor Networking drivers, it's a rather simple affair.  For transmit
packets, map/unmap them with the DMA_TO_DEVICE direction
specifier.  For receive packets, just the opposite, map/unmap them
with the DMA_FROM_DEVICE direction specifier.”h]”hŒîFor Networking drivers, itâ€™s a rather simple affair.  For transmit
packets, map/unmap them with the DMA_TO_DEVICE direction
specifier.  For receive packets, just the opposite, map/unmap them
with the DMA_FROM_DEVICE direction specifier.”…””}”(hjï	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M0hjR	  h²hubeh}”(h]”Œdma-direction”ah ]”h"]”Œdma direction”ah$]”h&]”uh1hµhh·h²hh³hÊh´M ubh¶)”}”(hhh]”(h»)”}”(hŒUsing Streaming DMA mappings”h]”hŒUsing Streaming DMA mappings”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj
  h²hh³hÊh´M6ubhì)”}”(hŒÐThe streaming DMA mapping routines can be called from interrupt
context.  There are two versions of each map/unmap, one which will
map/unmap a single memory region, and one which will map/unmap a
scatterlist.”h]”hŒÐThe streaming DMA mapping routines can be called from interrupt
context.  There are two versions of each map/unmap, one which will
map/unmap a single memory region, and one which will map/unmap a
scatterlist.”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M8hj
  h²hubhì)”}”(hŒ To map a single region, you do::”h]”hŒTo map a single region, you do:”…””}”(hj$
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M=hj
  h²hubj/  )”}”(hXz  struct device *dev = &my_dev->dev;
dma_addr_t dma_handle;
void *addr = buffer->ptr;
size_t size = buffer->len;

dma_handle = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}”h]”hXz  struct device *dev = &my_dev->dev;
dma_addr_t dma_handle;
void *addr = buffer->ptr;
size_t size = buffer->len;

dma_handle = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}”…””}”hj2
  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M?hj
  h²hubhì)”}”(hŒand to unmap it::”h]”hŒand to unmap it:”…””}”(hj@
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MNhj
  h²hubj/  )”}”(hŒ3dma_unmap_single(dev, dma_handle, size, direction);”h]”hŒ3dma_unmap_single(dev, dma_handle, size, direction);”…””}”hjN
  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MPhj
  h²hubhì)”}”(hX¥  You should call dma_mapping_error() as dma_map_single() could fail and return
error.  Doing so will ensure that the mapping code will work correctly on all
DMA implementations without any dependency on the specifics of the underlying
implementation. Using the returned address without checking for errors could
result in failures ranging from panics to silent data corruption.  The same
applies to dma_map_page() as well.”h]”hX¥  You should call dma_mapping_error() as dma_map_single() could fail and return
error.  Doing so will ensure that the mapping code will work correctly on all
DMA implementations without any dependency on the specifics of the underlying
implementation. Using the returned address without checking for errors could
result in failures ranging from panics to silent data corruption.  The same
applies to dma_map_page() as well.”…””}”(hj\
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MRhj
  h²hubhì)”}”(hŒŒYou should call dma_unmap_single() when the DMA activity is finished, e.g.,
from the interrupt which told you that the DMA transfer is done.”h]”hŒŒYou should call dma_unmap_single() when the DMA activity is finished, e.g.,
from the interrupt which told you that the DMA transfer is done.”…””}”(hjj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MYhj
  h²hubhì)”}”(hX  Using CPU pointers like this for single mappings has a disadvantage:
you cannot reference HIGHMEM memory in this way.  Thus, there is a
map/unmap interface pair akin to dma_{map,unmap}_single().  These
interfaces deal with page/offset pairs instead of CPU pointers.
Specifically::”h]”hX  Using CPU pointers like this for single mappings has a disadvantage:
you cannot reference HIGHMEM memory in this way.  Thus, there is a
map/unmap interface pair akin to dma_{map,unmap}_single().  These
interfaces deal with page/offset pairs instead of CPU pointers.
Specifically:”…””}”(hjx
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M\hj
  h²hubj/  )”}”(hXç  struct device *dev = &my_dev->dev;
dma_addr_t dma_handle;
struct page *page = buffer->page;
unsigned long offset = buffer->offset;
size_t size = buffer->len;

dma_handle = dma_map_page(dev, page, offset, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}

...

dma_unmap_page(dev, dma_handle, size, direction);”h]”hXç  struct device *dev = &my_dev->dev;
dma_addr_t dma_handle;
struct page *page = buffer->page;
unsigned long offset = buffer->offset;
size_t size = buffer->len;

dma_handle = dma_map_page(dev, page, offset, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}

...

dma_unmap_page(dev, dma_handle, size, direction);”…””}”hj†
  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mbhj
  h²hubhì)”}”(hŒ7Here, "offset" means byte offset within the given page.”h]”hŒ;Here, â€œoffsetâ€ means byte offset within the given page.”…””}”(hj”
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mvhj
  h²hubhì)”}”(hŒ„You should call dma_mapping_error() as dma_map_page() could fail and return
error as outlined under the dma_map_single() discussion.”h]”hŒ„You should call dma_mapping_error() as dma_map_page() could fail and return
error as outlined under the dma_map_single() discussion.”…””}”(hj¢
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mxhj
  h²hubhì)”}”(hŒŠYou should call dma_unmap_page() when the DMA activity is finished, e.g.,
from the interrupt which told you that the DMA transfer is done.”h]”hŒŠYou should call dma_unmap_page() when the DMA activity is finished, e.g.,
from the interrupt which told you that the DMA transfer is done.”…””}”(hj°
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M{hj
  h²hubhì)”}”(hŒFWith scatterlists, you map a region gathered from several regions by::”h]”hŒEWith scatterlists, you map a region gathered from several regions by:”…””}”(hj¾
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M~hj
  h²hubj/  )”}”(hŒÈint i, count = dma_map_sg(dev, sglist, nents, direction);
struct scatterlist *sg;

for_each_sg(sglist, sg, count, i) {
        hw_address[i] = sg_dma_address(sg);
        hw_len[i] = sg_dma_len(sg);
}”h]”hŒÈint i, count = dma_map_sg(dev, sglist, nents, direction);
struct scatterlist *sg;

for_each_sg(sglist, sg, count, i) {
        hw_address[i] = sg_dma_address(sg);
        hw_len[i] = sg_dma_len(sg);
}”…””}”hjÌ
  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M€hj
  h²hubhì)”}”(hŒ3where nents is the number of entries in the sglist.”h]”hŒ3where nents is the number of entries in the sglist.”…””}”(hjÚ
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mˆhj
  h²hubhì)”}”(hXê  The implementation is free to merge several consecutive sglist entries
into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any
consecutive sglist entries can be merged into one provided the first one
ends and the second one starts on a page boundary - in fact this is a huge
advantage for cards which either cannot do scatter-gather or have very
limited number of scatter-gather entries) and returns the actual number
of sg entries it mapped them to. On failure 0 is returned.”h]”hXê  The implementation is free to merge several consecutive sglist entries
into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any
consecutive sglist entries can be merged into one provided the first one
ends and the second one starts on a page boundary - in fact this is a huge
advantage for cards which either cannot do scatter-gather or have very
limited number of scatter-gather entries) and returns the actual number
of sg entries it mapped them to. On failure 0 is returned.”…””}”(hjè
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MŠhj
  h²hubhì)”}”(hŒÄThen you should loop count times (note: this can be less than nents times)
and use sg_dma_address() and sg_dma_len() macros where you previously
accessed sg->address and sg->length as shown above.”h]”hŒÄThen you should loop count times (note: this can be less than nents times)
and use sg_dma_address() and sg_dma_len() macros where you previously
accessed sg->address and sg->length as shown above.”…””}”(hjö
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M’hj
  h²hubhì)”}”(hŒ#To unmap a scatterlist, just call::”h]”hŒ"To unmap a scatterlist, just call:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M–hj
  h²hubj/  )”}”(hŒ,dma_unmap_sg(dev, sglist, nents, direction);”h]”hŒ,dma_unmap_sg(dev, sglist, nents, direction);”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M˜hj
  h²hubhì)”}”(hŒ3Again, make sure DMA activity has already finished.”h]”hŒ3Again, make sure DMA activity has already finished.”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mšhj
  h²hubjÝ  )”}”(hŒ³The 'nents' argument to the dma_unmap_sg call must be
the _same_ one you passed into the dma_map_sg call,
it should _NOT_ be the 'count' value _returned_ from the
dma_map_sg call.”h]”hì)”}”(hŒ³The 'nents' argument to the dma_unmap_sg call must be
the _same_ one you passed into the dma_map_sg call,
it should _NOT_ be the 'count' value _returned_ from the
dma_map_sg call.”h]”hŒ»The â€˜nentsâ€™ argument to the dma_unmap_sg call must be
the _same_ one you passed into the dma_map_sg call,
it should _NOT_ be the â€˜countâ€™ value _returned_ from the
dma_map_sg call.”…””}”(hj2  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mžhj.  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj
  h²hh³hÊh´Nubhì)”}”(hŒÒEvery dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()
counterpart, because the DMA address space is a shared resource and
you could render the machine unusable by consuming all DMA addresses.”h]”hŒÒEvery dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()
counterpart, because the DMA address space is a shared resource and
you could render the machine unusable by consuming all DMA addresses.”…””}”(hjF  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M£hj
  h²hubhì)”}”(hŒöIf you need to use the same streaming DMA region multiple times and touch
the data in between the DMA transfers, the buffer needs to be synced
properly in order for the CPU and device to see the most up-to-date and
correct copy of the DMA buffer.”h]”hŒöIf you need to use the same streaming DMA region multiple times and touch
the data in between the DMA transfers, the buffer needs to be synced
properly in order for the CPU and device to see the most up-to-date and
correct copy of the DMA buffer.”…””}”(hjT  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M§hj
  h²hubhì)”}”(hŒ^So, firstly, just map it with dma_map_{single,sg}(), and after each DMA
transfer call either::”h]”hŒ]So, firstly, just map it with dma_map_{single,sg}(), and after each DMA
transfer call either:”…””}”(hjb  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¬hj
  h²hubj/  )”}”(hŒ:dma_sync_single_for_cpu(dev, dma_handle, size, direction);”h]”hŒ:dma_sync_single_for_cpu(dev, dma_handle, size, direction);”…””}”hjp  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M¯hj
  h²hubhì)”}”(hŒor::”h]”hŒor:”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M±hj
  h²hubj/  )”}”(hŒ3dma_sync_sg_for_cpu(dev, sglist, nents, direction);”h]”hŒ3dma_sync_sg_for_cpu(dev, sglist, nents, direction);”…””}”hjŒ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M³hj
  h²hubhì)”}”(hŒas appropriate.”h]”hŒas appropriate.”…””}”(hjš  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mµhj
  h²hubhì)”}”(hŒ¯Then, if you wish to let the device get at the DMA area again,
finish accessing the data with the CPU, and then before actually
giving the buffer to the hardware call either::”h]”hŒ®Then, if you wish to let the device get at the DMA area again,
finish accessing the data with the CPU, and then before actually
giving the buffer to the hardware call either:”…””}”(hj¨  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M·hj
  h²hubj/  )”}”(hŒ=dma_sync_single_for_device(dev, dma_handle, size, direction);”h]”hŒ=dma_sync_single_for_device(dev, dma_handle, size, direction);”…””}”hj¶  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M»hj
  h²hubhì)”}”(hŒor::”h]”hŒor:”…””}”(hjÄ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M½hj
  h²hubj/  )”}”(hŒ6dma_sync_sg_for_device(dev, sglist, nents, direction);”h]”hŒ6dma_sync_sg_for_device(dev, sglist, nents, direction);”…””}”hjÒ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M¿hj
  h²hubhì)”}”(hŒas appropriate.”h]”hŒas appropriate.”…””}”(hjà  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÁhj
  h²hubjÝ  )”}”(hŒ£The 'nents' argument to dma_sync_sg_for_cpu() and
dma_sync_sg_for_device() must be the same passed to
dma_map_sg(). It is _NOT_ the count returned by
dma_map_sg().”h]”hì)”}”(hŒ£The 'nents' argument to dma_sync_sg_for_cpu() and
dma_sync_sg_for_device() must be the same passed to
dma_map_sg(). It is _NOT_ the count returned by
dma_map_sg().”h]”hŒ§The â€˜nentsâ€™ argument to dma_sync_sg_for_cpu() and
dma_sync_sg_for_device() must be the same passed to
dma_map_sg(). It is _NOT_ the count returned by
dma_map_sg().”…””}”(hjò  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÅhjî  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÜ  hj
  h²hh³hÊh´Nubhì)”}”(hŒåAfter the last DMA transfer call one of the DMA unmap routines
dma_unmap_{single,sg}(). If you don't touch the data from the first
dma_map_*() call till dma_unmap_*(), then you don't have to call the
dma_sync_*() routines at all.”h]”hŒéAfter the last DMA transfer call one of the DMA unmap routines
dma_unmap_{single,sg}(). If you donâ€™t touch the data from the first
dma_map_*() call till dma_unmap_*(), then you donâ€™t have to call the
dma_sync_*() routines at all.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÊhj
  h²hubhì)”}”(hŒhHere is pseudo code which shows a situation in which you would need
to use the dma_sync_*() interfaces::”h]”hŒgHere is pseudo code which shows a situation in which you would need
to use the dma_sync_*() interfaces:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÏhj
  h²hubj/  )”}”(hX1  my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)
{
        dma_addr_t mapping;

        mapping = dma_map_single(cp->dev, buffer, len, DMA_FROM_DEVICE);
        if (dma_mapping_error(cp->dev, mapping)) {
                /*
                 * reduce current DMA mapping usage,
                 * delay and try again later or
                 * reset driver.
                 */
                goto map_error_handling;
        }

        cp->rx_buf = buffer;
        cp->rx_len = len;
        cp->rx_dma = mapping;

        give_rx_buf_to_card(cp);
}

...

my_card_interrupt_handler(int irq, void *devid, struct pt_regs *regs)
{
        struct my_card *cp = devid;

        ...
        if (read_card_status(cp) == RX_BUF_TRANSFERRED) {
                struct my_card_header *hp;

                /* Examine the header to see if we wish
                 * to accept the data.  But synchronize
                 * the DMA transfer with the CPU first
                 * so that we see updated contents.
                 */
                dma_sync_single_for_cpu(&cp->dev, cp->rx_dma,
                                        cp->rx_len,
                                        DMA_FROM_DEVICE);

                /* Now it is safe to examine the buffer. */
                hp = (struct my_card_header *) cp->rx_buf;
                if (header_is_ok(hp)) {
                        dma_unmap_single(&cp->dev, cp->rx_dma, cp->rx_len,
                                         DMA_FROM_DEVICE);
                        pass_to_upper_layers(cp->rx_buf);
                        make_and_setup_new_rx_buf(cp);
                } else {
                        /* CPU should not write to
                         * DMA_FROM_DEVICE-mapped area,
                         * so dma_sync_single_for_device() is
                         * not needed here. It would be required
                         * for DMA_BIDIRECTIONAL mapping if
                         * the memory was modified.
                         */
                        give_rx_buf_to_card(cp);
                }
        }
}”h]”hX1  my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)
{
        dma_addr_t mapping;

        mapping = dma_map_single(cp->dev, buffer, len, DMA_FROM_DEVICE);
        if (dma_mapping_error(cp->dev, mapping)) {
                /*
                 * reduce current DMA mapping usage,
                 * delay and try again later or
                 * reset driver.
                 */
                goto map_error_handling;
        }

        cp->rx_buf = buffer;
        cp->rx_len = len;
        cp->rx_dma = mapping;

        give_rx_buf_to_card(cp);
}

...

my_card_interrupt_handler(int irq, void *devid, struct pt_regs *regs)
{
        struct my_card *cp = devid;

        ...
        if (read_card_status(cp) == RX_BUF_TRANSFERRED) {
                struct my_card_header *hp;

                /* Examine the header to see if we wish
                 * to accept the data.  But synchronize
                 * the DMA transfer with the CPU first
                 * so that we see updated contents.
                 */
                dma_sync_single_for_cpu(&cp->dev, cp->rx_dma,
                                        cp->rx_len,
                                        DMA_FROM_DEVICE);

                /* Now it is safe to examine the buffer. */
                hp = (struct my_card_header *) cp->rx_buf;
                if (header_is_ok(hp)) {
                        dma_unmap_single(&cp->dev, cp->rx_dma, cp->rx_len,
                                         DMA_FROM_DEVICE);
                        pass_to_upper_layers(cp->rx_buf);
                        make_and_setup_new_rx_buf(cp);
                } else {
                        /* CPU should not write to
                         * DMA_FROM_DEVICE-mapped area,
                         * so dma_sync_single_for_device() is
                         * not needed here. It would be required
                         * for DMA_BIDIRECTIONAL mapping if
                         * the memory was modified.
                         */
                        give_rx_buf_to_card(cp);
                }
        }
}”…””}”hj"  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MÒhj
  h²hubeh}”(h]”Œusing-streaming-dma-mappings”ah ]”h"]”Œusing streaming dma mappings”ah$]”h&]”uh1hµhh·h²hh³hÊh´M6ubh¶)”}”(hhh]”(h»)”}”(hŒHandling Errors”h]”hŒHandling Errors”…””}”(hj;  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj8  h²hh³hÊh´Mubhì)”}”(hŒbDMA address space is limited on some architectures and an allocation
failure can be determined by:”h]”hŒbDMA address space is limited on some architectures and an allocation
failure can be determined by:”…””}”(hjI  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhj8  h²hubjD  )”}”(hhh]”(j×  )”}”(hŒFchecking if dma_alloc_coherent() returns NULL or dma_map_sg returns 0
”h]”hì)”}”(hŒEchecking if dma_alloc_coherent() returns NULL or dma_map_sg returns 0”h]”hŒEchecking if dma_alloc_coherent() returns NULL or dma_map_sg returns 0”…””}”(hj^  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MhjZ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjW  h²hh³hÊh´Nubj×  )”}”(hXÉ  checking the dma_addr_t returned from dma_map_single() and dma_map_page()
by using dma_mapping_error()::

      dma_addr_t dma_handle;

      dma_handle = dma_map_single(dev, addr, size, direction);
      if (dma_mapping_error(dev, dma_handle)) {
              /*
               * reduce current DMA mapping usage,
               * delay and try again later or
               * reset driver.
               */
              goto map_error_handling;
      }
”h]”(hì)”}”(hŒhchecking the dma_addr_t returned from dma_map_single() and dma_map_page()
by using dma_mapping_error()::”h]”hŒgchecking the dma_addr_t returned from dma_map_single() and dma_map_page()
by using dma_mapping_error():”…””}”(hjv  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mhjr  ubj/  )”}”(hX"  dma_addr_t dma_handle;

dma_handle = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}”h]”hX"  dma_addr_t dma_handle;

dma_handle = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling;
}”…””}”hj„  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mhjr  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjW  h²hh³hÊh´Nubj×  )”}”(hŒ©unmap pages that are already mapped, when mapping error occurs in the middle
of a multiple page mapping attempt. These example are applicable to
dma_map_page() as well.
”h]”hì)”}”(hŒ¨unmap pages that are already mapped, when mapping error occurs in the middle
of a multiple page mapping attempt. These example are applicable to
dma_map_page() as well.”h]”hŒ¨unmap pages that are already mapped, when mapping error occurs in the middle
of a multiple page mapping attempt. These example are applicable to
dma_map_page() as well.”…””}”(hjœ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M%hj˜  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjW  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j×  jØ  uh1jC  h³hÊh´Mhj8  h²hubhì)”}”(hŒExample 1::”h]”hŒ
Example 1:”…””}”(hj¶  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M)hj8  h²hubj/  )”}”(hX£  dma_addr_t dma_handle1;
dma_addr_t dma_handle2;

dma_handle1 = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle1)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling1;
}
dma_handle2 = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle2)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling2;
}

...

map_error_handling2:
        dma_unmap_single(dma_handle1);
map_error_handling1:”h]”hX£  dma_addr_t dma_handle1;
dma_addr_t dma_handle2;

dma_handle1 = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle1)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling1;
}
dma_handle2 = dma_map_single(dev, addr, size, direction);
if (dma_mapping_error(dev, dma_handle2)) {
        /*
         * reduce current DMA mapping usage,
         * delay and try again later or
         * reset driver.
         */
        goto map_error_handling2;
}

...

map_error_handling2:
        dma_unmap_single(dma_handle1);
map_error_handling1:”…””}”hjÄ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M+hj8  h²hubhì)”}”(hŒExample 2::”h]”hŒ
Example 2:”…””}”(hjÒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MGhj8  h²hubj/  )”}”(hXú  /*
 * if buffers are allocated in a loop, unmap all mapped buffers when
 * mapping error is detected in the middle
 */

dma_addr_t dma_addr;
dma_addr_t array[DMA_BUFFERS];
int save_index = 0;

for (i = 0; i < DMA_BUFFERS; i++) {

        ...

        dma_addr = dma_map_single(dev, addr, size, direction);
        if (dma_mapping_error(dev, dma_addr)) {
                /*
                 * reduce current DMA mapping usage,
                 * delay and try again later or
                 * reset driver.
                 */
                goto map_error_handling;
        }
        array[i].dma_addr = dma_addr;
        save_index++;
}

...

map_error_handling:

for (i = 0; i < save_index; i++) {

        ...

        dma_unmap_single(array[i].dma_addr);
}”h]”hXú  /*
 * if buffers are allocated in a loop, unmap all mapped buffers when
 * mapping error is detected in the middle
 */

dma_addr_t dma_addr;
dma_addr_t array[DMA_BUFFERS];
int save_index = 0;

for (i = 0; i < DMA_BUFFERS; i++) {

        ...

        dma_addr = dma_map_single(dev, addr, size, direction);
        if (dma_mapping_error(dev, dma_addr)) {
                /*
                 * reduce current DMA mapping usage,
                 * delay and try again later or
                 * reset driver.
                 */
                goto map_error_handling;
        }
        array[i].dma_addr = dma_addr;
        save_index++;
}

...

map_error_handling:

for (i = 0; i < save_index; i++) {

        ...

        dma_unmap_single(array[i].dma_addr);
}”…””}”hjà  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MIhj8  h²hubhì)”}”(hŒåNetworking drivers must call dev_kfree_skb() to free the socket buffer
and return NETDEV_TX_OK if the DMA mapping fails on the transmit hook
(ndo_start_xmit). This means that the socket buffer is just dropped in
the failure case.”h]”hŒåNetworking drivers must call dev_kfree_skb() to free the socket buffer
and return NETDEV_TX_OK if the DMA mapping fails on the transmit hook
(ndo_start_xmit). This means that the socket buffer is just dropped in
the failure case.”…””}”(hjî  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mnhj8  h²hubhì)”}”(hŒ³SCSI drivers must return SCSI_MLQUEUE_HOST_BUSY if the DMA mapping
fails in the queuecommand hook. This means that the SCSI subsystem
passes the command to the driver again later.”h]”hŒ³SCSI drivers must return SCSI_MLQUEUE_HOST_BUSY if the DMA mapping
fails in the queuecommand hook. This means that the SCSI subsystem
passes the command to the driver again later.”…””}”(hjü  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mshj8  h²hubeh}”(h]”Œhandling-errors”ah ]”h"]”Œhandling errors”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mubh¶)”}”(hhh]”(h»)”}”(hŒ(Optimizing Unmap State Space Consumption”h]”hŒ(Optimizing Unmap State Space Consumption”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´Mxubhì)”}”(hX@  On many platforms, dma_unmap_{single,page}() is simply a nop.
Therefore, keeping track of the mapping address and length is a waste
of space.  Instead of filling your drivers up with ifdefs and the like
to "work around" this (which would defeat the whole purpose of a
portable API) the following facilities are provided.”h]”hXD  On many platforms, dma_unmap_{single,page}() is simply a nop.
Therefore, keeping track of the mapping address and length is a waste
of space.  Instead of filling your drivers up with ifdefs and the like
to â€œwork aroundâ€ this (which would defeat the whole purpose of a
portable API) the following facilities are provided.”…””}”(hj#  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mzhj  h²hubhì)”}”(hŒYActually, instead of describing the macros one by one, we'll
transform some example code.”h]”hŒ[Actually, instead of describing the macros one by one, weâ€™ll
transform some example code.”…””}”(hj1  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M€hj  h²hubjÒ  )”}”(hhh]”(j×  )”}”(hXm  Use DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.
Example, before::

     struct ring_state {
             struct sk_buff *skb;
             dma_addr_t mapping;
             __u32 len;
     };

after::

     struct ring_state {
             struct sk_buff *skb;
             DEFINE_DMA_UNMAP_ADDR(mapping);
             DEFINE_DMA_UNMAP_LEN(len);
     };
”h]”(hì)”}”(hŒMUse DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.
Example, before::”h]”hŒLUse DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.
Example, before:”…””}”(hjF  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MƒhjB  ubj/  )”}”(hŒbstruct ring_state {
        struct sk_buff *skb;
        dma_addr_t mapping;
        __u32 len;
};”h]”hŒbstruct ring_state {
        struct sk_buff *skb;
        dma_addr_t mapping;
        __u32 len;
};”…””}”hjT  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M†hjB  ubhì)”}”(hŒafter::”h]”hŒafter:”…””}”(hjb  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MŒhjB  ubj/  )”}”(hŒ~struct ring_state {
        struct sk_buff *skb;
        DEFINE_DMA_UNMAP_ADDR(mapping);
        DEFINE_DMA_UNMAP_LEN(len);
};”h]”hŒ~struct ring_state {
        struct sk_buff *skb;
        DEFINE_DMA_UNMAP_ADDR(mapping);
        DEFINE_DMA_UNMAP_LEN(len);
};”…””}”hjp  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MŽhjB  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hj?  h²hh³hÊh´Nubj×  )”}”(hŒÚUse dma_unmap_{addr,len}_set() to set these values.
Example, before::

     ringp->mapping = FOO;
     ringp->len = BAR;

after::

     dma_unmap_addr_set(ringp, mapping, FOO);
     dma_unmap_len_set(ringp, len, BAR);
”h]”(hì)”}”(hŒEUse dma_unmap_{addr,len}_set() to set these values.
Example, before::”h]”hŒDUse dma_unmap_{addr,len}_set() to set these values.
Example, before:”…””}”(hjˆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M”hj„  ubj/  )”}”(hŒ'ringp->mapping = FOO;
ringp->len = BAR;”h]”hŒ'ringp->mapping = FOO;
ringp->len = BAR;”…””}”hj–  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M—hj„  ubhì)”}”(hŒafter::”h]”hŒafter:”…””}”(hj¤  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´Mšhj„  ubj/  )”}”(hŒLdma_unmap_addr_set(ringp, mapping, FOO);
dma_unmap_len_set(ringp, len, BAR);”h]”hŒLdma_unmap_addr_set(ringp, mapping, FOO);
dma_unmap_len_set(ringp, len, BAR);”…””}”hj²  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´Mœhj„  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hj?  h²hh³hÊh´Nubj×  )”}”(hXY  Use dma_unmap_{addr,len}() to access these values.
Example, before::

     dma_unmap_single(dev, ringp->mapping, ringp->len,
                      DMA_FROM_DEVICE);

after::

     dma_unmap_single(dev,
                      dma_unmap_addr(ringp, mapping),
                      dma_unmap_len(ringp, len),
                      DMA_FROM_DEVICE);
”h]”(hì)”}”(hŒDUse dma_unmap_{addr,len}() to access these values.
Example, before::”h]”hŒCUse dma_unmap_{addr,len}() to access these values.
Example, before:”…””}”(hjÊ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MŸhjÆ  ubj/  )”}”(hŒTdma_unmap_single(dev, ringp->mapping, ringp->len,
                 DMA_FROM_DEVICE);”h]”hŒTdma_unmap_single(dev, ringp->mapping, ringp->len,
                 DMA_FROM_DEVICE);”…””}”hjØ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M¢hjÆ  ubhì)”}”(hŒafter::”h]”hŒafter:”…””}”(hjæ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¥hjÆ  ubj/  )”}”(hŒ•dma_unmap_single(dev,
                 dma_unmap_addr(ringp, mapping),
                 dma_unmap_len(ringp, len),
                 DMA_FROM_DEVICE);”h]”hŒ•dma_unmap_single(dev,
                 dma_unmap_addr(ringp, mapping),
                 dma_unmap_len(ringp, len),
                 DMA_FROM_DEVICE);”…””}”hjô  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´M§hjÆ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hj?  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jÑ  hj  h²hh³hÊh´Mƒubhì)”}”(hŒ»It really should be self-explanatory.  We treat the ADDR and LEN
separately, because it is possible for an implementation to only
need the address in order to perform the unmap operation.”h]”hŒ»It really should be self-explanatory.  We treat the ADDR and LEN
separately, because it is possible for an implementation to only
need the address in order to perform the unmap operation.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¬hj  h²hubeh}”(h]”Œ(optimizing-unmap-state-space-consumption”ah ]”h"]”Œ(optimizing unmap state space consumption”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mxubh¶)”}”(hhh]”(h»)”}”(hŒPlatform Issues”h]”hŒPlatform Issues”…””}”(hj'  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj$  h²hh³hÊh´M±ubhì)”}”(hŒ‰If you are just writing drivers for Linux and do not maintain
an architecture port for the kernel, you can safely skip down
to "Closing".”h]”hŒIf you are just writing drivers for Linux and do not maintain
an architecture port for the kernel, you can safely skip down
to â€œClosingâ€.”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M³hj$  h²hubjÒ  )”}”(hhh]”(j×  )”}”(hŒStruct scatterlist requirements.

You need to enable CONFIG_NEED_SG_DMA_LENGTH if the architecture
supports IOMMUs (including software IOMMU).
”h]”(hì)”}”(hŒ Struct scatterlist requirements.”h]”hŒ Struct scatterlist requirements.”…””}”(hjJ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M·hjF  ubhì)”}”(hŒlYou need to enable CONFIG_NEED_SG_DMA_LENGTH if the architecture
supports IOMMUs (including software IOMMU).”h]”hŒlYou need to enable CONFIG_NEED_SG_DMA_LENGTH if the architecture
supports IOMMUs (including software IOMMU).”…””}”(hjX  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¹hjF  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjC  h²hh³hÊh´Nubj×  )”}”(hXƒ  ARCH_DMA_MINALIGN

Architectures must ensure that kmalloc'ed buffer is
DMA-safe. Drivers and subsystems depend on it. If an architecture
isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in
the CPU cache is identical to data in main memory),
ARCH_DMA_MINALIGN must be set so that the memory allocator
makes sure that kmalloc'ed buffer doesn't share a cache line with
the others. See arch/arm/include/asm/cache.h as an example.

Note that ARCH_DMA_MINALIGN is about DMA memory alignment
constraints. You don't need to worry about the architecture data
alignment constraints (e.g. the alignment constraints about 64-bit
objects).
”h]”(hì)”}”(hŒARCH_DMA_MINALIGN”h]”hŒARCH_DMA_MINALIGN”…””}”(hjp  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¼hjl  ubhì)”}”(hX¦  Architectures must ensure that kmalloc'ed buffer is
DMA-safe. Drivers and subsystems depend on it. If an architecture
isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in
the CPU cache is identical to data in main memory),
ARCH_DMA_MINALIGN must be set so that the memory allocator
makes sure that kmalloc'ed buffer doesn't share a cache line with
the others. See arch/arm/include/asm/cache.h as an example.”h]”hX°  Architectures must ensure that kmallocâ€™ed buffer is
DMA-safe. Drivers and subsystems depend on it. If an architecture
isnâ€™t fully DMA-coherent (i.e. hardware doesnâ€™t ensure that data in
the CPU cache is identical to data in main memory),
ARCH_DMA_MINALIGN must be set so that the memory allocator
makes sure that kmallocâ€™ed buffer doesnâ€™t share a cache line with
the others. See arch/arm/include/asm/cache.h as an example.”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´M¾hjl  ubhì)”}”(hŒÇNote that ARCH_DMA_MINALIGN is about DMA memory alignment
constraints. You don't need to worry about the architecture data
alignment constraints (e.g. the alignment constraints about 64-bit
objects).”h]”hŒÉNote that ARCH_DMA_MINALIGN is about DMA memory alignment
constraints. You donâ€™t need to worry about the architecture data
alignment constraints (e.g. the alignment constraints about 64-bit
objects).”…””}”(hjŒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÆhjl  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÖ  hjC  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jÑ  hj$  h²hh³hÊh´M·ubeh}”(h]”Œplatform-issues”ah ]”h"]”Œplatform issues”ah$]”h&]”uh1hµhh·h²hh³hÊh´M±ubh¶)”}”(hhh]”(h»)”}”(hŒClosing”h]”hŒClosing”…””}”(hj±  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj®  h²hh³hÊh´MÌubhì)”}”(hŒÙThis document, and the API itself, would not be in its current
form without the feedback and suggestions from numerous individuals.
We would like to specifically mention, in no particular order, the
following people::”h]”hŒØThis document, and the API itself, would not be in its current
form without the feedback and suggestions from numerous individuals.
We would like to specifically mention, in no particular order, the
following people:”…””}”(hj¿  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hëh³hÊh´MÎhj®  h²hubj/  )”}”(hXK  Russell King <rmk@arm.linux.org.uk>
Leo Dagum <dagum@barrel.engr.sgi.com>
Ralf Baechle <ralf@oss.sgi.com>
Grant Grundler <grundler@cup.hp.com>
Jay Estabrook <Jay.Estabrook@compaq.com>
Thomas Sailer <sailer@ife.ee.ethz.ch>
Andrea Arcangeli <andrea@suse.de>
Jens Axboe <jens.axboe@oracle.com>
David Mosberger-Tang <davidm@hpl.hp.com>”h]”hXK  Russell King <rmk@arm.linux.org.uk>
Leo Dagum <dagum@barrel.engr.sgi.com>
Ralf Baechle <ralf@oss.sgi.com>
Grant Grundler <grundler@cup.hp.com>
Jay Estabrook <Jay.Estabrook@compaq.com>
Thomas Sailer <sailer@ife.ee.ethz.ch>
Andrea Arcangeli <andrea@suse.de>
Jens Axboe <jens.axboe@oracle.com>
David Mosberger-Tang <davidm@hpl.hp.com>”…””}”hjÍ  sbah}”(h]”h ]”h"]”h$]”h&]”j>  j?  uh1j.  h³hÊh´MÓhj®  h²hubeh}”(h]”Œclosing”ah ]”h"]”Œclosing”ah$]”h&]”uh1hµhh·h²hh³hÊh´MÌubeh}”(h]”Œdynamic-dma-mapping-guide”ah ]”h"]”Œdynamic dma mapping guide”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÊŒ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jè  jå  jÃ  jÀ  j0  j-  jû  jø  j!  j  jÔ  jÑ  jO	  jL	  j
  jÿ	  j5  j2  j  j  j!  j  j«  j¨  jà  jÝ  uŒ	nametypes”}”(jè  ‰jÃ  ‰j0  ‰jû  ‰j!  ‰jÔ  ‰jO	  ‰j
  ‰j5  ‰j  ‰j!  ‰j«  ‰jà  ‰uh}”(jå  h·jÀ  jµ  j-  jÆ  jø  j3  j  jþ  jÑ  j$  jL	  j×  jÿ	  jR	  j2  j
  j  j8  j  j  j¨  j$  jÝ  j®  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.