sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget#/translations/zh_CN/arch/xtensa/mmumodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/zh_TW/arch/xtensa/mmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/it_IT/arch/xtensa/mmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ja_JP/arch/xtensa/mmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/ko_KR/arch/xtensa/mmumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget#/translations/sp_SP/arch/xtensa/mmumodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hMMUv3 initialization sequenceh]hMMUv3 initialization sequence}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhh=/var/lib/git/docbuild/linux/Documentation/arch/xtensa/mmu.rsthKubh paragraph)}(hX5The code in the initialize_mmu macro sets up MMUv3 memory mapping identically to MMUv2 fixed memory mapping. Depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is located in addresses it was linked for (symbol undefined), or not (symbol defined), so it needs to be position-independent.h]hX5The code in the initialize_mmu macro sets up MMUv3 memory mapping identically to MMUv2 fixed memory mapping. Depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is located in addresses it was linked for (symbol undefined), or not (symbol defined), so it needs to be position-independent.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h'The code has the following assumptions:h]h'The code has the following assumptions:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh block_quote)}(hX- This code fragment is run only on an MMU v3. - TLBs are in their reset state. - ITLBCFG and DTLBCFG are zero (reset state). - RASID is 0x04030201 (reset state). - PS.RING is zero (reset state). - LITBASE is zero (reset state, PC-relative literals); required to be PIC. h]h bullet_list)}(hhh](h list_item)}(h,This code fragment is run only on an MMU v3.h]h)}(hhh]h,This code fragment is run only on an MMU v3.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hTLBs are in their reset state.h]h)}(hhh]hTLBs are in their reset state.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h+ITLBCFG and DTLBCFG are zero (reset state).h]h)}(hjh]h+ITLBCFG and DTLBCFG are zero (reset state).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhubh)}(h"RASID is 0x04030201 (reset state).h]h)}(hj)h]h"RASID is 0x04030201 (reset state).}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hPS.RING is zero (reset state).h]h)}(hj@h]hPS.RING is zero (reset state).}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj>ubah}(h]h ]h"]h$]h&]uh1hhhubh)}(hILITBASE is zero (reset state, PC-relative literals); required to be PIC. h]h)}(hHLITBASE is zero (reset state, PC-relative literals); required to be PIC.h]hHLITBASE is zero (reset state, PC-relative literals); required to be PIC.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjUubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(h-TLB setup proceeds along the following steps.h]h-TLB setup proceeds along the following steps.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hLegend: - VA = virtual address (two upper nibbles of it); - PA = physical address (two upper nibbles of it); - pc = physical range that contains this code; h](h)}(hLegend:h]hLegend:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h- VA = virtual address (two upper nibbles of it); - PA = physical address (two upper nibbles of it); - pc = physical range that contains this code; h]h)}(hhh](h)}(h/VA = virtual address (two upper nibbles of it);h]h)}(hjh]h/VA = virtual address (two upper nibbles of it);}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h0PA = physical address (two upper nibbles of it);h]h)}(hjh]h0PA = physical address (two upper nibbles of it);}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h-pc = physical range that contains this code; h]h)}(h,pc = physical range that contains this code;h]h,pc = physical range that contains this code;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jsjtuh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXyAfter step 2, we jump to virtual address in the range 0x40000000..0x5fffffff or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below 0x40000000 or above. That address corresponds to next instruction to execute in this code. After step 4, we jump to intended (linked) address of this code. The scheme below assumes that the kernel is loaded below 0x40000000.h]hXyAfter step 2, we jump to virtual address in the range 0x40000000..0x5fffffff or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below 0x40000000 or above. That address corresponds to next instruction to execute in this code. After step 4, we jump to intended (linked) address of this code. The scheme below assumes that the kernel is loaded below 0x40000000.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX{====== ===== ===== ===== ===== ====== ===== ===== - Step0 Step1 Step2 Step3 Step4 Step5 VA PA PA PA PA VA PA PA ====== ===== ===== ===== ===== ====== ===== ===== E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0 C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0 A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00 60..7F -> 60 -> 60 -> 60 40..5F -> 40 -> pc -> pc 40..5F -> pc 20..3F -> 20 -> 20 -> 20 00..1F -> 00 -> 00 -> 00 ====== ===== ===== ===== ===== ====== ===== ===== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubhthead)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hhh]h)}(hhh]h}(h]h ]h"]h$]h&]uh1hhjwubah}(h]h ]h"]h$]h&]jsjtuh1hhhhK#hjtubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep0h]hStep0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep1h]hStep1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep2h]hStep2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep3h]hStep3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep4h]hStep4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jrhjoubjs)}(hhh]h)}(hStep5h]hStep5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hj ubah}(h]h ]h"]h$]h&]uh1jrhjoubeh}(h]h ]h"]h$]h&]uh1jmhjjubjn)}(hhh](js)}(hhh]h)}(hVAh]hVA}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hj+ubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjBubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjYubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjpubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hVAh]hVA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jrhj(ubjs)}(hhh]h)}(hPAh]hPA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jrhj(ubeh}(h]h ]h"]h$]h&]uh1jmhjjubeh}(h]h ]h"]h$]h&]uh1jhhjubhtbody)}(hhh](jn)}(hhh](js)}(hhh]h)}(hE0..FFh]hE0..FF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> E0h]h-> E0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> E0h]h-> E0}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hj%ubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> E0h]h-> E0}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hj<ubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(hF0..FFh]hF0..FF}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hj\ubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> F0h]h-> F0}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjsubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> F0h]h-> F0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(hC0..DFh]hC0..DF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> C0h]h-> C0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> C0h]h-> C0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> C0h]h-> C0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(hE0..EFh]hE0..EF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> F0h]h-> F0}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hj&ubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> F0h]h-> F0}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hj=ubah}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(hA0..BFh]hA0..BF}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hj]ubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(h-> A0h]h-> A0}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjtubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(h-> A0h]h-> A0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(h-> A0h]h-> A0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(hD8..DFh]hD8..DF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jrhjZubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jrhjZubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(h80..9Fh]h80..9F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(h-> 80h]h-> 80}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj'ubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(h-> 80h]h-> 80}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj>ubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(h-> 80h]h-> 80}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjUubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(hD0..D7h]hD0..D7}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjuubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jrhj ubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jrhj ubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(h60..7Fh]h60..7F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 60h]h-> 60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 60h]h-> 60}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 60h]h-> 60}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(h40..5Fh]h40..5F}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjLubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h)}(h-> 40h]h-> 40}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjcubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h)}(h-> pch]h-> pc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h)}(h-> pch]h-> pc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h)}(h40..5Fh]h40..5F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h)}(h-> pch]h-> pc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jrhjIubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjIubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(h20..3Fh]h20..3F}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 20h]h-> 20}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 20h]h-> 20}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h)}(h-> 20h]h-> 20}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hj6ubah}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjubeh}(h]h ]h"]h$]h&]uh1jmhjubjn)}(hhh](js)}(hhh]h)}(h00..1Fh]h00..1F}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjzubah}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h)}(h-> 00h]h-> 00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjubah}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjwubjs)}(hhh]h}(h]h ]h"]h$]h&]uh1jrhjwubeh}(h]h ]h"]h$]h&]uh1jmhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1hhhhK"hhhhubh)}(hXThe default location of IO peripherals is above 0xf0000000. This may be changed using a "ranges" property in a device tree simple-bus node. See the Devicetree Specification, section 4.5 for details on the syntax and semantics of simple-bus nodes. The following limitations apply:h]hXThe default location of IO peripherals is above 0xf0000000. This may be changed using a “ranges” property in a device tree simple-bus node. See the Devicetree Specification, section 4.5 for details on the syntax and semantics of simple-bus nodes. The following limitations apply:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hhhhubhenumerated_list)}(hhh](h)}(h/Only top level simple-bus nodes are considered h]h)}(h.Only top level simple-bus nodes are consideredh]h.Only top level simple-bus nodes are considered}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hj, ubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhNubh)}(h/Only one (first) simple-bus node is considered h]h)}(h.Only one (first) simple-bus node is consideredh]h.Only one (first) simple-bus node is considered}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjD ubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhNubh)}(h,Empty "ranges" properties are not supported h]h)}(h+Empty "ranges" properties are not supportedh]h/Empty “ranges” properties are not supported}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj\ ubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhNubh)}(h>Only the first triplet in the "ranges" property is considered h]h)}(h=Only the first triplet in the "ranges" property is consideredh]hAOnly the first triplet in the “ranges” property is considered}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhNubh)}(hqThe IO area covers the entire 256MB segment of parent-bus-address; the "ranges" triplet length field is ignored h]h)}(hoThe IO area covers the entire 256MB segment of parent-bus-address; the "ranges" triplet length field is ignoredh]hsThe IO area covers the entire 256MB segment of parent-bus-address; the “ranges” triplet length field is ignored}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hj ubah}(h]h ]h"]h$]h&]uh1hhj) hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j' hhhhhhhK6ubh)}(hhh](h)}(hMMUv3 address space layouts.h]hMMUv3 address space layouts.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKEubh)}(h!Default MMUv2-compatible layout::h]h Default MMUv2-compatible layout:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj hhubh literal_block)}(hXr Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0xcffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+h]hXr Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0xcffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+}hj sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1j hhhKIhj hhubh)}(h&256MB cached + 256MB uncached layout::h]h%256MB cached + 256MB uncached layout:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhj hhubj )}(hX Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0xaffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB +------------------+ +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+h]hX Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0xaffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB +------------------+ +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+}hj sbah}(h]h ]h"]h$]h&]j j uh1j hhhKthj hhubh)}(h&512MB cached + 512MB uncached layout::h]h%512MB cached + 512MB uncached layout:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj )}(hXr Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0x9ffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+h]hXr Symbol VADDR Size +------------------+ | Userspace | 0x00000000 TASK_SIZE +------------------+ 0x40000000 +------------------+ | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE +------------------+ | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE +------------------+ 0x8e400000 +------------------+ | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB +------------------+ VMALLOC_END +------------------+ | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE | remap area 1 | +------------------+ | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE | remap area 2 | +------------------+ +------------------+ | KMAP area | PKMAP_BASE PTRS_PER_PTE * | | DCACHE_N_COLORS * | | PAGE_SIZE | | (4MB * DCACHE_N_COLORS) +------------------+ | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * | | NR_CPUS * | | DCACHE_N_COLORS * | | PAGE_SIZE +------------------+ FIXADDR_TOP 0x9ffff000 +------------------+ | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB +------------------+ | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB +------------------+ | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB +------------------+ | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB +------------------+}hj" sbah}(h]h ]h"]h$]h&]j j uh1j hhhKhj hhubeh}(h]mmuv3-address-space-layoutsah ]h"]mmuv3 address space layouts.ah$]h&]uh1hhhhhhhhKEubeh}(h]mmuv3-initialization-sequenceah ]h"]mmuv3 initialization sequenceah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjrfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjb error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j= j: j5 j2 u nametypes}(j= j5 uh}(j: hj2 j u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.