€•¯8Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/pt_BR/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/arch/xtensa/atomctl”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ+Atomic Operation Control (ATOMCTL) Register”h]”hŒ+Atomic Operation Control (ATOMCTL) Register”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³ŒA/var/lib/git/docbuild/linux/Documentation/arch/xtensa/atomctl.rst”h´KubhŒ paragraph”“”)”}”(hŒ”We Have Atomic Operation Control (ATOMCTL) Register. This register determines the effect of using a S32C1I instruction with various combinations of:”h]”hŒ”We Have Atomic Operation Control (ATOMCTL) Register. This register determines the effect of using a S32C1I instruction with various combinations of:”…””}”(hhÍh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhŒ block_quote”“”)”}”(hŒÑ1. With and without an Coherent Cache Controller which can do Atomic Transactions to the memory internally. 2. With and without An Intelligent Memory Controller which can do Atomic Transactions itself. ”h]”hŒenumerated_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒiWith and without an Coherent Cache Controller which can do Atomic Transactions to the memory internally. ”h]”hÌ)”}”(hŒhWith and without an Coherent Cache Controller which can do Atomic Transactions to the memory internally.”h]”hŒhWith and without an Coherent Cache Controller which can do Atomic Transactions to the memory internally.”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hhèubah}”(h]”h ]”h"]”h$]”h&]”uh1hæhhãubhç)”}”(hŒ[With and without An Intelligent Memory Controller which can do Atomic Transactions itself. ”h]”hÌ)”}”(hŒZWith and without An Intelligent Memory Controller which can do Atomic Transactions itself.”h]”hŒZWith and without An Intelligent Memory Controller which can do Atomic Transactions itself.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hjubah}”(h]”h ]”h"]”h$]”h&]”uh1hæhhãubeh}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1háhhÝubah}”(h]”h ]”h"]”h$]”h&]”uh1hÛh³hÊh´K hh·h²hubhÌ)”}”(hŒLThe Core comes up with a default value of for the three types of cache ops::”h]”hŒKThe Core comes up with a default value of for the three types of cache ops:”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhŒ literal_block”“”)”}”(hŒ00x28: (WB: Internal, WT: Internal, BY:Exception)”h]”hŒ00x28: (WB: Internal, WT: Internal, BY:Exception)”…””}”hj9sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1j7h³hÊh´Khh·h²hubhÌ)”}”(hX&On the FPGA Cards we typically simulate an Intelligent Memory controller which can implement RCW transactions. For FPGA cards with an External Memory controller we let it to the atomic operations internally while doing a Cached (WB) transaction and use the Memory RCW for un-cached operations.”h]”hX&On the FPGA Cards we typically simulate an Intelligent Memory controller which can implement RCW transactions. For FPGA cards with an External Memory controller we let it to the atomic operations internally while doing a Cached (WB) transaction and use the Memory RCW for un-cached operations.”…””}”(hjIh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhÌ)”}”(hŒ¤For systems without an coherent cache controller, non-MX, we always use the memory controllers RCW, though non-MX controllers likely support the Internal Operation.”h]”hŒ¤For systems without an coherent cache controller, non-MX, we always use the memory controllers RCW, though non-MX controllers likely support the Internal Operation.”…””}”(hjWh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒÆCUSTOMER-WARNING: Virtually all customers buy their memory controllers from vendors that don't support atomic RCW memory transactions and will likely want to configure this register to not use RCW. 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problems.”…””}”(hj¥h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K"hh·h²hubhÌ)”}”(hŒ#See Section 4.3.12.4 of ISA; Bits::”h]”hŒ"See Section 4.3.12.4 of ISA; Bits:”…””}”(hj³h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K%hh·h²hubj8)”}”(hŒ) WB WT BY 5 4 | 3 2 | 1 0”h]”hŒ) WB WT BY 5 4 | 3 2 | 1 0”…””}”hjÁsbah}”(h]”h ]”h"]”h$]”h&]”jGjHuh1j7h³hÊh´K'hh·h²hubhŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K uh1jÙhjÖubjÚ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jÙhjÖubjÚ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jÙhjÖubjÚ)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jÙhjÖubhŒthead”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hÌ)”}”(hŒ2 Bit”h]”hŒ2 Bit”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K+hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubj)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”uh1j hj ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhjubj 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