v}sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget(/translations/zh_CN/arch/x86/x86_64/fsgsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/zh_TW/arch/x86/x86_64/fsgsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/it_IT/arch/x86/x86_64/fsgsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/ja_JP/arch/x86/x86_64/fsgsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/ko_KR/arch/x86/x86_64/fsgsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget(/translations/sp_SP/arch/x86/x86_64/fsgsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhB/var/lib/git/docbuild/linux/Documentation/arch/x86/x86_64/fsgs.rsthKubhsection)}(hhh](htitle)}(h3Using FS and GS segments in user space applicationsh]h3Using FS and GS segments in user space applications}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe x86 architecture supports segmentation. Instructions which access memory can use segment register based addressing mode. The following notation is used to address a byte within a segment:h]hThe x86 architecture supports segmentation. Instructions which access memory can use segment register based addressing mode. The following notation is used to address a byte within a segment:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hSegment-register:Byte-address h]h)}(hSegment-register:Byte-addressh]hSegment-register:Byte-address}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hX;The segment base address is added to the Byte-address to compute the resulting virtual address which is accessed. This allows to access multiple instances of data with the identical Byte-address, i.e. the same code. The selection of a particular instance is purely based on the base-address in the segment register.h]hX;The segment base address is added to the Byte-address to compute the resulting virtual address which is accessed. This allows to access multiple instances of data with the identical Byte-address, i.e. the same code. The selection of a particular instance is purely based on the base-address in the segment register.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hIn 32-bit mode the CPU provides 6 segments, which also support segment limits. The limits can be used to enforce address space protections.h]hIn 32-bit mode the CPU provides 6 segments, which also support segment limits. The limits can be used to enforce address space protections.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hIn 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is always 0 to provide a full 64bit address space. The FS and GS segments are still functional in 64-bit mode.h]hIn 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is always 0 to provide a full 64bit address space. The FS and GS segments are still functional in 64-bit mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hCommon FS and GS usageh]hCommon FS and GS usage}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXAThe FS segment is commonly used to address Thread Local Storage (TLS). FS is usually managed by runtime code or a threading library. Variables declared with the '__thread' storage class specifier are instantiated per thread and the compiler emits the FS: address prefix for accesses to these variables. Each thread has its own FS base address so common code can be used without complex address offset calculations to access the per thread instances. Applications should not use FS for other purposes when they use runtimes or threading libraries which manage the per thread FS.h]hXEThe FS segment is commonly used to address Thread Local Storage (TLS). FS is usually managed by runtime code or a threading library. Variables declared with the ‘__thread’ storage class specifier are instantiated per thread and the compiler emits the FS: address prefix for accesses to these variables. Each thread has its own FS base address so common code can be used without complex address offset calculations to access the per thread instances. Applications should not use FS for other purposes when they use runtimes or threading libraries which manage the per thread FS.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThe GS segment has no common use and can be used freely by applications. GCC and Clang support GS based addressing via address space identifiers.h]hThe GS segment has no common use and can be used freely by applications. GCC and Clang support GS based addressing via address space identifiers.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjhhubeh}(h]common-fs-and-gs-usageah ]h"]common fs and gs usageah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h*Reading and writing the FS/GS base addressh]h*Reading and writing the FS/GS base address}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhhhhhK*ubh)}(hDThere exist two mechanisms to read and write the FS/GS base address:h]hDThere exist two mechanisms to read and write the FS/GS base address:}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjRhhubh)}(hB- the arch_prctl() system call - the FSGSBASE instruction family h]h bullet_list)}(hhh](h list_item)}(hthe arch_prctl() system call h]h)}(hthe arch_prctl() system callh]hthe arch_prctl() system call}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hj|ubah}(h]h ]h"]h$]h&]uh1jzhjwubj{)}(h the FSGSBASE instruction family h]h)}(hthe FSGSBASE instruction familyh]hthe FSGSBASE instruction family}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jzhjwubeh}(h]h ]h"]h$]h&]bullet-uh1juhhhK.hjqubah}(h]h ]h"]h$]h&]uh1hhhhK.hjRhhubeh}(h]*reading-and-writing-the-fs-gs-base-addressah ]h"]*reading and writing the fs/gs base addressah$]h&]uh1hhhhhhhhK*ubh)}(hhh](h)}(h&Accessing FS/GS base with arch_prctl()h]h&Accessing FS/GS base with arch_prctl()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK3ubh)}(hXqThe arch_prctl(2) based mechanism is available on all 64-bit CPUs and all kernel versions. Reading the base: arch_prctl(ARCH_GET_FS, &fsbase); arch_prctl(ARCH_GET_GS, &gsbase); Writing the base: arch_prctl(ARCH_SET_FS, fsbase); arch_prctl(ARCH_SET_GS, gsbase); The ARCH_SET_GS prctl may be disabled depending on kernel configuration and security settings. h](h)}(hZThe arch_prctl(2) based mechanism is available on all 64-bit CPUs and all kernel versions.h]hZThe arch_prctl(2) based mechanism is available on all 64-bit CPUs and all kernel versions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubh)}(hReading the base:h]hReading the base:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hjubh)}(hDarch_prctl(ARCH_GET_FS, &fsbase); arch_prctl(ARCH_GET_GS, &gsbase); h]h)}(hCarch_prctl(ARCH_GET_FS, &fsbase); arch_prctl(ARCH_GET_GS, &gsbase);h]hCarch_prctl(ARCH_GET_FS, &fsbase); arch_prctl(ARCH_GET_GS, &gsbase);}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubh)}(hWriting the base:h]hWriting the base:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubh)}(hBarch_prctl(ARCH_SET_FS, fsbase); arch_prctl(ARCH_SET_GS, gsbase); h]h)}(hAarch_prctl(ARCH_SET_FS, fsbase); arch_prctl(ARCH_SET_GS, gsbase);h]hAarch_prctl(ARCH_SET_FS, fsbase); arch_prctl(ARCH_SET_GS, gsbase);}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubah}(h]h ]h"]h$]h&]uh1hhhhK?hjubh)}(h^The ARCH_SET_GS prctl may be disabled depending on kernel configuration and security settings.h]h^The ARCH_SET_GS prctl may be disabled depending on kernel configuration and security settings.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhjubeh}(h]h ]h"]h$]h&]uh1hhhhK5hjhhubeh}(h]$accessing-fs-gs-base-with-arch-prctlah ]h"]&accessing fs/gs base with arch_prctl()ah$]h&]uh1hhhhhhhhK3ubh)}(hhh](h)}(h3Accessing FS/GS base with the FSGSBASE instructionsh]h3Accessing FS/GS base with the FSGSBASE instructions}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhKFubh)}(hX0With the Ivy Bridge CPU generation Intel introduced a new set of instructions to access the FS and GS base registers directly from user space. These instructions are also supported on AMD Family 17H CPUs. The following instructions are available: =============== =========================== RDFSBASE %reg Read the FS base register RDGSBASE %reg Read the GS base register WRFSBASE %reg Write the FS base register WRGSBASE %reg Write the GS base register =============== =========================== The instructions avoid the overhead of the arch_prctl() syscall and allow more flexible usage of the FS/GS addressing modes in user space applications. This does not prevent conflicts between threading libraries and runtimes which utilize FS and applications which want to use it for their own purpose. h](h)}(hWith the Ivy Bridge CPU generation Intel introduced a new set of instructions to access the FS and GS base registers directly from user space. These instructions are also supported on AMD Family 17H CPUs. The following instructions are available:h]hWith the Ivy Bridge CPU generation Intel introduced a new set of instructions to access the FS and GS base registers directly from user space. These instructions are also supported on AMD Family 17H CPUs. The following instructions are available:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhj^ubh)}(hX=============== =========================== RDFSBASE %reg Read the FS base register RDGSBASE %reg Read the GS base register WRFSBASE %reg Write the FS base register WRGSBASE %reg Write the GS base register =============== =========================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j~hj{ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j~hj{ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h RDFSBASE %regh]h RDFSBASE %reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRead the FS base registerh]hRead the FS base register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h RDGSBASE %regh]h RDGSBASE %reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRead the GS base registerh]hRead the GS base register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h WRFSBASE %regh]h WRFSBASE %reg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hWrite the FS base registerh]hWrite the FS base register}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhj%ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h WRGSBASE %regh]h WRGSBASE %reg}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjEubah}(h]h ]h"]h$]h&]uh1jhjBubj)}(hhh]h)}(hWrite the GS base registerh]hWrite the GS base register}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhj\ubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]colsKuh1jyhjvubah}(h]h ]h"]h$]h&]uh1jthjpubah}(h]h ]h"]h$]h&]uh1hhhhKMhj^ubh)}(hX.The instructions avoid the overhead of the arch_prctl() syscall and allow more flexible usage of the FS/GS addressing modes in user space applications. This does not prevent conflicts between threading libraries and runtimes which utilize FS and applications which want to use it for their own purpose.h]hX.The instructions avoid the overhead of the arch_prctl() syscall and allow more flexible usage of the FS/GS addressing modes in user space applications. This does not prevent conflicts between threading libraries and runtimes which utilize FS and applications which want to use it for their own purpose.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThj^ubeh}(h]h ]h"]h$]h&]uh1hhhhKHhjMhhubh)}(hhh](h)}(h FSGSBASE instructions enablementh]h FSGSBASE instructions enablement}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK[ubh)}(hXThe instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If available /proc/cpuinfo shows 'fsgsbase' in the flag entry of the CPUs. The availability of the instructions does not enable them automatically. The kernel has to enable them explicitly in CR4. The reason for this is that older kernels make assumptions about the values in the GS register and enforce them when GS base is set via arch_prctl(). Allowing user space to write arbitrary values to GS base would violate these assumptions and cause malfunction. On kernels which do not enable FSGSBASE the execution of the FSGSBASE instructions will fault with a #UD exception. The kernel provides reliable information about the enabled state in the ELF AUX vector. If the HWCAP2_FSGSBASE bit is set in the AUX vector, the kernel has FSGSBASE instructions enabled and applications can use them. The following code example shows how this detection works:: #include #include /* Will be eventually in asm/hwcap.h */ #ifndef HWCAP2_FSGSBASE #define HWCAP2_FSGSBASE (1 << 1) #endif .... unsigned val = getauxval(AT_HWCAP2); if (val & HWCAP2_FSGSBASE) printf("FSGSBASE enabled\n"); h](h)}(hThe instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If available /proc/cpuinfo shows 'fsgsbase' in the flag entry of the CPUs.h]hThe instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If available /proc/cpuinfo shows ‘fsgsbase’ in the flag entry of the CPUs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK\hjubh)}(hXThe availability of the instructions does not enable them automatically. The kernel has to enable them explicitly in CR4. The reason for this is that older kernels make assumptions about the values in the GS register and enforce them when GS base is set via arch_prctl(). Allowing user space to write arbitrary values to GS base would violate these assumptions and cause malfunction.h]hXThe availability of the instructions does not enable them automatically. The kernel has to enable them explicitly in CR4. The reason for this is that older kernels make assumptions about the values in the GS register and enforce them when GS base is set via arch_prctl(). Allowing user space to write arbitrary values to GS base would violate these assumptions and cause malfunction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubh)}(hsOn kernels which do not enable FSGSBASE the execution of the FSGSBASE instructions will fault with a #UD exception.h]hsOn kernels which do not enable FSGSBASE the execution of the FSGSBASE instructions will fault with a #UD exception.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubh)}(hXThe kernel provides reliable information about the enabled state in the ELF AUX vector. If the HWCAP2_FSGSBASE bit is set in the AUX vector, the kernel has FSGSBASE instructions enabled and applications can use them. The following code example shows how this detection works::h]hXThe kernel provides reliable information about the enabled state in the ELF AUX vector. If the HWCAP2_FSGSBASE bit is set in the AUX vector, the kernel has FSGSBASE instructions enabled and applications can use them. The following code example shows how this detection works:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubh literal_block)}(hX#include #include /* Will be eventually in asm/hwcap.h */ #ifndef HWCAP2_FSGSBASE #define HWCAP2_FSGSBASE (1 << 1) #endif .... unsigned val = getauxval(AT_HWCAP2); if (val & HWCAP2_FSGSBASE) printf("FSGSBASE enabled\n");h]hX#include #include /* Will be eventually in asm/hwcap.h */ #ifndef HWCAP2_FSGSBASE #define HWCAP2_FSGSBASE (1 << 1) #endif .... unsigned val = getauxval(AT_HWCAP2); if (val & HWCAP2_FSGSBASE) printf("FSGSBASE enabled\n");}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKnhjubeh}(h]h ]h"]h$]h&]uh1hhhhK\hjhhubeh}(h] fsgsbase-instructions-enablementah ]h"] fsgsbase instructions enablementah$]h&]uh1hhjMhhhhhK[ubh)}(hhh](h)}(h&FSGSBASE instructions compiler supporth]h&FSGSBASE instructions compiler support}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK~ubh)}(hlGCC version 4.6.4 and newer provide intrinsics for the FSGSBASE instructions. Clang 5 supports them as well.h]hlGCC version 4.6.4 and newer provide intrinsics for the FSGSBASE instructions. Clang 5 supports them as well.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX=================== =========================== _readfsbase_u64() Read the FS base register _readfsbase_u64() Read the GS base register _writefsbase_u64() Write the FS base register _writegsbase_u64() Write the GS base register =================== =========================== h]ju)}(hhh]jz)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j~hj7ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j~hj7ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h_readfsbase_u64()h]h_readfsbase_u64()}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hRead the FS base registerh]hRead the FS base register}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h_readfsbase_u64()h]h_readfsbase_u64()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRead the GS base registerh]hRead the GS base register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h_writefsbase_u64()h]h_writefsbase_u64()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hWrite the FS base registerh]hWrite the FS base register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh](j)}(hhh]h)}(h_writegsbase_u64()h]h_writegsbase_u64()}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hWrite the GS base registerh]hWrite the GS base register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]colsKuh1jyhj4ubah}(h]h ]h"]h$]h&]uh1jthj0ubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hTo utilize these intrinsics must be included in the source code and the compiler option -mfsgsbase has to be added.h]hTo utilize these intrinsics must be included in the source code and the compiler option -mfsgsbase has to be added.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]&fsgsbase-instructions-compiler-supportah ]h"]&fsgsbase instructions compiler supportah$]h&]uh1hhjMhhhhhK~ubeh}(h]3accessing-fs-gs-base-with-the-fsgsbase-instructionsah ]h"]3accessing fs/gs base with the fsgsbase instructionsah$]h&]uh1hhhhhhhhKFubh)}(hhh](h)}(h+Compiler support for FS/GS based addressingh]h+Compiler support for FS/GS based addressing}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdhhhhhKubh)}(hGCC version 6 and newer provide support for FS/GS based addressing via Named Address Spaces. GCC implements the following address space identifiers for x86:h]hGCC version 6 and newer provide support for FS/GS based addressing via Named Address Spaces. GCC implements the following address space identifiers for x86:}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(h========= ==================================== __seg_fs Variable is addressed relative to FS __seg_gs Variable is addressed relative to GS ========= ==================================== h]ju)}(hhh]jz)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1j~hjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1j~hjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h__seg_fsh]h__seg_fs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Variable is addressed relative to FSh]h$Variable is addressed relative to FS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h__seg_gsh]h__seg_gs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Variable is addressed relative to GSh]h$Variable is addressed relative to GS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jyhjubah}(h]h ]h"]h$]h&]uh1jthjubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hThe preprocessor symbols __SEG_FS and __SEG_GS are defined when these address spaces are supported. Code which implements fallback modes should check whether these symbols are defined. Usage example::h]hThe preprocessor symbols __SEG_FS and __SEG_GS are defined when these address spaces are supported. Code which implements fallback modes should check whether these symbols are defined. Usage example:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubj)}(hX#ifdef __SEG_GS long data0 = 0; long data1 = 1; long __seg_gs *ptr; /* Check whether FSGSBASE is enabled by the kernel (HWCAP2_FSGSBASE) */ .... /* Set GS base to point to data0 */ _writegsbase_u64(&data0); /* Access offset 0 of GS */ ptr = 0; printf("data0 = %ld\n", *ptr); /* Set GS base to point to data1 */ _writegsbase_u64(&data1); /* ptr still addresses offset 0! */ printf("data1 = %ld\n", *ptr);h]hX#ifdef __SEG_GS long data0 = 0; long data1 = 1; long __seg_gs *ptr; /* Check whether FSGSBASE is enabled by the kernel (HWCAP2_FSGSBASE) */ .... /* Set GS base to point to data0 */ _writegsbase_u64(&data0); /* Access offset 0 of GS */ ptr = 0; printf("data0 = %ld\n", *ptr); /* Set GS base to point to data1 */ _writegsbase_u64(&data1); /* ptr still addresses offset 0! */ printf("data1 = %ld\n", *ptr);}hj9sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjdhhubh)}(hClang does not provide the GCC address space identifiers, but it provides address spaces via an attribute based mechanism in Clang 2.6 and newer versions:h]hClang does not provide the GCC address space identifiers, but it provides address spaces via an attribute based mechanism in Clang 2.6 and newer versions:}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubh)}(hX*==================================== ===================================== __attribute__((address_space(256)) Variable is addressed relative to GS __attribute__((address_space(257)) Variable is addressed relative to FS ==================================== ===================================== h]ju)}(hhh]jz)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthK$uh1j~hj\ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK%uh1j~hj\ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h"__attribute__((address_space(256))h]h"__attribute__((address_space(256))}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjyubah}(h]h ]h"]h$]h&]uh1jhjvubj)}(hhh]h)}(h$Variable is addressed relative to GSh]h$Variable is addressed relative to GS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jhjsubj)}(hhh](j)}(hhh]h)}(h"__attribute__((address_space(257))h]h"__attribute__((address_space(257))}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Variable is addressed relative to FSh]h$Variable is addressed relative to FS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]colsKuh1jyhjYubah}(h]h ]h"]h$]h&]uh1jthjUubah}(h]h ]h"]h$]h&]uh1hhhhKhjdhhubeh}(h]+compiler-support-for-fs-gs-based-addressingah ]h"]+compiler support for fs/gs based addressingah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h+FS/GS based addressing with inline assemblyh]h+FS/GS based addressing with inline assembly}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hsIn case the compiler does not support address spaces, inline assembly can be used for FS/GS based addressing mode::h]hrIn case the compiler does not support address spaces, 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