€•ñ©      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ /translations/zh_CN/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/zh_TW/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/it_IT/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/ja_JP/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/ko_KR/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/pt_BR/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/sp_SP/arch/x86/sva”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³Œ:/var/lib/git/docbuild/linux/Documentation/arch/x86/sva.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ+Shared Virtual Addressing (SVA) with ENQCMD”h]”hŒ+Shared Virtual Addressing (SVA) with ENQCMD”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ
Background”h]”hŒ
Background”…””}”(hhàh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÝh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒêShared Virtual Addressing (SVA) allows the processor and device to use the
same virtual addresses avoiding the need for software to translate virtual
addresses to physical addresses. SVA is what PCIe calls Shared Virtual
Memory (SVM).”h]”hŒêShared Virtual Addressing (SVA) allows the processor and device to use the
same virtual addresses avoiding the need for software to translate virtual
addresses to physical addresses. SVA is what PCIe calls Shared Virtual
Memory (SVM).”…””}”(hhðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K
hhÝh²hubhï)”}”(hX‡  In addition to the convenience of using application virtual addresses
by the device, it also doesn't require pinning pages for DMA.
PCIe Address Translation Services (ATS) along with Page Request Interface
(PRI) allow devices to function much the same way as the CPU handling
application page-faults. For more information please refer to the PCIe
specification Chapter 10: ATS Specification.”h]”hX‰  In addition to the convenience of using application virtual addresses
by the device, it also doesnâ€™t require pinning pages for DMA.
PCIe Address Translation Services (ATS) along with Page Request Interface
(PRI) allow devices to function much the same way as the CPU handling
application page-faults. For more information please refer to the PCIe
specification Chapter 10: ATS Specification.”…””}”(hhþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhhÝh²hubhï)”}”(hX  Use of SVA requires IOMMU support in the platform. IOMMU is also
required to support the PCIe features ATS and PRI. ATS allows devices
to cache translations for virtual addresses. The IOMMU driver uses the
mmu_notifier() support to keep the device TLB cache and the CPU cache in
sync. When an ATS lookup fails for a virtual address, the device should
use the PRI in order to request the virtual address to be paged into the
CPU page tables. The device must use ATS again in order to fetch the
translation before use.”h]”hX  Use of SVA requires IOMMU support in the platform. IOMMU is also
required to support the PCIe features ATS and PRI. ATS allows devices
to cache translations for virtual addresses. The IOMMU driver uses the
mmu_notifier() support to keep the device TLB cache and the CPU cache in
sync. When an ATS lookup fails for a virtual address, the device should
use the PRI in order to request the virtual address to be paged into the
CPU page tables. The device must use ATS again in order to fetch the
translation before use.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhhÝh²hubeh}”(h]”Œ
background”ah ]”h"]”Œ
background”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒShared Hardware Workqueues”h]”hŒShared Hardware Workqueues”…””}”(hj%  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj"  h²hh³hÇh´K ubhï)”}”(hXì  Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
the use of Shared Work Queues (SWQ) by both applications and Virtual
Machines (VM's). This allows better hardware utilization vs. hard
partitioning resources that could result in under utilization. In order to
allow the hardware to distinguish the context for which work is being
executed in the hardware by SWQ interface, SIOV uses Process Address Space
ID (PASID), which is a 20-bit number defined by the PCIe SIG.”h]”hXî  Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
the use of Shared Work Queues (SWQ) by both applications and Virtual
Machines (VMâ€™s). This allows better hardware utilization vs. hard
partitioning resources that could result in under utilization. In order to
allow the hardware to distinguish the context for which work is being
executed in the hardware by SWQ interface, SIOV uses Process Address Space
ID (PASID), which is a 20-bit number defined by the PCIe SIG.”…””}”(hj3  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K"hj"  h²hubhï)”}”(hŒÓPASID value is encoded in all transactions from the device. This allows the
IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
Resource Identifier (RID) which is the Bus/Device/Function.”h]”hŒÓPASID value is encoded in all transactions from the device. This allows the
IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
Resource Identifier (RID) which is the Bus/Device/Function.”…””}”(hjA  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K*hj"  h²hubeh}”(h]”Œshared-hardware-workqueues”ah ]”h"]”Œshared hardware workqueues”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubhÉ)”}”(hhh]”(hÎ)”}”(hŒENQCMD”h]”hŒENQCMD”…””}”(hjZ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjW  h²hh³hÇh´K0ubhï)”}”(hX*  ENQCMD is a new instruction on Intel platforms that atomically submits a
work descriptor to a device. The descriptor includes the operation to be
performed, virtual addresses of all parameters, virtual address of a completion
record, and the PASID (process address space ID) of the current process.”h]”hX*  ENQCMD is a new instruction on Intel platforms that atomically submits a
work descriptor to a device. The descriptor includes the operation to be
performed, virtual addresses of all parameters, virtual address of a completion
record, and the PASID (process address space ID) of the current process.”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K2hjW  h²hubhï)”}”(hX  ENQCMD works with non-posted semantics and carries a status back if the
command was accepted by hardware. This allows the submitter to know if the
submission needs to be retried or other device specific mechanisms to
implement fairness or ensure forward progress should be provided.”h]”hX  ENQCMD works with non-posted semantics and carries a status back if the
command was accepted by hardware. This allows the submitter to know if the
submission needs to be retried or other device specific mechanisms to
implement fairness or ensure forward progress should be provided.”…””}”(hjv  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K7hjW  h²hubhï)”}”(hŒÂENQCMD is the glue that ensures applications can directly submit commands
to the hardware and also permits hardware to be aware of application context
to perform I/O operations via use of PASID.”h]”hŒÂENQCMD is the glue that ensures applications can directly submit commands
to the hardware and also permits hardware to be aware of application context
to perform I/O operations via use of PASID.”…””}”(hj„  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K<hjW  h²hubeh}”(h]”Œenqcmd”ah ]”h"]”Œenqcmd”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K0ubhÉ)”}”(hhh]”(hÎ)”}”(hŒProcess Address Space Tagging”h]”hŒProcess Address Space Tagging”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjš  h²hh³hÇh´KAubhï)”}”(hXK  A new thread-scoped MSR (IA32_PASID) provides the connection between
user processes and the rest of the hardware. When an application first
accesses an SVA-capable device, this MSR is initialized with a newly
allocated PASID. The driver for the device calls an IOMMU-specific API
that sets up the routing for DMA and page-requests.”h]”hXK  A new thread-scoped MSR (IA32_PASID) provides the connection between
user processes and the rest of the hardware. When an application first
accesses an SVA-capable device, this MSR is initialized with a newly
allocated PASID. The driver for the device calls an IOMMU-specific API
that sets up the routing for DMA and page-requests.”…””}”(hj«  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KChjš  h²hubhï)”}”(hŒrFor example, the Intel Data Streaming Accelerator (DSA) uses
iommu_sva_bind_device(), which will do the following:”h]”hŒrFor example, the Intel Data Streaming Accelerator (DSA) uses
iommu_sva_bind_device(), which will do the following:”…””}”(hj¹  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KIhjš  h²hubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒdAllocate the PASID, and program the process page-table (%cr3 register) in the
PASID context entries.”h]”hï)”}”(hŒdAllocate the PASID, and program the process page-table (%cr3 register) in the
PASID context entries.”h]”hŒdAllocate the PASID, and program the process page-table (%cr3 register) in the
PASID context entries.”…””}”(hjÒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KLhjÎ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjÉ  h²hh³hÇh´NubjÍ  )”}”(hXØ  Register for mmu_notifier() to track any page-table invalidations to keep
the device TLB in sync. For example, when a page-table entry is invalidated,
the IOMMU propagates the invalidation to the device TLB. This will force any
future access by the device to this virtual address to participate in
ATS. If the IOMMU responds with proper response that a page is not
present, the device would request the page to be paged in via the PCIe PRI
protocol before performing I/O.
”h]”hï)”}”(hX×  Register for mmu_notifier() to track any page-table invalidations to keep
the device TLB in sync. For example, when a page-table entry is invalidated,
the IOMMU propagates the invalidation to the device TLB. This will force any
future access by the device to this virtual address to participate in
ATS. If the IOMMU responds with proper response that a page is not
present, the device would request the page to be paged in via the PCIe PRI
protocol before performing I/O.”h]”hX×  Register for mmu_notifier() to track any page-table invalidations to keep
the device TLB in sync. For example, when a page-table entry is invalidated,
the IOMMU propagates the invalidation to the device TLB. This will force any
future access by the device to this virtual address to participate in
ATS. If the IOMMU responds with proper response that a page is not
present, the device would request the page to be paged in via the PCIe PRI
protocol before performing I/O.”…””}”(hjê  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KNhjæ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjÉ  h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jÇ  h³hÇh´KLhjš  h²hubhï)”}”(hŒxThis MSR is managed with the XSAVE feature set as "supervisor state" to
ensure the MSR is updated during context switch.”h]”hŒ|This MSR is managed with the XSAVE feature set as â€œsupervisor stateâ€ to
ensure the MSR is updated during context switch.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KVhjš  h²hubeh}”(h]”Œprocess-address-space-tagging”ah ]”h"]”Œprocess address space tagging”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KAubhÉ)”}”(hhh]”(hÎ)”}”(hŒPASID Management”h]”hŒPASID Management”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj  h²hh³hÇh´KZubhï)”}”(hXº  The kernel must allocate a PASID on behalf of each process which will use
ENQCMD and program it into the new MSR to communicate the process identity to
platform hardware.  ENQCMD uses the PASID stored in this MSR to tag requests
from this process.  When a user submits a work descriptor to a device using the
ENQCMD instruction, the PASID field in the descriptor is auto-filled with the
value from MSR_IA32_PASID. Requests for DMA from the device are also tagged
with the same PASID. The platform IOMMU uses the PASID in the transaction to
perform address translation. The IOMMU APIs setup the corresponding PASID
entry in IOMMU with the process address used by the CPU (e.g. %cr3 register in
x86).”h]”hXº  The kernel must allocate a PASID on behalf of each process which will use
ENQCMD and program it into the new MSR to communicate the process identity to
platform hardware.  ENQCMD uses the PASID stored in this MSR to tag requests
from this process.  When a user submits a work descriptor to a device using the
ENQCMD instruction, the PASID field in the descriptor is auto-filled with the
value from MSR_IA32_PASID. Requests for DMA from the device are also tagged
with the same PASID. The platform IOMMU uses the PASID in the transaction to
perform address translation. The IOMMU APIs setup the corresponding PASID
entry in IOMMU with the process address used by the CPU (e.g. %cr3 register in
x86).”…””}”(hj-  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K\hj  h²hubhï)”}”(hŒÅThe MSR must be configured on each logical CPU before any application
thread can interact with a device. Threads that belong to the same
process share the same page tables, thus the same MSR value.”h]”hŒÅThe MSR must be configured on each logical CPU before any application
thread can interact with a device. Threads that belong to the same
process share the same page tables, thus the same MSR value.”…””}”(hj;  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kghj  h²hubeh}”(h]”Œpasid-management”ah ]”h"]”Œpasid management”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KZubhÉ)”}”(hhh]”(hÎ)”}”(hŒPASID Life Cycle Management”h]”hŒPASID Life Cycle Management”…””}”(hjT  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjQ  h²hh³hÇh´Klubhï)”}”(hŒKPASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.”h]”hŒKPASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.”…””}”(hjb  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KnhjQ  h²hubhï)”}”(hX  Only processes that access SVA-capable devices need to have a PASID
allocated. This allocation happens when a process opens/binds an SVA-capable
device but finds no PASID for this process. Subsequent binds of the same, or
other devices will share the same PASID.”h]”hX  Only processes that access SVA-capable devices need to have a PASID
allocated. This allocation happens when a process opens/binds an SVA-capable
device but finds no PASID for this process. Subsequent binds of the same, or
other devices will share the same PASID.”…””}”(hjp  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KphjQ  h²hubhï)”}”(hŒòAlthough the PASID is allocated to the process by opening a device,
it is not active in any of the threads of that process. It's loaded to the
IA32_PASID MSR lazily when a thread tries to submit a work descriptor
to a device using the ENQCMD.”h]”hŒôAlthough the PASID is allocated to the process by opening a device,
it is not active in any of the threads of that process. Itâ€™s loaded to the
IA32_PASID MSR lazily when a thread tries to submit a work descriptor
to a device using the ENQCMD.”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KuhjQ  h²hubhï)”}”(hXU  That first access will trigger a #GP fault because the IA32_PASID MSR
has not been initialized with the PASID value assigned to the process
when the device was opened. The Linux #GP handler notes that a PASID has
been allocated for the process, and so initializes the IA32_PASID MSR
and returns so that the ENQCMD instruction is re-executed.”h]”hXU  That first access will trigger a #GP fault because the IA32_PASID MSR
has not been initialized with the PASID value assigned to the process
when the device was opened. The Linux #GP handler notes that a PASID has
been allocated for the process, and so initializes the IA32_PASID MSR
and returns so that the ENQCMD instruction is re-executed.”…””}”(hjŒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KzhjQ  h²hubhï)”}”(hŒŽOn fork(2) or exec(2) the PASID is removed from the process as it no
longer has the same address space that it had when the device was opened.”h]”hŒŽOn fork(2) or exec(2) the PASID is removed from the process as it no
longer has the same address space that it had when the device was opened.”…””}”(hjš  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K€hjQ  h²hubhï)”}”(hX:  On clone(2) the new task shares the same address space, so will be
able to use the PASID allocated to the process. The IA32_PASID is not
preemptively initialized as the PASID value might not be allocated yet or
the kernel does not know whether this thread is going to access the device
and the cleared IA32_PASID MSR reduces context switch overhead by xstate
init optimization. Since #GP faults have to be handled on any threads that
were created before the PASID was assigned to the mm of the process, newly
created threads might as well be treated in a consistent way.”h]”hX:  On clone(2) the new task shares the same address space, so will be
able to use the PASID allocated to the process. The IA32_PASID is not
preemptively initialized as the PASID value might not be allocated yet or
the kernel does not know whether this thread is going to access the device
and the cleared IA32_PASID MSR reduces context switch overhead by xstate
init optimization. Since #GP faults have to be handled on any threads that
were created before the PASID was assigned to the mm of the process, newly
created threads might as well be treated in a consistent way.”…””}”(hj¨  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KƒhjQ  h²hubhï)”}”(hŒˆDue to complexity of freeing the PASID and clearing all IA32_PASID MSRs in
all threads in unbind, free the PASID lazily only on mm exit.”h]”hŒˆDue to complexity of freeing the PASID and clearing all IA32_PASID MSRs in
all threads in unbind, free the PASID lazily only on mm exit.”…””}”(hj¶  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KŒhjQ  h²hubhï)”}”(hXP  If a process does a close(2) of the device file descriptor and munmap(2)
of the device MMIO portal, then the driver will unbind the device. The
PASID is still marked VALID in the PASID_MSR for any threads in the
process that accessed the device. But this is harmless as without the
MMIO portal they cannot submit new work to the device.”h]”hXP  If a process does a close(2) of the device file descriptor and munmap(2)
of the device MMIO portal, then the driver will unbind the device. The
PASID is still marked VALID in the PASID_MSR for any threads in the
process that accessed the device. But this is harmless as without the
MMIO portal they cannot submit new work to the device.”…””}”(hjÄ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhjQ  h²hubeh}”(h]”Œpasid-life-cycle-management”ah ]”h"]”Œpasid life cycle management”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KlubhÉ)”}”(hhh]”(hÎ)”}”(hŒRelationships”h]”hŒRelationships”…””}”(hjÝ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÚ  h²hh³hÇh´K–ubhŒblock_quote”“”)”}”(hX  * Each process has many threads, but only one PASID.
* Devices have a limited number (~10's to 1000's) of hardware workqueues.
  The device driver manages allocating hardware workqueues.
* A single mmap() maps a single hardware workqueue as a "portal" and
  each portal maps down to a single workqueue.
* For each device with which a process interacts, there must be
  one or more mmap()'d portals.
* Many threads within a process can share a single portal to access
  a single device.
* Multiple processes can separately mmap() the same portal, in
  which case they still share one device hardware workqueue.
* The single process-wide PASID is used by all threads to interact
  with all devices.  There is not, for instance, a PASID for each
  thread or each thread<->device pair.
”h]”jÈ  )”}”(hhh]”(jÍ  )”}”(hŒ2Each process has many threads, but only one PASID.”h]”hï)”}”(hjö  h]”hŒ2Each process has many threads, but only one PASID.”…””}”(hjø  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K˜hjô  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒDevices have a limited number (~10's to 1000's) of hardware workqueues.
The device driver manages allocating hardware workqueues.”h]”hï)”}”(hŒDevices have a limited number (~10's to 1000's) of hardware workqueues.
The device driver manages allocating hardware workqueues.”h]”hŒ…Devices have a limited number (~10â€™s to 1000â€™s) of hardware workqueues.
The device driver manages allocating hardware workqueues.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K™hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒoA single mmap() maps a single hardware workqueue as a "portal" and
each portal maps down to a single workqueue.”h]”hï)”}”(hŒoA single mmap() maps a single hardware workqueue as a "portal" and
each portal maps down to a single workqueue.”h]”hŒsA single mmap() maps a single hardware workqueue as a â€œportalâ€ and
each portal maps down to a single workqueue.”…””}”(hj'  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K›hj#  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒ[For each device with which a process interacts, there must be
one or more mmap()'d portals.”h]”hï)”}”(hŒ[For each device with which a process interacts, there must be
one or more mmap()'d portals.”h]”hŒ]For each device with which a process interacts, there must be
one or more mmap()â€™d portals.”…””}”(hj?  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khj;  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒRMany threads within a process can share a single portal to access
a single device.”h]”hï)”}”(hŒRMany threads within a process can share a single portal to access
a single device.”h]”hŒRMany threads within a process can share a single portal to access
a single device.”…””}”(hjW  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KŸhjS  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒwMultiple processes can separately mmap() the same portal, in
which case they still share one device hardware workqueue.”h]”hï)”}”(hŒwMultiple processes can separately mmap() the same portal, in
which case they still share one device hardware workqueue.”h]”hŒwMultiple processes can separately mmap() the same portal, in
which case they still share one device hardware workqueue.”…””}”(hjo  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¡hjk  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubjÍ  )”}”(hŒ¦The single process-wide PASID is used by all threads to interact
with all devices.  There is not, for instance, a PASID for each
thread or each thread<->device pair.
”h]”hï)”}”(hŒ¥The single process-wide PASID is used by all threads to interact
with all devices.  There is not, for instance, a PASID for each
thread or each thread<->device pair.”h]”hŒ¥The single process-wide PASID is used by all threads to interact
with all devices.  There is not, for instance, a PASID for each
thread or each thread<->device pair.”…””}”(hj‡  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K£hjƒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjñ  ubeh}”(h]”h ]”h"]”h$]”h&]”j  Œ*”uh1jÇ  h³hÇh´K˜hjí  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jë  h³hÇh´K˜hjÚ  h²hubeh}”(h]”Œrelationships”ah ]”h"]”Œrelationships”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K–ubhÉ)”}”(hhh]”(hÎ)”}”(hŒFAQ”h]”hŒFAQ”…””}”(hj³  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj°  h²hh³hÇh´K¨ubjÈ  )”}”(hhh]”jÍ  )”}”(hŒWhat is SVA/SVM?
”h]”hï)”}”(hŒWhat is SVA/SVM?”h]”hŒWhat is SVA/SVM?”…””}”(hjÈ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KªhjÄ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjÁ  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´Kªhj°  h²hubhï)”}”(hX5  Shared Virtual Addressing (SVA) permits I/O hardware and the processor to
work in the same address space, i.e., to share it. Some call it Shared
Virtual Memory (SVM), but Linux community wanted to avoid confusing it with
POSIX Shared Memory and Secure Virtual Machines which were terms already in
circulation.”h]”hX5  Shared Virtual Addressing (SVA) permits I/O hardware and the processor to
work in the same address space, i.e., to share it. Some call it Shared
Virtual Memory (SVM), but Linux community wanted to avoid confusing it with
POSIX Shared Memory and Secure Virtual Machines which were terms already in
circulation.”…””}”(hjâ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¬hj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒWhat is a PASID?
”h]”hï)”}”(hŒWhat is a PASID?”h]”hŒWhat is a PASID?”…””}”(hj÷  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K²hjó  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjð  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´K²hj°  h²hubhï)”}”(hŒâA Process Address Space ID (PASID) is a PCIe-defined Transaction Layer Packet
(TLP) prefix. A PASID is a 20-bit number allocated and managed by the OS.
PASID is included in all transactions between the platform and the device.”h]”hŒâA Process Address Space ID (PASID) is a PCIe-defined Transaction Layer Packet
(TLP) prefix. A PASID is a 20-bit number allocated and managed by the OS.
PASID is included in all transactions between the platform and the device.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K´hj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒ%How are shared workqueues different?
”h]”hï)”}”(hŒ$How are shared workqueues different?”h]”hŒ$How are shared workqueues different?”…””}”(hj&  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¸hj"  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hj  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´K¸hj°  h²hubhï)”}”(hX–  Traditionally, in order for userspace applications to interact with hardware,
there is a separate hardware instance required per process. For example,
consider doorbells as a mechanism of informing hardware about work to process.
Each doorbell is required to be spaced 4k (or page-size) apart for process
isolation. This requires hardware to provision that space and reserve it in
MMIO. This doesn't scale as the number of threads becomes quite large. The
hardware also manages the queue depth for Shared Work Queues (SWQ), and
consumers don't need to track queue depth. If there is no space to accept
a command, the device will return an error indicating retry.”h]”hXš  Traditionally, in order for userspace applications to interact with hardware,
there is a separate hardware instance required per process. For example,
consider doorbells as a mechanism of informing hardware about work to process.
Each doorbell is required to be spaced 4k (or page-size) apart for process
isolation. This requires hardware to provision that space and reserve it in
MMIO. This doesnâ€™t scale as the number of threads becomes quite large. The
hardware also manages the queue depth for Shared Work Queues (SWQ), and
consumers donâ€™t need to track queue depth. If there is no space to accept
a command, the device will return an error indicating retry.”…””}”(hj@  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kºhj°  h²hubhï)”}”(hX  A user should check Deferrable Memory Write (DMWr) capability on the device
and only submits ENQCMD when the device supports it. In the new DMWr PCIe
terminology, devices need to support DMWr completer capability. In addition,
it requires all switch ports to support DMWr routing and must be enabled by
the PCIe subsystem, much like how PCIe atomic operations are managed for
instance.”h]”hX  A user should check Deferrable Memory Write (DMWr) capability on the device
and only submits ENQCMD when the device supports it. In the new DMWr PCIe
terminology, devices need to support DMWr completer capability. In addition,
it requires all switch ports to support DMWr routing and must be enabled by
the PCIe subsystem, much like how PCIe atomic operations are managed for
instance.”…””}”(hjN  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÄhj°  h²hubhï)”}”(hX  SWQ allows hardware to provision just a single address in the device. When
used with ENQCMD to submit work, the device can distinguish the process
submitting the work since it will include the PASID assigned to that
process. This helps the device scale to a large number of processes.”h]”hX  SWQ allows hardware to provision just a single address in the device. When
used with ENQCMD to submit work, the device can distinguish the process
submitting the work since it will include the PASID assigned to that
process. This helps the device scale to a large number of processes.”…””}”(hj\  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KËhj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒ0Is this the same as a user space device driver?
”h]”hï)”}”(hŒ/Is this the same as a user space device driver?”h]”hŒ/Is this the same as a user space device driver?”…””}”(hjq  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÐhjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjj  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´KÐhj°  h²hubhï)”}”(hŒûCommunicating with the device via the shared workqueue is much simpler
than a full blown user space driver. The kernel driver does all the
initialization of the hardware. User space only needs to worry about
submitting work and processing completions.”h]”hŒûCommunicating with the device via the shared workqueue is much simpler
than a full blown user space driver. The kernel driver does all the
initialization of the hardware. User space only needs to worry about
submitting work and processing completions.”…””}”(hj‹  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÒhj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒIs this the same as SR-IOV?
”h]”hï)”}”(hŒIs this the same as SR-IOV?”h]”hŒIs this the same as SR-IOV?”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K×hjœ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hj™  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´K×hj°  h²hubhï)”}”(hXh  Single Root I/O Virtualization (SR-IOV) focuses on providing independent
hardware interfaces for virtualizing hardware. Hence, it's required to be
an almost fully functional interface to software supporting the traditional
BARs, space for interrupts via MSI-X, its own register layout.
Virtual Functions (VFs) are assisted by the Physical Function (PF)
driver.”h]”hXj  Single Root I/O Virtualization (SR-IOV) focuses on providing independent
hardware interfaces for virtualizing hardware. Hence, itâ€™s required to be
an almost fully functional interface to software supporting the traditional
BARs, space for interrupts via MSI-X, its own register layout.
Virtual Functions (VFs) are assisted by the Physical Function (PF)
driver.”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÙhj°  h²hubhï)”}”(hXÓ  Scalable I/O Virtualization builds on the PASID concept to create device
instances for virtualization. SIOV requires host software to assist in
creating virtual devices; each virtual device is represented by a PASID
along with the bus/device/function of the device.  This allows device
hardware to optimize device resource creation and can grow dynamically on
demand. SR-IOV creation and management is very static in nature. Consult
references below for more details.”h]”hXÓ  Scalable I/O Virtualization builds on the PASID concept to create device
instances for virtualization. SIOV requires host software to assist in
creating virtual devices; each virtual device is represented by a PASID
along with the bus/device/function of the device.  This allows device
hardware to optimize device resource creation and can grow dynamically on
demand. SR-IOV creation and management is very static in nature. Consult
references below for more details.”…””}”(hjÈ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kàhj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒ5Why not just create a virtual function for each app?
”h]”hï)”}”(hŒ4Why not just create a virtual function for each app?”h]”hŒ4Why not just create a virtual function for each app?”…””}”(hjÝ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KèhjÙ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hjÖ  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´Kèhj°  h²hubhï)”}”(hXe  Creating PCIe SR-IOV type Virtual Functions (VF) is expensive. VFs require
duplicated hardware for PCI config space and interrupts such as MSI-X.
Resources such as interrupts have to be hard partitioned between VFs at
creation time, and cannot scale dynamically on demand. The VFs are not
completely independent from the Physical Function (PF). Most VFs require
some communication and assistance from the PF driver. SIOV, in contrast,
creates a software-defined device where all the configuration and control
aspects are mediated via the slow path. The work submission and completion
happen without any mediation.”h]”hXe  Creating PCIe SR-IOV type Virtual Functions (VF) is expensive. VFs require
duplicated hardware for PCI config space and interrupts such as MSI-X.
Resources such as interrupts have to be hard partitioned between VFs at
creation time, and cannot scale dynamically on demand. The VFs are not
completely independent from the Physical Function (PF). Most VFs require
some communication and assistance from the PF driver. SIOV, in contrast,
creates a software-defined device where all the configuration and control
aspects are mediated via the slow path. The work submission and completion
happen without any mediation.”…””}”(hj÷  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kêhj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒ"Does this support virtualization?
”h]”hï)”}”(hŒ!Does this support virtualization?”h]”hŒ!Does this support virtualization?”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kôhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hj  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´Kôhj°  h²hubhï)”}”(hŒßENQCMD can be used from within a guest VM. In these cases, the VMM helps
with setting up a translation table to translate from Guest PASID to Host
PASID. Please consult the ENQCMD instruction set reference for more
details.”h]”hŒßENQCMD can be used from within a guest VM. In these cases, the VMM helps
with setting up a translation table to translate from Guest PASID to Host
PASID. Please consult the ENQCMD instruction set reference for more
details.”…””}”(hj&  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Köhj°  h²hubjÈ  )”}”(hhh]”jÍ  )”}”(hŒDoes memory need to be pinned?
”h]”hï)”}”(hŒDoes memory need to be pinned?”h]”hŒDoes memory need to be pinned?”…””}”(hj;  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kûhj7  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jÌ  hj4  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j¡  uh1jÇ  h³hÇh´Kûhj°  h²hubhï)”}”(hŒ÷When devices support SVA along with platform hardware such as IOMMU
supporting such devices, there is no need to pin memory for DMA purposes.
Devices that support SVA also support other PCIe features that remove the
pinning requirement for memory.”h]”hŒ÷When devices support SVA along with platform hardware such as IOMMU
supporting such devices, there is no need to pin memory for DMA purposes.
Devices that support SVA also support other PCIe features that remove the
pinning requirement for memory.”…””}”(hjU  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kýhj°  h²hubhï)”}”(hŒîDevice TLB support - Device requests the IOMMU to lookup an address before
use via Address Translation Service (ATS) requests.  If the mapping exists
but there is no page allocated by the OS, IOMMU hardware returns that no
mapping exists.”h]”hŒîDevice TLB support - Device requests the IOMMU to lookup an address before
use via Address Translation Service (ATS) requests.  If the mapping exists
but there is no page allocated by the OS, IOMMU hardware returns that no
mapping exists.”…””}”(hjc  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj°  h²hubhï)”}”(hŒíDevice requests the virtual address to be mapped via Page Request
Interface (PRI). Once the OS has successfully completed the mapping, it
returns the response back to the device. The device requests again for
a translation and continues.”h]”hŒíDevice requests the virtual address to be mapped via Page Request
Interface (PRI). Once the OS has successfully completed the mapping, it
returns the response back to the device. The device requests again for
a translation and continues.”…””}”(hjq  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj°  h²hubhï)”}”(hŒæIOMMU works with the OS in managing consistency of page-tables with the
device. When removing pages, it interacts with the device to remove any
device TLB entry that might have been cached before removing the mappings from
the OS.”h]”hŒæIOMMU works with the OS in managing consistency of page-tables with the
device. When removing pages, it interacts with the device to remove any
device TLB entry that might have been cached before removing the mappings from
the OS.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj°  h²hubeh}”(h]”Œfaq”ah ]”h"]”Œfaq”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K¨ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ
References”h]”hŒ
References”…””}”(hj˜  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj•  h²hh³hÇh´Mubhï)”}”(hŒtVT-D:
https://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o-intel-vt-d”h]”(hŒVT-D:
”…””}”(hj¦  h²hh³Nh´NubhŒ	reference”“”)”}”(hŒnhttps://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o-intel-vt-d”h]”hŒnhttps://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o-intel-vt-d”…””}”(hj°  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j²  uh1j®  hj¦  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj•  h²hubhï)”}”(hŒ]SIOV:
https://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux”h]”(hŒSIOV:
”…””}”(hjÅ  h²hh³Nh´Nubj¯  )”}”(hŒWhttps://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux”h]”hŒWhttps://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux”…””}”(hjÍ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jÏ  uh1j®  hjÅ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj•  h²hubhï)”}”(hŒENQCMD in ISE:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf”h]”(hŒENQCMD in ISE:
”…””}”(hjâ  h²hh³Nh´Nubj¯  )”}”(hŒ~https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf”h]”hŒ~https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf”…””}”(hjê  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jì  uh1j®  hjâ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Mhj•  h²hubhï)”}”(hŒiDSA spec:
https://software.intel.com/sites/default/files/341204-intel-data-streaming-accelerator-spec.pdf”h]”(hŒ
DSA spec:
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