€•Äž      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ /translations/zh_CN/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/zh_TW/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/it_IT/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/ja_JP/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/ko_KR/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/pt_BR/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ /translations/sp_SP/arch/x86/pti”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³Œ:/var/lib/git/docbuild/linux/Documentation/arch/x86/pti.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒPage Table Isolation (PTI)”h]”hŒPage Table Isolation (PTI)”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒOverview”h]”hŒOverview”…””}”(hhàh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÝh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒ­Page Table Isolation (pti, previously known as KAISER [1]_) is a
countermeasure against attacks on the shared user/kernel address
space such as the "Meltdown" approach [2]_.”h]”(hŒ6Page Table Isolation (pti, previously known as KAISER ”…””}”(hhðh²hh³Nh´NubhŒfootnote_reference”“”)”}”(hŒ[1]_”h]”hŒ1”…””}”(hhúh²hh³Nh´Nubah}”(h]”Œid1”ah ]”h"]”h$]”h&]”Œrefid”Œid3”Œdocname”Œarch/x86/pti”uh1høhhðŒresolved”KubhŒr) is a
countermeasure against attacks on the shared user/kernel address
space such as the â€œMeltdownâ€ approach ”…””}”(hhðh²hh³Nh´Nubhù)”}”(hŒ[2]_”h]”hŒ2”…””}”(hj  h²hh³Nh´Nubah}”(h]”Œid2”ah ]”h"]”h$]”h&]”j	  Œid4”j  j  uh1høhhðj  KubhŒ.”…””}”(hhðh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K
hhÝh²hubhï)”}”(hXF  To mitigate this class of attacks, we create an independent set of
page tables for use only when running userspace applications.  When
the kernel is entered via syscalls, interrupts or exceptions, the
page tables are switched to the full "kernel" copy.  When the system
switches back to user mode, the user copy is used again.”h]”hXJ  To mitigate this class of attacks, we create an independent set of
page tables for use only when running userspace applications.  When
the kernel is entered via syscalls, interrupts or exceptions, the
page tables are switched to the full â€œkernelâ€ copy.  When the system
switches back to user mode, the user copy is used again.”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhhÝh²hubhï)”}”(hXX  The userspace page tables contain only a minimal amount of kernel
data: only what is needed to enter/exit the kernel such as the
entry/exit functions themselves and the interrupt descriptor table
(IDT).  There are a few strictly unnecessary things that get mapped
such as the first C function when entering an interrupt (see
comments in pti.c).”h]”hXX  The userspace page tables contain only a minimal amount of kernel
data: only what is needed to enter/exit the kernel such as the
entry/exit functions themselves and the interrupt descriptor table
(IDT).  There are a few strictly unnecessary things that get mapped
such as the first C function when entering an interrupt (see
comments in pti.c).”…””}”(hj:  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhhÝh²hubhï)”}”(hXY  This approach helps to ensure that side-channel attacks leveraging
the paging structures do not function when PTI is enabled.  It can be
enabled by setting CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y at compile
time.  Once enabled at compile-time, it can be disabled at boot with
the 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).”h]”hXa  This approach helps to ensure that side-channel attacks leveraging
the paging structures do not function when PTI is enabled.  It can be
enabled by setting CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y at compile
time.  Once enabled at compile-time, it can be disabled at boot with
the â€˜noptiâ€™ or â€˜pti=â€™ kernel parameters (see kernel-parameters.txt).”…””}”(hjH  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KhhÝh²hubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒPage Table Management”h]”hŒPage Table Management”…””}”(hja  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj^  h²hh³hÇh´K"ubhï)”}”(hX   When PTI is enabled, the kernel manages two sets of page tables.
The first set is very similar to the single set which is present in
kernels without PTI.  This includes a complete mapping of userspace
that the kernel can use for things like copy_to_user().”h]”hX   When PTI is enabled, the kernel manages two sets of page tables.
The first set is very similar to the single set which is present in
kernels without PTI.  This includes a complete mapping of userspace
that the kernel can use for things like copy_to_user().”…””}”(hjo  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K$hj^  h²hubhï)”}”(hŒðAlthough _complete_, the user portion of the kernel page tables is
crippled by setting the NX bit in the top level.  This ensures
that any missed kernel->user CR3 switch will immediately crash
userspace upon executing its first instruction.”h]”hŒðAlthough _complete_, the user portion of the kernel page tables is
crippled by setting the NX bit in the top level.  This ensures
that any missed kernel->user CR3 switch will immediately crash
userspace upon executing its first instruction.”…””}”(hj}  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K)hj^  h²hubhï)”}”(hX  The userspace page tables map only the kernel data needed to enter
and exit the kernel.  This data is entirely contained in the 'struct
cpu_entry_area' structure which is placed in the fixmap which gives
each CPU's copy of the area a compile-time-fixed virtual address.”h]”hX  The userspace page tables map only the kernel data needed to enter
and exit the kernel.  This data is entirely contained in the â€˜struct
cpu_entry_areaâ€™ structure which is placed in the fixmap which gives
each CPUâ€™s copy of the area a compile-time-fixed virtual address.”…””}”(hj‹  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K.hj^  h²hubhï)”}”(hX  For new userspace mappings, the kernel makes the entries in its
page tables like normal.  The only difference is when the kernel
makes entries in the top (PGD) level.  In addition to setting the
entry in the main kernel PGD, a copy of the entry is made in the
userspace page tables' PGD.”h]”hX!  For new userspace mappings, the kernel makes the entries in its
page tables like normal.  The only difference is when the kernel
makes entries in the top (PGD) level.  In addition to setting the
entry in the main kernel PGD, a copy of the entry is made in the
userspace page tablesâ€™ PGD.”…””}”(hj™  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K3hj^  h²hubhï)”}”(hŒâThis sharing at the PGD level also inherently shares all the lower
layers of the page tables.  This leaves a single, shared set of
userspace page tables to manage.  One PTE to lock, one set of
accessed bits, dirty bits, etc...”h]”hŒâThis sharing at the PGD level also inherently shares all the lower
layers of the page tables.  This leaves a single, shared set of
userspace page tables to manage.  One PTE to lock, one set of
accessed bits, dirty bits, etc...”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K9hj^  h²hubeh}”(h]”Œpage-table-management”ah ]”h"]”Œpage table management”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K"ubhÉ)”}”(hhh]”(hÎ)”}”(hŒOverhead”h]”hŒOverhead”…””}”(hjÀ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj½  h²hh³hÇh´K?ubhï)”}”(hŒ\Protection against side-channel attacks is important.  But,
this protection comes at a cost:”h]”hŒ\Protection against side-channel attacks is important.  But,
this protection comes at a cost:”…””}”(hjÎ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KAhj½  h²hubhŒenumerated_list”“”)”}”(hhh]”hŒ	list_item”“”)”}”(hŒIncreased Memory Use
”h]”hï)”}”(hŒIncreased Memory Use”h]”hŒIncreased Memory Use”…””}”(hjç  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KDhjã  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÞ  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œenumtype”Œarabic”Œprefix”hŒsuffix”Œ.”uh1jÜ  hj½  h²hh³hÇh´KDubhŒblock_quote”“”)”}”(hX[  a. Each process now needs an order-1 PGD instead of order-0.
   (Consumes an additional 4k per process).
b. The 'cpu_entry_area' structure must be 2MB in size and 2MB
   aligned so that it can be mapped by setting a single PMD
   entry.  This consumes nearly 2MB of RAM once the kernel
   is decompressed, but no space in the kernel image itself.
”h]”jÝ  )”}”(hhh]”(jâ  )”}”(hŒbEach process now needs an order-1 PGD instead of order-0.
(Consumes an additional 4k per process).”h]”hï)”}”(hŒbEach process now needs an order-1 PGD instead of order-0.
(Consumes an additional 4k per process).”h]”hŒbEach process now needs an order-1 PGD instead of order-0.
(Consumes an additional 4k per process).”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KFhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hj  ubjâ  )”}”(hŒæThe 'cpu_entry_area' structure must be 2MB in size and 2MB
aligned so that it can be mapped by setting a single PMD
entry.  This consumes nearly 2MB of RAM once the kernel
is decompressed, but no space in the kernel image itself.
”h]”hï)”}”(hŒåThe 'cpu_entry_area' structure must be 2MB in size and 2MB
aligned so that it can be mapped by setting a single PMD
entry.  This consumes nearly 2MB of RAM once the kernel
is decompressed, but no space in the kernel image itself.”h]”hŒéThe â€˜cpu_entry_areaâ€™ structure must be 2MB in size and 2MB
aligned so that it can be mapped by setting a single PMD
entry.  This consumes nearly 2MB of RAM once the kernel
is decompressed, but no space in the kernel image itself.”…””}”(hj+  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KHhj'  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”j  Œ
loweralpha”j  hj  j  uh1jÜ  hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´KFhj½  h²hubjÝ  )”}”(hhh]”jâ  )”}”(hŒRuntime Cost
”h]”hï)”}”(hŒRuntime Cost”h]”hŒRuntime Cost”…””}”(hjS  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KMhjO  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjL  h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  Œstart”Kuh1jÜ  hj½  h²hh³hÇh´KMubj  )”}”(hXI
  a. CR3 manipulation to switch between the page table copies
   must be done at interrupt, syscall, and exception entry
   and exit (it can be skipped when the kernel is interrupted,
   though.)  Moves to CR3 are on the order of a hundred
   cycles, and are required at every entry and exit.
b. Percpu TSS is mapped into the user page tables to allow SYSCALL64 path
   to work under PTI. This doesn't have a direct runtime cost but it can
   be argued it opens certain timing attack scenarios.
c. Global pages are disabled for all kernel structures not
   mapped into both kernel and userspace page tables.  This
   feature of the MMU allows different processes to share TLB
   entries mapping the kernel.  Losing the feature means more
   TLB misses after a context switch.  The actual loss of
   performance is very small, however, never exceeding 1%.
d. Process Context IDentifiers (PCID) is a CPU feature that
   allows us to skip flushing the entire TLB when switching page
   tables by setting a special bit in CR3 when the page tables
   are changed.  This makes switching the page tables (at context
   switch, or kernel entry/exit) cheaper.  But, on systems with
   PCID support, the context switch code must flush both the user
   and kernel entries out of the TLB.  The user PCID TLB flush is
   deferred until the exit to userspace, minimizing the cost.
   See intel.com/sdm for the gory PCID/INVPCID details.
e. The userspace page tables must be populated for each new
   process.  Even without PTI, the shared kernel mappings
   are created by copying top-level (PGD) entries into each
   new process.  But, with PTI, there are now *two* kernel
   mappings: one in the kernel page tables that maps everything
   and one for the entry/exit structures.  At fork(), we need to
   copy both.
f. In addition to the fork()-time copying, there must also
   be an update to the userspace PGD any time a set_pgd() is done
   on a PGD used to map userspace.  This ensures that the kernel
   and userspace copies always map the same userspace
   memory.
g. On systems without PCID support, each CR3 write flushes
   the entire TLB.  That means that each syscall, interrupt
   or exception flushes the TLB.
h. INVPCID is a TLB-flushing instruction which allows flushing
   of TLB entries for non-current PCIDs.  Some systems support
   PCIDs, but do not support INVPCID.  On these systems, addresses
   can only be flushed from the TLB for the current PCID.  When
   flushing a kernel address, we need to flush all PCIDs, so a
   single kernel address flush will require a TLB-flushing CR3
   write upon the next use of every PCID.
”h]”jÝ  )”}”(hhh]”(jâ  )”}”(hX  CR3 manipulation to switch between the page table copies
must be done at interrupt, syscall, and exception entry
and exit (it can be skipped when the kernel is interrupted,
though.)  Moves to CR3 are on the order of a hundred
cycles, and are required at every entry and exit.”h]”hï)”}”(hX  CR3 manipulation to switch between the page table copies
must be done at interrupt, syscall, and exception entry
and exit (it can be skipped when the kernel is interrupted,
though.)  Moves to CR3 are on the order of a hundred
cycles, and are required at every entry and exit.”h]”hX  CR3 manipulation to switch between the page table copies
must be done at interrupt, syscall, and exception entry
and exit (it can be skipped when the kernel is interrupted,
though.)  Moves to CR3 are on the order of a hundred
cycles, and are required at every entry and exit.”…””}”(hjy  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KOhju  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hŒÀPercpu TSS is mapped into the user page tables to allow SYSCALL64 path
to work under PTI. This doesn't have a direct runtime cost but it can
be argued it opens certain timing attack scenarios.”h]”hï)”}”(hŒÀPercpu TSS is mapped into the user page tables to allow SYSCALL64 path
to work under PTI. This doesn't have a direct runtime cost but it can
be argued it opens certain timing attack scenarios.”h]”hŒÂPercpu TSS is mapped into the user page tables to allow SYSCALL64 path
to work under PTI. This doesnâ€™t have a direct runtime cost but it can
be argued it opens certain timing attack scenarios.”…””}”(hj‘  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KThj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hXU  Global pages are disabled for all kernel structures not
mapped into both kernel and userspace page tables.  This
feature of the MMU allows different processes to share TLB
entries mapping the kernel.  Losing the feature means more
TLB misses after a context switch.  The actual loss of
performance is very small, however, never exceeding 1%.”h]”hï)”}”(hXU  Global pages are disabled for all kernel structures not
mapped into both kernel and userspace page tables.  This
feature of the MMU allows different processes to share TLB
entries mapping the kernel.  Losing the feature means more
TLB misses after a context switch.  The actual loss of
performance is very small, however, never exceeding 1%.”h]”hXU  Global pages are disabled for all kernel structures not
mapped into both kernel and userspace page tables.  This
feature of the MMU allows different processes to share TLB
entries mapping the kernel.  Losing the feature means more
TLB misses after a context switch.  The actual loss of
performance is very small, however, never exceeding 1%.”…””}”(hj©  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KWhj¥  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hX  Process Context IDentifiers (PCID) is a CPU feature that
allows us to skip flushing the entire TLB when switching page
tables by setting a special bit in CR3 when the page tables
are changed.  This makes switching the page tables (at context
switch, or kernel entry/exit) cheaper.  But, on systems with
PCID support, the context switch code must flush both the user
and kernel entries out of the TLB.  The user PCID TLB flush is
deferred until the exit to userspace, minimizing the cost.
See intel.com/sdm for the gory PCID/INVPCID details.”h]”hï)”}”(hX  Process Context IDentifiers (PCID) is a CPU feature that
allows us to skip flushing the entire TLB when switching page
tables by setting a special bit in CR3 when the page tables
are changed.  This makes switching the page tables (at context
switch, or kernel entry/exit) cheaper.  But, on systems with
PCID support, the context switch code must flush both the user
and kernel entries out of the TLB.  The user PCID TLB flush is
deferred until the exit to userspace, minimizing the cost.
See intel.com/sdm for the gory PCID/INVPCID details.”h]”hX  Process Context IDentifiers (PCID) is a CPU feature that
allows us to skip flushing the entire TLB when switching page
tables by setting a special bit in CR3 when the page tables
are changed.  This makes switching the page tables (at context
switch, or kernel entry/exit) cheaper.  But, on systems with
PCID support, the context switch code must flush both the user
and kernel entries out of the TLB.  The user PCID TLB flush is
deferred until the exit to userspace, minimizing the cost.
See intel.com/sdm for the gory PCID/INVPCID details.”…””}”(hjÁ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K]hj½  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hXf  The userspace page tables must be populated for each new
process.  Even without PTI, the shared kernel mappings
are created by copying top-level (PGD) entries into each
new process.  But, with PTI, there are now *two* kernel
mappings: one in the kernel page tables that maps everything
and one for the entry/exit structures.  At fork(), we need to
copy both.”h]”hï)”}”(hXf  The userspace page tables must be populated for each new
process.  Even without PTI, the shared kernel mappings
are created by copying top-level (PGD) entries into each
new process.  But, with PTI, there are now *two* kernel
mappings: one in the kernel page tables that maps everything
and one for the entry/exit structures.  At fork(), we need to
copy both.”h]”(hŒÔThe userspace page tables must be populated for each new
process.  Even without PTI, the shared kernel mappings
are created by copying top-level (PGD) entries into each
new process.  But, with PTI, there are now ”…””}”(hjÙ  h²hh³Nh´NubhŒemphasis”“”)”}”(hŒ*two*”h]”hŒtwo”…””}”(hjã  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÙ  ubhŒ kernel
mappings: one in the kernel page tables that maps everything
and one for the entry/exit structures.  At fork(), we need to
copy both.”…””}”(hjÙ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KfhjÕ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hŒïIn addition to the fork()-time copying, there must also
be an update to the userspace PGD any time a set_pgd() is done
on a PGD used to map userspace.  This ensures that the kernel
and userspace copies always map the same userspace
memory.”h]”hï)”}”(hŒïIn addition to the fork()-time copying, there must also
be an update to the userspace PGD any time a set_pgd() is done
on a PGD used to map userspace.  This ensures that the kernel
and userspace copies always map the same userspace
memory.”h]”hŒïIn addition to the fork()-time copying, there must also
be an update to the userspace PGD any time a set_pgd() is done
on a PGD used to map userspace.  This ensures that the kernel
and userspace copies always map the same userspace
memory.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kmhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hŒŽOn systems without PCID support, each CR3 write flushes
the entire TLB.  That means that each syscall, interrupt
or exception flushes the TLB.”h]”hï)”}”(hŒŽOn systems without PCID support, each CR3 write flushes
the entire TLB.  That means that each syscall, interrupt
or exception flushes the TLB.”h]”hŒŽOn systems without PCID support, each CR3 write flushes
the entire TLB.  That means that each syscall, interrupt
or exception flushes the TLB.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Krhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubjâ  )”}”(hX”  INVPCID is a TLB-flushing instruction which allows flushing
of TLB entries for non-current PCIDs.  Some systems support
PCIDs, but do not support INVPCID.  On these systems, addresses
can only be flushed from the TLB for the current PCID.  When
flushing a kernel address, we need to flush all PCIDs, so a
single kernel address flush will require a TLB-flushing CR3
write upon the next use of every PCID.
”h]”hï)”}”(hX“  INVPCID is a TLB-flushing instruction which allows flushing
of TLB entries for non-current PCIDs.  Some systems support
PCIDs, but do not support INVPCID.  On these systems, addresses
can only be flushed from the TLB for the current PCID.  When
flushing a kernel address, we need to flush all PCIDs, so a
single kernel address flush will require a TLB-flushing CR3
write upon the next use of every PCID.”h]”hX“  INVPCID is a TLB-flushing instruction which allows flushing
of TLB entries for non-current PCIDs.  Some systems support
PCIDs, but do not support INVPCID.  On these systems, addresses
can only be flushed from the TLB for the current PCID.  When
flushing a kernel address, we need to flush all PCIDs, so a
single kernel address flush will require a TLB-flushing CR3
write upon the next use of every PCID.”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kuhj1  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjr  ubeh}”(h]”h ]”h"]”h$]”h&]”j  jE  j  hj  j  uh1jÜ  hjn  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´KOhj½  h²hubeh}”(h]”Œoverhead”ah ]”h"]”Œoverhead”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K?ubhÉ)”}”(hhh]”(hÎ)”}”(hŒPossible Future Work”h]”hŒPossible Future Work”…””}”(hj`  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj]  h²hh³hÇh´K~ubjÝ  )”}”(hhh]”(jâ  )”}”(hŒ^We can be more careful about not actually writing to CR3
unless its value is actually changed.”h]”hï)”}”(hŒ^We can be more careful about not actually writing to CR3
unless its value is actually changed.”h]”hŒ^We can be more careful about not actually writing to CR3
unless its value is actually changed.”…””}”(hju  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khjq  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjn  h²hh³hÇh´Nubjâ  )”}”(hŒTAllow PTI to be enabled/disabled at runtime in addition to the
boot-time switching.
”h]”hï)”}”(hŒSAllow PTI to be enabled/disabled at runtime in addition to the
boot-time switching.”h]”hŒSAllow PTI to be enabled/disabled at runtime in addition to the
boot-time switching.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khj‰  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjn  h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jÜ  hj]  h²hh³hÇh´Kubeh}”(h]”Œpossible-future-work”ah ]”h"]”Œpossible future work”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K~ubhÉ)”}”(hhh]”(hÎ)”}”(hŒTesting”h]”hŒTesting”…””}”(hj²  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¯  h²hh³hÇh´K…ubhï)”}”(hŒnTo test stability of PTI, the following test procedure is recommended,
ideally doing all of these in parallel:”h]”hŒnTo test stability of PTI, the following test procedure is recommended,
ideally doing all of these in parallel:”…””}”(hjÀ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K‡hj¯  h²hubjÝ  )”}”(hhh]”(jâ  )”}”(hŒSet CONFIG_DEBUG_ENTRY=y”h]”hï)”}”(hjÓ  h]”hŒSet CONFIG_DEBUG_ENTRY=y”…””}”(hjÕ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KŠhjÑ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÎ  h²hh³hÇh´Nubjâ  )”}”(hXL  Run several copies of all of the tools/testing/selftests/x86/ tests
(excluding MPX and protection_keys) in a loop on multiple CPUs for
several minutes.  These tests frequently uncover corner cases in the
kernel entry code.  In general, old kernels might cause these tests
themselves to crash, but they should never crash the kernel.”h]”hï)”}”(hXL  Run several copies of all of the tools/testing/selftests/x86/ tests
(excluding MPX and protection_keys) in a loop on multiple CPUs for
several minutes.  These tests frequently uncover corner cases in the
kernel entry code.  In general, old kernels might cause these tests
themselves to crash, but they should never crash the kernel.”h]”hXL  Run several copies of all of the tools/testing/selftests/x86/ tests
(excluding MPX and protection_keys) in a loop on multiple CPUs for
several minutes.  These tests frequently uncover corner cases in the
kernel entry code.  In general, old kernels might cause these tests
themselves to crash, but they should never crash the kernel.”…””}”(hjì  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K‹hjè  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÎ  h²hh³hÇh´Nubjâ  )”}”(hX	  Run the 'perf' tool in a mode (top or record) that generates many
frequent performance monitoring non-maskable interrupts (see "NMI"
in /proc/interrupts).  This exercises the NMI entry/exit code which
is known to trigger bugs in code paths that did not expect to be
interrupted, including nested NMIs.  Using "-c" boosts the rate of
NMIs, and using two -c with separate counters encourages nested NMIs
and less deterministic behavior.
::

     while true; do perf record -c 10000 -e instructions,cycles -a sleep 10; done
”h]”(hï)”}”(hXµ  Run the 'perf' tool in a mode (top or record) that generates many
frequent performance monitoring non-maskable interrupts (see "NMI"
in /proc/interrupts).  This exercises the NMI entry/exit code which
is known to trigger bugs in code paths that did not expect to be
interrupted, including nested NMIs.  Using "-c" boosts the rate of
NMIs, and using two -c with separate counters encourages nested NMIs
and less deterministic behavior.
::”h]”hX¾  Run the â€˜perfâ€™ tool in a mode (top or record) that generates many
frequent performance monitoring non-maskable interrupts (see â€œNMIâ€
in /proc/interrupts).  This exercises the NMI entry/exit code which
is known to trigger bugs in code paths that did not expect to be
interrupted, including nested NMIs.  Using â€œ-câ€ boosts the rate of
NMIs, and using two -c with separate counters encourages nested NMIs
and less deterministic behavior.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Khj   ubhŒliteral_block”“”)”}”(hŒLwhile true; do perf record -c 10000 -e instructions,cycles -a sleep 10; done”h]”hŒLwhile true; do perf record -c 10000 -e instructions,cycles -a sleep 10; done”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j  h³hÇh´K™hj   ubeh}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÎ  h²hh³hÇh´Nubjâ  )”}”(hŒLaunch a KVM virtual machine.”h]”hï)”}”(hj*  h]”hŒLaunch a KVM virtual machine.”…””}”(hj,  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K›hj(  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÎ  h²hh³hÇh´Nubjâ  )”}”(hŒ†Run 32-bit binaries on systems supporting the SYSCALL instruction.
This has been a lightly-tested code path and needs extra scrutiny.
”h]”hï)”}”(hŒ…Run 32-bit binaries on systems supporting the SYSCALL instruction.
This has been a lightly-tested code path and needs extra scrutiny.”h]”hŒ…Run 32-bit binaries on systems supporting the SYSCALL instruction.
This has been a lightly-tested code path and needs extra scrutiny.”…””}”(hjC  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´Kœhj?  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjÎ  h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  j  hj  j  uh1jÜ  hj¯  h²hh³hÇh´KŠubeh}”(h]”Œtesting”ah ]”h"]”Œtesting”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K…ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ	Debugging”h]”hŒ	Debugging”…””}”(hjh  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhje  h²hh³hÇh´K ubhï)”}”(hŒSBugs in PTI cause a few different signatures of crashes
that are worth noting here.”h]”hŒSBugs in PTI cause a few different signatures of crashes
that are worth noting here.”…””}”(hjv  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¢hje  h²hubj  )”}”(hX§  * Failures of the selftests/x86 code.  Usually a bug in one of the
  more obscure corners of entry_64.S
* Crashes in early boot, especially around CPU bringup.  Bugs
  in the mappings cause these.
* Crashes at the first interrupt.  Caused by bugs in entry_64.S,
  like screwing up a page table switch.  Also caused by
  incorrectly mapping the IRQ handler entry code.
* Crashes at the first NMI.  The NMI code is separate from main
  interrupt handlers and can have bugs that do not affect
  normal interrupts.  Also caused by incorrectly mapping NMI
  code.  NMIs that interrupt the entry code must be very
  careful and can be the cause of crashes that show up when
  running perf.
* Kernel crashes at the first exit to userspace.  entry_64.S
  bugs, or failing to map some of the exit code.
* Crashes at first interrupt that interrupts userspace. The paths
  in entry_64.S that return to userspace are sometimes separate
  from the ones that return to the kernel.
* Double faults: overflowing the kernel stack because of page
  faults upon page faults.  Caused by touching non-pti-mapped
  data in the entry code, or forgetting to switch to kernel
  CR3 before calling into C functions which are not pti-mapped.
* Userspace segfaults early in boot, sometimes manifesting
  as mount(8) failing to mount the rootfs.  These have
  tended to be TLB invalidation issues.  Usually invalidating
  the wrong PCID, or otherwise missing an invalidation.
”h]”hŒbullet_list”“”)”}”(hhh]”(jâ  )”}”(hŒcFailures of the selftests/x86 code.  Usually a bug in one of the
more obscure corners of entry_64.S”h]”hï)”}”(hŒcFailures of the selftests/x86 code.  Usually a bug in one of the
more obscure corners of entry_64.S”h]”hŒcFailures of the selftests/x86 code.  Usually a bug in one of the
more obscure corners of entry_64.S”…””}”(hj‘  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¥hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒXCrashes in early boot, especially around CPU bringup.  Bugs
in the mappings cause these.”h]”hï)”}”(hŒXCrashes in early boot, especially around CPU bringup.  Bugs
in the mappings cause these.”h]”hŒXCrashes in early boot, especially around CPU bringup.  Bugs
in the mappings cause these.”…””}”(hj©  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K§hj¥  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒ¤Crashes at the first interrupt.  Caused by bugs in entry_64.S,
like screwing up a page table switch.  Also caused by
incorrectly mapping the IRQ handler entry code.”h]”hï)”}”(hŒ¤Crashes at the first interrupt.  Caused by bugs in entry_64.S,
like screwing up a page table switch.  Also caused by
incorrectly mapping the IRQ handler entry code.”h]”hŒ¤Crashes at the first interrupt.  Caused by bugs in entry_64.S,
like screwing up a page table switch.  Also caused by
incorrectly mapping the IRQ handler entry code.”…””}”(hjÁ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K©hj½  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hX/  Crashes at the first NMI.  The NMI code is separate from main
interrupt handlers and can have bugs that do not affect
normal interrupts.  Also caused by incorrectly mapping NMI
code.  NMIs that interrupt the entry code must be very
careful and can be the cause of crashes that show up when
running perf.”h]”hï)”}”(hX/  Crashes at the first NMI.  The NMI code is separate from main
interrupt handlers and can have bugs that do not affect
normal interrupts.  Also caused by incorrectly mapping NMI
code.  NMIs that interrupt the entry code must be very
careful and can be the cause of crashes that show up when
running perf.”h]”hX/  Crashes at the first NMI.  The NMI code is separate from main
interrupt handlers and can have bugs that do not affect
normal interrupts.  Also caused by incorrectly mapping NMI
code.  NMIs that interrupt the entry code must be very
careful and can be the cause of crashes that show up when
running perf.”…””}”(hjÙ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K¬hjÕ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒiKernel crashes at the first exit to userspace.  entry_64.S
bugs, or failing to map some of the exit code.”h]”hï)”}”(hŒiKernel crashes at the first exit to userspace.  entry_64.S
bugs, or failing to map some of the exit code.”h]”hŒiKernel crashes at the first exit to userspace.  entry_64.S
bugs, or failing to map some of the exit code.”…””}”(hjñ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K²hjí  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒ¦Crashes at first interrupt that interrupts userspace. The paths
in entry_64.S that return to userspace are sometimes separate
from the ones that return to the kernel.”h]”hï)”}”(hŒ¦Crashes at first interrupt that interrupts userspace. The paths
in entry_64.S that return to userspace are sometimes separate
from the ones that return to the kernel.”h]”hŒ¦Crashes at first interrupt that interrupts userspace. The paths
in entry_64.S that return to userspace are sometimes separate
from the ones that return to the kernel.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K´hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒïDouble faults: overflowing the kernel stack because of page
faults upon page faults.  Caused by touching non-pti-mapped
data in the entry code, or forgetting to switch to kernel
CR3 before calling into C functions which are not pti-mapped.”h]”hï)”}”(hŒïDouble faults: overflowing the kernel stack because of page
faults upon page faults.  Caused by touching non-pti-mapped
data in the entry code, or forgetting to switch to kernel
CR3 before calling into C functions which are not pti-mapped.”h]”hŒïDouble faults: overflowing the kernel stack because of page
faults upon page faults.  Caused by touching non-pti-mapped
data in the entry code, or forgetting to switch to kernel
CR3 before calling into C functions which are not pti-mapped.”…””}”(hj!  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K·hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubjâ  )”}”(hŒàUserspace segfaults early in boot, sometimes manifesting
as mount(8) failing to mount the rootfs.  These have
tended to be TLB invalidation issues.  Usually invalidating
the wrong PCID, or otherwise missing an invalidation.
”h]”hï)”}”(hŒßUserspace segfaults early in boot, sometimes manifesting
as mount(8) failing to mount the rootfs.  These have
tended to be TLB invalidation issues.  Usually invalidating
the wrong PCID, or otherwise missing an invalidation.”h]”hŒßUserspace segfaults early in boot, sometimes manifesting
as mount(8) failing to mount the rootfs.  These have
tended to be TLB invalidation issues.  Usually invalidating
the wrong PCID, or otherwise missing an invalidation.”…””}”(hj9  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´K»hj5  ubah}”(h]”h ]”h"]”h$]”h&]”uh1já  hjŠ  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ*”uh1jˆ  h³hÇh´K¥hj„  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  h³hÇh´K¥hje  h²hubhŒfootnote”“”)”}”(hŒ!https://gruss.cc/files/kaiser.pdf”h]”(hŒlabel”“”)”}”(hŒ1”h]”hŒ1”…””}”(hjc  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1ja  hj]  ubhï)”}”(hj_  h]”hŒ	reference”“”)”}”(hj_  h]”hŒ!https://gruss.cc/files/kaiser.pdf”…””}”(hjv  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j_  uh1jt  hjq  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÀhj]  ubeh}”(h]”j
  ah ]”h"]”Œ1”ah$]”h&]”j  aj  j  uh1j[  h³hÇh´KÀhje  h²hj  Kubj\  )”}”(hŒ'https://meltdownattack.com/meltdown.pdf”h]”(jb  )”}”(hŒ2”h]”hŒ2”…””}”(hj•  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1ja  hj‘  ubhï)”}”(hj“  h]”ju  )”}”(hj“  h]”hŒ'https://meltdownattack.com/meltdown.pdf”…””}”(hj¦  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”j“  uh1jt  hj£  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîh³hÇh´KÁhj‘  ubeh}”(h]”j!  ah ]”h"]”Œ2”ah$]”h&]”j  aj  j  uh1j[  h³hÇh´KÁhje  h²hj  Kubeh}”(h]”Œ	debugging”ah ]”h"]”Œ	debugging”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubeh}”(h]”Œpage-table-isolation-pti”ah ]”h"]”Œpage table isolation (pti)”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
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  j¾  j!  uŒ	nametypes”}”(jÎ  ‰j[  ‰jº  ‰jZ  ‰j¬  ‰jb  ‰jÆ  ‰jŽ  ˆj¾  ˆuh}”(jË  hÊjX  hÝj  húj  j  j·  j^  jW  j½  j©  j]  j_  j¯  jÃ  je  j
  j]  j!  j‘  uŒfootnote_refs”}”(j4  ]”húaj6  ]”j  auŒcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”(j]  j‘  eŒ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”j  Ks…”R”Œparse_messages”]”hŒsystem_message”“”)”}”(hhh]”hï)”}”(hŒ:Enumerated list start value not ordinal-1: "2" (ordinal 2)”h]”hŒ>Enumerated list start value not ordinal-1: â€œ2â€ (ordinal 2)”…””}”(hja  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj^  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œsource”hÇŒline”Kuh1j\  hj½  h²hh³hÇh´KMubaŒtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
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