€•ïnŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ&/translations/zh_CN/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/zh_TW/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/it_IT/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ja_JP/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/ko_KR/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/pt_BR/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ&/translations/sp_SP/arch/x86/microcode”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œ@/var/lib/git/docbuild/linux/Documentation/arch/x86/microcode.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒThe Linux Microcode Loader”h]”hŒThe Linux Microcode Loader”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ field_list”“”)”}”(hhh]”hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒAuthors”h]”hŒAuthors”…””}”(hhéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hçhhäh³hÇh´KubhŒ field_body”“”)”}”(hŒe- Fenghua Yu - Borislav Petkov - Ashok Raj ”h]”hŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ!Fenghua Yu ”h]”hŒ paragraph”“”)”}”(hjh]”(hŒ Fenghua Yu <”…””}”(hj h²hh³Nh´NubhŒ reference”“”)”}”(hŒfenghua.yu@intel.com”h]”hŒfenghua.yu@intel.com”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:fenghua.yu@intel.com”uh1jhj ubhŒ>”…””}”(hj h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhhÿubj)”}”(hŒBorislav Petkov ”h]”j )”}”(hj5h]”(hŒBorislav Petkov <”…””}”(hj7h²hh³Nh´Nubj)”}”(hŒ bp@suse.de”h]”hŒ bp@suse.de”…””}”(hj>h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:bp@suse.de”uh1jhj7ubhŒ>”…””}”(hj7h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Khj3ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhhÿubj)”}”(hŒ Ashok Raj ”h]”j )”}”(hŒAshok Raj ”h]”(hŒ Ashok Raj <”…””}”(hjbh²hh³Nh´Nubj)”}”(hŒashok.raj@intel.com”h]”hŒashok.raj@intel.com”…””}”(hjjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:ashok.raj@intel.com”uh1jhjbubhŒ>”…””}”(hjbh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K hj^ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhhÿubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hýh³hÇh´Khhùubah}”(h]”h ]”h"]”h$]”h&]”uh1h÷hhäubeh}”(h]”h ]”h"]”h$]”h&]”uh1hâh³hÇh´Khhßh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhhÊh²hh³hÇh´Kubj )”}”(hXThe kernel has a x86 microcode loading facility which is supposed to provide microcode loading methods in the OS. Potential use cases are updating the microcode on platforms beyond the OEM End-Of-Life support, and updating the microcode on long-running systems without rebooting.”h]”hXThe kernel has a x86 microcode loading facility which is supposed to provide microcode loading methods in the OS. Potential use cases are updating the microcode on platforms beyond the OEM End-Of-Life support, and updating the microcode on long-running systems without rebooting.”…””}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K hhÊh²hubj )”}”(hŒ*The loader supports three loading methods:”h]”hŒ*The loader supports three loading methods:”…””}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒEarly load microcode”h]”hŒEarly load microcode”…””}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÀh²hh³hÇh´Kubj )”}”(hŒ”The kernel can update microcode very early during boot. Loading microcode early can fix CPU issues before they are observed during kernel boot time.”h]”hŒ”The kernel can update microcode very early during boot. Loading microcode early can fix CPU issues before they are observed during kernel boot time.”…””}”(hjÑh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÀh²hubj )”}”(hŒiThe microcode is stored in an initrd file. During boot, it is read from it and loaded into the CPU cores.”h]”hŒiThe microcode is stored in an initrd file. During boot, it is read from it and loaded into the CPU cores.”…””}”(hjßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÀh²hubj )”}”(hŒ¿The format of the combined initrd image is microcode in (uncompressed) cpio format followed by the (possibly compressed) initrd image. The loader parses the combined initrd image during boot.”h]”hŒ¿The format of the combined initrd image is microcode in (uncompressed) cpio format followed by the (possibly compressed) initrd image. The loader parses the combined initrd image during boot.”…””}”(hjíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÀh²hubj )”}”(hŒ+The microcode files in cpio name space are:”h]”hŒ+The microcode files in cpio name space are:”…””}”(hjûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K hjÀh²hubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒ/on Intel: kernel/x86/microcode/GenuineIntel.bin”h]”(hŒterm”“”)”}”(hŒ on Intel:”h]”hŒ on Intel:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K"hjubhŒ definition”“”)”}”(hhh]”j )”}”(hŒ%kernel/x86/microcode/GenuineIntel.bin”h]”hŒ%kernel/x86/microcode/GenuineIntel.bin”…””}”(hj)h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K#hj&ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K"hj ubj)”}”(hŒ0on AMD : kernel/x86/microcode/AuthenticAMD.bin ”h]”(j)”}”(hŒ on AMD :”h]”hŒ on AMD :”…””}”(hjGh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K%hjCubj%)”}”(hhh]”j )”}”(hŒ%kernel/x86/microcode/AuthenticAMD.bin”h]”hŒ%kernel/x86/microcode/AuthenticAMD.bin”…””}”(hjXh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K%hjUubah}”(h]”h ]”h"]”h$]”h&]”uh1j$hjCubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K%hj h²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1j hjÀh²hh³hÇh´Nubj )”}”(hŒßDuring BSP (BootStrapping Processor) boot (pre-SMP), the kernel scans the microcode file in the initrd. If microcode matching the CPU is found, it will be applied in the BSP and later on in all APs (Application Processors).”h]”hŒßDuring BSP (BootStrapping Processor) boot (pre-SMP), the kernel scans the microcode file in the initrd. If microcode matching the CPU is found, it will be applied in the BSP and later on in all APs (Application Processors).”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K'hjÀh²hubj )”}”(hŒ”The loader also saves the matching microcode for the CPU in memory. Thus, the cached microcode patch is applied when CPUs resume from a sleep state.”h]”hŒ”The loader also saves the matching microcode for the CPU in memory. Thus, the cached microcode patch is applied when CPUs resume from a sleep state.”…””}”(hj†h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K,hjÀh²hubj )”}”(hŒõHere's a crude example how to prepare an initrd with microcode (this is normally done automatically by the distribution, when recreating the initrd, so you don't really have to do it yourself. It is documented here for future reference only). ::”h]”hŒöHere’s a crude example how to prepare an initrd with microcode (this is normally done automatically by the distribution, when recreating the initrd, so you don’t really have to do it yourself. It is documented here for future reference only).”…””}”(hj”h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K0hjÀh²hubhŒ literal_block”“”)”}”(hX@#!/bin/bash if [ -z "$1" ]; then echo "You need to supply an initrd file" exit 1 fi INITRD="$1" DSTDIR=kernel/x86/microcode TMPDIR=/tmp/initrd rm -rf $TMPDIR mkdir $TMPDIR cd $TMPDIR mkdir -p $DSTDIR if [ -d /lib/firmware/amd-ucode ]; then cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin fi if [ -d /lib/firmware/intel-ucode ]; then cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin fi find . | cpio -o -H newc >../ucode.cpio cd .. mv $INITRD $INITRD.orig cat ucode.cpio $INITRD.orig > $INITRD rm -rf $TMPDIR”h]”hX@#!/bin/bash if [ -z "$1" ]; then echo "You need to supply an initrd file" exit 1 fi INITRD="$1" DSTDIR=kernel/x86/microcode TMPDIR=/tmp/initrd rm -rf $TMPDIR mkdir $TMPDIR cd $TMPDIR mkdir -p $DSTDIR if [ -d /lib/firmware/amd-ucode ]; then cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin fi if [ -d /lib/firmware/intel-ucode ]; then cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin fi find . | cpio -o -H newc >../ucode.cpio cd .. mv $INITRD $INITRD.orig cat ucode.cpio $INITRD.orig > $INITRD rm -rf $TMPDIR”…””}”hj¤sbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j¢h³hÇh´K6hjÀh²hubj )”}”(hŒÖThe system needs to have the microcode packages installed into /lib/firmware or you need to fixup the paths above if yours are somewhere else and/or you've downloaded them directly from the processor vendor's site.”h]”hŒÚThe system needs to have the microcode packages installed into /lib/firmware or you need to fixup the paths above if yours are somewhere else and/or you’ve downloaded them directly from the processor vendor’s site.”…””}”(hj²h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KXhjÀh²hubeh}”(h]”Œearly-load-microcode”ah ]”h"]”Œearly load microcode”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Late loading”h]”hŒ Late loading”…””}”(hjËh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÈh²hh³hÇh´K^ubj )”}”(hŒHYou simply install the microcode packages your distro supplies and run::”h]”hŒGYou simply install the microcode packages your distro supplies and run:”…””}”(hjÙh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K`hjÈh²hubj£)”}”(hŒ3# echo 1 > /sys/devices/system/cpu/microcode/reload”h]”hŒ3# echo 1 > /sys/devices/system/cpu/microcode/reload”…””}”hjçsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j¢h³hÇh´KchjÈh²hubj )”}”(hŒas root.”h]”hŒas root.”…””}”(hjõh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KehjÈh²hubj )”}”(hŒšThe loading mechanism looks for microcode blobs in /lib/firmware/{intel-ucode,amd-ucode}. The default distro installation packages already put them there.”h]”hŒšThe loading mechanism looks for microcode blobs in /lib/firmware/{intel-ucode,amd-ucode}. The default distro installation packages already put them there.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KghjÈh²hubj )”}”(hŒ:Since kernel 5.19, late loading is not enabled by default.”h]”hŒ:Since kernel 5.19, late loading is not enabled by default.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KkhjÈh²hubj )”}”(hŒ7The /dev/cpu/microcode method has been removed in 5.19.”h]”hŒ7The /dev/cpu/microcode method has been removed in 5.19.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KmhjÈh²hubeh}”(h]”Œ late-loading”ah ]”h"]”Œ late loading”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K^ubhÉ)”}”(hhh]”(hÎ)”}”(hŒWhy is late loading dangerous?”h]”hŒWhy is late loading dangerous?”…””}”(hj8h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj5h²hh³hÇh´KpubhÉ)”}”(hhh]”(hÎ)”}”(hŒSynchronizing all CPUs”h]”hŒSynchronizing all CPUs”…””}”(hjIh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjFh²hh³hÇh´Ksubj )”}”(hŒæThe microcode engine which receives the microcode update is shared between the two logical threads in a SMT system. Therefore, when the update is executed on one SMT thread of the core, the sibling "automatically" gets the update.”h]”hŒêThe microcode engine which receives the microcode update is shared between the two logical threads in a SMT system. Therefore, when the update is executed on one SMT thread of the core, the sibling “automatically†gets the update.”…””}”(hjWh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KuhjFh²hubj )”}”(hXsSince the microcode can "simulate" MSRs too, while the microcode update is in progress, those simulated MSRs transiently cease to exist. This can result in unpredictable results if the SMT sibling thread happens to be in the middle of an access to such an MSR. The usual observation is that such MSR accesses cause #GPs to be raised to signal that former are not present.”h]”hXwSince the microcode can “simulate†MSRs too, while the microcode update is in progress, those simulated MSRs transiently cease to exist. This can result in unpredictable results if the SMT sibling thread happens to be in the middle of an access to such an MSR. The usual observation is that such MSR accesses cause #GPs to be raised to signal that former are not present.”…””}”(hjeh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KzhjFh²hubj )”}”(hŒàThe disappearing MSRs are just one common issue which is being observed. Any other instruction that's being patched and gets concurrently executed by the other SMT sibling, can also result in similar, unpredictable behavior.”h]”hŒâThe disappearing MSRs are just one common issue which is being observed. Any other instruction that’s being patched and gets concurrently executed by the other SMT sibling, can also result in similar, unpredictable behavior.”…””}”(hjsh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjFh²hubj )”}”(hŒÑTo eliminate this case, a stop_machine()-based CPU synchronization was introduced as a way to guarantee that all logical CPUs will not execute any code but just wait in a spin loop, polling an atomic variable.”h]”hŒÑTo eliminate this case, a stop_machine()-based CPU synchronization was introduced as a way to guarantee that all logical CPUs will not execute any code but just wait in a spin loop, polling an atomic variable.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K†hjFh²hubj )”}”(hXWhile this took care of device or external interrupts, IPIs including LVT ones, such as CMCI etc, it cannot address other special interrupts that can't be shut off. Those are Machine Check (#MC), System Management (#SMI) and Non-Maskable interrupts (#NMI).”h]”hXWhile this took care of device or external interrupts, IPIs including LVT ones, such as CMCI etc, it cannot address other special interrupts that can’t be shut off. Those are Machine Check (#MC), System Management (#SMI) and Non-Maskable interrupts (#NMI).”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KŠhjFh²hubeh}”(h]”Œsynchronizing-all-cpus”ah ]”h"]”Œsynchronizing all cpus”ah$]”h&]”uh1hÈhj5h²hh³hÇh´KsubhÉ)”}”(hhh]”(hÎ)”}”(hŒMachine Checks”h]”hŒMachine Checks”…””}”(hj¨h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhj¥h²hh³hÇh´Kubj )”}”(hŒøMachine Checks (#MC) are non-maskable. There are two kinds of MCEs. Fatal un-recoverable MCEs and recoverable MCEs. While un-recoverable errors are fatal, recoverable errors can also happen in kernel context are also treated as fatal by the kernel.”h]”hŒøMachine Checks (#MC) are non-maskable. There are two kinds of MCEs. Fatal un-recoverable MCEs and recoverable MCEs. While un-recoverable errors are fatal, recoverable errors can also happen in kernel context are also treated as fatal by the kernel.”…””}”(hj¶h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K’hj¥h²hubj )”}”(hXwOn certain Intel machines, MCEs are also broadcast to all threads in a system. If one thread is in the middle of executing WRMSR, a MCE will be taken at the end of the flow. Either way, they will wait for the thread performing the wrmsr(0x79) to rendezvous in the MCE handler and shutdown eventually if any of the threads in the system fail to check in to the MCE rendezvous.”h]”hXwOn certain Intel machines, MCEs are also broadcast to all threads in a system. If one thread is in the middle of executing WRMSR, a MCE will be taken at the end of the flow. Either way, they will wait for the thread performing the wrmsr(0x79) to rendezvous in the MCE handler and shutdown eventually if any of the threads in the system fail to check in to the MCE rendezvous.”…””}”(hjÄh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K—hj¥h²hubj )”}”(hXTo be paranoid and get predictable behavior, the OS can choose to set MCG_STATUS.MCIP. Since MCEs can be at most one in a system, if an MCE was signaled, the above condition will promote to a system reset automatically. OS can turn off MCIP at the end of the update for that core.”h]”hXTo be paranoid and get predictable behavior, the OS can choose to set MCG_STATUS.MCIP. Since MCEs can be at most one in a system, if an MCE was signaled, the above condition will promote to a system reset automatically. OS can turn off MCIP at the end of the update for that core.”…””}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kžhj¥h²hubeh}”(h]”Œmachine-checks”ah ]”h"]”Œmachine checks”ah$]”h&]”uh1hÈhj5h²hh³hÇh´KubhÉ)”}”(hhh]”(hÎ)”}”(hŒSystem Management Interrupt”h]”hŒSystem Management Interrupt”…””}”(hjëh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjèh²hh³hÇh´K¥ubj )”}”(hX%SMIs are also broadcast to all CPUs in the platform. Microcode update requests exclusive access to the core before writing to MSR 0x79. So if it does happen such that, one thread is in WRMSR flow, and the 2nd got an SMI, that thread will be stopped in the first instruction in the SMI handler.”h]”hX%SMIs are also broadcast to all CPUs in the platform. Microcode update requests exclusive access to the core before writing to MSR 0x79. So if it does happen such that, one thread is in WRMSR flow, and the 2nd got an SMI, that thread will be stopped in the first instruction in the SMI handler.”…””}”(hjùh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K§hjèh²hubj )”}”(hŒÜSince the secondary thread is stopped in the first instruction in SMI, there is very little chance that it would be in the middle of executing an instruction being patched. Plus OS has no way to stop SMIs from happening.”h]”hŒÜSince the secondary thread is stopped in the first instruction in SMI, there is very little chance that it would be in the middle of executing an instruction being patched. Plus OS has no way to stop SMIs from happening.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K­hjèh²hubeh}”(h]”Œsystem-management-interrupt”ah ]”h"]”Œsystem management interrupt”ah$]”h&]”uh1hÈhj5h²hh³hÇh´K¥ubhÉ)”}”(hhh]”(hÎ)”}”(hŒNon-Maskable Interrupts”h]”hŒNon-Maskable Interrupts”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K³ubj )”}”(hŒ”When thread0 of a core is doing the microcode update, if thread1 is pulled into NMI, that can cause unpredictable behavior due to the reasons above.”h]”hŒ”When thread0 of a core is doing the microcode update, if thread1 is pulled into NMI, that can cause unpredictable behavior due to the reasons above.”…””}”(hj.h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kµhjh²hubj )”}”(hŒHOS can choose a variety of methods to avoid running into this situation.”h]”hŒHOS can choose a variety of methods to avoid running into this situation.”…””}”(hj<h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K¹hjh²hubeh}”(h]”Œnon-maskable-interrupts”ah ]”h"]”Œnon-maskable interrupts”ah$]”h&]”uh1hÈhj5h²hh³hÇh´K³ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ+Is the microcode suitable for late loading?”h]”hŒ+Is the microcode suitable for late loading?”…””}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjRh²hh³hÇh´K½ubj )”}”(hŒ»Late loading is done when the system is fully operational and running real workloads. Late loading behavior depends on what the base patch on the CPU is before upgrading to the new patch.”h]”hŒ»Late loading is done when the system is fully operational and running real workloads. Late loading behavior depends on what the base patch on the CPU is before upgrading to the new patch.”…””}”(hjch²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K¿hjRh²hubj )”}”(hŒThis is true for Intel CPUs.”h]”hŒThis is true for Intel CPUs.”…””}”(hjqh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÃhjRh²hubj )”}”(hŒRConsider, for example, a CPU has patch level 1 and the update is to patch level 3.”h]”hŒRConsider, for example, a CPU has patch level 1 and the update is to patch level 3.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÅhjRh²hubj )”}”(hŒSBetween patch1 and patch3, patch2 might have deprecated a software-visible feature.”h]”hŒSBetween patch1 and patch3, patch2 might have deprecated a software-visible feature.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÈhjRh²hubj )”}”(hŒ³This is unacceptable if software is even potentially using that feature. For instance, say MSR_X is no longer available after an update, accessing that MSR will cause a #GP fault.”h]”hŒ³This is unacceptable if software is even potentially using that feature. For instance, say MSR_X is no longer available after an update, accessing that MSR will cause a #GP fault.”…””}”(hj›h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KËhjRh²hubj )”}”(hŒ±Basically there is no way to declare a new microcode update suitable for late-loading. This is another one of the problems that caused late loading to be not enabled by default.”h]”hŒ±Basically there is no way to declare a new microcode update suitable for late-loading. This is another one of the problems that caused late loading to be not enabled by default.”…””}”(hj©h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÏhjRh²hubeh}”(h]”Œ*is-the-microcode-suitable-for-late-loading”ah ]”h"]”Œ+is the microcode suitable for late loading?”ah$]”h&]”uh1hÈhj5h²hh³hÇh´K½ubeh}”(h]”Œwhy-is-late-loading-dangerous”ah ]”h"]”Œwhy is late loading dangerous?”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KpubhÉ)”}”(hhh]”(hÎ)”}”(hŒBuiltin microcode”h]”hŒBuiltin microcode”…””}”(hjÊh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÇh²hh³hÇh´KÔubj )”}”(hŒ§The loader supports also loading of a builtin microcode supplied through the regular builtin firmware method CONFIG_EXTRA_FIRMWARE. Only 64-bit is currently supported.”h]”hŒ§The loader supports also loading of a builtin microcode supplied through the regular builtin firmware method CONFIG_EXTRA_FIRMWARE. Only 64-bit is currently supported.”…””}”(hjØh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÖhjÇh²hubj )”}”(hŒHere's an example::”h]”hŒHere’s an example:”…””}”(hjæh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KÚhjÇh²hubj£)”}”(hŒyCONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin" CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"”h]”hŒyCONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin" CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"”…””}”hjôsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j¢h³hÇh´KÜhjÇh²hubj )”}”(hŒEThis basically means, you have the following tree structure locally::”h]”hŒDThis basically means, you have the following tree structure locally:”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KßhjÇh²hubj£)”}”(hŒn/lib/firmware/ |-- amd-ucode ... | |-- microcode_amd_fam15h.bin ... |-- intel-ucode ... | |-- 06-3a-09 ...”h]”hŒn/lib/firmware/ |-- amd-ucode ... | |-- microcode_amd_fam15h.bin ... |-- intel-ucode ... | |-- 06-3a-09 ...”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1j¢h³hÇh´KáhjÇh²hubj )”}”(hŒ‹so that the build system can find those files and integrate them into the final kernel image. The early loader finds them and applies them.”h]”hŒ‹so that the build system can find those files and integrate them into the final kernel image. The early loader finds them and applies them.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KëhjÇh²hubj )”}”(hŒ¡Needless to say, this method is not the most flexible one because it requires rebuilding the kernel each time updated microcode from the CPU vendor is available.”h]”hŒ¡Needless to say, this method is not the most flexible one because it requires rebuilding the kernel each time updated microcode from the CPU vendor is available.”…””}”(hj,h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KîhjÇh²hubeh}”(h]”Œbuiltin-microcode”ah ]”h"]”Œbuiltin microcode”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KÔubeh}”(h]”Œthe-linux-microcode-loader”ah ]”h"]”Œthe linux microcode loader”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jmŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jGjDjÅjÂj2j/jÄjÁj¢jŸjåjâjjjOjLj¼j¹j?j<uŒ nametypes”}”(jG‰jʼnj2‰jĉj¢‰jå‰j‰jO‰j¼‰j?‰uh}”(jDhÊjÂjÀj/jÈjÁj5jŸjFjâj¥jjèjLjj¹jRj<jÇuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.