€•îl      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ&/translations/zh_CN/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/zh_TW/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/it_IT/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/ja_JP/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/ko_KR/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ&/translations/sp_SP/arch/x86/microcode”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒ@/var/lib/git/docbuild/linux/Documentation/arch/x86/microcode.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒThe Linux Microcode Loader”h]”hŒThe Linux Microcode Loader”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ
field_list”“”)”}”(hhh]”hŒfield”“”)”}”(hhh]”(hŒ
field_name”“”)”}”(hŒAuthors”h]”hŒAuthors”…””}”(hhÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÓhhÐhŸh³h K ubhŒ
field_body”“”)”}”(hŒe- Fenghua Yu <fenghua.yu@intel.com>
- Borislav Petkov <bp@suse.de>
- Ashok Raj <ashok.raj@intel.com>
”h]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ!Fenghua Yu <fenghua.yu@intel.com>”h]”hŒ	paragraph”“”)”}”(hhòh]”(hŒFenghua Yu <”…””}”(hhöhžhhŸNh NubhŒ	reference”“”)”}”(hŒfenghua.yu@intel.com”h]”hŒfenghua.yu@intel.com”…””}”(hhÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:fenghua.yu@intel.com”uh1hýhhöubhŒ>”…””}”(hhöhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khhðubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhëubhï)”}”(hŒBorislav Petkov <bp@suse.de>”h]”hõ)”}”(hj!  h]”(hŒBorislav Petkov <”…””}”(hj#  hžhhŸNh Nubhþ)”}”(hŒ
bp@suse.de”h]”hŒ
bp@suse.de”…””}”(hj*  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:bp@suse.de”uh1hýhj#  ubhŒ>”…””}”(hj#  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhëubhï)”}”(hŒ Ashok Raj <ashok.raj@intel.com>
”h]”hõ)”}”(hŒAshok Raj <ashok.raj@intel.com>”h]”(hŒAshok Raj <”…””}”(hjN  hžhhŸNh Nubhþ)”}”(hŒashok.raj@intel.com”h]”hŒashok.raj@intel.com”…””}”(hjV  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:ashok.raj@intel.com”uh1hýhjN  ubhŒ>”…””}”(hjN  hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K	hjJ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhëubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1héhŸh³h Khhåubah}”(h]”h ]”h"]”h$]”h&]”uh1hãhhÐubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h KhhËhžhubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhh¶hžhhŸh³h Kubhõ)”}”(hX  The kernel has a x86 microcode loading facility which is supposed to
provide microcode loading methods in the OS. Potential use cases are
updating the microcode on platforms beyond the OEM End-Of-Life support,
and updating the microcode on long-running systems without rebooting.”h]”hX  The kernel has a x86 microcode loading facility which is supposed to
provide microcode loading methods in the OS. Potential use cases are
updating the microcode on platforms beyond the OEM End-Of-Life support,
and updating the microcode on long-running systems without rebooting.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khh¶hžhubhõ)”}”(hŒ*The loader supports three loading methods:”h]”hŒ*The loader supports three loading methods:”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒEarly load microcode”h]”hŒEarly load microcode”…””}”(hj¯  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj¬  hžhhŸh³h Kubhõ)”}”(hŒ”The kernel can update microcode very early during boot. Loading
microcode early can fix CPU issues before they are observed during
kernel boot time.”h]”hŒ”The kernel can update microcode very early during boot. Loading
microcode early can fix CPU issues before they are observed during
kernel boot time.”…””}”(hj½  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj¬  hžhubhõ)”}”(hŒiThe microcode is stored in an initrd file. During boot, it is read from
it and loaded into the CPU cores.”h]”hŒiThe microcode is stored in an initrd file. During boot, it is read from
it and loaded into the CPU cores.”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj¬  hžhubhõ)”}”(hŒ¿The format of the combined initrd image is microcode in (uncompressed)
cpio format followed by the (possibly compressed) initrd image. The
loader parses the combined initrd image during boot.”h]”hŒ¿The format of the combined initrd image is microcode in (uncompressed)
cpio format followed by the (possibly compressed) initrd image. The
loader parses the combined initrd image during boot.”…””}”(hjÙ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj¬  hžhubhõ)”}”(hŒ+The microcode files in cpio name space are:”h]”hŒ+The microcode files in cpio name space are:”…””}”(hjç  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K hj¬  hžhubhŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒ/on Intel:
kernel/x86/microcode/GenuineIntel.bin”h]”(hŒterm”“”)”}”(hŒ	on Intel:”h]”hŒ	on Intel:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j   hŸh³h K"hjü  ubhŒ
definition”“”)”}”(hhh]”hõ)”}”(hŒ%kernel/x86/microcode/GenuineIntel.bin”h]”hŒ%kernel/x86/microcode/GenuineIntel.bin”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K#hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjü  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jú  hŸh³h K"hj÷  ubjû  )”}”(hŒ0on AMD  :
kernel/x86/microcode/AuthenticAMD.bin
”h]”(j  )”}”(hŒ	on AMD  :”h]”hŒ	on AMD  :”…””}”(hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j   hŸh³h K%hj/  ubj  )”}”(hhh]”hõ)”}”(hŒ%kernel/x86/microcode/AuthenticAMD.bin”h]”hŒ%kernel/x86/microcode/AuthenticAMD.bin”…””}”(hjD  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K%hjA  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj/  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jú  hŸh³h K%hj÷  hžhubeh}”(h]”h ]”h"]”h$]”h&]”uh1jõ  hj¬  hžhhŸh³h Nubhõ)”}”(hŒßDuring BSP (BootStrapping Processor) boot (pre-SMP), the kernel
scans the microcode file in the initrd. If microcode matching the
CPU is found, it will be applied in the BSP and later on in all APs
(Application Processors).”h]”hŒßDuring BSP (BootStrapping Processor) boot (pre-SMP), the kernel
scans the microcode file in the initrd. If microcode matching the
CPU is found, it will be applied in the BSP and later on in all APs
(Application Processors).”…””}”(hjd  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K'hj¬  hžhubhõ)”}”(hŒ”The loader also saves the matching microcode for the CPU in memory.
Thus, the cached microcode patch is applied when CPUs resume from a
sleep state.”h]”hŒ”The loader also saves the matching microcode for the CPU in memory.
Thus, the cached microcode patch is applied when CPUs resume from a
sleep state.”…””}”(hjr  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K,hj¬  hžhubhõ)”}”(hŒõHere's a crude example how to prepare an initrd with microcode (this is
normally done automatically by the distribution, when recreating the
initrd, so you don't really have to do it yourself. It is documented
here for future reference only).
::”h]”hŒöHereâ€™s a crude example how to prepare an initrd with microcode (this is
normally done automatically by the distribution, when recreating the
initrd, so you donâ€™t really have to do it yourself. It is documented
here for future reference only).”…””}”(hj€  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K0hj¬  hžhubhŒliteral_block”“”)”}”(hX@  #!/bin/bash

if [ -z "$1" ]; then
    echo "You need to supply an initrd file"
    exit 1
fi

INITRD="$1"

DSTDIR=kernel/x86/microcode
TMPDIR=/tmp/initrd

rm -rf $TMPDIR

mkdir $TMPDIR
cd $TMPDIR
mkdir -p $DSTDIR

if [ -d /lib/firmware/amd-ucode ]; then
        cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
fi

if [ -d /lib/firmware/intel-ucode ]; then
        cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin
fi

find . | cpio -o -H newc >../ucode.cpio
cd ..
mv $INITRD $INITRD.orig
cat ucode.cpio $INITRD.orig > $INITRD

rm -rf $TMPDIR”h]”hX@  #!/bin/bash

if [ -z "$1" ]; then
    echo "You need to supply an initrd file"
    exit 1
fi

INITRD="$1"

DSTDIR=kernel/x86/microcode
TMPDIR=/tmp/initrd

rm -rf $TMPDIR

mkdir $TMPDIR
cd $TMPDIR
mkdir -p $DSTDIR

if [ -d /lib/firmware/amd-ucode ]; then
        cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
fi

if [ -d /lib/firmware/intel-ucode ]; then
        cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin
fi

find . | cpio -o -H newc >../ucode.cpio
cd ..
mv $INITRD $INITRD.orig
cat ucode.cpio $INITRD.orig > $INITRD

rm -rf $TMPDIR”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jŽ  hŸh³h K6hj¬  hžhubhõ)”}”(hŒÖThe system needs to have the microcode packages installed into
/lib/firmware or you need to fixup the paths above if yours are
somewhere else and/or you've downloaded them directly from the processor
vendor's site.”h]”hŒÚThe system needs to have the microcode packages installed into
/lib/firmware or you need to fixup the paths above if yours are
somewhere else and/or youâ€™ve downloaded them directly from the processor
vendorâ€™s site.”…””}”(hjž  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KXhj¬  hžhubeh}”(h]”Œearly-load-microcode”ah ]”h"]”Œearly load microcode”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒLate loading”h]”hŒLate loading”…””}”(hj·  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj´  hžhhŸh³h K^ubhõ)”}”(hŒHYou simply install the microcode packages your distro supplies and
run::”h]”hŒGYou simply install the microcode packages your distro supplies and
run:”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K`hj´  hžhubj  )”}”(hŒ3# echo 1 > /sys/devices/system/cpu/microcode/reload”h]”hŒ3# echo 1 > /sys/devices/system/cpu/microcode/reload”…””}”hjÓ  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jŽ  hŸh³h Kchj´  hžhubhõ)”}”(hŒas root.”h]”hŒas root.”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kehj´  hžhubhõ)”}”(hŒšThe loading mechanism looks for microcode blobs in
/lib/firmware/{intel-ucode,amd-ucode}. The default distro installation
packages already put them there.”h]”hŒšThe loading mechanism looks for microcode blobs in
/lib/firmware/{intel-ucode,amd-ucode}. The default distro installation
packages already put them there.”…””}”(hjï  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kghj´  hžhubhõ)”}”(hŒ:Since kernel 5.19, late loading is not enabled by default.”h]”hŒ:Since kernel 5.19, late loading is not enabled by default.”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kkhj´  hžhubhõ)”}”(hŒ7The /dev/cpu/microcode method has been removed in 5.19.”h]”hŒ7The /dev/cpu/microcode method has been removed in 5.19.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kmhj´  hžhubeh}”(h]”Œlate-loading”ah ]”h"]”Œlate loading”ah$]”h&]”uh1h´hh¶hžhhŸh³h K^ubhµ)”}”(hhh]”(hº)”}”(hŒWhy is late loading dangerous?”h]”hŒWhy is late loading dangerous?”…””}”(hj$  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj!  hžhhŸh³h Kpubhµ)”}”(hhh]”(hº)”}”(hŒSynchronizing all CPUs”h]”hŒSynchronizing all CPUs”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj2  hžhhŸh³h Ksubhõ)”}”(hŒæThe microcode engine which receives the microcode update is shared
between the two logical threads in a SMT system. Therefore, when
the update is executed on one SMT thread of the core, the sibling
"automatically" gets the update.”h]”hŒêThe microcode engine which receives the microcode update is shared
between the two logical threads in a SMT system. Therefore, when
the update is executed on one SMT thread of the core, the sibling
â€œautomaticallyâ€ gets the update.”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kuhj2  hžhubhõ)”}”(hXs  Since the microcode can "simulate" MSRs too, while the microcode update
is in progress, those simulated MSRs transiently cease to exist. This
can result in unpredictable results if the SMT sibling thread happens to
be in the middle of an access to such an MSR. The usual observation is
that such MSR accesses cause #GPs to be raised to signal that former are
not present.”h]”hXw  Since the microcode can â€œsimulateâ€ MSRs too, while the microcode update
is in progress, those simulated MSRs transiently cease to exist. This
can result in unpredictable results if the SMT sibling thread happens to
be in the middle of an access to such an MSR. The usual observation is
that such MSR accesses cause #GPs to be raised to signal that former are
not present.”…””}”(hjQ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kzhj2  hžhubhõ)”}”(hŒàThe disappearing MSRs are just one common issue which is being observed.
Any other instruction that's being patched and gets concurrently
executed by the other SMT sibling, can also result in similar,
unpredictable behavior.”h]”hŒâThe disappearing MSRs are just one common issue which is being observed.
Any other instruction thatâ€™s being patched and gets concurrently
executed by the other SMT sibling, can also result in similar,
unpredictable behavior.”…””}”(hj_  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj2  hžhubhõ)”}”(hŒÑTo eliminate this case, a stop_machine()-based CPU synchronization was
introduced as a way to guarantee that all logical CPUs will not execute
any code but just wait in a spin loop, polling an atomic variable.”h]”hŒÑTo eliminate this case, a stop_machine()-based CPU synchronization was
introduced as a way to guarantee that all logical CPUs will not execute
any code but just wait in a spin loop, polling an atomic variable.”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K†hj2  hžhubhõ)”}”(hX   While this took care of device or external interrupts, IPIs including
LVT ones, such as CMCI etc, it cannot address other special interrupts
that can't be shut off. Those are Machine Check (#MC), System Management
(#SMI) and Non-Maskable interrupts (#NMI).”h]”hX  While this took care of device or external interrupts, IPIs including
LVT ones, such as CMCI etc, it cannot address other special interrupts
that canâ€™t be shut off. Those are Machine Check (#MC), System Management
(#SMI) and Non-Maskable interrupts (#NMI).”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KŠhj2  hžhubeh}”(h]”Œsynchronizing-all-cpus”ah ]”h"]”Œsynchronizing all cpus”ah$]”h&]”uh1h´hj!  hžhhŸh³h Ksubhµ)”}”(hhh]”(hº)”}”(hŒMachine Checks”h]”hŒMachine Checks”…””}”(hj”  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj‘  hžhhŸh³h Kubhõ)”}”(hŒøMachine Checks (#MC) are non-maskable. There are two kinds of MCEs.
Fatal un-recoverable MCEs and recoverable MCEs. While un-recoverable
errors are fatal, recoverable errors can also happen in kernel context
are also treated as fatal by the kernel.”h]”hŒøMachine Checks (#MC) are non-maskable. There are two kinds of MCEs.
Fatal un-recoverable MCEs and recoverable MCEs. While un-recoverable
errors are fatal, recoverable errors can also happen in kernel context
are also treated as fatal by the kernel.”…””}”(hj¢  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K’hj‘  hžhubhõ)”}”(hXw  On certain Intel machines, MCEs are also broadcast to all threads in a
system. If one thread is in the middle of executing WRMSR, a MCE will be
taken at the end of the flow. Either way, they will wait for the thread
performing the wrmsr(0x79) to rendezvous in the MCE handler and shutdown
eventually if any of the threads in the system fail to check in to the
MCE rendezvous.”h]”hXw  On certain Intel machines, MCEs are also broadcast to all threads in a
system. If one thread is in the middle of executing WRMSR, a MCE will be
taken at the end of the flow. Either way, they will wait for the thread
performing the wrmsr(0x79) to rendezvous in the MCE handler and shutdown
eventually if any of the threads in the system fail to check in to the
MCE rendezvous.”…””}”(hj°  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K—hj‘  hžhubhõ)”}”(hX  To be paranoid and get predictable behavior, the OS can choose to set
MCG_STATUS.MCIP. Since MCEs can be at most one in a system, if an
MCE was signaled, the above condition will promote to a system reset
automatically. OS can turn off MCIP at the end of the update for that
core.”h]”hX  To be paranoid and get predictable behavior, the OS can choose to set
MCG_STATUS.MCIP. Since MCEs can be at most one in a system, if an
MCE was signaled, the above condition will promote to a system reset
automatically. OS can turn off MCIP at the end of the update for that
core.”…””}”(hj¾  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kžhj‘  hžhubeh}”(h]”Œmachine-checks”ah ]”h"]”Œmachine checks”ah$]”h&]”uh1h´hj!  hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒSystem Management Interrupt”h]”hŒSystem Management Interrupt”…””}”(hj×  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjÔ  hžhhŸh³h K¥ubhõ)”}”(hX%  SMIs are also broadcast to all CPUs in the platform. Microcode update
requests exclusive access to the core before writing to MSR 0x79. So if
it does happen such that, one thread is in WRMSR flow, and the 2nd got
an SMI, that thread will be stopped in the first instruction in the SMI
handler.”h]”hX%  SMIs are also broadcast to all CPUs in the platform. Microcode update
requests exclusive access to the core before writing to MSR 0x79. So if
it does happen such that, one thread is in WRMSR flow, and the 2nd got
an SMI, that thread will be stopped in the first instruction in the SMI
handler.”…””}”(hjå  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K§hjÔ  hžhubhõ)”}”(hŒÜSince the secondary thread is stopped in the first instruction in SMI,
there is very little chance that it would be in the middle of executing
an instruction being patched. Plus OS has no way to stop SMIs from
happening.”h]”hŒÜSince the secondary thread is stopped in the first instruction in SMI,
there is very little chance that it would be in the middle of executing
an instruction being patched. Plus OS has no way to stop SMIs from
happening.”…””}”(hjó  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K­hjÔ  hžhubeh}”(h]”Œsystem-management-interrupt”ah ]”h"]”Œsystem management interrupt”ah$]”h&]”uh1h´hj!  hžhhŸh³h K¥ubhµ)”}”(hhh]”(hº)”}”(hŒNon-Maskable Interrupts”h]”hŒNon-Maskable Interrupts”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj	  hžhhŸh³h K³ubhõ)”}”(hŒ”When thread0 of a core is doing the microcode update, if thread1 is
pulled into NMI, that can cause unpredictable behavior due to the
reasons above.”h]”hŒ”When thread0 of a core is doing the microcode update, if thread1 is
pulled into NMI, that can cause unpredictable behavior due to the
reasons above.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kµhj	  hžhubhõ)”}”(hŒHOS can choose a variety of methods to avoid running into this situation.”h]”hŒHOS can choose a variety of methods to avoid running into this situation.”…””}”(hj(  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K¹hj	  hžhubeh}”(h]”Œnon-maskable-interrupts”ah ]”h"]”Œnon-maskable interrupts”ah$]”h&]”uh1h´hj!  hžhhŸh³h K³ubhµ)”}”(hhh]”(hº)”}”(hŒ+Is the microcode suitable for late loading?”h]”hŒ+Is the microcode suitable for late loading?”…””}”(hjA  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj>  hžhhŸh³h K½ubhõ)”}”(hŒ»Late loading is done when the system is fully operational and running
real workloads. Late loading behavior depends on what the base patch on
the CPU is before upgrading to the new patch.”h]”hŒ»Late loading is done when the system is fully operational and running
real workloads. Late loading behavior depends on what the base patch on
the CPU is before upgrading to the new patch.”…””}”(hjO  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K¿hj>  hžhubhõ)”}”(hŒThis is true for Intel CPUs.”h]”hŒThis is true for Intel CPUs.”…””}”(hj]  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÃhj>  hžhubhõ)”}”(hŒRConsider, for example, a CPU has patch level 1 and the update is to
patch level 3.”h]”hŒRConsider, for example, a CPU has patch level 1 and the update is to
patch level 3.”…””}”(hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÅhj>  hžhubhõ)”}”(hŒSBetween patch1 and patch3, patch2 might have deprecated a software-visible
feature.”h]”hŒSBetween patch1 and patch3, patch2 might have deprecated a software-visible
feature.”…””}”(hjy  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÈhj>  hžhubhõ)”}”(hŒ³This is unacceptable if software is even potentially using that feature.
For instance, say MSR_X is no longer available after an update,
accessing that MSR will cause a #GP fault.”h]”hŒ³This is unacceptable if software is even potentially using that feature.
For instance, say MSR_X is no longer available after an update,
accessing that MSR will cause a #GP fault.”…””}”(hj‡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KËhj>  hžhubhõ)”}”(hŒ±Basically there is no way to declare a new microcode update suitable
for late-loading. This is another one of the problems that caused late
loading to be not enabled by default.”h]”hŒ±Basically there is no way to declare a new microcode update suitable
for late-loading. This is another one of the problems that caused late
loading to be not enabled by default.”…””}”(hj•  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÏhj>  hžhubeh}”(h]”Œ*is-the-microcode-suitable-for-late-loading”ah ]”h"]”Œ+is the microcode suitable for late loading?”ah$]”h&]”uh1h´hj!  hžhhŸh³h K½ubeh}”(h]”Œwhy-is-late-loading-dangerous”ah ]”h"]”Œwhy is late loading dangerous?”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kpubhµ)”}”(hhh]”(hº)”}”(hŒBuiltin microcode”h]”hŒBuiltin microcode”…””}”(hj¶  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj³  hžhhŸh³h KÔubhõ)”}”(hŒ§The loader supports also loading of a builtin microcode supplied through
the regular builtin firmware method CONFIG_EXTRA_FIRMWARE. Only 64-bit is
currently supported.”h]”hŒ§The loader supports also loading of a builtin microcode supplied through
the regular builtin firmware method CONFIG_EXTRA_FIRMWARE. Only 64-bit is
currently supported.”…””}”(hjÄ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÖhj³  hžhubhõ)”}”(hŒHere's an example::”h]”hŒHereâ€™s an example:”…””}”(hjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÚhj³  hžhubj  )”}”(hŒyCONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"”h]”hŒyCONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"”…””}”hjà  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jŽ  hŸh³h KÜhj³  hžhubhõ)”}”(hŒEThis basically means, you have the following tree structure locally::”h]”hŒDThis basically means, you have the following tree structure locally:”…””}”(hjî  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kßhj³  hžhubj  )”}”(hŒn/lib/firmware/
|-- amd-ucode
...
|   |-- microcode_amd_fam15h.bin
...
|-- intel-ucode
...
|   |-- 06-3a-09
...”h]”hŒn/lib/firmware/
|-- amd-ucode
...
|   |-- microcode_amd_fam15h.bin
...
|-- intel-ucode
...
|   |-- 06-3a-09
...”…””}”hjü  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jŽ  hŸh³h Káhj³  hžhubhõ)”}”(hŒ‹so that the build system can find those files and integrate them into
the final kernel image. The early loader finds them and applies them.”h]”hŒ‹so that the build system can find those files and integrate them into
the final kernel image. The early loader finds them and applies them.”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Këhj³  hžhubhõ)”}”(hŒ¡Needless to say, this method is not the most flexible one because it
requires rebuilding the kernel each time updated microcode from the CPU
vendor is available.”h]”hŒ¡Needless to say, this method is not the most flexible one because it
requires rebuilding the kernel each time updated microcode from the CPU
vendor is available.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kîhj³  hžhubeh}”(h]”Œbuiltin-microcode”ah ]”h"]”Œbuiltin microcode”ah$]”h&]”uh1h´hh¶hžhhŸh³h KÔubeh}”(h]”Œthe-linux-microcode-loader”ah ]”h"]”Œthe linux microcode loader”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jY  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j3  j0  j±  j®  j  j  j°  j­  jŽ  j‹  jÑ  jÎ  j  j  j;  j8  j¨  j¥  j+  j(  uŒ	nametypes”}”(j3  ‰j±  ‰j  ‰j°  ‰jŽ  ‰jÑ  ‰j  ‰j;  ‰j¨  ‰j+  ‰uh}”(j0  h¶j®  j¬  j  j´  j­  j!  j‹  j2  jÎ  j‘  j  jÔ  j8  j	  j¥  j>  j(  j³  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.