Wsphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget2/translations/zh_CN/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/zh_TW/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/it_IT/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ja_JP/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/ko_KR/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/pt_BR/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget2/translations/sp_SP/arch/x86/amd-memory-encryptionmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhL/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-memory-encryption.rsthKubhsection)}(hhh](htitle)}(hAMD Memory Encryptionh]hAMD Memory Encryption}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hnSecure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are features found on AMD processors.h]hnSecure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are features found on AMD processors.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXESME provides the ability to mark individual pages of memory as encrypted using the standard x86 page tables. A page that is marked encrypted will be automatically decrypted when read from DRAM and encrypted when written to DRAM. SME can therefore be used to protect the contents of DRAM from physical attacks on the system.h]hXESME provides the ability to mark individual pages of memory as encrypted using the standard x86 page tables. A page that is marked encrypted will be automatically decrypted when read from DRAM and encrypted when written to DRAM. SME can therefore be used to protect the contents of DRAM from physical attacks on the system.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXSEV enables running encrypted virtual machines (VMs) in which the code and data of the guest VM are secured so that a decrypted version is available only within the VM itself. SEV guest VMs have the concept of private and shared memory. Private memory is encrypted with the guest-specific key, while shared memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor key is the same key which is used in SME.h]hXSEV enables running encrypted virtual machines (VMs) in which the code and data of the guest VM are secured so that a decrypted version is available only within the VM itself. SEV guest VMs have the concept of private and shared memory. Private memory is encrypted with the guest-specific key, while shared memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor key is the same key which is used in SME.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXVA page is encrypted when a page table entry has the encryption bit set (see below on how to determine its position). The encryption bit can also be specified in the cr3 register, allowing the PGD table to be encrypted. Each successive level of page tables can also be encrypted by setting the encryption bit in the page table entry that points to the next table. This allows the full page table hierarchy to be encrypted. Note, this means that just because the encryption bit is set in cr3, doesn't imply the full hierarchy is encrypted. Each page table entry in the hierarchy needs to have the encryption bit set to achieve that. So, theoretically, you could have the encryption bit set in cr3 so that the PGD is encrypted, but not set the encryption bit in the PGD entry for a PUD which results in the PUD pointed to by that entry to not be encrypted.h]hXXA page is encrypted when a page table entry has the encryption bit set (see below on how to determine its position). The encryption bit can also be specified in the cr3 register, allowing the PGD table to be encrypted. Each successive level of page tables can also be encrypted by setting the encryption bit in the page table entry that points to the next table. This allows the full page table hierarchy to be encrypted. Note, this means that just because the encryption bit is set in cr3, doesn’t imply the full hierarchy is encrypted. Each page table entry in the hierarchy needs to have the encryption bit set to achieve that. So, theoretically, you could have the encryption bit set in cr3 so that the PGD is encrypted, but not set the encryption bit in the PGD entry for a PUD which results in the PUD pointed to by that entry to not be encrypted.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXcWhen SEV is enabled, instruction pages and guest page tables are always treated as private. All the DMA operations inside the guest must be performed on shared memory. Since the memory encryption bit is controlled by the guest OS when it is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware forces the memory encryption bit to 1.h]hXcWhen SEV is enabled, instruction pages and guest page tables are always treated as private. All the DMA operations inside the guest must be performed on shared memory. Since the memory encryption bit is controlled by the guest OS when it is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware forces the memory encryption bit to 1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hhhhubh)}(hSupport for SME and SEV can be determined through the CPUID instruction. The CPUID function 0x8000001f reports information related to SME::h]hSupport for SME and SEV can be determined through the CPUID instruction. The CPUID function 0x8000001f reports information related to SME:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hhhhubh literal_block)}(hX0x8000001f[eax]: Bit[0] indicates support for SME Bit[1] indicates support for SEV 0x8000001f[ebx]: Bits[5:0] pagetable bit number used to activate memory encryption Bits[11:6] reduction in physical address space, in bits, when memory encryption is enabled (this only affects system physical addresses, not guest physical addresses)h]hX0x8000001f[eax]: Bit[0] indicates support for SME Bit[1] indicates support for SEV 0x8000001f[ebx]: Bits[5:0] pagetable bit number used to activate memory encryption Bits[11:6] reduction in physical address space, in bits, when memory encryption is enabled (this only affects system physical addresses, not guest physical addresses)}hj5sbah}(h]h ]h"]h$]h&]hhuh1j3hhhK-hhhhubh)}(hIf support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to determine if SME is enabled and/or to enable memory encryption::h]hIf support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to determine if SME is enabled and/or to enable memory encryption:}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hhhhubj4)}(h0xc0010010: Bit[23] 0 = memory encryption features are disabled 1 = memory encryption features are enabledh]h0xc0010010: Bit[23] 0 = memory encryption features are disabled 1 = memory encryption features are enabled}hjQsbah}(h]h ]h"]h$]h&]hhuh1j3hhhK;hhhhubh)}(h_If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if SEV is active::h]h^If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if SEV is active:}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hhhhubj4)}(hs0xc0010131: Bit[0] 0 = memory encryption is not active 1 = memory encryption is activeh]hs0xc0010131: Bit[0] 0 = memory encryption is not active 1 = memory encryption is active}hjmsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKBhhhhubh)}(hX|Linux relies on BIOS to set this bit if BIOS has determined that the reduction in the physical address space as a result of enabling memory encryption (see CPUID information above) will not conflict with the address space resource requirements for the system. If this bit is not set upon Linux startup then Linux itself will not set it and memory encryption will not be possible.h]hX|Linux relies on BIOS to set this bit if BIOS has determined that the reduction in the physical address space as a result of enabling memory encryption (see CPUID information above) will not conflict with the address space resource requirements for the system. If this bit is not set upon Linux startup then Linux itself will not set it and memory encryption will not be possible.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKFhhhhubh)}(hBThe state of SME in the Linux kernel can be documented as follows:h]hBThe state of SME in the Linux kernel can be documented as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhhhhubh block_quote)}(hX,- Supported: The CPU supports SME (determined through CPUID instruction). - Enabled: Supported and bit 23 of MSR_AMD64_SYSCFG is set. - Active: Supported, Enabled and the Linux kernel is actively applying the encryption bit to page table entries (the SME mask in the kernel is non-zero). h]h bullet_list)}(hhh](h list_item)}(hHSupported: The CPU supports SME (determined through CPUID instruction). h]h)}(hGSupported: The CPU supports SME (determined through CPUID instruction).h]hGSupported: The CPU supports SME (determined through CPUID instruction).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h:Enabled: Supported and bit 23 of MSR_AMD64_SYSCFG is set. h]h)}(h9Enabled: Supported and bit 23 of MSR_AMD64_SYSCFG is set.h]h9Enabled: Supported and bit 23 of MSR_AMD64_SYSCFG is set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hActive: Supported, Enabled and the Linux kernel is actively applying the encryption bit to page table entries (the SME mask in the kernel is non-zero). h]h)}(hActive: Supported, Enabled and the Linux kernel is actively applying the encryption bit to page table entries (the SME mask in the kernel is non-zero).h]hActive: Supported, Enabled and the Linux kernel is actively applying the encryption bit to page table entries (the SME mask in the kernel is non-zero).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKNhjubah}(h]h ]h"]h$]h&]uh1jhhhKNhhhhubh)}(hSME can also be enabled and activated in the BIOS. If SME is enabled and activated in the BIOS, then all memory accesses will be encrypted and it will not be necessary to activate the Linux memory encryption support.h]hSME can also be enabled and activated in the BIOS. If SME is enabled and activated in the BIOS, then all memory accesses will be encrypted and it will not be necessary to activate the Linux memory encryption support.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhhhhubh)}(hXgIf the BIOS merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG), then memory encryption can be enabled by supplying mem_encrypt=on on the kernel command line. However, if BIOS does not enable SME, then Linux will not be able to activate memory encryption, even if configured to do so by default or the mem_encrypt=on command line parameter is specified.h]hXgIf the BIOS merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG), then memory encryption can be enabled by supplying mem_encrypt=on on the kernel command line. However, if BIOS does not enable SME, then Linux will not be able to activate memory encryption, even if configured to do so by default or the mem_encrypt=on command line parameter is specified.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hhhhubh)}(hhh](h)}(hSecure Nested Paging (SNP)h]hSecure Nested Paging (SNP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKdubh)}(hX>SEV-SNP introduces new features (SEV_FEATURES[1:63]) which can be enabled by the hypervisor for security enhancements. Some of these features need guest side implementation to function correctly. The below table lists the expected guest behavior with various possible scenarios of guest/hypervisor SNP feature support.h]hX>SEV-SNP introduces new features (SEV_FEATURES[1:63]) which can be enabled by the hypervisor for security enhancements. Some of these features need guest side implementation to function correctly. The below table lists the expected guest behavior with various possible scenarios of guest/hypervisor SNP feature support.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j?hj<ubj@)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j?hj<ubj@)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j?hj<ubj@)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j?hj<ubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hFeature Enabled by the HVh]hFeature Enabled by the HV}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjuubah}(h]h ]h"]h$]h&]uh1jshjpubjt)}(hhh]h)}(hGuest needs implementationh]hGuest needs implementation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jshjpubjt)}(hhh]h)}(hGuest has implementationh]hGuest has implementation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jshjpubjt)}(hhh]h)}(hGuest boot behaviourh]hGuest boot behaviour}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhjubah}(h]h ]h"]h$]h&]uh1jshjpubeh}(h]h ]h"]h$]h&]uh1jnhjkubah}(h]h ]h"]h$]h&]uh1jihj<ubhtbody)}(hhh](jo)}(hhh](jt)}(hhh]h)}(hNoh]hNo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hNoh]hNo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hNoh]hNo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hBooth]hBoot}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphj*ubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hNoh]hNo}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjJubah}(h]h ]h"]h$]h&]uh1jshjGubjt)}(hhh]h)}(hYesh]hYes}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjaubah}(h]h ]h"]h$]h&]uh1jshjGubjt)}(hhh]h)}(hNoh]hNo}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjxubah}(h]h ]h"]h$]h&]uh1jshjGubjt)}(hhh]h)}(hBooth]hBoot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1jshjGubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hNoh]hNo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hBooth]hBoot}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hNoh]hNo}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhj+ubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hNoh]hNo}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjBubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hBoot with feature enabledh]hBoot with feature enabled}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjYubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hYesh]hYes}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjyubah}(h]h ]h"]h$]h&]uh1jshjvubjt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjubah}(h]h ]h"]h$]h&]uh1jshjvubjt)}(hhh]h)}(hNoh]hNo}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjubah}(h]h ]h"]h$]h&]uh1jshjvubjt)}(hhh]h)}(hGraceful boot failureh]hGraceful boot failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hjubah}(h]h ]h"]h$]h&]uh1jshjvubeh}(h]h ]h"]h$]h&]uh1jnhjubjo)}(hhh](jt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hYesh]hYes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jshjubjt)}(hhh]h)}(hBoot with feature enabledh]hBoot with feature enabled}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#ubah}(h]h ]h"]h$]h&]uh1jshjubeh}(h]h ]h"]h$]h&]uh1jnhjubeh}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]colsKuh1j:hj7ubah}(h]h ]h"]h$]h&]uh1j5hjhhhhhNubh)}(h;More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSRh]h;More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSR}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]secure-nested-paging-snpah ]h"]secure nested paging (snp)ah$]h&]uh1hhhhhhhhKdubh)}(hhh](h)}(hReverse Map Table (RMP)h]hReverse Map Table (RMP)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhhhhKubh)}(hThe RMP is a structure in system memory that is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses. Each page of memory that is potentially assignable to guests has one entry within the RMP.h]hThe RMP is a structure in system memory that is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses. Each page of memory that is potentially assignable to guests has one entry within the RMP.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjihhubh)}(hWThe RMP table can be either contiguous in memory or a collection of segments in memory.h]hWThe RMP table can be either contiguous in memory or a collection of segments in memory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjihhubh)}(hhh](h)}(hContiguous RMPh]hContiguous RMP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hSupport for this form of the RMP is present when support for SEV-SNP is present, which can be determined using the CPUID instruction::h]hSupport for this form of the RMP is present when support for SEV-SNP is present, which can be determined using the CPUID instruction:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(h=0x8000001f[eax]: Bit[4] indicates support for SEV-SNPh]h=0x8000001f[eax]: Bit[4] indicates support for SEV-SNP}hjsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hHThe location of the RMP is identified to the hardware through two MSRs::h]hGThe location of the RMP is identified to the hardware through two MSRs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(h0xc0010132 (RMP_BASE): System physical address of the first byte of the RMP 0xc0010133 (RMP_END): System physical address of the last byte of the RMPh]h0xc0010132 (RMP_BASE): System physical address of the first byte of the RMP 0xc0010133 (RMP_END): System physical address of the last byte of the RMP}hjsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hHardware requires that RMP_BASE and (RPM_END + 1) be 8KB aligned, but SEV firmware increases the alignment requirement to require a 1MB alignment.h]hHardware requires that RMP_BASE and (RPM_END + 1) be 8KB aligned, but SEV firmware increases the alignment requirement to require a 1MB alignment.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe RMP consists of a 16KB region used for processor bookkeeping followed by the RMP entries, which are 16 bytes in size. The size of the RMP determines the range of physical memory that the hypervisor can assign to SEV-SNP guests. The RMP covers the system physical address from::h]hXThe RMP consists of a 16KB region used for processor bookkeeping followed by the RMP entries, which are 16 bytes in size. The size of the RMP determines the range of physical memory that the hypervisor can assign to SEV-SNP guests. The RMP covers the system physical address from:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(h30 to ((RMP_END + 1 - RMP_BASE - 16KB) / 16B) x 4KB.h]h30 to ((RMP_END + 1 - RMP_BASE - 16KB) / 16B) x 4KB.}hjsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hXThe current Linux support relies on BIOS to allocate/reserve the memory for the RMP and to set RMP_BASE and RMP_END appropriately. Linux uses the MSR values to locate the RMP and determine the size of the RMP. The RMP must cover all of system memory in order for Linux to enable SEV-SNP.h]hXThe current Linux support relies on BIOS to allocate/reserve the memory for the RMP and to set RMP_BASE and RMP_END appropriately. Linux uses the MSR values to locate the RMP and determine the size of the RMP. The RMP must cover all of system memory in order for Linux to enable SEV-SNP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]contiguous-rmpah ]h"]contiguous rmpah$]h&]uh1hhjihhhhhKubh)}(hhh](h)}(h Segmented RMPh]h Segmented RMP}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hX,Segmented RMP support is a new way of representing the layout of an RMP. Initial RMP support required the RMP table to be contiguous in memory. RMP accesses from a NUMA node on which the RMP doesn't reside can take longer than accesses from a NUMA node on which the RMP resides. Segmented RMP support allows the RMP entries to be located on the same node as the memory the RMP is covering, potentially reducing latency associated with accessing an RMP entry associated with the memory. Each RMP segment covers a specific range of system physical addresses.h]hX.Segmented RMP support is a new way of representing the layout of an RMP. Initial RMP support required the RMP table to be contiguous in memory. RMP accesses from a NUMA node on which the RMP doesn’t reside can take longer than accesses from a NUMA node on which the RMP resides. Segmented RMP support allows the RMP entries to be located on the same node as the memory the RMP is covering, potentially reducing latency associated with accessing an RMP entry associated with the memory. Each RMP segment covers a specific range of system physical addresses.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hPSupport for this form of the RMP can be determined using the CPUID instruction::h]hOSupport for this form of the RMP can be determined using the CPUID instruction:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(hD0x8000001f[eax]: Bit[23] indicates support for segmented RMPh]hD0x8000001f[eax]: Bit[23] indicates support for segmented RMP}hjLsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hQIf supported, segmented RMP attributes can be found using the CPUID instruction::h]hPIf supported, segmented RMP attributes can be found using the CPUID instruction:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(hX50x80000025[eax]: Bits[5:0] minimum supported RMP segment size Bits[11:6] maximum supported RMP segment size 0x80000025[ebx]: Bits[9:0] number of cacheable RMP segment definitions Bit[10] indicates if the number of cacheable RMP segments is a hard limith]hX50x80000025[eax]: Bits[5:0] minimum supported RMP segment size Bits[11:6] maximum supported RMP segment size 0x80000025[ebx]: Bits[9:0] number of cacheable RMP segment definitions Bit[10] indicates if the number of cacheable RMP segments is a hard limit}hjhsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(h3To enable a segmented RMP, a new MSR is available::h]h2To enable a segmented RMP, a new MSR is available:}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(h0xc0010136 (RMP_CFG): Bit[0] indicates if segmented RMP is enabled Bits[13:8] contains the size of memory covered by an RMP segment (expressed as a power of 2)h]h0xc0010136 (RMP_CFG): Bit[0] indicates if segmented RMP is enabled Bits[13:8] contains the size of memory covered by an RMP segment (expressed as a power of 2)}hjsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hXThe RMP segment size defined in the RMP_CFG MSR applies to all segments of the RMP. Therefore each RMP segment covers a specific range of system physical addresses. For example, if the RMP_CFG MSR value is 0x2401, then the RMP segment coverage value is 0x24 => 36, meaning the size of memory covered by an RMP segment is 64GB (1 << 36). So the first RMP segment covers physical addresses from 0 to 0xF_FFFF_FFFF, the second RMP segment covers physical addresses from 0x10_0000_0000 to 0x1F_FFFF_FFFF, etc.h]hXThe RMP segment size defined in the RMP_CFG MSR applies to all segments of the RMP. Therefore each RMP segment covers a specific range of system physical addresses. For example, if the RMP_CFG MSR value is 0x2401, then the RMP segment coverage value is 0x24 => 36, meaning the size of memory covered by an RMP segment is 64GB (1 << 36). So the first RMP segment covers physical addresses from 0 to 0xF_FFFF_FFFF, the second RMP segment covers physical addresses from 0x10_0000_0000 to 0x1F_FFFF_FFFF, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX.When a segmented RMP is enabled, RMP_BASE points to the RMP bookkeeping area as it does today (16K in size). However, instead of RMP entries beginning immediately after the bookkeeping area, there is a 4K RMP segment table (RST). Each entry in the RST is 8-bytes in size and represents an RMP segment::h]hX-When a segmented RMP is enabled, RMP_BASE points to the RMP bookkeeping area as it does today (16K in size). However, instead of RMP entries beginning immediately after the bookkeeping area, there is a 4K RMP segment table (RST). Each entry in the RST is 8-bytes in size and represents an RMP segment:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj4)}(hXBits[19:0] mapped size (in GB) The mapped size can be less than the defined segment size. A value of zero, indicates that no RMP exists for the range of system physical addresses associated with this segment. Bits[51:20] segment physical address This address is left shift 20-bits (or just masked when read) to form the physical address of the segment (1MB alignment).h]hXBits[19:0] mapped size (in GB) The mapped size can be less than the defined segment size. A value of zero, indicates that no RMP exists for the range of system physical addresses associated with this segment. Bits[51:20] segment physical address This address is left shift 20-bits (or just masked when read) to form the physical address of the segment (1MB alignment).}hjsbah}(h]h ]h"]h$]h&]hhuh1j3hhhKhjhhubh)}(hThe RST can hold 512 segment entries but can be limited in size to the number of cacheable RMP segments (CPUID 0x80000025_EBX[9:0]) if the number of cacheable RMP segments is a hard limit (CPUID 0x80000025_EBX[10]).h]hThe RST can hold 512 segment entries but can be limited in size to the number of cacheable RMP segments (CPUID 0x80000025_EBX[9:0]) if the number of cacheable RMP segments is a hard limit (CPUID 0x80000025_EBX[10]).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe current Linux support relies on BIOS to allocate/reserve the memory for the segmented RMP (the bookkeeping area, RST, and all segments), build the RST and to set RMP_BASE, RMP_END, and RMP_CFG appropriately. Linux uses the MSR values to locate the RMP and determine the size and location of the RMP segments. The RMP must cover all of system memory in order for Linux to enable SEV-SNP.h]hXThe current Linux support relies on BIOS to allocate/reserve the memory for the segmented RMP (the bookkeeping area, RST, and all segments), build the RST and to set RMP_BASE, RMP_END, and RMP_CFG appropriately. Linux uses the MSR values to locate the RMP and determine the size and location of the RMP segments. The RMP must cover all of system memory in order for Linux to enable SEV-SNP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWMore details in the AMD64 APM Vol 2, section "15.36.3 Reverse Map Table", docID: 24593.h]h[More details in the AMD64 APM Vol 2, section “15.36.3 Reverse Map Table”, docID: 24593.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h] segmented-rmpah ]h"] segmented rmpah$]h&]uh1hhjihhhhhKubeh}(h]reverse-map-table-rmpah ]h"]reverse map table (rmp)ah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSecure VM Service Module (SVSM)h]hSecure VM Service Module (SVSM)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXGSNP provides a feature called Virtual Machine Privilege Levels (VMPL) which defines four privilege levels at which guest software can run. The most privileged level is 0 and numerically higher numbers have lesser privileges. More details in the AMD64 APM Vol 2, section "15.35.7 Virtual Machine Privilege Levels", docID: 24593.h]hXKSNP provides a feature called Virtual Machine Privilege Levels (VMPL) which defines four privilege levels at which guest software can run. The most privileged level is 0 and numerically higher numbers have lesser privileges. More details in the AMD64 APM Vol 2, section “15.35.7 Virtual Machine Privilege Levels”, docID: 24593.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWhen using that feature, different services can run at different protection levels, apart from the guest OS but still within the secure SNP environment. They can provide services to the guest, like a vTPM, for example.h]hWhen using that feature, different services can run at different protection levels, apart from the guest OS but still within the secure SNP environment. They can provide services to the guest, like a vTPM, for example.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hX When a guest is not running at VMPL0, it needs to communicate with the software running at VMPL0 to perform privileged operations or to interact with secure services. An example fur such a privileged operation is PVALIDATE which is *required* to be executed at VMPL0.h](hWhen a guest is not running at VMPL0, it needs to communicate with the software running at VMPL0 to perform privileged operations or to interact with secure services. An example fur such a privileged operation is PVALIDATE which is }(hj#hhhNhNubhemphasis)}(h *required*h]hrequired}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j+hj#ubh to be executed at VMPL0.}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hIn this scenario, the software running at VMPL0 is usually called a Secure VM Service Module (SVSM). Discovery of an SVSM and the API used to communicate with it is documented in "Secure VM Service Module for SEV-SNP Guests", docID: 58019.h]hIn this scenario, the software running at VMPL0 is usually called a Secure VM Service Module (SVSM). Discovery of an SVSM and the API used to communicate with it is documented in “Secure VM Service Module for SEV-SNP Guests”, docID: 58019.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hz(Latest versions of the above-mentioned documents can be found by using a search engine like duckduckgo.com and typing in:h]hz(Latest versions of the above-mentioned documents can be found by using a search engine like duckduckgo.com and typing in:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hIsite:amd.com "Secure VM Service Module for SEV-SNP Guests", docID: 58019 h]h)}(hHsite:amd.com "Secure VM Service Module for SEV-SNP Guests", docID: 58019h]hLsite:amd.com “Secure VM Service Module for SEV-SNP Guests”, docID: 58019}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjaubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubh)}(h for example.)h]h for example.)}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]secure-vm-service-module-svsmah ]h"]secure vm service module (svsm)ah$]h&]uh1hhhhhhhhKubeh}(h]amd-memory-encryptionah ]h"]amd memory encryptionah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjsfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjjfjcjjjjjjjju nametypes}(jjfjjjjuh}(jhjcjjjijjjjjju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.