sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget$/translations/zh_CN/arch/x86/amd-hfimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/zh_TW/arch/x86/amd-hfimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/it_IT/arch/x86/amd-hfimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/ja_JP/arch/x86/amd-hfimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/ko_KR/arch/x86/amd-hfimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget$/translations/sp_SP/arch/x86/amd-hfimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh>/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi.rsthKubhsection)}(hhh](htitle)}(hFHardware Feedback Interface For Hetero Core Scheduling On AMD Platformh]hFHardware Feedback Interface For Hetero Core Scheduling On AMD Platform}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h72025 Advanced Micro Devices, Inc. All Rights Reserved. h]h paragraph)}(h62025 Advanced Micro Devices, Inc. All Rights Reserved.h]h62025 Advanced Micro Devices, Inc. All Rights Reserved.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hAuthorh]hAuthor}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hPerry Yuan h]h)}(hjh](h Perry Yuan <}(hjhhhNhNubh reference)}(hperry.yuan@amd.comh]hperry.yuan@amd.com}(hj#hhhNhNubah}(h]h ]h"]h$]h&]refurimailto:perry.yuan@amd.comuh1j!hjubh>}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(hAuthorh]hAuthor}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhKubh)}(h.Mario Limonciello h]h)}(h-Mario Limonciello h](hMario Limonciello <}(hj^hhhNhNubj")}(hmario.limonciello@amd.comh]hmario.limonciello@amd.com}(hjfhhhNhNubah}(h]h ]h"]h$]h&]refuri mailto:mario.limonciello@amd.comuh1j!hj^ubh>}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hjZubah}(h]h ]h"]h$]h&]uh1hhjIubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubeh}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK ubh)}(hXAMD Heterogeneous Core implementations are comprised of more than one architectural class and CPUs are comprised of cores of various efficiency and power capabilities: performance-oriented *classic cores* and power-efficient *dense cores*. As such, power management strategies must be designed to accommodate the complexities introduced by incorporating different core types. Heterogeneous systems can also extend to more than two architectural classes as well. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time such that the scheduler can direct threads to the optimal core.h](hAMD Heterogeneous Core implementations are comprised of more than one architectural class and CPUs are comprised of cores of various efficiency and power capabilities: performance-oriented }(hjhhhNhNubhemphasis)}(h*classic cores*h]h classic cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and power-efficient }(hjhhhNhNubj)}(h *dense cores*h]h dense cores}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhX. As such, power management strategies must be designed to accommodate the complexities introduced by incorporating different core types. Heterogeneous systems can also extend to more than two architectural classes as well. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time such that the scheduler can direct threads to the optimal core.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXThe goal of AMD's heterogeneous architecture is to attain power benefit by sending background threads to the dense cores while sending high priority threads to the classic cores. From a performance perspective, sending background threads to dense cores can free up power headroom and allow the classic cores to optimally service demanding threads. Furthermore, the area optimized nature of the dense cores allows for an increasing number of physical cores. This improved core density will have positive multithreaded performance impact.h]hXThe goal of AMD’s heterogeneous architecture is to attain power benefit by sending background threads to the dense cores while sending high priority threads to the classic cores. From a performance perspective, sending background threads to dense cores can free up power headroom and allow the classic cores to optimally service demanding threads. Furthermore, the area optimized nature of the dense cores allows for an increasing number of physical cores. This improved core density will have positive multithreaded performance impact.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hAMD Heterogeneous Core Driverh]hAMD Heterogeneous Core Driver}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK#ubh)}(hThe ``amd_hfi`` driver delivers the operating system a performance and energy efficiency capability data for each CPU in the system. The scheduler can use the ranking data from the HFI driver to make task placement decisions.h](hThe }(hjhhhNhNubhliteral)}(h ``amd_hfi``h]hamd_hfi}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh driver delivers the operating system a performance and energy efficiency capability data for each CPU in the system. The scheduler can use the ranking data from the HFI driver to make task placement decisions.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK%hjhhubeh}(h]amd-heterogeneous-core-driverah ]h"]amd heterogeneous core driverah$]h&]uh1hhhhhhhhK#ubh)}(hhh](h)}(h3Thread Classification and Ranking Table Interactionh]h3Thread Classification and Ranking Table Interaction}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhK*ubh)}(hThe thread classification is used to select into a ranking table that describes an efficiency and performance ranking for each classification.h]hThe thread classification is used to select into a ranking table that describes an efficiency and performance ranking for each classification.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hj(hhubh)}(hXThreads are classified during runtime into enumerated classes. The classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. The below table depicts an example of thread classification and a preference where a given thread should be scheduled based on its thread class. The real time thread classification is consumed by the operating system and is used to inform the scheduler of where the thread should be placed.h]hXThreads are classified during runtime into enumerated classes. The classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. The below table depicts an example of thread classification and a preference where a given thread should be scheduled based on its thread class. The real time thread classification is consumed by the operating system and is used to inform the scheduler of where the thread should be placed.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hj(hhubh)}(hhh](h)}(h#Thread Classification Example Tableh]h#Thread Classification Example Table}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhhhK8ubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jphjmubjq)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jphjmubjq)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jphjmubjq)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jphjmubjq)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jphjmubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hclass IDh]hclass ID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hClassificationh]hClassification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPreferred scheduling behaviorh]hPreferred scheduling behavior}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPreemption priorityh]hPreemption priority}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCounterh]hCounter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h0h]h0}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Non-scalableh]h Non-scalable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Efficienth]h Efficient}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hLowesth]hLowest}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMCx1A1h]hPMCx1A1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h I/O boundh]h I/O bound}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hj-ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Efficienth]h Efficient}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjDubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hLowesth]hLowest}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hj[ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPMCx044h]hPMCx044}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjrubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]colsKuh1jkhjhubah}(h]h ]h"]h$]h&]uh1jfhjUhhhhhNubh)}(hThread classification is performed by the hardware each time that the thread is switched out. Threads that don't meet any hardware specified criteria are classified as "default".h]hThread classification is performed by the hardware each time that the thread is switched out. Threads that don’t meet any hardware specified criteria are classified as “default”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjUhhubeh}(h]#thread-classification-example-tableah ]h"]#thread classification example tableah$]h&]uh1hhj(hhhhhK8ubeh}(h]3thread-classification-and-ranking-table-interactionah ]h"]3thread classification and ranking table interactionah$]h&]uh1hhhhhhhhK*ubh)}(hhh](h)}(hAMD Hardware Feedback Interfaceh]hAMD Hardware Feedback Interface}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKGubh)}(hXThe Hardware Feedback Interface provides to the operating system information about the performance and energy efficiency of each CPU in the system. Each capability is given as a unit-less quantity in the range [0-255]. A higher performance value indicates higher performance capability, and a higher efficiency value indicates more efficiency. Energy efficiency and performance are reported in separate capabilities in the shared memory based ranking table.h]hXThe Hardware Feedback Interface provides to the operating system information about the performance and energy efficiency of each CPU in the system. Each capability is given as a unit-less quantity in the range [0-255]. A higher performance value indicates higher performance capability, and a higher efficiency value indicates more efficiency. Energy efficiency and performance are reported in separate capabilities in the shared memory based ranking table.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjhhubh)}(hXlThese capabilities may change at runtime as a result of changes in the operating conditions of the system or the action of external factors. Power Management firmware is responsible for detecting events that require a reordering of the performance and efficiency ranking. Table updates happen relatively infrequently and occur on the time scale of seconds or more.h]hXlThese capabilities may change at runtime as a result of changes in the operating conditions of the system or the action of external factors. Power Management firmware is responsible for detecting events that require a reordering of the performance and efficiency ranking. Table updates happen relatively infrequently and occur on the time scale of seconds or more.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hvThe following events trigger a table update: * Thermal Stress Events * Silent Compute * Extreme Low Battery Scenarios h](hterm)}(h,The following events trigger a table update:h]h,The following events trigger a table update:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKYhjubh definition)}(hhh]h bullet_list)}(hhh](h list_item)}(hThermal Stress Eventsh]h)}(hjh]hThermal Stress Events}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hSilent Computeh]h)}(hj-h]hSilent Compute}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKXhj+ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hExtreme Low Battery Scenarios h]h)}(hExtreme Low Battery Scenariosh]hExtreme Low Battery Scenarios}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjBubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet*uh1j hhhKWhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjhhhNhNubh)}(hXThe kernel or a userspace policy daemon can use these capabilities to modify task placement decisions. For instance, if either the performance or energy capabilities of a given logical processor becomes zero, it is an indication that the hardware recommends to the operating system to not schedule any tasks on that processor for performance or energy efficiency reasons, respectively.h]hXThe kernel or a userspace policy daemon can use these capabilities to modify task placement decisions. For instance, if either the performance or energy capabilities of a given logical processor becomes zero, it is an indication that the hardware recommends to the operating system to not schedule any tasks on that processor for performance or energy efficiency reasons, respectively.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjhhubeh}(h]amd-hardware-feedback-interfaceah ]h"]amd hardware feedback interfaceah$]h&]uh1hhhhhhhhKGubh)}(hhh](h)}(h Implementation details for Linuxh]h Implementation details for Linux}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKbubh)}(hIThe implementation of threads scheduling consists of the following steps:h]hIThe implementation of threads scheduling consists of the following steps:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjhhubhenumerated_list)}(hhh](j)}(hfA thread is spawned and scheduled to the ideal core using the default heterogeneous scheduling policy.h]h)}(hfA thread is spawned and scheduled to the ideal core using the default heterogeneous scheduling policy.h]hfA thread is spawned and scheduled to the ideal core using the default heterogeneous scheduling policy.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hThe processor profiles thread execution and assigns an enumerated classification ID. This classification is communicated to the OS via logical processor scope MSR.h]h)}(hThe processor profiles thread execution and assigns an enumerated classification ID. This classification is communicated to the OS via logical processor scope MSR.h]hThe processor profiles thread execution and assigns an enumerated classification ID. This classification is communicated to the OS via logical processor scope MSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hDuring the thread context switch out the operating system consumes the workload (WL) classification which resides in a logical processor scope MSR.h]h)}(hDuring the thread context switch out the operating system consumes the workload (WL) classification which resides in a logical processor scope MSR.h]hDuring the thread context switch out the operating system consumes the workload (WL) classification which resides in a logical processor scope MSR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hThe OS triggers the hardware to clear its history by writing to an MSR, after consuming the WL classification and before switching in the new thread.h]h)}(hThe OS triggers the hardware to clear its history by writing to an MSR, after consuming the WL classification and before switching in the new thread.h]hThe OS triggers the hardware to clear its history by writing to an MSR, after consuming the WL classification and before switching in the new thread.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hIf due to the classification, ranking table, and processor availability, the thread is not on its ideal processor, the OS will then consider scheduling the thread on its ideal processor (if available). h]h)}(hIf due to the classification, ranking table, and processor availability, the thread is not on its ideal processor, the OS will then consider scheduling the thread on its ideal processor (if available).h]hIf due to the classification, ranking table, and processor availability, the thread is not on its ideal processor, the OS will then consider scheduling the thread on its ideal processor (if available).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKphjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjhhhhhKfubeh}(h] implementation-details-for-linuxah ]h"] implementation details for linuxah$]h&]uh1hhhhhhhhKbubh)}(hhh](h)}(h Ranking Tableh]h Ranking Table}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhKuubh)}(hThe ranking table is a shared memory region that is used to communicate the performance and energy efficiency capabilities of each CPU in the system.h]hThe ranking table is a shared memory region that is used to communicate the performance and energy efficiency capabilities of each CPU in the system.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhj9hhubh)}(hThe ranking table design includes rankings for each APIC ID in the system and rankings both for performance and efficiency for each workload classification.h]hThe ranking table design includes rankings for each APIC ID in the system and rankings both for performance and efficiency for each workload classification.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhj9hhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singleamd_shmem_info (C struct)c.amd_shmem_infohNtauh1jfhj9hhhNhNubhdesc)}(hhh](hdesc_signature)}(hamd_shmem_infoh]hdesc_signature_line)}(hstruct amd_shmem_infoh](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhjhKubh desc_name)}(hamd_shmem_infoh]h desc_sig_name)}(hjh]hamd_shmem_info}(hjhhhNhNubah}(h]h ]nah"]h$]h&]uh1jhjubah}(h]h ](sig-namedescnameeh"]h$]h&]hhuh1jhjhhhjhKubeh}(h]h ]h"]h$]h&]hh add_permalinkuh1jsphinx_line_type declaratorhj~hhhjhKubah}(h]juah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1j|hjhKhjyhhubh desc_content)}(hhh]h)}(hShared memory table for AMD HFIh]hShared memory table for AMD HFI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK,hjhhubah}(h]h ]h"]h$]h&]uh1jhjyhhhjhKubeh}(h]h ](cstructeh"]h$]h&]domainjobjtypejdesctypejnoindex noindexentrynocontentsentryuh1jwhhhj9hNhNubh container)}(hX**Definition**:: struct amd_shmem_info { struct acpi_pcct_ext_pcc_shared_memory header; u32 version_number :8, n_logical_processors :8, n_capabilities :8, table_update_context :8; u32 n_bitmaps :8, reserved :24; u32 table_data[]; }; **Members** ``header`` The PCCT table header including signature, length flags and command. ``version_number`` Version number of the table ``n_logical_processors`` Number of logical processors ``n_capabilities`` Number of ranking dimensions (performance, efficiency, etc) ``table_update_context`` Command being sent over the subspace ``n_bitmaps`` Number of 32-bit bitmaps to enumerate all the APIC IDs This is based on the maximum APIC ID enumerated in the system ``reserved`` 24 bit spare ``table_data`` Bit Map(s) of enabled logical processors Followed by the ranking data for each logical processorh](h)}(h**Definition**::h](hstrong)}(h**Definition**h]h Definition}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK0hjubh literal_block)}(hXstruct amd_shmem_info { struct acpi_pcct_ext_pcc_shared_memory header; u32 version_number :8, n_logical_processors :8, n_capabilities :8, table_update_context :8; u32 n_bitmaps :8, reserved :24; u32 table_data[]; };h]hXstruct amd_shmem_info { struct acpi_pcct_ext_pcc_shared_memory header; u32 version_number :8, n_logical_processors :8, n_capabilities :8, table_update_context :8; u32 n_bitmaps :8, reserved :24; u32 table_data[]; };}hj,sbah}(h]h ]h"]h$]h&]hhuh1j*hd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK2hjubh)}(h **Members**h]j)}(hj=h]hMembers}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK9hjubj)}(hhh](j)}(hP``header`` The PCCT table header including signature, length flags and command. h](j)}(h ``header``h]j)}(hj\h]hheader}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK/hjVubj )}(hhh]h)}(hDThe PCCT table header including signature, length flags and command.h]hDThe PCCT table header including signature, length flags and command.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjqhK/hjrubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jhjqhK/hjSubj)}(h/``version_number`` Version number of the table h](j)}(h``version_number``h]j)}(hjh]hversion_number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK0hjubj )}(hhh]h)}(hVersion number of the tableh]hVersion number of the table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK0hjSubj)}(h6``n_logical_processors`` Number of logical processors h](j)}(h``n_logical_processors``h]j)}(hjh]hn_logical_processors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK1hjubj )}(hhh]h)}(hNumber of logical processorsh]hNumber of logical processors}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK1hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK1hjSubj)}(hO``n_capabilities`` Number of ranking dimensions (performance, efficiency, etc) h](j)}(h``n_capabilities``h]j)}(hjh]hn_capabilities}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK2hjubj )}(hhh]h)}(h;Number of ranking dimensions (performance, efficiency, etc)h]h;Number of ranking dimensions (performance, efficiency, etc)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK2hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK2hjSubj)}(h>``table_update_context`` Command being sent over the subspace h](j)}(h``table_update_context``h]j)}(hj@h]htable_update_context}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK3hj:ubj )}(hhh]h)}(h$Command being sent over the subspaceh]h$Command being sent over the subspace}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhK3hjVubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjUhK3hjSubj)}(h``n_bitmaps`` Number of 32-bit bitmaps to enumerate all the APIC IDs This is based on the maximum APIC ID enumerated in the system h](j)}(h ``n_bitmaps``h]j)}(hjyh]h n_bitmaps}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjwubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK5hjsubj )}(hhh]h)}(htNumber of 32-bit bitmaps to enumerate all the APIC IDs This is based on the maximum APIC ID enumerated in the systemh]htNumber of 32-bit bitmaps to enumerate all the APIC IDs This is based on the maximum APIC ID enumerated in the system}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK4hjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jhjhK5hjSubj)}(h``reserved`` 24 bit spare h](j)}(h ``reserved``h]j)}(hjh]hreserved}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK6hjubj )}(hhh]h)}(h 24 bit spareh]h 24 bit spare}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhK6hjSubj)}(ho``table_data`` Bit Map(s) of enabled logical processors Followed by the ranking data for each logical processorh](j)}(h``table_data``h]j)}(hjh]h table_data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhd/var/lib/git/docbuild/linux/Documentation/arch/x86/amd-hfi:124: ./drivers/platform/x86/amd/hfi/hfi.chK7hjubj )}(hhh]h)}(h`Bit Map(s) of enabled logical processors Followed by the ranking data for each logical processorh]h`Bit Map(s) of enabled logical processors Followed by the ranking data for each logical processor}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hK7hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj hK7hjSubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ] kernelindentah"]h$]h&]uh1jhj9hhhNhNubeh}(h] ranking-tableah ]h"] ranking tableah$]h&]uh1hhhhhhhhKuubh)}(hhh](h)}(hRanking Table updateh]hRanking Table update}(hj7 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4 hhhhhKubh)}(hX\The power management firmware issues an platform interrupt after updating the ranking table and is ready for the operating system to consume it. CPUs receive such interrupt and read new ranking table from shared memory which PCCT table has provided, then ``amd_hfi`` driver parses the new table to provide new consume data for scheduling decisions.h](hThe power management firmware issues an platform interrupt after updating the ranking table and is ready for the operating system to consume it. CPUs receive such interrupt and read new ranking table from shared memory which PCCT table has provided, then }(hjE hhhNhNubj)}(h ``amd_hfi``h]hamd_hfi}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjE ubhR driver parses the new table to provide new consume data for scheduling decisions.}(hjE hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj4 hhubeh}(h]ranking-table-updateah ]h"]ranking table updateah$]h&]uh1hhhhhhhhKubeh}(h]Fhardware-feedback-interface-for-hetero-core-scheduling-on-amd-platformah ]h"]Fhardware feedback interface for hetero core scheduling on amd platformah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jr jo jjj%j"jjjjjjj6j3j1 j. jj jg u nametypes}(jr jj%jjjj6j1 jj uh}(jo hjjj"jjj(jjUjjj3jj. j9juj~jg j4 u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.